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Code Activity
yosys/passes/proc
History
Marcelina Kościelnicka 009940f56c rtlil: Make Process handling more uniform with Cell and Wire. 
- add a backlink to module from Process
- make constructor and destructor protected, expose Module functions
  to add and remove processes
2021-07-12 00:47:34 +02:00
..
Makefile.inc Add support for memory writes in processes. 2021-03-08 20:16:29 +01:00
proc.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
proc_arst.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
proc_clean.cc rtlil: Make Process handling more uniform with Cell and Wire. 2021-07-12 00:47:34 +02:00
proc_dff.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
proc_dlatch.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
proc_init.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
proc_memwr.cc Add support for memory writes in processes. 2021-03-08 20:16:29 +01:00
proc_mux.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
proc_prune.cc Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
proc_rmdead.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00