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Code Activity
yosys/passes
History
Marcelina Kościelnicka 009940f56c rtlil: Make Process handling more uniform with Cell and Wire. 
- add a backlink to module from Process
- make constructor and destructor protected, expose Module functions
  to add and remove processes
2021-07-12 00:47:34 +02:00
..
cmds rtlil: Make Process handling more uniform with Cell and Wire. 2021-07-12 00:47:34 +02:00
equiv Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
fsm Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
hierarchy Move interface expansion in hierarchy.cc into a helper class 2021-06-16 21:48:18 -04:00
memory Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
opt opt_muxtree: Update port_off and port_idx even for constant bits 2021-06-11 12:06:35 +01:00
pmgen Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
proc rtlil: Make Process handling more uniform with Cell and Wire. 2021-07-12 00:47:34 +02:00
sat Use HTTPS for website links, gatecat email 2021-06-09 12:16:56 +02:00
techmap Fix deadname SVN links 2021-06-09 12:44:37 +02:00
tests Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00