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32 lines
641 B
Text
32 lines
641 B
Text
# warn
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read_verilog <<EOT
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module top(input g, rn, d, output reg q);
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always @* if (~rn) q <= 0; else if (g) q <= d;
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endmodule
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EOT
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logger -expect warning "Latch inferred for signal" 1
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proc
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logger -check-expected
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design -reset
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# info
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read_verilog <<EOT
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module top(input g, rn, d, output reg q);
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always @* if (~rn) q <= 0; else if (g) q <= d;
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endmodule
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EOT
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logger -expect-no-warnings
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proc -latches info
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logger -check-expected
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design -reset
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# error
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read_verilog <<EOT
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module top(input g, rn, d, output reg q);
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always @* if (~rn) q <= 0; else if (g) q <= d;
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endmodule
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EOT
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logger -expect error "Latch inferred for signal" 1
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proc -latches error
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