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59 lines
1.4 KiB
Verilog
59 lines
1.4 KiB
Verilog
module top (
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input wire clk,
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input wire rst,
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input wire [7:0] a,
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input wire [7:0] b,
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input wire [3:0] c,
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input wire en,
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output wire [7:0] out1,
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output wire [7:0] out2
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);
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// Shared intermediate signal
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wire [7:0] ab_sum;
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assign ab_sum = a + b;
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// Logic cone for out1
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wire [7:0] cone1_1, cone1_2;
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assign cone1_1 = ab_sum ^ {4{c[1:0]}};
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assign cone1_2 = (a & b) | {4{c[3:2]}};
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reg [7:0] reg1, reg2; // only reg1 feeds into out1, but both share a source location
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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reg1 <= 8'h00;
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reg2 <= 8'hFF;
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end else if (en) begin
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reg1 <= cone1_1 + cone1_2;
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reg2 <= cone1_2 - cone1_1;
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end
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end
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wire [7:0] cone1_3;
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assign cone1_3 = reg1 & ~a[0];
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// Logic cone for out2
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wire [7:0] cone2_1, cone2_2;
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assign cone2_1 = (ab_sum << 1) | (a >> 2);
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assign cone2_2 = (b ^ {4{c[2:0]}}) & 8'hAA;
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reg [7:0] reg3;
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always @(posedge clk or posedge rst) begin
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if (rst)
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reg3 <= 8'h0F;
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else
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reg3 <= cone2_1 ^ cone2_2 ^ reg1[7:0];
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end
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wire [7:0] cone2_3;
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assign cone2_3 = reg3 | (reg2 ^ 8'h55);
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// Outputs
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assign out1 = cone1_3 | (reg1 ^ 8'hA5);
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assign out2 = cone2_3 & (reg3 | 8'h5A);
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always @(posedge clk) begin
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assert (out1 == 8'h42);
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end
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endmodule
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