mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-22 08:35:32 +00:00
8 lines
92 B
Text
8 lines
92 B
Text
read_verilog <<EOF
|
|
module top;
|
|
wire a;
|
|
wire b;
|
|
assign a = b;
|
|
endmodule
|
|
EOF
|
|
delete w:a
|