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yosys/tests/verilog/unique_if_else_begin.ys
Gary Wong 9770ece187 Accept (and ignore) SystemVerilog unique/priority if.
Add support to the "read_verilog -sv" parser to validate the
"unique", "unique0", and "priority" keywords in contexts where
they're legal according to 1800-2012 12.4.2.

This affects only the grammar accepted; the behaviour of conditionals
is not changed.  (But accepting this syntax will provide scope for
possible optimisations as future work.)

Three test cases ("unique_if", "unique_if_else", and
"unique_if_else_begin") verify that the keywords are accepted where
legal and rejected where illegal, as described in the final paragraph
of 12.4.2.
2025-05-22 19:28:28 -06:00

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read_verilog -sv <<EOF
module top( input[2:0] a );
always_comb begin
// example from 1800-2012 12.4.2
unique if ((a==0) || (a==1)) $display("0 or 1");
else begin
unique if (a == 2) $display("2");
else if (a == 4) $display("4");
end
end
endmodule
EOF