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15 lines
194 B
Text
15 lines
194 B
Text
read_rtlil << EOT
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module \top
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wire \sig
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wire \val
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process $2
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attribute \full_case 1
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switch \sig
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end
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end
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end
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EOT
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write_verilog bug5572.v
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design -reset
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read_verilog bug5572.v
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