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yosys/techlibs/xilinx
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George Haworth aba5b279c6 Fix RAMB36E1/E2 SDP parity port mapping typo 
DIPBDIP/DINPBDINP condition checked PORT_W_WIDTH == 71, which never
matches any valid SDP width. Should be 72, matching the DIBDI/DINBDIN
condition on the line above. This caused data bits 68-69 to be
silently overwritten with copies of bits 64-65 on every write.

Affects both xc6v (RAMB36E1, Artix-7/Kintex-7/Virtex-7) and xcu
(RAMB36E2, UltraScale/UltraScale+) mapping templates. The RAMB18E1/E2
equivalents correctly use == 36.
2026-04-18 19:10:18 +03:00
..
tests Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
abc9_model.v Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
arith_map.v Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
brams_defs.vh xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
brams_xc2v.txt xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
brams_xc2v_map.v xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
brams_xc3sda.txt xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
brams_xc3sda_map.v xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
brams_xc4v.txt xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
brams_xc4v_map.v xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
brams_xc5v_map.v xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
brams_xc6v_map.v Fix RAMB36E1/E2 SDP parity port mapping typo 2026-04-18 19:10:18 +03:00
brams_xcu_map.v Fix RAMB36E1/E2 SDP parity port mapping typo 2026-04-18 19:10:18 +03:00
brams_xcv.txt xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
brams_xcv_map.v xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
cells_map.v Clearer diff for the all-x corner case 2025-04-07 07:55:30 +02:00
cells_sim.v Update Xilinx cell definitions, fixes #3699 2023-03-23 09:44:36 +01:00
cells_xtra.py Update Xilinx cell definitions, fixes #3699 2023-03-23 09:44:36 +01:00
cells_xtra.v Add and use fix_mod.py 2026-01-28 07:45:58 +13:00
ff_map.v Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
lut_map.v Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
lutrams_xc5v.txt xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
lutrams_xc5v_map.v xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
lutrams_xcu.txt xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
lutrams_xcv.txt xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
lutrams_xcv_map.v xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Makefile.inc pmgen: Move passes out of pmgen folder 2025-01-31 15:18:28 +13:00
mux_map.v Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
synth_xilinx.cc Move Design::sort() calls out of opt and opt_clean passes into the synth passes that need them. 2026-01-23 01:14:35 +00:00
urams.txt URAM mapping : Add test for 2048 x 144b 2025-05-10 14:53:56 +02:00
urams_map.v URAM mapping : Fix port indexes according to Yosys warnings 2025-05-09 15:09:11 +02:00
xc3s_mult_map.v xilinx: Support multiplier mapping for all families. 2019-10-22 18:06:57 +02:00
xc3sda_dsp_map.v xilinx_dsp: Initial DSP48A/DSP48A1 support. 2019-12-22 20:51:14 +01:00
xc4v_dsp_map.v xilinx: Support multiplier mapping for all families. 2019-10-22 18:06:57 +02:00
xc5v_dsp_map.v xilinx: Support multiplier mapping for all families. 2019-10-22 18:06:57 +02:00
xc6s_dsp_map.v xilinx_dsp: Initial DSP48A/DSP48A1 support. 2019-12-22 20:51:14 +01:00
xc7_dsp_map.v xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325) 2020-09-23 09:15:24 -07:00
xcu_dsp_map.v xilinx: Support multiplier mapping for all families. 2019-10-22 18:06:57 +02:00
xilinx_dffopt.cc Update techlibs to avoid bits() 2025-09-16 03:17:23 +00:00
xilinx_dsp.cc Add support for subtraction in preadder 2026-02-03 08:31:01 -08:00
xilinx_dsp.pmg Add support for subtraction in preadder 2026-02-03 08:31:01 -08:00
xilinx_dsp48a.pmg pmgen: Move passes out of pmgen folder 2025-01-31 15:18:28 +13:00
xilinx_dsp_cascade.pmg xilinx: fix IdString memory leak 2025-11-13 14:10:52 +01:00
xilinx_dsp_CREG.pmg pmgen: Move passes out of pmgen folder 2025-01-31 15:18:28 +13:00
xilinx_srl.cc Update techlibs to avoid bits() 2025-09-16 03:17:23 +00:00
xilinx_srl.pmg pmgen: Move passes out of pmgen folder 2025-01-31 15:18:28 +13:00