mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-30 19:22:31 +00:00
2a3720921c
For these primitives, Gowin decided to use a different option for describing ports—directly in the module header, i.e. ``` verilog module ADC(input CLK); ``` instead of ``` verilog module ADC(CLK); input CLK; ``` Since this one-time parser becomes too confusing, it is easier to simply add ADC descriptions as they are from a separate file, especially since these primitives are only available in the GW5A series. Test: ``` shell yosys -p "read_verilog top.v; synth_gowin -json top-synth.json -family gw5a" ``` The old version of Yosys simply won't compile the design due to the lack of port descriptions, while the new version will compile without errors. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> |
||
|---|---|---|
| .. | ||
| adc.v | ||
| arith_map.v | ||
| brams.txt | ||
| brams_map.v | ||
| brams_map_gw5a.v | ||
| cells_map.v | ||
| cells_sim.v | ||
| cells_xtra.py | ||
| cells_xtra_gw1n.v | ||
| cells_xtra_gw2a.v | ||
| cells_xtra_gw5a.v | ||
| lutrams.txt | ||
| lutrams_map.v | ||
| Makefile.inc | ||
| synth_gowin.cc | ||