mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-07 18:05:24 +00:00
Code Activity
14948 commits 94 branches 52 tags 62 MiB
Commit graph

106 commits

Author SHA1 Message Date
YRabbit c37db637c7 Gowin. Remove unnecessary modules 
Primitives that are not planned for implementation for reasons of
belonging to old unsupported chips or representing composite complex IPs
rather than primitives are removed.
Also latches and large MUXes not planned for implementation.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-03-28 06:34:26 +10:00
Aritz Erkiaga 9a11204329 Update ALU MULT mode in gowin to match nextpnr 2024-12-23 11:12:48 +01:00
Pepijn de Vos be836f4af3 gowin: split cells_xtra by family 2024-11-26 15:42:22 +01:00
Pepijn de Vos b8329df1d0 add GW2A and GW5A cells 2024-11-17 20:25:11 +01:00
YRabbit ab35dff702 Gowin. Add the EMCU primitive. 
EMCU is a micro-processor based on ARM Cortex-M3 embedded in the
GW1NSR-4C chip used in the Tangnano4k board.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-09-11 10:18:51 +10:00
David Lanzendörfer d1b767ea8b Adding missing to Gowin tech files 
Without OSER4_MEM, IDES4_MEM and DQS the synthesis of my Rocket Chip
design for my Sipeed Tang FPGA fails.
 2024-08-18 19:38:31 +01:00
Emil J 43c1328fbb
Merge pull request #4479 from yrabbit/z1-power 
Gowin. Add an energy saving primitive
 2024-07-18 11:56:00 +02:00
YRabbit 19bbdd8800 Gowin. Add the DCS primitive 
Not so much adding the primitive itself, but only its DCS_MODE
parameter, without which an error occurs.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-07-11 21:39:44 +10:00
YRabbit 9d0bca9775 Gowin. Add an energy saving primitive 
We add a BANDGAP primitive used to turn off power to OSC, PLL and other
things on some GOWIN chips.

We also mark this primitive and GSR as keep.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-07-06 18:58:21 +10:00
Krystine Sherwin ff10aeebd6
Fix some synth_* help messages 
Mostly memory_libmap arg checks; puts the checks into an else block on the `if (help_mode)` check to avoid cases like `synth_ice40` listing `-no-auto-huge [-no-auto-huge]`.
Also fix `map_iopad` section being empty in `synth_fabulous`.
 2024-03-18 11:33:18 +13:00
YRabbit 79c5a06673 gowin: Fix SDP write enable port. 
This primitive does not have a separate WRE port, so we regulate writing
using Clock Enable.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-01-30 17:06:59 +10:00
YRabbit a5fdf3f881 gowin: Change BYTE ENABLE handling. 
When inferring we allow writing to all bytes for now.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-01-27 17:19:49 +10:00
YRabbit ae991abf2e gowin: fix the BRAM mapping. 
The primitives used have been corrected and changes have been made to the set of signals.
The empirically established need to set the OCEx signal to 1 when using READ_MODE=0 is reflected.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-01-19 15:26:37 +10:00
Pepijn de Vos f19c6b4415
Enable bram for Gowin 2023-12-03 10:17:28 +01:00
Lofty 309558767d gowin: fix typo 2023-11-14 22:37:29 +00:00
Lofty 7ae4041e20 ice40, ecp5, gowin: enable ABC9 by default 2023-11-13 15:28:13 +00:00
Lofty 294844137b gowin: fix abc9 attributes and specify blocks 2023-10-04 00:16:10 +01:00
Miodrag Milanović 7aab324e85
Merge pull request #3737 from yrabbit/all-primitives-script 
gowin: Add all the primitives.
 2023-05-09 11:13:51 +02:00
Ralf Fuest 30f1d10948 gowin: Fix X output of $alu techmap 2023-05-01 17:56:41 +02:00
YRabbit a1dd794ff8 gowin: Add all the primitives. 
Use selected data (names, ports and parameters) from vendor file for
GW1N series primitives.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-04-22 17:10:53 +10:00
YRabbit f9a6c0fcbd gowin: Add serialization/deserialization primitives 
Primitives are added to convert parallel signals to serial and vice versa.

IDES4, IDES8, IDES10, IDES16, IVIDEO, OSER4, OSER8, OSER10, OSER16, OVIDEO.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-04-12 09:59:57 +01:00
Miodrag Milanović bb28e48136
Merge pull request #3663 from uis246/master 
gowin: Add new types of oscillator
 2023-02-28 06:56:01 +01:00
uis ea6f562d49 gowin: Add new types of oscillator 2023-02-06 21:34:32 +00:00
martell dbc8b77222 gowin: Add support for emulated differential output 2023-01-29 20:48:43 -08:00
YRabbit d6a1e022e1 gowin: add a new type of PLL - PLLVR 
This primitive is used in the GW1NS-4, GW1NS-4C, GW1NSR-4, GW1NSR-4C and
GW1NSER-4C chips.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-01-11 11:41:29 +10:00
Pepijn de Vos de07eb11c1
Apicula now supports lutram 2022-07-03 12:45:03 +02:00
Marcelina Kościelnicka 71dfbf33b2 Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}. 2022-06-02 23:16:12 +02:00
Marcelina Kościelnicka e4d811561c gowin: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Tim Pambor 30bc0d26ea gowin: Add oscillator primitives 2022-03-28 13:33:24 +02:00
YRabbit 19b7633aca gowin: add support for Double Data Rate primitives 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-03-14 23:14:21 +01:00
YRabbit 22d9bbb308 gowin: Remove unnecessary attributes 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-02-24 05:38:33 +01:00
YRabbit 9b3cd4f0d8 gowin: Add support for true differential output 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-02-24 05:38:33 +01:00
Marcelina Kościelnicka 3a62fa0c97 gowin: Add remaining block RAM blackboxes. 2022-02-12 11:48:57 +01:00
Marcelina Kościelnicka f61f2a4078 gowin: Fix LUT RAM inference, add more models. 2022-02-09 09:04:34 +01:00
Marcelina Kościelnicka 15b0d717ed iopadmap: Add native support for negative-polarity output enable. 2021-11-09 15:40:16 +01:00
Pepijn de Vos 4bf8deacbb
synth_gowin: move splitnets to after iopadmap (#2435) 2021-11-07 18:00:18 +01:00
Pepijn de Vos a3eec687e0 Remove noalu from synth_gowin json output as Apicula now supports it 2021-11-07 03:04:21 +01:00
Pepijn de Vos 0c7461fe5e
gowin: widelut support (#3042) 2021-11-06 16:09:30 +01:00
Pepijn de Vos c2d358484f
Gowin: deal with active-low tristate (#2971) 
* deal with active-low tristate

* remove empty port

* update sim models

* add expected lut1 to tests
 2021-08-20 21:21:06 +02:00
Claire Xenia Wolf 0ada13cbe2 Use HTTPS for website links, gatecat email 
git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed

s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;
 2021-06-09 12:16:56 +02:00
Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames 
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
 2021-06-08 00:39:36 +02:00
gatecat cae905f551 Blackbox all whiteboxes after synthesis 
This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-17 21:07:20 +00:00
Pepijn de Vos f155826a70 add -noalu and -json option for apicula 2020-11-30 11:43:12 +01:00
Konrad Beckmann 5b9a975eba synth_gowin: Add rPLL blackbox 2020-11-11 17:06:54 +01:00
Marcelina Kościelnicka 9a4f420b4b Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
Marcelina Kościelnicka c73ebeb90e gowin: Use dfflegalize. 2020-07-06 12:27:46 +02:00
Dan Ravensloft 7f45cab27a synth_gowin: ABC9 support 
This adds ABC9 support for synth_gowin; drastically improving
synthesis quality.
 2020-07-05 22:07:17 +02:00
Marcelina Kościelnicka 90b89e5ebc
Merge pull request #2232 from YosysHQ/mwk/gowin-sim-init 
gowin: Fix INIT values in sim library.
 2020-07-05 12:02:31 +02:00
Marcelina Kościelnicka 9beed4d771 gowin: Fix INIT values in sim library. 2020-07-05 03:03:48 +02:00
Dan Ravensloft 01772dec8c gowin: replace determine_init with setundef 2020-07-04 23:26:56 +02:00