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yosys/passes
Krystine Sherwin a7c8651b76
Add check_mem command
Comes with a set of tests which (currently) pass with `read_verilog` but fail with `verific` based on #5878.
Add `--check-sv`, an alternative to `--prove-sv` with generator defined yosys commands.  Helpful for when you want to run the same set of commands on a bunch of sv files.
2026-05-20 15:02:30 +12:00
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cmds Add check_mem command 2026-05-20 15:02:30 +12:00
equiv remove unused hashlib containers 2026-05-12 12:52:10 +02:00
fsm fsm_detect: add adff detection 2025-11-06 23:29:47 +02:00
hierarchy hierarchy.cc: Tidying 2025-10-15 09:42:47 +13:00
memory memlib: fix documentation for PORT_<name>_CLK_POL 2026-05-09 10:28:07 +02:00
opt remove unused hashlib containers 2026-05-12 12:52:10 +02:00
pmgen Fix typo in pmgen/README.md 2026-04-02 10:24:31 -05:00
proc proc_clean: Removing an empty full_case is doing something 2026-01-07 13:10:32 +13:00
sat remove unused hashlib containers 2026-05-12 12:52:10 +02:00
techmap remove unused hashlib containers 2026-05-12 12:52:10 +02:00
tests test_cell.cc: Generate .aag for all compatible cells 2025-12-02 14:03:36 +13:00