mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-30 11:12:29 +00:00
28 lines
497 B
Text
28 lines
497 B
Text
# SV LRM A2.2.1
|
|
|
|
read_verilog -sv <<EOT
|
|
module test_signed();
|
|
parameter integer signed a = 0;
|
|
parameter integer unsigned b = 0;
|
|
|
|
endmodule
|
|
EOT
|
|
|
|
design -reset
|
|
read_verilog -sv <<EOT
|
|
module test_signed();
|
|
parameter logic signed [7:0] a = 0;
|
|
parameter logic unsigned [7:0] b = 0;
|
|
|
|
endmodule
|
|
EOT
|
|
|
|
design -reset
|
|
logger -expect error "syntax error, unexpected TOK_INTEGER" 1
|
|
read_verilog -sv <<EOT
|
|
module test_signed();
|
|
parameter signed integer a = 0;
|
|
parameter unsigned integer b = 0;
|
|
|
|
endmodule
|
|
EOT
|