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Code Activity
yosys/techlibs/quicklogic/qlf_k6n10f
History
Exact
N. Engelhardt 64609afe2c add example memory test
2023-11-30 19:35:43 +01:00
..
arith_map.v change ql-bram-types pass to use mode parameter; clean up primitive libraries 2023-11-27 12:05:52 +01:00
bram_types_sim.v change ql-bram-types pass to use mode parameter; clean up primitive libraries 2023-11-27 12:05:52 +01:00
brams_map.v merge brams_final_map.v into brams_map.v 2023-11-27 12:05:55 +01:00
brams_sim.v fixup! quicklogic: Add missing RAM_INIT param on TDP36K sim model 2023-11-30 10:18:48 +01:00
cells_sim.v quicklogic: Drop blackbox off adder_carry 2023-11-27 14:21:59 +01:00
dsp_final_map.v add dsp inference 2023-11-27 12:05:53 +01:00
dsp_map.v ql_k6n10f: Remove support for parameter-configured DSP variety 2023-11-27 12:05:55 +01:00
dsp_sim.v ql_k6n10f: Remove support for parameter-configured DSP variety 2023-11-27 12:05:55 +01:00
ffs_map.v change ql-bram-types pass to use mode parameter; clean up primitive libraries 2023-11-27 12:05:52 +01:00
generate_bram_types_sim.py quicklogic: Add RAM_INIT to specialized BRAM models 2023-11-30 10:41:55 +01:00
libmap_brams.txt add qlf_k6n10f architecture + bram inference 2023-11-27 12:05:45 +01:00
libmap_brams_map.v fixup! add qlf_k6n10f architecture + bram inference 2023-11-27 18:28:10 +01:00
sram1024x18_mem.v add example memory test 2023-11-30 19:35:43 +01:00
TDP18K_FIFO.v add example memory test 2023-11-30 19:35:43 +01:00
ufifo_ctl.v add example memory test 2023-11-30 19:35:43 +01:00