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https://github.com/YosysHQ/yosys
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117 lines
2.1 KiB
Text
117 lines
2.1 KiB
Text
module inv (A, Y);
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input A;
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output Y;
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assign Y = ~A; // "A'"
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endmodule
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module tri_inv (A, S, Z);
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input A;
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input S;
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output Z;
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assign Z = ~A; // "A'"
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endmodule
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module buffer (A, Y);
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input A;
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output Y;
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assign Y = A; // "A"
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endmodule
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module nand2 (A, B, Y);
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input A;
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input B;
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output Y;
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assign Y = ~(A&B); // "(A * B)'"
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endmodule
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module nor2 (A, B, Y);
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input A;
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input B;
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output Y;
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assign Y = ~(A|B); // "(A + B)'"
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endmodule
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module xor2 (A, B, Y);
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input A;
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input B;
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output Y;
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assign Y = (A&~B)|(~A&B); // "(A *B') + (A' * B)"
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endmodule
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module imux2 (A, B, S, Y);
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input A;
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input B;
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input S;
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output Y;
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assign Y = ~(&(A&S)|(B&~S)&); // "( (A * S) + (B * S') )'"
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endmodule
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module dff (D, CLK, RESET, PRESET, Q, QN);
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reg "IQ", "IQN";
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input D;
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input CLK;
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input RESET;
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input PRESET;
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output Q;
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assign Q = IQ; // "IQ"
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output QN;
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assign QN = IQN; // "IQN"
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always @(posedge CLK, posedge RESET, posedge PRESET) begin
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if ((RESET) && (PRESET)) begin
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"IQ" <= 0;
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"IQN" <= 0;
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end
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else if (RESET) begin
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"IQ" <= 0;
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"IQN" <= 1;
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end
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else if (PRESET) begin
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"IQ" <= 1;
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"IQN" <= 0;
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end
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else begin
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// "D"
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"IQ" <= D;
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"IQN" <= ~(D);
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end
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end
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endmodule
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module latch (D, G, Q, QN);
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reg "IQ", "IQN";
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input D;
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input G;
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output Q;
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assign Q = IQ; // "IQ"
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output QN;
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assign QN = IQN; // "IQN"
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always @* begin
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if (G) begin
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"IQ" <= D;
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"IQN" <= ~(D);
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end
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end
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endmodule
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module aoi211 (A, B, C, Y);
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input A;
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input B;
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input C;
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output Y;
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assign Y = ~((A&B)|C); // "((A * B) + C)'"
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endmodule
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module oai211 (A, B, C, Y);
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input A;
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input B;
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input C;
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output Y;
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assign Y = ~((A|B)&C); // "((A + B) * C)'"
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endmodule
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module halfadder (A, B, C, Y);
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input A;
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input B;
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output C;
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assign C = (A&B); // "(A * B)"
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output Y;
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assign Y = (A&~B)|(~A&B); // "(A *B') + (A' * B)"
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endmodule
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module fulladder (A, B, CI, CO, Y);
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input A;
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input B;
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input CI;
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output CO;
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assign CO = (((A&B)|(B&CI))|(CI&A)); // "(((A * B)+(B * CI))+(CI * A))"
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output Y;
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assign Y = ((A^B)^CI); // "((A^B)^CI)"
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endmodule
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