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yosys/passes
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Emil J 5c630a366d
Merge pull request #5555 from rocallahan/defer-redirects 
Defer redirecting cell outputs when merging cells in `opt_merge` untill after we've done a full pass over the cells.
2026-01-06 18:48:16 +01:00
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cmds Merge pull request #5571 from YosysHQ/micko/warning 2025-12-23 16:32:10 +01:00
equiv Merge pull request #5357 from rocallahan/builtin-ff 2025-09-17 11:37:16 +02:00
fsm fsm_detect: add adff detection 2025-11-06 23:29:47 +02:00
hierarchy hierarchy.cc: Tidying 2025-10-15 09:42:47 +13:00
memory Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
opt Merge pull request #5555 from rocallahan/defer-redirects 2026-01-06 18:48:16 +01:00
pmgen Remove .c_str() from log_cmd_error() and log_file_error() parameters 2025-09-16 22:59:08 +00:00
proc Update passes/proc to avoid bits() 2025-09-16 03:17:23 +00:00
sat Revert sim's cycle_width default back to 10, but keep -width option 2025-10-20 14:40:05 +02:00
techmap Merge pull request #5568 from rocallahan/abc-spawn-errno 2025-12-23 08:09:14 +01:00
tests test_cell.cc: Generate .aag for all compatible cells 2025-12-02 14:03:36 +13:00