mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
14 lines
349 B
Text
14 lines
349 B
Text
# Check that opt_reduce doesn't produce zero width $reduce_or/$reduce_and,
|
|
|
|
read_verilog <<EOT
|
|
module reduce_const(output wire o, output wire a);
|
|
wire [3:0] zero = 4'b0000;
|
|
wire [3:0] ones = 4'b1111;
|
|
assign o = |zero;
|
|
assign a = &ones;
|
|
endmodule
|
|
EOT
|
|
|
|
equiv_opt -assert opt_reduce
|
|
design -load postopt
|
|
select -assert-none r:A_WIDTH=0
|