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yosys/passes
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Emil J. Tywoniak 775b8f2f4c proc_mux, genrtlil: make use of case_src for better case condition vs block tracking
2025-12-11 00:45:30 +01:00
..
cmds rtlil: replace SigSig actions with new type SyncAction 2025-12-10 18:32:39 +01:00
equiv Merge pull request #5357 from rocallahan/builtin-ff 2025-09-17 11:37:16 +02:00
fsm fsm_detect: add adff detection 2025-11-06 23:29:47 +02:00
hierarchy hierarchy.cc: Tidying 2025-10-15 09:42:47 +13:00
memory Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
opt Remove cover() coverage tracking 2025-12-04 16:27:13 +01:00
pmgen Remove .c_str() from log_cmd_error() and log_file_error() parameters 2025-09-16 22:59:08 +00:00
proc proc_mux, genrtlil: make use of case_src for better case condition vs block tracking 2025-12-11 00:45:30 +01:00
sat Revert sim's cycle_width default back to 10, but keep -width option 2025-10-20 14:40:05 +02:00
techmap rtlil: replace SigSig actions with new type SyncAction 2025-12-10 18:32:39 +01:00
tests Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00