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Mono Color

• 325b764341 Added eval -set-undef and eval -table Clifford Wolf 2013-12-07 11:58:22 +0100
• 5d83904746 Fixes and improvements in RTLIL::SigSpec::parse Clifford Wolf 2013-12-07 11:57:29 +0100
• 06d96e8fcf Fixes in fsm detect/extract for better detection of non-fsm circuits Clifford Wolf 2013-12-06 12:53:20 +0100
• 8311492475 Fixed bug in example prog in appnote 011 Clifford Wolf 2013-12-05 18:15:14 +0100
• 891e4b5b0d Keep strings as strings in const ternary and concat Clifford Wolf 2013-12-05 13:26:17 +0100
• e935bb6eda Added const folding support for $signed and $unsigned Clifford Wolf 2013-12-05 13:09:41 +0100
• 5c39948ead Added AstNode::mkconst_str API Clifford Wolf 2013-12-05 12:53:49 +0100
• 853538d78b Fixed generate-for (and disabled double warning for auto-wire) Clifford Wolf 2013-12-04 21:33:00 +0100
• 3c220e0b32 Added support for $clog2 system function Clifford Wolf 2013-12-04 21:19:54 +0100
• 4a4a3fc337 Various improvements in support for generate statements Clifford Wolf 2013-12-04 21:06:54 +0100
• f4b46ed31e Replaced signed_parameters API with CONST_FLAG_SIGNED Clifford Wolf 2013-12-04 14:24:44 +0100
• 93a70959f3 Replaced RTLIL::Const::str with generic decoder method Clifford Wolf 2013-12-04 14:14:05 +0100
• a2d053694b Fix in sincos testbench gen Clifford Wolf 2013-12-04 09:24:52 +0100
• d1517b7982 Added sincos test case Clifford Wolf 2013-12-04 09:10:41 +0100
• 507c63d112 Added support for local regs in named blocks Clifford Wolf 2013-12-04 09:10:16 +0100
• b5afd75b0a Fixed gentb_constant handling in autotest backend Clifford Wolf 2013-12-04 09:09:42 +0100
• bb20aceeb3 More ABC releated Makefile changes Clifford Wolf 2013-12-04 08:31:52 +0100
• 637a12b7e3 Minor improvements in ABc build Clifford Wolf 2013-12-03 16:50:14 +0100
• 0f4055d4c6 Progress on AppNote 011 Clifford Wolf 2013-12-02 12:54:21 +0100
• 6e227e3666 Fixed submod for non-primitive cells Clifford Wolf 2013-12-02 12:53:55 +0100
• e881878341 Fixed submod for non-cleaned designs Clifford Wolf 2013-12-02 12:18:07 +0100
• a66ca0472a Added Pass:call_newsel API Clifford Wolf 2013-12-02 12:17:04 +0100
• 905eac04f1 Added "history" command Clifford Wolf 2013-12-02 11:29:39 +0100
• 97efc2ed5f A fix in memory_dff for write ports with static addresses Clifford Wolf 2013-12-01 14:08:18 +0100
• 73e28f0e39 Progress on AppNote 011 Clifford Wolf 2013-12-01 14:07:44 +0100
• 7295b25955 Progress on AppNote 011 Clifford Wolf 2013-11-29 16:42:49 +0100
• e23a0072ec Progress on AppNote 011 Clifford Wolf 2013-11-29 12:51:16 +0100
• 1b3a60976d Using RTLIL::id2cstr for prompt printing Clifford Wolf 2013-11-29 11:55:18 +0100
• ed441346ca Added dump -m and -n options Clifford Wolf 2013-11-29 10:33:36 +0100
• f89ecbc100 Progress on AppNote 011 Clifford Wolf 2013-11-28 23:09:03 +0100
• d90ef1e143 Merge pull request #17 from mschmoelzer/master Clifford Wolf 2013-11-28 13:04:45 -0800
• 10aa08dca1 Fixed temp net name generation in rtlil process generator for abbreviated name matching Clifford Wolf 2013-11-28 21:47:08 +0100
• c60aaf8fa3 Added pattern support to "ls" command Clifford Wolf 2013-11-28 21:34:41 +0100
• 293356e87c Improved ID matching scheme in select (and thus for all commands) Clifford Wolf 2013-11-28 21:13:16 +0100
• 792bbad448 Fixes and improvements in "show" command Clifford Wolf 2013-11-28 21:02:19 +0100
• 6ad868ae25 Include unistd.h in svgview.cpp (required for getcwd() function) Martin Schmölzer 2013-11-28 18:38:40 +0100
• 9595eca181 More progress on AppNote 011 Clifford Wolf 2013-11-28 17:39:16 +0100
• 0e52f3fa01 Added "src" attribute to processes Clifford Wolf 2013-11-28 17:37:50 +0100
• 6dfb66d262 Started writing appnote 011 Clifford Wolf 2013-11-28 13:48:38 +0100
• 5af7f4db72 Added support for "show -pause" and "show -format dot" Clifford Wolf 2013-11-28 13:35:28 +0100
• 143a58bccc Added QGraphicsWebView to yosys-svgviewer Clifford Wolf 2013-11-28 11:57:25 +0100
• 1268182f0b Updated ABC to 9241719523f6 Clifford Wolf 2013-11-28 00:43:17 +0100
• 9826f6ae02 Added some svgviewer code for possible future switch to QGraphicsWebView Clifford Wolf 2013-11-27 20:43:42 +0100
• 18e52d81bf Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2013-11-27 09:08:42 +0100
• 38e7fa6530 Tighter integration of ABC build Clifford Wolf 2013-11-27 09:08:35 +0100
• 0256105ac2 Set version number to 0.1.0+ Clifford Wolf 2013-11-27 06:29:13 +0100
• bc3cc88719 Started implementing undef support in "sat" command Clifford Wolf 2013-11-25 21:40:00 +0100
• 3d95047ce2 Bugfixes in new "stat" command Clifford Wolf 2013-11-25 21:08:34 +0100
• 4c7d6e63ec Added "stat" command Clifford Wolf 2013-11-25 20:43:57 +0100
• 61412d167f Improvements in satgen undef handling Clifford Wolf 2013-11-25 16:50:45 +0100
• bd65e67d8a Improvements in satgen undef handling Clifford Wolf 2013-11-25 15:12:01 +0100
• 11e8118589 Added ezsat vec_const() api Clifford Wolf 2013-11-25 15:10:32 +0100
• 8c3f4b3957 Started implementing undef handling in satgen Clifford Wolf 2013-11-25 04:51:33 +0100
• 4d43331748 Removed undef feature from ezsat api Clifford Wolf 2013-11-25 02:50:34 +0100
• 76f7c10cfc Using simplemap mappers from techmap Clifford Wolf 2013-11-24 23:31:14 +0100
• 3ee33cbdaf Added simplemap pass Clifford Wolf 2013-11-24 22:52:30 +0100
• 1afe6589df Renamed stdcells_sim.v to simcells.v and fixed blackbox.v Clifford Wolf 2013-11-24 20:44:00 +0100
• 8dafecd34d Added module->avail_parameters (for advanced techmap features) Clifford Wolf 2013-11-24 20:29:07 +0100
• 4011d47646 Added techmap -D and -I options Clifford Wolf 2013-11-24 20:04:48 +0100
• 7d9a90396d Added verilog frontend -ignore_redef option Clifford Wolf 2013-11-24 19:57:42 +0100
• 20175afd29 Added "techmap -share_map" option Clifford Wolf 2013-11-24 19:50:25 +0100
• 019b301541 Early wire/reg/parameter width calculation in ast/simplify Clifford Wolf 2013-11-24 19:40:23 +0100
• 620b7c900a Updated TODOs Clifford Wolf 2013-11-24 17:58:05 +0100
• ae798d3fd5 Fixed xilinx/example_sim_counter test bench Clifford Wolf 2013-11-24 17:55:46 +0100
• 41205afc39 Added proper dumping of signed/unsigned parameters to verilog backend Clifford Wolf 2013-11-24 17:47:22 +0100
• 0ef22c7609 Added support for signed parameters in ilang Clifford Wolf 2013-11-24 17:37:27 +0100
• 7eaad2218d Removed now obsolete test cases Clifford Wolf 2013-11-24 17:30:04 +0100
• f71e27dbf1 Remove auto_wire framework (smarter than the verilog standard) Clifford Wolf 2013-11-24 17:29:11 +0100
• 609caa23b5 Implemented correct handling of signed module parameters Clifford Wolf 2013-11-24 17:17:21 +0100
• 1e6836933d Added modelsim support to autotest Clifford Wolf 2013-11-24 15:10:43 +0100
• 72b35e0b99 Fixed "flatten" top-module detection: Only use on fully selected designs Clifford Wolf 2013-11-24 14:10:46 +0100
• 981677cf09 Fixed "make install" dependencies Clifford Wolf 2013-11-24 05:05:50 +0100
• 28093d9dd2 Added "top" attribute to mark top module in hierarchy Clifford Wolf 2013-11-24 05:03:43 +0100
• a4edecb0ca Updated command-reference-manual.tex Clifford Wolf 2013-11-23 20:09:47 +0100
• db8ce0fe95 AppNote 010 typo fixes and corrections Clifford Wolf 2013-11-23 20:04:51 +0100
• e216e0e291 AppNote 010 progress Clifford Wolf 2013-11-23 17:33:26 +0100
• 5f9c7fc6ea Improved handling of techmap special wires Clifford Wolf 2013-11-23 16:49:58 +0100
• 1de12e1efc Improved handling of initialized registers Clifford Wolf 2013-11-23 16:26:59 +0100
• 532091afcb Added more generic _TECHMAP_ wire mechanism to techmap pass Clifford Wolf 2013-11-23 15:58:06 +0100
• 9ab850e45e Making prograss on Appnote 010 Clifford Wolf 2013-11-23 05:46:51 +0100
• 3c023054bc Progress on AppNote 010 Clifford Wolf 2013-11-22 19:08:29 +0100
• bf501b9ba3 Started to write on AppNote 010: Verilog to BLIF Clifford Wolf 2013-11-22 17:33:59 +0100
• 7b9ca46f8d Updated command-reference-manual.tex Clifford Wolf 2013-11-22 15:02:40 +0100
• 295e352ba6 Renamed "placeholder" to "blackbox" Clifford Wolf 2013-11-22 15:01:12 +0100
• c854ad2e7e Some driver changes/fixes Clifford Wolf 2013-11-22 14:53:57 +0100
• a362fd81ae Fixed O(n^2) performance bug in verilog preprocessor Clifford Wolf 2013-11-22 14:08:43 +0100
• 058ceda6a0 Added more performance measurement infrastructure Clifford Wolf 2013-11-22 14:08:10 +0100
• e4429c480e Enable {* .. *} feature per default (removes dependency to REJECT feature in flex) Clifford Wolf 2013-11-22 12:46:02 +0100
• 18d003254c Massive performance improvement from refactoring RTLIL::SigSpec::optimize() Clifford Wolf 2013-11-22 04:41:20 +0100
• 8e58bb330d Added SigBit struct and refactored RTLIL::SigSpec::extract Clifford Wolf 2013-11-22 04:07:13 +0100
• 7b01ba384f Improved make rules for profiling and debugging Clifford Wolf 2013-11-22 04:05:30 +0100
• 1c4a6411af Updated abc Clifford Wolf 2013-11-21 22:39:10 +0100
• 40d9542647 Implemented $_DFFSR_ expression generator in verilog backend Clifford Wolf 2013-11-21 21:52:30 +0100
• 95c94a02fc Fixed async proc detection in mem2reg Clifford Wolf 2013-11-21 21:26:56 +0100
• 09471846c5 Major improvements in mem2reg and added "init" sync rules Clifford Wolf 2013-11-21 13:49:00 +0100
• 84ced2bb8e Fixed a bug in "add -global_input" Clifford Wolf 2013-11-21 03:01:20 +0100
• 64a5f8f75e Added "proc_arst -global_arst" feature Clifford Wolf 2013-11-20 21:00:43 +0100
• 08ceb3729e Fixed ilang parser: memory width Clifford Wolf 2013-11-20 19:55:52 +0100
• 2279b2a196 Added "add" command (only wires for now) Clifford Wolf 2013-11-20 19:37:40 +0100
• 65ad556f3d Another name resolution bugfix for generate blocks Clifford Wolf 2013-11-20 13:57:40 +0100