diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index c67636ccc..e000781bb 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1649,7 +1649,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 						cell->parameters[ID::MEMID] = RTLIL::Const(memory->name.str());
 						cell->parameters[ID::ABITS] = 32;
 						cell->parameters[ID::WIDTH] = memory->width;
-						cell->parameters[ID::PRIORITY] = RTLIL::Const(autoidx-1);
+						cell->parameters[ID::PRIORITY] = 0;
 					}
 				}
 			}
diff --git a/kernel/mem.cc b/kernel/mem.cc
index ada290309..80be52a0e 100644
--- a/kernel/mem.cc
+++ b/kernel/mem.cc
@@ -783,11 +783,10 @@ namespace {
 			mwr.addr = cell->getPort(ID::WR_ADDR).extract(i * abits, abits);
 			mwr.data = cell->getPort(ID::WR_DATA).extract(i * res.width, (ni - i) * res.width);
 			if (!is_compat) {
-				// Const priority_mask = cell->parameters.at(ID::WR_PRIORITY_MASK).extract(i * n_wr_ports, n_wr_ports);
+				Const priority_mask = cell->parameters.at(ID::WR_PRIORITY_MASK).extract(i * n_wr_ports, n_wr_ports);
 				for (int j = 0; j < n_wr_ports; j++)
 					if (wr_wide_continuation[j] != State::S1)
-						mwr.priority_mask.push_back(false);
-						// mwr.priority_mask.push_back(priority_mask[j] == State::S1);
+						mwr.priority_mask.push_back(priority_mask[j] == State::S1);
 			}
 			res.wr_ports.push_back(mwr);
 		}