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autoname.cc: Return number of renames

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Was previously the number of proposed renames, but since renames can be skipped this causes the final count to differ from the number of actually renamed objects.
Check counts in `tests/various/autoname.ys`.
This commit is contained in:
Krystine Sherwin 2025-09-26 11:05:50 +12:00
parent bc77b6213b
commit fef6bdae6c
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2 changed files with 10 additions and 1 deletions
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5
passes/cmds/autoname.cc
View file

@ -81,6 +81,7 @@ int autoname_worker(Module *module, const dict<Wire*, unsigned int>& wire_score)
} }
} }
int count = 0;
// compare against double best score for following comparisons so we don't // compare against double best score for following comparisons so we don't
// pre-empt a future iteration // pre-empt a future iteration
best_name.score *= 2; best_name.score *= 2;
@ -91,6 +92,7 @@ int autoname_worker(Module *module, const dict<Wire*, unsigned int>& wire_score)
IdString n = module->uniquify(IdString(it.second.name)); IdString n = module->uniquify(IdString(it.second.name));
log_debug("Rename cell %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n)); log_debug("Rename cell %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n));
module->rename(it.first, n); module->rename(it.first, n);
count++;
} }
for (auto &it : proposed_wire_names) { for (auto &it : proposed_wire_names) {
@ -99,9 +101,10 @@ int autoname_worker(Module *module, const dict<Wire*, unsigned int>& wire_score)
IdString n = module->uniquify(IdString(it.second.name)); IdString n = module->uniquify(IdString(it.second.name));
log_debug("Rename wire %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n)); log_debug("Rename wire %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n));
module->rename(it.first, n); module->rename(it.first, n);
count++;
} }
return proposed_cell_names.size() + proposed_wire_names.size(); return count;
} }
struct AutonamePass : public Pass { struct AutonamePass : public Pass {

6
tests/various/autoname.ys
View file

@ -18,6 +18,7 @@ module \top
end end
EOT EOT
logger -expect log "Rename cell .name in top to y_.and_Y" 1 logger -expect log "Rename cell .name in top to y_.and_Y" 1
logger -expect log "Renamed 1 objects" 1
debug autoname debug autoname
logger -check-expected logger -check-expected
@ -42,6 +43,7 @@ module \top
end end
EOT EOT
logger -expect log "Rename cell .name in top to ab_.or_A" 1 logger -expect log "Rename cell .name in top to ab_.or_A" 1
logger -expect log "Renamed 1 objects" 1
debug autoname debug autoname
logger -check-expected logger -check-expected
@ -78,6 +80,7 @@ end
EOT EOT
logger -expect log "Rename cell .name in top to bcd_.and_B" 1 logger -expect log "Rename cell .name in top to bcd_.and_B" 1
logger -expect log "Rename cell .name2 in top to c_has_a_long_name_.or_B" 1 logger -expect log "Rename cell .name2 in top to c_has_a_long_name_.or_B" 1
logger -expect log "Renamed 2 objects" 1
debug autoname debug autoname
logger -check-expected logger -check-expected
@ -113,6 +116,7 @@ end
EOT EOT
logger -expect log "Rename cell .name in top to y_.and_Y" 1 logger -expect log "Rename cell .name in top to y_.and_Y" 1
logger -expect log "Rename cell .name2 in top to y_.and_Y_1" 1 logger -expect log "Rename cell .name2 in top to y_.and_Y_1" 1
logger -expect log "Renamed 2 objects" 1
debug autoname debug autoname
logger -check-expected logger -check-expected
@ -174,6 +178,7 @@ EOT
# wires are named for being cell outputs # wires are named for being cell outputs
logger -expect log "Rename wire .d in top to or_Y" 1 logger -expect log "Rename wire .d in top to or_Y" 1
logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1 logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1
logger -expect log "Renamed 2 objects" 1
debug autoname t:$or debug autoname t:$or
logger -check-expected logger -check-expected
@ -186,5 +191,6 @@ logger -expect log "Rename cell .name3 in top to or_Y_.or_B_Y_.and_B" 1
# $c gets shortest name, since the cell driving it doesn't have known port # $c gets shortest name, since the cell driving it doesn't have known port
# directions # directions
logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1 logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1
logger -expect log "Renamed 4 objects" 1
debug autoname debug autoname
logger -check-expected logger -check-expected