From fef6bdae6cda277a022381c2f325ba374a94f377 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 26 Sep 2025 11:05:50 +1200
Subject: [PATCH] autoname.cc: Return number of renames

Was previously the number of proposed renames, but since renames can be skipped this causes the final count to differ from the number of actually renamed objects.
Check counts in `tests/various/autoname.ys`.
---
 passes/cmds/autoname.cc   | 5 ++++-
 tests/various/autoname.ys | 6 ++++++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/passes/cmds/autoname.cc b/passes/cmds/autoname.cc
index d2ff568c3..1ad2eab3c 100644
--- a/passes/cmds/autoname.cc
+++ b/passes/cmds/autoname.cc
@@ -81,6 +81,7 @@ int autoname_worker(Module *module, const dict<Wire*, unsigned int>& wire_score)
 		}
 	}
 
+	int count = 0;
 	// compare against double best score for following comparisons so we don't
 	// pre-empt a future iteration
 	best_name.score *= 2;
@@ -91,6 +92,7 @@ int autoname_worker(Module *module, const dict<Wire*, unsigned int>& wire_score)
 		IdString n = module->uniquify(IdString(it.second.name));
 		log_debug("Rename cell %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n));
 		module->rename(it.first, n);
+		count++;
 	}
 
 	for (auto &it : proposed_wire_names) {
@@ -99,9 +101,10 @@ int autoname_worker(Module *module, const dict<Wire*, unsigned int>& wire_score)
 		IdString n = module->uniquify(IdString(it.second.name));
 		log_debug("Rename wire %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n));
 		module->rename(it.first, n);
+		count++;
 	}
 
-	return proposed_cell_names.size() + proposed_wire_names.size();
+	return count;
 }
 
 struct AutonamePass : public Pass {
diff --git a/tests/various/autoname.ys b/tests/various/autoname.ys
index 29ca81bbe..fccecb1c2 100644
--- a/tests/various/autoname.ys
+++ b/tests/various/autoname.ys
@@ -18,6 +18,7 @@ module \top
 end
 EOT
 logger -expect log "Rename cell .name in top to y_.and_Y" 1
+logger -expect log "Renamed 1 objects" 1
 debug autoname
 logger -check-expected
 
@@ -42,6 +43,7 @@ module \top
 end
 EOT
 logger -expect log "Rename cell .name in top to ab_.or_A" 1
+logger -expect log "Renamed 1 objects" 1
 debug autoname
 logger -check-expected
 
@@ -78,6 +80,7 @@ end
 EOT
 logger -expect log "Rename cell .name in top to bcd_.and_B" 1
 logger -expect log "Rename cell .name2 in top to c_has_a_long_name_.or_B" 1
+logger -expect log "Renamed 2 objects" 1
 debug autoname
 logger -check-expected
 
@@ -113,6 +116,7 @@ end
 EOT
 logger -expect log "Rename cell .name in top to y_.and_Y" 1
 logger -expect log "Rename cell .name2 in top to y_.and_Y_1" 1
+logger -expect log "Renamed 2 objects" 1
 debug autoname
 logger -check-expected
 
@@ -174,6 +178,7 @@ EOT
 # wires are named for being cell outputs
 logger -expect log "Rename wire .d in top to or_Y" 1
 logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1
+logger -expect log "Renamed 2 objects" 1
 debug autoname t:$or
 logger -check-expected
 
@@ -186,5 +191,6 @@ logger -expect log "Rename cell .name3 in top to or_Y_.or_B_Y_.and_B" 1
 # $c gets shortest name, since the cell driving it doesn't have known port
 # directions
 logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1
+logger -expect log "Renamed 4 objects" 1
 debug autoname
 logger -check-expected