From fd811ddaee26a7f853687a67feb0a8f858f27a2b Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Fri, 14 Feb 2025 08:48:27 -0800 Subject: [PATCH] Cleanup --- Brewfile | 1 + Makefile | 38 +++++----------- frontends/verific/verific.cc | 4 +- passes/cmds/Makefile.inc | 7 --- passes/opt/Makefile.inc | 8 ++-- passes/silimate/Makefile.inc | 11 +++++ passes/{cmds => silimate}/activity.cc | 0 .../annotate_cell_fanout.cc | 0 .../annotate_logic_depth.cc | 0 passes/{techmap => silimate}/breaksop.cc | 0 passes/{cmds => silimate}/bus_rebuild.cc | 0 passes/{cmds => silimate}/longloop_select.cc | 0 passes/{opt => silimate}/opt_balance_tree.cc | 0 passes/{cmds => silimate}/selectconst.cc | 0 passes/{cmds => silimate}/splitfanout.cc | 0 passes/{cmds => silimate}/splitnetlist.cc | 0 passes/techmap/Makefile.inc | 16 +++---- passes/techmap/bufnorm.cc | 2 +- passes/techmap/libparse.cc | 20 ++------- tests/liberty/busdef2.lib | 45 ------------------- tests/liberty/busdef2.lib.filtered.ok | 8 ---- tests/liberty/busdef2.lib.verilogsim.ok | 4 -- tests/peepopt/.gitignore | 1 - 23 files changed, 39 insertions(+), 126 deletions(-) create mode 100644 passes/silimate/Makefile.inc rename passes/{cmds => silimate}/activity.cc (100%) rename passes/{cmds => silimate}/annotate_cell_fanout.cc (100%) rename passes/{cmds => silimate}/annotate_logic_depth.cc (100%) rename passes/{techmap => silimate}/breaksop.cc (100%) rename passes/{cmds => silimate}/bus_rebuild.cc (100%) rename passes/{cmds => silimate}/longloop_select.cc (100%) rename passes/{opt => silimate}/opt_balance_tree.cc (100%) rename passes/{cmds => silimate}/selectconst.cc (100%) rename passes/{cmds => silimate}/splitfanout.cc (100%) rename passes/{cmds => silimate}/splitnetlist.cc (100%) delete mode 100644 tests/liberty/busdef2.lib delete mode 100644 tests/liberty/busdef2.lib.filtered.ok delete mode 100644 tests/liberty/busdef2.lib.verilogsim.ok delete mode 100644 tests/peepopt/.gitignore diff --git a/Brewfile b/Brewfile index 8e8163651..89502bdab 100644 --- a/Brewfile +++ b/Brewfile @@ -12,6 +12,7 @@ brew "bash" brew "boost-python3" brew "llvm" brew "lld" +brew "m4" brew "autoconf" brew "dwarfutils" diff --git a/Makefile b/Makefile index 528a39090..6316cfc4a 100644 --- a/Makefile +++ b/Makefile @@ -123,7 +123,6 @@ BISON ?= bison STRIP ?= strip AWK ?= awk - ifeq ($(OS), Linux) LIBS += -ldw # SILIMATE: support for backward-cpp CXXFLAGS += -I/usr/include/libdwarf/ -DBACKWARD_HAS_DW # SILIMATE: support for backward-cpp @@ -711,32 +710,19 @@ include $(YOSYS_SRC)/frontends/blif/Makefile.inc include $(YOSYS_SRC)/frontends/liberty/Makefile.inc include $(YOSYS_SRC)/passes/equiv/Makefile.inc -OBJS += passes/cmds/select.o -OBJS += passes/cmds/show.o -OBJS += passes/cmds/stat.o -OBJS += passes/cmds/cover.o -OBJS += passes/cmds/design.o -OBJS += passes/cmds/plugin.o -OBJS += passes/cmds/annotate_logic_depth.o -OBJS += passes/cmds/blackbox.o -OBJS += passes/cmds/check.o -OBJS += passes/cmds/clean_zerowidth.o -OBJS += passes/cmds/selectconst.o -OBJS += passes/cmds/setattr.o -OBJS += passes/cmds/splitcells.o -OBJS += passes/cmds/annotate_cell_fanout.o -OBJS += passes/cmds/splitfanout.o -OBJS += passes/cmds/splitnets.o -OBJS += passes/cmds/tee.o -OBJS += passes/cmds/activity.o -OBJS += passes/cmds/splitnetlist.o -OBJS += passes/cmds/bus_rebuild.o -OBJS += passes/cmds/longloop_select.o +include $(YOSYS_SRC)/passes/cmds/Makefile.inc +include $(YOSYS_SRC)/passes/silimate/Makefile.inc + +OBJS += passes/opt/pmux2shiftx.o +OBJS += passes/opt/muxpack.o OBJS += passes/sat/sim.o -OBJS += passes/techmap/bufnorm.o -OBJS += passes/cmds/rename.o -OBJS += passes/cmds/segv.o -OBJS += passes/cmds/delete.o +OBJS += passes/techmap/extract.o +OBJS += passes/techmap/extract_reduce.o +OBJS += passes/techmap/alumacc.o +OBJS += passes/techmap/pmuxtree.o +OBJS += passes/techmap/bmuxmap.o +OBJS += passes/techmap/demuxmap.o +OBJS += passes/techmap/aigmap.o include $(YOSYS_SRC)/passes/hierarchy/Makefile.inc include $(YOSYS_SRC)/passes/memory/Makefile.inc diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index b635518b7..12fec7a79 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -4564,10 +4564,8 @@ struct ReadPass : public Pass { args[0] = "verific"; } else { args[0] = "read_verilog"; - if (args[1] == "-formal") { + if (args[1] == "-formal") args.insert(args.begin()+1, std::string()); - RuntimeFlags::SetVar("veri_ignore_assertion_statements", 0); - } args[1] = "-sv"; args.insert(args.begin()+1, "-defer"); } diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index 623ef2653..5a2af4df5 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -6,7 +6,6 @@ OBJS += passes/cmds/add.o OBJS += passes/cmds/delete.o OBJS += passes/cmds/design.o OBJS += passes/cmds/select.o -OBJS += passes/cmds/selectconst.o OBJS += passes/cmds/show.o OBJS += passes/cmds/viz.o OBJS += passes/cmds/rename.o @@ -16,7 +15,6 @@ OBJS += passes/cmds/scatter.o OBJS += passes/cmds/setundef.o OBJS += passes/cmds/splitnets.o OBJS += passes/cmds/splitcells.o -OBJS += passes/cmds/splitfanout.o OBJS += passes/cmds/stat.o OBJS += passes/cmds/internal_stats.o OBJS += passes/cmds/setattr.o @@ -53,10 +51,5 @@ OBJS += passes/cmds/future.o OBJS += passes/cmds/box_derive.o OBJS += passes/cmds/example_dt.o OBJS += passes/cmds/portarcs.o - -OBJS += passes/cmds/activity.o -OBJS += passes/cmds/splitnetlist.o -OBJS += passes/cmds/bus_rebuild.o - OBJS += passes/cmds/wrapcell.o OBJS += passes/cmds/setenv.o diff --git a/passes/opt/Makefile.inc b/passes/opt/Makefile.inc index 481acd250..76bf8a84e 100644 --- a/passes/opt/Makefile.inc +++ b/passes/opt/Makefile.inc @@ -12,16 +12,14 @@ OBJS += passes/opt/opt_share.o OBJS += passes/opt/opt_clean.o OBJS += passes/opt/opt_expr.o -OBJS += passes/opt/opt_balance_tree.o -OBJS += passes/opt/muxpack.o -OBJS += passes/opt/wreduce.o -OBJS += passes/opt/pmux2shiftx.o - ifneq ($(SMALL),1) OBJS += passes/opt/share.o +OBJS += passes/opt/wreduce.o OBJS += passes/opt/opt_demorgan.o OBJS += passes/opt/rmports.o OBJS += passes/opt/opt_lut.o OBJS += passes/opt/opt_lut_ins.o OBJS += passes/opt/opt_ffinv.o +OBJS += passes/opt/pmux2shiftx.o +OBJS += passes/opt/muxpack.o endif diff --git a/passes/silimate/Makefile.inc b/passes/silimate/Makefile.inc new file mode 100644 index 000000000..209adcd9a --- /dev/null +++ b/passes/silimate/Makefile.inc @@ -0,0 +1,11 @@ + +OBJS += passes/silimate/activity.o +OBJS += passes/silimate/annotate_cell_fanout.o +OBJS += passes/silimate/annotate_logic_depth.o +OBJS += passes/silimate/breaksop.o +OBJS += passes/silimate/bus_rebuild.o +OBJS += passes/silimate/longloop_select.o +OBJS += passes/silimate/opt_balance_tree.o +OBJS += passes/silimate/selectconst.o +OBJS += passes/silimate/splitfanout.o +OBJS += passes/silimate/splitnetlist.o diff --git a/passes/cmds/activity.cc b/passes/silimate/activity.cc similarity index 100% rename from passes/cmds/activity.cc rename to passes/silimate/activity.cc diff --git a/passes/cmds/annotate_cell_fanout.cc b/passes/silimate/annotate_cell_fanout.cc similarity index 100% rename from passes/cmds/annotate_cell_fanout.cc rename to passes/silimate/annotate_cell_fanout.cc diff --git a/passes/cmds/annotate_logic_depth.cc b/passes/silimate/annotate_logic_depth.cc similarity index 100% rename from passes/cmds/annotate_logic_depth.cc rename to passes/silimate/annotate_logic_depth.cc diff --git a/passes/techmap/breaksop.cc b/passes/silimate/breaksop.cc similarity index 100% rename from passes/techmap/breaksop.cc rename to passes/silimate/breaksop.cc diff --git a/passes/cmds/bus_rebuild.cc b/passes/silimate/bus_rebuild.cc similarity index 100% rename from passes/cmds/bus_rebuild.cc rename to passes/silimate/bus_rebuild.cc diff --git a/passes/cmds/longloop_select.cc b/passes/silimate/longloop_select.cc similarity index 100% rename from passes/cmds/longloop_select.cc rename to passes/silimate/longloop_select.cc diff --git a/passes/opt/opt_balance_tree.cc b/passes/silimate/opt_balance_tree.cc similarity index 100% rename from passes/opt/opt_balance_tree.cc rename to passes/silimate/opt_balance_tree.cc diff --git a/passes/cmds/selectconst.cc b/passes/silimate/selectconst.cc similarity index 100% rename from passes/cmds/selectconst.cc rename to passes/silimate/selectconst.cc diff --git a/passes/cmds/splitfanout.cc b/passes/silimate/splitfanout.cc similarity index 100% rename from passes/cmds/splitfanout.cc rename to passes/silimate/splitfanout.cc diff --git a/passes/cmds/splitnetlist.cc b/passes/silimate/splitnetlist.cc similarity index 100% rename from passes/cmds/splitnetlist.cc rename to passes/silimate/splitnetlist.cc diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index c98b6d2de..4e1d16744 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -7,15 +7,6 @@ OBJS += passes/techmap/maccmap.o OBJS += passes/techmap/booth.o OBJS += passes/techmap/libparse.o -OBJS += passes/techmap/bmuxmap.o -OBJS += passes/techmap/demuxmap.o -OBJS += passes/techmap/pmuxtree.o -OBJS += passes/techmap/alumacc.o -OBJS += passes/techmap/extract.o -OBJS += passes/techmap/extract_reduce.o -OBJS += passes/techmap/aigmap.o -OBJS += passes/techmap/breaksop.o - ifeq ($(ENABLE_ABC),1) OBJS += passes/techmap/abc.o OBJS += passes/techmap/abc9.o @@ -34,11 +25,18 @@ ifneq ($(SMALL),1) OBJS += passes/techmap/iopadmap.o OBJS += passes/techmap/clkbufmap.o OBJS += passes/techmap/hilomap.o +OBJS += passes/techmap/extract.o OBJS += passes/techmap/extract_fa.o OBJS += passes/techmap/extract_counter.o +OBJS += passes/techmap/extract_reduce.o +OBJS += passes/techmap/alumacc.o OBJS += passes/techmap/dffinit.o +OBJS += passes/techmap/pmuxtree.o +OBJS += passes/techmap/bmuxmap.o +OBJS += passes/techmap/demuxmap.o OBJS += passes/techmap/bwmuxmap.o OBJS += passes/techmap/muxcover.o +OBJS += passes/techmap/aigmap.o OBJS += passes/techmap/tribuf.o OBJS += passes/techmap/lut2mux.o OBJS += passes/techmap/nlutmap.o diff --git a/passes/techmap/bufnorm.cc b/passes/techmap/bufnorm.cc index affb7dd21..a4552c71b 100644 --- a/passes/techmap/bufnorm.cc +++ b/passes/techmap/bufnorm.cc @@ -391,7 +391,7 @@ struct BufnormPass : public Pass { } if (w->name.isPublic()) - log_debug(" directly driven by cell %s port %s: %s\n", + log(" directly driven by cell %s port %s: %s\n", log_id(cell), log_id(conn.first), log_id(w)); for (auto bit : SigSpec(w)) diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc index ac3d3d2bd..06dd6288e 100644 --- a/passes/techmap/libparse.cc +++ b/passes/techmap/libparse.cc @@ -389,12 +389,9 @@ LibertyAst *LibertyParser::parse() if (tok == 'v') { tok = lexer(str); } - while (tok == '(' || tok == ')' || tok == '+' || tok == '-' || tok == '*' || tok == '/' || tok == '!') { // SILIMATE: added parentheses + while (tok == '+' || tok == '-' || tok == '*' || tok == '/' || tok == '!') { ast->value += tok; - if (tok == ')') { // SILIMATE: semicolon may follow close parenthesis - tok = lexer(str); - if (tok == ';') break; - } else tok = lexer(str); + tok = lexer(str); if (tok != 'v') error(); ast->value += str; @@ -407,13 +404,6 @@ LibertyAst *LibertyParser::parse() // instead of the ';' too.. if ((tok == ';') || (tok == 'n')) break; - else if (tok == '[') { - while (tok != ']') { - tok = lexer(str); - } - ast->value += '[' + str + ']'; - continue; - } else error(); continue; @@ -475,16 +465,12 @@ LibertyAst *LibertyParser::parse() { case 'n': continue; - case ':': // SILIMATE HACK: eat up the ':' and the next thing too - tok = lexer(arg); - if (tok != 'v') - error("Expecting string after ':'."); - break; case '[': case ']': case '}': case '{': case '\"': + case ':': eReport = "Unexpected '"; eReport += static_cast(tok); eReport += "'."; diff --git a/tests/liberty/busdef2.lib b/tests/liberty/busdef2.lib deleted file mode 100644 index 6ccbbba14..000000000 --- a/tests/liberty/busdef2.lib +++ /dev/null @@ -1,45 +0,0 @@ -/* Tests two things: */ -/* (1) Bus without any individual pin definition */ -/* (2) Having a custom field with define, which can allow square brackets */ -library (liberty_define) { - delay_model : "table_lookup" ; - simulation : false ; - capacitive_load_unit (1,pF) ; - leakage_power_unit : "1pW" ; - current_unit : "1A" ; - pulling_resistance_unit : "1kohm" ; - time_unit : "1ns" ; - voltage_unit : "1v" ; - library_features : "report_delay_calculation" ; - input_threshold_pct_rise : 50 ; - input_threshold_pct_fall : 50 ; - output_threshold_pct_rise : 50 ; - output_threshold_pct_fall : 50 ; - slew_lower_threshold_pct_rise : 30 ; - slew_lower_threshold_pct_fall : 30 ; - slew_upper_threshold_pct_rise : 70 ; - slew_upper_threshold_pct_fall : 70 ; - slew_derate_from_library : 1.0 ; - nom_process : 1.0 ; - nom_temperature : 85.0 ; - nom_voltage : 0.75 ; - type (bus8) { - base_type : "array"; - data_type : "bit"; - bit_width : 8; - bit_from : 7; - bit_to : 0; - } - define (original_pin, pin, string) ; - cell (not_cell) { - bus (A) { - bus_type : "bus8" ; - direction : "input" ; - } - pin (Y) { - function : !A[0] ; - direction : "output" ; - original_pin : A[0] ; - } - } -} \ No newline at end of file diff --git a/tests/liberty/busdef2.lib.filtered.ok b/tests/liberty/busdef2.lib.filtered.ok deleted file mode 100644 index d9df6a978..000000000 --- a/tests/liberty/busdef2.lib.filtered.ok +++ /dev/null @@ -1,8 +0,0 @@ -library(liberty_define) { - cell(not_cell) { - pin(Y) { - function : !A[0] ; - direction : output ; - } - } -} diff --git a/tests/liberty/busdef2.lib.verilogsim.ok b/tests/liberty/busdef2.lib.verilogsim.ok deleted file mode 100644 index b9a8d597a..000000000 --- a/tests/liberty/busdef2.lib.verilogsim.ok +++ /dev/null @@ -1,4 +0,0 @@ -module not_cell (Y); - output Y; - assign Y = !A[0]; // !A[0] -endmodule diff --git a/tests/peepopt/.gitignore b/tests/peepopt/.gitignore deleted file mode 100644 index 50e13221d..000000000 --- a/tests/peepopt/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/*.log