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Cleanup

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This commit is contained in:
Akash Levy 2025-02-14 08:48:27 -08:00
parent f76fd9280b
commit fd811ddaee
23 changed files with 39 additions and 126 deletions
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16
passes/techmap/Makefile.inc
View file

@ -7,15 +7,6 @@ OBJS += passes/techmap/maccmap.o
OBJS += passes/techmap/booth.o
OBJS += passes/techmap/libparse.o
OBJS += passes/techmap/bmuxmap.o
OBJS += passes/techmap/demuxmap.o
OBJS += passes/techmap/pmuxtree.o
OBJS += passes/techmap/alumacc.o
OBJS += passes/techmap/extract.o
OBJS += passes/techmap/extract_reduce.o
OBJS += passes/techmap/aigmap.o
OBJS += passes/techmap/breaksop.o
ifeq ($(ENABLE_ABC),1)
OBJS += passes/techmap/abc.o
OBJS += passes/techmap/abc9.o
@ -34,11 +25,18 @@ ifneq ($(SMALL),1)
OBJS += passes/techmap/iopadmap.o
OBJS += passes/techmap/clkbufmap.o
OBJS += passes/techmap/hilomap.o
OBJS += passes/techmap/extract.o
OBJS += passes/techmap/extract_fa.o
OBJS += passes/techmap/extract_counter.o
OBJS += passes/techmap/extract_reduce.o
OBJS += passes/techmap/alumacc.o
OBJS += passes/techmap/dffinit.o
OBJS += passes/techmap/pmuxtree.o
OBJS += passes/techmap/bmuxmap.o
OBJS += passes/techmap/demuxmap.o
OBJS += passes/techmap/bwmuxmap.o
OBJS += passes/techmap/muxcover.o
OBJS += passes/techmap/aigmap.o
OBJS += passes/techmap/tribuf.o
OBJS += passes/techmap/lut2mux.o
OBJS += passes/techmap/nlutmap.o

96
passes/techmap/breaksop.cc
View file

@ -1,96 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2017 Robert Ou <rqou@robertou.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct BreakSopPass : public Pass {
BreakSopPass() : Pass("breaksop", "break $sop cells into $reduce_and/$reduce_or cells") { }
void help() override
{
log("\n");
log(" breaksop [selection]\n");
log("\n");
log("Break $sop cells into $reduce_and/$reduce_or cells.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing BREAKSOP pass (break $sop cells into $reduce_and/$reduce_or cells).\n");
extra_args(args, 1, design);
for (auto module : design->selected_modules())
{
// Data structures
pool<Cell*> cells_to_remove;
SigMap sigmap(module);
// Process $sop cells
for (auto cell : module->selected_cells())
{
if (cell->type == ID($sop))
{
// Read the inputs/outputs/parameters of the $sop cell
auto sop_inputs = sigmap(cell->getPort(ID::A));
auto sop_output = sigmap(cell->getPort(ID::Y))[0];
auto sop_depth = cell->getParam(ID::DEPTH).as_int();
auto sop_width = cell->getParam(ID::WIDTH).as_int();
auto sop_table = cell->getParam(ID::TABLE);
// Get $sop output wire name
module->rename(cell->name, module->uniquify(sop_output.wire->name.str() + "_sop"));
// Construct $reduce_and cells
pool<SigBit> intermed_wires;
for (int i = 0; i < sop_depth; i++) {
// Wire for the output
auto and_out = module->addWire(NEW_ID2_SUFFIX("andterm_out"));
intermed_wires.insert(and_out);
// Signals for the inputs
pool<SigBit> and_in;
for (int j = 0; j < sop_width; j++)
if (sop_table[2 * (i * sop_width + j) + 0])
and_in.insert(module->Not(NEW_ID2_SUFFIX(stringf("sop_in_%d_comp", j)), sop_inputs[j], false, cell->get_src_attribute()));
else if (sop_table[2 * (i * sop_width + j) + 1])
and_in.insert(sop_inputs[j]);
// Construct the cell
module->addReduceAnd(NEW_ID2_SUFFIX("andterm"), and_in, and_out, false, cell->get_src_attribute());
}
// Construct the $reduce_or cell
module->addReduceOr(NEW_ID2_SUFFIX("orterm"), intermed_wires, sop_output, false, cell->get_src_attribute());
// Mark the $sop cell for removal
cells_to_remove.insert(cell);
}
}
// Perform removal of $sop cells
for (auto cell : cells_to_remove)
module->remove(cell);
}
}
} BreakSopPass;
PRIVATE_NAMESPACE_END

2
passes/techmap/bufnorm.cc
View file

@ -391,7 +391,7 @@ struct BufnormPass : public Pass {
}
if (w->name.isPublic())
log_debug(" directly driven by cell %s port %s: %s\n",
log(" directly driven by cell %s port %s: %s\n",
log_id(cell), log_id(conn.first), log_id(w));
for (auto bit : SigSpec(w))

20
passes/techmap/libparse.cc
View file

@ -389,12 +389,9 @@ LibertyAst *LibertyParser::parse()
if (tok == 'v') {
tok = lexer(str);
}
while (tok == '(' || tok == ')' || tok == '+' || tok == '-' || tok == '*' || tok == '/' || tok == '!') { // SILIMATE: added parentheses
while (tok == '+' || tok == '-' || tok == '*' || tok == '/' || tok == '!') {
ast->value += tok;
if (tok == ')') { // SILIMATE: semicolon may follow close parenthesis
tok = lexer(str);
if (tok == ';') break;
} else tok = lexer(str);
tok = lexer(str);
if (tok != 'v')
error();
ast->value += str;
@ -407,13 +404,6 @@ LibertyAst *LibertyParser::parse()
// instead of the ';' too..
if ((tok == ';') || (tok == 'n'))
break;
else if (tok == '[') {
while (tok != ']') {
tok = lexer(str);
}
ast->value += '[' + str + ']';
continue;
}
else
error();
continue;
@ -475,16 +465,12 @@ LibertyAst *LibertyParser::parse()
{
case 'n':
continue;
case ':': // SILIMATE HACK: eat up the ':' and the next thing too
tok = lexer(arg);
if (tok != 'v')
error("Expecting string after ':'.");
break;
case '[':
case ']':
case '}':
case '{':
case '\"':
case ':':
eReport = "Unexpected '";
eReport += static_cast<char>(tok);
eReport += "'.";