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https://github.com/YosysHQ/yosys
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Cleanup
This commit is contained in:
Akash Levy
parent
f76fd9280b
commit
fd811ddaee
23 changed files with 39 additions and 126 deletions
272
passes/silimate/splitnetlist.cc
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272
passes/silimate/splitnetlist.cc
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#include "kernel/sigtools.h"
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#include "kernel/yosys.h"
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#include <set>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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// Recursively traverses backward from a sig, record if a cell was traversed, and push onto the cell's inputs.
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// Similarly with assign statements traverses lhs -> rhs
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void recordTransFanin(RTLIL::SigSpec &sig, dict<RTLIL::SigSpec, std::set<Cell *> *> &sig2CellsInFanin,
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dict<RTLIL::SigSpec, RTLIL::SigSpec> &lhsSig2RhsSig, std::set<Cell *> &visitedCells, std::set<RTLIL::SigSpec> &visitedSigSpec)
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{
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if (sig.is_fully_const()) {
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return;
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}
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if (visitedSigSpec.count(sig)) {
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return;
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}
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visitedSigSpec.insert(sig);
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if (sig2CellsInFanin.count(sig)) {
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std::set<Cell *> *sigFanin = sig2CellsInFanin[sig];
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for (std::set<Cell *>::iterator it = sigFanin->begin(); it != sigFanin->end(); it++) {
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Cell *cell = *it;
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if (visitedCells.count(cell)) {
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continue;
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}
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visitedCells.insert(cell);
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for (auto &conn : cell->connections()) {
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IdString portName = conn.first;
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RTLIL::SigSpec actual = conn.second;
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if (cell->input(portName)) {
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if (!actual.is_chunk()) {
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for (auto it = actual.chunks().rbegin(); it != actual.chunks().rend(); ++it) {
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RTLIL::SigSpec sub_actual = *it;
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recordTransFanin(sub_actual, sig2CellsInFanin, lhsSig2RhsSig, visitedCells, visitedSigSpec);
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}
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} else {
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recordTransFanin(actual, sig2CellsInFanin, lhsSig2RhsSig, visitedCells, visitedSigSpec);
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}
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}
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}
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}
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}
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if (lhsSig2RhsSig.count(sig)) {
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RTLIL::SigSpec rhs = lhsSig2RhsSig[sig];
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recordTransFanin(rhs, sig2CellsInFanin, lhsSig2RhsSig, visitedCells, visitedSigSpec);
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}
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}
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// Signal cell driver(s), precompute a cell output signal to a cell map
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void sigCellDrivers(RTLIL::Design *design, dict<RTLIL::SigSpec, std::set<Cell *> *> &sig2CellsInFanin)
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{
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if (!design->top_module())
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return;
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if (design->top_module()->cells().size() == 0)
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return;
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for (auto cell : design->top_module()->cells()) {
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for (auto &conn : cell->connections()) {
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IdString portName = conn.first;
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RTLIL::SigSpec actual = conn.second;
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std::set<Cell *> *newSet;
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if (cell->output(portName)) {
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if (!actual.is_chunk()) {
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for (auto it = actual.chunks().rbegin(); it != actual.chunks().rend(); ++it) {
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RTLIL::SigSpec sub_actual = *it;
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if (sig2CellsInFanin.count(sub_actual)) {
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newSet = sig2CellsInFanin[sub_actual];
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} else {
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newSet = new std::set<Cell *>;
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sig2CellsInFanin[sub_actual] = newSet;
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}
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newSet->insert(cell);
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}
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} else {
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if (sig2CellsInFanin.count(actual)) {
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newSet = sig2CellsInFanin[actual];
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} else {
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newSet = new std::set<Cell *>;
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sig2CellsInFanin[actual] = newSet;
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}
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newSet->insert(cell);
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for (int i = 0; i < actual.size(); i++) {
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SigSpec bit_sig = actual.extract(i, 1);
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if (sig2CellsInFanin.count(bit_sig)) {
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newSet = sig2CellsInFanin[bit_sig];
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} else {
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newSet = new std::set<Cell *>;
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sig2CellsInFanin[bit_sig] = newSet;
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}
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newSet->insert(cell);
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}
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}
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}
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}
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}
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}
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// Assign statements fanin, traces the lhs to rhs sigspecs and precompute a map
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void lhs2rhs(RTLIL::Design *design, dict<RTLIL::SigSpec, RTLIL::SigSpec> &lhsSig2rhsSig)
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{
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if (!design->top_module())
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return;
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if (design->top_module()->connections().size() == 0)
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return;
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for (auto it = design->top_module()->connections().begin(); it != design->top_module()->connections().end(); ++it) {
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RTLIL::SigSpec lhs = it->first;
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RTLIL::SigSpec rhs = it->second;
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if (rhs.is_fully_const()) {
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continue;
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}
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if (!lhs.is_chunk()) {
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// If lhs is not a chunk (leaf) ie: assign {a,b} = ..., then bitblast both lhs and rhs
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std::vector<SigSpec> lhsBits;
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for (int i = 0; i < lhs.size(); i++) {
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SigSpec bit_sig = lhs.extract(i, 1);
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lhsBits.push_back(bit_sig);
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}
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std::vector<SigSpec> rhsBits;
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for (int i = 0; i < rhs.size(); i++) {
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SigSpec bit_sig = rhs.extract(i, 1);
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rhsBits.push_back(bit_sig);
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}
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for (uint32_t i = 0; i < lhsBits.size(); i++) {
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if (i < rhsBits.size())
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lhsSig2rhsSig[lhsBits[i]] = rhsBits[i];
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}
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} else {
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lhsSig2rhsSig[lhs] = rhs;
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}
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}
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}
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std::string_view rtrim_until(std::string_view str, char c)
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{
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auto pos = str.rfind(c);
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if (pos != std::string_view::npos)
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str = str.substr(0, pos);
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return str;
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}
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struct SplitNetlist : public ScriptPass {
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SplitNetlist()
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: ScriptPass("splitnetlist", "Splits a netlist into multiple modules using transitive fanin grouping. \
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The output names that belong in the same logical cluster have to have the same prefix: <prefix>_<name>")
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{
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}
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void script() override {}
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void execute(std::vector<std::string>, RTLIL::Design *design) override
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{
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if (design == nullptr) {
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log_error("No design object");
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return;
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}
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bool debug = false;
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if (std::getenv("DEBUG_SPLITNETLIST")) {
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debug = true;
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}
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log("Running splitnetlist pass\n");
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log_flush();
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if (debug)
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run_pass("write_rtlil post_buf.rtlil");
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log("Mapping signals to cells\n");
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log_flush();
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// Precompute cell output sigspec to cell map
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dict<RTLIL::SigSpec, std::set<Cell *> *> sig2CellsInFanin;
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sigCellDrivers(design, sig2CellsInFanin);
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log("Mapping assignments\n");
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log_flush();
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// Precompute lhs to rhs sigspec map
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dict<RTLIL::SigSpec, RTLIL::SigSpec> lhsSig2RhsSig;
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lhs2rhs(design, lhsSig2RhsSig);
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// Struct representing a cluster
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typedef struct CellsAndSigs {
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std::set<Cell *> visitedCells;
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std::set<RTLIL::SigSpec> visitedSigSpec;
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} CellsAndSigs;
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// Cluster mapped by prefix
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typedef std::map<std::string, CellsAndSigs> CellName_ObjectMap;
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CellName_ObjectMap cellName_ObjectMap;
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// Record logic cone by output sharing the same prefix
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if (!design->top_module())
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return;
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if (design->top_module()->wires().size() == 0)
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return;
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log("Cells grouping\n");
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log_flush();
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for (auto wire : design->top_module()->wires()) {
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if (!wire->port_output)
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continue;
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std::string output_port_name = wire ? wire->name.c_str() : "";
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if (output_port_name.empty())
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continue;
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// We want to truncate the final _<index>_ part of the string
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// Example: "add_Y_0_"
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// Result: "add_Y"
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std::string::iterator end = output_port_name.end() - 1;
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if ((*end) == '_') {
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// Last character is an _, it is a bit blasted index
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end--;
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for (; end != output_port_name.begin(); end--) {
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if ((*end) != '_') {
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// Truncate until the next _
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continue;
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} else {
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// Truncate the _
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break;
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}
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}
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}
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std::string no_bitblast_prefix;
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std::copy(output_port_name.begin(), end, std::back_inserter(no_bitblast_prefix));
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// We then truncate the port name, Result: "add"
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std::string_view po_prefix = rtrim_until(std::string_view(no_bitblast_prefix), '_');
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std::set<Cell *> visitedCells;
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std::set<RTLIL::SigSpec> visitedSigSpec;
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RTLIL::SigSpec actual = wire;
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// Visit the output sigspec
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recordTransFanin(actual, sig2CellsInFanin, lhsSig2RhsSig, visitedCells, visitedSigSpec);
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// Visit the output sigspec bits
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for (int i = 0; i < actual.size(); i++) {
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SigSpec bit_sig = actual.extract(i, 1);
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recordTransFanin(bit_sig, sig2CellsInFanin, lhsSig2RhsSig, visitedCells, visitedSigSpec);
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}
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// Record the visited objects in the corresponding cluster
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CellName_ObjectMap::iterator itr = cellName_ObjectMap.find(std::string(po_prefix));
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if (itr == cellName_ObjectMap.end()) {
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CellsAndSigs components;
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for (auto cell : visitedCells) {
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components.visitedCells.insert(cell);
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}
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for (auto sig : visitedSigSpec) {
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components.visitedSigSpec.insert(sig);
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}
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cellName_ObjectMap.emplace(std::string(po_prefix), components);
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} else {
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CellsAndSigs &components = itr->second;
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for (auto cell : visitedCells) {
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components.visitedCells.insert(cell);
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}
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for (auto sig : visitedSigSpec) {
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components.visitedSigSpec.insert(sig);
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}
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}
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}
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// Create submod attributes for the submod command
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log("Creating submods\n");
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log_flush();
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for (CellName_ObjectMap::iterator itr = cellName_ObjectMap.begin(); itr != cellName_ObjectMap.end(); itr++) {
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if (debug)
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std::cout << "Cluster name: " << itr->first << std::endl;
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CellsAndSigs &components = itr->second;
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for (auto cell : components.visitedCells) {
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cell->set_string_attribute(RTLIL::escape_id("submod"), itr->first);
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if (debug)
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std::cout << " CELL: " << cell->name.c_str() << std::endl;
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}
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}
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// Execute the submod command
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Pass::call(design, "submod");
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log("End splitnetlist pass\n");
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log_flush();
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}
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} SplitNetlist;
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PRIVATE_NAMESPACE_END
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