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https://github.com/YosysHQ/yosys
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Cleanup
This commit is contained in:
Akash Levy
parent
f76fd9280b
commit
fd811ddaee
23 changed files with 39 additions and 126 deletions
257
passes/silimate/longloop_select.cc
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257
passes/silimate/longloop_select.cc
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/celltypes.h"
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#include "kernel/sigtools.h"
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#include "kernel/utils.h"
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#include "kernel/yosys.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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typedef RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell> cell_ptr_cmp;
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struct LongLoopSelect : public ScriptPass {
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LongLoopSelect()
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: ScriptPass("longloop_select", "Selects long for-loops (Creating logic above a certain logic depth) for further optimizations")
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{
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}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" longloop_select [-depth <for-loop threshold depth>] [-abc_opt <ABC options>] [-abc_script <ABC script>]\n");
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log(" If no ABC script/option is provided, this pass simply selects cells in for-loops\n");
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log(" If an ABC script/option is provided, this pass selects cells in a per for-loop basis and runs ABC with the given script\n");
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log("\n");
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}
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void script() override {}
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// Adapted from the torder pass
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void toposorting(std::vector<Cell *> &cells, SigMap &sigmap,
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TopoSort<RTLIL::Cell *, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> &toposort, bool debug)
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{
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if (debug) {
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log(" Collecting design data\n");
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log_flush();
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}
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dict<SigBit, pool<Cell *>> bit_drivers, bit_users;
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for (Cell *cell : cells) {
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for (auto conn : cell->connections()) {
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bool noautostop = false;
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if (!noautostop && yosys_celltypes.cell_known(cell->type)) {
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if (conn.first.in(ID::Q, ID::CTRL_OUT, ID::RD_DATA))
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continue;
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if (cell->type.in(ID($memrd), ID($memrd_v2)) && conn.first == ID::DATA)
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continue;
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}
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if (cell->input(conn.first))
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for (auto bit : sigmap(conn.second))
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bit_users[bit].insert(cell);
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if (cell->output(conn.first))
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for (auto bit : sigmap(conn.second))
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bit_drivers[bit].insert(cell);
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toposort.node(cell);
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}
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}
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if (debug) {
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log(" Creating sorting data structure\n");
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log_flush();
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}
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for (auto &it : bit_users)
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if (bit_drivers.count(it.first))
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for (auto driver_cell : bit_drivers.at(it.first))
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for (auto user_cell : it.second)
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toposort.edge(driver_cell, user_cell);
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toposort.analyze_loops = false;
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if (debug) {
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log(" Sorting\n");
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log_flush();
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}
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toposort.sort();
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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if (design == nullptr) {
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log_error("No design object");
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return;
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}
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uint32_t threshold_depth = 100;
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bool debug = false;
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size_t argidx;
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std::string abc_script;
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std::string abc_options;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-depth") {
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argidx++;
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threshold_depth = std::stoul(args[argidx], nullptr, 10);
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} else if (args[argidx] == "-debug") {
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debug = true;
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} else if (args[argidx] == "-abc_script") {
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argidx++;
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abc_script = args[argidx];
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} else if (args[argidx] == "-abc_opt") {
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argidx++;
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abc_options = args[argidx];
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} else {
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break;
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}
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}
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extra_args(args, argidx, design);
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if (std::getenv("DEBUG_LONGLOOPS")) {
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debug = true;
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}
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log("Running longloop_select pass\n");
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log_flush();
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// Memorize the existing selection, so the loop over modules still works after "select -none"
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const std::vector<Yosys::RTLIL::Module *> &modules = design->selected_modules();
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// Start with an empty selection, the code below is going to add selection based on loop depth
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Pass::call(design, "select -none");
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for (auto module : modules) {
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if (debug) {
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log("Module %s\n", log_id(module));
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log_flush();
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}
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if (debug) {
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log(" Creating sigmap\n");
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log_flush();
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}
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SigMap sigmap(module);
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std::map<std::string, std::vector<Cell *>> loopIndexCellMap;
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if (debug) {
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log(" Creating sorting datastructures\n");
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log_flush();
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}
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for (auto cell : module->cells()) {
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std::string loopIndex = cell->get_string_attribute("\\in_for_loop");
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if (!loopIndex.empty()) {
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std::map<std::string, std::vector<Cell *>>::iterator itr = loopIndexCellMap.find(loopIndex);
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if (itr == loopIndexCellMap.end()) {
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std::vector<Cell *> cellSet;
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cellSet.push_back(cell);
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loopIndexCellMap.emplace(loopIndex, cellSet);
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} else {
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itr->second.push_back(cell);
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}
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}
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}
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if (!loopIndexCellMap.empty()) {
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log(" Found %ld for-loop clusters in module %s\n", loopIndexCellMap.size(), module->name.c_str());
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log_flush();
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}
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for (std::map<std::string, std::vector<Cell *>>::iterator itrCluster = loopIndexCellMap.begin();
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itrCluster != loopIndexCellMap.end(); itrCluster++) {
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std::string loopInd = itrCluster->first;
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if (itrCluster->second.size() < threshold_depth) {
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if (debug) {
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log(" Skipping loop location %s as it contains only %ld cells\n", loopInd.c_str(),
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itrCluster->second.size());
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log_flush();
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}
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continue;
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}
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if (debug) {
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log(" Analyzing loop location %s containing %ld cells\n", loopInd.c_str(), itrCluster->second.size());
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log_flush();
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}
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// For a given for-loop cell group, perform topological sorting to get the logic depth of the ending cell in
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// the group
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std::map<RTLIL::Cell *, int> celllevel;
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for (auto cell : itrCluster->second) {
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celllevel.emplace(cell, 0);
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}
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TopoSort<RTLIL::Cell *, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> toposort;
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toposorting(itrCluster->second, sigmap, toposort, debug);
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std::vector<Cell *>::reverse_iterator itrLastCell = toposort.sorted.rbegin();
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int logicdepth = 0;
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std::map<RTLIL::Cell *, std::set<RTLIL::Cell *, cell_ptr_cmp>, cell_ptr_cmp> topo_cell_drivers =
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toposort.get_database();
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for (auto cell : toposort.sorted) {
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int level = 0;
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auto itrAdj = topo_cell_drivers.find(cell);
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for (auto c : (*itrAdj).second) {
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level = std::max(level, celllevel[c]);
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}
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level++;
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celllevel[cell] = level;
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logicdepth = std::max(logicdepth, level);
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}
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if (debug) {
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log(" Logic depth: %d\n", logicdepth);
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log_flush();
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}
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if (logicdepth > (int)threshold_depth) {
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log(" Selecting %ld cells in for-loop location %s of depth %d ending with cell %s\n",
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itrCluster->second.size(), loopInd.c_str(), logicdepth, log_id((*itrLastCell)));
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log_flush();
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std::string src_info = (*itrLastCell)->get_src_attribute();
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if (!(*itrLastCell)->get_string_attribute("\\in_for_loop").empty()) {
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src_info = (*itrLastCell)->get_string_attribute("\\in_for_loop");
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}
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// Select all cells in the loop cluster
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if (!abc_script.empty()) {
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// If an ABC script is provided, select on a per-loop basis
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Pass::call(design, "select -none");
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}
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for (auto cell : itrCluster->second) {
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if (debug) {
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log(" Selecting: %s\n", cell->name.c_str());
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log_flush();
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}
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design->select(module, cell);
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if (cell->get_string_attribute("\\in_for_loop").empty()) {
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cell->set_string_attribute("\\in_for_loop", src_info);
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} else {
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src_info = cell->get_string_attribute("\\in_for_loop");
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}
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}
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if (!abc_script.empty()) {
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std::string command = "abc -map_src " + src_info + " -script " + abc_script;
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log(" Executing: %s\n", command.c_str());
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log_flush();
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Pass::call(design, command);
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} else if (!abc_options.empty()) {
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abc_options.erase(std::remove(abc_options.begin(), abc_options.end(), '"'), abc_options.end());
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std::string command = "abc -map_src " + src_info + " " + abc_options;
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log(" Executing: %s\n", command.c_str());
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log_flush();
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Pass::call(design, command);
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}
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}
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}
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}
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log("End longloop_select pass\n");
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log_flush();
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}
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} LongLoopSelect;
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PRIVATE_NAMESPACE_END
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