mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-30 19:22:31 +00:00
Code Activity

Rename minor things in opt_share

Browse source
This commit is contained in:
Akash Levy 2025-03-05 06:17:41 -08:00
parent 7c1cb53c85
commit fce2f2676d
1 changed files with 7 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

13
passes/opt/opt_share.cc
View file

@ -172,6 +172,7 @@ ExtSigSpec decode_port(RTLIL::Cell *cell, RTLIL::IdString port_name, const SigMa
void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<OpMuxConn> &ports, const ExtSigSpec &operand, const SigMap &sigmap)
{
Cell *cell = mux; // SILIMATE: Improve the naming
std::vector<ExtSigSpec> muxed_operands;
int max_width = 0;
for (const auto& p : ports) {
@ -196,7 +197,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
for (auto &operand : muxed_operands) {
operand.sig.extend_u0(max_width, operand.is_signed);
if (operand.sign != muxed_operands[0].sign)
operand = ExtSigSpec(module->Neg(NEW_ID, operand.sig, operand.is_signed));
operand = ExtSigSpec(module->Neg(NEW_ID2_SUFFIX("neg"), operand.sig, operand.is_signed)); // SILIMATE: Improve the naming
}
for (const auto& p : ports) {
@ -219,7 +220,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
RTLIL::SigSpec shared_pmux_s;
// Make a new wire to avoid false equivalence with whatever the former shared output was connected to.
Wire *new_out = module->addWire(NEW_ID, conn_op_offset + conn_width);
Wire *new_out = module->addWire(NEW_ID2_SUFFIX("new_out"), conn_op_offset + conn_width); // SILIMATE: Improve the naming
SigSpec new_sig_out = SigSpec(new_out, conn_op_offset, conn_width);
for (int i = 0; i < GetSize(ports); i++) {
@ -241,14 +242,14 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
SigSpec mux_to_oper;
if (GetSize(shared_pmux_s) == 1) {
mux_to_oper = module->Mux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
mux_to_oper = module->Mux(NEW_ID2_SUFFIX("mux"), shared_pmux_a, shared_pmux_b, shared_pmux_s); // SILIMATE: Improve the naming
} else {
mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
mux_to_oper = module->Pmux(NEW_ID2_SUFFIX("pmux"), shared_pmux_a, shared_pmux_b, shared_pmux_s); // SILIMATE: Improve the naming
}
if (shared_op->type.in(ID($alu))) {
shared_op->setPort(ID::X, module->addWire(NEW_ID, GetSize(new_out)));
shared_op->setPort(ID::CO, module->addWire(NEW_ID, GetSize(new_out)));
shared_op->setPort(ID::X, module->addWire(NEW_ID2_SUFFIX("X"), GetSize(new_out))); // SILIMATE: Improve the naming
shared_op->setPort(ID::CO, module->addWire(NEW_ID2_SUFFIX("CO"), GetSize(new_out))); // SILIMATE: Improve the naming
}
bool is_fine = shared_op->type.in(FINE_BITWISE_OPS);