diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index bf9569d99..681015999 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -172,6 +172,7 @@ ExtSigSpec decode_port(RTLIL::Cell *cell, RTLIL::IdString port_name, const SigMa
 
 void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<OpMuxConn> &ports, const ExtSigSpec &operand, const SigMap &sigmap)
 {
+	Cell *cell = mux; // SILIMATE: Improve the naming
 	std::vector<ExtSigSpec> muxed_operands;
 	int max_width = 0;
 	for (const auto& p : ports) {
@@ -196,7 +197,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
 	for (auto &operand : muxed_operands) {
 		operand.sig.extend_u0(max_width, operand.is_signed);
 		if (operand.sign != muxed_operands[0].sign)
-			operand = ExtSigSpec(module->Neg(NEW_ID, operand.sig, operand.is_signed));
+			operand = ExtSigSpec(module->Neg(NEW_ID2_SUFFIX("neg"), operand.sig, operand.is_signed)); // SILIMATE: Improve the naming
 	}
 
 	for (const auto& p : ports) {
@@ -219,7 +220,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
 	RTLIL::SigSpec shared_pmux_s;
 
 	// Make a new wire to avoid false equivalence with whatever the former shared output was connected to.
-	Wire *new_out = module->addWire(NEW_ID, conn_op_offset + conn_width);
+	Wire *new_out = module->addWire(NEW_ID2_SUFFIX("new_out"), conn_op_offset + conn_width); // SILIMATE: Improve the naming
 	SigSpec new_sig_out = SigSpec(new_out, conn_op_offset, conn_width);
 
 	for (int i = 0; i < GetSize(ports); i++) {
@@ -241,14 +242,14 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
 
 	SigSpec mux_to_oper;
 	if (GetSize(shared_pmux_s) == 1) {
-		mux_to_oper = module->Mux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
+		mux_to_oper = module->Mux(NEW_ID2_SUFFIX("mux"), shared_pmux_a, shared_pmux_b, shared_pmux_s); // SILIMATE: Improve the naming
 	} else {
-		mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
+		mux_to_oper = module->Pmux(NEW_ID2_SUFFIX("pmux"), shared_pmux_a, shared_pmux_b, shared_pmux_s); // SILIMATE: Improve the naming
 	}
 
 	if (shared_op->type.in(ID($alu))) {
-		shared_op->setPort(ID::X, module->addWire(NEW_ID, GetSize(new_out)));
-		shared_op->setPort(ID::CO, module->addWire(NEW_ID, GetSize(new_out)));
+		shared_op->setPort(ID::X, module->addWire(NEW_ID2_SUFFIX("X"), GetSize(new_out))); // SILIMATE: Improve the naming
+		shared_op->setPort(ID::CO, module->addWire(NEW_ID2_SUFFIX("CO"), GetSize(new_out))); // SILIMATE: Improve the naming
 	}
 
 	bool is_fine = shared_op->type.in(FINE_BITWISE_OPS);