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https://github.com/YosysHQ/yosys
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Activity info and rename cmd
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parent
88ff296657
commit
fc63cd7f58
1 changed files with 22 additions and 5 deletions
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@ -28,6 +28,7 @@ struct ActivityProp {
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Module *module;
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Module *module;
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SigMap sigmap;
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SigMap sigmap;
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uint32_t nbBitsWithActivity = 0;
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uint32_t nbBitsWithActivity = 0;
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uint32_t wireCount = 0;
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// Split a string based on separator, returns a vector of tokens as reference argument
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// Split a string based on separator, returns a vector of tokens as reference argument
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// If skipEmpty is true, return "" for string " ", when separator is " "
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// If skipEmpty is true, return "" for string " ", when separator is " "
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@ -66,7 +67,14 @@ struct ActivityProp {
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std::map<SigBit, std::string> ActivityMap;
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std::map<SigBit, std::string> ActivityMap;
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std::map<SigBit, std::string> DutyMap;
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std::map<SigBit, std::string> DutyMap;
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// Build {signal bit - activity} map from the wire activities calculated in the sim pass
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// Build {signal bit - activity} map from the wire activities calculated in the sim pass
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bool debug = false;
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if (std::getenv("DEBUG_ACTIVITY_PROP")) {
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debug = true;
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}
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int localActivity = 0;
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for (Wire *wire : module->wires()) {
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for (Wire *wire : module->wires()) {
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wireCount++;
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SigSpec sig(sigmap(wire));
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SigSpec sig(sigmap(wire));
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// Retrieve the activity/dutycycle attributes created in the sim pass, attached to wires, in the form:
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// Retrieve the activity/dutycycle attributes created in the sim pass, attached to wires, in the form:
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// $ACKT: 0.1 0.2 .... (Each bit in a bus has its own activity, index 0 of the bus is left most)
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// $ACKT: 0.1 0.2 .... (Each bit in a bus has its own activity, index 0 of the bus is left most)
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@ -83,14 +91,20 @@ struct ActivityProp {
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ActivityMap.emplace(bit, activities[i]);
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ActivityMap.emplace(bit, activities[i]);
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DutyMap.emplace(bit, duties[i]);
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DutyMap.emplace(bit, duties[i]);
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nbBitsWithActivity++;
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nbBitsWithActivity++;
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localActivity++;
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if (debug)
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log("Found activity for module: %s, wire: %s, wire_size: %d, activity: %s\n", module->name.c_str(), wire->name.c_str(), GetSize(sig), act.c_str());
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} else {
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} else {
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log_warning("Zeroing out activity for module: %s, wire: %s, wire_size: %d, activ_size: %ld\n",
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if (debug)
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module->name.c_str(), wire->name.c_str(), GetSize(sig), activities.size());
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log_warning("Zeroing out activity for module: %s, wire: %s, wire_size: %d, activ_size: %ld\n",
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module->name.c_str(), wire->name.c_str(), GetSize(sig), activities.size());
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ActivityMap.emplace(bit, "0.0");
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ActivityMap.emplace(bit, "0.0");
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DutyMap.emplace(bit, "0.0");
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DutyMap.emplace(bit, "0.0");
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}
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}
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}
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}
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}
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}
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if (localActivity)
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log("Collected %d bits with activity in module %s out of %d wires\n", localActivity, module->name.c_str(), wireCount);
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// Attach port activity to cell using sigmap
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// Attach port activity to cell using sigmap
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for (auto cell : module->cells()) {
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for (auto cell : module->cells()) {
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std::string cell_ports_activity;
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std::string cell_ports_activity;
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@ -136,6 +150,7 @@ struct ActivityProp {
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}
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}
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uint32_t getNbBitsWithActivity() { return nbBitsWithActivity; }
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uint32_t getNbBitsWithActivity() { return nbBitsWithActivity; }
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uint32_t getWireCount() { return wireCount; }
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};
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};
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struct ActivityClear {
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struct ActivityClear {
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@ -174,11 +189,13 @@ struct ActivityPropPass : public Pass {
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}
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}
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extra_args(args, argidx, design);
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extra_args(args, argidx, design);
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uint32_t totalNbBitsWithActivity = 0;
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uint32_t totalNbBitsWithActivity = 0;
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for (auto module : design->modules()) {
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uint32_t wireCount = 0;
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for (auto module : design->selected_modules()) {
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ActivityProp worker(module);
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ActivityProp worker(module);
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totalNbBitsWithActivity += worker.getNbBitsWithActivity();
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totalNbBitsWithActivity += worker.getNbBitsWithActivity();
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wireCount += worker.getWireCount();
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}
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}
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log("Collected %d bits with activity\n", totalNbBitsWithActivity);
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log("Collected %d bits in total with activity out of %d wires\n", totalNbBitsWithActivity, wireCount);
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log_flush();
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log_flush();
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}
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}
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} ActivityPropPass;
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} ActivityPropPass;
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@ -203,7 +220,7 @@ struct ActivityClearPass : public Pass {
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}
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}
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extra_args(args, argidx, design);
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extra_args(args, argidx, design);
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for (auto module : design->modules()) {
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for (auto module : design->selected_modules()) {
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ActivityClear worker(module);
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ActivityClear worker(module);
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}
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}
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}
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}
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