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ice40: add support for both 1364.1 and LSE RAM/ROM attributes.

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This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
  * LSE supports both `syn_ramstyle` and `syn_romstyle`.
  * Synplify only supports `syn_ramstyle`, with same values as LSE.
  * Synplify also supports `syn_rw_conflict_logic`, which is not
    documented as supported for LSE.

Limitations of the Yosys implementation:
  * LSE/Synplify appear to interpret attribute values insensitive
    to case. There is currently no way to do this in Yosys (attrmap
    can only change case of attribute names).
  * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
    syntax to turn off insertion of transparency logic. There is
    currently no way to support multiple valued attributes in
    memory_bram. It is also not clear if that is a good idea, since
    it can cause sim/synth mismatches.
  * LSE/Synplify/1364.1 support block ROM inference from full case
    statements. Yosys does not currently perform this transformation.
  * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
    from the module to the inner memories. There is currently no way
    to do this in Yosys (attrmvcp only works on cells and wires).
This commit is contained in:
whitequark 2020-01-01 06:18:53 +00:00
parent 29d130dee9
commit fc28bf55aa
4 changed files with 239 additions and 21 deletions
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61
techlibs/ice40/brams.txt
View file

@ -28,13 +28,72 @@ bram $__ICE40_RAM4K_M123
clkpol 2 3
endbram
# The syn_* attributes are described in:
# https://www.latticesemi.com/-/media/LatticeSemi/Documents/Tutorials/AK/LatticeDiamondTutorial311.ashx
match $__ICE40_RAM4K_M0
# implicitly requested RAM or ROM
attribute !syn_ramstyle syn_ramstyle=auto
attribute !syn_romstyle syn_romstyle=auto
attribute !ram_block
attribute !rom_block
attribute !logic_block
min efficiency 2
make_transp
or_next_if_better
endmatch
match $__ICE40_RAM4K_M0
# explicitly requested RAM
attribute syn_ramstyle=block_ram ram_block
attribute !syn_romstyle
attribute !rom_block
attribute !logic_block
min wports 1
make_transp
or_next_if_better
endmatch
match $__ICE40_RAM4K_M0
# explicitly requested ROM
attribute syn_romstyle=ebr rom_block
attribute !syn_ramstyle
attribute !ram_block
attribute !logic_block
max wports 0
make_transp
or_next_if_better
endmatch
match $__ICE40_RAM4K_M123
# implicitly requested RAM or ROM
attribute !syn_ramstyle syn_ramstyle=auto
attribute !syn_romstyle syn_romstyle=auto
attribute !ram_block
attribute !rom_block
attribute !logic_block
min efficiency 2
make_transp
or_next_if_better
endmatch
match $__ICE40_RAM4K_M123
min efficiency 2
# explicitly requested RAM
attribute syn_ramstyle=block_ram ram_block
attribute !syn_romstyle
attribute !rom_block
attribute !logic_block
min wports 1
make_transp
or_next_if_better
endmatch
match $__ICE40_RAM4K_M123
# explicitly requested ROM
attribute syn_romstyle=ebr rom_block
attribute !syn_ramstyle
attribute !ram_block
attribute !logic_block
max wports 0
make_transp
endmatch