mirror of
https://github.com/YosysHQ/yosys
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fc28bf55aa
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
* LSE supports both `syn_ramstyle` and `syn_romstyle`.
* Synplify only supports `syn_ramstyle`, with same values as LSE.
* Synplify also supports `syn_rw_conflict_logic`, which is not
documented as supported for LSE.
Limitations of the Yosys implementation:
* LSE/Synplify appear to interpret attribute values insensitive
to case. There is currently no way to do this in Yosys (attrmap
can only change case of attribute names).
* LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
syntax to turn off insertion of transparency logic. There is
currently no way to support multiple valued attributes in
memory_bram. It is also not clear if that is a good idea, since
it can cause sim/synth mismatches.
* LSE/Synplify/1364.1 support block ROM inference from full case
statements. Yosys does not currently perform this transformation.
* LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
from the module to the inner memories. There is currently no way
to do this in Yosys (attrmvcp only works on cells and wires).
99 lines
1.9 KiB
Text
99 lines
1.9 KiB
Text
bram $__ICE40_RAM4K_M0
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init 1
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abits 8
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dbits 16
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groups 2
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ports 1 1
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wrmode 0 1
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enable 1 16
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transp 0 0
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clocks 2 3
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clkpol 2 3
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endbram
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bram $__ICE40_RAM4K_M123
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init 1
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abits 9 @M1
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dbits 8 @M1
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abits 10 @M2
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dbits 4 @M2
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abits 11 @M3
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dbits 2 @M3
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groups 2
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ports 1 1
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wrmode 0 1
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enable 1 1
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transp 0 0
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clocks 2 3
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clkpol 2 3
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endbram
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# The syn_* attributes are described in:
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# https://www.latticesemi.com/-/media/LatticeSemi/Documents/Tutorials/AK/LatticeDiamondTutorial311.ashx
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match $__ICE40_RAM4K_M0
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# implicitly requested RAM or ROM
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attribute !syn_ramstyle syn_ramstyle=auto
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attribute !syn_romstyle syn_romstyle=auto
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attribute !ram_block
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attribute !rom_block
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attribute !logic_block
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min efficiency 2
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make_transp
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or_next_if_better
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endmatch
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match $__ICE40_RAM4K_M0
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# explicitly requested RAM
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attribute syn_ramstyle=block_ram ram_block
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attribute !syn_romstyle
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attribute !rom_block
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attribute !logic_block
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min wports 1
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make_transp
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or_next_if_better
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endmatch
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match $__ICE40_RAM4K_M0
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# explicitly requested ROM
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attribute syn_romstyle=ebr rom_block
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attribute !syn_ramstyle
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attribute !ram_block
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attribute !logic_block
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max wports 0
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make_transp
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or_next_if_better
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endmatch
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match $__ICE40_RAM4K_M123
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# implicitly requested RAM or ROM
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attribute !syn_ramstyle syn_ramstyle=auto
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attribute !syn_romstyle syn_romstyle=auto
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attribute !ram_block
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attribute !rom_block
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attribute !logic_block
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min efficiency 2
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make_transp
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or_next_if_better
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endmatch
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match $__ICE40_RAM4K_M123
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# explicitly requested RAM
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attribute syn_ramstyle=block_ram ram_block
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attribute !syn_romstyle
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attribute !rom_block
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attribute !logic_block
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min wports 1
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make_transp
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or_next_if_better
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endmatch
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match $__ICE40_RAM4K_M123
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# explicitly requested ROM
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attribute syn_romstyle=ebr rom_block
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attribute !syn_ramstyle
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attribute !ram_block
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attribute !logic_block
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max wports 0
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make_transp
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endmatch
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