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WIP merging synth phases with example

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Replace `typical_phases.rst` and `examples.rst` with a single `example_synth.rst`.
Also updating the counter example to match.

Aims to reduce redundancy, and simplify the getting started section.
Details on things like `proc`, `memory` and `fsm` should instead be in the advanced section (under the new `synth` subsection).
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Krystine Sherwin 2023-12-07 13:04:46 +13:00
parent bad8dba2cd
commit f9ce3d1c26
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9
docs/source/code_examples/intro/counter_outputs.ys
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@ -1,12 +1,13 @@
# read design
# read
read_verilog counter.v
hierarchy -check -top counter
show -notitle -format dot -prefix counter_00
# the high-level stuff
proc; opt; memory; opt; fsm; opt
# elaborate
proc
show -notitle -format dot -prefix counter_proc
opt
show -notitle -format dot -prefix counter_01
# mapping to internal cell library