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https://github.com/YosysHQ/yosys
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f9ce3d1c26
Replace `typical_phases.rst` and `examples.rst` with a single `example_synth.rst`. Also updating the counter example to match. Aims to reduce redundancy, and simplify the getting started section. Details on things like `proc`, `memory` and `fsm` should instead be in the advanced section (under the new `synth` subsection).
29 lines
537 B
Plaintext
29 lines
537 B
Plaintext
# read
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read_verilog counter.v
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hierarchy -check -top counter
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show -notitle -format dot -prefix counter_00
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# elaborate
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proc
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show -notitle -format dot -prefix counter_proc
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opt
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show -notitle -format dot -prefix counter_01
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# mapping to internal cell library
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techmap; opt
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splitnets -ports;;
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show -notitle -format dot -prefix counter_02
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# mapping flip-flops to mycells.lib
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dfflibmap -liberty mycells.lib
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# mapping logic to mycells.lib
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abc -liberty mycells.lib
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# cleanup
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clean
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show -notitle -lib mycells.v -format dot -prefix counter_03
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