mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-02 12:37:53 +00:00
Fix comments
This commit is contained in:
parent
9224b3bc17
commit
f9906eed68
8 changed files with 11 additions and 10 deletions
|
|
@ -2,4 +2,5 @@ read_verilog memory.v
|
|||
synth_ice40
|
||||
cd top
|
||||
select -assert-count 1 t:SB_RAM40_4K
|
||||
select -assert-none t:SB_RAM40_4K %% t:* %D
|
||||
write_verilog memory_synth.v
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue