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cleanup in le tests

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This commit is contained in:
Artur Swiderski 2020-11-03 00:35:35 +01:00
parent f7dc93c652
commit f8bcb78a32
14 changed files with 69 additions and 173 deletions
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4
tests/arch/intel_le/logic.ys
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@ -1,7 +1,7 @@
read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclonev # equivalency check
equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
@ -15,7 +15,7 @@ design -reset
read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclone10gx # equivalency check
equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneive # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module