diff --git a/techlibs/intel_le/synth_intel_le.cc b/techlibs/intel_le/synth_intel_le.cc
index dc3cd8ce8..d85495327 100644
--- a/techlibs/intel_le/synth_intel_le.cc
+++ b/techlibs/intel_le/synth_intel_le.cc
@@ -208,8 +208,6 @@ struct SynthIntelLEPass : public ScriptPass {
 
 		if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
 			run(stringf("memory_bram -rules +/intel_le/common/bram_%s.txt", bram_type.c_str()));
-			if (help_mode || bram_type != "m9k")
-				run(stringf("techmap -map +/intel_le/common/bram_%s_map.v", bram_type.c_str()));
 		}
 
 		if (check_label("map_ffram")) {
diff --git a/tests/arch/intel_le/add_sub.ys b/tests/arch/intel_le/add_sub.ys
index ac75935b7..da0f2bcb5 100644
--- a/tests/arch/intel_le/add_sub.ys
+++ b/tests/arch/intel_le/add_sub.ys
@@ -1,18 +1,21 @@
 read_verilog ../common/add_sub.v
 hierarchy -top top
-equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclonev # equivalency check
+equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 stat
 select -assert-count 8 t:MISTRAL_ALUT_ARITH
-select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
+select -assert-count 4 t:MISTRAL_NOT
+select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH  %% t:* %D
+
 
 design -reset
 read_verilog ../common/add_sub.v
 hierarchy -top top
-equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneive # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 stat
 select -assert-count 8 t:MISTRAL_ALUT_ARITH
-select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
+select -assert-count 4 t:MISTRAL_NOT
+select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH  %% t:* %D
diff --git a/tests/arch/intel_le/adffs.ys b/tests/arch/intel_le/adffs.ys
index ec0085d65..2fb313696 100644
--- a/tests/arch/intel_le/adffs.ys
+++ b/tests/arch/intel_le/adffs.ys
@@ -3,7 +3,7 @@ design -save read
 
 hierarchy -top adff
 proc
-equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclonev # equivalency check
+equiv_opt -async2sync -assert -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneiv # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adff # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -15,7 +15,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
 design -load read
 hierarchy -top adff
 proc
-equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclone10gx # equivalency check
+equiv_opt -async2sync -assert -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneive # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adff # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -27,7 +27,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
 design -load read
 hierarchy -top adffn
 proc
-equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclonev # equivalency check
+equiv_opt -async2sync -assert -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneiv # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adffn # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -38,7 +38,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D
 design -load read
 hierarchy -top adffn
 proc
-equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclone10gx # equivalency check
+equiv_opt -async2sync -assert -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneive # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adffn # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -49,7 +49,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D
 design -load read
 hierarchy -top dffs
 proc
-equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclonev # equivalency check
+equiv_opt -async2sync -assert -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneiv # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -61,7 +61,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 %% t:* %D
 design -load read
 hierarchy -top dffs
 proc
-equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclone10gx # equivalency check
+equiv_opt -async2sync -assert -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneive # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -73,7 +73,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 %% t:* %D
 design -load read
 hierarchy -top ndffnr
 proc
-equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclonev # equivalency check
+equiv_opt -async2sync -assert -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneiv # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd ndffnr # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -85,7 +85,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
 design -load read
 hierarchy -top ndffnr
 proc
-equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclone10gx # equivalency check
+equiv_opt -async2sync -assert -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneive # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd ndffnr # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
diff --git a/tests/arch/intel_le/blockram.ys b/tests/arch/intel_le/blockram.ys
index ce7502571..8d260dbc3 100644
--- a/tests/arch/intel_le/blockram.ys
+++ b/tests/arch/intel_le/blockram.ys
@@ -1,6 +1,6 @@
 read_verilog ../common/blockram.v
-chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 10 sync_ram_sdp
-synth_intel_le -family cyclonev
+chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 9 sync_ram_sdp
+synth_intel_le -family cycloneiv
 cd sync_ram_sdp
-select -assert-count 1 t:MISTRAL_M10K
-select -assert-none t:MISTRAL_M10K %% t:* %D
+select -assert-count 1 t:MISTRAL_M9K
+select -assert-none t:MISTRAL_M9K %% t:* %D
diff --git a/tests/arch/intel_le/counter.ys b/tests/arch/intel_le/counter.ys
index 147b3d4c0..d0a7b1f2d 100644
--- a/tests/arch/intel_le/counter.ys
+++ b/tests/arch/intel_le/counter.ys
@@ -2,7 +2,7 @@ read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -async2sync -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclonev # equivalency check
+equiv_opt -async2sync -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneiv # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
@@ -13,11 +13,12 @@ select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D
 
 
 design -reset
+
 read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -async2sync -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclone10gx # equivalency check
+equiv_opt -async2sync -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneive # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
diff --git a/tests/arch/intel_le/dffs.ys b/tests/arch/intel_le/dffs.ys
index 484e4b7ba..89db9e16f 100644
--- a/tests/arch/intel_le/dffs.ys
+++ b/tests/arch/intel_le/dffs.ys
@@ -3,7 +3,7 @@ design -save read
 
 hierarchy -top dff
 proc
-equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclonev # equivalency check
+equiv_opt -async2sync -assert -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneiv # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dff # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -13,7 +13,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D
 design -load read
 hierarchy -top dff
 proc
-equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclone10gx # equivalency check
+equiv_opt -async2sync -assert -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneive # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dff # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -24,7 +24,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D
 design -load read
 hierarchy -top dffe
 proc
-equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclonev # equivalency check
+equiv_opt -async2sync -assert -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneiv # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -35,7 +35,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D
 design -load read
 hierarchy -top dffe
 proc
-equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclone10gx # equivalency check
+equiv_opt -async2sync -assert -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneive # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
diff --git a/tests/arch/intel_le/fsm.ys b/tests/arch/intel_le/fsm.ys
index 0bccaf549..f2b3d631a 100644
--- a/tests/arch/intel_le/fsm.ys
+++ b/tests/arch/intel_le/fsm.ys
@@ -3,7 +3,7 @@ hierarchy -top fsm
 proc
 flatten
 
-equiv_opt -run :prove -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclonev
+equiv_opt -run :prove -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneiv
 async2sync
 miter -equiv -make_assert -flatten gold gate miter
 sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
@@ -13,12 +13,10 @@ cd fsm # Constrain all select calls below inside the top module
 
 select -assert-count 6 t:MISTRAL_FF
 select -assert-max 1 t:MISTRAL_NOT
-select -assert-max 2 t:MISTRAL_ALUT2 # Clang returns 2, GCC returns 1
+select -assert-max 5 t:MISTRAL_ALUT2 # 
 select -assert-max 1 t:MISTRAL_ALUT3
-select -assert-max 2 t:MISTRAL_ALUT4 # Clang returns 0, GCC returns 1
-select -assert-max 6 t:MISTRAL_ALUT5 # Clang returns 5, GCC returns 4
-select -assert-max 2 t:MISTRAL_ALUT6 # Clang returns 1, GCC returns 2
-select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
+select -assert-max 9 t:MISTRAL_ALUT4 # 
+select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D
 
 design -reset
 read_verilog ../common/fsm.v
@@ -26,7 +24,7 @@ hierarchy -top fsm
 proc
 flatten
 
-equiv_opt -run :prove -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclone10gx
+equiv_opt -run :prove -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneive
 async2sync
 miter -equiv -make_assert -flatten gold gate miter
 sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
@@ -36,9 +34,7 @@ cd fsm # Constrain all select calls below inside the top module
 
 select -assert-count 6 t:MISTRAL_FF
 select -assert-max 1 t:MISTRAL_NOT
-select -assert-max 2 t:MISTRAL_ALUT2 # Clang returns 2, GCC returns 1
-select -assert-max 2 t:MISTRAL_ALUT3 # Clang returns 2, GCC returns 1
-select -assert-max 2 t:MISTRAL_ALUT4 # Clang returns 0, GCC returns 1
-select -assert-max 6 t:MISTRAL_ALUT5 # Clang returns 5, GCC returns 4
-select -assert-max 2 t:MISTRAL_ALUT6 # Clang returns 1, GCC returns 2
-select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
+select -assert-max 5 t:MISTRAL_ALUT2 # 
+select -assert-max 1 t:MISTRAL_ALUT3
+select -assert-max 9 t:MISTRAL_ALUT4 # 
+select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D
diff --git a/tests/arch/intel_le/logic.ys b/tests/arch/intel_le/logic.ys
index 689c9908f..1184558b7 100644
--- a/tests/arch/intel_le/logic.ys
+++ b/tests/arch/intel_le/logic.ys
@@ -1,7 +1,7 @@
 read_verilog ../common/logic.v
 hierarchy -top top
 proc
-equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclonev # equivalency check
+equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
@@ -15,7 +15,7 @@ design -reset
 read_verilog ../common/logic.v
 hierarchy -top top
 proc
-equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneive # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
diff --git a/tests/arch/intel_le/lutram.ys b/tests/arch/intel_le/lutram.ys
deleted file mode 100644
index f08bb1c7c..000000000
--- a/tests/arch/intel_le/lutram.ys
+++ /dev/null
@@ -1,41 +0,0 @@
-read_verilog ../common/lutram.v
-hierarchy -top lutram_1w1r
-proc
-memory -nomap
-equiv_opt -run :prove -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v -map +/intel_le/common/mem_sim.v synth_intel_le -family cyclonev -nobram
-memory
-opt -full
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
-
-design -load postopt
-cd lutram_1w1r
-select -assert-count 16 t:MISTRAL_MLAB
-select -assert-count 1 t:MISTRAL_NOT
-select -assert-count 2 t:MISTRAL_ALUT2
-select -assert-count 8 t:MISTRAL_ALUT3
-select -assert-count 17 t:MISTRAL_FF
-select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
-
-
-design -reset
-read_verilog ../common/lutram.v
-hierarchy -top lutram_1w1r
-proc
-memory -nomap
-equiv_opt -run :prove -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v -map +/intel_le/common/mem_sim.v synth_intel_le -family cyclonev -nobram
-memory
-opt -full
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
-
-design -load postopt
-cd lutram_1w1r
-select -assert-count 16 t:MISTRAL_MLAB
-select -assert-count 1 t:MISTRAL_NOT
-select -assert-count 2 t:MISTRAL_ALUT2
-select -assert-count 8 t:MISTRAL_ALUT3
-select -assert-count 17 t:MISTRAL_FF
-select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
diff --git a/tests/arch/intel_le/mul.ys b/tests/arch/intel_le/mul.ys
deleted file mode 100644
index e0b8e8142..000000000
--- a/tests/arch/intel_le/mul.ys
+++ /dev/null
@@ -1,60 +0,0 @@
-read_verilog ../common/mul.v
-chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
-hierarchy -top top
-proc
-equiv_opt -assert -map +/intel_le/common/dsp_sim.v synth_intel_le -family cyclonev # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-select -assert-count 1 t:MISTRAL_MUL9X9
-select -assert-none t:MISTRAL_MUL9X9 %% t:* %D
-
-# Cyclone 10 GX does not have 9x9 multipliers.
-
-design -reset
-read_verilog ../common/mul.v
-chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34
-hierarchy -top top
-proc
-equiv_opt -assert -map +/intel_le/common/dsp_sim.v synth_intel_le -family cyclonev # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-select -assert-count 1 t:MISTRAL_MUL18X18
-select -assert-none t:MISTRAL_MUL18X18 %% t:* %D
-
-design -reset
-read_verilog ../common/mul.v
-chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34
-hierarchy -top top
-proc
-equiv_opt -assert -map +/intel_le/common/dsp_sim.v synth_intel_le -family cyclone10gx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-select -assert-count 1 t:MISTRAL_MUL18X18
-select -assert-none t:MISTRAL_MUL18X18 %% t:* %D
-
-design -reset
-read_verilog ../common/mul.v
-chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52
-hierarchy -top top
-proc
-equiv_opt -assert -map +/intel_le/common/dsp_sim.v synth_intel_le -family cyclonev # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-select -assert-count 1 t:MISTRAL_MUL27X27
-select -assert-none t:MISTRAL_MUL27X27 %% t:* %D
-
-design -reset
-read_verilog ../common/mul.v
-chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52
-hierarchy -top top
-proc
-equiv_opt -assert -map +/intel_le/common/dsp_sim.v synth_intel_le -family cyclone10gx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-select -assert-count 1 t:MISTRAL_MUL27X27
-select -assert-none t:MISTRAL_MUL27X27 %% t:* %D
diff --git a/tests/arch/intel_le/mux.ys b/tests/arch/intel_le/mux.ys
index 67bdabae1..f5afafeb3 100644
--- a/tests/arch/intel_le/mux.ys
+++ b/tests/arch/intel_le/mux.ys
@@ -4,7 +4,7 @@ design -save read
 
 hierarchy -top mux2
 proc
-equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclonev # equivalency check
+equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux2 # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_ALUT3
@@ -14,7 +14,7 @@ select -assert-none t:MISTRAL_ALUT3 %% t:* %D
 design -load read
 hierarchy -top mux2
 proc
-equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneive # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux2 # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_ALUT3
@@ -24,65 +24,64 @@ select -assert-none t:MISTRAL_ALUT3 %% t:* %D
 design -load read
 hierarchy -top mux4
 proc
-equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclonev # equivalency check
+equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_ALUT6
-select -assert-none t:MISTRAL_ALUT6 %% t:* %D
+select -assert-count 3 t:MISTRAL_ALUT3
+select -assert-none t:MISTRAL_ALUT3 %% t:* %D
 
 
 design -load read
 hierarchy -top mux4
 proc
-equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneive # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_ALUT6
-select -assert-none t:MISTRAL_ALUT6 %% t:* %D
+select -assert-count 3 t:MISTRAL_ALUT3
+select -assert-none t:MISTRAL_ALUT3 %% t:* %D
 
 
 design -load read
 hierarchy -top mux8
 proc
-equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclonev # equivalency check
+equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_ALUT3
-select -assert-count 2 t:MISTRAL_ALUT6
-select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D
+select -assert-count 3 t:MISTRAL_ALUT3
+select -assert-count 3 t:MISTRAL_ALUT4
+select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D
 
 
 design -load read
 hierarchy -top mux8
 proc
-equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneive # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_ALUT3
-select -assert-count 2 t:MISTRAL_ALUT6
-select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D
+select -assert-count 3 t:MISTRAL_ALUT3
+select -assert-count 3 t:MISTRAL_ALUT4
+select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D
 
 
 design -load read
 hierarchy -top mux16
 proc
-equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclonev # equivalency check
+equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_ALUT3
-select -assert-max 2 t:MISTRAL_ALUT5
-select -assert-max 5 t:MISTRAL_ALUT6
-select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
+select -assert-count 1 t:MISTRAL_ALUT2
+select -assert-max 6 t:MISTRAL_ALUT3
+select -assert-max 7 t:MISTRAL_ALUT4
+select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D
 
 
 design -load read
 hierarchy -top mux16
 proc
-equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneive # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_ALUT3
-select -assert-count 2 t:MISTRAL_ALUT5
-select -assert-count 4 t:MISTRAL_ALUT6
-
-select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
+select -assert-count 1 t:MISTRAL_ALUT2
+select -assert-max 6 t:MISTRAL_ALUT3
+select -assert-max 7 t:MISTRAL_ALUT4
+select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D
diff --git a/tests/arch/intel_le/quartus_ice.ys b/tests/arch/intel_le/quartus_ice.ys
index 0f15f4d86..1855fbcb6 100644
--- a/tests/arch/intel_le/quartus_ice.ys
+++ b/tests/arch/intel_le/quartus_ice.ys
@@ -8,7 +8,7 @@ module top();
 endmodule
 EOT
 
-synth_intel_le -family cyclonev -quartus
+synth_intel_le -family cycloneiv -quartus
 select -assert-none w:*[* w:*]*
 
 design -reset
@@ -22,5 +22,5 @@ module top();
 endmodule
 EOT
 
-synth_intel_le -family cyclone10gx -quartus
+synth_intel_le -family cycloneive -quartus
 select -assert-none w:*[* w:*]*
diff --git a/tests/arch/intel_le/shifter.ys b/tests/arch/intel_le/shifter.ys
index fb7b99c73..059f593d5 100644
--- a/tests/arch/intel_le/shifter.ys
+++ b/tests/arch/intel_le/shifter.ys
@@ -2,7 +2,7 @@ read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclonev # equivalency check
+equiv_opt -async2sync -assert -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneiv # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 8 t:MISTRAL_FF
@@ -14,7 +14,7 @@ read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclone10gx # equivalency check
+equiv_opt -async2sync -assert -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneive # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 8 t:MISTRAL_FF
diff --git a/tests/arch/intel_le/tribuf.ys b/tests/arch/intel_le/tribuf.ys
index 2ec25ad6a..40218ddcb 100644
--- a/tests/arch/intel_le/tribuf.ys
+++ b/tests/arch/intel_le/tribuf.ys
@@ -4,7 +4,7 @@ proc
 tribuf
 flatten
 synth
-equiv_opt -assert -map +/simcells.v synth_intel_le -family cyclonev # equivalency check
+equiv_opt -assert -map +/simcells.v synth_intel_le -family cycloneiv # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd tristate # Constrain all select calls below inside the top module
 #Internal cell type used. Need support it.
@@ -19,7 +19,7 @@ proc
 tribuf
 flatten
 synth
-equiv_opt -assert -map +/simcells.v synth_intel_le -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/simcells.v synth_intel_le -family cycloneive # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd tristate # Constrain all select calls below inside the top module
 #Internal cell type used. Need support it.