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Merge branch 'main' into related_load_data

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Arnim Läuger 2026-03-12 16:22:28 +01:00 • committed by GitHub
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226 changed files with 16144 additions and 2736 deletions
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1246
tests/opt/opt_balance_tree.ys Normal file
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File diff suppressed because it is too large Load diff

10
tests/opt/opt_clean_standalone_wires.ys Normal file
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@ -0,0 +1,10 @@
read_rtlil << EOT
module \test
wire \wire_a
wire \wire_f
connect \wire_f \wire_a
end
EOT
opt_clean
select -assert-count 0 */*

56
tests/opt/opt_expr.ys
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@ -319,3 +319,59 @@ check
equiv_opt -assert opt_expr -keepdc
design -load postopt
select -assert-count 1 t:$mul r:A_WIDTH=4 %i r:B_WIDTH=4 %i r:Y_WIDTH=8 %i
###########
design -reset
read_rtlil <<EOF
module \top
wire width 3 input 2 \binary
wire width 32 output 3 \y
cell $pow $0
parameter \A_WIDTH 32
parameter \B_WIDTH 3
parameter \A_SIGNED 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A 2
connect \B \binary
connect \Y \y
end
end
EOF
scratchpad -set opt.did_something false
opt_expr
scratchpad -assert opt.did_something true
sat -verify -set binary 0 -prove y 1
sat -verify -set binary 1 -prove y 2
sat -verify -set binary 2 -prove y 4
sat -verify -set binary 3 -prove y 8
###########
design -reset
read_rtlil <<EOF
module \top
wire width 3 input 2 \binary
wire width 32 output 3 \y
cell $pow $0
parameter \A_WIDTH 2
parameter \B_WIDTH 3
parameter \A_SIGNED 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A 2'10
connect \B \binary
connect \Y \y
end
end
EOF
scratchpad -set opt.did_something false
opt_expr
scratchpad -assert opt.did_something false

41
tests/opt/opt_expr_combined_assign.ys
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@ -1,11 +1,12 @@
read_verilog -sv <<EOT
module opt_expr_or_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0;
wire[8:0] a;
initial begin
a = 8'b0;
a |= i;
a |= j;
end
assign o = a;
assign o = a;
endmodule
EOT
proc
@ -17,12 +18,13 @@ select -assert-count 1 t:$or r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
design -reset
read_verilog -sv <<EOT
module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0;
wire[8:0] a;
initial begin
a += i;
a += j;
a = 8'b0;
a += i;
a += j;
end
assign o = a;
assign o = a;
endmodule
EOT
proc
@ -34,12 +36,13 @@ select -assert-count 1 t:$add r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
design -reset
read_verilog -sv <<EOT
module opt_expr_xor_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0;
wire[8:0] a;
initial begin
a ^= i;
a ^= j;
a = 8'b0;
a ^= i;
a ^= j;
end
assign o = a;
assign o = a;
endmodule
EOT
proc
@ -51,12 +54,13 @@ select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
design -reset
read_verilog -sv <<EOT
module opt_expr_sub_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0;
wire[8:0] a;
initial begin
a -= i;
a -= j;
a = 8'b0;
a -= i;
a -= j;
end
assign o = a;
assign o = a;
endmodule
EOT
proc
@ -68,12 +72,13 @@ select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
design -reset
read_verilog -sv <<EOT
module opt_expr_and_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b11111111;
wire[8:0] a;
initial begin
a &= i;
a &= j;
a = 8'b11111111;
a &= i;
a &= j;
end
assign o = a;
assign o = a;
endmodule
EOT
proc

2
tests/opt/opt_hier.tcl
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@ -27,7 +27,7 @@ foreach fn [glob opt_hier_*.v] {
design -copy-from gate -as gate A:top
yosys rename -hide
equiv_make gold gate equiv
equiv_induct equiv
equiv_induct -ignore-unknown-cells equiv
equiv_status -assert equiv
log -pop