From 214d09a8c6a4280ef45d436f97412411861a56b6 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 27 Nov 2025 14:57:02 +0100 Subject: [PATCH 001/291] .github: everything that triggers on main or PRs should trigger on merge queue commit --- .github/workflows/extra-builds.yml | 1 + .github/workflows/prepare-docs.yml | 2 +- .github/workflows/test-build.yml | 1 + .github/workflows/test-compile.yml | 1 + .github/workflows/test-sanitizers.yml | 1 + .github/workflows/test-verific.yml | 1 + 6 files changed, 6 insertions(+), 1 deletion(-) diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml index b22a399db..5a2454fd4 100644 --- a/.github/workflows/extra-builds.yml +++ b/.github/workflows/extra-builds.yml @@ -5,6 +5,7 @@ on: push: branches: - main + merge_group: # test PRs pull_request: # allow triggering tests, ignores skip check diff --git a/.github/workflows/prepare-docs.yml b/.github/workflows/prepare-docs.yml index f19b1c7af..e3d917942 100644 --- a/.github/workflows/prepare-docs.yml +++ b/.github/workflows/prepare-docs.yml @@ -1,6 +1,6 @@ name: Build docs artifact with Verific -on: [push, pull_request] +on: [push, pull_request, merge_group] jobs: check_docs_rebuild: diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index 8c1a3bbd2..ab6eb3148 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -5,6 +5,7 @@ on: push: branches: - main + merge_group: # test PRs pull_request: # allow triggering tests, ignores skip check diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml index 31c8bccf6..000d1c400 100644 --- a/.github/workflows/test-compile.yml +++ b/.github/workflows/test-compile.yml @@ -5,6 +5,7 @@ on: push: branches: - main + merge_group: # test PRs pull_request: # allow triggering tests, ignores skip check diff --git a/.github/workflows/test-sanitizers.yml b/.github/workflows/test-sanitizers.yml index 4c8e3ec51..11a339cd3 100644 --- a/.github/workflows/test-sanitizers.yml +++ b/.github/workflows/test-sanitizers.yml @@ -5,6 +5,7 @@ on: push: branches: - main + merge_group: # ignore PRs due to time needed # allow triggering tests, ignores skip check workflow_dispatch: diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml index 6619e1124..adc6f59d8 100644 --- a/.github/workflows/test-verific.yml +++ b/.github/workflows/test-verific.yml @@ -5,6 +5,7 @@ on: push: branches: - main + merge_group: # test PRs pull_request: # allow triggering tests, ignores skip check From 436a247d60c970015564de7a39e466ea3926d7e8 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Dec 2025 19:48:32 +0100 Subject: [PATCH 002/291] Shuffle around information about bug reports and contributions --- .github/ISSUE_TEMPLATE/bug_report.yml | 2 + CONTRIBUTING.md | 60 ++++++----- .../extending_yosys/contributing.rst | 99 +++++++++++-------- 3 files changed, 86 insertions(+), 75 deletions(-) diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml index f754d16c7..2c1483345 100644 --- a/.github/ISSUE_TEMPLATE/bug_report.yml +++ b/.github/ISSUE_TEMPLATE/bug_report.yml @@ -6,6 +6,8 @@ body: attributes: value: > + Learn more [here](https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/extending_yosys/contributing.html#reporting-bugs) about how to report bugs. We fix well-reported bugs the fastest. + If you have a general question, please ask it on the [Discourse forum](https://yosyshq.discourse.group/). diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 403292b0b..9ce09c013 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -1,41 +1,44 @@ -# Introduction +# Contributing to Yosys -Thanks for thinking about contributing to the Yosys project. If this is your +Thanks for considering helping out. If this is your first time contributing to an open source project, please take a look at the -following guide: +following guide about the basics: https://opensource.guide/how-to-contribute/#orienting-yourself-to-a-new-project. -Information about the Yosys coding style is available on our Read the Docs: -https://yosys.readthedocs.io/en/latest/yosys_internals/extending_yosys/contributing.html. +## Asking questions -# Using the issue tracker +If you have a question about how to use Yosys, please ask on our [Discourse forum](https://yosyshq.discourse.group/). +The Discourse is also a great place to ask questions about developing or +contributing to Yosys. + +We have open [dev 'jour fixe' (JF) meetings](https://docs.google.com/document/d/1SapA6QAsJcsgwsdKJDgnGR2mr97pJjV4eeXg_TVJhRU/edit?usp=sharing) where developers from YosysHQ and the +community come together to discuss open issues and PRs. This is also a good +place to talk to us about how to implement larger PRs. + +## Using the issue tracker The [issue tracker](https://github.com/YosysHQ/yosys/issues) is used for tracking bugs or other problems with Yosys or its documentation. It is also the place to go for requesting new features. -When [creating a new issue](https://github.com/YosysHQ/yosys/issues/new/choose), -we have a few templates available. Please make use of these! It will make it -much easier for someone to respond and help. ### Bug reports -Before you submit an issue, please check out the [how-to guide for -`bugpoint`](https://yosys.readthedocs.io/en/latest/using_yosys/bugpoint.html). -This guide will take you through the process of using the [`bugpoint` -command](https://yosys.readthedocs.io/en/latest/cmd/bugpoint.html) in Yosys to -produce a [minimal, complete and verifiable -example](https://stackoverflow.com/help/minimal-reproducible-example) (MVCE). -Providing an MVCE with your bug report drastically increases the likelihood that -someone will be able to help resolve your issue. +Learn more [here](https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/extending_yosys/contributing.html#reporting-bugs) about how to report bugs. We fix well-reported bugs the fastest. +## Contributing code -# Using pull requests +### Using pull requests If you are working on something to add to Yosys, or fix something that isn't -working quite right, make a [PR](https://github.com/YosysHQ/yosys/pulls)! An -open PR, even as a draft, tells everyone that you're working on it and they -don't have to. It can also be a useful way to solicit feedback on in-progress -changes. See below to find the best way to [ask us +working quite right, +make a [pull request (PR)](https://github.com/YosysHQ/yosys/pulls). + +If you're adding complex functionality, or modifying core parts of yosys, +we highly recommend discussing your motivation and approach +ahead of time on the [Discourse forum](https://yosyshq.discourse.group/). +An open PR, even as a draft, tells everyone that you're working on it and they +don't have to. It can also be a useful way to solicit feedback on in-progress +changes. See below to find the best way to [ask us questions](#asking-questions). In general, all changes to the code are done as a PR, with [Continuous @@ -53,18 +56,11 @@ work under a range of compilers, settings, and targets. We use [labels](https://github.com/YosysHQ/yosys/labels) to help categorise issues and PRs. If a label seems relevant to your work, please do add it; this -also includes the labels beggining with 'status-'. The 'merge-' labels are used +also includes the labels beginning with 'status-'. The 'merge-' labels are used by maintainers for tracking and communicating which PRs are ready and pending merge; please do not use these labels if you are not a maintainer. -# Asking questions +### Coding style -If you have a question about how to use Yosys, please ask on our [Discourse forum](https://yosyshq.discourse.group/) or in our [discussions -page](https://github.com/YosysHQ/yosys/discussions). -The Discourse is also a great place to ask questions about developing or -contributing to Yosys. - -We have open [dev 'jour fixe' (JF) meetings](https://docs.google.com/document/d/1SapA6QAsJcsgwsdKJDgnGR2mr97pJjV4eeXg_TVJhRU/edit?usp=sharing) where developers from YosysHQ and the -community come together to discuss open issues and PRs. This is also a good -place to talk to us about how to implement larger PRs. +Learn more [here](https://yosys.readthedocs.io/en/latest/yosys_internals/extending_yosys/contributing.html). diff --git a/docs/source/yosys_internals/extending_yosys/contributing.rst b/docs/source/yosys_internals/extending_yosys/contributing.rst index 70170fc48..1907832f1 100644 --- a/docs/source/yosys_internals/extending_yosys/contributing.rst +++ b/docs/source/yosys_internals/extending_yosys/contributing.rst @@ -1,14 +1,6 @@ Contributing to Yosys ===================== -.. note:: - - For information on making a pull request on github, refer to our - |CONTRIBUTING|_ file. - -.. |CONTRIBUTING| replace:: :file:`CONTRIBUTING.md` -.. _CONTRIBUTING: https://github.com/YosysHQ/yosys/blob/main/CONTRIBUTING.md - Coding Style ------------ @@ -47,11 +39,13 @@ Use range-based for loops whenever applicable. Reporting bugs -------------- -- use the `bug report template`_ +A good bug report includes the following information: -.. _bug report template: https://github.com/YosysHQ/yosys/issues/new?template=bug_report.yml -- short title briefly describing the issue, e.g. +Title +~~~~~ + +briefly describe the issue, for example: techmap of wide mux with undefined inputs raises error during synth_xilinx @@ -64,10 +58,18 @@ Reporting bugs Reproduction Steps ~~~~~~~~~~~~~~~~~~ -- ideally a code-block (starting and ending with triple backquotes) containing - the minimized design (Verilog or RTLIL), followed by a code-block containing - the minimized yosys script OR a command line call to yosys with - code-formatting (starting and ending with single backquotes) +The reproduction steps should be a minimal, complete and verifiable +example `MVCE`_. +Providing an MVCE with your bug report drastically increases the likelihood that +someone will be able to help resolve your issue. +One way to minimize a design is to use the `bugpoint_` command. +You can learn more in the `how-to guide for bugpoint_`. + +The reproduction steps are ideally a code-block (starting and ending with +triple backquotes) containing +the minimized design (Verilog or RTLIL), followed by a code-block containing +the minimized yosys script OR a command line call to yosys with +code-formatting (starting and ending with single backquotes). .. code-block:: markdown @@ -86,9 +88,9 @@ Reproduction Steps `yosys -p ': minimum sequence of commands;' min.v` -- alternatively can provide a single code-block which includes the minimized - design as a "here document" followed by the sequence of commands which - reproduce the error +Alternatively, you can provide a single code-block which includes the minimized +design as a "here document" followed by the sequence of commands which +reproduce the error + see :doc:`/using_yosys/more_scripting/load_design` for more on heredocs. @@ -101,7 +103,9 @@ Reproduction Steps # minimum sequence of commands ``` -- any environment variables or command line options should also be mentioned +Don't forget to mention: + +- any important environment variables or command line options - if the problem occurs for a range of values/designs, what is that range - if you're using an external tool, such as ``valgrind``, to detect the issue, what version of that tool are you using and what options are you giving it @@ -115,24 +119,31 @@ Reproduction Steps around Yosys such as OpenLane; you should instead minimize your input and reproduction steps to just the Yosys part. -"Expected Behaviour" -~~~~~~~~~~~~~~~~~~~~ +.. _MVCE: https://stackoverflow.com/help/minimal-reproducible-example +.. _bugpoint: https://yosys.readthedocs.io/en/latest/cmd/bugpoint.html +.. _how-to guide for bugpoint: https://yosys.readthedocs.io/en/latest/using_yosys/bugpoint.html -- if you have a similar design/script that doesn't give the error, include it - here as a reference -- if the bug is that an error *should* be raised but isn't, are there any other - commands with similar error messages - - -"Actual Behaviour" +Expected Behaviour ~~~~~~~~~~~~~~~~~~ -- any error messages go here +Describe what you'd expect to happen when we follow the reproduction steps +if the bug was fixed. + +If you have a similar design/script that doesn't give the error, include it +here as a reference. If the bug is that an error *should* be raised but isn't, +note if there are any other commands with similar error messages. + + +Actual Behaviour +~~~~~~~~~~~~~~~~ + +Describe what you actually see when you follow the reproduction steps. + +This can include: +- any error messages - any details relevant to the crash that were found with ``--trace`` or ``--debug`` flags -- if you identified the point of failure in the source code, you could mention - it here, or as a comment below - +- the part of the source code that triggers the bug + if possible, use a permalink to the source on GitHub + you can browse the source repository for a certain commit with the failure and open the source file, select the relevant lines (click on the line @@ -145,16 +156,19 @@ Reproduction Steps source specified, with a link to the source file at the given commit -Additional details +Additional Details ~~~~~~~~~~~~~~~~~~ -- once you have created the issue, any additional details can be added as a - comment on that issue -- could include any additional context as to what you were doing when you first - encountered the bug -- was this issue discovered through the use of a fuzzer -- if you've minimized the script, consider including the `bugpoint` script you - used, or the original script, e.g. +Anything else you think might be helpful or relevant when verifying or fixing +the bug. + +Once you have created the issue, any additional details can be added as a +comment on that issue. You can include any additional context as to what you +were doing when you first encountered the bug. + +If this issue discovered through the use of a fuzzer, ALWAYS declare that. +If you've minimized the script, consider including the `bugpoint` script you +used, or the original script, for example: .. code-block:: markdown @@ -171,8 +185,7 @@ Additional details Minimized from `yosys -p ': original sequence of commands to produce error;' design.v` -- if you're able to, it may also help to share the original un-minimized design - - + if the design is too big for a comment, consider turning it into a `Gist`_ +If possible, it may also help to share the original un-minimized design. +If the design is too big for a comment, consider turning it into a `Gist`_ .. _Gist: https://gist.github.com/ From 6778151207880f4639b67627c7e73307e23859f2 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Dec 2025 22:32:51 +0100 Subject: [PATCH 003/291] CONTRIBUTING: simplify CI description --- CONTRIBUTING.md | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 9ce09c013..c51cc9a68 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -41,16 +41,20 @@ don't have to. It can also be a useful way to solicit feedback on in-progress changes. See below to find the best way to [ask us questions](#asking-questions). -In general, all changes to the code are done as a PR, with [Continuous -Integration (CI)](https://github.com/YosysHQ/yosys/actions) tools that -automatically run the full suite of tests compiling and running Yosys. Please -make use of this! If you're adding a feature: add a test! Not only does it +### Continuous integration + +[Continuous Integration (CI)](https://github.com/YosysHQ/yosys/actions) tools +automatically compile Yosys and run it with the full suite of tests. +If you're a first time contributor, a maintainer has to trigger a run for you. +We test on various platforms, compilers. Sanitizer builds are only tested +on the main branch. + + ### Labels From 9c9f4f347e6e95496c13096cd5a4d255371a0718 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 3 Dec 2025 01:48:57 +0100 Subject: [PATCH 004/291] README: mention docs can be read offline --- README.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README.md b/README.md index 427d59c9e..3b2f41768 100644 --- a/README.md +++ b/README.md @@ -246,6 +246,8 @@ Building the documentation Note that there is no need to build the manual if you just want to read it. Simply visit https://yosys.readthedocs.io/en/latest/ instead. +If you're offline, you can read the sources, replacing `.../en/latest` +with `docs/source`. In addition to those packages listed above for building Yosys from source, the following are used for building the website: From e2dffbf991f6464ee6494d1d69d16143aab703dd Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 3 Dec 2025 01:49:15 +0100 Subject: [PATCH 005/291] contributing: move to docs, expand --- CONTRIBUTING.md | 17 +- .../extending_yosys/contributing.rst | 167 ++++++++++++++---- 2 files changed, 137 insertions(+), 47 deletions(-) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index c51cc9a68..6eadbec31 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -27,19 +27,19 @@ Learn more [here](https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_ ## Contributing code +If you're adding complex functionality, or modifying core parts of Yosys, +we highly recommend discussing your motivation and approach +ahead of time on the [Discourse forum](https://yosyshq.discourse.group/). + ### Using pull requests If you are working on something to add to Yosys, or fix something that isn't working quite right, make a [pull request (PR)](https://github.com/YosysHQ/yosys/pulls). -If you're adding complex functionality, or modifying core parts of yosys, -we highly recommend discussing your motivation and approach -ahead of time on the [Discourse forum](https://yosyshq.discourse.group/). An open PR, even as a draft, tells everyone that you're working on it and they don't have to. It can also be a useful way to solicit feedback on in-progress -changes. See below to find the best way to [ask us -questions](#asking-questions). +changes. See above to find the best way to [ask us questions](#asking-questions). ### Continuous integration @@ -49,13 +49,6 @@ If you're a first time contributor, a maintainer has to trigger a run for you. We test on various platforms, compilers. Sanitizer builds are only tested on the main branch. - - ### Labels We use [labels](https://github.com/YosysHQ/yosys/labels) to help categorise diff --git a/docs/source/yosys_internals/extending_yosys/contributing.rst b/docs/source/yosys_internals/extending_yosys/contributing.rst index 1907832f1..6b8b4aa40 100644 --- a/docs/source/yosys_internals/extending_yosys/contributing.rst +++ b/docs/source/yosys_internals/extending_yosys/contributing.rst @@ -1,41 +1,6 @@ Contributing to Yosys ===================== -Coding Style ------------- - -Formatting of code -~~~~~~~~~~~~~~~~~~ - -- Yosys code is using tabs for indentation. Tabs are 8 characters. - -- A continuation of a statement in the following line is indented by two - additional tabs. - -- Lines are as long as you want them to be. A good rule of thumb is to break - lines at about column 150. - -- Opening braces can be put on the same or next line as the statement opening - the block (if, switch, for, while, do). Put the opening brace on its own line - for larger blocks, especially blocks that contains blank lines. - -- Otherwise stick to the `Linux Kernel Coding Style`_. - -.. _Linux Kernel Coding Style: https://www.kernel.org/doc/Documentation/process/coding-style.rst - - -C++ Language -~~~~~~~~~~~~ - -Yosys is written in C++17. - -In general Yosys uses ``int`` instead of ``size_t``. To avoid compiler warnings -for implicit type casts, always use ``GetSize(foobar)`` instead of -``foobar.size()``. (``GetSize()`` is defined in :file:`kernel/yosys.h`) - -Use range-based for loops whenever applicable. - - Reporting bugs -------------- @@ -189,3 +154,135 @@ If possible, it may also help to share the original un-minimized design. If the design is too big for a comment, consider turning it into a `Gist`_ .. _Gist: https://gist.github.com/ + +Contributing code +----------------- + +Code that matters +~~~~~~~~~~~~~~~~~ + +If you're adding complex functionality, or modifying core parts of yosys, +we highly recommend discussing your motivation and approach +ahead of time on the `Discourse forum`_. + +Before you build or fix something, search for existing `issues`_. + +.. _`Discourse forum`: https://yosyshq.discourse.group/ +.. _`issues`: https://github.com/YosysHQ/yosys/issues + +Making sense +~~~~~~~~~~~~ + +Given enough effort, the behavior of any code can be figured out to any +desired extent. However, the author of the code is by far in the best +position to make this as easy as possible. + +Yosys is a long-standing project and has accumulated a lot of C-style code +that's not written to be read, just written to run. We improve this bit +by bit when opportunities arise, but it is what it is. +New additions are expected to be a lot cleaner. + +Your change should contain exactly what it needs. This means: + +- nothing more than that - no dead code etc +- nothing missing + +Here are some software engineering approaches that help: + +- Use abstraction to model the problem and hide details + - Maximize the usage of types (structs over loose variables), + not necessarily in an object-oriented way + - Use functions, scopes, type aliases +- In new passes, make sure the logic behind how and why it works is actually provided + in coherent comments, and that variable and type naming is consistent with the terms + you use in the description. +- The logic of the implementation should be described in mathematical + or algorithm theory terms. Why would a non-trivial loop be guaranteed to terminate? + Is there some variant? Are you re-implementing a classic data structure from logic + synthesis? +- There's various ways of traversing the design with use-def indices (for getting + drivers and driven signals) available in Yosys. They have advantages and sometimes + disadvantages. Prefer not re-implementing these +- Prefer references over pointers, and smart pointers over raw pointers +- Aggressively deduplicate code. Within functions, within passes, + across passes, even against existing code +- Refactor and document existing code if you touch it, + but in separate commits from your functional changes +- Prefer smaller commits organized by good chunks. Git has a lot of features + like fixup commits, interactive rebase with autosquash +- Prefer declaring things ``const`` +- Prefer range-based for loops over C-style + +Common mistakes +~~~~~~~~~~~~~~~ + +.. - Pointer invalidation when erasing design objects on a module while iterating +.. TODO figure out how it works again and describe it +- Iterating over an entire design and checking if things are selected is more +inefficient than using the ``selected_*`` methods +- Remember to call ``fixup_ports`` at the end if you're modifying module interfaces + +Testing your change +~~~~~~~~~~~~~~~~~~~ + +Untested code can't be maintained. Inevitable codebase-wide changes +are likely to break anything untested. Tests also help reviewers understand +the purpose of the code change in practice. + +Your code needs to come with tests. If it's a feature, a test that covers +representative examples of the added behavior. If it's a bug fix, it should +reproduce the original isolated bug. But in some situations, adding a test +isn't viable. If you can't provide a test, explain this decision. + +Prefer writing unit tests (:file:`tests/unit`) for isolated tests to +the internals of more serious code changes, like those to the core of yosys, +or more algorithmic ones. + +The rest of the test suite is mostly based on running Yosys on various Yosys +and Tcl scripts that manually call Yosys commands. +See :doc:`/yosys_internals/extending_yosys/test_suites` for more information +about how our test suite is structured. +The basic test writing approach is checking +for the presence of some kind of object or pattern with ``-assert-count`` in +:doc:`docs/source/using_yosys/more_scripting/selections.rst`. + +It's often best to use equivalence checking with ``equiv_opt -assert`` +or similar to prove that the changes done to the design by a modified pass +preserve equivalence. But some code isn't meant to preserve equivalence. +Sometimes proving equivalence takes an impractically long time for larger +inputs. + +.. Changes to core parts of Yosys or passes that are included in synthesis flows +.. can change runtime and memory usage - for the better or for worse. This strongly +.. depends on the design involved. Such risky changes should then be benchmarked +.. with various designs. + +.. TODO Emil benchmarking + +Coding style +~~~~~~~~~~~~ + +Yosys is written in C++17. + +In general Yosys uses ``int`` instead of ``size_t``. To avoid compiler warnings +for implicit type casts, always use ``GetSize(foobar)`` instead of +``foobar.size()``. (``GetSize()`` is defined in :file:`kernel/yosys.h`) + +For auto formatting code, a :file:`.clang-format` file is present top-level. +Yosys code is using tabs for indentation. A continuation of a statement +in the following line is indented by two additional tabs. Lines are +as long as you want them to be. A good rule of thumb is to break lines +at about column 150. Opening braces can be put on the same or next line +as the statement opening the block (if, switch, for, while, do). +Put the opening brace on its own line for larger blocks, especially +blocks that contains blank lines. Remove trailing whitespace on sight. +Remember to keep formatting-only commits separate from functional ones. +Otherwise stick to the `Linux Kernel Coding Style`_. + +.. _Linux Kernel Coding Style: https://www.kernel.org/doc/Documentation/process/coding-style.rst + + +.. Reviewing PRs +.. ------------- + +.. TODO Emil review process From 2843ea3008a620c3ba824e66bba6026225369b42 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 3 Dec 2025 13:10:20 +0100 Subject: [PATCH 006/291] contributing: fix rst --- .../extending_yosys/contributing.rst | 55 ++++++++++--------- 1 file changed, 30 insertions(+), 25 deletions(-) diff --git a/docs/source/yosys_internals/extending_yosys/contributing.rst b/docs/source/yosys_internals/extending_yosys/contributing.rst index 6b8b4aa40..6515e9a28 100644 --- a/docs/source/yosys_internals/extending_yosys/contributing.rst +++ b/docs/source/yosys_internals/extending_yosys/contributing.rst @@ -105,19 +105,21 @@ Actual Behaviour Describe what you actually see when you follow the reproduction steps. This can include: -- any error messages -- any details relevant to the crash that were found with ``--trace`` or + +* any error messages +* any details relevant to the crash that were found with ``--trace`` or ``--debug`` flags -- the part of the source code that triggers the bug - + if possible, use a permalink to the source on GitHub - + you can browse the source repository for a certain commit with the failure +* the part of the source code that triggers the bug + + * if possible, use a permalink to the source on GitHub + * you can browse the source repository for a certain commit with the failure and open the source file, select the relevant lines (click on the line number for the first relevant line, then while holding shift click on the line number for the last relevant line), click on the ``...`` that appears and select "Copy permalink" - + should look something like + * should look something like ``https://github.com/YosysHQ/yosys/blob//path/to/file#L139-L147`` - + clicking on "Preview" should reveal a code block containing the lines of + * clicking on "Preview" should reveal a code block containing the lines of source specified, with a link to the source file at the given commit @@ -184,43 +186,46 @@ New additions are expected to be a lot cleaner. Your change should contain exactly what it needs. This means: -- nothing more than that - no dead code etc -- nothing missing +* nothing more than that - no dead code etc +* nothing missing Here are some software engineering approaches that help: -- Use abstraction to model the problem and hide details - - Maximize the usage of types (structs over loose variables), +* Use abstraction to model the problem and hide details + + * Maximize the usage of types (structs over loose variables), not necessarily in an object-oriented way - - Use functions, scopes, type aliases -- In new passes, make sure the logic behind how and why it works is actually provided + * Use functions, scopes, type aliases + +* In new passes, make sure the logic behind how and why it works is actually provided in coherent comments, and that variable and type naming is consistent with the terms you use in the description. -- The logic of the implementation should be described in mathematical +* The logic of the implementation should be described in mathematical or algorithm theory terms. Why would a non-trivial loop be guaranteed to terminate? Is there some variant? Are you re-implementing a classic data structure from logic synthesis? -- There's various ways of traversing the design with use-def indices (for getting +* There's various ways of traversing the design with use-def indices (for getting drivers and driven signals) available in Yosys. They have advantages and sometimes disadvantages. Prefer not re-implementing these -- Prefer references over pointers, and smart pointers over raw pointers -- Aggressively deduplicate code. Within functions, within passes, +* Prefer references over pointers, and smart pointers over raw pointers +* Aggressively deduplicate code. Within functions, within passes, across passes, even against existing code -- Refactor and document existing code if you touch it, +* Refactor and document existing code if you touch it, but in separate commits from your functional changes -- Prefer smaller commits organized by good chunks. Git has a lot of features +* Prefer smaller commits organized by good chunks. Git has a lot of features like fixup commits, interactive rebase with autosquash -- Prefer declaring things ``const`` -- Prefer range-based for loops over C-style +* Prefer declaring things ``const`` +* Prefer range-based for loops over C-style Common mistakes ~~~~~~~~~~~~~~~ .. - Pointer invalidation when erasing design objects on a module while iterating .. TODO figure out how it works again and describe it -- Iterating over an entire design and checking if things are selected is more -inefficient than using the ``selected_*`` methods -- Remember to call ``fixup_ports`` at the end if you're modifying module interfaces + +* Iterating over an entire design and checking if things are selected is more + inefficient than using the ``selected_*`` methods +* Remember to call ``fixup_ports`` at the end if you're modifying module interfaces Testing your change ~~~~~~~~~~~~~~~~~~~ @@ -244,7 +249,7 @@ See :doc:`/yosys_internals/extending_yosys/test_suites` for more information about how our test suite is structured. The basic test writing approach is checking for the presence of some kind of object or pattern with ``-assert-count`` in -:doc:`docs/source/using_yosys/more_scripting/selections.rst`. +:doc:`/using_yosys/more_scripting/selections`. It's often best to use equivalence checking with ``equiv_opt -assert`` or similar to prove that the changes done to the design by a modified pass From 518610bbc4b0587e531e3149f70645614e588290 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 4 Dec 2025 17:26:51 +0100 Subject: [PATCH 007/291] contributing: split out git style --- .../extending_yosys/contributing.rst | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/docs/source/yosys_internals/extending_yosys/contributing.rst b/docs/source/yosys_internals/extending_yosys/contributing.rst index 6515e9a28..109bfe9b0 100644 --- a/docs/source/yosys_internals/extending_yosys/contributing.rst +++ b/docs/source/yosys_internals/extending_yosys/contributing.rst @@ -210,10 +210,6 @@ Here are some software engineering approaches that help: * Prefer references over pointers, and smart pointers over raw pointers * Aggressively deduplicate code. Within functions, within passes, across passes, even against existing code -* Refactor and document existing code if you touch it, - but in separate commits from your functional changes -* Prefer smaller commits organized by good chunks. Git has a lot of features - like fixup commits, interactive rebase with autosquash * Prefer declaring things ``const`` * Prefer range-based for loops over C-style @@ -281,11 +277,22 @@ at about column 150. Opening braces can be put on the same or next line as the statement opening the block (if, switch, for, while, do). Put the opening brace on its own line for larger blocks, especially blocks that contains blank lines. Remove trailing whitespace on sight. -Remember to keep formatting-only commits separate from functional ones. + Otherwise stick to the `Linux Kernel Coding Style`_. .. _Linux Kernel Coding Style: https://www.kernel.org/doc/Documentation/process/coding-style.rst +Git style +~~~~~~~~~ + +We don't have a strict commit message style. + +Some style hints: + +* Refactor and document existing code if you touch it, + but in separate commits from your functional changes +* Prefer smaller commits organized by good chunks. Git has a lot of features + like fixup commits, interactive rebase with autosquash .. Reviewing PRs .. ------------- From 16a420afee756f10c2b291e3d06c62563b1eb8f4 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Fri, 5 Dec 2025 12:16:14 +0100 Subject: [PATCH 008/291] contributing: clarify some things --- .../extending_yosys/contributing.rst | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/docs/source/yosys_internals/extending_yosys/contributing.rst b/docs/source/yosys_internals/extending_yosys/contributing.rst index 109bfe9b0..4d1a74b2f 100644 --- a/docs/source/yosys_internals/extending_yosys/contributing.rst +++ b/docs/source/yosys_internals/extending_yosys/contributing.rst @@ -184,10 +184,14 @@ that's not written to be read, just written to run. We improve this bit by bit when opportunities arise, but it is what it is. New additions are expected to be a lot cleaner. -Your change should contain exactly what it needs. This means: +The purpose and behavior of the code changed should be described clearly. +Your change should contain exactly what it needs to match that description. +This means: -* nothing more than that - no dead code etc -* nothing missing +* nothing more than that - no dead code, no undocumented features +* nothing missing - if something is partially built, that's fine, + but you have to make that clear. For example, some passes + only support some types of cells Here are some software engineering approaches that help: @@ -251,7 +255,8 @@ It's often best to use equivalence checking with ``equiv_opt -assert`` or similar to prove that the changes done to the design by a modified pass preserve equivalence. But some code isn't meant to preserve equivalence. Sometimes proving equivalence takes an impractically long time for larger -inputs. +inputs. Also beware, the ``equiv_`` passes are a bit quirky and might even +have incorrect results in unusual situations. .. Changes to core parts of Yosys or passes that are included in synthesis flows .. can change runtime and memory usage - for the better or for worse. This strongly @@ -270,7 +275,8 @@ for implicit type casts, always use ``GetSize(foobar)`` instead of ``foobar.size()``. (``GetSize()`` is defined in :file:`kernel/yosys.h`) For auto formatting code, a :file:`.clang-format` file is present top-level. -Yosys code is using tabs for indentation. A continuation of a statement +Yosys code is using tabs for indentation. A tab is 8 characters wide, +but prefer not relying on it. A continuation of a statement in the following line is indented by two additional tabs. Lines are as long as you want them to be. A good rule of thumb is to break lines at about column 150. Opening braces can be put on the same or next line From 54b278d57496cf771490d1f4d343cff65a078a89 Mon Sep 17 00:00:00 2001 From: Yannick Lamarre Date: Fri, 23 Feb 2024 21:33:14 -0500 Subject: [PATCH 009/291] Add tests for implicit wires in generate blocks. Signed-off-by: Yannick Lamarre --- tests/verilog/genblk_wire.sv | 20 ++++++++++++++++++++ tests/verilog/genblk_wire.ys | 17 +++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 tests/verilog/genblk_wire.sv create mode 100644 tests/verilog/genblk_wire.ys diff --git a/tests/verilog/genblk_wire.sv b/tests/verilog/genblk_wire.sv new file mode 100644 index 000000000..ef95fa98a --- /dev/null +++ b/tests/verilog/genblk_wire.sv @@ -0,0 +1,20 @@ +module gold(a, b); + output wire [1:0] a; + input wire [1:0] b; + genvar i; + for (i = 0; i < 2; i++) begin + wire x; + assign x = b[i]; + assign a[i] = x; + end +endmodule + +module gate(a, b); + output wire [1:0] a; + input wire [1:0] b; + genvar i; + for (i = 0; i < 2; i++) begin + assign x = b[i]; + assign a[i] = x; + end +endmodule diff --git a/tests/verilog/genblk_wire.ys b/tests/verilog/genblk_wire.ys new file mode 100644 index 000000000..582303760 --- /dev/null +++ b/tests/verilog/genblk_wire.ys @@ -0,0 +1,17 @@ +logger -expect warning "Identifier `\\genblk1[[]0[]]\.x' is implicitly declared." 1 +logger -expect warning "Identifier `\\genblk1[[]1[]]\.x' is implicitly declared." 1 +read_verilog -sv genblk_wire.sv +logger -check-expected + +select -assert-count 1 gate/genblk1[0].x +select -assert-count 1 gate/genblk1[1].x +select -assert-count 0 gate/genblk1[2].x + +select -assert-count 1 gold/genblk1[0].x +select -assert-count 1 gold/genblk1[1].x +select -assert-count 0 gold/genblk1[2].x + +proc +equiv_make gold gate equiv +equiv_simple +equiv_status -assert From 9814f9dc4f16c623822a6fd140a1d0c6c8d79a0d Mon Sep 17 00:00:00 2001 From: Yannick Lamarre Date: Fri, 23 Feb 2024 21:42:16 -0500 Subject: [PATCH 010/291] Add autowires in genblk/for expension Signed-off-by: Yannick Lamarre --- frontends/ast/simplify.cc | 88 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 83174e963..f65bf4f24 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -4690,6 +4690,7 @@ void AstNode::expand_genblock(const std::string &prefix) switch (child->type) { case AST_WIRE: + case AST_AUTOWIRE: case AST_MEMORY: case AST_STRUCT: case AST_UNION: @@ -4718,6 +4719,93 @@ void AstNode::expand_genblock(const std::string &prefix) } break; + case AST_IDENTIFIER: + if (!child->str.empty() && prefix.size() > 0) { + bool is_resolved = false; + std::string identifier_str = child->str; + if (current_ast_mod != nullptr && identifier_str.compare(0, current_ast_mod->str.size(), current_ast_mod->str) == 0) { + if (identifier_str.at(current_ast_mod->str.size()) == '.') { + identifier_str = '\\' + identifier_str.substr(current_ast_mod->str.size()+1, identifier_str.size()); + } + } + // search starting in the innermost scope and then stepping outward + for (size_t ppos = prefix.size() - 1; ppos; --ppos) { + if (prefix.at(ppos) != '.') continue; + + std::string new_prefix = prefix.substr(0, ppos + 1); + auto attempt_resolve = [&new_prefix](const std::string &ident) -> std::string { + std::string new_name = prefix_id(new_prefix, ident); + if (current_scope.count(new_name)) + return new_name; + return {}; + }; + + // attempt to resolve the full identifier + std::string resolved = attempt_resolve(identifier_str); + if (!resolved.empty()) { + is_resolved = true; + break; + } + // attempt to resolve hierarchical prefixes within the identifier, + // as the prefix could refer to a local scope which exists but + // hasn't yet been elaborated + for (size_t spos = identifier_str.size() - 1; spos; --spos) { + if (identifier_str.at(spos) != '.') continue; + resolved = attempt_resolve(identifier_str.substr(0, spos)); + if (!resolved.empty()) { + is_resolved = true; + identifier_str = resolved + identifier_str.substr(spos); + ppos = 1; // break outer loop + break; + } + } + if (current_scope.count(identifier_str) == 0) { + AstNode *current_scope_ast = (current_ast_mod == nullptr) ? current_ast : current_ast_mod; + for (auto& node : current_scope_ast->children) { + switch (node->type) { + case AST_PARAMETER: + case AST_LOCALPARAM: + case AST_WIRE: + case AST_AUTOWIRE: + case AST_GENVAR: + case AST_MEMORY: + case AST_FUNCTION: + case AST_TASK: + case AST_DPI_FUNCTION: + if (prefix_id(new_prefix, identifier_str) == node->str) { + is_resolved = true; + current_scope[node->str] = node.get(); + } + break; + case AST_ENUM: + current_scope[node->str] = node.get(); + for (auto& enum_node : node->children) { + log_assert(enum_node->type==AST_ENUM_ITEM); + if (prefix_id(new_prefix, identifier_str) == enum_node->str) { + is_resolved = true; + current_scope[enum_node->str] = enum_node.get(); + } + } + break; + default: + break; + } + } + } + } + if ((current_scope.count(identifier_str) == 0) && is_resolved == false) { + if (current_ast_mod == nullptr) { + input_error("Identifier `%s' is implicitly declared outside of a module.\n", child->str.c_str()); + } else if (flag_autowire || identifier_str == "\\$global_clock") { + auto auto_wire = std::make_unique(child->location, AST_AUTOWIRE); + auto_wire->str = identifier_str; + children.push_back(std::move(auto_wire)); + } else { + input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", identifier_str.c_str()); + } + } + } + break; default: break; } From 5b317ee03c1791b6dfadcb9e2d7c3ef71b5c6332 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 15 Dec 2025 12:08:07 +1300 Subject: [PATCH 011/291] sim.cc: Check eval err Some cells (e.g. $macc_v2) are marked evaluable, but will raise an abort if called with `CellTypes::eval()`. Instead of falling through to the abort, we can pass a pointer to a boolean to check for errors. Use said check to catch `CellTypes::eval()` errors and treat them as unevaluable but otherwise continue. Reflows the series of if checks into `if ... else if ... else` so that we can check for errors and set state in one place. --- passes/sat/sim.cc | 44 ++++++++++++++++++++------------------------ 1 file changed, 20 insertions(+), 24 deletions(-) diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index a29651653..27d6d12c1 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -549,31 +549,27 @@ struct SimInstance if (shared->debug) log("[%s] eval %s (%s)\n", hiername(), log_id(cell), log_id(cell->type)); - // Simple (A -> Y) and (A,B -> Y) cells - if (has_a && !has_c && !has_d && !has_s && has_y) { - set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_b))); - return; - } + bool err = false; + RTLIL::Const eval_state; + if (has_a && !has_c && !has_d && !has_s && has_y) + // Simple (A -> Y) and (A,B -> Y) cells + eval_state = CellTypes::eval(cell, get_state(sig_a), get_state(sig_b), &err); + else if (has_a && has_b && has_c && !has_d && !has_s && has_y) + // (A,B,C -> Y) cells + eval_state = CellTypes::eval(cell, get_state(sig_a), get_state(sig_b), get_state(sig_c), &err); + else if (has_a && !has_b && !has_c && !has_d && has_s && has_y) + // (A,S -> Y) cells + eval_state = CellTypes::eval(cell, get_state(sig_a), get_state(sig_s), &err); + else if (has_a && has_b && !has_c && !has_d && has_s && has_y) + // (A,B,S -> Y) cells + eval_state = CellTypes::eval(cell, get_state(sig_a), get_state(sig_b), get_state(sig_s), &err); + else + err = true; - // (A,B,C -> Y) cells - if (has_a && has_b && has_c && !has_d && !has_s && has_y) { - set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_b), get_state(sig_c))); - return; - } - - // (A,S -> Y) cells - if (has_a && !has_b && !has_c && !has_d && has_s && has_y) { - set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_s))); - return; - } - - // (A,B,S -> Y) cells - if (has_a && has_b && !has_c && !has_d && has_s && has_y) { - set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_b), get_state(sig_s))); - return; - } - - log_warning("Unsupported evaluable cell type: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell)); + if (err) + log_warning("Unsupported evaluable cell type: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell)); + else + set_state(sig_y, eval_state); return; } From 18a7d4c2625ca5f92f64ec4af28e6bca9edfbfe9 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 15 Dec 2025 15:42:41 +1300 Subject: [PATCH 012/291] Document nesting packages as unsupported --- docs/source/using_yosys/verilog.rst | 3 +++ 1 file changed, 3 insertions(+) diff --git a/docs/source/using_yosys/verilog.rst b/docs/source/using_yosys/verilog.rst index a557360b7..ef52bfc25 100644 --- a/docs/source/using_yosys/verilog.rst +++ b/docs/source/using_yosys/verilog.rst @@ -355,6 +355,9 @@ from SystemVerilog: design with `read_verilog`, all its packages are available to SystemVerilog files being read into the same design afterwards. + - nested packages are currently not supported (i.e. calling ``import`` inside + a ``package`` .. ``endpackage`` block) + - typedefs are supported (including inside packages) - type casts are currently not supported From 772d821fb0f68bcf0c2baf321ebd1aa64965fe42 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Fri, 19 Dec 2025 18:30:17 +0100 Subject: [PATCH 013/291] opt_expr: reindent test --- tests/opt/opt_expr_combined_assign.ys | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/tests/opt/opt_expr_combined_assign.ys b/tests/opt/opt_expr_combined_assign.ys index b18923c7b..f84978a0a 100644 --- a/tests/opt/opt_expr_combined_assign.ys +++ b/tests/opt/opt_expr_combined_assign.ys @@ -5,7 +5,7 @@ initial begin a |= i; a |= j; end - assign o = a; + assign o = a; endmodule EOT proc @@ -19,10 +19,10 @@ read_verilog -sv < Date: Fri, 19 Dec 2025 18:32:06 +0100 Subject: [PATCH 014/291] opt_expr: avoid multiple drivers issue #4792 in combined assign tests --- tests/opt/opt_expr_combined_assign.ys | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/tests/opt/opt_expr_combined_assign.ys b/tests/opt/opt_expr_combined_assign.ys index f84978a0a..823ca959a 100644 --- a/tests/opt/opt_expr_combined_assign.ys +++ b/tests/opt/opt_expr_combined_assign.ys @@ -1,7 +1,8 @@ read_verilog -sv < Date: Tue, 16 Dec 2025 01:39:39 +0000 Subject: [PATCH 015/291] Implement design_equal command --- passes/cmds/Makefile.inc | 1 + passes/cmds/design_equal.cc | 352 +++++++++++++++++++++++++++++ tests/various/design_equal_fail.ys | 22 ++ tests/various/design_equal_pass.ys | 17 ++ 4 files changed, 392 insertions(+) create mode 100644 passes/cmds/design_equal.cc create mode 100644 tests/various/design_equal_fail.ys create mode 100644 tests/various/design_equal_pass.ys diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index b1b1383b1..dc12c92c2 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -5,6 +5,7 @@ endif OBJS += passes/cmds/add.o OBJS += passes/cmds/delete.o OBJS += passes/cmds/design.o +OBJS += passes/cmds/design_equal.o OBJS += passes/cmds/select.o OBJS += passes/cmds/show.o OBJS += passes/cmds/viz.o diff --git a/passes/cmds/design_equal.cc b/passes/cmds/design_equal.cc new file mode 100644 index 000000000..a949db9ff --- /dev/null +++ b/passes/cmds/design_equal.cc @@ -0,0 +1,352 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/rtlil.h" + +YOSYS_NAMESPACE_BEGIN + +class ModuleComparator +{ + RTLIL::Module *mod_a; + RTLIL::Module *mod_b; + +public: + ModuleComparator(RTLIL::Module *mod_a, RTLIL::Module *mod_b) : mod_a(mod_a), mod_b(mod_b) {} + + bool compare_sigbit(const RTLIL::SigBit &a, const RTLIL::SigBit &b) + { + if (a.wire == nullptr && b.wire == nullptr) + return a.data == b.data; + if (a.wire != nullptr && b.wire != nullptr) + return a.wire->name == b.wire->name && a.offset == b.offset; + return false; + } + + bool compare_sigspec(const RTLIL::SigSpec &a, const RTLIL::SigSpec &b) + { + if (a.size() != b.size()) return false; + auto it_a = a.begin(), it_b = b.begin(); + for (; it_a != a.end(); ++it_a, ++it_b) { + if (!compare_sigbit(*it_a, *it_b)) return false; + } + return true; + } + + std::string compare_attributes(const RTLIL::AttrObject *a, const RTLIL::AttrObject *b) + { + for (const auto &it : a->attributes) { + if (b->attributes.count(it.first) == 0) + return "missing attribute " + std::string(log_id(it.first)) + " in second design"; + if (it.second != b->attributes.at(it.first)) + return "attribute " + std::string(log_id(it.first)) + " mismatch: " + log_const(it.second) + " != " + log_const(b->attributes.at(it.first)); + } + for (const auto &it : b->attributes) + if (a->attributes.count(it.first) == 0) + return "missing attribute " + std::string(log_id(it.first)) + " in first design"; + return ""; + } + + std::string compare_wires(const RTLIL::Wire *a, const RTLIL::Wire *b) + { + if (a->name != b->name) + return "name mismatch: " + std::string(log_id(a->name)) + " != " + log_id(b->name); + if (a->width != b->width) + return "width mismatch: " + std::to_string(a->width) + " != " + std::to_string(b->width); + if (a->start_offset != b->start_offset) + return "start_offset mismatch: " + std::to_string(a->start_offset) + " != " + std::to_string(b->start_offset); + if (a->port_id != b->port_id) + return "port_id mismatch: " + std::to_string(a->port_id) + " != " + std::to_string(b->port_id); + if (a->port_input != b->port_input) + return "port_input mismatch: " + std::to_string(a->port_input) + " != " + std::to_string(b->port_input); + if (a->port_output != b->port_output) + return "port_output mismatch: " + std::to_string(a->port_output) + " != " + std::to_string(b->port_output); + if (a->upto != b->upto) + return "upto mismatch: " + std::to_string(a->upto) + " != " + std::to_string(b->upto); + if (a->is_signed != b->is_signed) + return "is_signed mismatch: " + std::to_string(a->is_signed) + " != " + std::to_string(b->is_signed); + if (std::string mismatch = compare_attributes(a, b); !mismatch.empty()) + return mismatch; + return ""; + } + + void check_wires() + { + for (const auto &it : mod_a->wires_) { + if (mod_b->wires_.count(it.first) == 0) + log_error("Module %s missing wire %s in second design.\n", log_id(mod_a->name), log_id(it.first)); + if (std::string mismatch = compare_wires(it.second, mod_b->wires_.at(it.first)); !mismatch.empty()) + log_error("Module %s wire %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch); + } + for (const auto &it : mod_b->wires_) + if (mod_a->wires_.count(it.first) == 0) + log_error("Module %s missing wire %s in first design.\n", log_id(mod_b->name), log_id(it.first)); + } + + std::string compare_memories(const RTLIL::Memory *a, const RTLIL::Memory *b) + { + if (a->name != b->name) + return "name mismatch: " + std::string(log_id(a->name)) + " != " + log_id(b->name); + if (a->width != b->width) + return "width mismatch: " + std::to_string(a->width) + " != " + std::to_string(b->width); + if (a->start_offset != b->start_offset) + return "start_offset mismatch: " + std::to_string(a->start_offset) + " != " + std::to_string(b->start_offset); + if (a->size != b->size) + return "size mismatch: " + std::to_string(a->size) + " != " + std::to_string(b->size); + if (std::string mismatch = compare_attributes(a, b); !mismatch.empty()) + return mismatch; + return ""; + } + + std::string compare_cells(const RTLIL::Cell *a, const RTLIL::Cell *b) + { + if (a->name != b->name) + return "name mismatch: " + std::string(log_id(a->name)) + " != " + log_id(b->name); + if (a->type != b->type) + return "type mismatch: " + std::string(log_id(a->type)) + " != " + log_id(b->type); + if (std::string mismatch = compare_attributes(a, b); !mismatch.empty()) + return mismatch; + + for (const auto &it : a->parameters) { + if (b->parameters.count(it.first) == 0) + return "parameter mismatch: missing parameter " + std::string(log_id(it.first)) + " in second design"; + if (it.second != b->parameters.at(it.first)) + return "parameter mismatch: " + std::string(log_id(it.first)) + " mismatch: " + log_const(it.second) + " != " + log_const(b->parameters.at(it.first)); + } + for (const auto &it : b->parameters) + if (a->parameters.count(it.first) == 0) + return "parameter mismatch: missing parameter " + std::string(log_id(it.first)) + " in first design"; + + for (const auto &it : a->connections()) { + if (b->connections().count(it.first) == 0) + return "connection mismatch: missing connection " + std::string(log_id(it.first)) + " in second design"; + if (!compare_sigspec(it.second, b->connections().at(it.first))) + return "connection " + std::string(log_id(it.first)) + " mismatch: " + log_signal(it.second) + " != " + log_signal(b->connections().at(it.first)); + } + for (const auto &it : b->connections()) + if (a->connections().count(it.first) == 0) + return "connection mismatch: missing connection " + std::string(log_id(it.first)) + " in first design"; + + return ""; + } + + void check_cells() + { + for (const auto &it : mod_a->cells_) { + if (mod_b->cells_.count(it.first) == 0) + log_error("Module %s missing cell %s in second design.\n", log_id(mod_a->name), log_id(it.first)); + if (std::string mismatch = compare_cells(it.second, mod_b->cells_.at(it.first)); !mismatch.empty()) + log_error("Module %s cell %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch); + } + for (const auto &it : mod_b->cells_) + if (mod_a->cells_.count(it.first) == 0) + log_error("Module %s missing cell %s in first design.\n", log_id(mod_b->name), log_id(it.first)); + } + + void check_memories() + { + for (const auto &it : mod_a->memories) { + if (mod_b->memories.count(it.first) == 0) + log_error("Module %s missing memory %s in second design.\n", log_id(mod_a->name), log_id(it.first)); + if (std::string mismatch = compare_memories(it.second, mod_b->memories.at(it.first)); !mismatch.empty()) + log_error("Module %s memory %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch); + } + for (const auto &it : mod_b->memories) + if (mod_a->memories.count(it.first) == 0) + log_error("Module %s missing memory %s in first design.\n", log_id(mod_b->name), log_id(it.first)); + } + + std::string compare_case_rules(const RTLIL::CaseRule *a, const RTLIL::CaseRule *b) + { + if (std::string mismatch = compare_attributes(a, b); !mismatch.empty()) return mismatch; + + if (a->compare.size() != b->compare.size()) + return "compare size mismatch: " + std::to_string(a->compare.size()) + " != " + std::to_string(b->compare.size()); + for (size_t i = 0; i < a->compare.size(); i++) + if (!compare_sigspec(a->compare[i], b->compare[i])) + return "compare " + std::to_string(i) + " mismatch: " + log_signal(a->compare[i]) + " != " + log_signal(b->compare[i]); + + if (a->actions.size() != b->actions.size()) + return "actions size mismatch: " + std::to_string(a->actions.size()) + " != " + std::to_string(b->actions.size()); + for (size_t i = 0; i < a->actions.size(); i++) { + if (!compare_sigspec(a->actions[i].first, b->actions[i].first)) + return "action " + std::to_string(i) + " first mismatch: " + log_signal(a->actions[i].first) + " != " + log_signal(b->actions[i].first); + if (!compare_sigspec(a->actions[i].second, b->actions[i].second)) + return "action " + std::to_string(i) + " second mismatch: " + log_signal(a->actions[i].second) + " != " + log_signal(b->actions[i].second); + } + + if (a->switches.size() != b->switches.size()) + return "switches size mismatch: " + std::to_string(a->switches.size()) + " != " + std::to_string(b->switches.size()); + for (size_t i = 0; i < a->switches.size(); i++) + if (std::string mismatch = compare_switch_rules(a->switches[i], b->switches[i]); !mismatch.empty()) + return "switch " + std::to_string(i) + " " + mismatch; + + return ""; + } + + std::string compare_switch_rules(const RTLIL::SwitchRule *a, const RTLIL::SwitchRule *b) + { + if (std::string mismatch = compare_attributes(a, b); !mismatch.empty()) + return mismatch; + if (!compare_sigspec(a->signal, b->signal)) + return "signal mismatch: " + log_signal(a->signal) + " != " + log_signal(b->signal); + + if (a->cases.size() != b->cases.size()) + return "cases size mismatch: " + std::to_string(a->cases.size()) + " != " + std::to_string(b->cases.size()); + for (size_t i = 0; i < a->cases.size(); i++) + if (std::string mismatch = compare_case_rules(a->cases[i], b->cases[i]); !mismatch.empty()) + return "case " + std::to_string(i) + " " + mismatch; + + return ""; + } + + std::string compare_sync_rules(const RTLIL::SyncRule *a, const RTLIL::SyncRule *b) + { + if (a->type != b->type) + return "type mismatch: " + std::to_string(a->type) + " != " + std::to_string(b->type); + if (!compare_sigspec(a->signal, b->signal)) + return "signal mismatch: " + log_signal(a->signal) + " != " + log_signal(b->signal); + if (a->actions.size() != b->actions.size()) + return "actions size mismatch: " + std::to_string(a->actions.size()) + " != " + std::to_string(b->actions.size()); + for (size_t i = 0; i < a->actions.size(); i++) { + if (!compare_sigspec(a->actions[i].first, b->actions[i].first)) + return "action " + std::to_string(i) + " first mismatch: " + log_signal(a->actions[i].first) + " != " + log_signal(b->actions[i].first); + if (!compare_sigspec(a->actions[i].second, b->actions[i].second)) + return "action " + std::to_string(i) + " second mismatch: " + log_signal(a->actions[i].second) + " != " + log_signal(b->actions[i].second); + } + if (a->mem_write_actions.size() != b->mem_write_actions.size()) + return "mem_write_actions size mismatch: " + std::to_string(a->mem_write_actions.size()) + " != " + std::to_string(b->mem_write_actions.size()); + for (size_t i = 0; i < a->mem_write_actions.size(); i++) { + const auto &ma = a->mem_write_actions[i]; + const auto &mb = b->mem_write_actions[i]; + if (ma.memid != mb.memid) + return "mem_write_actions " + std::to_string(i) + " memid mismatch: " + log_id(ma.memid) + " != " + log_id(mb.memid); + if (!compare_sigspec(ma.address, mb.address)) + return "mem_write_actions " + std::to_string(i) + " address mismatch: " + log_signal(ma.address) + " != " + log_signal(mb.address); + if (!compare_sigspec(ma.data, mb.data)) + return "mem_write_actions " + std::to_string(i) + " data mismatch: " + log_signal(ma.data) + " != " + log_signal(mb.data); + if (!compare_sigspec(ma.enable, mb.enable)) + return "mem_write_actions " + std::to_string(i) + " enable mismatch: " + log_signal(ma.enable) + " != " + log_signal(mb.enable); + if (ma.priority_mask != mb.priority_mask) + return "mem_write_actions " + std::to_string(i) + " priority_mask mismatch: " + log_const(ma.priority_mask) + " != " + log_const(mb.priority_mask); + if (std::string mismatch = compare_attributes(&ma, &mb); !mismatch.empty()) + return "mem_write_actions " + std::to_string(i) + " " + mismatch; + } + return ""; + } + + std::string compare_processes(const RTLIL::Process *a, const RTLIL::Process *b) + { + if (a->name != b->name) return "name mismatch: " + std::string(log_id(a->name)) + " != " + log_id(b->name); + if (std::string mismatch = compare_attributes(a, b); !mismatch.empty()) + return mismatch; + if (std::string mismatch = compare_case_rules(&a->root_case, &b->root_case); !mismatch.empty()) + return "case rule " + mismatch; + if (a->syncs.size() != b->syncs.size()) + return "sync count mismatch: " + std::to_string(a->syncs.size()) + " != " + std::to_string(b->syncs.size()); + for (size_t i = 0; i < a->syncs.size(); i++) + if (std::string mismatch = compare_sync_rules(a->syncs[i], b->syncs[i]); !mismatch.empty()) + return "sync " + std::to_string(i) + " " + mismatch; + return ""; + } + + void check_processes() + { + for (auto &it : mod_a->processes) { + if (mod_b->processes.count(it.first) == 0) + log_error("Module %s missing process %s in second design.\n", log_id(mod_a->name), log_id(it.first)); + if (std::string mismatch = compare_processes(it.second, mod_b->processes.at(it.first)); !mismatch.empty()) + log_error("Module %s process %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch.c_str()); + } + for (auto &it : mod_b->processes) + if (mod_a->processes.count(it.first) == 0) + log_error("Module %s missing process %s in first design.\n", log_id(mod_b->name), log_id(it.first)); + } + + void check_connections() + { + const auto &conns_a = mod_a->connections(); + const auto &conns_b = mod_b->connections(); + if (conns_a.size() != conns_b.size()) { + log_error("Module %s connection count differs: %zu != %zu\n", log_id(mod_a->name), conns_a.size(), conns_b.size()); + } else { + for (size_t i = 0; i < conns_a.size(); i++) { + if (!compare_sigspec(conns_a[i].first, conns_b[i].first)) + log_error("Module %s connection %zu LHS %s != %s.\n", log_id(mod_a->name), i, log_signal(conns_a[i].first), log_signal(conns_b[i].first)); + if (!compare_sigspec(conns_a[i].second, conns_b[i].second)) + log_error("Module %s connection %zu RHS %s != %s.\n", log_id(mod_a->name), i, log_signal(conns_a[i].second), log_signal(conns_b[i].second)); + } + } + } + + void check() + { + if (mod_a->name != mod_b->name) + log_error("Modules have different names: %s != %s\n", log_id(mod_a->name), log_id(mod_b->name)); + if (std::string mismatch = compare_attributes(mod_a, mod_b); !mismatch.empty()) + log_error("Module %s %s.\n", log_id(mod_a->name), mismatch); + check_wires(); + check_cells(); + check_memories(); + check_connections(); + check_processes(); + } +}; + +struct DesignEqualPass : public Pass { + DesignEqualPass() : Pass("design_equal", "check if two designs are the same") { } + void help() override + { + log("\n"); + log(" design_equal \n"); + log("\n"); + log("Compare the current design with the design previously saved under the given\n"); + log("name. Abort with an error if the designs are different.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) override + { + if (args.size() != 2) + log_cmd_error("Missing argument.\n"); + + std::string check_name = args[1]; + if (saved_designs.count(check_name) == 0) + log_cmd_error("No saved design '%s' found!\n", check_name.c_str()); + + RTLIL::Design *other = saved_designs.at(check_name); + + for (auto &it : design->modules_) { + RTLIL::Module *mod = it.second; + if (!other->has(mod->name)) + log_error("Second design missing module %s.\n", log_id(mod->name)); + + ModuleComparator cmp(mod, other->module(mod->name)); + cmp.check(); + } + for (auto &it : other->modules_) { + RTLIL::Module *mod = it.second; + if (!design->has(mod->name)) + log_error("First design missing module %s.\n", log_id(mod->name)); + } + + log("Designs are identical.\n"); + } +} DesignEqualPass; + +YOSYS_NAMESPACE_END diff --git a/tests/various/design_equal_fail.ys b/tests/various/design_equal_fail.ys new file mode 100644 index 000000000..330d8d838 --- /dev/null +++ b/tests/various/design_equal_fail.ys @@ -0,0 +1,22 @@ +logger -expect error "Second design missing module top_renamed" 1 + +read_rtlil < Date: Wed, 17 Dec 2025 03:11:06 +0000 Subject: [PATCH 016/291] Add -legalize option to read_rtlil --- frontends/rtlil/rtlil_frontend.cc | 141 +++++++++++++++++++++++++----- kernel/rtlil.cc | 7 ++ kernel/rtlil.h | 3 + 3 files changed, 131 insertions(+), 20 deletions(-) diff --git a/frontends/rtlil/rtlil_frontend.cc b/frontends/rtlil/rtlil_frontend.cc index 271962725..a1412d983 100644 --- a/frontends/rtlil/rtlil_frontend.cc +++ b/frontends/rtlil/rtlil_frontend.cc @@ -40,6 +40,7 @@ struct RTLILFrontendWorker { bool flag_nooverwrite = false; bool flag_overwrite = false; bool flag_lib = false; + bool flag_legalize = false; int line_num; std::string line_buf; @@ -322,6 +323,17 @@ struct RTLILFrontendWorker { return val; } + RTLIL::Wire *legalize_wire(RTLIL::IdString id) + { + int wires_size = current_module->wires_size(); + if (wires_size == 0) + error("No wires found for legalization"); + int hash = hash_ops::hash(id).yield(); + RTLIL::Wire *wire = current_module->wire_at(abs(hash % wires_size)); + log("Legalizing wire `%s' to `%s'.\n", log_id(id), log_id(wire->name)); + return wire; + } + RTLIL::SigSpec parse_sigspec() { RTLIL::SigSpec sig; @@ -339,8 +351,12 @@ struct RTLILFrontendWorker { std::optional id = try_parse_id(); if (id.has_value()) { RTLIL::Wire *wire = current_module->wire(*id); - if (wire == nullptr) - error("Wire `%s' not found.", *id); + if (wire == nullptr) { + if (flag_legalize) + wire = legalize_wire(*id); + else + error("Wire `%s' not found.", *id); + } sig = RTLIL::SigSpec(wire); } else { sig = RTLIL::SigSpec(parse_const()); @@ -349,17 +365,44 @@ struct RTLILFrontendWorker { while (try_parse_char('[')) { int left = parse_integer(); - if (left >= sig.size() || left < 0) - error("bit index %d out of range", left); + if (left >= sig.size() || left < 0) { + if (flag_legalize) { + int legalized; + if (sig.size() == 0) + legalized = 0; + else + legalized = std::max(0, std::min(left, sig.size() - 1)); + log("Legalizing bit index %d to %d.\n", left, legalized); + left = legalized; + } else { + error("bit index %d out of range", left); + } + } if (try_parse_char(':')) { int right = parse_integer(); - if (right < 0) - error("bit index %d out of range", right); - if (left < right) - error("invalid slice [%d:%d]", left, right); - sig = sig.extract(right, left-right+1); + if (right < 0) { + if (flag_legalize) { + log("Legalizing bit index %d to %d.\n", right, 0); + right = 0; + } else + error("bit index %d out of range", right); + } + if (left < right) { + if (flag_legalize) { + log("Legalizing bit index %d to %d.\n", left, right); + left = right; + } else + error("invalid slice [%d:%d]", left, right); + } + if (flag_legalize && left >= sig.size()) + log("Legalizing slice %d:%d by igoring it\n", left, right); + else + sig = sig.extract(right, left - right + 1); } else { - sig = sig.extract(left); + if (flag_legalize && left >= sig.size()) + log("Legalizing slice %d by igoring it\n", left); + else + sig = sig.extract(left); } expect_char(']'); } @@ -476,8 +519,14 @@ struct RTLILFrontendWorker { { std::optional id = try_parse_id(); if (id.has_value()) { - if (current_module->wire(*id) != nullptr) - error("RTLIL error: redefinition of wire %s.", *id); + if (current_module->wire(*id) != nullptr) { + if (flag_legalize) { + log("Legalizing redefinition of wire %s.\n", *id); + pool wires = {current_module->wire(*id)}; + current_module->remove(wires); + } else + error("RTLIL error: redefinition of wire %s.", *id); + } wire = current_module->addWire(std::move(*id)); break; } @@ -528,8 +577,13 @@ struct RTLILFrontendWorker { { std::optional id = try_parse_id(); if (id.has_value()) { - if (current_module->memories.count(*id) != 0) - error("RTLIL error: redefinition of memory %s.", *id); + if (current_module->memories.count(*id) != 0) { + if (flag_legalize) { + log("Legalizing redefinition of memory %s.\n", *id); + current_module->remove(current_module->memories.at(*id)); + } else + error("RTLIL error: redefinition of memory %s.", *id); + } memory->name = std::move(*id); break; } @@ -551,14 +605,36 @@ struct RTLILFrontendWorker { expect_eol(); } + void legalize_width_parameter(RTLIL::Cell *cell, RTLIL::IdString port_name) + { + std::string width_param_name = port_name.str() + "_WIDTH"; + if (cell->parameters.count(width_param_name) == 0) + return; + RTLIL::Const ¶m = cell->parameters.at(width_param_name); + if (param.as_int() != 0) + return; + cell->parameters[width_param_name] = RTLIL::Const(cell->getPort(port_name).size()); + } + void parse_cell() { RTLIL::IdString cell_type = parse_id(); RTLIL::IdString cell_name = parse_id(); expect_eol(); - if (current_module->cell(cell_name) != nullptr) - error("RTLIL error: redefinition of cell %s.", cell_name); + if (current_module->cell(cell_name) != nullptr) { + if (flag_legalize) { + RTLIL::IdString new_name; + int suffix = 1; + do { + new_name = RTLIL::IdString(cell_name.str() + "_" + std::to_string(suffix)); + ++suffix; + } while (current_module->cell(new_name) != nullptr); + log("Legalizing redefinition of cell %s by renaming to %s.\n", cell_name, new_name); + cell_name = new_name; + } else + error("RTLIL error: redefinition of cell %s.", cell_name); + } RTLIL::Cell *cell = current_module->addCell(cell_name, cell_type); cell->attributes = std::move(attrbuf); @@ -587,9 +663,15 @@ struct RTLILFrontendWorker { expect_eol(); } else if (try_parse_keyword("connect")) { RTLIL::IdString port_name = parse_id(); - if (cell->hasPort(port_name)) - error("RTLIL error: redefinition of cell port %s.", port_name); + if (cell->hasPort(port_name)) { + if (flag_legalize) + log("Legalizing redefinition of cell port %s.", port_name); + else + error("RTLIL error: redefinition of cell port %s.", port_name); + } cell->setPort(std::move(port_name), parse_sigspec()); + if (flag_legalize) + legalize_width_parameter(cell, port_name); expect_eol(); } else if (try_parse_keyword("end")) { expect_eol(); @@ -606,6 +688,11 @@ struct RTLILFrontendWorker { error("dangling attribute"); RTLIL::SigSpec s1 = parse_sigspec(); RTLIL::SigSpec s2 = parse_sigspec(); + if (flag_legalize) { + int min_size = std::min(s1.size(), s2.size()); + s1 = s1.extract(0, min_size); + s2 = s2.extract(0, min_size); + } current_module->connect(std::move(s1), std::move(s2)); expect_eol(); } @@ -682,8 +769,13 @@ struct RTLILFrontendWorker { RTLIL::IdString proc_name = parse_id(); expect_eol(); - if (current_module->processes.count(proc_name) != 0) - error("RTLIL error: redefinition of process %s.", proc_name); + if (current_module->processes.count(proc_name) != 0) { + if (flag_legalize) { + log("Legalizing redefinition of process %s.\n", proc_name); + current_module->remove(current_module->processes.at(proc_name)); + } else + error("RTLIL error: redefinition of process %s.", proc_name); + } RTLIL::Process *proc = current_module->addProcess(std::move(proc_name)); proc->attributes = std::move(attrbuf); @@ -804,6 +896,11 @@ struct RTLILFrontend : public Frontend { log(" -lib\n"); log(" only create empty blackbox modules\n"); log("\n"); + log(" -legalize\n"); + log(" prevent semantic errors (e.g. reference to unknown wire, redefinition of wire/cell)\n"); + log(" by deterministically rewriting the input into something valid. Useful when using\n"); + log(" fuzzing to generate random but valid RTLIL.\n"); + log("\n"); } void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { @@ -828,6 +925,10 @@ struct RTLILFrontend : public Frontend { worker.flag_lib = true; continue; } + if (arg == "-legalize") { + worker.flag_legalize = true; + continue; + } break; } extra_args(f, filename, args, argidx); diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index d92aec73b..a09f9497a 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3039,6 +3039,13 @@ void RTLIL::Module::remove(RTLIL::Cell *cell) } } +void RTLIL::Module::remove(RTLIL::Memory *memory) +{ + log_assert(memories.count(memory->name) != 0); + memories.erase(memory->name); + delete memory; +} + void RTLIL::Module::remove(RTLIL::Process *process) { log_assert(processes.count(process->name) != 0); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index f841df1ed..163dbe5a8 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -2139,6 +2139,8 @@ public: } RTLIL::ObjRange wires() { return RTLIL::ObjRange(&wires_, &refcount_wires_); } + int wires_size() const { return wires_.size(); } + RTLIL::Wire* wire_at(int index) const { return wires_.element(index)->second; } RTLIL::ObjRange cells() { return RTLIL::ObjRange(&cells_, &refcount_cells_); } void add(RTLIL::Binding *binding); @@ -2146,6 +2148,7 @@ public: // Removing wires is expensive. If you have to remove wires, remove them all at once. void remove(const pool &wires); void remove(RTLIL::Cell *cell); + void remove(RTLIL::Memory *memory); void remove(RTLIL::Process *process); void rename(RTLIL::Wire *wire, RTLIL::IdString new_name); From 9ee51c8f27164e85c15ccbfc18910169f6d647b8 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Sun, 21 Dec 2025 22:45:06 +0000 Subject: [PATCH 017/291] Add AFL++ Grammar-Generator grammar for RTLIL fuzzing, and instructions for how to use it. --- tests/pass-fuzzing.md | 106 ++++++++++++++++++++++++++++ tests/tools/rtlil-fuzz-grammar.json | 104 +++++++++++++++++++++++++++ 2 files changed, 210 insertions(+) create mode 100644 tests/pass-fuzzing.md create mode 100644 tests/tools/rtlil-fuzz-grammar.json diff --git a/tests/pass-fuzzing.md b/tests/pass-fuzzing.md new file mode 100644 index 000000000..993f36078 --- /dev/null +++ b/tests/pass-fuzzing.md @@ -0,0 +1,106 @@ +Suppose you're making significant changes to a pass that should not change +the pass's output in any way. It might be useful to run a large number of +automatically generated tests to try to find bugs where the output has +changed. This document describes how to do that. + +Basically we're going to use [AFL++](https://github.com/AFLplusplus/AFLplusplus) with the +[Grammar-Mutator](https://github.com/AFLplusplus/Grammar-Mutator) plugin to generate +RTLIL testcases. For each testcase, we run a Yosys script that applies both the old and new +implementation of the pass to the same design and compares the results. Testcase +generation is coverage-guided, i.e. the fuzzer will try to find testcases that exercise all +code in the old and new implementation of the pass (and in the RTLIL parser). + +## Setup + +These instructions clone tools into subdirectories of your home directory. They assume +you have a Yosys checkout under `$HOME/yosys`, and that you're testing the `opt_merge` pass. +They have been tested with AFL++ revision 68b492b2c7725816068718ef9437b72b40e67519 and Grammar-Mutator revision 05d8f537f8d656f0754e7ad5dcc653c42cb4f8ff. + +Clone and build AFL++ and Grammar-Mutator: +``` +cd $HOME +git clone https://github.com/AFLplusplus/AFLplusplus.git +git -C AFLplusplus checkout stable +git clone https://github.com/AFLplusplus/Grammar-Mutator.git +git -C Grammar-Mutator checkout stable +``` + +Check that `rtlil-fuzz-grammar.json` generates RTLIL constructs relevant to your pass. +Currently it's quite simple and generates a limited set of cells and wires; you may need to +extend it to generate different kinds of cells and other RTLIL constructs (e.g. `proc`). + +Build AFL++ and Grammar-Mutator: +``` +make -C $HOME/AFLplusplus -j all +make -C $HOME/Grammar-Mutator -j GRAMMAR_FILE=$HOME/yosys/tests/tools/rtlil-fuzz-grammar.json +``` + +Create a Yosys commit that adds the old version of your pass as a new command, e.g. copy +`opt_merge.cc` into `old_opt_merge.cc` and change the name of the command to `old_opt_merge`. +[Here's](https://github.com/YosysHQ/yosys/commit/827cd8c998f3e455b14ac990a3159030ddc19b21) an example. + +You may also need to patch in [this commit](https://github.com/YosysHQ/yosys/commit/121c52f514c4ca282b4e6b3b14f71184f3849ddf) to work around a bug involving `std::reverse` on +empty vectors in the RTLIL parser when building with fuzzing instrumentation. +I think this is a clang++ bug so hopefully it will get fixed eventually and that patch will not be +necessary. + +Rebuild Yosys with the AFL++ compiler wrapper. This assumes your config builds Yosys with clang++. +``` +(cd $HOME/yosys; patch -lp1 << EOF) +diff --git a/Makefile b/Makefile +index 9c361294d..c9a98f74c 100644 +--- a/Makefile ++++ b/Makefile +@@ -238,7 +238,7 @@ + LTOFLAGS := $(GCC_LTO) + + ifeq ($(CONFIG),clang) +-CXX = clang++ ++CXX = $(HOME)/AFLplusplus/afl-c++ + CXXFLAGS += -std=$(CXXSTD) $(OPT_LEVEL) + ifeq ($(ENABLE_LTO),1) + LINKFLAGS += -fuse-ld=lld +EOF +make -C yosys clean && make -C yosys -j +``` + +You probably need to configure coredumps to work normally instead of going through some OS service: +``` +echo core | sudo tee /proc/sys/kernel/core_pattern +``` + +## Running the fuzzer + +Generate some initial testcases using Grammar-Mutator: +``` +(cd $HOME/Grammar-Mutator; rm -rf seeds trees; ./grammar_generator-rtlil 100 1000 ./seeds ./trees) +``` + +Now run AFL++. +``` +(cd $HOME/Grammar-Mutator; \ + AFL_CUSTOM_MUTATOR_LIBRARY=./libgrammarmutator-rtlil.so \ + AFL_CUSTOM_MUTATOR_ONLY=1 \ + AFL_BENCH_UNTIL_CRASH=1 \ + YOSYS_WORK_UNITS_PER_THREAD=1 \ + YOSYS_ABORT_ON_LOG_ERROR=1 \ + $HOME/AFLplusplus/afl-fuzz -t 5000 -m none -i seeds -o out -- \ + $HOME/yosys/yosys -p 'read_rtlil -legalize @@; design -save init; old_opt_merge; design -save old; design -load init; opt_merge; design_equal old' \ +) +``` +This will run the fuzzer until the first crash (including any pass output mismatches) and then stop. +Or if you're lucky, the fuzzer will run indefinitely. This uses very little parallelism; if it doesn't find any errors right away, you can increase the test throughput by running AFL++ in parallel using the instructions [here](https://aflplus.plus/docs/parallel_fuzzing). + +## Working with fuzz test failures + +Any failing testcases will be dropped in `$HOME/Grammar-Mutator/out/default/crashes`. +Run `yosys -p 'read_rtlil -legalize ... ; dump'` to get the testcase as legalized RTLIL. + +## Notes on generating semantically valid RTLIL + +`Grammar-Mutator` generates RTLIL files according to the context-free grammar in `rtlil-fuzz-grammar.json`. +However, the testcases must also be semantically valid, e.g. references to wires should only refer to +wires that actually exist. These constraints cannot reasonably be expresed in a CFG. Therefore we +have added a `-legalize` option to the `read_rtlil` command. When `-legalize` is set, when `read_rtlil` +detects a failed semantic check, instead of erroring out it emits a warning and patches the incoming RTLIL +to make it valid. diff --git a/tests/tools/rtlil-fuzz-grammar.json b/tests/tools/rtlil-fuzz-grammar.json new file mode 100644 index 000000000..c27b160f4 --- /dev/null +++ b/tests/tools/rtlil-fuzz-grammar.json @@ -0,0 +1,104 @@ +{ + "": [ + [ + "module \\test\n", + "", "", + "", + "", + "end\n" + ] + ], + "": [ [ " wire width ", "", " ", "", " ", "", "\n" ] ], + "": [ [ "1" ], [ "2" ], [ "3" ], [ "4" ], [ "32" ], [ "128" ] ], + "": [ [ "input ", "" ], [ "output ", "" ], [ "inout ", "" ], [] ], + "": [ + [ + " cell $not ", "", "\n", + " parameter \\A_SIGNED 0\n", + " parameter \\A_WIDTH 0\n", + " parameter \\Y_WIDTH 0\n", + " connect \\A ", "", "\n", + " connect \\Y ", "", "\n", + " end\n" + ], + [ + " cell $and ", "", "\n", + " parameter \\A_SIGNED 0\n", + " parameter \\B_SIGNED 0\n", + " parameter \\A_WIDTH 0\n", + " parameter \\B_WIDTH 0\n", + " parameter \\Y_WIDTH 0\n", + " connect \\A ", "", "\n", + " connect \\B ", "", "\n", + " connect \\Y ", "", "\n", + " end\n" + ], + [ + " cell $or ", "", "\n", + " parameter \\A_SIGNED 0\n", + " parameter \\B_SIGNED 0\n", + " parameter \\A_WIDTH 0\n", + " parameter \\B_WIDTH 0\n", + " parameter \\Y_WIDTH 0\n", + " connect \\A ", "", "\n", + " connect \\B ", "", "\n", + " connect \\Y ", "", "\n", + " end\n" + ], + [ + " cell $xor ", "", "\n", + " parameter \\A_SIGNED 0\n", + " parameter \\B_SIGNED 0\n", + " parameter \\A_WIDTH 0\n", + " parameter \\B_WIDTH 0\n", + " parameter \\Y_WIDTH 0\n", + " connect \\A ", "", "\n", + " connect \\B ", "", "\n", + " connect \\Y ", "", "\n", + " end\n" + ], + [ + " cell ", "", " ", "", "\n", + " connect \\A ", "", "\n", + " connect \\Y ", "", "\n", + " end\n" + ], + [ + " cell ", "", " ", "", "\n", + " connect \\A ", "", "\n", + " connect \\B ", "", "\n", + " connect \\Y ", "", "\n", + " end\n" + ] + ], + "": [ [ "\\wire_a" ], [ "\\wire_b" ], [ "\\wire_c" ], [ "\\wire_d" ], [ "\\wire_e" ], [ "\\wire_f" ], [ "\\wire_g" ], [ "\\wire_h" ], [ "\\wire_i" ], [ "\\wire_j" ] ], + "": [ [ "\\cell_a" ], [ "\\cell_b" ], [ "\\cell_c" ], [ "\\cell_d" ], [ "\\cell_e" ], [ "\\cell_f" ], [ "\\cell_g" ], [ "\\cell_h" ], [ "\\cell_i" ], [ "\\cell_j" ] ], + "": [ [ "\\bb1" ], [ "\\bb2" ] ], + "": [ + [ "", " " ], + [ "{", "", " ", "", "}" ], + [ "" ], + [ "", "[", "", "]" ], + [ "", "[", "", ":", "", "]" ] + ], + "": [ + [ "0'", "" ], + [ "1'", "" ], + [ "2'", "" ], + [ "3'", "" ], + [ "4'", "" ], + [ "31'", "" ], + [ "32'", "" ], + [ "128'", "" ] + ], + "": [ [ "0" ], [ "1" ], [ "x" ], [ "z" ], [ "-" ], [ "m" ] ], + "": [ "0", "1", "2", "3", "31", "32" ], + "": [ "1", "2", "3", "4", "5", "6", "7", "8", "9", "10" ], + "": [ [ " connect ", "", " ", "", "\n" ] ], + + "": [ [ ], [ "", "" ] ], + "": [ [ ], [ "", "" ] ], + "": [ [ ], [ "", "" ] ], + "": [ [ ], [ "", "" ] ], + "": [ [ ], [ "", " ", "" ] ] +} From 721b5044799d891620f734081a31221617fbec84 Mon Sep 17 00:00:00 2001 From: Natalia Date: Thu, 18 Dec 2025 13:06:22 -0800 Subject: [PATCH 018/291] lut2mux: add -word option and test --- passes/techmap/lut2mux.cc | 38 +++++++++++++++++++++++------------ tests/techmap/lut2mux.ys | 42 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+), 13 deletions(-) create mode 100644 tests/techmap/lut2mux.ys diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc index ef76e0deb..28f466874 100644 --- a/passes/techmap/lut2mux.cc +++ b/passes/techmap/lut2mux.cc @@ -23,7 +23,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -int lut2mux(Cell *cell) +int lut2mux(Cell *cell, bool word_mode) { SigSpec sig_a = cell->getPort(ID::A); SigSpec sig_y = cell->getPort(ID::Y); @@ -32,7 +32,10 @@ int lut2mux(Cell *cell) if (GetSize(sig_a) == 1) { - cell->module->addMuxGate(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y); + if (!word_mode) + cell->module->addMuxGate(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y); + else + cell->module->addMux(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y); } else { @@ -44,10 +47,13 @@ int lut2mux(Cell *cell) Const lut1 = lut.extract(0, GetSize(lut)/2); Const lut2 = lut.extract(GetSize(lut)/2, GetSize(lut)/2); - count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y1, lut1)); - count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y2, lut2)); + count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y1, lut1), word_mode); + count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y2, lut2), word_mode); - cell->module->addMuxGate(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y); + if (!word_mode) + cell->module->addMuxGate(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y); + else + cell->module->addMux(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y); } cell->module->remove(cell); @@ -55,35 +61,41 @@ int lut2mux(Cell *cell) } struct Lut2muxPass : public Pass { - Lut2muxPass() : Pass("lut2mux", "convert $lut to $_MUX_") { } + Lut2muxPass() : Pass("lut2mux", "convert $lut to $mux/$_MUX_") { } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" lut2mux [options] [selection]\n"); log("\n"); - log("This pass converts $lut cells to $_MUX_ gates.\n"); + log("This pass converts $lut cells to $mux/$_MUX_ gates.\n"); + log("\n"); + log(" -word\n"); + log(" Convert $lut cells with a single input to word-level $mux gates.\n"); + log(" The default is to convert them to bit-level $_MUX_ gates.\n"); log("\n"); } void execute(std::vector args, RTLIL::Design *design) override { - log_header(design, "Executing LUT2MUX pass (convert $lut to $_MUX_).\n"); + log_header(design, "Executing LUT2MUX pass (convert $lut to $mux/$_MUX_).\n"); + log("ARGS:"); for (auto &a: args) log(" [%s]", a.c_str()); log("\n"); size_t argidx; + bool word_mode = false; for (argidx = 1; argidx < args.size(); argidx++) { - // if (args[argidx] == "-v") { - // continue; - // } + if (args[argidx] == "-word") { + word_mode = true; + continue; + } break; } - extra_args(args, argidx, design); for (auto module : design->selected_modules()) for (auto cell : module->selected_cells()) { if (cell->type == ID($lut)) { IdString cell_name = cell->name; - int count = lut2mux(cell); + int count = lut2mux(cell, word_mode); log("Converted %s.%s to %d MUX cells.\n", log_id(module), log_id(cell_name), count); } } diff --git a/tests/techmap/lut2mux.ys b/tests/techmap/lut2mux.ys new file mode 100644 index 000000000..212003756 --- /dev/null +++ b/tests/techmap/lut2mux.ys @@ -0,0 +1,42 @@ +# Test lut2mux pass using a directly constructed $lut (avoids frontend/synth differences in test-verific) + +read_rtlil << EOT +module \top + wire width 2 input 1 \a + wire width 1 output 2 \y + cell $lut \u_lut + parameter \WIDTH 2 + parameter \LUT 4'0110 + connect \A \a + connect \Y \y + end +end +EOT + +select -assert-count 1 t:$lut + +# default mode -> gate-level $_MUX_ +design -save gold +lut2mux +rename \top \gate +select -assert-count 3 gate/t:$_MUX_ +select -assert-count 0 gate/t:$mux +select -assert-count 0 gate/t:$lut + +# -word mode -> word-level $mux +design -copy-from gold -as top \top +select -none +select top +lut2mux -word +select -clear +rename \top \word +select -assert-count 3 word/t:$mux +select -assert-count 0 word/t:$_MUX_ +select -assert-count 0 gate/t:$lut + +# equivalence +equiv_make \gate \word equiv +hierarchy -top equiv +equiv_simple +equiv_induct +equiv_status -assert From a6d696ba2b4abaf2e3941d884f7db989d6b09e8b Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 30 Dec 2025 03:53:02 +0000 Subject: [PATCH 019/291] Give `IdString` a default move constructor and make it a POD type. Now that we're not refcounting `IdString`, it can use the default move constructor. This lets us make `IdString` a POD type so it can be passed in registers in the standard C++ ABI. --- kernel/rtlil.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index ec47adb0e..6549c1760 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -223,8 +223,8 @@ struct RTLIL::IdString constexpr inline IdString() : index_(0) { } inline IdString(const char *str) : index_(insert(std::string_view(str))) { } - constexpr inline IdString(const IdString &str) : index_(str.index_) { } - inline IdString(IdString &&str) : index_(str.index_) { str.index_ = 0; } + constexpr IdString(const IdString &str) = default; + IdString(IdString &&str) = default; inline IdString(const std::string &str) : index_(insert(std::string_view(str))) { } inline IdString(std::string_view str) : index_(insert(str)) { } constexpr inline IdString(StaticId id) : index_(static_cast(id)) {} From ea90f54783ce8170b8485b9bf012c8de519635dd Mon Sep 17 00:00:00 2001 From: YRabbit Date: Sat, 3 Jan 2026 17:42:49 +1000 Subject: [PATCH 020/291] Gowin. Implement byte enable. Enable write port with byte enables for BSRAM primitives. Signed-off-by: YRabbit --- techlibs/gowin/brams.txt | 6 ++++++ techlibs/gowin/brams_map.v | 18 +++++++++++++----- techlibs/gowin/brams_map_gw5a.v | 18 +++++++++++++----- 3 files changed, 32 insertions(+), 10 deletions(-) diff --git a/techlibs/gowin/brams.txt b/techlibs/gowin/brams.txt index ee76dd73a..6898c9bd9 100644 --- a/techlibs/gowin/brams.txt +++ b/techlibs/gowin/brams.txt @@ -2,6 +2,7 @@ ram block $__GOWIN_SP_ { abits 14; widths 1 2 4 9 18 36 per_port; cost 128; + byte 9; init no_undef; port srsw "A" { clock posedge; @@ -24,6 +25,7 @@ ram block $__GOWIN_SP_ { rdwr old; } } + wrbe_separate; } } @@ -31,6 +33,7 @@ ram block $__GOWIN_DP_ { abits 14; widths 1 2 4 9 18 per_port; cost 128; + byte 9; init no_undef; port srsw "A" "B" { clock posedge; @@ -53,6 +56,7 @@ ram block $__GOWIN_DP_ { rdwr old; } } + wrbe_separate; } } @@ -60,6 +64,7 @@ ram block $__GOWIN_SDP_ { abits 14; widths 1 2 4 9 18 36 per_port; cost 128; + byte 9; init no_undef; port sr "R" { clock posedge; @@ -75,5 +80,6 @@ ram block $__GOWIN_SDP_ { port sw "W" { clock posedge; clken; + wrbe_separate; } } diff --git a/techlibs/gowin/brams_map.v b/techlibs/gowin/brams_map.v index 8e6cc6140..5ffe13e11 100644 --- a/techlibs/gowin/brams_map.v +++ b/techlibs/gowin/brams_map.v @@ -14,7 +14,7 @@ `define x8_width(width) (width / 9 * 8 + width % 9) `define x8_rd_data(data) {1'bx, data[31:24], 1'bx, data[23:16], 1'bx, data[15:8], 1'bx, data[7:0]} `define x8_wr_data(data) {data[34:27], data[25:18], data[16:9], data[7:0]} -`define addrbe_always(width, addr) (width < 18 ? addr : width == 18 ? {addr[13:4], 4'b0011} : {addr[13:5], 5'b01111}) +`define addrbe(width, addr, w_be) (width < 18 ? addr : width == 18 ? {addr[13:4], 2'b00, w_be[1:0]} : {addr[13:5], 1'b0, w_be[3:0]}) `define INIT(func) \ @@ -90,6 +90,7 @@ parameter OPTION_RESET_MODE = "SYNC"; parameter PORT_A_WIDTH = 36; parameter PORT_A_OPTION_WRITE_MODE = 0; +parameter PORT_A_WR_BE_WIDTH = 4; input PORT_A_CLK; input PORT_A_CLK_EN; @@ -97,13 +98,14 @@ input PORT_A_WR_EN; input PORT_A_RD_SRST; input PORT_A_RD_ARST; input [13:0] PORT_A_ADDR; +input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE; input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA; output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA; `DEF_FUNCS wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST; -wire [13:0] AD = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR); +wire [13:0] AD = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE); generate @@ -173,9 +175,11 @@ parameter OPTION_RESET_MODE = "SYNC"; parameter PORT_A_WIDTH = 18; parameter PORT_A_OPTION_WRITE_MODE = 0; +parameter PORT_A_WR_BE_WIDTH = 4; parameter PORT_B_WIDTH = 18; parameter PORT_B_OPTION_WRITE_MODE = 0; +parameter PORT_B_WR_BE_WIDTH = 4; input PORT_A_CLK; input PORT_A_CLK_EN; @@ -183,6 +187,7 @@ input PORT_A_WR_EN; input PORT_A_RD_SRST; input PORT_A_RD_ARST; input [13:0] PORT_A_ADDR; +input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE; input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA; output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA; @@ -192,6 +197,7 @@ input PORT_B_WR_EN; input PORT_B_RD_SRST; input PORT_B_RD_ARST; input [13:0] PORT_B_ADDR; +input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE; input [PORT_A_WIDTH-1:0] PORT_B_WR_DATA; output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA; @@ -199,8 +205,8 @@ output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA; wire RSTA = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST; wire RSTB = OPTION_RESET_MODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST; -wire [13:0] ADA = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR); -wire [13:0] ADB = `addrbe_always(PORT_B_WIDTH, PORT_B_ADDR); +wire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_B_WR_BE); +wire [13:0] ADB = `addrbe(PORT_B_WIDTH, PORT_B_ADDR, PORT_B_WR_BE); generate @@ -306,6 +312,7 @@ parameter OPTION_RESET_MODE = "SYNC"; parameter PORT_R_WIDTH = 18; parameter PORT_W_WIDTH = 18; +parameter PORT_W_WR_BE_WIDTH=4; input PORT_R_CLK; input PORT_R_CLK_EN; @@ -318,12 +325,13 @@ input PORT_W_CLK; input PORT_W_CLK_EN; input PORT_W_WR_EN; input [13:0] PORT_W_ADDR; +input [PORT_W_WR_BE_WIDTH-1:0] PORT_W_WR_BE; input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA; `DEF_FUNCS wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST; -wire [13:0] ADW = `addrbe_always(PORT_W_WIDTH, PORT_W_ADDR); +wire [13:0] ADW = `addrbe(PORT_W_WIDTH, PORT_W_ADDR, PORT_W_WR_BE); wire WRE = PORT_W_CLK_EN & PORT_W_WR_EN; generate diff --git a/techlibs/gowin/brams_map_gw5a.v b/techlibs/gowin/brams_map_gw5a.v index 246146ee5..812f04edf 100644 --- a/techlibs/gowin/brams_map_gw5a.v +++ b/techlibs/gowin/brams_map_gw5a.v @@ -14,7 +14,7 @@ `define x8_width(width) (width / 9 * 8 + width % 9) `define x8_rd_data(data) {1'bx, data[31:24], 1'bx, data[23:16], 1'bx, data[15:8], 1'bx, data[7:0]} `define x8_wr_data(data) {data[34:27], data[25:18], data[16:9], data[7:0]} -`define addrbe_always(width, addr) (width < 18 ? addr : width == 18 ? {addr[13:4], 4'b0011} : {addr[13:5], 5'b01111}) +`define addrbe(width, addr, w_be) (width < 18 ? addr : width == 18 ? {addr[13:4], 2'b00, w_be[1:0]} : {addr[13:5], 1'b0, w_be[3:0]}) `define INIT(func) \ @@ -90,6 +90,7 @@ parameter OPTION_RESET_MODE = "SYNC"; parameter PORT_A_WIDTH = 36; parameter PORT_A_OPTION_WRITE_MODE = 0; +parameter PORT_A_WR_BE_WIDTH = 4; input PORT_A_CLK; input PORT_A_CLK_EN; @@ -97,13 +98,14 @@ input PORT_A_WR_EN; input PORT_A_RD_SRST; input PORT_A_RD_ARST; input [13:0] PORT_A_ADDR; +input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE; input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA; output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA; `DEF_FUNCS wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST; -wire [13:0] AD = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR); +wire [13:0] AD = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE); generate @@ -173,9 +175,11 @@ parameter OPTION_RESET_MODE = "SYNC"; parameter PORT_A_WIDTH = 18; parameter PORT_A_OPTION_WRITE_MODE = 0; +parameter PORT_A_WR_BE_WIDTH = 4; parameter PORT_B_WIDTH = 18; parameter PORT_B_OPTION_WRITE_MODE = 0; +parameter PORT_B_WR_BE_WIDTH = 4; input PORT_A_CLK; input PORT_A_CLK_EN; @@ -183,6 +187,7 @@ input PORT_A_WR_EN; input PORT_A_RD_SRST; input PORT_A_RD_ARST; input [13:0] PORT_A_ADDR; +input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE; input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA; output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA; @@ -192,6 +197,7 @@ input PORT_B_WR_EN; input PORT_B_RD_SRST; input PORT_B_RD_ARST; input [13:0] PORT_B_ADDR; +input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE; input [PORT_A_WIDTH-1:0] PORT_B_WR_DATA; output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA; @@ -199,8 +205,8 @@ output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA; wire RSTA = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST; wire RSTB = OPTION_RESET_MODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST; -wire [13:0] ADA = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR); -wire [13:0] ADB = `addrbe_always(PORT_B_WIDTH, PORT_B_ADDR); +wire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_B_WR_BE); +wire [13:0] ADB = `addrbe(PORT_B_WIDTH, PORT_B_ADDR, PORT_B_WR_BE); generate @@ -306,6 +312,7 @@ parameter OPTION_RESET_MODE = "SYNC"; parameter PORT_R_WIDTH = 18; parameter PORT_W_WIDTH = 18; +parameter PORT_W_WR_BE_WIDTH=4; input PORT_R_CLK; input PORT_R_CLK_EN; @@ -318,12 +325,13 @@ input PORT_W_CLK; input PORT_W_CLK_EN; input PORT_W_WR_EN; input [13:0] PORT_W_ADDR; +input [PORT_W_WR_BE_WIDTH-1:0] PORT_W_WR_BE; input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA; `DEF_FUNCS wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST; -wire [13:0] ADW = `addrbe_always(PORT_W_WIDTH, PORT_W_ADDR); +wire [13:0] ADW = `addrbe(PORT_W_WIDTH, PORT_W_ADDR, PORT_W_WR_BE); wire WRE = PORT_W_CLK_EN & PORT_W_WR_EN; generate From 8a78f2f7c594932769c6881f6460df5abed8d29f Mon Sep 17 00:00:00 2001 From: YRabbit Date: Mon, 5 Jan 2026 20:07:31 +1000 Subject: [PATCH 021/291] Gowin. Fix style. Signed-off-by: YRabbit --- techlibs/gowin/brams_map.v | 2 +- techlibs/gowin/brams_map_gw5a.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/gowin/brams_map.v b/techlibs/gowin/brams_map.v index 5ffe13e11..774896e79 100644 --- a/techlibs/gowin/brams_map.v +++ b/techlibs/gowin/brams_map.v @@ -312,7 +312,7 @@ parameter OPTION_RESET_MODE = "SYNC"; parameter PORT_R_WIDTH = 18; parameter PORT_W_WIDTH = 18; -parameter PORT_W_WR_BE_WIDTH=4; +parameter PORT_W_WR_BE_WIDTH = 4; input PORT_R_CLK; input PORT_R_CLK_EN; diff --git a/techlibs/gowin/brams_map_gw5a.v b/techlibs/gowin/brams_map_gw5a.v index 812f04edf..547b0d1d1 100644 --- a/techlibs/gowin/brams_map_gw5a.v +++ b/techlibs/gowin/brams_map_gw5a.v @@ -312,7 +312,7 @@ parameter OPTION_RESET_MODE = "SYNC"; parameter PORT_R_WIDTH = 18; parameter PORT_W_WIDTH = 18; -parameter PORT_W_WR_BE_WIDTH=4; +parameter PORT_W_WR_BE_WIDTH = 4; input PORT_R_CLK; input PORT_R_CLK_EN; From 6e5a5160518d422cee7cae922e930b3dc27c124c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 5 Jan 2026 16:34:45 +0100 Subject: [PATCH 022/291] Update ABC as per 2026-01-05 --- abc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/abc b/abc index ef74590eb..799ba6322 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit ef74590ebd78b3b707eeba56d8284faf018affa6 +Subproject commit 799ba632239b2a4db2bacda81de4e6efdc486b0c From 1567526954905120629315c807957938721871e8 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 6 Jan 2026 00:26:49 +0000 Subject: [PATCH 023/291] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 0008025ee..c859422cd 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.60+70 +YOSYS_VER := 0.60+78 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 11b0e7ad92e883af05f68fd3f4a9cdebbe14b85d Mon Sep 17 00:00:00 2001 From: Natalia Date: Fri, 19 Dec 2025 02:18:27 -0800 Subject: [PATCH 024/291] add lut2bmux --- passes/techmap/Makefile.inc | 1 + passes/techmap/lut2bmux.cc | 58 +++++++++++++++++++++++++++++++++++++ tests/techmap/lut2bmux.ys | 24 +++++++++++++++ 3 files changed, 83 insertions(+) create mode 100644 passes/techmap/lut2bmux.cc create mode 100644 tests/techmap/lut2bmux.ys diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 91b3b563a..083778d3c 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -39,6 +39,7 @@ OBJS += passes/techmap/muxcover.o OBJS += passes/techmap/aigmap.o OBJS += passes/techmap/tribuf.o OBJS += passes/techmap/lut2mux.o +OBJS += passes/techmap/lut2bmux.o OBJS += passes/techmap/nlutmap.o OBJS += passes/techmap/shregmap.o OBJS += passes/techmap/deminout.o diff --git a/passes/techmap/lut2bmux.cc b/passes/techmap/lut2bmux.cc new file mode 100644 index 000000000..42042c942 --- /dev/null +++ b/passes/techmap/lut2bmux.cc @@ -0,0 +1,58 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct Lut2BmuxPass : public Pass { + Lut2BmuxPass() : Pass("lut2bmux", "convert $lut to $bmux") { } + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" lut2bmux [options] [selection]\n"); + log("\n"); + log("This pass converts $lut cells to $bmux cells.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing LUT2BMUX pass (convert $lut to $bmux).\n"); + + size_t argidx = 1; + extra_args(args, argidx, design); + + for (auto module : design->selected_modules()) + for (auto cell : module->selected_cells()) { + if (cell->type == ID($lut)) { + cell->type = ID($bmux); + cell->setPort(ID::S, cell->getPort(ID::A)); + cell->setPort(ID::A, cell->getParam(ID::LUT)); + cell->unsetParam(ID::LUT); + cell->fixup_parameters(); + log("Converted %s.%s to BMUX cell.\n", log_id(module), log_id(cell)); + } + } + } +} Lut2BmuxPass; + +PRIVATE_NAMESPACE_END diff --git a/tests/techmap/lut2bmux.ys b/tests/techmap/lut2bmux.ys new file mode 100644 index 000000000..2d7387fc1 --- /dev/null +++ b/tests/techmap/lut2bmux.ys @@ -0,0 +1,24 @@ +read_rtlil << EOT +module \top + wire width 4 input 0 \A + wire output 1 \Y + + cell $lut $0 + parameter \WIDTH 4 + parameter \LUT 16'0110100110010110 + connect \A \A + connect \Y \Y + end +end +EOT + +hierarchy -auto-top + + +equiv_opt -assert lut2bmux + + +lut2bmux + +select -assert-count 0 t:$lut +select -assert-count 1 t:$bmux r:WIDTH=1 r:S_WIDTH=4 %i From 042ec1cf6076155e6a8ffa9d006fac789e12145a Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Fri, 19 Dec 2025 00:38:47 +0000 Subject: [PATCH 025/291] Defer redirecting cell outputs when merging cells in `opt_merge` until after we've done a full pass over the cells. This avoids changing `assign_map` and `initvals`, which are inputs to the hash function for `known_cells`, while `known_cells` exists. Changing the hash function for a hashtable while it exists leads to confusing behavior. That also means the exact behavior of `opt_merge` cannot be reproduced by a parallel implementation. --- passes/opt/opt_merge.cc | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index 6cdcbc822..2914debbc 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -284,6 +284,7 @@ struct OptMergeWorker CellPtrHash, CellPtrEqual> known_cells (0, CellPtrHash(*this), CellPtrEqual(*this)); + std::vector redirects; for (auto cell : cells) { auto [cell_in_map, inserted] = known_cells.insert(cell); @@ -305,12 +306,7 @@ struct OptMergeWorker RTLIL::SigSpec other_sig = other_cell->getPort(it.first); log_debug(" Redirecting output %s: %s = %s\n", it.first, log_signal(it.second), log_signal(other_sig)); - Const init = initvals(other_sig); - initvals.remove_init(it.second); - initvals.remove_init(other_sig); - module->connect(RTLIL::SigSig(it.second, other_sig)); - assign_map.add(it.second, other_sig); - initvals.set_init(other_sig, init); + redirects.push_back(RTLIL::SigSig(it.second, std::move(other_sig))); } } log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type, cell->name, module->name); @@ -318,6 +314,14 @@ struct OptMergeWorker total_count++; } } + for (const RTLIL::SigSig &redirect : redirects) { + module->connect(redirect); + Const init = initvals(redirect.second); + initvals.remove_init(redirect.first); + initvals.remove_init(redirect.second); + assign_map.add(redirect.first, redirect.second); + initvals.set_init(redirect.second, init); + } } log_suppressed(); From fcb8695261bd4ecd23f6c67701a49074eb08af63 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Wed, 7 Jan 2026 13:09:49 +1300 Subject: [PATCH 026/291] write_verilog: Skip empty switches --- backends/verilog/verilog_backend.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 8d77160fd..3d451117c 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -2143,6 +2143,9 @@ void dump_case_actions(std::ostream &f, std::string indent, RTLIL::CaseRule *cs) bool dump_proc_switch_ifelse(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw) { + if (sw->cases.empty()) + return true; + for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) { if ((*it)->compare.size() == 0) { break; From c0e29ef57c07da504038d2e3434f2937fc70dd26 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Wed, 7 Jan 2026 13:10:32 +1300 Subject: [PATCH 027/291] proc_clean: Removing an empty full_case is doing something --- passes/proc/proc_clean.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 19c2be4ca..8cccb96c4 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -97,6 +97,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did all_empty = false; if (all_empty) { + did_something = true; for (auto cs : sw->cases) delete cs; sw->cases.clear(); From 9f774651707e3d62e3aee94b7adf9b114e59bae8 Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Tue, 6 Jan 2026 16:19:04 -0800 Subject: [PATCH 028/291] Add test --- .../test_smtbmc_witness_mismatch.py | 190 ++++++++++++++++++ 1 file changed, 190 insertions(+) create mode 100644 tests/functional/test_smtbmc_witness_mismatch.py diff --git a/tests/functional/test_smtbmc_witness_mismatch.py b/tests/functional/test_smtbmc_witness_mismatch.py new file mode 100644 index 000000000..f13620f1d --- /dev/null +++ b/tests/functional/test_smtbmc_witness_mismatch.py @@ -0,0 +1,190 @@ +import json +import shutil +import subprocess +from pathlib import Path + +import pytest + +base_path = Path(__file__).resolve().parent.parent.parent + +pytestmark = pytest.mark.skipif(shutil.which("z3") is None, reason="z3 not available") + +def run(cmd, **kwargs): + """Run a command and assert it succeeds.""" + status = subprocess.run(cmd, **kwargs) + assert status.returncode == 0, f"{cmd[0]} failed" + return status + + +def write_smt2(tmp_path, verilog_text): + """Write Verilog to temp and emit SMT2 via yosys.""" + vfile = tmp_path / "design.v" + smt2 = tmp_path / "design.smt2" + vfile.write_text(verilog_text) + run([base_path / "yosys", "-Q", "-p", + f"read_verilog {vfile}; prep -top top; write_smt2 {smt2}"]) + return smt2 + + +def witness_entries(smt2_path): + """Parse yosys-smt2-witness JSON records from an SMT2 file.""" + entries = [] + marker = "yosys-smt2-witness" + with open(smt2_path, "r") as f: + for line in f: + if marker not in line: + continue + payload = line.split(marker, 1)[1].strip() + entries.append(json.loads(payload)) + return entries + + +def find_entry(entries, entry_type): + """Return the first witness entry of the given type.""" + for entry in entries: + if entry.get("type") == entry_type: + return entry + return None + + +def write_yw(yw_path, signals, bits): + """Write a minimal Yosys witness file with one step of bits.""" + data = { + "format": "Yosys Witness Trace", + "clocks": [], + "signals": signals, + "steps": [{"bits": bits}], + } + yw_path.write_text(json.dumps(data)) + + +def run_smtbmc(smt2_path, yw_path): + """Run yosys-smtbmc on the SMT2 file with a witness trace.""" + cmd = [ + base_path / "yosys-smtbmc", + "-s", "z3", + "-m", "top", + "--check-witness", + "--yw", yw_path, + "-t", "1", + smt2_path, + ] + return subprocess.run(cmd, capture_output=True, text=True) + + +def assert_no_mismatch_message(result): + """Assert the mismatch error prefix is absent from outputs.""" + combined = (result.stderr or "") + (result.stdout or "") + assert "Yosys witness signal mismatch" not in combined + + +def assert_has_mismatch_message(result, msg): + """Assert the mismatch error prefix and substring are present.""" + combined = (result.stderr or "") + (result.stdout or "") + assert "Yosys witness signal mismatch" in combined + assert msg in combined + + +def test_missing_signal_path(tmp_path): + smt2 = write_smt2(tmp_path, "module top(input ok, output out); assign out = ok; endmodule") + yw_path = tmp_path / "trace.yw" + signals = [{"path": ["\\missing"], "offset": 0, "width": 1, "init_only": False}] + write_yw(yw_path, signals, "1") + result = run_smtbmc(smt2, yw_path) + assert result.returncode != 0 + assert_has_mismatch_message(result, "signal not found in design") + + +def test_width_mismatch(tmp_path): + smt2 = write_smt2(tmp_path, "module top(input ok, output out); assign out = ok; endmodule") + entries = witness_entries(smt2) + input_entry = find_entry(entries, "input") + assert input_entry is not None + yw_path = tmp_path / "trace.yw" + signals = [{ + "path": input_entry["path"], + "offset": 0, + "width": 2, + "init_only": False, + }] + write_yw(yw_path, signals, "10") + result = run_smtbmc(smt2, yw_path) + assert result.returncode != 0 + assert_has_mismatch_message(result, "signal width/offset mismatch") + + +def test_memory_address_oob(tmp_path): + verilog = """ +module top(input ok, output [7:0] mem_out); + reg [7:0] mem [0:1]; + assign mem_out = mem[0] ^ {8{ok}}; +endmodule +""" + smt2 = write_smt2(tmp_path, verilog) + entries = witness_entries(smt2) + mem_entry = find_entry(entries, "mem") + assert mem_entry is not None + addr = mem_entry["size"] + yw_path = tmp_path / "trace.yw" + signals = [{ + "path": mem_entry["path"] + [f"\\[{addr}]"], + "offset": 0, + "width": mem_entry["width"], + "init_only": False, + }] + bits = "0" * mem_entry["width"] + write_yw(yw_path, signals, bits) + result = run_smtbmc(smt2, yw_path) + assert result.returncode != 0 + assert_has_mismatch_message(result, "memory address out of bounds") + + +def test_allowed_extra_signal_in_design(tmp_path): + verilog = """ +module top(input ok, input extra, output [1:0] out); + assign out = {ok, extra}; +endmodule +""" + smt2 = write_smt2(tmp_path, verilog) + entries = witness_entries(smt2) + input_entry = find_entry(entries, "input") + assert input_entry is not None + yw_path = tmp_path / "trace.yw" + signals = [{ + "path": input_entry["path"], + "offset": 0, + "width": input_entry["width"], + "init_only": False, + }] + bits = "0" * input_entry["width"] + write_yw(yw_path, signals, bits) + result = run_smtbmc(smt2, yw_path) + # With --check-witness and no assertions, smtbmc can still exit non-zero. + # Thus we don't check the result.returncode here and in the other success + # cases. + assert_no_mismatch_message(result) + + +def test_allowed_extra_memory_in_design(tmp_path): + verilog = """ +module top(input ok, output [7:0] out); + reg [7:0] mem0 [0:1]; + reg [7:0] mem1 [0:3]; + assign out = mem0[0] ^ mem1[0]; +endmodule +""" + smt2 = write_smt2(tmp_path, verilog) + entries = witness_entries(smt2) + input_entry = find_entry(entries, "input") + assert input_entry is not None + yw_path = tmp_path / "trace.yw" + signals = [{ + "path": input_entry["path"], + "offset": 0, + "width": input_entry["width"], + "init_only": False, + }] + bits = "1" * input_entry["width"] + write_yw(yw_path, signals, bits) + result = run_smtbmc(smt2, yw_path) + assert_no_mismatch_message(result) From 4d237bdd921e8c405722a148043731c63e0971db Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Tue, 6 Jan 2026 16:19:54 -0800 Subject: [PATCH 029/291] Deliver more helpful error messages --- backends/smt2/smtbmc.py | 32 ++++++++++++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/backends/smt2/smtbmc.py b/backends/smt2/smtbmc.py index 4e47117b3..9dfbd2a25 100644 --- a/backends/smt2/smtbmc.py +++ b/backends/smt2/smtbmc.py @@ -735,6 +735,12 @@ def ywfile_signal(sig, step, mask=None): output = [] + def ywfile_signal_error(reason, detail=None): + msg = f"Yosys witness signal mismatch for {sig.pretty()}: {reason}" + if detail: + msg += f" ({detail})" + raise ValueError(msg) + if sig.path in smt_wires: for wire in smt_wires[sig.path]: width, offset = wire["width"], wire["offset"] @@ -765,6 +771,12 @@ def ywfile_signal(sig, step, mask=None): for mem in smt_mems[sig.memory_path]: width, size, bv = mem["width"], mem["size"], mem["statebv"] + if sig.memory_addr is not None and sig.memory_addr >= size: + ywfile_signal_error( + "memory address out of bounds", + f"address={sig.memory_addr} size={size}", + ) + smt_expr = smt.net_expr(topmod, f"s{step}", mem["smtpath"]) if bv: @@ -781,18 +793,34 @@ def ywfile_signal(sig, step, mask=None): smt_expr = "((_ extract %d %d) %s)" % (slice_high, sig.offset, smt_expr) output.append((0, sig.width, smt_expr)) + else: + ywfile_signal_error("memory not found in design") output.sort() output = [chunk for chunk in output if chunk[0] != chunk[1]] + if not output: + if sig.memory_path: + ywfile_signal_error("memory signal has no matching bits in design") + else: + ywfile_signal_error("signal not found in design") + pos = 0 for start, end, smt_expr in output: - assert start == pos + if start != pos: + ywfile_signal_error( + "signal width/offset mismatch", + f"expected coverage at bit {pos}", + ) pos = end - assert pos == sig.width + if pos != sig.width: + ywfile_signal_error( + "signal width/offset mismatch", + f"covered {pos} of {sig.width} bits", + ) if len(output) == 1: return output[0][-1] From 9a09758f5683bacad0776d5cf2353c88f986751c Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Wed, 7 Jan 2026 13:21:23 +1300 Subject: [PATCH 030/291] Test empty switches --- tests/proc/bug5572.ys | 19 +++++++++++++++++++ tests/verilog/.gitignore | 1 + tests/verilog/bug5572.ys | 15 +++++++++++++++ 3 files changed, 35 insertions(+) create mode 100644 tests/proc/bug5572.ys create mode 100644 tests/verilog/bug5572.ys diff --git a/tests/proc/bug5572.ys b/tests/proc/bug5572.ys new file mode 100644 index 000000000..1d8f4e514 --- /dev/null +++ b/tests/proc/bug5572.ys @@ -0,0 +1,19 @@ +read_rtlil << EOT +attribute \top 1 +module \top + wire width 1 \sig + wire width 1 \val + + process $2 + switch \sig [0] + case 1'0 + case 1'1 + case + assign \val [0] 1'1 + end + end +end +EOT +proc_rmdead +proc_clean +select -assert-none p:* diff --git a/tests/verilog/.gitignore b/tests/verilog/.gitignore index b16ed0890..6a226989c 100644 --- a/tests/verilog/.gitignore +++ b/tests/verilog/.gitignore @@ -1,3 +1,4 @@ +/bug5572.v /const_arst.v /const_sr.v /doubleslash.v diff --git a/tests/verilog/bug5572.ys b/tests/verilog/bug5572.ys new file mode 100644 index 000000000..3044e3572 --- /dev/null +++ b/tests/verilog/bug5572.ys @@ -0,0 +1,15 @@ +read_rtlil << EOT +module \top + wire \sig + wire \val + process $2 + attribute \full_case 1 + switch \sig + end + end +end +EOT + +write_verilog bug5572.v +design -reset +read_verilog bug5572.v From 35321cd292075daabe847589d32d1f8a6c4224ba Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 7 Jan 2026 00:25:36 +0000 Subject: [PATCH 031/291] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index c859422cd..3dc5f0fe0 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.60+78 +YOSYS_VER := 0.60+88 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From f1fc704c84418318154d63de15fa1d3ae36d4292 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Wed, 7 Jan 2026 23:46:33 +0100 Subject: [PATCH 032/291] abc: handle ABC script errors instead of hanging --- passes/techmap/abc.cc | 6 ++++++ tests/techmap/bug5574.ys | 7 +++++++ 2 files changed, 13 insertions(+) create mode 100644 tests/techmap/bug5574.ys diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index e25a6facd..3f6e07e15 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1152,6 +1152,12 @@ bool read_until_abc_done(abc_output_filter &filt, int fd, DeferredLogs &logs) { // Ignore any leftover output, there should only be a prompt perhaps return true; } + // If ABC aborted the sourced script, it returns to the prompt and will + // never print YOSYS_ABC_DONE. Treat this as a failed run, not a hang. + if (line.substr(0, 7) == "Error: ") { + logs.log_error("ABC: %s", line.c_str()); + return false; + } filt.next_line(line); line.clear(); start = p + 1; diff --git a/tests/techmap/bug5574.ys b/tests/techmap/bug5574.ys new file mode 100644 index 000000000..c347a0436 --- /dev/null +++ b/tests/techmap/bug5574.ys @@ -0,0 +1,7 @@ +read_verilog << EOT +module fuzz_mwoqk (input i0, output o0); + assign o0 = i0 ^ 1; +endmodule +EOT +synth +abc -script +resub,-K,8; \ No newline at end of file From 8da919587d75d0ac84b4ee5c54606cc2e387b808 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 25 Nov 2025 01:35:00 +0000 Subject: [PATCH 033/291] Parallelize `opt_merge`. I'm not sure why but this is actually faster than existing `opt_merge` even with YOSYS_MAX_THREADS=1, for the jpeg synthesis test. 16.0s before, 15.5s after for end-to-end synthesis. --- kernel/hashlib.h | 6 + kernel/rtlil.h | 2 + passes/opt/opt_merge.cc | 407 +++++++++++++++++++++++++++++----------- 3 files changed, 301 insertions(+), 114 deletions(-) diff --git a/kernel/hashlib.h b/kernel/hashlib.h index ca600231a..b43a68abf 100644 --- a/kernel/hashlib.h +++ b/kernel/hashlib.h @@ -1321,6 +1321,12 @@ public: return i < 0 ? 0 : 1; } + int lookup(const K &key) const + { + Hasher::hash_t hash = database.do_hash(key); + return database.do_lookup_no_rehash(key, hash); + } + void expect(const K &key, int i) { int j = (*this)(key); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 1f1d8e0da..e3a5a3bf8 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -2140,6 +2140,8 @@ public: int wires_size() const { return wires_.size(); } RTLIL::Wire* wire_at(int index) const { return wires_.element(index)->second; } RTLIL::ObjRange cells() { return RTLIL::ObjRange(&cells_, &refcount_cells_); } + int cells_size() const { return cells_.size(); } + RTLIL::Cell* cell_at(int index) const { return cells_.element(index)->second; } void add(RTLIL::Binding *binding); diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index 69474b5f9..a6121b268 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -22,6 +22,7 @@ #include "kernel/sigtools.h" #include "kernel/log.h" #include "kernel/celltypes.h" +#include "kernel/threading.h" #include "libs/sha1/sha1.h" #include #include @@ -37,16 +38,73 @@ PRIVATE_NAMESPACE_BEGIN template inline Hasher hash_pair(const T &t, const U &u) { return hash_ops>::hash(t, u); } -struct OptMergeWorker +// Some cell and its hash value. +struct CellHash { - RTLIL::Design *design; - RTLIL::Module *module; - SigMap assign_map; - FfInitVals initvals; - bool mode_share_all; + // Index of a cell in the module + int cell_index; + Hasher::hash_t hash_value; +}; - CellTypes ct; - int total_count; +// The algorithm: +// 1) Compute and store the hashes of all relevant cells, in parallel. +// 2) Given N = the number of threads, partition the cells into N buckets by hash value: +// bucket k contains the cells whose hash value mod N = k. +// 3) For each bucket in parallel, build a hashtable of that bucket’s cells (using the +// precomputed hashes) and record the duplicates found. +// 4) On the main thread, process the list of duplicates to remove cells. +// For efficiency we fuse the second step into the first step by having the parallel +// threads write the cells into buckets directly. +// To avoid synchronization overhead, we divide each bucket into N shards. Each +// thread j adds a cell to bucket k by writing to shard j of bucket k — +// no synchronization required. In the next phase, thread k builds the hashtable for +// bucket k by iterating over all shards of the bucket. + +// The input to each thread in the "compute cell hashes" phase. +struct CellRange +{ + int begin; + int end; +}; + +// The output from each thread in the "compute cell hashes" phase. +struct CellHashes +{ + // Entry i contains the hashes where hash_value % bucketed_cell_hashes.size() == i + std::vector> bucketed_cell_hashes; +}; + +// A duplicate cell that has been found. +struct DuplicateCell +{ + // Remove this cell from the design + int remove_cell; + // ... and use this cell instead. + int keep_cell; +}; + +// The input to each thread in the "find duplicate cells" phase. +// Shards of buckets of cell hashes +struct Shards +{ + std::vector>> &bucketed_cell_hashes; +}; + +// The output from each thread in the "find duplicate cells" phase. +struct FoundDuplicates +{ + std::vector duplicates; +}; + +struct OptMergeThreadWorker +{ + const RTLIL::Module *module; + const SigMap &assign_map; + const FfInitVals &initvals; + const CellTypes &ct; + int workers; + bool mode_share_all; + bool mode_keepdc; static Hasher hash_pmux_in(const SigSpec& sig_s, const SigSpec& sig_b, Hasher h) { @@ -62,8 +120,8 @@ struct OptMergeWorker static void sort_pmux_conn(dict &conn) { - SigSpec sig_s = conn.at(ID::S); - SigSpec sig_b = conn.at(ID::B); + const SigSpec &sig_s = conn.at(ID::S); + const SigSpec &sig_b = conn.at(ID::B); int s_width = GetSize(sig_s); int width = GetSize(sig_b) / s_width; @@ -144,7 +202,6 @@ struct OptMergeWorker if (cell1->parameters != cell2->parameters) return false; - if (cell1->connections_.size() != cell2->connections_.size()) return false; for (const auto &it : cell1->connections_) @@ -199,7 +256,7 @@ struct OptMergeWorker return conn1 == conn2; } - bool has_dont_care_initval(const RTLIL::Cell *cell) + bool has_dont_care_initval(const RTLIL::Cell *cell) const { if (!cell->is_builtin_ff()) return false; @@ -207,36 +264,134 @@ struct OptMergeWorker return !initvals(cell->getPort(ID::Q)).is_fully_def(); } - OptMergeWorker(RTLIL::Design *design, RTLIL::Module *module, bool mode_nomux, bool mode_share_all, bool mode_keepdc) : - design(design), module(module), mode_share_all(mode_share_all) + OptMergeThreadWorker(const RTLIL::Module *module, const FfInitVals &initvals, + const SigMap &assign_map, const CellTypes &ct, int workers, + bool mode_share_all, bool mode_keepdc) : + module(module), assign_map(assign_map), initvals(initvals), ct(ct), + workers(workers), mode_share_all(mode_share_all), mode_keepdc(mode_keepdc) { - total_count = 0; - ct.setup_internals(); - ct.setup_internals_mem(); - ct.setup_stdcells(); - ct.setup_stdcells_mem(); + } - if (mode_nomux) { - ct.cell_types.erase(ID($mux)); - ct.cell_types.erase(ID($pmux)); + CellHashes compute_cell_hashes(const CellRange &cell_range) const + { + std::vector> bucketed_cell_hashes(workers); + for (int cell_index = cell_range.begin; cell_index < cell_range.end; ++cell_index) { + const RTLIL::Cell *cell = module->cell_at(cell_index); + if (!module->selected(cell)) + continue; + if (cell->type.in(ID($meminit), ID($meminit_v2), ID($mem), ID($mem_v2))) { + // Ignore those for performance: meminit can have an excessively large port, + // mem can have an excessively large parameter holding the init data + continue; + } + if (cell->type == ID($scopeinfo)) + continue; + if (mode_keepdc && has_dont_care_initval(cell)) + continue; + if (!cell->known()) + continue; + if (!mode_share_all && !ct.cell_known(cell->type)) + continue; + + Hasher::hash_t h = hash_cell_function(cell, Hasher()).yield(); + int bucket_index = h % workers; + bucketed_cell_hashes[bucket_index].push_back({cell_index, h}); } + return {std::move(bucketed_cell_hashes)}; + } - ct.cell_types.erase(ID($tribuf)); - ct.cell_types.erase(ID($_TBUF_)); - ct.cell_types.erase(ID($anyseq)); - ct.cell_types.erase(ID($anyconst)); - ct.cell_types.erase(ID($allseq)); - ct.cell_types.erase(ID($allconst)); - ct.cell_types.erase(ID($check)); - ct.cell_types.erase(ID($assert)); - ct.cell_types.erase(ID($assume)); - ct.cell_types.erase(ID($live)); - ct.cell_types.erase(ID($cover)); + FoundDuplicates find_duplicate_cells(int index, const Shards &in) const + { + // We keep a set of known cells. They're hashed with our hash_cell_function + // and compared with our compare_cell_parameters_and_connections. + struct CellHashOp { + std::size_t operator()(const CellHash &c) const { + return (std::size_t)c.hash_value; + } + }; + struct CellEqualOp { + const OptMergeThreadWorker& worker; + CellEqualOp(const OptMergeThreadWorker& w) : worker(w) {} + bool operator()(const CellHash &lhs, const CellHash &rhs) const { + return worker.compare_cell_parameters_and_connections( + worker.module->cell_at(lhs.cell_index), + worker.module->cell_at(rhs.cell_index)); + } + }; + std::unordered_set< + CellHash, + CellHashOp, + CellEqualOp> known_cells(0, CellHashOp(), CellEqualOp(*this)); + + std::vector duplicates; + for (const std::vector> &buckets : in.bucketed_cell_hashes) { + // Clear out our buckets as we go. This keeps the work of deallocation + // off the main thread. + std::vector bucket = std::move(buckets[index]); + for (CellHash c : bucket) { + auto [cell_in_map, inserted] = known_cells.insert(c); + if (inserted) + continue; + CellHash map_c = *cell_in_map; + if (module->cell_at(c.cell_index)->has_keep_attr()) { + if (module->cell_at(map_c.cell_index)->has_keep_attr()) + continue; + known_cells.erase(map_c); + known_cells.insert(c); + std::swap(c, map_c); + } + duplicates.push_back({c.cell_index, map_c.cell_index}); + } + } + return {duplicates}; + } +}; + +template +void initialize_queues(std::vector> &queues, int size) { + queues.reserve(size); + for (int i = 0; i < size; ++i) + queues.emplace_back(1); +} + +struct OptMergeWorker +{ + int total_count; + + OptMergeWorker(RTLIL::Module *module, const CellTypes &ct, bool mode_share_all, bool mode_keepdc) : + total_count(0) + { + SigMap assign_map(module); + FfInitVals initvals; + initvals.set(&assign_map, module); log("Finding identical cells in module `%s'.\n", module->name); - assign_map.set(module); - initvals.set(&assign_map, module); + // Use no more than one worker per thousand cells, rounded down, so + // we only start multithreading with at least 2000 cells. + int num_worker_threads = ThreadPool::pool_size(0, module->cells_size()/1000); + int workers = std::max(1, num_worker_threads); + + // The main thread doesn't do any work, so if there is only one worker thread, + // just run everything on the main thread instead. + // This avoids creating and waiting on a thread, which is pretty high overhead + // for very small modules. + if (num_worker_threads == 1) + num_worker_threads = 0; + OptMergeThreadWorker thread_worker(module, initvals, assign_map, ct, workers, mode_share_all, mode_keepdc); + + std::vector> cell_ranges_queues(num_worker_threads); + std::vector> cell_hashes_queues(num_worker_threads); + std::vector> shards_queues(num_worker_threads); + std::vector> duplicates_queues(num_worker_threads); + + ThreadPool thread_pool(num_worker_threads, [&](int i) { + while (std::optional c = cell_ranges_queues[i].pop_front()) { + cell_hashes_queues[i].push_back(thread_worker.compute_cell_hashes(*c)); + std::optional shards = shards_queues[i].pop_front(); + duplicates_queues[i].push_back(thread_worker.find_duplicate_cells(i, *shards)); + } + }); bool did_something = true; // A cell may have to go through a lot of collisions if the hash @@ -244,91 +399,99 @@ struct OptMergeWorker // beyond the user's control. while (did_something) { - std::vector cells; - cells.reserve(module->cells().size()); - for (auto cell : module->cells()) { - if (!design->selected(module, cell)) - continue; - if (cell->type.in(ID($meminit), ID($meminit_v2), ID($mem), ID($mem_v2))) { - // Ignore those for performance: meminit can have an excessively large port, - // mem can have an excessively large parameter holding the init data - continue; - } - if (cell->type == ID($scopeinfo)) - continue; - if (mode_keepdc && has_dont_care_initval(cell)) - continue; - if (!cell->known()) - continue; - if (!mode_share_all && !ct.cell_known(cell->type)) - continue; - cells.push_back(cell); - } + int cells_size = module->cells_size(); + log("Computing hashes of %d cells of `%s'.\n", cells_size, module->name); + std::vector>> sharded_bucketed_cell_hashes(workers); - did_something = false; - - // We keep a set of known cells. They're hashed with our hash_cell_function - // and compared with our compare_cell_parameters_and_connections. - // Both need to capture OptMergeWorker to access initvals - struct CellPtrHash { - const OptMergeWorker& worker; - CellPtrHash(const OptMergeWorker& w) : worker(w) {} - std::size_t operator()(const Cell* c) const { - return (std::size_t)worker.hash_cell_function(c, Hasher()).yield(); - } - }; - struct CellPtrEqual { - const OptMergeWorker& worker; - CellPtrEqual(const OptMergeWorker& w) : worker(w) {} - bool operator()(const Cell* lhs, const Cell* rhs) const { - return worker.compare_cell_parameters_and_connections(lhs, rhs); - } - }; - std::unordered_set< - RTLIL::Cell*, - CellPtrHash, - CellPtrEqual> known_cells (0, CellPtrHash(*this), CellPtrEqual(*this)); - - std::vector redirects; - for (auto cell : cells) + int cell_index = 0; + int cells_size_mod_workers = cells_size % workers; { - auto [cell_in_map, inserted] = known_cells.insert(cell); - if (!inserted) { - // We've failed to insert since we already have an equivalent cell - Cell* other_cell = *cell_in_map; - if (cell->has_keep_attr()) { - if (other_cell->has_keep_attr()) - continue; - known_cells.erase(other_cell); - known_cells.insert(cell); - std::swap(other_cell, cell); - } - - did_something = true; - log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name, other_cell->name); - for (auto &it : cell->connections()) { - if (cell->output(it.first)) { - RTLIL::SigSpec other_sig = other_cell->getPort(it.first); - log_debug(" Redirecting output %s: %s = %s\n", it.first, - log_signal(it.second), log_signal(other_sig)); - redirects.push_back(RTLIL::SigSig(it.second, std::move(other_sig))); - } - } - log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type, cell->name, module->name); - module->remove(cell); - total_count++; + Multithreading multithreading; + for (int i = 0; i < workers; ++i) { + int num_cells = cells_size/workers + ((i < cells_size_mod_workers) ? 1 : 0); + CellRange c = { cell_index, cell_index + num_cells }; + cell_index += num_cells; + if (num_worker_threads > 0) + cell_ranges_queues[i].push_back(c); + else + sharded_bucketed_cell_hashes[i] = std::move(thread_worker.compute_cell_hashes(c).bucketed_cell_hashes); } + log_assert(cell_index == cells_size); + if (num_worker_threads > 0) + for (int i = 0; i < workers; ++i) + sharded_bucketed_cell_hashes[i] = std::move(cell_hashes_queues[i].pop_front()->bucketed_cell_hashes); } - for (const RTLIL::SigSig &redirect : redirects) { - module->connect(redirect); - Const init = initvals(redirect.second); - initvals.remove_init(redirect.first); - initvals.remove_init(redirect.second); - assign_map.add(redirect.first, redirect.second); - initvals.set_init(redirect.second, init); + + log("Finding duplicate cells in `%s'.\n", module->name); + std::vector merged_duplicates; + { + Multithreading multithreading; + for (int i = 0; i < workers; ++i) { + Shards thread_shards = { sharded_bucketed_cell_hashes }; + if (num_worker_threads > 0) + shards_queues[i].push_back(thread_shards); + else { + std::vector d = std::move(thread_worker.find_duplicate_cells(i, thread_shards).duplicates); + merged_duplicates.insert(merged_duplicates.end(), d.begin(), d.end()); + } + } + if (num_worker_threads > 0) + for (int i = 0; i < workers; ++i) { + std::vector d = std::move(duplicates_queues[i].pop_front()->duplicates); + merged_duplicates.insert(merged_duplicates.end(), d.begin(), d.end()); + } } + std::sort(merged_duplicates.begin(), merged_duplicates.end(), [](const DuplicateCell &lhs, const DuplicateCell &rhs) { + // Sort them by the order in which duplicates would have been detected in a single-threaded + // run. The cell at which the duplicate would have been detected is the latter of the two + // cells involved. + return std::max(lhs.remove_cell, lhs.keep_cell) < std::max(rhs.remove_cell, rhs.keep_cell); + }); + + // Convert to cell pointers because removing cells will invalidate the indices. + std::vector> cell_ptrs; + for (DuplicateCell dup : merged_duplicates) + cell_ptrs.push_back({module->cell_at(dup.remove_cell), module->cell_at(dup.keep_cell)}); + + for (auto [remove_cell, keep_cell] : cell_ptrs) + { + log_debug(" Cell `%s' is identical to cell `%s'.\n", remove_cell->name, keep_cell->name); + for (auto &it : remove_cell->connections()) { + if (remove_cell->output(it.first)) { + RTLIL::SigSpec keep_sig = keep_cell->getPort(it.first); + log_debug(" Redirecting output %s: %s = %s\n", it.first, + log_signal(it.second), log_signal(keep_sig)); + Const init = initvals(keep_sig); + initvals.remove_init(it.second); + initvals.remove_init(keep_sig); + module->connect(RTLIL::SigSig(it.second, keep_sig)); + auto keep_sig_it = keep_sig.begin(); + for (SigBit remove_sig_bit : it.second) { + assign_map.add(remove_sig_bit, *keep_sig_it); + ++keep_sig_it; + } + initvals.set_init(keep_sig, init); + } + } + log_debug(" Removing %s cell `%s' from module `%s'.\n", remove_cell->type, remove_cell->name, module->name); + module->remove(remove_cell); + total_count++; + } + did_something = !merged_duplicates.empty(); } + for (ConcurrentQueue &q : cell_ranges_queues) + q.close(); + + for (ConcurrentQueue &q : shards_queues) + q.close(); + + for (ConcurrentQueue &q : cell_ranges_queues) + q.close(); + + for (ConcurrentQueue &q : shards_queues) + q.close(); + log_suppressed(); } }; @@ -381,9 +544,25 @@ struct OptMergePass : public Pass { } extra_args(args, argidx, design); + CellTypes ct; + ct.setup_internals(); + ct.setup_internals_mem(); + ct.setup_stdcells(); + ct.setup_stdcells_mem(); + if (mode_nomux) { + ct.cell_types.erase(ID($mux)); + ct.cell_types.erase(ID($pmux)); + } + ct.cell_types.erase(ID($tribuf)); + ct.cell_types.erase(ID($_TBUF_)); + ct.cell_types.erase(ID($anyseq)); + ct.cell_types.erase(ID($anyconst)); + ct.cell_types.erase(ID($allseq)); + ct.cell_types.erase(ID($allconst)); + int total_count = 0; for (auto module : design->selected_modules()) { - OptMergeWorker worker(design, module, mode_nomux, mode_share_all, mode_keepdc); + OptMergeWorker worker(module, ct, mode_share_all, mode_keepdc); total_count += worker.total_count; } From 41a098172d4328f96cad3b2bd7acc4e3c7d53f3f Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 8 Jan 2026 05:10:43 +0000 Subject: [PATCH 034/291] Expect an error from the bug5574.ys test --- tests/techmap/bug5574.ys | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/techmap/bug5574.ys b/tests/techmap/bug5574.ys index c347a0436..d986e688d 100644 --- a/tests/techmap/bug5574.ys +++ b/tests/techmap/bug5574.ys @@ -1,3 +1,4 @@ +logger -expect error "ABC: Error: This command can only be applied to an AIG" 1 read_verilog << EOT module fuzz_mwoqk (input i0, output o0); assign o0 = i0 ^ 1; From 991e7048993735cb072b913994cf81759c19df64 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Fri, 9 Jan 2026 00:26:46 +0000 Subject: [PATCH 035/291] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 3dc5f0fe0..a7e2020a4 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.60+88 +YOSYS_VER := 0.60+95 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 37347aacb2fddd8a79dcb372f89a79e981a22c76 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Mon, 29 Dec 2025 05:32:55 +0000 Subject: [PATCH 036/291] Check for missing port in SDC code I am getting weird crashes on `main` in `tests/sdc/alu_sub.ys` which I traced to a null `Wire*` in `SdcObjects::constrained_ports`. The null `Wire*` is being set in the `SdcObjects` constructor. I don't understand what's going on here, so I added this check to detect the missing wire early ... and that made the crash go away. Compiler bug maybe? I have `Debian clang version 19.1.7 (3+build5)`, default build configuration. Anyway this code seems fine to have. --- passes/cmds/sdc/sdc.cc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/passes/cmds/sdc/sdc.cc b/passes/cmds/sdc/sdc.cc index fad001e50..635aad016 100644 --- a/passes/cmds/sdc/sdc.cc +++ b/passes/cmds/sdc/sdc.cc @@ -165,7 +165,12 @@ struct SdcObjects { if (!top) log_error("Top module couldn't be determined. Check 'top' attribute usage"); for (auto port : top->ports) { - design_ports.push_back(std::make_pair(port.str().substr(1), top->wire(port))); + RTLIL::Wire *wire = top->wire(port); + if (!wire) { + // This should not be possible. See https://github.com/YosysHQ/yosys/pull/5594#issue-3791198573 + log_error("Port %s doesn't exist", log_id(port)); + } + design_ports.push_back(std::make_pair(port.str().substr(1), wire)); } std::list hierarchy{}; sniff_module(hierarchy, top); From 2b12b74121d01772c207ee90608486c8321d8498 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sun, 11 Jan 2026 15:23:38 +0100 Subject: [PATCH 037/291] musllinux fix so wheels build can work --- passes/techmap/abc.cc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index e25a6facd..88311fc2c 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -253,7 +253,11 @@ std::optional spawn_abc(const char* abc_exe, DeferredLogs &logs) { char arg1[] = "-s"; char* argv[] = { strdup(abc_exe), arg1, nullptr }; if (0 != posix_spawnp(&result.pid, abc_exe, &file_actions, nullptr, argv, environ)) { +#if defined(__GLIBC__) logs.log_error("posix_spawnp %s failed (errno=%s)", abc_exe, strerrorname_np(errno)); +#else + logs.log_error("posix_spawnp %s failed (errno=%s)", abc_exe, strerror(errno)); +#endif return std::nullopt; } free(argv[0]); From b3b71df07c38616e02cb4eab0757d6249dd6e12a Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 12 Jan 2026 15:38:45 +0100 Subject: [PATCH 038/291] musllinux fix so wheels build can work --- passes/techmap/abc.cc | 4 ---- 1 file changed, 4 deletions(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 88311fc2c..ad4dc5ccd 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -253,11 +253,7 @@ std::optional spawn_abc(const char* abc_exe, DeferredLogs &logs) { char arg1[] = "-s"; char* argv[] = { strdup(abc_exe), arg1, nullptr }; if (0 != posix_spawnp(&result.pid, abc_exe, &file_actions, nullptr, argv, environ)) { -#if defined(__GLIBC__) - logs.log_error("posix_spawnp %s failed (errno=%s)", abc_exe, strerrorname_np(errno)); -#else logs.log_error("posix_spawnp %s failed (errno=%s)", abc_exe, strerror(errno)); -#endif return std::nullopt; } free(argv[0]); From b8497217bca2e0cf12b72fb4a09f20197b4dee73 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 13 Jan 2026 00:16:58 +0100 Subject: [PATCH 039/291] contributing: review process --- .../extending_yosys/contributing.rst | 93 ++++++++++++++++--- 1 file changed, 82 insertions(+), 11 deletions(-) diff --git a/docs/source/yosys_internals/extending_yosys/contributing.rst b/docs/source/yosys_internals/extending_yosys/contributing.rst index 4d1a74b2f..458d7dc36 100644 --- a/docs/source/yosys_internals/extending_yosys/contributing.rst +++ b/docs/source/yosys_internals/extending_yosys/contributing.rst @@ -165,9 +165,16 @@ Code that matters If you're adding complex functionality, or modifying core parts of yosys, we highly recommend discussing your motivation and approach -ahead of time on the `Discourse forum`_. +ahead of time on the `Discourse forum`_. Please, be as explicit and concrete +as possible when explaining the motivation for what you're building. +Additionally, if you do so on the forum first before you starting hacking +away at C++, you might solve your problem without writing a single line +of code! -Before you build or fix something, search for existing `issues`_. +PRs are considered for relevance, priority, and quality +based on their descriptions first, code second. + +Before you build or fix something, also search for existing `issues`_. .. _`Discourse forum`: https://yosyshq.discourse.group/ .. _`issues`: https://github.com/YosysHQ/yosys/issues @@ -205,9 +212,10 @@ Here are some software engineering approaches that help: in coherent comments, and that variable and type naming is consistent with the terms you use in the description. * The logic of the implementation should be described in mathematical - or algorithm theory terms. Why would a non-trivial loop be guaranteed to terminate? - Is there some variant? Are you re-implementing a classic data structure from logic - synthesis? + or algorithm theory terms. Correctness, termination, computational complexity. + Make it clear if you're re-implementing a classic data structure for logic synthesis + or graph traversal etc. + * There's various ways of traversing the design with use-def indices (for getting drivers and driven signals) available in Yosys. They have advantages and sometimes disadvantages. Prefer not re-implementing these @@ -220,9 +228,10 @@ Here are some software engineering approaches that help: Common mistakes ~~~~~~~~~~~~~~~ -.. - Pointer invalidation when erasing design objects on a module while iterating -.. TODO figure out how it works again and describe it - +* Deleting design objects invalidates iterators. Defer deletions or hold a copy + of the list of pointers to design objects +* Deleting wires can get sketchy and is intended to be done solely by + the ``opt_clean`` pass so just don't do it * Iterating over an entire design and checking if things are selected is more inefficient than using the ``selected_*`` methods * Remember to call ``fixup_ports`` at the end if you're modifying module interfaces @@ -300,7 +309,69 @@ Some style hints: * Prefer smaller commits organized by good chunks. Git has a lot of features like fixup commits, interactive rebase with autosquash -.. Reviewing PRs -.. ------------- +Reviewing PRs +------------- -.. TODO Emil review process +Reviewing PRs is a totally valid form of external contributing to the project! + +Who's the reviewer? +~~~~~~~~~~~~~~~~~~~ + +Yosys HQ is a company with the inherited mandate to make decisions on behalf +of the open source project. As such, we at HQ are collectively the maintainers. +Within HQ, we allocate reviews based on expertise with the topic at hand +as well as member time constraints. + +If you're intimately acquainted with a part of the codebase, we will be happy +to defer to your experience and have you review PRs. The official way we like +is our CODEOWNERS file in the git repository. What we're looking for in code +owners is activity and trust. For activity, if you're only interested in +a yosys pass for example for the time you spend writing a thesis, it might be +better to focus on writing good tests and docs in the PRs you submit rather than +to commit to code ownership and therefore to be responsible for fixing things +and reviewing other people's PRs at various unexpected points later. If you're +prolific in some part of the codebase and not a code owner, we still value your +experience and may tag you in PRs. + +As a matter of fact, the purpose of code ownership is to avoid maintainer +burnout by removing orphaned parts of the codebase. If you become a code owner +and stop being responsive, in the future, we might decide to remove such code +if convenient and costly to maintain. It's simply more respectful of the users' +time to explicitly cut something out than let it "bitrot". Larger projects like +LLVM or linux could not survive without such things, but Yosys is far smaller, +and there are expectations + +.. TODO this deserves its own section elsewhere I think? But it would be distracting elsewhere + +Sometimes, multiple maintainers may add review comments. This is considered +healthy collaborative even if it might create disagreement at times. If +somebody is already reviewing a PR, others, even non-maintainers are free to +leave comments with extra observations and alternate perspectives in a +collaborative spirit. + +How to review +~~~~~~~~~~~~~ + +First, read everything above about contributing. Those are the values you +should gently enforce as a reviewer. They're ordered by importance, but +explicitly, descriptions are more important than code, long-form comments +describing the design are more important than piecemeal comments, etc. + +If a PR is poorly described, incomplete, tests are broken, or if the +author is not responding, please don't feel pressured to take over their +role by reverse engineering the code or fixing things for them, unless +there are good reasons to do so. + +If a PR author submits LLM outputs they haven't understood themselves, +they will not be able to implement feedback. Take this into consideration +as well. We do not ban LLM code from the codebase, we ban bad code. + +Reviewers may have diverse styles of communication while reviewing - one +may do one thorough review, another may prefer a back and forth with the +basics out the way before digging into the code. Generally, PRs may have +several requests for modifications and long discussions, but often +they just are good enough to merge as-is. + +The CI is required to go green for merging. New contributors need a CI +run to be triggered by a maintainer before their PRs take up computing +resources. It's a single click from the github web interface. From 78cbc21b94e5898bb6f9586e228d0d1c63668637 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 13 Jan 2026 00:22:49 +0000 Subject: [PATCH 040/291] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index a7e2020a4..3f287741f 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.60+95 +YOSYS_VER := 0.60+102 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 5ae48ee25f298f7b3c8c0de30bd2f85a94133031 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 13 Jan 2026 08:35:02 +0100 Subject: [PATCH 041/291] Release version 0.61 --- CHANGELOG | 12 +++++++++++- COPYING | 2 +- Makefile | 4 ++-- docs/source/conf.py | 4 ++-- 4 files changed, 16 insertions(+), 6 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 69f8ab1ce..252189ce8 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,8 +2,18 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.60 .. Yosys 0.61-dev +Yosys 0.60 .. Yosys 0.61 -------------------------- + * Various + - Removed "cover" pass for coverage tracking. + - Avoid merging formal properties with "opt_merge" pass. + - Parallelize "opt_merge" pass. + + * New commands and options + - Added "design_equal" pass to support fuzz-test comparison. + - Added "lut2bmux" pass to convert $lut to $bmux. + - Added "-legalize" option to "read_rtlil" pass to prevent + semantic errors. Yosys 0.59 .. Yosys 0.60 -------------------------- diff --git a/COPYING b/COPYING index 2d962dddc..a3ca45b42 100644 --- a/COPYING +++ b/COPYING @@ -1,6 +1,6 @@ ISC License -Copyright (C) 2012 - 2025 Claire Xenia Wolf +Copyright (C) 2012 - 2026 Claire Xenia Wolf Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above diff --git a/Makefile b/Makefile index 3f287741f..db7a115e8 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.60+102 +YOSYS_VER := 0.61 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) @@ -186,7 +186,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: - sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 5bafeb7.. | wc -l`/;" Makefile +# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 5bafeb7.. | wc -l`/;" Makefile ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q) diff --git a/docs/source/conf.py b/docs/source/conf.py index 01bb620ea..34f8be029 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -5,8 +5,8 @@ import os project = 'YosysHQ Yosys' author = 'YosysHQ GmbH' -copyright ='2025 YosysHQ GmbH' -yosys_ver = "0.60" +copyright ='2026 YosysHQ GmbH' +yosys_ver = "0.61" # select HTML theme html_theme = 'furo-ys' From b08e044994ffd32d94040931bc255313084d091d Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 13 Jan 2026 09:24:49 +0100 Subject: [PATCH 042/291] Next dev cycle --- CHANGELOG | 3 +++ Makefile | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 252189ce8..73c1606da 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ List of major changes and improvements between releases ======================================================= +Yosys 0.61 .. Yosys 0.62-dev +-------------------------- + Yosys 0.60 .. Yosys 0.61 -------------------------- * Various diff --git a/Makefile b/Makefile index db7a115e8..f2fc3e545 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.61 +YOSYS_VER := 0.61+0 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) @@ -186,7 +186,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: -# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 5bafeb7.. | wc -l`/;" Makefile + sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 5ae48ee.. | wc -l`/;" Makefile ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q) From 0e6973037d7ee6d216f3de2d5c17e34d48aa534b Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 13 Jan 2026 14:23:51 +0100 Subject: [PATCH 043/291] Update year in banner and license --- kernel/register.cc | 2 +- kernel/yosys.cc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/register.cc b/kernel/register.cc index 3f5aa49ca..abde8f47e 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -1204,7 +1204,7 @@ struct LicensePass : public Pass { log(" | |\n"); log(" | yosys -- Yosys Open SYnthesis Suite |\n"); log(" | |\n"); - log(" | Copyright (C) 2012 - 2025 Claire Xenia Wolf |\n"); + log(" | Copyright (C) 2012 - 2026 Claire Xenia Wolf |\n"); log(" | |\n"); log(" | Permission to use, copy, modify, and/or distribute this software for any |\n"); log(" | purpose with or without fee is hereby granted, provided that the above |\n"); diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 2c9b8304d..4264cb772 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -173,7 +173,7 @@ void yosys_banner() log("\n"); log(" /----------------------------------------------------------------------------\\\n"); log(" | yosys -- Yosys Open SYnthesis Suite |\n"); - log(" | Copyright (C) 2012 - 2025 Claire Xenia Wolf |\n"); + log(" | Copyright (C) 2012 - 2026 Claire Xenia Wolf |\n"); log(" | Distributed under an ISC-like license, type \"license\" to see terms |\n"); log(" \\----------------------------------------------------------------------------/\n"); log(" %s\n", yosys_maybe_version()); From 21e6833010348920eec3ec1baed8a1a634da4bae Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 13 Jan 2026 16:33:11 +0100 Subject: [PATCH 044/291] Makefile: no longer install ast.h and ast_binding.h --- Makefile | 2 -- 1 file changed, 2 deletions(-) diff --git a/Makefile b/Makefile index f2fc3e545..2fcc2fd95 100644 --- a/Makefile +++ b/Makefile @@ -645,8 +645,6 @@ $(eval $(call add_include_file,libs/sha1/sha1.h)) $(eval $(call add_include_file,libs/json11/json11.hpp)) $(eval $(call add_include_file,passes/fsm/fsmdata.h)) $(eval $(call add_include_file,passes/techmap/libparse.h)) -$(eval $(call add_include_file,frontends/ast/ast.h)) -$(eval $(call add_include_file,frontends/ast/ast_binding.h)) $(eval $(call add_include_file,frontends/blif/blifparse.h)) $(eval $(call add_include_file,backends/rtlil/rtlil_backend.h)) From 8e2038c4195e09b1002f3af61bbc0c6041510aea Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 24 Nov 2025 12:28:30 +0100 Subject: [PATCH 045/291] Use digit separators for large decimal integers --- kernel/log.cc | 6 +++--- passes/cmds/select.cc | 2 +- passes/opt/opt_muxtree.cc | 2 +- passes/techmap/extract_fa.cc | 8 ++++---- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/kernel/log.cc b/kernel/log.cc index 2a1261621..018a19081 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -90,11 +90,11 @@ int gettimeofday(struct timeval *tv, struct timezone *tz) QueryPerformanceFrequency(&freq); QueryPerformanceCounter(&counter); - counter.QuadPart *= 1000000; + counter.QuadPart *= 1'000'000; counter.QuadPart /= freq.QuadPart; tv->tv_sec = long(counter.QuadPart / 1000000); - tv->tv_usec = counter.QuadPart % 1000000; + tv->tv_usec = counter.QuadPart % 1'000'000; return 0; } @@ -135,7 +135,7 @@ static void logv_string(std::string_view format, std::string str) { initial_tv = tv; if (tv.tv_usec < initial_tv.tv_usec) { tv.tv_sec--; - tv.tv_usec += 1000000; + tv.tv_usec += 1'000'000; } tv.tv_sec -= initial_tv.tv_sec; tv.tv_usec -= initial_tv.tv_usec; diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 6da15c19a..0df47664f 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -570,7 +570,7 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char ct.setup(design); if (pos < int(arg.size()) && arg[pos] == '*') { - levels = 1000000; + levels = 1'000'000; pos++; } else if (pos < int(arg.size()) && '0' <= arg[pos] && arg[pos] <= '9') { diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 2f7d26dcf..0020af09f 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -64,7 +64,7 @@ struct OptMuxtreeWorker RTLIL::Module *module; SigMap assign_map; int removed_count; - int glob_evals_left = 10000000; + int glob_evals_left = 10'000'000; struct bitinfo_t { // Is bit directly used by non-mux cells or ports? diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc index 1984f82f5..46ab7e520 100644 --- a/passes/techmap/extract_fa.cc +++ b/passes/techmap/extract_fa.cc @@ -40,10 +40,10 @@ int bindec(unsigned char v) r += (~((v & 2) - 1)) & 10; r += (~((v & 4) - 1)) & 100; r += (~((v & 8) - 1)) & 1000; - r += (~((v & 16) - 1)) & 10000; - r += (~((v & 32) - 1)) & 100000; - r += (~((v & 64) - 1)) & 1000000; - r += (~((v & 128) - 1)) & 10000000; + r += (~((v & 16) - 1)) & 10'000; + r += (~((v & 32) - 1)) & 100'000; + r += (~((v & 64) - 1)) & 1'000'000; + r += (~((v & 128) - 1)) & 10'000'000; return r; } From 83c1364eeb0e0c8c2771c5fefdbfad6645c6e282 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 13 Jan 2026 18:47:23 +0100 Subject: [PATCH 046/291] read_verilog: remove log I left behind by accident --- frontends/verilog/verilog_frontend.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 6c9e67dc5..29a739f81 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -500,7 +500,6 @@ struct VerilogFrontend : public Frontend { log("Parsing %s%s input from `%s' to AST representation.\n", parse_mode.formal ? "formal " : "", parse_mode.sv ? "SystemVerilog" : "Verilog", filename.c_str()); - log("verilog frontend filename %s\n", filename.c_str()); if (flag_relative_share) { auto share_path = proc_share_dirname(); if (filename.substr(0, share_path.length()) == share_path) From 8b6925c5b022613a884afa3ef1c563408570a080 Mon Sep 17 00:00:00 2001 From: Natalia Kokoromyti Date: Tue, 13 Jan 2026 14:20:11 -0800 Subject: [PATCH 047/291] Add opt_balance_tree pass for timing optimization This pass converts cascaded chains of arithmetic and logic cells ($add, $mul, $and, $or, $xor) into balanced binary trees to improve timing performance in hardware synthesis. The optimization uses a breadth-first search approach to identify chains of compatible cells, then recursively constructs balanced trees that reduce the critical path depth. Features: - Supports arithmetic cells: $add, $mul - Supports logic cells: $and, $or, $xor - Command-line options: -arith (arithmetic only), -logic (logic only) - Preserves signed/unsigned semantics - Comprehensive test suite with 30 test cases Original implementation by Akash Levy for Silimate. Upstreamed from https://github.com/Silimate/yosys --- passes/opt/Makefile.inc | 1 + passes/opt/opt_balance_tree.cc | 355 +++++++++ tests/opt/opt_balance_tree.ys | 1356 ++++++++++++++++++++++++++++++++ 3 files changed, 1712 insertions(+) create mode 100644 passes/opt/opt_balance_tree.cc create mode 100644 tests/opt/opt_balance_tree.ys diff --git a/passes/opt/Makefile.inc b/passes/opt/Makefile.inc index 426d9a79a..5dee824ff 100644 --- a/passes/opt/Makefile.inc +++ b/passes/opt/Makefile.inc @@ -23,6 +23,7 @@ OBJS += passes/opt/opt_lut_ins.o OBJS += passes/opt/opt_ffinv.o OBJS += passes/opt/pmux2shiftx.o OBJS += passes/opt/muxpack.o +OBJS += passes/opt/opt_balance_tree.o OBJS += passes/opt/peepopt.o GENFILES += passes/opt/peepopt_pm.h diff --git a/passes/opt/opt_balance_tree.cc b/passes/opt/opt_balance_tree.cc new file mode 100644 index 000000000..273a74af3 --- /dev/null +++ b/passes/opt/opt_balance_tree.cc @@ -0,0 +1,355 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * 2019 Eddie Hung + * 2024 Akash Levy + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + + +struct OptBalanceTreeWorker { + // Module and signal map + Module *module; + SigMap sigmap; + + // Counts of each cell type that are getting balanced + dict cell_count; + + // Check if cell is of the right type and has matching input/output widths + bool is_right_type(Cell* cell, IdString cell_type) { + return cell->type == cell_type && + cell->getParam(ID::Y_WIDTH).as_int() >= cell->getParam(ID::A_WIDTH).as_int() && + cell->getParam(ID::Y_WIDTH).as_int() >= cell->getParam(ID::B_WIDTH).as_int(); + } + + // Create a balanced binary tree from a vector of source signals + SigSpec create_balanced_tree(vector &sources, IdString cell_type, Cell* cell) { + // Base case: if we have no sources, return an empty signal + if (sources.size() == 0) + return SigSpec(); + + // Base case: if we have only one source, return it + if (sources.size() == 1) + return sources[0]; + + // Base case: if we have two sources, create a single cell + if (sources.size() == 2) { + // Create a new cell of the same type + Cell* new_cell = module->addCell(NEW_ID, cell_type); + + // Copy attributes from reference cell + new_cell->attributes = cell->attributes; + + // Create output wire + int out_width = cell->getParam(ID::Y_WIDTH).as_int(); + if (cell_type == ID($add)) + out_width = max(sources[0].size(), sources[1].size()) + 1; + else if (cell_type == ID($mul)) + out_width = sources[0].size() + sources[1].size(); + Wire* out_wire = module->addWire(NEW_ID, out_width); + + // Connect ports and fix up parameters + new_cell->setPort(ID::A, sources[0]); + new_cell->setPort(ID::B, sources[1]); + new_cell->setPort(ID::Y, out_wire); + new_cell->fixup_parameters(); + new_cell->setParam(ID::A_SIGNED, cell->getParam(ID::A_SIGNED)); + new_cell->setParam(ID::B_SIGNED, cell->getParam(ID::B_SIGNED)); + + // Update count and return output wire + cell_count[cell_type]++; + return out_wire; + } + + // Recursive case: split sources into two groups and create subtrees + int mid = (sources.size() + 1) / 2; + vector left_sources(sources.begin(), sources.begin() + mid); + vector right_sources(sources.begin() + mid, sources.end()); + + SigSpec left_tree = create_balanced_tree(left_sources, cell_type, cell); + SigSpec right_tree = create_balanced_tree(right_sources, cell_type, cell); + + // Create a cell to combine the two subtrees + Cell* new_cell = module->addCell(NEW_ID, cell_type); + + // Copy attributes from reference cell + new_cell->attributes = cell->attributes; + + // Create output wire + int out_width = cell->getParam(ID::Y_WIDTH).as_int(); + if (cell_type == ID($add)) + out_width = max(left_tree.size(), right_tree.size()) + 1; + else if (cell_type == ID($mul)) + out_width = left_tree.size() + right_tree.size(); + Wire* out_wire = module->addWire(NEW_ID, out_width); + + // Connect ports and fix up parameters + new_cell->setPort(ID::A, left_tree); + new_cell->setPort(ID::B, right_tree); + new_cell->setPort(ID::Y, out_wire); + new_cell->fixup_parameters(); + new_cell->setParam(ID::A_SIGNED, cell->getParam(ID::A_SIGNED)); + new_cell->setParam(ID::B_SIGNED, cell->getParam(ID::B_SIGNED)); + + // Update count and return output wire + cell_count[cell_type]++; + return out_wire; + } + + OptBalanceTreeWorker(Module *module, const vector cell_types) : module(module), sigmap(module) { + // Do for each cell type + for (auto cell_type : cell_types) { + // Index all of the nets in the module + dict sig_to_driver; + dict> sig_to_sink; + for (auto cell : module->selected_cells()) + { + for (auto &conn : cell->connections()) + { + if (cell->output(conn.first)) + sig_to_driver[sigmap(conn.second)] = cell; + + if (cell->input(conn.first)) + { + SigSpec sig = sigmap(conn.second); + if (sig_to_sink.count(sig) == 0) + sig_to_sink[sig] = pool(); + sig_to_sink[sig].insert(cell); + } + } + } + + // Need to check if any wires connect to module ports + pool input_port_sigs; + pool output_port_sigs; + for (auto wire : module->selected_wires()) + if (wire->port_input || wire->port_output) { + SigSpec sig = sigmap(wire); + for (auto bit : sig) { + if (wire->port_input) + input_port_sigs.insert(bit); + if (wire->port_output) + output_port_sigs.insert(bit); + } + } + + // Actual logic starts here + pool consumed_cells; + for (auto cell : module->selected_cells()) + { + // If consumed or not the correct type, skip + if (consumed_cells.count(cell) || !is_right_type(cell, cell_type)) + continue; + + // BFS, following all chains until they hit a cell of a different type + // Pick the longest one + auto y = sigmap(cell->getPort(ID::Y)); + pool sinks; + pool current_loads = sig_to_sink[y]; + pool next_loads; + while (!current_loads.empty()) + { + // Find each sink and see what they are + for (auto x : current_loads) + { + // If not the correct type, don't follow any further + // (but add the originating cell to the list of sinks) + if (!is_right_type(x, cell_type)) + { + sinks.insert(cell); + continue; + } + + auto xy = sigmap(x->getPort(ID::Y)); + + // If this signal drives a port, add it to the sinks + // (even though it may not be the end of a chain) + for (auto bit : xy) { + if (output_port_sigs.count(bit) && !consumed_cells.count(x)) { + sinks.insert(x); + break; + } + } + + // Search signal's fanout + auto& next = sig_to_sink[xy]; + for (auto z : next) + next_loads.insert(z); + } + + // If we couldn't find any downstream loads, stop. + // Create a reduction for each of the max-length chains we found + if (next_loads.empty()) + { + for (auto s : current_loads) + { + // Not one of our gates? Don't follow any further + if (!is_right_type(s, cell_type)) + continue; + + sinks.insert(s); + } + break; + } + + // Otherwise, continue down the chain + current_loads = next_loads; + next_loads.clear(); + } + + // We have our list of sinks, now go tree balance the chains + for (auto head_cell : sinks) + { + // Avoid duplication if we already were covered + if (consumed_cells.count(head_cell)) + continue; + + // Get sources of the chain + dict sources; + dict signeds; + int inner_cells = 0; + std::deque bfs_queue = {head_cell}; + while (bfs_queue.size()) + { + Cell* x = bfs_queue.front(); + bfs_queue.pop_front(); + + for (IdString port: {ID::A, ID::B}) { + auto sig = sigmap(x->getPort(port)); + Cell* drv = sig_to_driver[sig]; + bool drv_ok = drv && is_right_type(drv, cell_type); + for (auto bit : sig) { + if (input_port_sigs.count(bit) && !consumed_cells.count(drv)) { + drv_ok = false; + break; + } + } + if (drv_ok) { + inner_cells++; + bfs_queue.push_back(drv); + } else { + sources[sig]++; + signeds[sig] = x->getParam(port == ID::A ? ID::A_SIGNED : ID::B_SIGNED).as_bool(); + } + } + } + + if (inner_cells) + { + // Create a tree + log_debug(" Creating tree for %s with %d sources and %d inner cells...\n", log_id(head_cell), GetSize(sources), inner_cells); + + // Build a vector of all source signals + vector source_signals; + vector signed_flags; + for (auto &source : sources) { + for (int i = 0; i < source.second; i++) { + source_signals.push_back(source.first); + signed_flags.push_back(signeds[source.first]); + } + } + + // If not all signed flags are the same, do not balance + if (!std::all_of(signed_flags.begin(), signed_flags.end(), [&](bool flag) { return flag == signed_flags[0]; })) { + continue; + } + + // Create the balanced tree + SigSpec tree_output = create_balanced_tree(source_signals, cell_type, head_cell); + + // Connect the tree output to the head cell's output + SigSpec head_output = sigmap(head_cell->getPort(ID::Y)); + int connect_width = std::min(head_output.size(), tree_output.size()); + module->connect(head_output.extract(0, connect_width), tree_output.extract(0, connect_width)); + if (head_output.size() > tree_output.size()) { + SigBit sext_bit = head_cell->getParam(ID::A_SIGNED).as_bool() ? head_output[connect_width - 1] : State::S0; + module->connect(head_output.extract(connect_width, head_output.size() - connect_width), SigSpec(sext_bit, head_output.size() - connect_width)); + } + + // Mark consumed cell for removal + consumed_cells.insert(head_cell); + } + } + } + + // Remove all consumed cells, which now have been replaced by trees + for (auto cell : consumed_cells) + module->remove(cell); + } + } +}; + +struct OptBalanceTreePass : public Pass { + OptBalanceTreePass() : Pass("opt_balance_tree", "$and/$or/$xor/$add/$mul cascades to trees") { } + void help() override { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" opt_balance_tree [options] [selection]\n"); + log("\n"); + log("This pass converts cascaded chains of $and/$or/$xor/$add/$mul cells into\n"); + log("trees of cells to improve timing.\n"); + log("\n"); + log(" -arith\n"); + log(" only convert arithmetic cells.\n"); + log("\n"); + log(" -logic\n"); + log(" only convert logic cells.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) override { + log_header(design, "Executing OPT_BALANCE_TREE pass (cell cascades to trees).\n"); + + // Handle arguments + size_t argidx; + vector cell_types = {ID($and), ID($or), ID($xor), ID($add), ID($mul)}; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-arith") { + cell_types = {ID($add), ID($mul)}; + continue; + } + if (args[argidx] == "-logic") { + cell_types = {ID($and), ID($or), ID($xor)}; + continue; + } + break; + } + extra_args(args, argidx, design); + + // Count of all cells that were packed + dict cell_count; + for (auto module : design->selected_modules()) { + OptBalanceTreeWorker worker(module, cell_types); + for (auto cell : worker.cell_count) { + cell_count[cell.first] += cell.second; + } + } + + // Log stats + for (auto cell_type : cell_types) + log("Converted %d %s cells into trees.\n", cell_count[cell_type], log_id(cell_type)); + + // Clean up + Yosys::run_pass("clean -purge"); + } +} OptBalanceTreePass; + +PRIVATE_NAMESPACE_END diff --git a/tests/opt/opt_balance_tree.ys b/tests/opt/opt_balance_tree.ys new file mode 100644 index 000000000..508f5fc24 --- /dev/null +++ b/tests/opt/opt_balance_tree.ys @@ -0,0 +1,1356 @@ +# Test 1 +log -header "Simple AND chain" +log -push +design -reset +read_verilog <signed + + // Combine with unsigned offset + assign result = sum_full + $signed({6'b0, unsigned_offset}); +endmodule +EOF +check -assert + +# Check equivalence after opt_balance_tree +equiv_opt -assert opt_balance_tree +design -load postopt + +# Width reduction +equiv_opt -assert wreduce +design -load postopt + +design -reset +log -pop + + + +# Test 30 +log -header "Complex signedness with conditional sign extension" +log -push +design -reset +read_verilog < Date: Tue, 13 Jan 2026 14:43:52 -0800 Subject: [PATCH 048/291] restore extra_args --- passes/techmap/lut2mux.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc index 28f466874..0da58f95d 100644 --- a/passes/techmap/lut2mux.cc +++ b/passes/techmap/lut2mux.cc @@ -90,7 +90,8 @@ struct Lut2muxPass : public Pass { } break; } - + extra_args(args, argidx, design); + for (auto module : design->selected_modules()) for (auto cell : module->selected_cells()) { if (cell->type == ID($lut)) { From 6a93a94d9ffa31ea4d3f72b28c21b3e0f5fbae68 Mon Sep 17 00:00:00 2001 From: nataliakokoromyti <126305457+nataliakokoromyti@users.noreply.github.com> Date: Tue, 13 Jan 2026 14:44:51 -0800 Subject: [PATCH 049/291] fix line --- passes/techmap/lut2mux.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc index 0da58f95d..d1d2284f0 100644 --- a/passes/techmap/lut2mux.cc +++ b/passes/techmap/lut2mux.cc @@ -91,7 +91,6 @@ struct Lut2muxPass : public Pass { break; } extra_args(args, argidx, design); - for (auto module : design->selected_modules()) for (auto cell : module->selected_cells()) { if (cell->type == ID($lut)) { From 40f9e235de23073421816f58c2e5bc043e5fb28f Mon Sep 17 00:00:00 2001 From: nataliakokoromyti <126305457+nataliakokoromyti@users.noreply.github.com> Date: Tue, 13 Jan 2026 14:45:46 -0800 Subject: [PATCH 050/291] Update lut2mux.cc --- passes/techmap/lut2mux.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc index d1d2284f0..0da58f95d 100644 --- a/passes/techmap/lut2mux.cc +++ b/passes/techmap/lut2mux.cc @@ -91,6 +91,7 @@ struct Lut2muxPass : public Pass { break; } extra_args(args, argidx, design); + for (auto module : design->selected_modules()) for (auto cell : module->selected_cells()) { if (cell->type == ID($lut)) { From 8a596f330a343e4c52a5f89edc875c825dc41513 Mon Sep 17 00:00:00 2001 From: nataliakokoromyti <126305457+nataliakokoromyti@users.noreply.github.com> Date: Tue, 13 Jan 2026 14:56:24 -0800 Subject: [PATCH 051/291] Update lut2mux.cc --- passes/techmap/lut2mux.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc index 0da58f95d..3d45734ec 100644 --- a/passes/techmap/lut2mux.cc +++ b/passes/techmap/lut2mux.cc @@ -91,7 +91,7 @@ struct Lut2muxPass : public Pass { break; } extra_args(args, argidx, design); - + for (auto module : design->selected_modules()) for (auto cell : module->selected_cells()) { if (cell->type == ID($lut)) { From 6aef8ea8ab28702b4429147ddbea825ca4715582 Mon Sep 17 00:00:00 2001 From: Natalia Kokoromyti Date: Tue, 13 Jan 2026 15:31:46 -0800 Subject: [PATCH 052/291] Add missing include for MSVC compatibility --- passes/opt/opt_balance_tree.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/passes/opt/opt_balance_tree.cc b/passes/opt/opt_balance_tree.cc index 273a74af3..8811b1331 100644 --- a/passes/opt/opt_balance_tree.cc +++ b/passes/opt/opt_balance_tree.cc @@ -21,6 +21,7 @@ #include "kernel/yosys.h" #include "kernel/sigtools.h" +#include USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN From 4c1a18f01dffa18442c1a7efa20f9c289f18583c Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 14 Jan 2026 06:40:44 +0000 Subject: [PATCH 053/291] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 2fcc2fd95..00d20bb9a 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.61+0 +YOSYS_VER := 0.61+18 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 210b733555a83cea868c87522d6ed665876d18bb Mon Sep 17 00:00:00 2001 From: nella Date: Wed, 14 Jan 2026 15:37:18 +0100 Subject: [PATCH 054/291] Add rtlil string getters --- kernel/rtlil.cc | 43 ++++++++++++++++++++ kernel/rtlil.h | 9 ++++ tests/unit/kernel/rtlilStringTest.cc | 61 ++++++++++++++++++++++++++++ 3 files changed, 113 insertions(+) create mode 100644 tests/unit/kernel/rtlilStringTest.cc diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 0dbe8bb13..0103cabfb 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -31,6 +31,7 @@ #include #include #include +#include YOSYS_NAMESPACE_BEGIN @@ -1548,6 +1549,13 @@ void RTLIL::Design::pop_selection() push_full_selection(); } +std::string RTLIL::Design::to_rtlil_str(bool only_selected) const +{ + std::ostringstream f; + RTLIL_BACKEND::dump_design(f, const_cast(this), only_selected); + return f.str(); +} + std::vector RTLIL::Design::selected_modules(RTLIL::SelectPartials partials, RTLIL::SelectBoxes boxes) const { bool include_partials = partials == RTLIL::SELECT_ALL; @@ -4288,6 +4296,13 @@ RTLIL::SigSpec RTLIL::Module::FutureFF(RTLIL::IdString name, const RTLIL::SigSpe return sig; } +std::string RTLIL::Module::to_rtlil_str() const +{ + std::ostringstream f; + RTLIL_BACKEND::dump_module(f, "", const_cast(this), design, false); + return f.str(); +} + RTLIL::Wire::Wire() { static unsigned int hashidx_count = 123456789; @@ -4315,6 +4330,13 @@ RTLIL::Wire::~Wire() #endif } +std::string RTLIL::Wire::to_rtlil_str() const +{ + std::ostringstream f; + RTLIL_BACKEND::dump_wire(f, "", this); + return f.str(); +} + #ifdef YOSYS_ENABLE_PYTHON static std::map all_wires; std::map *RTLIL::Wire::get_all_wires(void) @@ -4337,6 +4359,13 @@ RTLIL::Memory::Memory() #endif } +std::string RTLIL::Memory::to_rtlil_str() const +{ + std::ostringstream f; + RTLIL_BACKEND::dump_memory(f, "", this); + return f.str(); +} + RTLIL::Process::Process() : module(nullptr) { static unsigned int hashidx_count = 123456789; @@ -4344,6 +4373,13 @@ RTLIL::Process::Process() : module(nullptr) hashidx_ = hashidx_count; } +std::string RTLIL::Process::to_rtlil_str() const +{ + std::ostringstream f; + RTLIL_BACKEND::dump_proc(f, "", this); + return f.str(); +} + RTLIL::Cell::Cell() : module(nullptr) { static unsigned int hashidx_count = 123456789; @@ -4365,6 +4401,13 @@ RTLIL::Cell::~Cell() #endif } +std::string RTLIL::Cell::to_rtlil_str() const +{ + std::ostringstream f; + RTLIL_BACKEND::dump_cell(f, "", this); + return f.str(); +} + #ifdef YOSYS_ENABLE_PYTHON static std::map all_cells; std::map *RTLIL::Cell::get_all_cells(void) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index e3a5a3bf8..fe280c965 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -2032,6 +2032,8 @@ struct RTLIL::Design // partially selected or boxed modules have been ignored std::vector selected_unboxed_whole_modules_warn() const { return selected_modules(SELECT_WHOLE_WARN, SB_UNBOXED_WARN); } static std::map *get_all_designs(void); + + std::string to_rtlil_str(bool only_selected = true) const; }; struct RTLIL::Module : public RTLIL::NamedObject @@ -2395,6 +2397,7 @@ public: RTLIL::SigSpec OriginalTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = ""); RTLIL::SigSpec FutureFF (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = ""); + std::string to_rtlil_str() const; #ifdef YOSYS_ENABLE_PYTHON static std::map *get_all_modules(void); #endif @@ -2448,6 +2451,7 @@ public: return zero_index + start_offset; } + std::string to_rtlil_str() const; #ifdef YOSYS_ENABLE_PYTHON static std::map *get_all_wires(void); #endif @@ -2465,6 +2469,8 @@ struct RTLIL::Memory : public RTLIL::NamedObject Memory(); int width, start_offset, size; + + std::string to_rtlil_str() const; #ifdef YOSYS_ENABLE_PYTHON ~Memory(); static std::map *get_all_memorys(void); @@ -2523,6 +2529,8 @@ public: template void rewrite_sigspecs(T &functor); template void rewrite_sigspecs2(T &functor); + std::string to_rtlil_str() const; + #ifdef YOSYS_ENABLE_PYTHON static std::map *get_all_cells(void); #endif @@ -2601,6 +2609,7 @@ public: template void rewrite_sigspecs(T &functor); template void rewrite_sigspecs2(T &functor); RTLIL::Process *clone() const; + std::string to_rtlil_str() const; }; diff --git a/tests/unit/kernel/rtlilStringTest.cc b/tests/unit/kernel/rtlilStringTest.cc new file mode 100644 index 000000000..26b296dd4 --- /dev/null +++ b/tests/unit/kernel/rtlilStringTest.cc @@ -0,0 +1,61 @@ +#include + +#include "kernel/rtlil.h" +#include "kernel/yosys.h" + +YOSYS_NAMESPACE_BEGIN + +namespace RTLIL { + + TEST(RtlilStrTest, DesignToString) { + Design design; + Module *mod = design.addModule(ID(my_module)); + mod->addWire(ID(my_wire), 1); + + std::string design_str = design.to_rtlil_str(); + + EXPECT_NE(design_str.find("module \\my_module"), std::string::npos); + EXPECT_NE(design_str.find("end"), std::string::npos); + } + + TEST(RtlilStrTest, ModuleToString) { + Design design; + Module *mod = design.addModule(ID(test_mod)); + Wire *wire = mod->addWire(ID(clk), 1); + wire->port_input = true; + + std::string mod_str = mod->to_rtlil_str(); + + EXPECT_NE(mod_str.find("module \\test_mod"), std::string::npos); + EXPECT_NE(mod_str.find("wire"), std::string::npos); + EXPECT_NE(mod_str.find("\\clk"), std::string::npos); + EXPECT_NE(mod_str.find("input"), std::string::npos); + } + + TEST(RtlilStrTest, WireToString) { + Design design; + Module *mod = design.addModule(ID(m)); + Wire *wire = mod->addWire(ID(data), 8); + + std::string wire_str = wire->to_rtlil_str(); + + EXPECT_NE(wire_str.find("wire"), std::string::npos); + EXPECT_NE(wire_str.find("width 8"), std::string::npos); + EXPECT_NE(wire_str.find("\\data"), std::string::npos); + } + + TEST(RtlilStrTest, CellToString) { + Design design; + Module *mod = design.addModule(ID(m)); + Cell *cell = mod->addCell(ID(u1), ID(my_cell_type)); + + std::string cell_str = cell->to_rtlil_str(); + + EXPECT_NE(cell_str.find("cell"), std::string::npos); + EXPECT_NE(cell_str.find("\\my_cell_type"), std::string::npos); + EXPECT_NE(cell_str.find("\\u1"), std::string::npos); + } + +} + +YOSYS_NAMESPACE_END From e0077b188d2bd7e1ad32577651509d4a13346b90 Mon Sep 17 00:00:00 2001 From: kamay Date: Tue, 4 Mar 2025 11:31:59 +0100 Subject: [PATCH 055/291] Add gatesi_mode in BLIF format --- backends/blif/blif.cc | 32 +++++++++++++++++++++++++------- frontends/blif/blifparse.cc | 21 +++++++++++++++++++++ 2 files changed, 46 insertions(+), 7 deletions(-) diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index ab7861802..85db8679e 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -44,6 +44,7 @@ struct BlifDumperConfig bool iattr_mode; bool blackbox_mode; bool noalias_mode; + bool gatesi_mode; std::string buf_type, buf_in, buf_out; std::map> unbuf_types; @@ -51,7 +52,7 @@ struct BlifDumperConfig BlifDumperConfig() : icells_mode(false), conn_mode(false), impltf_mode(false), gates_mode(false), cname_mode(false), iname_mode(false), param_mode(false), attr_mode(false), iattr_mode(false), - blackbox_mode(false), noalias_mode(false) { } + blackbox_mode(false), noalias_mode(false), gatesi_mode(false) { } }; struct BlifDumper @@ -118,16 +119,21 @@ struct BlifDumper return str; } - const std::string str_init(RTLIL::SigBit sig) + template const std::string str_init(RTLIL::SigBit sig) { sigmap.apply(sig); - if (init_bits.count(sig) == 0) - return " 2"; + if (init_bits.count(sig) == 0) { + if constexpr (Space) + return " 2"; + else + return "2"; + } - string str = stringf(" %d", init_bits.at(sig)); - - return str; + if constexpr (Space) + return stringf(" %d", init_bits.at(sig)); + else + return stringf("%d", init_bits.at(sig)); } const char *subckt_or_gate(std::string cell_type) @@ -469,6 +475,11 @@ struct BlifDumper f << stringf(".names %s %s\n1 1\n", str(rhs_bit), str(lhs_bit)); } + if (config->gatesi_mode) { + for (auto &&init_bit : init_bits) + f << stringf(".gateinit %s=%s\n", str(init_bit.first), str_init(init_bit.first)); + } + f << stringf(".end\n"); } @@ -550,6 +561,9 @@ struct BlifBackend : public Backend { log(" -impltf\n"); log(" do not write definitions for the $true, $false and $undef wires.\n"); log("\n"); + log(" -gatesi\n"); + log(" write initial bit(s) with .gateinit for gates that needs to be initialized.\n"); + log("\n"); } void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { @@ -640,6 +654,10 @@ struct BlifBackend : public Backend { config.noalias_mode = true; continue; } + if (args[argidx] == "-gatesi") { + config.gatesi_mode = true; + continue; + } break; } extra_args(f, filename, args, argidx); diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index bff347ea2..30512d324 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -470,6 +470,27 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool continue; } + if (!strcmp(cmd, ".gateinit")) + { + char *p = strtok(NULL, " \t\r\n"); + if (p == NULL) + goto error; + + char *n = strtok(p, "="); + char *init = strtok(NULL, "="); + if (n == NULL || init == NULL) + goto error; + if (init[0] != '0' && init[0] != '1') + goto error; + + if (blif_wire(n)->attributes.find(ID::init) == blif_wire(n)->attributes.end()) + blif_wire(n)->attributes.emplace(ID::init, Const(init[0] == '1' ? 1 : 0, 1)); + else + blif_wire(n)->attributes[ID::init] = Const(init[0] == '1' ? 1 : 0, 1); + + continue; + } + if (!strcmp(cmd, ".names")) { char *p; From ddf3c6c8b7e71f227a2d3d800eaca24d68b7b22e Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 13 Jan 2026 22:53:16 +0100 Subject: [PATCH 056/291] blif: add -gatesi test --- tests/blif/.gitignore | 1 + tests/blif/gatesi.blif | 480 +++++++++++++++++++++++++++++++++++++ tests/blif/gatesi.blif.ok | 484 ++++++++++++++++++++++++++++++++++++++ tests/blif/gatesi.ys | 2 + tests/blif/run-test.sh | 6 +- 5 files changed, 972 insertions(+), 1 deletion(-) create mode 100644 tests/blif/.gitignore create mode 100644 tests/blif/gatesi.blif create mode 100644 tests/blif/gatesi.blif.ok create mode 100644 tests/blif/gatesi.ys diff --git a/tests/blif/.gitignore b/tests/blif/.gitignore new file mode 100644 index 000000000..e87afd97c --- /dev/null +++ b/tests/blif/.gitignore @@ -0,0 +1 @@ +/*.out diff --git a/tests/blif/gatesi.blif b/tests/blif/gatesi.blif new file mode 100644 index 000000000..d6fa4d5c9 --- /dev/null +++ b/tests/blif/gatesi.blif @@ -0,0 +1,480 @@ +# Generated by Yosys 0.60+88 (git sha1 69b604104, g++ 15.2.1 -fPIC -O3) + +.model test +.inputs clk in_a_var[0] in_a_var[1] in_a_var[2] in_a_var[3] in_a_var[4] in_a_var[5] in_a_var[6] in_a_var[7] in_b_var[0] in_b_var[1] in_b_var[2] in_b_var[3] in_b_var[4] in_b_var[5] in_b_var[6] in_b_var[7] +.outputs out_var[0] out_var[1] out_var[2] out_var[3] out_var[4] out_var[5] out_var[6] out_var[7] +.gate ORNOT A=:1.test_1[0] B=in_a_var[0] Y=$abc$2385$new_n57 +.gate ORNOT A=in_a_var[0] B=:1.test_1[0] Y=$abc$2385$new_n58 +.gate XNOR A=:1.test_1[0] B=in_a_var[0] Y=$abc$2385$new_n59 +.gate NAND A=in_b_var[0] B=$abc$2385$new_n59 Y=$abc$2385$new_n60 +.gate XOR A=in_b_var[0] B=$abc$2385$new_n59 Y=$abc$2385$auto$maccmap.cc:114:fulladd$252.Y[0] +.gate NAND A=$abc$2385$new_n57 B=$abc$2385$new_n60 Y=$abc$2385$new_n62 +.gate NOR A=:1.test_1[0] B=:1.test_1[1] Y=$abc$2385$new_n63 +.gate AND A=:1.test_1[0] B=:1.test_1[1] Y=$abc$2385$new_n64 +.gate XOR A=:1.test_1[0] B=:1.test_1[1] Y=$abc$2385$new_n65 +.gate NOT A=$abc$2385$new_n65 Y=$abc$2385$new_n66 +.gate AND A=:1.test_1[2] B=$abc$2385$new_n64 Y=$abc$2385$new_n67 +.gate AND A=:1.test_1[3] B=$abc$2385$new_n67 Y=$abc$2385$new_n68 +.gate AND A=:1.test_1[4] B=$abc$2385$new_n68 Y=$abc$2385$new_n69 +.gate AND A=:1.test_1[5] B=$abc$2385$new_n69 Y=$abc$2385$new_n70 +.gate AND A=:1.test_1[6] B=$abc$2385$new_n70 Y=$abc$2385$new_n71 +.gate XNOR A=:1.test_1[6] B=$abc$2385$new_n70 Y=$abc$2385$new_n72 +.gate NOT A=$abc$2385$new_n72 Y=$abc$2385$new_n73 +.gate AND A=:1.test_1[7] B=$abc$2385$new_n71 Y=$abc$2385$new_n74 +.gate XNOR A=:1.test_1[7] B=$abc$2385$new_n71 Y=$abc$2385$new_n75 +.gate ANDNOT A=:1.test_1[5] B=$abc$2385$new_n69 Y=$abc$2385$new_n76 +.gate XNOR A=:1.test_1[5] B=$abc$2385$new_n69 Y=$abc$2385$new_n77 +.gate NOR A=:1.test_1[3] B=:1.test_1[4] Y=$abc$2385$new_n78 +.gate AND A=$abc$2385$new_n63 B=$abc$2385$new_n78 Y=$abc$2385$new_n79 +.gate ANDNOT A=$abc$2385$new_n79 B=:1.test_1[2] Y=$abc$2385$new_n80 +.gate AND A=$abc$2385$new_n77 B=$abc$2385$new_n80 Y=$abc$2385$new_n81 +.gate NAND A=$abc$2385$new_n75 B=$abc$2385$new_n81 Y=$abc$2385$new_n82 +.gate OR A=$abc$2385$new_n73 B=$abc$2385$new_n82 Y=$abc$2385$new_n83 +.gate AND A=$abc$2385$new_n66 B=$abc$2385$new_n83 Y=$abc$2385$new_n84 +.gate ORNOT A=$abc$2385$new_n84 B=in_a_var[1] Y=$abc$2385$new_n85 +.gate XNOR A=in_a_var[1] B=$abc$2385$new_n84 Y=$abc$2385$new_n86 +.gate NAND A=in_b_var[1] B=$abc$2385$new_n86 Y=$abc$2385$new_n87 +.gate XNOR A=in_b_var[1] B=$abc$2385$new_n86 Y=$abc$2385$new_n88 +.gate ANDNOT A=$abc$2385$new_n62 B=$abc$2385$new_n88 Y=$abc$2385$new_n89 +.gate AND A=$abc$2385$new_n85 B=$abc$2385$new_n87 Y=$abc$2385$new_n90 +.gate XNOR A=:1.test_1[2] B=$abc$2385$new_n64 Y=$abc$2385$new_n91 +.gate AND A=$abc$2385$new_n83 B=$abc$2385$new_n91 Y=$abc$2385$new_n92 +.gate ORNOT A=$abc$2385$new_n92 B=in_a_var[2] Y=$abc$2385$new_n93 +.gate XNOR A=in_a_var[2] B=$abc$2385$new_n92 Y=$abc$2385$new_n94 +.gate NAND A=in_b_var[2] B=$abc$2385$new_n94 Y=$abc$2385$new_n95 +.gate XNOR A=in_b_var[2] B=$abc$2385$new_n94 Y=$abc$2385$new_n96 +.gate OR A=$abc$2385$new_n90 B=$abc$2385$new_n96 Y=$abc$2385$new_n97 +.gate XOR A=$abc$2385$new_n90 B=$abc$2385$new_n96 Y=$abc$2385$new_n98 +.gate NAND A=$abc$2385$new_n89 B=$abc$2385$new_n98 Y=$abc$2385$new_n99 +.gate XOR A=$abc$2385$new_n89 B=$abc$2385$new_n98 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[2] +.gate NAND A=$abc$2385$new_n97 B=$abc$2385$new_n99 Y=$abc$2385$new_n101 +.gate AND A=$abc$2385$new_n93 B=$abc$2385$new_n95 Y=$abc$2385$new_n102 +.gate XNOR A=:1.test_1[3] B=$abc$2385$new_n67 Y=$abc$2385$new_n103 +.gate AND A=$abc$2385$new_n83 B=$abc$2385$new_n103 Y=$abc$2385$new_n104 +.gate ORNOT A=$abc$2385$new_n104 B=in_a_var[3] Y=$abc$2385$new_n105 +.gate XNOR A=in_a_var[3] B=$abc$2385$new_n104 Y=$abc$2385$new_n106 +.gate NAND A=in_b_var[3] B=$abc$2385$new_n106 Y=$abc$2385$new_n107 +.gate XNOR A=in_b_var[3] B=$abc$2385$new_n106 Y=$abc$2385$new_n108 +.gate OR A=$abc$2385$new_n102 B=$abc$2385$new_n108 Y=$abc$2385$new_n109 +.gate XOR A=$abc$2385$new_n102 B=$abc$2385$new_n108 Y=$abc$2385$new_n110 +.gate NAND A=$abc$2385$new_n101 B=$abc$2385$new_n110 Y=$abc$2385$new_n111 +.gate XOR A=$abc$2385$new_n101 B=$abc$2385$new_n110 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[3] +.gate NAND A=$abc$2385$new_n109 B=$abc$2385$new_n111 Y=$abc$2385$new_n113 +.gate AND A=$abc$2385$new_n105 B=$abc$2385$new_n107 Y=$abc$2385$new_n114 +.gate XNOR A=:1.test_1[4] B=$abc$2385$new_n68 Y=$abc$2385$new_n115 +.gate AND A=$abc$2385$new_n83 B=$abc$2385$new_n115 Y=$abc$2385$new_n116 +.gate ORNOT A=$abc$2385$new_n116 B=in_a_var[4] Y=$abc$2385$new_n117 +.gate XNOR A=in_a_var[4] B=$abc$2385$new_n116 Y=$abc$2385$new_n118 +.gate NAND A=in_b_var[4] B=$abc$2385$new_n118 Y=$abc$2385$new_n119 +.gate XNOR A=in_b_var[4] B=$abc$2385$new_n118 Y=$abc$2385$new_n120 +.gate OR A=$abc$2385$new_n114 B=$abc$2385$new_n120 Y=$abc$2385$new_n121 +.gate XOR A=$abc$2385$new_n114 B=$abc$2385$new_n120 Y=$abc$2385$new_n122 +.gate NAND A=$abc$2385$new_n113 B=$abc$2385$new_n122 Y=$abc$2385$new_n123 +.gate XOR A=$abc$2385$new_n113 B=$abc$2385$new_n122 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[4] +.gate AND A=$abc$2385$new_n121 B=$abc$2385$new_n123 Y=$abc$2385$new_n125 +.gate AND A=$abc$2385$new_n117 B=$abc$2385$new_n119 Y=$abc$2385$new_n126 +.gate AND A=$abc$2385$new_n77 B=$abc$2385$new_n83 Y=$abc$2385$new_n127 +.gate ORNOT A=$abc$2385$new_n127 B=in_a_var[5] Y=$abc$2385$new_n128 +.gate XNOR A=in_a_var[5] B=$abc$2385$new_n127 Y=$abc$2385$new_n129 +.gate NAND A=in_b_var[5] B=$abc$2385$new_n129 Y=$abc$2385$new_n130 +.gate XNOR A=in_b_var[5] B=$abc$2385$new_n129 Y=$abc$2385$new_n131 +.gate OR A=$abc$2385$new_n126 B=$abc$2385$new_n131 Y=$abc$2385$new_n132 +.gate NAND A=$abc$2385$new_n126 B=$abc$2385$new_n131 Y=$abc$2385$new_n133 +.gate XOR A=$abc$2385$new_n126 B=$abc$2385$new_n131 Y=$abc$2385$new_n134 +.gate XNOR A=$abc$2385$new_n125 B=$abc$2385$new_n134 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[5] +.gate AND A=$abc$2385$new_n128 B=$abc$2385$new_n130 Y=$abc$2385$new_n136 +.gate AND A=$abc$2385$new_n72 B=$abc$2385$new_n82 Y=$abc$2385$new_n137 +.gate ORNOT A=$abc$2385$new_n137 B=in_a_var[6] Y=$abc$2385$new_n138 +.gate XNOR A=in_a_var[6] B=$abc$2385$new_n137 Y=$abc$2385$new_n139 +.gate NAND A=in_b_var[6] B=$abc$2385$new_n139 Y=$abc$2385$new_n140 +.gate XNOR A=in_b_var[6] B=$abc$2385$new_n139 Y=$abc$2385$new_n141 +.gate OR A=$abc$2385$new_n136 B=$abc$2385$new_n141 Y=$abc$2385$new_n142 +.gate XOR A=$abc$2385$new_n136 B=$abc$2385$new_n141 Y=$abc$2385$new_n143 +.gate NAND A=$abc$2385$new_n125 B=$abc$2385$new_n132 Y=$abc$2385$new_n144 +.gate AND A=$abc$2385$new_n133 B=$abc$2385$new_n144 Y=$abc$2385$new_n145 +.gate NAND A=$abc$2385$new_n143 B=$abc$2385$new_n145 Y=$abc$2385$new_n146 +.gate XOR A=$abc$2385$new_n143 B=$abc$2385$new_n145 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[6] +.gate AND A=$abc$2385$new_n142 B=$abc$2385$new_n146 Y=$abc$2385$new_n148 +.gate AND A=$abc$2385$new_n138 B=$abc$2385$new_n140 Y=$abc$2385$new_n149 +.gate AND A=$abc$2385$new_n75 B=$abc$2385$new_n83 Y=$abc$2385$new_n150 +.gate NOR A=in_b_var[7] B=in_a_var[7] Y=$abc$2385$new_n151 +.gate XOR A=in_b_var[7] B=in_a_var[7] Y=$abc$2385$new_n152 +.gate XNOR A=$abc$2385$new_n150 B=$abc$2385$new_n152 Y=$abc$2385$new_n153 +.gate XNOR A=$abc$2385$new_n149 B=$abc$2385$new_n153 Y=$abc$2385$new_n154 +.gate XNOR A=$abc$2385$new_n148 B=$abc$2385$new_n154 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[7] +.gate XNOR A=$abc$2385$new_n62 B=$abc$2385$new_n88 Y=$abc$2385$auto$maccmap.cc:240:synth$253.P[1] +.gate NAND A=:1.test_1[0] B=:1.test_2[0] Y=$abc$2385$new_n157 +.gate ANDNOT A=:1.test_2[0] B=$abc$2385$new_n91 Y=$abc$2385$new_n158 +.gate ANDNOT A=:1.test_2[1] B=$abc$2385$new_n64 Y=$abc$2385$new_n159 +.gate AND A=:1.test_2[1] B=$abc$2385$new_n65 Y=$abc$2385$new_n160 +.gate ORNOT A=$abc$2385$new_n160 B=:1.test_1[0] Y=$abc$2385$new_n161 +.gate AND A=:1.test_2[2] B=$abc$2385$new_n161 Y=$abc$2385$new_n162 +.gate ANDNOT A=:1.test_1[1] B=:1.test_1[0] Y=$abc$2385$new_n163 +.gate ANDNOT A=:1.test_2[2] B=:1.test_1[0] Y=$abc$2385$new_n164 +.gate XNOR A=$abc$2385$new_n160 B=$abc$2385$new_n164 Y=$abc$2385$new_n165 +.gate MUX A=$abc$2385$new_n160 B=$abc$2385$new_n165 S=:1.test_2[2] Y=$abc$2385$new_n166 +.gate ORNOT A=:1.test_2[0] B=:1.test_1[0] Y=$abc$2385$new_n167 +.gate AND A=$abc$2385$new_n159 B=$abc$2385$new_n167 Y=$abc$2385$new_n168 +.gate AND A=$abc$2385$new_n166 B=$abc$2385$new_n168 Y=$abc$2385$new_n169 +.gate XOR A=$abc$2385$new_n166 B=$abc$2385$new_n168 Y=$abc$2385$new_n170 +.gate AND A=$abc$2385$new_n158 B=$abc$2385$new_n170 Y=$abc$2385$new_n171 +.gate ANDNOT A=:1.test_2[0] B=$abc$2385$new_n103 Y=$abc$2385$new_n172 +.gate ANDNOT A=:1.test_2[1] B=$abc$2385$new_n91 Y=$abc$2385$new_n173 +.gate ANDNOT A=:1.test_2[1] B=$abc$2385$new_n103 Y=$abc$2385$new_n174 +.gate AND A=$abc$2385$new_n158 B=$abc$2385$new_n174 Y=$abc$2385$new_n175 +.gate XOR A=$abc$2385$new_n172 B=$abc$2385$new_n173 Y=$abc$2385$new_n176 +.gate NAND A=:1.test_2[2] B=$abc$2385$new_n65 Y=$abc$2385$new_n177 +.gate AND A=:1.test_1[0] B=:1.test_2[3] Y=$abc$2385$new_n178 +.gate NAND A=:1.test_1[0] B=$abc$2385$new_n177 Y=$abc$2385$new_n179 +.gate XNOR A=$abc$2385$new_n177 B=$abc$2385$new_n178 Y=$abc$2385$new_n180 +.gate NAND A=$abc$2385$new_n162 B=$abc$2385$new_n180 Y=$abc$2385$new_n181 +.gate XOR A=$abc$2385$new_n162 B=$abc$2385$new_n180 Y=$abc$2385$new_n182 +.gate NAND A=$abc$2385$new_n176 B=$abc$2385$new_n182 Y=$abc$2385$new_n183 +.gate XOR A=$abc$2385$new_n176 B=$abc$2385$new_n182 Y=$abc$2385$new_n184 +.gate NAND A=$abc$2385$new_n171 B=$abc$2385$new_n184 Y=$abc$2385$new_n185 +.gate XOR A=$abc$2385$new_n171 B=$abc$2385$new_n184 Y=$abc$2385$new_n186 +.gate NAND A=$abc$2385$new_n169 B=$abc$2385$new_n186 Y=$abc$2385$new_n187 +.gate NAND A=$abc$2385$new_n185 B=$abc$2385$new_n187 Y=$abc$2385$new_n188 +.gate ANDNOT A=:1.test_2[0] B=$abc$2385$new_n115 Y=$abc$2385$new_n189 +.gate ANDNOT A=:1.test_2[1] B=$abc$2385$new_n115 Y=$abc$2385$new_n190 +.gate NAND A=$abc$2385$new_n172 B=$abc$2385$new_n190 Y=$abc$2385$new_n191 +.gate XOR A=$abc$2385$new_n174 B=$abc$2385$new_n189 Y=$abc$2385$new_n192 +.gate ANDNOT A=:1.test_2[2] B=$abc$2385$new_n91 Y=$abc$2385$new_n193 +.gate NAND A=$abc$2385$new_n192 B=$abc$2385$new_n193 Y=$abc$2385$new_n194 +.gate XOR A=$abc$2385$new_n192 B=$abc$2385$new_n193 Y=$abc$2385$new_n195 +.gate AND A=:1.test_2[3] B=$abc$2385$new_n179 Y=$abc$2385$new_n196 +.gate NAND A=:1.test_2[3] B=$abc$2385$new_n65 Y=$abc$2385$new_n197 +.gate NAND A=:1.test_1[0] B=$abc$2385$new_n197 Y=$abc$2385$new_n198 +.gate AND A=:1.test_2[4] B=$abc$2385$new_n198 Y=$abc$2385$new_n199 +.gate NAND A=:1.test_2[3] B=$abc$2385$new_n163 Y=$abc$2385$new_n200 +.gate NAND A=$abc$2385$new_n199 B=$abc$2385$new_n200 Y=$abc$2385$new_n201 +.gate ORNOT A=:1.test_2[4] B=$abc$2385$new_n197 Y=$abc$2385$new_n202 +.gate AND A=$abc$2385$new_n201 B=$abc$2385$new_n202 Y=$abc$2385$new_n203 +.gate NAND A=$abc$2385$new_n175 B=$abc$2385$new_n203 Y=$abc$2385$new_n204 +.gate XOR A=$abc$2385$new_n175 B=$abc$2385$new_n203 Y=$abc$2385$new_n205 +.gate NAND A=$abc$2385$new_n196 B=$abc$2385$new_n205 Y=$abc$2385$new_n206 +.gate XOR A=$abc$2385$new_n196 B=$abc$2385$new_n205 Y=$abc$2385$new_n207 +.gate AND A=$abc$2385$new_n195 B=$abc$2385$new_n207 Y=$abc$2385$new_n208 +.gate XOR A=$abc$2385$new_n195 B=$abc$2385$new_n207 Y=$abc$2385$new_n209 +.gate NAND A=$abc$2385$new_n181 B=$abc$2385$new_n183 Y=$abc$2385$new_n210 +.gate AND A=$abc$2385$new_n209 B=$abc$2385$new_n210 Y=$abc$2385$new_n211 +.gate XOR A=$abc$2385$new_n209 B=$abc$2385$new_n210 Y=$abc$2385$new_n212 +.gate AND A=$abc$2385$new_n188 B=$abc$2385$new_n212 Y=$abc$2385$new_n213 +.gate ANDNOT A=:1.test_2[0] B=$abc$2385$new_n77 Y=$abc$2385$new_n214 +.gate ANDNOT A=:1.test_2[3] B=$abc$2385$new_n91 Y=$abc$2385$new_n215 +.gate ANDNOT A=:1.test_2[2] B=$abc$2385$new_n103 Y=$abc$2385$new_n216 +.gate ANDNOT A=:1.test_2[2] B=$abc$2385$new_n115 Y=$abc$2385$new_n217 +.gate NAND A=$abc$2385$new_n174 B=$abc$2385$new_n217 Y=$abc$2385$new_n218 +.gate XOR A=$abc$2385$new_n190 B=$abc$2385$new_n216 Y=$abc$2385$new_n219 +.gate NAND A=$abc$2385$new_n215 B=$abc$2385$new_n219 Y=$abc$2385$new_n220 +.gate XOR A=$abc$2385$new_n215 B=$abc$2385$new_n219 Y=$abc$2385$new_n221 +.gate AND A=$abc$2385$new_n214 B=$abc$2385$new_n221 Y=$abc$2385$new_n222 +.gate XOR A=$abc$2385$new_n214 B=$abc$2385$new_n221 Y=$abc$2385$new_n223 +.gate NAND A=:1.test_2[4] B=$abc$2385$new_n65 Y=$abc$2385$new_n224 +.gate NAND A=:1.test_1[0] B=$abc$2385$new_n224 Y=$abc$2385$new_n225 +.gate AND A=:1.test_2[5] B=$abc$2385$new_n225 Y=$abc$2385$new_n226 +.gate NAND A=:1.test_2[4] B=$abc$2385$new_n163 Y=$abc$2385$new_n227 +.gate NAND A=$abc$2385$new_n226 B=$abc$2385$new_n227 Y=$abc$2385$new_n228 +.gate ORNOT A=:1.test_2[5] B=$abc$2385$new_n224 Y=$abc$2385$new_n229 +.gate AND A=$abc$2385$new_n228 B=$abc$2385$new_n229 Y=$abc$2385$new_n230 +.gate NAND A=$abc$2385$new_n191 B=$abc$2385$new_n194 Y=$abc$2385$new_n231 +.gate NAND A=$abc$2385$new_n230 B=$abc$2385$new_n231 Y=$abc$2385$new_n232 +.gate XOR A=$abc$2385$new_n230 B=$abc$2385$new_n231 Y=$abc$2385$new_n233 +.gate NAND A=$abc$2385$new_n199 B=$abc$2385$new_n233 Y=$abc$2385$new_n234 +.gate XOR A=$abc$2385$new_n199 B=$abc$2385$new_n233 Y=$abc$2385$new_n235 +.gate AND A=$abc$2385$new_n223 B=$abc$2385$new_n235 Y=$abc$2385$new_n236 +.gate XOR A=$abc$2385$new_n223 B=$abc$2385$new_n235 Y=$abc$2385$new_n237 +.gate NAND A=$abc$2385$new_n208 B=$abc$2385$new_n237 Y=$abc$2385$new_n238 +.gate XOR A=$abc$2385$new_n208 B=$abc$2385$new_n237 Y=$abc$2385$new_n239 +.gate NAND A=$abc$2385$new_n204 B=$abc$2385$new_n206 Y=$abc$2385$new_n240 +.gate NAND A=$abc$2385$new_n239 B=$abc$2385$new_n240 Y=$abc$2385$new_n241 +.gate XOR A=$abc$2385$new_n239 B=$abc$2385$new_n240 Y=$abc$2385$new_n242 +.gate AND A=$abc$2385$new_n211 B=$abc$2385$new_n242 Y=$abc$2385$new_n243 +.gate XOR A=$abc$2385$new_n211 B=$abc$2385$new_n242 Y=$abc$2385$new_n244 +.gate NAND A=$abc$2385$new_n213 B=$abc$2385$new_n244 Y=$abc$2385$new_n245 +.gate AND A=:1.test_2[0] B=$abc$2385$new_n163 Y=$abc$2385$new_n246 +.gate NAND A=:1.test_2[0] B=$abc$2385$new_n163 Y=$abc$2385$new_n247 +.gate XOR A=$abc$2385$new_n158 B=$abc$2385$new_n170 Y=$abc$2385$new_n248 +.gate AND A=$abc$2385$new_n246 B=$abc$2385$new_n248 Y=$abc$2385$new_n249 +.gate XOR A=$abc$2385$new_n169 B=$abc$2385$new_n186 Y=$abc$2385$new_n250 +.gate AND A=$abc$2385$new_n249 B=$abc$2385$new_n250 Y=$abc$2385$new_n251 +.gate XOR A=$abc$2385$new_n188 B=$abc$2385$new_n212 Y=$abc$2385$new_n252 +.gate AND A=$abc$2385$new_n251 B=$abc$2385$new_n252 Y=$abc$2385$new_n253 +.gate NAND A=$abc$2385$new_n244 B=$abc$2385$new_n253 Y=$abc$2385$new_n254 +.gate XNOR A=$abc$2385$new_n213 B=$abc$2385$new_n244 Y=$abc$2385$new_n255 +.gate NAND A=$abc$2385$new_n245 B=$abc$2385$new_n254 Y=$abc$2385$new_n256 +.gate NAND A=$abc$2385$new_n238 B=$abc$2385$new_n241 Y=$abc$2385$new_n257 +.gate ANDNOT A=:1.test_2[0] B=$abc$2385$new_n72 Y=$abc$2385$new_n258 +.gate ORNOT A=$abc$2385$new_n77 B=:1.test_2[1] Y=$abc$2385$new_n259 +.gate ANDNOT A=:1.test_2[1] B=$abc$2385$new_n72 Y=$abc$2385$new_n260 +.gate NAND A=$abc$2385$new_n214 B=$abc$2385$new_n260 Y=$abc$2385$new_n261 +.gate XNOR A=$abc$2385$new_n258 B=$abc$2385$new_n259 Y=$abc$2385$new_n262 +.gate ANDNOT A=:1.test_2[4] B=$abc$2385$new_n91 Y=$abc$2385$new_n263 +.gate ANDNOT A=:1.test_2[3] B=$abc$2385$new_n103 Y=$abc$2385$new_n264 +.gate ANDNOT A=:1.test_2[3] B=$abc$2385$new_n115 Y=$abc$2385$new_n265 +.gate NAND A=$abc$2385$new_n216 B=$abc$2385$new_n265 Y=$abc$2385$new_n266 +.gate XOR A=$abc$2385$new_n217 B=$abc$2385$new_n264 Y=$abc$2385$new_n267 +.gate NAND A=$abc$2385$new_n263 B=$abc$2385$new_n267 Y=$abc$2385$new_n268 +.gate XOR A=$abc$2385$new_n263 B=$abc$2385$new_n267 Y=$abc$2385$new_n269 +.gate AND A=$abc$2385$new_n262 B=$abc$2385$new_n269 Y=$abc$2385$new_n270 +.gate XOR A=$abc$2385$new_n262 B=$abc$2385$new_n269 Y=$abc$2385$new_n271 +.gate NAND A=$abc$2385$new_n222 B=$abc$2385$new_n271 Y=$abc$2385$new_n272 +.gate XOR A=$abc$2385$new_n222 B=$abc$2385$new_n271 Y=$abc$2385$new_n273 +.gate NAND A=:1.test_2[5] B=$abc$2385$new_n65 Y=$abc$2385$new_n274 +.gate NAND A=:1.test_1[0] B=$abc$2385$new_n274 Y=$abc$2385$new_n275 +.gate AND A=:1.test_2[6] B=$abc$2385$new_n275 Y=$abc$2385$new_n276 +.gate NAND A=:1.test_2[5] B=$abc$2385$new_n163 Y=$abc$2385$new_n277 +.gate NAND A=:1.test_2[6] B=$abc$2385$new_n65 Y=$abc$2385$new_n278 +.gate NAND A=$abc$2385$new_n276 B=$abc$2385$new_n277 Y=$abc$2385$new_n279 +.gate ORNOT A=:1.test_2[6] B=$abc$2385$new_n274 Y=$abc$2385$new_n280 +.gate AND A=$abc$2385$new_n279 B=$abc$2385$new_n280 Y=$abc$2385$new_n281 +.gate NAND A=$abc$2385$new_n218 B=$abc$2385$new_n220 Y=$abc$2385$new_n282 +.gate NAND A=$abc$2385$new_n281 B=$abc$2385$new_n282 Y=$abc$2385$new_n283 +.gate XOR A=$abc$2385$new_n281 B=$abc$2385$new_n282 Y=$abc$2385$new_n284 +.gate NAND A=$abc$2385$new_n226 B=$abc$2385$new_n284 Y=$abc$2385$new_n285 +.gate XOR A=$abc$2385$new_n226 B=$abc$2385$new_n284 Y=$abc$2385$new_n286 +.gate NAND A=$abc$2385$new_n273 B=$abc$2385$new_n286 Y=$abc$2385$new_n287 +.gate XOR A=$abc$2385$new_n273 B=$abc$2385$new_n286 Y=$abc$2385$new_n288 +.gate NAND A=$abc$2385$new_n236 B=$abc$2385$new_n288 Y=$abc$2385$new_n289 +.gate XOR A=$abc$2385$new_n236 B=$abc$2385$new_n288 Y=$abc$2385$new_n290 +.gate NAND A=$abc$2385$new_n232 B=$abc$2385$new_n234 Y=$abc$2385$new_n291 +.gate NAND A=$abc$2385$new_n290 B=$abc$2385$new_n291 Y=$abc$2385$new_n292 +.gate XOR A=$abc$2385$new_n290 B=$abc$2385$new_n291 Y=$abc$2385$new_n293 +.gate NAND A=$abc$2385$new_n257 B=$abc$2385$new_n293 Y=$abc$2385$new_n294 +.gate XOR A=$abc$2385$new_n257 B=$abc$2385$new_n293 Y=$abc$2385$new_n295 +.gate NAND A=$abc$2385$new_n243 B=$abc$2385$new_n295 Y=$abc$2385$new_n296 +.gate XOR A=$abc$2385$new_n243 B=$abc$2385$new_n295 Y=$abc$2385$new_n297 +.gate NAND A=$abc$2385$new_n256 B=$abc$2385$new_n297 Y=$abc$2385$new_n298 +.gate XNOR A=$abc$2385$new_n256 B=$abc$2385$new_n297 Y=$abc$2385$new_n299 +.gate NAND A=$abc$2385$new_n73 B=$abc$2385$new_n299 Y=$abc$2385$new_n300 +.gate OR A=$abc$2385$new_n73 B=$abc$2385$new_n299 Y=$abc$2385$new_n301 +.gate XOR A=$abc$2385$new_n253 B=$abc$2385$new_n255 Y=$abc$2385$new_n302 +.gate XNOR A=$abc$2385$new_n251 B=$abc$2385$new_n252 Y=$abc$2385$new_n303 +.gate XOR A=$abc$2385$new_n249 B=$abc$2385$new_n250 Y=$abc$2385$new_n304 +.gate XNOR A=$abc$2385$new_n249 B=$abc$2385$new_n250 Y=$abc$2385$new_n305 +.gate NAND A=$abc$2385$new_n103 B=$abc$2385$new_n304 Y=$abc$2385$new_n306 +.gate OR A=$abc$2385$new_n103 B=$abc$2385$new_n304 Y=$abc$2385$new_n307 +.gate XNOR A=$abc$2385$new_n247 B=$abc$2385$new_n248 Y=$abc$2385$new_n308 +.gate NAND A=:1.test_1[0] B=:1.test_2[1] Y=$abc$2385$new_n309 +.gate ANDNOT A=:1.test_2[0] B=$abc$2385$new_n64 Y=$abc$2385$new_n310 +.gate XNOR A=$abc$2385$new_n309 B=$abc$2385$new_n310 Y=$abc$2385$new_n311 +.gate NAND A=$abc$2385$new_n66 B=$abc$2385$new_n311 Y=$abc$2385$new_n312 +.gate OR A=:1.test_2[1] B=$abc$2385$new_n157 Y=$abc$2385$new_n313 +.gate NAND A=$abc$2385$new_n312 B=$abc$2385$new_n313 Y=$abc$2385$new_n314 +.gate OR A=$abc$2385$new_n308 B=$abc$2385$new_n314 Y=$abc$2385$new_n315 +.gate NAND A=$abc$2385$new_n91 B=$abc$2385$new_n315 Y=$abc$2385$new_n316 +.gate NAND A=$abc$2385$new_n308 B=$abc$2385$new_n314 Y=$abc$2385$new_n317 +.gate NAND A=$abc$2385$new_n316 B=$abc$2385$new_n317 Y=$abc$2385$new_n318 +.gate NAND A=$abc$2385$new_n307 B=$abc$2385$new_n318 Y=$abc$2385$new_n319 +.gate NAND A=$abc$2385$new_n247 B=$abc$2385$new_n311 Y=$abc$2385$new_n320 +.gate NAND A=$abc$2385$new_n306 B=$abc$2385$new_n319 Y=$abc$2385$new_n321 +.gate ORNOT A=$abc$2385$new_n115 B=$abc$2385$new_n303 Y=$abc$2385$new_n322 +.gate ORNOT A=$abc$2385$new_n303 B=$abc$2385$new_n115 Y=$abc$2385$new_n323 +.gate NAND A=$abc$2385$new_n321 B=$abc$2385$new_n322 Y=$abc$2385$new_n324 +.gate NAND A=$abc$2385$new_n323 B=$abc$2385$new_n324 Y=$abc$2385$new_n325 +.gate NAND A=$abc$2385$new_n77 B=$abc$2385$new_n325 Y=$abc$2385$new_n326 +.gate NAND A=$abc$2385$new_n302 B=$abc$2385$new_n326 Y=$abc$2385$new_n327 +.gate OR A=$abc$2385$new_n77 B=$abc$2385$new_n325 Y=$abc$2385$new_n328 +.gate AND A=$abc$2385$new_n327 B=$abc$2385$new_n328 Y=$abc$2385$new_n329 +.gate NAND A=$abc$2385$new_n300 B=$abc$2385$new_n329 Y=$abc$2385$new_n330 +.gate AND A=$abc$2385$new_n301 B=$abc$2385$new_n330 Y=$abc$2385$new_n331 +.gate NAND A=$abc$2385$new_n75 B=$abc$2385$new_n331 Y=$abc$2385$new_n332 +.gate OR A=in_b_var[5] B=$abc$2385$new_n302 Y=$abc$2385$new_n333 +.gate NAND A=in_b_var[4] B=$abc$2385$new_n303 Y=$abc$2385$new_n334 +.gate OR A=in_b_var[4] B=$abc$2385$new_n303 Y=$abc$2385$new_n335 +.gate AND A=in_b_var[1] B=$abc$2385$new_n320 Y=$abc$2385$new_n336 +.gate OR A=in_b_var[3] B=$abc$2385$new_n305 Y=$abc$2385$new_n337 +.gate ANDNOT A=in_b_var[2] B=$abc$2385$new_n308 Y=$abc$2385$new_n338 +.gate XNOR A=in_b_var[2] B=$abc$2385$new_n308 Y=$abc$2385$new_n339 +.gate NAND A=in_b_var[3] B=$abc$2385$new_n305 Y=$abc$2385$new_n340 +.gate XNOR A=in_b_var[3] B=$abc$2385$new_n304 Y=$abc$2385$new_n341 +.gate AND A=$abc$2385$new_n339 B=$abc$2385$new_n341 Y=$abc$2385$new_n342 +.gate NAND A=$abc$2385$new_n336 B=$abc$2385$new_n342 Y=$abc$2385$new_n343 +.gate NAND A=$abc$2385$new_n337 B=$abc$2385$new_n338 Y=$abc$2385$new_n344 +.gate AND A=$abc$2385$new_n340 B=$abc$2385$new_n344 Y=$abc$2385$new_n345 +.gate AND A=$abc$2385$new_n343 B=$abc$2385$new_n345 Y=$abc$2385$new_n346 +.gate AND A=in_b_var[0] B=$abc$2385$new_n157 Y=$abc$2385$new_n347 +.gate XOR A=in_b_var[1] B=$abc$2385$new_n320 Y=$abc$2385$new_n348 +.gate AND A=$abc$2385$new_n342 B=$abc$2385$new_n348 Y=$abc$2385$new_n349 +.gate NAND A=$abc$2385$new_n347 B=$abc$2385$new_n349 Y=$abc$2385$new_n350 +.gate NAND A=$abc$2385$new_n346 B=$abc$2385$new_n350 Y=$abc$2385$new_n351 +.gate NAND A=$abc$2385$new_n335 B=$abc$2385$new_n351 Y=$abc$2385$new_n352 +.gate NAND A=$abc$2385$new_n334 B=$abc$2385$new_n352 Y=$abc$2385$new_n353 +.gate NAND A=$abc$2385$new_n333 B=$abc$2385$new_n353 Y=$abc$2385$new_n354 +.gate NAND A=in_b_var[6] B=$abc$2385$new_n299 Y=$abc$2385$new_n355 +.gate NAND A=in_b_var[5] B=$abc$2385$new_n302 Y=$abc$2385$new_n356 +.gate AND A=$abc$2385$new_n355 B=$abc$2385$new_n356 Y=$abc$2385$new_n357 +.gate NAND A=$abc$2385$new_n354 B=$abc$2385$new_n357 Y=$abc$2385$new_n358 +.gate AND A=$abc$2385$new_n157 B=$abc$2385$new_n320 Y=$abc$2385$new_n359 +.gate ANDNOT A=$abc$2385$new_n359 B=$abc$2385$new_n308 Y=$abc$2385$new_n360 +.gate AND A=$abc$2385$new_n305 B=$abc$2385$new_n360 Y=$abc$2385$new_n361 +.gate AND A=$abc$2385$new_n303 B=$abc$2385$new_n361 Y=$abc$2385$new_n362 +.gate AND A=$abc$2385$new_n302 B=$abc$2385$new_n362 Y=$abc$2385$new_n363 +.gate NAND A=$abc$2385$new_n299 B=$abc$2385$new_n363 Y=$abc$2385$new_n364 +.gate AND A=$abc$2385$new_n296 B=$abc$2385$new_n298 Y=$abc$2385$new_n365 +.gate AND A=$abc$2385$new_n289 B=$abc$2385$new_n292 Y=$abc$2385$new_n366 +.gate OR A=:1.test_2[0] B=$abc$2385$new_n75 Y=$abc$2385$new_n367 +.gate AND A=$abc$2385$new_n261 B=$abc$2385$new_n367 Y=$abc$2385$new_n368 +.gate XNOR A=$abc$2385$new_n270 B=$abc$2385$new_n368 Y=$abc$2385$new_n369 +.gate XNOR A=$abc$2385$new_n276 B=$abc$2385$new_n369 Y=$abc$2385$new_n370 +.gate ANDNOT A=:1.test_2[2] B=$abc$2385$new_n77 Y=$abc$2385$new_n371 +.gate ANDNOT A=:1.test_2[5] B=$abc$2385$new_n91 Y=$abc$2385$new_n372 +.gate ANDNOT A=:1.test_2[4] B=$abc$2385$new_n103 Y=$abc$2385$new_n373 +.gate XNOR A=$abc$2385$new_n372 B=$abc$2385$new_n373 Y=$abc$2385$new_n374 +.gate XNOR A=$abc$2385$new_n371 B=$abc$2385$new_n374 Y=$abc$2385$new_n375 +.gate XOR A=$abc$2385$new_n260 B=$abc$2385$new_n265 Y=$abc$2385$new_n376 +.gate XNOR A=$abc$2385$new_n375 B=$abc$2385$new_n376 Y=$abc$2385$new_n377 +.gate NAND A=$abc$2385$new_n266 B=$abc$2385$new_n268 Y=$abc$2385$new_n378 +.gate ANDNOT A=:1.test_2[7] B=:1.test_1[0] Y=$abc$2385$new_n379 +.gate XNOR A=$abc$2385$new_n278 B=$abc$2385$new_n379 Y=$abc$2385$new_n380 +.gate XNOR A=$abc$2385$new_n75 B=$abc$2385$new_n380 Y=$abc$2385$new_n381 +.gate XNOR A=$abc$2385$new_n378 B=$abc$2385$new_n381 Y=$abc$2385$new_n382 +.gate XNOR A=$abc$2385$new_n377 B=$abc$2385$new_n382 Y=$abc$2385$new_n383 +.gate XNOR A=$abc$2385$new_n370 B=$abc$2385$new_n383 Y=$abc$2385$new_n384 +.gate NAND A=$abc$2385$new_n283 B=$abc$2385$new_n285 Y=$abc$2385$new_n385 +.gate AND A=$abc$2385$new_n272 B=$abc$2385$new_n287 Y=$abc$2385$new_n386 +.gate XNOR A=$abc$2385$new_n385 B=$abc$2385$new_n386 Y=$abc$2385$new_n387 +.gate XNOR A=$abc$2385$new_n384 B=$abc$2385$new_n387 Y=$abc$2385$new_n388 +.gate XNOR A=$abc$2385$new_n366 B=$abc$2385$new_n388 Y=$abc$2385$new_n389 +.gate XNOR A=:1.test_2[7] B=$abc$2385$new_n294 Y=$abc$2385$new_n390 +.gate XNOR A=$abc$2385$new_n389 B=$abc$2385$new_n390 Y=$abc$2385$new_n391 +.gate XNOR A=$abc$2385$new_n365 B=$abc$2385$new_n391 Y=$abc$2385$new_n392 +.gate OR A=in_b_var[6] B=$abc$2385$new_n299 Y=$abc$2385$new_n393 +.gate ORNOT A=in_b_var[6] B=in_a_var[6] Y=$abc$2385$new_n394 +.gate ORNOT A=in_a_var[5] B=in_b_var[5] Y=$abc$2385$new_n395 +.gate ORNOT A=in_b_var[5] B=in_a_var[5] Y=$abc$2385$new_n396 +.gate ORNOT A=in_b_var[4] B=in_a_var[4] Y=$abc$2385$new_n397 +.gate AND A=$abc$2385$new_n396 B=$abc$2385$new_n397 Y=$abc$2385$new_n398 +.gate ORNOT A=in_b_var[2] B=in_a_var[2] Y=$abc$2385$new_n399 +.gate ORNOT A=in_b_var[3] B=in_a_var[3] Y=$abc$2385$new_n400 +.gate NAND A=$abc$2385$new_n399 B=$abc$2385$new_n400 Y=$abc$2385$new_n401 +.gate ORNOT A=in_a_var[3] B=in_b_var[3] Y=$abc$2385$new_n402 +.gate NAND A=$abc$2385$new_n401 B=$abc$2385$new_n402 Y=$abc$2385$new_n403 +.gate ORNOT A=in_a_var[2] B=in_b_var[2] Y=$abc$2385$new_n404 +.gate NAND A=$abc$2385$new_n402 B=$abc$2385$new_n404 Y=$abc$2385$new_n405 +.gate NOR A=$abc$2385$new_n401 B=$abc$2385$new_n405 Y=$abc$2385$new_n406 +.gate ORNOT A=in_a_var[0] B=in_b_var[0] Y=$abc$2385$new_n407 +.gate ORNOT A=in_a_var[1] B=in_b_var[1] Y=$abc$2385$new_n408 +.gate NAND A=$abc$2385$new_n407 B=$abc$2385$new_n408 Y=$abc$2385$new_n409 +.gate ORNOT A=in_b_var[1] B=in_a_var[1] Y=$abc$2385$new_n410 +.gate NAND A=$abc$2385$new_n409 B=$abc$2385$new_n410 Y=$abc$2385$new_n411 +.gate NAND A=$abc$2385$new_n406 B=$abc$2385$new_n411 Y=$abc$2385$new_n412 +.gate NAND A=$abc$2385$new_n403 B=$abc$2385$new_n412 Y=$abc$2385$new_n413 +.gate ORNOT A=in_a_var[4] B=in_b_var[4] Y=$abc$2385$new_n414 +.gate NAND A=$abc$2385$new_n413 B=$abc$2385$new_n414 Y=$abc$2385$new_n415 +.gate NAND A=$abc$2385$new_n398 B=$abc$2385$new_n415 Y=$abc$2385$new_n416 +.gate NAND A=$abc$2385$new_n395 B=$abc$2385$new_n416 Y=$abc$2385$new_n417 +.gate NAND A=$abc$2385$new_n394 B=$abc$2385$new_n417 Y=$abc$2385$new_n418 +.gate NAND A=$abc$2385$new_n394 B=$abc$2385$new_n395 Y=$abc$2385$new_n419 +.gate NOR A=$abc$2385$new_n409 B=$abc$2385$new_n419 Y=$abc$2385$new_n420 +.gate AND A=$abc$2385$new_n398 B=$abc$2385$new_n420 Y=$abc$2385$new_n421 +.gate ORNOT A=in_b_var[0] B=in_a_var[0] Y=$abc$2385$new_n422 +.gate AND A=$abc$2385$new_n410 B=$abc$2385$new_n414 Y=$abc$2385$new_n423 +.gate AND A=$abc$2385$new_n422 B=$abc$2385$new_n423 Y=$abc$2385$new_n424 +.gate AND A=$abc$2385$new_n406 B=$abc$2385$new_n424 Y=$abc$2385$new_n425 +.gate NAND A=$abc$2385$new_n421 B=$abc$2385$new_n425 Y=$abc$2385$new_n426 +.gate ORNOT A=in_a_var[6] B=in_b_var[6] Y=$abc$2385$new_n427 +.gate AND A=$abc$2385$new_n151 B=$abc$2385$new_n427 Y=$abc$2385$new_n428 +.gate AND A=$abc$2385$new_n426 B=$abc$2385$new_n428 Y=$abc$2385$new_n429 +.gate AND A=$abc$2385$new_n418 B=$abc$2385$new_n429 Y=$abc$2385$new_n430 +.gate AND A=$abc$2385$new_n393 B=$abc$2385$new_n430 Y=$abc$2385$new_n431 +.gate AND A=$abc$2385$new_n392 B=$abc$2385$new_n431 Y=$abc$2385$new_n432 +.gate AND A=$abc$2385$new_n364 B=$abc$2385$new_n432 Y=$abc$2385$new_n433 +.gate AND A=$abc$2385$new_n358 B=$abc$2385$new_n433 Y=$abc$2385$new_n434 +.gate AND A=$abc$2385$new_n332 B=$abc$2385$new_n434 Y=$abc$2385$new_n435 +.gate AND A=$abc$2385$new_n157 B=$abc$2385$new_n435 Y=$abc$2385$new_n436 +.gate XNOR A=$abc$2385$new_n157 B=$abc$2385$new_n435 Y=$abc$2385$new_n437 +.gate ORNOT A=$abc$2385$new_n74 B=:1.test_1[0] Y=$abc$2385$new_n438 +.gate MUX A=:1.test_1[0] B=$abc$2385$new_n437 S=$abc$2385$new_n74 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[0] +.gate ORNOT A=:1.test_1[1] B=$abc$2385$new_n83 Y=$abc$2385$new_n440 +.gate XNOR A=$abc$2385$new_n320 B=$abc$2385$new_n436 Y=$abc$2385$new_n441 +.gate MUX A=$abc$2385$new_n440 B=$abc$2385$new_n441 S=$abc$2385$new_n74 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[1] +.gate ORNOT A=:1.test_1[2] B=$abc$2385$new_n83 Y=$abc$2385$new_n443 +.gate ANDNOT A=$abc$2385$new_n308 B=$abc$2385$new_n359 Y=$abc$2385$new_n444 +.gate XNOR A=$abc$2385$new_n308 B=$abc$2385$new_n359 Y=$abc$2385$new_n445 +.gate NAND A=$abc$2385$new_n435 B=$abc$2385$new_n445 Y=$abc$2385$new_n446 +.gate ORNOT A=$abc$2385$new_n435 B=$abc$2385$new_n308 Y=$abc$2385$new_n447 +.gate AND A=$abc$2385$new_n74 B=$abc$2385$new_n446 Y=$abc$2385$new_n448 +.gate NAND A=$abc$2385$new_n447 B=$abc$2385$new_n448 Y=$abc$2385$new_n449 +.gate AND A=$abc$2385$new_n443 B=$abc$2385$new_n449 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[2] +.gate ORNOT A=:1.test_1[3] B=$abc$2385$new_n83 Y=$abc$2385$new_n451 +.gate AND A=$abc$2385$new_n435 B=$abc$2385$new_n444 Y=$abc$2385$new_n452 +.gate AND A=$abc$2385$new_n304 B=$abc$2385$new_n452 Y=$abc$2385$new_n453 +.gate XNOR A=$abc$2385$new_n305 B=$abc$2385$new_n452 Y=$abc$2385$new_n454 +.gate MUX A=$abc$2385$new_n451 B=$abc$2385$new_n454 S=$abc$2385$new_n74 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[3] +.gate ORNOT A=:1.test_1[4] B=$abc$2385$new_n83 Y=$abc$2385$new_n456 +.gate ORNOT A=$abc$2385$new_n303 B=$abc$2385$new_n453 Y=$abc$2385$new_n457 +.gate XNOR A=$abc$2385$new_n303 B=$abc$2385$new_n453 Y=$abc$2385$new_n458 +.gate MUX A=$abc$2385$new_n456 B=$abc$2385$new_n458 S=$abc$2385$new_n74 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[4] +.gate ORNOT A=:1.test_1[5] B=$abc$2385$new_n83 Y=$abc$2385$new_n460 +.gate OR A=$abc$2385$new_n302 B=$abc$2385$new_n457 Y=$abc$2385$new_n461 +.gate XOR A=$abc$2385$new_n302 B=$abc$2385$new_n457 Y=$abc$2385$new_n462 +.gate NAND A=$abc$2385$new_n74 B=$abc$2385$new_n462 Y=$abc$2385$new_n463 +.gate NAND A=$abc$2385$new_n460 B=$abc$2385$new_n463 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[5] +.gate NAND A=$abc$2385$new_n299 B=$abc$2385$new_n461 Y=$abc$2385$new_n465 +.gate OR A=$abc$2385$new_n299 B=$abc$2385$new_n461 Y=$abc$2385$new_n466 +.gate AND A=$abc$2385$new_n74 B=$abc$2385$new_n466 Y=$abc$2385$new_n467 +.gate NAND A=$abc$2385$new_n465 B=$abc$2385$new_n467 Y=$abc$2385$new_n468 +.gate MUX A=$abc$2385$new_n73 B=$abc$2385$new_n137 S=$abc$2385$new_n76 Y=$abc$2385$new_n469 +.gate OR A=$abc$2385$new_n74 B=$abc$2385$new_n469 Y=$abc$2385$new_n470 +.gate NAND A=$abc$2385$new_n468 B=$abc$2385$new_n470 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[6] +.gate NAND A=$abc$2385$new_n392 B=$abc$2385$new_n467 Y=$abc$2385$new_n472 +.gate ANDNOT A=$abc$2385$new_n137 B=$abc$2385$new_n76 Y=$abc$2385$new_n473 +.gate XNOR A=$abc$2385$new_n150 B=$abc$2385$new_n473 Y=$abc$2385$new_n474 +.gate AND A=$abc$2385$new_n472 B=$abc$2385$new_n474 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[7] +.gate AND A=$abc$2385$new_n58 B=$abc$2385$new_n438 Y=:38.Y[0] +.gate NAND A=in_a_var[1] B=$abc$2385$new_n74 Y=$abc$2385$new_n477 +.gate NAND A=$abc$2385$new_n84 B=$abc$2385$new_n477 Y=:38.Y[1] +.gate NAND A=in_a_var[2] B=$abc$2385$new_n74 Y=$abc$2385$new_n479 +.gate NAND A=$abc$2385$new_n92 B=$abc$2385$new_n479 Y=:38.Y[2] +.gate NAND A=in_a_var[3] B=$abc$2385$new_n74 Y=$abc$2385$new_n481 +.gate NAND A=$abc$2385$new_n104 B=$abc$2385$new_n481 Y=:38.Y[3] +.gate NAND A=in_a_var[4] B=$abc$2385$new_n74 Y=$abc$2385$new_n483 +.gate NAND A=$abc$2385$new_n116 B=$abc$2385$new_n483 Y=:38.Y[4] +.gate NAND A=in_a_var[5] B=$abc$2385$new_n74 Y=$abc$2385$new_n485 +.gate NAND A=$abc$2385$new_n127 B=$abc$2385$new_n485 Y=:38.Y[5] +.gate NAND A=in_a_var[6] B=$abc$2385$new_n74 Y=$abc$2385$new_n487 +.gate NAND A=$abc$2385$new_n137 B=$abc$2385$new_n487 Y=:38.Y[6] +.gate NAND A=in_a_var[7] B=$abc$2385$new_n74 Y=$abc$2385$new_n489 +.gate NAND A=$abc$2385$new_n150 B=$abc$2385$new_n489 Y=:38.Y[7] +.gate DFF C=clk D=$abc$2385$auto$maccmap.cc:114:fulladd$252.Y[0] Q=out_var[0] +.gate DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.P[1] Q=out_var[1] +.gate DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[2] Q=out_var[2] +.gate DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[3] Q=out_var[3] +.gate DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[4] Q=out_var[4] +.gate DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[5] Q=out_var[5] +.gate DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[6] Q=out_var[6] +.gate DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[7] Q=out_var[7] +.gate DFF C=clk D=:38.Y[0] Q=:1.test_1[0] +.gate DFF C=clk D=:38.Y[1] Q=:1.test_1[1] +.gate DFF C=clk D=:38.Y[2] Q=:1.test_1[2] +.gate DFF C=clk D=:38.Y[3] Q=:1.test_1[3] +.gate DFF C=clk D=:38.Y[4] Q=:1.test_1[4] +.gate DFF C=clk D=:38.Y[5] Q=:1.test_1[5] +.gate DFF C=clk D=:38.Y[6] Q=:1.test_1[6] +.gate DFF C=clk D=:38.Y[7] Q=:1.test_1[7] +.gate DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[0] Q=:1.test_2[0] +.gate DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[1] Q=:1.test_2[1] +.gate DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[2] Q=:1.test_2[2] +.gate DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[3] Q=:1.test_2[3] +.gate DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[4] Q=:1.test_2[4] +.gate DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[5] Q=:1.test_2[5] +.gate DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[6] Q=:1.test_2[6] +.gate DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[7] Q=:1.test_2[7] +.gateinit :1.test_2[7]=0 +.gateinit :1.test_2[6]=0 +.gateinit :1.test_2[5]=0 +.gateinit :1.test_2[4]=0 +.gateinit :1.test_2[3]=0 +.gateinit :1.test_2[2]=0 +.gateinit :1.test_2[1]=0 +.gateinit :1.test_2[0]=0 +.gateinit :1.test_1[7]=1 +.gateinit :1.test_1[6]=1 +.gateinit :1.test_1[5]=1 +.gateinit :1.test_1[4]=1 +.gateinit :1.test_1[3]=1 +.gateinit :1.test_1[2]=1 +.gateinit :1.test_1[1]=1 +.gateinit :1.test_1[0]=1 +.end diff --git a/tests/blif/gatesi.blif.ok b/tests/blif/gatesi.blif.ok new file mode 100644 index 000000000..e99d7906f --- /dev/null +++ b/tests/blif/gatesi.blif.ok @@ -0,0 +1,484 @@ +# Generated by Yosys + +.model test +.inputs clk in_a_var[0] in_a_var[1] in_a_var[2] in_a_var[3] in_a_var[4] in_a_var[5] in_a_var[6] in_a_var[7] in_b_var[0] in_b_var[1] in_b_var[2] in_b_var[3] in_b_var[4] in_b_var[5] in_b_var[6] in_b_var[7] +.outputs out_var[0] out_var[1] out_var[2] out_var[3] out_var[4] out_var[5] out_var[6] out_var[7] +.names $false +.names $true +1 +.names $undef +.subckt ORNOT A=:1.test_1[0] B=in_a_var[0] Y=$abc$2385$new_n57 +.subckt NOT A=$abc$2385$new_n65 Y=$abc$2385$new_n66 +.subckt XNOR A=$abc$2385$new_n62 B=$abc$2385$new_n88 Y=$abc$2385$auto$maccmap.cc:240:synth$253.P[1] +.subckt NAND A=:1.test_1[0] B=:1.test_2[0] Y=$abc$2385$new_n157 +.subckt ANDNOT A=:1.test_2[0] B=$abc$2385$new_n91 Y=$abc$2385$new_n158 +.subckt ANDNOT A=:1.test_2[1] B=$abc$2385$new_n64 Y=$abc$2385$new_n159 +.subckt AND A=:1.test_2[1] B=$abc$2385$new_n65 Y=$abc$2385$new_n160 +.subckt ORNOT A=$abc$2385$new_n160 B=:1.test_1[0] Y=$abc$2385$new_n161 +.subckt AND A=:1.test_2[2] B=$abc$2385$new_n161 Y=$abc$2385$new_n162 +.subckt ANDNOT A=:1.test_1[1] B=:1.test_1[0] Y=$abc$2385$new_n163 +.subckt ANDNOT A=:1.test_2[2] B=:1.test_1[0] Y=$abc$2385$new_n164 +.subckt XNOR A=$abc$2385$new_n160 B=$abc$2385$new_n164 Y=$abc$2385$new_n165 +.subckt AND A=:1.test_1[2] B=$abc$2385$new_n64 Y=$abc$2385$new_n67 +.subckt MUX A=$abc$2385$new_n160 B=$abc$2385$new_n165 S=:1.test_2[2] Y=$abc$2385$new_n166 +.subckt ORNOT A=:1.test_2[0] B=:1.test_1[0] Y=$abc$2385$new_n167 +.subckt AND A=$abc$2385$new_n159 B=$abc$2385$new_n167 Y=$abc$2385$new_n168 +.subckt AND A=$abc$2385$new_n166 B=$abc$2385$new_n168 Y=$abc$2385$new_n169 +.subckt XOR A=$abc$2385$new_n166 B=$abc$2385$new_n168 Y=$abc$2385$new_n170 +.subckt AND A=$abc$2385$new_n158 B=$abc$2385$new_n170 Y=$abc$2385$new_n171 +.subckt ANDNOT A=:1.test_2[0] B=$abc$2385$new_n103 Y=$abc$2385$new_n172 +.subckt ANDNOT A=:1.test_2[1] B=$abc$2385$new_n91 Y=$abc$2385$new_n173 +.subckt ANDNOT A=:1.test_2[1] B=$abc$2385$new_n103 Y=$abc$2385$new_n174 +.subckt AND A=$abc$2385$new_n158 B=$abc$2385$new_n174 Y=$abc$2385$new_n175 +.subckt AND A=:1.test_1[3] B=$abc$2385$new_n67 Y=$abc$2385$new_n68 +.subckt XOR A=$abc$2385$new_n172 B=$abc$2385$new_n173 Y=$abc$2385$new_n176 +.subckt NAND A=:1.test_2[2] B=$abc$2385$new_n65 Y=$abc$2385$new_n177 +.subckt AND A=:1.test_1[0] B=:1.test_2[3] Y=$abc$2385$new_n178 +.subckt NAND A=:1.test_1[0] B=$abc$2385$new_n177 Y=$abc$2385$new_n179 +.subckt XNOR A=$abc$2385$new_n177 B=$abc$2385$new_n178 Y=$abc$2385$new_n180 +.subckt NAND A=$abc$2385$new_n162 B=$abc$2385$new_n180 Y=$abc$2385$new_n181 +.subckt XOR A=$abc$2385$new_n162 B=$abc$2385$new_n180 Y=$abc$2385$new_n182 +.subckt NAND A=$abc$2385$new_n176 B=$abc$2385$new_n182 Y=$abc$2385$new_n183 +.subckt XOR A=$abc$2385$new_n176 B=$abc$2385$new_n182 Y=$abc$2385$new_n184 +.subckt NAND A=$abc$2385$new_n171 B=$abc$2385$new_n184 Y=$abc$2385$new_n185 +.subckt AND A=:1.test_1[4] B=$abc$2385$new_n68 Y=$abc$2385$new_n69 +.subckt XOR A=$abc$2385$new_n171 B=$abc$2385$new_n184 Y=$abc$2385$new_n186 +.subckt NAND A=$abc$2385$new_n169 B=$abc$2385$new_n186 Y=$abc$2385$new_n187 +.subckt NAND A=$abc$2385$new_n185 B=$abc$2385$new_n187 Y=$abc$2385$new_n188 +.subckt ANDNOT A=:1.test_2[0] B=$abc$2385$new_n115 Y=$abc$2385$new_n189 +.subckt ANDNOT A=:1.test_2[1] B=$abc$2385$new_n115 Y=$abc$2385$new_n190 +.subckt NAND A=$abc$2385$new_n172 B=$abc$2385$new_n190 Y=$abc$2385$new_n191 +.subckt XOR A=$abc$2385$new_n174 B=$abc$2385$new_n189 Y=$abc$2385$new_n192 +.subckt ANDNOT A=:1.test_2[2] B=$abc$2385$new_n91 Y=$abc$2385$new_n193 +.subckt NAND A=$abc$2385$new_n192 B=$abc$2385$new_n193 Y=$abc$2385$new_n194 +.subckt XOR A=$abc$2385$new_n192 B=$abc$2385$new_n193 Y=$abc$2385$new_n195 +.subckt AND A=:1.test_1[5] B=$abc$2385$new_n69 Y=$abc$2385$new_n70 +.subckt AND A=:1.test_2[3] B=$abc$2385$new_n179 Y=$abc$2385$new_n196 +.subckt NAND A=:1.test_2[3] B=$abc$2385$new_n65 Y=$abc$2385$new_n197 +.subckt NAND A=:1.test_1[0] B=$abc$2385$new_n197 Y=$abc$2385$new_n198 +.subckt AND A=:1.test_2[4] B=$abc$2385$new_n198 Y=$abc$2385$new_n199 +.subckt NAND A=:1.test_2[3] B=$abc$2385$new_n163 Y=$abc$2385$new_n200 +.subckt NAND A=$abc$2385$new_n199 B=$abc$2385$new_n200 Y=$abc$2385$new_n201 +.subckt ORNOT A=:1.test_2[4] B=$abc$2385$new_n197 Y=$abc$2385$new_n202 +.subckt AND A=$abc$2385$new_n201 B=$abc$2385$new_n202 Y=$abc$2385$new_n203 +.subckt NAND A=$abc$2385$new_n175 B=$abc$2385$new_n203 Y=$abc$2385$new_n204 +.subckt XOR A=$abc$2385$new_n175 B=$abc$2385$new_n203 Y=$abc$2385$new_n205 +.subckt AND A=:1.test_1[6] B=$abc$2385$new_n70 Y=$abc$2385$new_n71 +.subckt NAND A=$abc$2385$new_n196 B=$abc$2385$new_n205 Y=$abc$2385$new_n206 +.subckt XOR A=$abc$2385$new_n196 B=$abc$2385$new_n205 Y=$abc$2385$new_n207 +.subckt AND A=$abc$2385$new_n195 B=$abc$2385$new_n207 Y=$abc$2385$new_n208 +.subckt XOR A=$abc$2385$new_n195 B=$abc$2385$new_n207 Y=$abc$2385$new_n209 +.subckt NAND A=$abc$2385$new_n181 B=$abc$2385$new_n183 Y=$abc$2385$new_n210 +.subckt AND A=$abc$2385$new_n209 B=$abc$2385$new_n210 Y=$abc$2385$new_n211 +.subckt XOR A=$abc$2385$new_n209 B=$abc$2385$new_n210 Y=$abc$2385$new_n212 +.subckt AND A=$abc$2385$new_n188 B=$abc$2385$new_n212 Y=$abc$2385$new_n213 +.subckt ANDNOT A=:1.test_2[0] B=$abc$2385$new_n77 Y=$abc$2385$new_n214 +.subckt ANDNOT A=:1.test_2[3] B=$abc$2385$new_n91 Y=$abc$2385$new_n215 +.subckt XNOR A=:1.test_1[6] B=$abc$2385$new_n70 Y=$abc$2385$new_n72 +.subckt ANDNOT A=:1.test_2[2] B=$abc$2385$new_n103 Y=$abc$2385$new_n216 +.subckt ANDNOT A=:1.test_2[2] B=$abc$2385$new_n115 Y=$abc$2385$new_n217 +.subckt NAND A=$abc$2385$new_n174 B=$abc$2385$new_n217 Y=$abc$2385$new_n218 +.subckt XOR A=$abc$2385$new_n190 B=$abc$2385$new_n216 Y=$abc$2385$new_n219 +.subckt NAND A=$abc$2385$new_n215 B=$abc$2385$new_n219 Y=$abc$2385$new_n220 +.subckt XOR A=$abc$2385$new_n215 B=$abc$2385$new_n219 Y=$abc$2385$new_n221 +.subckt AND A=$abc$2385$new_n214 B=$abc$2385$new_n221 Y=$abc$2385$new_n222 +.subckt XOR A=$abc$2385$new_n214 B=$abc$2385$new_n221 Y=$abc$2385$new_n223 +.subckt NAND A=:1.test_2[4] B=$abc$2385$new_n65 Y=$abc$2385$new_n224 +.subckt NAND A=:1.test_1[0] B=$abc$2385$new_n224 Y=$abc$2385$new_n225 +.subckt NOT A=$abc$2385$new_n72 Y=$abc$2385$new_n73 +.subckt AND A=:1.test_2[5] B=$abc$2385$new_n225 Y=$abc$2385$new_n226 +.subckt NAND A=:1.test_2[4] B=$abc$2385$new_n163 Y=$abc$2385$new_n227 +.subckt NAND A=$abc$2385$new_n226 B=$abc$2385$new_n227 Y=$abc$2385$new_n228 +.subckt ORNOT A=:1.test_2[5] B=$abc$2385$new_n224 Y=$abc$2385$new_n229 +.subckt AND A=$abc$2385$new_n228 B=$abc$2385$new_n229 Y=$abc$2385$new_n230 +.subckt NAND A=$abc$2385$new_n191 B=$abc$2385$new_n194 Y=$abc$2385$new_n231 +.subckt NAND A=$abc$2385$new_n230 B=$abc$2385$new_n231 Y=$abc$2385$new_n232 +.subckt XOR A=$abc$2385$new_n230 B=$abc$2385$new_n231 Y=$abc$2385$new_n233 +.subckt NAND A=$abc$2385$new_n199 B=$abc$2385$new_n233 Y=$abc$2385$new_n234 +.subckt XOR A=$abc$2385$new_n199 B=$abc$2385$new_n233 Y=$abc$2385$new_n235 +.subckt AND A=:1.test_1[7] B=$abc$2385$new_n71 Y=$abc$2385$new_n74 +.subckt AND A=$abc$2385$new_n223 B=$abc$2385$new_n235 Y=$abc$2385$new_n236 +.subckt XOR A=$abc$2385$new_n223 B=$abc$2385$new_n235 Y=$abc$2385$new_n237 +.subckt NAND A=$abc$2385$new_n208 B=$abc$2385$new_n237 Y=$abc$2385$new_n238 +.subckt XOR A=$abc$2385$new_n208 B=$abc$2385$new_n237 Y=$abc$2385$new_n239 +.subckt NAND A=$abc$2385$new_n204 B=$abc$2385$new_n206 Y=$abc$2385$new_n240 +.subckt NAND A=$abc$2385$new_n239 B=$abc$2385$new_n240 Y=$abc$2385$new_n241 +.subckt XOR A=$abc$2385$new_n239 B=$abc$2385$new_n240 Y=$abc$2385$new_n242 +.subckt AND A=$abc$2385$new_n211 B=$abc$2385$new_n242 Y=$abc$2385$new_n243 +.subckt XOR A=$abc$2385$new_n211 B=$abc$2385$new_n242 Y=$abc$2385$new_n244 +.subckt NAND A=$abc$2385$new_n213 B=$abc$2385$new_n244 Y=$abc$2385$new_n245 +.subckt XNOR A=:1.test_1[7] B=$abc$2385$new_n71 Y=$abc$2385$new_n75 +.subckt AND A=:1.test_2[0] B=$abc$2385$new_n163 Y=$abc$2385$new_n246 +.subckt NAND A=:1.test_2[0] B=$abc$2385$new_n163 Y=$abc$2385$new_n247 +.subckt XOR A=$abc$2385$new_n158 B=$abc$2385$new_n170 Y=$abc$2385$new_n248 +.subckt AND A=$abc$2385$new_n246 B=$abc$2385$new_n248 Y=$abc$2385$new_n249 +.subckt XOR A=$abc$2385$new_n169 B=$abc$2385$new_n186 Y=$abc$2385$new_n250 +.subckt AND A=$abc$2385$new_n249 B=$abc$2385$new_n250 Y=$abc$2385$new_n251 +.subckt XOR A=$abc$2385$new_n188 B=$abc$2385$new_n212 Y=$abc$2385$new_n252 +.subckt AND A=$abc$2385$new_n251 B=$abc$2385$new_n252 Y=$abc$2385$new_n253 +.subckt NAND A=$abc$2385$new_n244 B=$abc$2385$new_n253 Y=$abc$2385$new_n254 +.subckt XNOR A=$abc$2385$new_n213 B=$abc$2385$new_n244 Y=$abc$2385$new_n255 +.subckt ORNOT A=in_a_var[0] B=:1.test_1[0] Y=$abc$2385$new_n58 +.subckt ANDNOT A=:1.test_1[5] B=$abc$2385$new_n69 Y=$abc$2385$new_n76 +.subckt NAND A=$abc$2385$new_n245 B=$abc$2385$new_n254 Y=$abc$2385$new_n256 +.subckt NAND A=$abc$2385$new_n238 B=$abc$2385$new_n241 Y=$abc$2385$new_n257 +.subckt ANDNOT A=:1.test_2[0] B=$abc$2385$new_n72 Y=$abc$2385$new_n258 +.subckt ORNOT A=$abc$2385$new_n77 B=:1.test_2[1] Y=$abc$2385$new_n259 +.subckt ANDNOT A=:1.test_2[1] B=$abc$2385$new_n72 Y=$abc$2385$new_n260 +.subckt NAND A=$abc$2385$new_n214 B=$abc$2385$new_n260 Y=$abc$2385$new_n261 +.subckt XNOR A=$abc$2385$new_n258 B=$abc$2385$new_n259 Y=$abc$2385$new_n262 +.subckt ANDNOT A=:1.test_2[4] B=$abc$2385$new_n91 Y=$abc$2385$new_n263 +.subckt ANDNOT A=:1.test_2[3] B=$abc$2385$new_n103 Y=$abc$2385$new_n264 +.subckt ANDNOT A=:1.test_2[3] B=$abc$2385$new_n115 Y=$abc$2385$new_n265 +.subckt XNOR A=:1.test_1[5] B=$abc$2385$new_n69 Y=$abc$2385$new_n77 +.subckt NAND A=$abc$2385$new_n216 B=$abc$2385$new_n265 Y=$abc$2385$new_n266 +.subckt XOR A=$abc$2385$new_n217 B=$abc$2385$new_n264 Y=$abc$2385$new_n267 +.subckt NAND A=$abc$2385$new_n263 B=$abc$2385$new_n267 Y=$abc$2385$new_n268 +.subckt XOR A=$abc$2385$new_n263 B=$abc$2385$new_n267 Y=$abc$2385$new_n269 +.subckt AND A=$abc$2385$new_n262 B=$abc$2385$new_n269 Y=$abc$2385$new_n270 +.subckt XOR A=$abc$2385$new_n262 B=$abc$2385$new_n269 Y=$abc$2385$new_n271 +.subckt NAND A=$abc$2385$new_n222 B=$abc$2385$new_n271 Y=$abc$2385$new_n272 +.subckt XOR A=$abc$2385$new_n222 B=$abc$2385$new_n271 Y=$abc$2385$new_n273 +.subckt NAND A=:1.test_2[5] B=$abc$2385$new_n65 Y=$abc$2385$new_n274 +.subckt NAND A=:1.test_1[0] B=$abc$2385$new_n274 Y=$abc$2385$new_n275 +.subckt NOR A=:1.test_1[3] B=:1.test_1[4] Y=$abc$2385$new_n78 +.subckt AND A=:1.test_2[6] B=$abc$2385$new_n275 Y=$abc$2385$new_n276 +.subckt NAND A=:1.test_2[5] B=$abc$2385$new_n163 Y=$abc$2385$new_n277 +.subckt NAND A=:1.test_2[6] B=$abc$2385$new_n65 Y=$abc$2385$new_n278 +.subckt NAND A=$abc$2385$new_n276 B=$abc$2385$new_n277 Y=$abc$2385$new_n279 +.subckt ORNOT A=:1.test_2[6] B=$abc$2385$new_n274 Y=$abc$2385$new_n280 +.subckt AND A=$abc$2385$new_n279 B=$abc$2385$new_n280 Y=$abc$2385$new_n281 +.subckt NAND A=$abc$2385$new_n218 B=$abc$2385$new_n220 Y=$abc$2385$new_n282 +.subckt NAND A=$abc$2385$new_n281 B=$abc$2385$new_n282 Y=$abc$2385$new_n283 +.subckt XOR A=$abc$2385$new_n281 B=$abc$2385$new_n282 Y=$abc$2385$new_n284 +.subckt NAND A=$abc$2385$new_n226 B=$abc$2385$new_n284 Y=$abc$2385$new_n285 +.subckt AND A=$abc$2385$new_n63 B=$abc$2385$new_n78 Y=$abc$2385$new_n79 +.subckt XOR A=$abc$2385$new_n226 B=$abc$2385$new_n284 Y=$abc$2385$new_n286 +.subckt NAND A=$abc$2385$new_n273 B=$abc$2385$new_n286 Y=$abc$2385$new_n287 +.subckt XOR A=$abc$2385$new_n273 B=$abc$2385$new_n286 Y=$abc$2385$new_n288 +.subckt NAND A=$abc$2385$new_n236 B=$abc$2385$new_n288 Y=$abc$2385$new_n289 +.subckt XOR A=$abc$2385$new_n236 B=$abc$2385$new_n288 Y=$abc$2385$new_n290 +.subckt NAND A=$abc$2385$new_n232 B=$abc$2385$new_n234 Y=$abc$2385$new_n291 +.subckt NAND A=$abc$2385$new_n290 B=$abc$2385$new_n291 Y=$abc$2385$new_n292 +.subckt XOR A=$abc$2385$new_n290 B=$abc$2385$new_n291 Y=$abc$2385$new_n293 +.subckt NAND A=$abc$2385$new_n257 B=$abc$2385$new_n293 Y=$abc$2385$new_n294 +.subckt XOR A=$abc$2385$new_n257 B=$abc$2385$new_n293 Y=$abc$2385$new_n295 +.subckt ANDNOT A=$abc$2385$new_n79 B=:1.test_1[2] Y=$abc$2385$new_n80 +.subckt NAND A=$abc$2385$new_n243 B=$abc$2385$new_n295 Y=$abc$2385$new_n296 +.subckt XOR A=$abc$2385$new_n243 B=$abc$2385$new_n295 Y=$abc$2385$new_n297 +.subckt NAND A=$abc$2385$new_n256 B=$abc$2385$new_n297 Y=$abc$2385$new_n298 +.subckt XNOR A=$abc$2385$new_n256 B=$abc$2385$new_n297 Y=$abc$2385$new_n299 +.subckt NAND A=$abc$2385$new_n73 B=$abc$2385$new_n299 Y=$abc$2385$new_n300 +.subckt OR A=$abc$2385$new_n73 B=$abc$2385$new_n299 Y=$abc$2385$new_n301 +.subckt XOR A=$abc$2385$new_n253 B=$abc$2385$new_n255 Y=$abc$2385$new_n302 +.subckt XNOR A=$abc$2385$new_n251 B=$abc$2385$new_n252 Y=$abc$2385$new_n303 +.subckt XOR A=$abc$2385$new_n249 B=$abc$2385$new_n250 Y=$abc$2385$new_n304 +.subckt XNOR A=$abc$2385$new_n249 B=$abc$2385$new_n250 Y=$abc$2385$new_n305 +.subckt AND A=$abc$2385$new_n77 B=$abc$2385$new_n80 Y=$abc$2385$new_n81 +.subckt NAND A=$abc$2385$new_n103 B=$abc$2385$new_n304 Y=$abc$2385$new_n306 +.subckt OR A=$abc$2385$new_n103 B=$abc$2385$new_n304 Y=$abc$2385$new_n307 +.subckt XNOR A=$abc$2385$new_n247 B=$abc$2385$new_n248 Y=$abc$2385$new_n308 +.subckt NAND A=:1.test_1[0] B=:1.test_2[1] Y=$abc$2385$new_n309 +.subckt ANDNOT A=:1.test_2[0] B=$abc$2385$new_n64 Y=$abc$2385$new_n310 +.subckt XNOR A=$abc$2385$new_n309 B=$abc$2385$new_n310 Y=$abc$2385$new_n311 +.subckt NAND A=$abc$2385$new_n66 B=$abc$2385$new_n311 Y=$abc$2385$new_n312 +.subckt OR A=:1.test_2[1] B=$abc$2385$new_n157 Y=$abc$2385$new_n313 +.subckt NAND A=$abc$2385$new_n312 B=$abc$2385$new_n313 Y=$abc$2385$new_n314 +.subckt OR A=$abc$2385$new_n308 B=$abc$2385$new_n314 Y=$abc$2385$new_n315 +.subckt NAND A=$abc$2385$new_n75 B=$abc$2385$new_n81 Y=$abc$2385$new_n82 +.subckt NAND A=$abc$2385$new_n91 B=$abc$2385$new_n315 Y=$abc$2385$new_n316 +.subckt NAND A=$abc$2385$new_n308 B=$abc$2385$new_n314 Y=$abc$2385$new_n317 +.subckt NAND A=$abc$2385$new_n316 B=$abc$2385$new_n317 Y=$abc$2385$new_n318 +.subckt NAND A=$abc$2385$new_n307 B=$abc$2385$new_n318 Y=$abc$2385$new_n319 +.subckt NAND A=$abc$2385$new_n247 B=$abc$2385$new_n311 Y=$abc$2385$new_n320 +.subckt NAND A=$abc$2385$new_n306 B=$abc$2385$new_n319 Y=$abc$2385$new_n321 +.subckt ORNOT A=$abc$2385$new_n115 B=$abc$2385$new_n303 Y=$abc$2385$new_n322 +.subckt ORNOT A=$abc$2385$new_n303 B=$abc$2385$new_n115 Y=$abc$2385$new_n323 +.subckt NAND A=$abc$2385$new_n321 B=$abc$2385$new_n322 Y=$abc$2385$new_n324 +.subckt NAND A=$abc$2385$new_n323 B=$abc$2385$new_n324 Y=$abc$2385$new_n325 +.subckt OR A=$abc$2385$new_n73 B=$abc$2385$new_n82 Y=$abc$2385$new_n83 +.subckt NAND A=$abc$2385$new_n77 B=$abc$2385$new_n325 Y=$abc$2385$new_n326 +.subckt NAND A=$abc$2385$new_n302 B=$abc$2385$new_n326 Y=$abc$2385$new_n327 +.subckt OR A=$abc$2385$new_n77 B=$abc$2385$new_n325 Y=$abc$2385$new_n328 +.subckt AND A=$abc$2385$new_n327 B=$abc$2385$new_n328 Y=$abc$2385$new_n329 +.subckt NAND A=$abc$2385$new_n300 B=$abc$2385$new_n329 Y=$abc$2385$new_n330 +.subckt AND A=$abc$2385$new_n301 B=$abc$2385$new_n330 Y=$abc$2385$new_n331 +.subckt NAND A=$abc$2385$new_n75 B=$abc$2385$new_n331 Y=$abc$2385$new_n332 +.subckt OR A=in_b_var[5] B=$abc$2385$new_n302 Y=$abc$2385$new_n333 +.subckt NAND A=in_b_var[4] B=$abc$2385$new_n303 Y=$abc$2385$new_n334 +.subckt OR A=in_b_var[4] B=$abc$2385$new_n303 Y=$abc$2385$new_n335 +.subckt AND A=$abc$2385$new_n66 B=$abc$2385$new_n83 Y=$abc$2385$new_n84 +.subckt AND A=in_b_var[1] B=$abc$2385$new_n320 Y=$abc$2385$new_n336 +.subckt OR A=in_b_var[3] B=$abc$2385$new_n305 Y=$abc$2385$new_n337 +.subckt ANDNOT A=in_b_var[2] B=$abc$2385$new_n308 Y=$abc$2385$new_n338 +.subckt XNOR A=in_b_var[2] B=$abc$2385$new_n308 Y=$abc$2385$new_n339 +.subckt NAND A=in_b_var[3] B=$abc$2385$new_n305 Y=$abc$2385$new_n340 +.subckt XNOR A=in_b_var[3] B=$abc$2385$new_n304 Y=$abc$2385$new_n341 +.subckt AND A=$abc$2385$new_n339 B=$abc$2385$new_n341 Y=$abc$2385$new_n342 +.subckt NAND A=$abc$2385$new_n336 B=$abc$2385$new_n342 Y=$abc$2385$new_n343 +.subckt NAND A=$abc$2385$new_n337 B=$abc$2385$new_n338 Y=$abc$2385$new_n344 +.subckt AND A=$abc$2385$new_n340 B=$abc$2385$new_n344 Y=$abc$2385$new_n345 +.subckt ORNOT A=$abc$2385$new_n84 B=in_a_var[1] Y=$abc$2385$new_n85 +.subckt AND A=$abc$2385$new_n343 B=$abc$2385$new_n345 Y=$abc$2385$new_n346 +.subckt AND A=in_b_var[0] B=$abc$2385$new_n157 Y=$abc$2385$new_n347 +.subckt XOR A=in_b_var[1] B=$abc$2385$new_n320 Y=$abc$2385$new_n348 +.subckt AND A=$abc$2385$new_n342 B=$abc$2385$new_n348 Y=$abc$2385$new_n349 +.subckt NAND A=$abc$2385$new_n347 B=$abc$2385$new_n349 Y=$abc$2385$new_n350 +.subckt NAND A=$abc$2385$new_n346 B=$abc$2385$new_n350 Y=$abc$2385$new_n351 +.subckt NAND A=$abc$2385$new_n335 B=$abc$2385$new_n351 Y=$abc$2385$new_n352 +.subckt NAND A=$abc$2385$new_n334 B=$abc$2385$new_n352 Y=$abc$2385$new_n353 +.subckt NAND A=$abc$2385$new_n333 B=$abc$2385$new_n353 Y=$abc$2385$new_n354 +.subckt NAND A=in_b_var[6] B=$abc$2385$new_n299 Y=$abc$2385$new_n355 +.subckt XNOR A=:1.test_1[0] B=in_a_var[0] Y=$abc$2385$new_n59 +.subckt XNOR A=in_a_var[1] B=$abc$2385$new_n84 Y=$abc$2385$new_n86 +.subckt NAND A=in_b_var[5] B=$abc$2385$new_n302 Y=$abc$2385$new_n356 +.subckt AND A=$abc$2385$new_n355 B=$abc$2385$new_n356 Y=$abc$2385$new_n357 +.subckt NAND A=$abc$2385$new_n354 B=$abc$2385$new_n357 Y=$abc$2385$new_n358 +.subckt AND A=$abc$2385$new_n157 B=$abc$2385$new_n320 Y=$abc$2385$new_n359 +.subckt ANDNOT A=$abc$2385$new_n359 B=$abc$2385$new_n308 Y=$abc$2385$new_n360 +.subckt AND A=$abc$2385$new_n305 B=$abc$2385$new_n360 Y=$abc$2385$new_n361 +.subckt AND A=$abc$2385$new_n303 B=$abc$2385$new_n361 Y=$abc$2385$new_n362 +.subckt AND A=$abc$2385$new_n302 B=$abc$2385$new_n362 Y=$abc$2385$new_n363 +.subckt NAND A=$abc$2385$new_n299 B=$abc$2385$new_n363 Y=$abc$2385$new_n364 +.subckt AND A=$abc$2385$new_n296 B=$abc$2385$new_n298 Y=$abc$2385$new_n365 +.subckt NAND A=in_b_var[1] B=$abc$2385$new_n86 Y=$abc$2385$new_n87 +.subckt AND A=$abc$2385$new_n289 B=$abc$2385$new_n292 Y=$abc$2385$new_n366 +.subckt OR A=:1.test_2[0] B=$abc$2385$new_n75 Y=$abc$2385$new_n367 +.subckt AND A=$abc$2385$new_n261 B=$abc$2385$new_n367 Y=$abc$2385$new_n368 +.subckt XNOR A=$abc$2385$new_n270 B=$abc$2385$new_n368 Y=$abc$2385$new_n369 +.subckt XNOR A=$abc$2385$new_n276 B=$abc$2385$new_n369 Y=$abc$2385$new_n370 +.subckt ANDNOT A=:1.test_2[2] B=$abc$2385$new_n77 Y=$abc$2385$new_n371 +.subckt ANDNOT A=:1.test_2[5] B=$abc$2385$new_n91 Y=$abc$2385$new_n372 +.subckt ANDNOT A=:1.test_2[4] B=$abc$2385$new_n103 Y=$abc$2385$new_n373 +.subckt XNOR A=$abc$2385$new_n372 B=$abc$2385$new_n373 Y=$abc$2385$new_n374 +.subckt XNOR A=$abc$2385$new_n371 B=$abc$2385$new_n374 Y=$abc$2385$new_n375 +.subckt XNOR A=in_b_var[1] B=$abc$2385$new_n86 Y=$abc$2385$new_n88 +.subckt XOR A=$abc$2385$new_n260 B=$abc$2385$new_n265 Y=$abc$2385$new_n376 +.subckt XNOR A=$abc$2385$new_n375 B=$abc$2385$new_n376 Y=$abc$2385$new_n377 +.subckt NAND A=$abc$2385$new_n266 B=$abc$2385$new_n268 Y=$abc$2385$new_n378 +.subckt ANDNOT A=:1.test_2[7] B=:1.test_1[0] Y=$abc$2385$new_n379 +.subckt XNOR A=$abc$2385$new_n278 B=$abc$2385$new_n379 Y=$abc$2385$new_n380 +.subckt XNOR A=$abc$2385$new_n75 B=$abc$2385$new_n380 Y=$abc$2385$new_n381 +.subckt XNOR A=$abc$2385$new_n378 B=$abc$2385$new_n381 Y=$abc$2385$new_n382 +.subckt XNOR A=$abc$2385$new_n377 B=$abc$2385$new_n382 Y=$abc$2385$new_n383 +.subckt XNOR A=$abc$2385$new_n370 B=$abc$2385$new_n383 Y=$abc$2385$new_n384 +.subckt NAND A=$abc$2385$new_n283 B=$abc$2385$new_n285 Y=$abc$2385$new_n385 +.subckt ANDNOT A=$abc$2385$new_n62 B=$abc$2385$new_n88 Y=$abc$2385$new_n89 +.subckt AND A=$abc$2385$new_n272 B=$abc$2385$new_n287 Y=$abc$2385$new_n386 +.subckt XNOR A=$abc$2385$new_n385 B=$abc$2385$new_n386 Y=$abc$2385$new_n387 +.subckt XNOR A=$abc$2385$new_n384 B=$abc$2385$new_n387 Y=$abc$2385$new_n388 +.subckt XNOR A=$abc$2385$new_n366 B=$abc$2385$new_n388 Y=$abc$2385$new_n389 +.subckt XNOR A=:1.test_2[7] B=$abc$2385$new_n294 Y=$abc$2385$new_n390 +.subckt XNOR A=$abc$2385$new_n389 B=$abc$2385$new_n390 Y=$abc$2385$new_n391 +.subckt XNOR A=$abc$2385$new_n365 B=$abc$2385$new_n391 Y=$abc$2385$new_n392 +.subckt OR A=in_b_var[6] B=$abc$2385$new_n299 Y=$abc$2385$new_n393 +.subckt ORNOT A=in_b_var[6] B=in_a_var[6] Y=$abc$2385$new_n394 +.subckt ORNOT A=in_a_var[5] B=in_b_var[5] Y=$abc$2385$new_n395 +.subckt AND A=$abc$2385$new_n85 B=$abc$2385$new_n87 Y=$abc$2385$new_n90 +.subckt ORNOT A=in_b_var[5] B=in_a_var[5] Y=$abc$2385$new_n396 +.subckt ORNOT A=in_b_var[4] B=in_a_var[4] Y=$abc$2385$new_n397 +.subckt AND A=$abc$2385$new_n396 B=$abc$2385$new_n397 Y=$abc$2385$new_n398 +.subckt ORNOT A=in_b_var[2] B=in_a_var[2] Y=$abc$2385$new_n399 +.subckt ORNOT A=in_b_var[3] B=in_a_var[3] Y=$abc$2385$new_n400 +.subckt NAND A=$abc$2385$new_n399 B=$abc$2385$new_n400 Y=$abc$2385$new_n401 +.subckt ORNOT A=in_a_var[3] B=in_b_var[3] Y=$abc$2385$new_n402 +.subckt NAND A=$abc$2385$new_n401 B=$abc$2385$new_n402 Y=$abc$2385$new_n403 +.subckt ORNOT A=in_a_var[2] B=in_b_var[2] Y=$abc$2385$new_n404 +.subckt NAND A=$abc$2385$new_n402 B=$abc$2385$new_n404 Y=$abc$2385$new_n405 +.subckt XNOR A=:1.test_1[2] B=$abc$2385$new_n64 Y=$abc$2385$new_n91 +.subckt NOR A=$abc$2385$new_n401 B=$abc$2385$new_n405 Y=$abc$2385$new_n406 +.subckt ORNOT A=in_a_var[0] B=in_b_var[0] Y=$abc$2385$new_n407 +.subckt ORNOT A=in_a_var[1] B=in_b_var[1] Y=$abc$2385$new_n408 +.subckt NAND A=$abc$2385$new_n407 B=$abc$2385$new_n408 Y=$abc$2385$new_n409 +.subckt ORNOT A=in_b_var[1] B=in_a_var[1] Y=$abc$2385$new_n410 +.subckt NAND A=$abc$2385$new_n409 B=$abc$2385$new_n410 Y=$abc$2385$new_n411 +.subckt NAND A=$abc$2385$new_n406 B=$abc$2385$new_n411 Y=$abc$2385$new_n412 +.subckt NAND A=$abc$2385$new_n403 B=$abc$2385$new_n412 Y=$abc$2385$new_n413 +.subckt ORNOT A=in_a_var[4] B=in_b_var[4] Y=$abc$2385$new_n414 +.subckt NAND A=$abc$2385$new_n413 B=$abc$2385$new_n414 Y=$abc$2385$new_n415 +.subckt AND A=$abc$2385$new_n83 B=$abc$2385$new_n91 Y=$abc$2385$new_n92 +.subckt NAND A=$abc$2385$new_n398 B=$abc$2385$new_n415 Y=$abc$2385$new_n416 +.subckt NAND A=$abc$2385$new_n395 B=$abc$2385$new_n416 Y=$abc$2385$new_n417 +.subckt NAND A=$abc$2385$new_n394 B=$abc$2385$new_n417 Y=$abc$2385$new_n418 +.subckt NAND A=$abc$2385$new_n394 B=$abc$2385$new_n395 Y=$abc$2385$new_n419 +.subckt NOR A=$abc$2385$new_n409 B=$abc$2385$new_n419 Y=$abc$2385$new_n420 +.subckt AND A=$abc$2385$new_n398 B=$abc$2385$new_n420 Y=$abc$2385$new_n421 +.subckt ORNOT A=in_b_var[0] B=in_a_var[0] Y=$abc$2385$new_n422 +.subckt AND A=$abc$2385$new_n410 B=$abc$2385$new_n414 Y=$abc$2385$new_n423 +.subckt AND A=$abc$2385$new_n422 B=$abc$2385$new_n423 Y=$abc$2385$new_n424 +.subckt AND A=$abc$2385$new_n406 B=$abc$2385$new_n424 Y=$abc$2385$new_n425 +.subckt ORNOT A=$abc$2385$new_n92 B=in_a_var[2] Y=$abc$2385$new_n93 +.subckt NAND A=$abc$2385$new_n421 B=$abc$2385$new_n425 Y=$abc$2385$new_n426 +.subckt ORNOT A=in_a_var[6] B=in_b_var[6] Y=$abc$2385$new_n427 +.subckt AND A=$abc$2385$new_n151 B=$abc$2385$new_n427 Y=$abc$2385$new_n428 +.subckt AND A=$abc$2385$new_n426 B=$abc$2385$new_n428 Y=$abc$2385$new_n429 +.subckt AND A=$abc$2385$new_n418 B=$abc$2385$new_n429 Y=$abc$2385$new_n430 +.subckt AND A=$abc$2385$new_n393 B=$abc$2385$new_n430 Y=$abc$2385$new_n431 +.subckt AND A=$abc$2385$new_n392 B=$abc$2385$new_n431 Y=$abc$2385$new_n432 +.subckt AND A=$abc$2385$new_n364 B=$abc$2385$new_n432 Y=$abc$2385$new_n433 +.subckt AND A=$abc$2385$new_n358 B=$abc$2385$new_n433 Y=$abc$2385$new_n434 +.subckt AND A=$abc$2385$new_n332 B=$abc$2385$new_n434 Y=$abc$2385$new_n435 +.subckt XNOR A=in_a_var[2] B=$abc$2385$new_n92 Y=$abc$2385$new_n94 +.subckt AND A=$abc$2385$new_n157 B=$abc$2385$new_n435 Y=$abc$2385$new_n436 +.subckt XNOR A=$abc$2385$new_n157 B=$abc$2385$new_n435 Y=$abc$2385$new_n437 +.subckt ORNOT A=$abc$2385$new_n74 B=:1.test_1[0] Y=$abc$2385$new_n438 +.subckt MUX A=:1.test_1[0] B=$abc$2385$new_n437 S=$abc$2385$new_n74 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[0] +.subckt ORNOT A=:1.test_1[1] B=$abc$2385$new_n83 Y=$abc$2385$new_n440 +.subckt XNOR A=$abc$2385$new_n320 B=$abc$2385$new_n436 Y=$abc$2385$new_n441 +.subckt MUX A=$abc$2385$new_n440 B=$abc$2385$new_n441 S=$abc$2385$new_n74 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[1] +.subckt ORNOT A=:1.test_1[2] B=$abc$2385$new_n83 Y=$abc$2385$new_n443 +.subckt ANDNOT A=$abc$2385$new_n308 B=$abc$2385$new_n359 Y=$abc$2385$new_n444 +.subckt XNOR A=$abc$2385$new_n308 B=$abc$2385$new_n359 Y=$abc$2385$new_n445 +.subckt NAND A=in_b_var[2] B=$abc$2385$new_n94 Y=$abc$2385$new_n95 +.subckt NAND A=$abc$2385$new_n435 B=$abc$2385$new_n445 Y=$abc$2385$new_n446 +.subckt ORNOT A=$abc$2385$new_n435 B=$abc$2385$new_n308 Y=$abc$2385$new_n447 +.subckt AND A=$abc$2385$new_n74 B=$abc$2385$new_n446 Y=$abc$2385$new_n448 +.subckt NAND A=$abc$2385$new_n447 B=$abc$2385$new_n448 Y=$abc$2385$new_n449 +.subckt AND A=$abc$2385$new_n443 B=$abc$2385$new_n449 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[2] +.subckt ORNOT A=:1.test_1[3] B=$abc$2385$new_n83 Y=$abc$2385$new_n451 +.subckt AND A=$abc$2385$new_n435 B=$abc$2385$new_n444 Y=$abc$2385$new_n452 +.subckt AND A=$abc$2385$new_n304 B=$abc$2385$new_n452 Y=$abc$2385$new_n453 +.subckt XNOR A=$abc$2385$new_n305 B=$abc$2385$new_n452 Y=$abc$2385$new_n454 +.subckt MUX A=$abc$2385$new_n451 B=$abc$2385$new_n454 S=$abc$2385$new_n74 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[3] +.subckt NAND A=in_b_var[0] B=$abc$2385$new_n59 Y=$abc$2385$new_n60 +.subckt XNOR A=in_b_var[2] B=$abc$2385$new_n94 Y=$abc$2385$new_n96 +.subckt ORNOT A=:1.test_1[4] B=$abc$2385$new_n83 Y=$abc$2385$new_n456 +.subckt ORNOT A=$abc$2385$new_n303 B=$abc$2385$new_n453 Y=$abc$2385$new_n457 +.subckt XNOR A=$abc$2385$new_n303 B=$abc$2385$new_n453 Y=$abc$2385$new_n458 +.subckt MUX A=$abc$2385$new_n456 B=$abc$2385$new_n458 S=$abc$2385$new_n74 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[4] +.subckt ORNOT A=:1.test_1[5] B=$abc$2385$new_n83 Y=$abc$2385$new_n460 +.subckt OR A=$abc$2385$new_n302 B=$abc$2385$new_n457 Y=$abc$2385$new_n461 +.subckt XOR A=$abc$2385$new_n302 B=$abc$2385$new_n457 Y=$abc$2385$new_n462 +.subckt NAND A=$abc$2385$new_n74 B=$abc$2385$new_n462 Y=$abc$2385$new_n463 +.subckt NAND A=$abc$2385$new_n460 B=$abc$2385$new_n463 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[5] +.subckt NAND A=$abc$2385$new_n299 B=$abc$2385$new_n461 Y=$abc$2385$new_n465 +.subckt OR A=$abc$2385$new_n90 B=$abc$2385$new_n96 Y=$abc$2385$new_n97 +.subckt OR A=$abc$2385$new_n299 B=$abc$2385$new_n461 Y=$abc$2385$new_n466 +.subckt AND A=$abc$2385$new_n74 B=$abc$2385$new_n466 Y=$abc$2385$new_n467 +.subckt NAND A=$abc$2385$new_n465 B=$abc$2385$new_n467 Y=$abc$2385$new_n468 +.subckt MUX A=$abc$2385$new_n73 B=$abc$2385$new_n137 S=$abc$2385$new_n76 Y=$abc$2385$new_n469 +.subckt OR A=$abc$2385$new_n74 B=$abc$2385$new_n469 Y=$abc$2385$new_n470 +.subckt NAND A=$abc$2385$new_n468 B=$abc$2385$new_n470 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[6] +.subckt NAND A=$abc$2385$new_n392 B=$abc$2385$new_n467 Y=$abc$2385$new_n472 +.subckt ANDNOT A=$abc$2385$new_n137 B=$abc$2385$new_n76 Y=$abc$2385$new_n473 +.subckt XNOR A=$abc$2385$new_n150 B=$abc$2385$new_n473 Y=$abc$2385$new_n474 +.subckt AND A=$abc$2385$new_n472 B=$abc$2385$new_n474 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[7] +.subckt XOR A=$abc$2385$new_n90 B=$abc$2385$new_n96 Y=$abc$2385$new_n98 +.subckt AND A=$abc$2385$new_n58 B=$abc$2385$new_n438 Y=:38.Y[0] +.subckt NAND A=in_a_var[1] B=$abc$2385$new_n74 Y=$abc$2385$new_n477 +.subckt NAND A=$abc$2385$new_n84 B=$abc$2385$new_n477 Y=:38.Y[1] +.subckt NAND A=in_a_var[2] B=$abc$2385$new_n74 Y=$abc$2385$new_n479 +.subckt NAND A=$abc$2385$new_n92 B=$abc$2385$new_n479 Y=:38.Y[2] +.subckt NAND A=in_a_var[3] B=$abc$2385$new_n74 Y=$abc$2385$new_n481 +.subckt NAND A=$abc$2385$new_n104 B=$abc$2385$new_n481 Y=:38.Y[3] +.subckt NAND A=in_a_var[4] B=$abc$2385$new_n74 Y=$abc$2385$new_n483 +.subckt NAND A=$abc$2385$new_n116 B=$abc$2385$new_n483 Y=:38.Y[4] +.subckt NAND A=in_a_var[5] B=$abc$2385$new_n74 Y=$abc$2385$new_n485 +.subckt NAND A=$abc$2385$new_n89 B=$abc$2385$new_n98 Y=$abc$2385$new_n99 +.subckt NAND A=$abc$2385$new_n127 B=$abc$2385$new_n485 Y=:38.Y[5] +.subckt NAND A=in_a_var[6] B=$abc$2385$new_n74 Y=$abc$2385$new_n487 +.subckt NAND A=$abc$2385$new_n137 B=$abc$2385$new_n487 Y=:38.Y[6] +.subckt NAND A=in_a_var[7] B=$abc$2385$new_n74 Y=$abc$2385$new_n489 +.subckt NAND A=$abc$2385$new_n150 B=$abc$2385$new_n489 Y=:38.Y[7] +.subckt DFF C=clk D=$abc$2385$auto$maccmap.cc:114:fulladd$252.Y[0] Q=out_var[0] +.subckt DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.P[1] Q=out_var[1] +.subckt DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[2] Q=out_var[2] +.subckt DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[3] Q=out_var[3] +.subckt DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[4] Q=out_var[4] +.subckt XOR A=$abc$2385$new_n89 B=$abc$2385$new_n98 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[2] +.subckt DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[5] Q=out_var[5] +.subckt DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[6] Q=out_var[6] +.subckt DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[7] Q=out_var[7] +.subckt DFF C=clk D=:38.Y[0] Q=:1.test_1[0] +.subckt DFF C=clk D=:38.Y[1] Q=:1.test_1[1] +.subckt DFF C=clk D=:38.Y[2] Q=:1.test_1[2] +.subckt DFF C=clk D=:38.Y[3] Q=:1.test_1[3] +.subckt DFF C=clk D=:38.Y[4] Q=:1.test_1[4] +.subckt DFF C=clk D=:38.Y[5] Q=:1.test_1[5] +.subckt DFF C=clk D=:38.Y[6] Q=:1.test_1[6] +.subckt NAND A=$abc$2385$new_n97 B=$abc$2385$new_n99 Y=$abc$2385$new_n101 +.subckt DFF C=clk D=:38.Y[7] Q=:1.test_1[7] +.subckt DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[0] Q=:1.test_2[0] +.subckt DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[1] Q=:1.test_2[1] +.subckt DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[2] Q=:1.test_2[2] +.subckt DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[3] Q=:1.test_2[3] +.subckt DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[4] Q=:1.test_2[4] +.subckt DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[5] Q=:1.test_2[5] +.subckt DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[6] Q=:1.test_2[6] +.subckt DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[7] Q=:1.test_2[7] +.subckt AND A=$abc$2385$new_n93 B=$abc$2385$new_n95 Y=$abc$2385$new_n102 +.subckt XNOR A=:1.test_1[3] B=$abc$2385$new_n67 Y=$abc$2385$new_n103 +.subckt AND A=$abc$2385$new_n83 B=$abc$2385$new_n103 Y=$abc$2385$new_n104 +.subckt ORNOT A=$abc$2385$new_n104 B=in_a_var[3] Y=$abc$2385$new_n105 +.subckt XOR A=in_b_var[0] B=$abc$2385$new_n59 Y=$abc$2385$auto$maccmap.cc:114:fulladd$252.Y[0] +.subckt XNOR A=in_a_var[3] B=$abc$2385$new_n104 Y=$abc$2385$new_n106 +.subckt NAND A=in_b_var[3] B=$abc$2385$new_n106 Y=$abc$2385$new_n107 +.subckt XNOR A=in_b_var[3] B=$abc$2385$new_n106 Y=$abc$2385$new_n108 +.subckt OR A=$abc$2385$new_n102 B=$abc$2385$new_n108 Y=$abc$2385$new_n109 +.subckt XOR A=$abc$2385$new_n102 B=$abc$2385$new_n108 Y=$abc$2385$new_n110 +.subckt NAND A=$abc$2385$new_n101 B=$abc$2385$new_n110 Y=$abc$2385$new_n111 +.subckt XOR A=$abc$2385$new_n101 B=$abc$2385$new_n110 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[3] +.subckt NAND A=$abc$2385$new_n109 B=$abc$2385$new_n111 Y=$abc$2385$new_n113 +.subckt AND A=$abc$2385$new_n105 B=$abc$2385$new_n107 Y=$abc$2385$new_n114 +.subckt XNOR A=:1.test_1[4] B=$abc$2385$new_n68 Y=$abc$2385$new_n115 +.subckt NAND A=$abc$2385$new_n57 B=$abc$2385$new_n60 Y=$abc$2385$new_n62 +.subckt AND A=$abc$2385$new_n83 B=$abc$2385$new_n115 Y=$abc$2385$new_n116 +.subckt ORNOT A=$abc$2385$new_n116 B=in_a_var[4] Y=$abc$2385$new_n117 +.subckt XNOR A=in_a_var[4] B=$abc$2385$new_n116 Y=$abc$2385$new_n118 +.subckt NAND A=in_b_var[4] B=$abc$2385$new_n118 Y=$abc$2385$new_n119 +.subckt XNOR A=in_b_var[4] B=$abc$2385$new_n118 Y=$abc$2385$new_n120 +.subckt OR A=$abc$2385$new_n114 B=$abc$2385$new_n120 Y=$abc$2385$new_n121 +.subckt XOR A=$abc$2385$new_n114 B=$abc$2385$new_n120 Y=$abc$2385$new_n122 +.subckt NAND A=$abc$2385$new_n113 B=$abc$2385$new_n122 Y=$abc$2385$new_n123 +.subckt XOR A=$abc$2385$new_n113 B=$abc$2385$new_n122 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[4] +.subckt AND A=$abc$2385$new_n121 B=$abc$2385$new_n123 Y=$abc$2385$new_n125 +.subckt NOR A=:1.test_1[0] B=:1.test_1[1] Y=$abc$2385$new_n63 +.subckt AND A=$abc$2385$new_n117 B=$abc$2385$new_n119 Y=$abc$2385$new_n126 +.subckt AND A=$abc$2385$new_n77 B=$abc$2385$new_n83 Y=$abc$2385$new_n127 +.subckt ORNOT A=$abc$2385$new_n127 B=in_a_var[5] Y=$abc$2385$new_n128 +.subckt XNOR A=in_a_var[5] B=$abc$2385$new_n127 Y=$abc$2385$new_n129 +.subckt NAND A=in_b_var[5] B=$abc$2385$new_n129 Y=$abc$2385$new_n130 +.subckt XNOR A=in_b_var[5] B=$abc$2385$new_n129 Y=$abc$2385$new_n131 +.subckt OR A=$abc$2385$new_n126 B=$abc$2385$new_n131 Y=$abc$2385$new_n132 +.subckt NAND A=$abc$2385$new_n126 B=$abc$2385$new_n131 Y=$abc$2385$new_n133 +.subckt XOR A=$abc$2385$new_n126 B=$abc$2385$new_n131 Y=$abc$2385$new_n134 +.subckt XNOR A=$abc$2385$new_n125 B=$abc$2385$new_n134 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[5] +.subckt AND A=:1.test_1[0] B=:1.test_1[1] Y=$abc$2385$new_n64 +.subckt AND A=$abc$2385$new_n128 B=$abc$2385$new_n130 Y=$abc$2385$new_n136 +.subckt AND A=$abc$2385$new_n72 B=$abc$2385$new_n82 Y=$abc$2385$new_n137 +.subckt ORNOT A=$abc$2385$new_n137 B=in_a_var[6] Y=$abc$2385$new_n138 +.subckt XNOR A=in_a_var[6] B=$abc$2385$new_n137 Y=$abc$2385$new_n139 +.subckt NAND A=in_b_var[6] B=$abc$2385$new_n139 Y=$abc$2385$new_n140 +.subckt XNOR A=in_b_var[6] B=$abc$2385$new_n139 Y=$abc$2385$new_n141 +.subckt OR A=$abc$2385$new_n136 B=$abc$2385$new_n141 Y=$abc$2385$new_n142 +.subckt XOR A=$abc$2385$new_n136 B=$abc$2385$new_n141 Y=$abc$2385$new_n143 +.subckt NAND A=$abc$2385$new_n125 B=$abc$2385$new_n132 Y=$abc$2385$new_n144 +.subckt AND A=$abc$2385$new_n133 B=$abc$2385$new_n144 Y=$abc$2385$new_n145 +.subckt XOR A=:1.test_1[0] B=:1.test_1[1] Y=$abc$2385$new_n65 +.subckt NAND A=$abc$2385$new_n143 B=$abc$2385$new_n145 Y=$abc$2385$new_n146 +.subckt XOR A=$abc$2385$new_n143 B=$abc$2385$new_n145 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[6] +.subckt AND A=$abc$2385$new_n142 B=$abc$2385$new_n146 Y=$abc$2385$new_n148 +.subckt AND A=$abc$2385$new_n138 B=$abc$2385$new_n140 Y=$abc$2385$new_n149 +.subckt AND A=$abc$2385$new_n75 B=$abc$2385$new_n83 Y=$abc$2385$new_n150 +.subckt NOR A=in_b_var[7] B=in_a_var[7] Y=$abc$2385$new_n151 +.subckt XOR A=in_b_var[7] B=in_a_var[7] Y=$abc$2385$new_n152 +.subckt XNOR A=$abc$2385$new_n150 B=$abc$2385$new_n152 Y=$abc$2385$new_n153 +.subckt XNOR A=$abc$2385$new_n149 B=$abc$2385$new_n153 Y=$abc$2385$new_n154 +.subckt XNOR A=$abc$2385$new_n148 B=$abc$2385$new_n154 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[7] +.gateinit :1.test_2[7]=0 +.gateinit :1.test_2[6]=0 +.gateinit :1.test_2[5]=0 +.gateinit :1.test_2[4]=0 +.gateinit :1.test_2[3]=0 +.gateinit :1.test_2[2]=0 +.gateinit :1.test_2[1]=0 +.gateinit :1.test_2[0]=0 +.gateinit :1.test_1[7]=1 +.gateinit :1.test_1[6]=1 +.gateinit :1.test_1[5]=1 +.gateinit :1.test_1[4]=1 +.gateinit :1.test_1[3]=1 +.gateinit :1.test_1[2]=1 +.gateinit :1.test_1[1]=1 +.gateinit :1.test_1[0]=1 +.end diff --git a/tests/blif/gatesi.ys b/tests/blif/gatesi.ys new file mode 100644 index 000000000..44c022bb9 --- /dev/null +++ b/tests/blif/gatesi.ys @@ -0,0 +1,2 @@ +read_blif gatesi.blif +write_blif -gatesi gatesi.blif.out \ No newline at end of file diff --git a/tests/blif/run-test.sh b/tests/blif/run-test.sh index 2e3f5235c..14b9ead8e 100755 --- a/tests/blif/run-test.sh +++ b/tests/blif/run-test.sh @@ -3,5 +3,9 @@ source ../common-env.sh set -e for x in *.ys; do echo "Running $x.." - ../../yosys -ql ${x%.ys}.log $x + ../../yosys --no-version -ql ${x%.ys}.log $x done + +for x in *.blif; do + diff $x.out $x.ok +done \ No newline at end of file From 60ac3670cbcf320275fc7cf31ece78638fa6e87f Mon Sep 17 00:00:00 2001 From: Natalia Date: Wed, 14 Jan 2026 13:12:55 -0800 Subject: [PATCH 057/291] Fix truncation issue in opt_balance_tree pass Only allow rebalancing of cells with "natural" output widths (no truncation). This prevents equivalence failures when moving operands between adders with different intermediate truncation points. For each operation type, the natural width is: - Addition: max(A_WIDTH, B_WIDTH) + 1 (for carry bit) - Multiplication: A_WIDTH + B_WIDTH - Logic ops: max(A_WIDTH, B_WIDTH) Fixes widlarizer's counterexample in YosysHQ/yosys#5605 where an 8-bit intermediate wire was intentionally truncating adder results, and rebalancing would change where that truncation occurred. --- passes/opt/opt_balance_tree.cc | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/passes/opt/opt_balance_tree.cc b/passes/opt/opt_balance_tree.cc index 8811b1331..9e4fa0620 100644 --- a/passes/opt/opt_balance_tree.cc +++ b/passes/opt/opt_balance_tree.cc @@ -36,10 +36,31 @@ struct OptBalanceTreeWorker { dict cell_count; // Check if cell is of the right type and has matching input/output widths + // Only allow cells with "natural" output widths (no truncation) to prevent + // equivalence issues when rebalancing (see YosysHQ/yosys#5605) bool is_right_type(Cell* cell, IdString cell_type) { - return cell->type == cell_type && - cell->getParam(ID::Y_WIDTH).as_int() >= cell->getParam(ID::A_WIDTH).as_int() && - cell->getParam(ID::Y_WIDTH).as_int() >= cell->getParam(ID::B_WIDTH).as_int(); + if (cell->type != cell_type) + return false; + + int y_width = cell->getParam(ID::Y_WIDTH).as_int(); + int a_width = cell->getParam(ID::A_WIDTH).as_int(); + int b_width = cell->getParam(ID::B_WIDTH).as_int(); + + // Calculate the "natural" output width for this operation + int natural_width; + if (cell_type == ID($add)) { + // Addition produces max(A_WIDTH, B_WIDTH) + 1 (for carry bit) + natural_width = std::max(a_width, b_width) + 1; + } else if (cell_type == ID($mul)) { + // Multiplication produces A_WIDTH + B_WIDTH + natural_width = a_width + b_width; + } else { + // Logic operations ($and/$or/$xor) produce max(A_WIDTH, B_WIDTH) + natural_width = std::max(a_width, b_width); + } + + // Only allow cells where Y_WIDTH equals the natural width (no truncation) + return y_width == natural_width; } // Create a balanced binary tree from a vector of source signals From 305b6c81d7a39a4ee46f94eaded2162e2dd74eb3 Mon Sep 17 00:00:00 2001 From: Natalia Date: Wed, 14 Jan 2026 14:58:53 -0800 Subject: [PATCH 058/291] Refine width check to allow Y_WIDTH >= natural width Change from equality check to >= to allow cells where output is wider than natural width (zero-extended). Only reject cells with Y_WIDTH < natural width (truncated). This fixes test failures while still preventing the truncation issue identified in widlarizer's feedback. --- passes/opt/opt_balance_tree.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/passes/opt/opt_balance_tree.cc b/passes/opt/opt_balance_tree.cc index 9e4fa0620..5c19e3975 100644 --- a/passes/opt/opt_balance_tree.cc +++ b/passes/opt/opt_balance_tree.cc @@ -59,8 +59,9 @@ struct OptBalanceTreeWorker { natural_width = std::max(a_width, b_width); } - // Only allow cells where Y_WIDTH equals the natural width (no truncation) - return y_width == natural_width; + // Only allow cells where Y_WIDTH >= natural width (no truncation) + // This prevents rebalancing chains where truncation semantics matter + return y_width >= natural_width; } // Create a balanced binary tree from a vector of source signals From 967b47d98412bb34b1e32fb9b31ba91792db1d3e Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Thu, 15 Jan 2026 00:24:54 +0000 Subject: [PATCH 059/291] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 00d20bb9a..775cf8828 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.61+18 +YOSYS_VER := 0.61+21 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From fb864e91ee7ba47cc52a38024c353acec156b78a Mon Sep 17 00:00:00 2001 From: Natalia Date: Wed, 14 Jan 2026 17:35:45 -0800 Subject: [PATCH 060/291] Add Design::run_pass() API for programmatic pass execution This commit adds a new run_pass() method to the RTLIL::Design class, providing a convenient API for executing Yosys passes programmatically. This is particularly useful for PyYosys users who want to run passes on a design object without needing to manually construct Pass::call() invocations. The method wraps Pass::call() with appropriate logging to maintain consistency with command-line pass execution. Example usage (from Python): design = ys.Design() # ... build or load design ... design.run_pass("hierarchy") design.run_pass("proc") design.run_pass("opt") Changes: - kernel/rtlil.h: Add run_pass() method declaration - kernel/rtlil.cc: Implement run_pass() method - tests/unit/kernel/test_design_run_pass.cc: Add unit tests --- kernel/rtlil.cc | 7 +++ kernel/rtlil.h | 3 ++ tests/unit/kernel/test_design_run_pass.cc | 59 +++++++++++++++++++++++ 3 files changed, 69 insertions(+) create mode 100644 tests/unit/kernel/test_design_run_pass.cc diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 0103cabfb..357ac2c5a 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1610,6 +1610,13 @@ std::vector RTLIL::Design::selected_modules(RTLIL::SelectPartial return result; } +void RTLIL::Design::run_pass(std::string command) +{ + log("\n-- Running command `%s' --\n", command.c_str()); + Pass::call(this, command); + log_flush(); +} + RTLIL::Module::Module() { static unsigned int hashidx_count = 123456789; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index fe280c965..532aa20b4 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -2031,6 +2031,9 @@ struct RTLIL::Design // returns all selected unboxed whole modules, warning the user if any // partially selected or boxed modules have been ignored std::vector selected_unboxed_whole_modules_warn() const { return selected_modules(SELECT_WHOLE_WARN, SB_UNBOXED_WARN); } + + void run_pass(std::string command); + static std::map *get_all_designs(void); std::string to_rtlil_str(bool only_selected = true) const; diff --git a/tests/unit/kernel/test_design_run_pass.cc b/tests/unit/kernel/test_design_run_pass.cc new file mode 100644 index 000000000..0553f4eb2 --- /dev/null +++ b/tests/unit/kernel/test_design_run_pass.cc @@ -0,0 +1,59 @@ +#include +#include "kernel/rtlil.h" +#include "kernel/register.h" + +YOSYS_NAMESPACE_BEGIN + +class DesignRunPassTest : public testing::Test { +protected: + DesignRunPassTest() { + if (log_files.empty()) log_files.emplace_back(stdout); + } + virtual void SetUp() override { + IdString::ensure_prepopulated(); + } +}; + +TEST_F(DesignRunPassTest, RunPassExecutesSuccessfully) +{ + // Create a design with a simple module + RTLIL::Design *design = new RTLIL::Design; + RTLIL::Module *module = new RTLIL::Module; + module->name = RTLIL::IdString("\\test_module"); + design->add(module); + + // Add a simple wire to the module + RTLIL::Wire *wire = module->addWire(RTLIL::IdString("\\test_wire"), 1); + wire->port_input = true; + wire->port_id = 1; + module->fixup_ports(); + + // Call run_pass with a simple pass + // We use "check" which is a simple pass that just validates the design + ASSERT_NO_THROW(design->run_pass("check")); + + // Verify the design still exists and has the module + EXPECT_EQ(design->modules().size(), 1); + EXPECT_NE(design->module(RTLIL::IdString("\\test_module")), nullptr); + + delete design; +} + +TEST_F(DesignRunPassTest, RunPassWithHierarchy) +{ + // Create a design with a simple module + RTLIL::Design *design = new RTLIL::Design; + RTLIL::Module *module = new RTLIL::Module; + module->name = RTLIL::IdString("\\top"); + design->add(module); + + // Call run_pass with hierarchy pass + ASSERT_NO_THROW(design->run_pass("hierarchy")); + + // Verify the design still has the module + EXPECT_EQ(design->modules().size(), 1); + + delete design; +} + +YOSYS_NAMESPACE_END From d5e1647d1167a0943a2b2c488ce63291c35d3972 Mon Sep 17 00:00:00 2001 From: Natalia Date: Wed, 14 Jan 2026 17:06:01 -0800 Subject: [PATCH 061/291] fix tests with truncation issues --- tests/opt/opt_balance_tree.ys | 154 +++++----------------------------- 1 file changed, 22 insertions(+), 132 deletions(-) diff --git a/tests/opt/opt_balance_tree.ys b/tests/opt/opt_balance_tree.ys index 508f5fc24..6f8b8b711 100644 --- a/tests/opt/opt_balance_tree.ys +++ b/tests/opt/opt_balance_tree.ys @@ -385,7 +385,7 @@ log -pop # Test 8 -log -header "Simple 1-bit ADD chain" +log -header "Simple 1-bit ADD chain (4 inputs)" log -push design -reset read_verilog < Date: Thu, 15 Jan 2026 12:07:26 -0800 Subject: [PATCH 062/291] Add -on/-off modes to debug pass --- passes/cmds/trace.cc | 31 ++++++++++++++++++++++++++++++- tests/various/debugon.ys | 14 ++++++++++++++ 2 files changed, 44 insertions(+), 1 deletion(-) create mode 100644 tests/various/debugon.ys diff --git a/passes/cmds/trace.cc b/passes/cmds/trace.cc index df7b665d5..222fecaca 100644 --- a/passes/cmds/trace.cc +++ b/passes/cmds/trace.cc @@ -115,16 +115,45 @@ struct DebugPass : public Pass { log("\n"); log("Execute the specified command with debug log messages enabled\n"); log("\n"); + log(" debug -on\n"); + log(" debug -off\n"); + log("\n"); + log("Enable or disable debug log messages globally\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) override { size_t argidx; + bool mode_on = false; + bool mode_off = false; + for (argidx = 1; argidx < args.size(); argidx++) { - // .. parse options .. + if (args[argidx] == "-on") { + mode_on = true; + continue; + } + if (args[argidx] == "-off") { + mode_off = true; + continue; + } break; } + if (mode_on && mode_off) + log_cmd_error("Cannot specify both -on and -off\n"); + + if (mode_on) { + log_force_debug++; + return; + } + + if (mode_off) { + if (log_force_debug > 0) + log_force_debug--; + return; + } + log_force_debug++; try { diff --git a/tests/various/debugon.ys b/tests/various/debugon.ys new file mode 100644 index 000000000..a984a26bb --- /dev/null +++ b/tests/various/debugon.ys @@ -0,0 +1,14 @@ +# Test debug -on/-off modes + +design -reset + +read_verilog < Date: Fri, 16 Jan 2026 07:56:53 +0100 Subject: [PATCH 063/291] verific: add explicit System Verilog 2017 option --- frontends/verific/verific.cc | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 5790e92f0..63023a306 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3161,7 +3161,7 @@ struct VerificPass : public Pass { #endif #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT log(" verific {-f|-F} [-vlog95|-vlog2k|-sv2005|-sv2009|\n"); - log(" -sv2012|-sv|-formal] \n"); + log(" -sv2012|-sv2017|-sv|-formal] \n"); log("\n"); log("Load and execute the specified command file.\n"); log("Override verilog parsing mode can be set.\n"); @@ -3753,7 +3753,8 @@ struct VerificPass : public Pass { } if (GetSize(args) > argidx && (args[argidx] == "-vlog95" || args[argidx] == "-vlog2k" || args[argidx] == "-sv2005" || - args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal")) + args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv2017" || args[argidx] == "-sv" || + args[argidx] == "-formal")) { Array file_names; unsigned verilog_mode; @@ -3766,7 +3767,11 @@ struct VerificPass : public Pass { verilog_mode = veri_file::SYSTEM_VERILOG_2005; else if (args[argidx] == "-sv2009") verilog_mode = veri_file::SYSTEM_VERILOG_2009; - else if (args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal") + else if (args[argidx] == "-sv2012") + verilog_mode = veri_file::SYSTEM_VERILOG_2012; + else if (args[argidx] == "-sv2017") + verilog_mode = veri_file::SYSTEM_VERILOG_2017; + else if (args[argidx] == "-sv" || args[argidx] == "-formal") verilog_mode = veri_file::SYSTEM_VERILOG; else log_abort(); From cf511628b0dc3ec3cc3d372cab3f74f0208f79cc Mon Sep 17 00:00:00 2001 From: Natalia Date: Sun, 18 Jan 2026 02:11:09 -0800 Subject: [PATCH 064/291] modify generator for pyosys/wrappers.cc instead of headers --- kernel/rtlil.cc | 7 --- kernel/rtlil.h | 2 - pyosys/generator.py | 10 ++++ tests/pyosys/test_design_run_pass.py | 12 +++++ tests/unit/kernel/test_design_run_pass.cc | 59 ----------------------- 5 files changed, 22 insertions(+), 68 deletions(-) create mode 100644 tests/pyosys/test_design_run_pass.py delete mode 100644 tests/unit/kernel/test_design_run_pass.cc diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 357ac2c5a..0103cabfb 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1610,13 +1610,6 @@ std::vector RTLIL::Design::selected_modules(RTLIL::SelectPartial return result; } -void RTLIL::Design::run_pass(std::string command) -{ - log("\n-- Running command `%s' --\n", command.c_str()); - Pass::call(this, command); - log_flush(); -} - RTLIL::Module::Module() { static unsigned int hashidx_count = 123456789; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 532aa20b4..fea53081e 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -2032,8 +2032,6 @@ struct RTLIL::Design // partially selected or boxed modules have been ignored std::vector selected_unboxed_whole_modules_warn() const { return selected_modules(SELECT_WHOLE_WARN, SB_UNBOXED_WARN); } - void run_pass(std::string command); - static std::map *get_all_designs(void); std::string to_rtlil_str(bool only_selected = true) const; diff --git a/pyosys/generator.py b/pyosys/generator.py index 7d4293abd..0dda98015 100644 --- a/pyosys/generator.py +++ b/pyosys/generator.py @@ -701,6 +701,16 @@ class PyosysWrapperGenerator(object): self.process_class_members(metadata, metadata, cls, basename) + if basename == "Design": + print( + '\t\t\t.def("run_pass", [](Design &s, std::vector cmd) { Pass::call(cmd, &s); })', + file=self.f, + ) + print( + '\t\t\t.def("run_pass", [](Design &s, std::string cmd) { Pass::call(cmd, &s); })', + file=self.f, + ) + if expr := metadata.string_expr: print( f'\t\t.def("__str__", [](const {basename} &s) {{ return {expr}; }})', diff --git a/tests/pyosys/test_design_run_pass.py b/tests/pyosys/test_design_run_pass.py new file mode 100644 index 000000000..c9656fd7a --- /dev/null +++ b/tests/pyosys/test_design_run_pass.py @@ -0,0 +1,12 @@ +from pathlib import Path + +from pyosys import libyosys as ys + +__file_dir__ = Path(__file__).absolute().parent + +design = ys.Design() +design.run_pass( + ["read_verilog", str(__file_dir__.parent / "simple" / "fiedler-cooley.v")] +) +design.run_pass("prep") +design.run_pass(["opt", "-full"]) diff --git a/tests/unit/kernel/test_design_run_pass.cc b/tests/unit/kernel/test_design_run_pass.cc deleted file mode 100644 index 0553f4eb2..000000000 --- a/tests/unit/kernel/test_design_run_pass.cc +++ /dev/null @@ -1,59 +0,0 @@ -#include -#include "kernel/rtlil.h" -#include "kernel/register.h" - -YOSYS_NAMESPACE_BEGIN - -class DesignRunPassTest : public testing::Test { -protected: - DesignRunPassTest() { - if (log_files.empty()) log_files.emplace_back(stdout); - } - virtual void SetUp() override { - IdString::ensure_prepopulated(); - } -}; - -TEST_F(DesignRunPassTest, RunPassExecutesSuccessfully) -{ - // Create a design with a simple module - RTLIL::Design *design = new RTLIL::Design; - RTLIL::Module *module = new RTLIL::Module; - module->name = RTLIL::IdString("\\test_module"); - design->add(module); - - // Add a simple wire to the module - RTLIL::Wire *wire = module->addWire(RTLIL::IdString("\\test_wire"), 1); - wire->port_input = true; - wire->port_id = 1; - module->fixup_ports(); - - // Call run_pass with a simple pass - // We use "check" which is a simple pass that just validates the design - ASSERT_NO_THROW(design->run_pass("check")); - - // Verify the design still exists and has the module - EXPECT_EQ(design->modules().size(), 1); - EXPECT_NE(design->module(RTLIL::IdString("\\test_module")), nullptr); - - delete design; -} - -TEST_F(DesignRunPassTest, RunPassWithHierarchy) -{ - // Create a design with a simple module - RTLIL::Design *design = new RTLIL::Design; - RTLIL::Module *module = new RTLIL::Module; - module->name = RTLIL::IdString("\\top"); - design->add(module); - - // Call run_pass with hierarchy pass - ASSERT_NO_THROW(design->run_pass("hierarchy")); - - // Verify the design still has the module - EXPECT_EQ(design->modules().size(), 1); - - delete design; -} - -YOSYS_NAMESPACE_END From b43c96b03da9a3d1a4ea358c6bc0920f5723f3e0 Mon Sep 17 00:00:00 2001 From: Natalia Date: Sun, 18 Jan 2026 02:24:36 -0800 Subject: [PATCH 065/291] fix pyosys Design.run_pass binding to use Pass::call signature --- pyosys/generator.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pyosys/generator.py b/pyosys/generator.py index 0dda98015..f1d429724 100644 --- a/pyosys/generator.py +++ b/pyosys/generator.py @@ -703,11 +703,11 @@ class PyosysWrapperGenerator(object): if basename == "Design": print( - '\t\t\t.def("run_pass", [](Design &s, std::vector cmd) { Pass::call(cmd, &s); })', + '\t\t\t.def("run_pass", [](Design &s, std::vector cmd) { Pass::call(&s, cmd); })', file=self.f, ) print( - '\t\t\t.def("run_pass", [](Design &s, std::string cmd) { Pass::call(cmd, &s); })', + '\t\t\t.def("run_pass", [](Design &s, std::string cmd) { Pass::call(&s, cmd); })', file=self.f, ) From 28c199fbbd4f6788370b1d9d4683ace009ddecc3 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Mon, 19 Jan 2026 03:25:09 +0000 Subject: [PATCH 066/291] Fix warning about unused variable in `dffunmap`. --- passes/techmap/dffunmap.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/passes/techmap/dffunmap.cc b/passes/techmap/dffunmap.cc index 020597c4b..e72c250bb 100644 --- a/passes/techmap/dffunmap.cc +++ b/passes/techmap/dffunmap.cc @@ -78,7 +78,6 @@ struct DffunmapPass : public Pass { continue; FfData ff(&initvals, cell); - IdString name = cell->name; if (!ff.has_clk) continue; From befadf6d4dfb52c331230aa5bd423a0c8b55ef48 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 19 Jan 2026 12:00:18 +0100 Subject: [PATCH 067/291] consteval: describe --- kernel/consteval.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/kernel/consteval.h b/kernel/consteval.h index b13c7ea5c..ca04d722f 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -27,6 +27,10 @@ YOSYS_NAMESPACE_BEGIN +/** + * ConstEval provides on-demand constant propagation by traversing input cones + * with caching + */ struct ConstEval { RTLIL::Module *module; From c3f36afe7f548bc6358cf6965d60b397f230cec3 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 19 Jan 2026 12:01:25 +0100 Subject: [PATCH 068/291] opt_balance_tree: mark experimental --- passes/opt/opt_balance_tree.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/passes/opt/opt_balance_tree.cc b/passes/opt/opt_balance_tree.cc index 5c19e3975..129a27376 100644 --- a/passes/opt/opt_balance_tree.cc +++ b/passes/opt/opt_balance_tree.cc @@ -340,6 +340,7 @@ struct OptBalanceTreePass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing OPT_BALANCE_TREE pass (cell cascades to trees).\n"); + log_experimental("open_balance_tree"); // Handle arguments size_t argidx; From 691983be1492923ea149828552c5d3a9888452ee Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 19 Jan 2026 12:08:24 +0100 Subject: [PATCH 069/291] Update ABC as per 2026-01-19 --- abc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/abc b/abc index 799ba6322..01ad37aad 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit 799ba632239b2a4db2bacda81de4e6efdc486b0c +Subproject commit 01ad37aada7566964219c993818af75234f93ce0 From cc3038f4682a94561bc34edfcd8adf197a9debe1 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 19 Jan 2026 16:32:46 +0100 Subject: [PATCH 070/291] verific: Fix -sv2017 message --- frontends/verific/verific.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 63023a306..bace13563 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3114,9 +3114,10 @@ struct VerificPass : public Pass { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT - log(" verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv} ..\n"); + log(" verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv2017|-sv} ..\n"); log("\n"); log("Load the specified Verilog/SystemVerilog files into Verific.\n"); + log("Note that -sv option will use parser for latest supported standard.\n"); log("\n"); log("All files specified in one call to this command are one compilation unit.\n"); log("Files passed to different calls to this command are treated as belonging to\n"); From 0f478a5952da2e6c6b2e0cca99a78486d9fe4c01 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 20 Jan 2026 05:56:14 +1300 Subject: [PATCH 071/291] tests/bug5574: Fix for non threaded abc --- tests/techmap/bug5574.ys | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/tests/techmap/bug5574.ys b/tests/techmap/bug5574.ys index d986e688d..56b290a4a 100644 --- a/tests/techmap/bug5574.ys +++ b/tests/techmap/bug5574.ys @@ -1,8 +1,11 @@ -logger -expect error "ABC: Error: This command can only be applied to an AIG" 1 +# On Linux, with a spawned abc, this message is the error +# otherwise the error is the failure to load the output.blif +logger -expect log "ABC: Error: This command can only be applied to an AIG" 1 +logger -expect error "ABC" 1 read_verilog << EOT module fuzz_mwoqk (input i0, output o0); assign o0 = i0 ^ 1; endmodule EOT synth -abc -script +resub,-K,8; \ No newline at end of file +abc -script +resub,-K,8; From 49e5950791c9dd256e30820134097c1e2f66ed72 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 20 Jan 2026 00:26:10 +0000 Subject: [PATCH 072/291] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 775cf8828..8205bb3ed 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.61+21 +YOSYS_VER := 0.61+39 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From f67d4bcfa4893c51d1f314bc60a1d4923e5de3f9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 7 Mar 2024 15:19:17 +0100 Subject: [PATCH 073/291] verilog: Do not set `module_not_derived` on internal cells --- frontends/ast/genrtlil.cc | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 86ea70b51..d9eb51a9c 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -2085,8 +2085,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) check_unique_id(current_module, id, this, "cell"); RTLIL::Cell *cell = current_module->addCell(id, ""); set_src_attr(cell, this); - // Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass - cell->set_bool_attribute(ID::module_not_derived); for (auto it = children.begin(); it != children.end(); it++) { auto* child = it->get(); @@ -2149,6 +2147,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } log_abort(); } + + // Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass + if (cell->type.isPublic()) + cell->set_bool_attribute(ID::module_not_derived); + for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) input_error("Attribute `%s' with non-constant value.\n", attr.first); From 90673cb0a261c0a8032cab8d2e44a5f4c16945d3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 7 Mar 2024 15:20:15 +0100 Subject: [PATCH 074/291] techmap: Use `-icells` mode of frontend instead of type fixup --- passes/techmap/techmap.cc | 31 ++++++------------------------- 1 file changed, 6 insertions(+), 25 deletions(-) diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index b49a40704..cf7ce56e2 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -333,9 +333,6 @@ struct TechmapWorker RTLIL::Cell *c = module->addCell(c_name, tpl_cell); design->select(module, c); - - if (c->type.begins_with("\\$")) - c->type = c->type.substr(1); if (c->type == ID::_TECHMAP_PLACEHOLDER_ && tpl_cell->has_attribute(ID::techmap_chtype)) { c->type = RTLIL::escape_id(tpl_cell->get_string_attribute(ID::techmap_chtype)); @@ -436,13 +433,9 @@ struct TechmapWorker if (handled_cells.count(cell) > 0) continue; - std::string cell_type = cell->type.str(); - if (in_recursion && cell->type.begins_with("\\$")) - cell_type = cell_type.substr(1); - - if (celltypeMap.count(cell_type) == 0) { - if (assert_mode && cell_type.back() != '_') - log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell_type)); + if (celltypeMap.count(cell->type) == 0) { + if (assert_mode && !cell->type.ends_with("_")) + log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell->type)); continue; } @@ -454,7 +447,7 @@ struct TechmapWorker if (GetSize(sig) == 0) continue; - for (auto &tpl_name : celltypeMap.at(cell_type)) { + for (auto &tpl_name : celltypeMap.at(cell->type)) { RTLIL::Module *tpl = map->module(tpl_name); RTLIL::Wire *port = tpl->wire(conn.first); if (port && port->port_input) @@ -481,12 +474,7 @@ struct TechmapWorker log_assert(cell == module->cell(cell->name)); bool mapped_cell = false; - std::string cell_type = cell->type.str(); - - if (in_recursion && cell->type.begins_with("\\$")) - cell_type = cell_type.substr(1); - - for (auto &tpl_name : celltypeMap.at(cell_type)) + for (auto &tpl_name : celltypeMap.at(cell->type)) { IdString derived_name = tpl_name; RTLIL::Module *tpl = map->module(tpl_name); @@ -508,8 +496,6 @@ struct TechmapWorker if (!extmapper_name.empty()) { - cell->type = cell_type; - if ((extern_mode && !in_recursion) || extmapper_name == "wrap") { std::string m_name = stringf("$extern:%s:%s", extmapper_name, log_id(cell->type)); @@ -935,11 +921,6 @@ struct TechmapWorker RTLIL::Module *m = design->addModule(m_name); tpl->cloneInto(m); - for (auto cell : m->cells()) { - if (cell->type.begins_with("\\$")) - cell->type = cell->type.substr(1); - } - module_queue.insert(m); } @@ -1168,7 +1149,7 @@ struct TechmapPass : public Pass { std::vector map_files; std::vector dont_map; - std::string verilog_frontend = "verilog -nooverwrite -noblackbox"; + std::string verilog_frontend = "verilog -nooverwrite -noblackbox -icells"; int max_iter = -1; size_t argidx; From 491276983ee1bd1004acd4e6fea71c2976b83732 Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Mon, 19 Jan 2026 18:34:55 -0800 Subject: [PATCH 075/291] Add test --- tests/techmap/module_not_derived.ys | 31 +++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 tests/techmap/module_not_derived.ys diff --git a/tests/techmap/module_not_derived.ys b/tests/techmap/module_not_derived.ys new file mode 100644 index 000000000..299e4b75b --- /dev/null +++ b/tests/techmap/module_not_derived.ys @@ -0,0 +1,31 @@ +# Test 1: internal cells from alumacc/techmap must not keep module_not_derived. +read_verilog < Date: Tue, 20 Jan 2026 08:07:26 +0100 Subject: [PATCH 076/291] verific: Fix -sv2017 message and formatting --- frontends/verific/verific.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index bace13563..92df86fd5 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3114,10 +3114,11 @@ struct VerificPass : public Pass { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT - log(" verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv2017|-sv} ..\n"); + log(" verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|\n"); + log(" -sv2017|-sv} ..\n"); log("\n"); log("Load the specified Verilog/SystemVerilog files into Verific.\n"); - log("Note that -sv option will use parser for latest supported standard.\n"); + log("Note that -sv option will use latest supported SystemVerilog standard.\n"); log("\n"); log("All files specified in one call to this command are one compilation unit.\n"); log("Files passed to different calls to this command are treated as belonging to\n"); From 5a9d73369abd5e1ca03ce09ff748901cb8e83cfb Mon Sep 17 00:00:00 2001 From: Lofty Date: Tue, 20 Jan 2026 09:51:53 +0000 Subject: [PATCH 077/291] abc9: verify post-mapping equivalence by default --- passes/techmap/abc9_exe.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc index 4449065f8..2baf53a02 100644 --- a/passes/techmap/abc9_exe.cc +++ b/passes/techmap/abc9_exe.cc @@ -248,7 +248,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe } abc9_script += stringf("; &ps -l; &write -n %s/output.aig", tempdir_name); - if (design->scratchpad_get_bool("abc9.verify")) { + if (design->scratchpad_get_bool("abc9.verify", true)) { if (dff_mode) abc9_script += "; &verify -s"; else From 9315f02c17ef5b3149a4767d9851045f2cee15cb Mon Sep 17 00:00:00 2001 From: Gabriel Gouvine Date: Mon, 25 Mar 2024 11:33:52 +0000 Subject: [PATCH 078/291] ezsat: New Sat class to call an external command --- Makefile | 2 + libs/ezsat/ezcommand.cc | 83 +++++++++++++++++++++++++++++++++++++++++ libs/ezsat/ezcommand.h | 36 ++++++++++++++++++ 3 files changed, 121 insertions(+) create mode 100644 libs/ezsat/ezcommand.cc create mode 100644 libs/ezsat/ezcommand.h diff --git a/Makefile b/Makefile index 8205bb3ed..afe559712 100644 --- a/Makefile +++ b/Makefile @@ -638,6 +638,7 @@ $(eval $(call add_include_file,kernel/yosys_common.h)) $(eval $(call add_include_file,kernel/yw.h)) $(eval $(call add_include_file,libs/ezsat/ezsat.h)) $(eval $(call add_include_file,libs/ezsat/ezminisat.h)) +$(eval $(call add_include_file,libs/ezsat/ezcommand.h)) ifeq ($(ENABLE_ZLIB),1) $(eval $(call add_include_file,libs/fst/fstapi.h)) endif @@ -683,6 +684,7 @@ OBJS += libs/json11/json11.o OBJS += libs/ezsat/ezsat.o OBJS += libs/ezsat/ezminisat.o +OBJS += libs/ezsat/ezcommand.o OBJS += libs/minisat/Options.o OBJS += libs/minisat/SimpSolver.o diff --git a/libs/ezsat/ezcommand.cc b/libs/ezsat/ezcommand.cc new file mode 100644 index 000000000..10104a2cd --- /dev/null +++ b/libs/ezsat/ezcommand.cc @@ -0,0 +1,83 @@ + +#include "ezcommand.h" + +#include "../../kernel/yosys.h" + +ezSATCommand::ezSATCommand(const std::string &cmd) : command(cmd) {} + +ezSATCommand::~ezSATCommand() {} + +bool ezSATCommand::solver(const std::vector &modelExpressions, std::vector &modelValues, const std::vector &assumptions) +{ + if (!assumptions.empty()) { + Yosys::log_error("Assumptions are not supported yet by command-based Sat solver\n"); + } + const std::string tempdir_name = Yosys::make_temp_dir(Yosys::get_base_tmpdir() + "/yosys-sat-XXXXXX"); + const std::string cnf_filename = Yosys::stringf("%s/problem.cnf", tempdir_name.c_str()); + const std::string sat_command = Yosys::stringf("%s %s", command.c_str(), cnf_filename.c_str()); + FILE *dimacs = fopen(cnf_filename.c_str(), "w"); + printDIMACS(dimacs); + fclose(dimacs); + + std::vector modelIdx; + for (auto id : modelExpressions) + modelIdx.push_back(bind(id)); + + bool status_sat = false; + bool status_unsat = false; + std::vector values; + + auto line_callback = [&](const std::string &line) { + if (line.empty()) { + return; + } + if (line[0] == 's') { + if (line.substr(0, 5) == "s SAT") { + status_sat = true; + } + if (line.substr(0, 7) == "s UNSAT") { + status_unsat = true; + } + return; + } + if (line[0] == 'v') { + std::stringstream ss(line.substr(1)); + int lit; + while (ss >> lit) { + if (lit == 0) { + return; + } + bool val = lit >= 0; + int ind = lit >= 0 ? lit - 1 : -lit - 1; + if (Yosys::GetSize(values) <= ind) { + values.resize(ind + 1); + } + values[ind] = val; + } + } + }; + if (Yosys::run_command(sat_command, line_callback) != 0) { + Yosys::log_cmd_error("Shell command failed!\n"); + } + + modelValues.clear(); + modelValues.resize(modelIdx.size()); + + if (!status_sat && !status_unsat) { + solverTimoutStatus = true; + } + if (!status_sat) { + return false; + } + + for (size_t i = 0; i < modelIdx.size(); i++) { + int idx = modelIdx[i]; + bool refvalue = true; + + if (idx < 0) + idx = -idx, refvalue = false; + + modelValues[i] = (values.at(idx - 1) == refvalue); + } + return true; +} \ No newline at end of file diff --git a/libs/ezsat/ezcommand.h b/libs/ezsat/ezcommand.h new file mode 100644 index 000000000..a0e3de4ed --- /dev/null +++ b/libs/ezsat/ezcommand.h @@ -0,0 +1,36 @@ +/* + * ezSAT -- A simple and easy to use CNF generator for SAT solvers + * + * Copyright (C) 2013 Claire Xenia Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef EZSATCOMMAND_H +#define EZSATCOMMAND_H + +#include "ezsat.h" + +class ezSATCommand : public ezSAT +{ +private: + std::string command; + +public: + ezSATCommand(const std::string &cmd); + virtual ~ezSATCommand(); + bool solver(const std::vector &modelExpressions, std::vector &modelValues, const std::vector &assumptions) override; +}; + +#endif From 12315c0d17c911a971298e233c4a1d1aa291c9c7 Mon Sep 17 00:00:00 2001 From: Gabriel Gouvine Date: Thu, 28 Mar 2024 09:56:48 +0000 Subject: [PATCH 079/291] ezsat: Support for assumptions in Sat command --- libs/ezsat/ezcommand.cc | 11 ++++++----- libs/ezsat/ezsat.cc | 6 ++++-- libs/ezsat/ezsat.h | 2 +- 3 files changed, 11 insertions(+), 8 deletions(-) diff --git a/libs/ezsat/ezcommand.cc b/libs/ezsat/ezcommand.cc index 10104a2cd..c2925b647 100644 --- a/libs/ezsat/ezcommand.cc +++ b/libs/ezsat/ezcommand.cc @@ -9,19 +9,20 @@ ezSATCommand::~ezSATCommand() {} bool ezSATCommand::solver(const std::vector &modelExpressions, std::vector &modelValues, const std::vector &assumptions) { - if (!assumptions.empty()) { - Yosys::log_error("Assumptions are not supported yet by command-based Sat solver\n"); - } const std::string tempdir_name = Yosys::make_temp_dir(Yosys::get_base_tmpdir() + "/yosys-sat-XXXXXX"); const std::string cnf_filename = Yosys::stringf("%s/problem.cnf", tempdir_name.c_str()); const std::string sat_command = Yosys::stringf("%s %s", command.c_str(), cnf_filename.c_str()); FILE *dimacs = fopen(cnf_filename.c_str(), "w"); - printDIMACS(dimacs); - fclose(dimacs); std::vector modelIdx; for (auto id : modelExpressions) modelIdx.push_back(bind(id)); + std::vector> extraClauses; + for (auto id : assumptions) + extraClauses.push_back({bind(id)}); + + printDIMACS(dimacs, false, extraClauses); + fclose(dimacs); bool status_sat = false; bool status_unsat = false; diff --git a/libs/ezsat/ezsat.cc b/libs/ezsat/ezsat.cc index 20a210abe..fbdfc20f6 100644 --- a/libs/ezsat/ezsat.cc +++ b/libs/ezsat/ezsat.cc @@ -1222,7 +1222,7 @@ ezSATvec ezSAT::vec(const std::vector &vec) return ezSATvec(*this, vec); } -void ezSAT::printDIMACS(FILE *f, bool verbose) const +void ezSAT::printDIMACS(FILE *f, bool verbose, const std::vector> &extraClauses) const { if (cnfConsumed) { fprintf(stderr, "Usage error: printDIMACS() must not be called after cnfConsumed()!"); @@ -1259,8 +1259,10 @@ void ezSAT::printDIMACS(FILE *f, bool verbose) const std::vector> all_clauses; getFullCnf(all_clauses); assert(cnfClausesCount == int(all_clauses.size())); + for (auto c : extraClauses) + all_clauses.push_back(c); - fprintf(f, "p cnf %d %d\n", cnfVariableCount, cnfClausesCount); + fprintf(f, "p cnf %d %d\n", cnfVariableCount, (int) all_clauses.size()); int maxClauseLen = 0; for (auto &clause : all_clauses) maxClauseLen = std::max(int(clause.size()), maxClauseLen); diff --git a/libs/ezsat/ezsat.h b/libs/ezsat/ezsat.h index 7f3bdf68d..507708cb2 100644 --- a/libs/ezsat/ezsat.h +++ b/libs/ezsat/ezsat.h @@ -295,7 +295,7 @@ public: // printing CNF and internal state - void printDIMACS(FILE *f, bool verbose = false) const; + void printDIMACS(FILE *f, bool verbose = false, const std::vector> &extraClauses = std::vector>()) const; void printInternalState(FILE *f) const; // more sophisticated constraints (designed to be used directly with assume(..)) From 6565bf3ebfeba59bd17acce26632bc0ae6858304 Mon Sep 17 00:00:00 2001 From: Gabriel Gouvine Date: Thu, 28 Mar 2024 10:14:30 +0000 Subject: [PATCH 080/291] ezsat: Fix build for emscripten/wasi --- libs/ezsat/ezcommand.cc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/libs/ezsat/ezcommand.cc b/libs/ezsat/ezcommand.cc index c2925b647..2040d3c1a 100644 --- a/libs/ezsat/ezcommand.cc +++ b/libs/ezsat/ezcommand.cc @@ -9,6 +9,7 @@ ezSATCommand::~ezSATCommand() {} bool ezSATCommand::solver(const std::vector &modelExpressions, std::vector &modelValues, const std::vector &assumptions) { +#if !defined(YOSYS_DISABLE_SPAWN) const std::string tempdir_name = Yosys::make_temp_dir(Yosys::get_base_tmpdir() + "/yosys-sat-XXXXXX"); const std::string cnf_filename = Yosys::stringf("%s/problem.cnf", tempdir_name.c_str()); const std::string sat_command = Yosys::stringf("%s %s", command.c_str(), cnf_filename.c_str()); @@ -81,4 +82,7 @@ bool ezSATCommand::solver(const std::vector &modelExpressions, std::vector< modelValues[i] = (values.at(idx - 1) == refvalue); } return true; +#else + Yosys::log_error("SAT solver command not available in this build!\n"); +#endif } \ No newline at end of file From d2b6bd00b1eb73d1d800544fcd16e21050f35a80 Mon Sep 17 00:00:00 2001 From: Gabriel Gouvine Date: Thu, 28 Mar 2024 17:25:19 +0000 Subject: [PATCH 081/291] ezsat: Rename files and class for ezCmdlineSat --- Makefile | 4 ++-- libs/ezsat/{ezcommand.cc => ezcmdline.cc} | 10 +++++----- libs/ezsat/{ezcommand.h => ezcmdline.h} | 6 +++--- 3 files changed, 10 insertions(+), 10 deletions(-) rename libs/ezsat/{ezcommand.cc => ezcmdline.cc} (91%) rename libs/ezsat/{ezcommand.h => ezcmdline.h} (92%) diff --git a/Makefile b/Makefile index afe559712..0fe20288b 100644 --- a/Makefile +++ b/Makefile @@ -638,7 +638,7 @@ $(eval $(call add_include_file,kernel/yosys_common.h)) $(eval $(call add_include_file,kernel/yw.h)) $(eval $(call add_include_file,libs/ezsat/ezsat.h)) $(eval $(call add_include_file,libs/ezsat/ezminisat.h)) -$(eval $(call add_include_file,libs/ezsat/ezcommand.h)) +$(eval $(call add_include_file,libs/ezsat/ezcmdline.h)) ifeq ($(ENABLE_ZLIB),1) $(eval $(call add_include_file,libs/fst/fstapi.h)) endif @@ -684,7 +684,7 @@ OBJS += libs/json11/json11.o OBJS += libs/ezsat/ezsat.o OBJS += libs/ezsat/ezminisat.o -OBJS += libs/ezsat/ezcommand.o +OBJS += libs/ezsat/ezcmdline.o OBJS += libs/minisat/Options.o OBJS += libs/minisat/SimpSolver.o diff --git a/libs/ezsat/ezcommand.cc b/libs/ezsat/ezcmdline.cc similarity index 91% rename from libs/ezsat/ezcommand.cc rename to libs/ezsat/ezcmdline.cc index 2040d3c1a..1b5278fab 100644 --- a/libs/ezsat/ezcommand.cc +++ b/libs/ezsat/ezcmdline.cc @@ -1,13 +1,13 @@ -#include "ezcommand.h" +#include "ezcmdline.h" #include "../../kernel/yosys.h" -ezSATCommand::ezSATCommand(const std::string &cmd) : command(cmd) {} +ezCmdlineSAT::ezCmdlineSAT(const std::string &cmd) : command(cmd) {} -ezSATCommand::~ezSATCommand() {} +ezCmdlineSAT::~ezCmdlineSAT() {} -bool ezSATCommand::solver(const std::vector &modelExpressions, std::vector &modelValues, const std::vector &assumptions) +bool ezCmdlineSAT::solver(const std::vector &modelExpressions, std::vector &modelValues, const std::vector &assumptions) { #if !defined(YOSYS_DISABLE_SPAWN) const std::string tempdir_name = Yosys::make_temp_dir(Yosys::get_base_tmpdir() + "/yosys-sat-XXXXXX"); @@ -85,4 +85,4 @@ bool ezSATCommand::solver(const std::vector &modelExpressions, std::vector< #else Yosys::log_error("SAT solver command not available in this build!\n"); #endif -} \ No newline at end of file +} diff --git a/libs/ezsat/ezcommand.h b/libs/ezsat/ezcmdline.h similarity index 92% rename from libs/ezsat/ezcommand.h rename to libs/ezsat/ezcmdline.h index a0e3de4ed..8ec8c7043 100644 --- a/libs/ezsat/ezcommand.h +++ b/libs/ezsat/ezcmdline.h @@ -22,14 +22,14 @@ #include "ezsat.h" -class ezSATCommand : public ezSAT +class ezCmdlineSAT : public ezSAT { private: std::string command; public: - ezSATCommand(const std::string &cmd); - virtual ~ezSATCommand(); + ezCmdlineSAT(const std::string &cmd); + virtual ~ezCmdlineSAT(); bool solver(const std::vector &modelExpressions, std::vector &modelValues, const std::vector &assumptions) override; }; From 979b673f206bb92e2f76b0c59afe27741b516717 Mon Sep 17 00:00:00 2001 From: Gabriel Gouvine Date: Tue, 9 Apr 2024 15:56:36 +0100 Subject: [PATCH 082/291] ezsat: Fix handling of error codes --- libs/ezsat/ezcmdline.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/libs/ezsat/ezcmdline.cc b/libs/ezsat/ezcmdline.cc index 1b5278fab..dddec1067 100644 --- a/libs/ezsat/ezcmdline.cc +++ b/libs/ezsat/ezcmdline.cc @@ -58,7 +58,8 @@ bool ezCmdlineSAT::solver(const std::vector &modelExpressions, std::vector< } } }; - if (Yosys::run_command(sat_command, line_callback) != 0) { + int return_code = Yosys::run_command(sat_command, line_callback); + if (return_code != 0 && return_code != 10 && return_code != 20) { Yosys::log_cmd_error("Shell command failed!\n"); } From 0f6ef777750e9c537d71b37a1698c08d38add2b7 Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Tue, 20 Jan 2026 09:28:00 -0800 Subject: [PATCH 083/291] Add test for ezCmdlineSAT --- tests/various/.gitignore | 2 + tests/various/ezcmdline_dummy_solver | 61 ++++++++++++++++++++++++++++ tests/various/ezcmdline_plugin.cc | 53 ++++++++++++++++++++++++ tests/various/ezcmdline_plugin.sh | 8 ++++ 4 files changed, 124 insertions(+) create mode 100755 tests/various/ezcmdline_dummy_solver create mode 100644 tests/various/ezcmdline_plugin.cc create mode 100644 tests/various/ezcmdline_plugin.sh diff --git a/tests/various/.gitignore b/tests/various/.gitignore index e116179ae..9296a04c0 100644 --- a/tests/various/.gitignore +++ b/tests/various/.gitignore @@ -4,6 +4,8 @@ /plugin.so /plugin_search /plugin.so.dSYM +/ezcmdline_plugin.so +/ezcmdline_plugin.so.dSYM /temp /smtlib2_module.smt2 /smtlib2_module-filtered.smt2 diff --git a/tests/various/ezcmdline_dummy_solver b/tests/various/ezcmdline_dummy_solver new file mode 100755 index 000000000..db5b21b8e --- /dev/null +++ b/tests/various/ezcmdline_dummy_solver @@ -0,0 +1,61 @@ +#!/bin/sh +# Dummy SAT solver for ezCmdlineSAT tests. +# Accepts exactly two CNF shapes: +# - SAT: p cnf 1 1; clause: "1 0" -> exits 10 with v 1 +# - UNSAT: p cnf 1 2; clauses: "1 0" and "-1 0" -> exits 20 +set -e + +if [ "$#" -ne 1 ]; then + echo "usage: $0 " >&2 + exit 1 +fi + +awk ' +BEGIN { + vars = 0; + clauses = 0; + clause_count = 0; + clause_data = ""; + current = ""; +} +$1 == "c" { + next; +} +$1 == "p" && $2 == "cnf" { + vars = $3; + clauses = $4; + next; +} +{ + for (i = 1; i <= NF; i++) { + lit = $i; + if (lit == 0) { + clause_count++; + if (clause_data != "") + clause_data = clause_data ";" current; + else + clause_data = current; + current = ""; + } else { + if (current == "") + current = lit; + else + current = current "," lit; + } + } +} +END { + if (vars == 1 && clause_count == 1 && clause_data == "1") { + print "s SATISFIABLE"; + print "v 1 0"; + exit 10; + } + if (vars == 1 && clause_count == 2 && clause_data == "1;-1") { + print "s UNSATISFIABLE"; + exit 20; + } + print "c unexpected CNF for dummy solver"; + print "c vars=" vars " header_clauses=" clauses " parsed_clauses=" clause_count " data=" clause_data; + exit 1; +} +' "$1" diff --git a/tests/various/ezcmdline_plugin.cc b/tests/various/ezcmdline_plugin.cc new file mode 100644 index 000000000..b775829b3 --- /dev/null +++ b/tests/various/ezcmdline_plugin.cc @@ -0,0 +1,53 @@ +#include "kernel/yosys.h" +#include "libs/ezsat/ezcmdline.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct EzCmdlineTestPass : public Pass { + EzCmdlineTestPass() : Pass("ezcmdline_test", "smoke-test ezCmdlineSAT") { } + void execute(std::vector args, RTLIL::Design *design) override + { + std::string cmd; + size_t argidx = 1; + + while (argidx < args.size()) { + if (args[argidx] == "-cmd" && argidx + 1 < args.size()) { + cmd = args[argidx + 1]; + argidx += 2; + continue; + } + break; + } + + extra_args(args, argidx, design); + + if (cmd.empty()) + log_error("Missing -cmd argument.\n"); + + ezCmdlineSAT sat(cmd); + sat.non_incremental(); + + // assume("A") adds a permanent CNF clause "A". + sat.assume(sat.VAR("A")); + + std::vector model_expressions; + std::vector model_values; + model_expressions.push_back(sat.VAR("A")); + + // Expect SAT with A=true. + if (!sat.solve(model_expressions, model_values)) + log_error("ezCmdlineSAT SAT case failed.\n"); + if (model_values.size() != 1 || !model_values[0]) + log_error("ezCmdlineSAT SAT model mismatch.\n"); + + // Passing NOT("A") here adds a temporary unit clause for this solve call, + // so the solver sees A && !A and must return UNSAT. + if (sat.solve(model_expressions, model_values, sat.NOT("A"))) + log_error("ezCmdlineSAT UNSAT case failed.\n"); + + log("ezcmdline_test passed!\n"); + } +} EzCmdlineTestPass; + +PRIVATE_NAMESPACE_END diff --git a/tests/various/ezcmdline_plugin.sh b/tests/various/ezcmdline_plugin.sh new file mode 100644 index 000000000..cc1ed4bc9 --- /dev/null +++ b/tests/various/ezcmdline_plugin.sh @@ -0,0 +1,8 @@ +set -e + +DIR=$(cd "$(dirname "$0")" && pwd) +BASEDIR=$(cd "$DIR/../.." && pwd) +rm -f "$DIR/ezcmdline_plugin.so" +chmod +x "$DIR/ezcmdline_dummy_solver" +"$BASEDIR/yosys-config" --build "$DIR/ezcmdline_plugin.so" "$DIR/ezcmdline_plugin.cc" +"$BASEDIR/yosys" -m "$DIR/ezcmdline_plugin.so" -p "ezcmdline_test -cmd $DIR/ezcmdline_dummy_solver" | grep -q "ezcmdline_test passed!" From bd9dbea4eac201c4fee2e93785e357c1b837c5e3 Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Tue, 20 Jan 2026 10:07:44 -0800 Subject: [PATCH 084/291] Add -I --- tests/various/ezcmdline_plugin.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/various/ezcmdline_plugin.sh b/tests/various/ezcmdline_plugin.sh index cc1ed4bc9..58dc7d9c8 100644 --- a/tests/various/ezcmdline_plugin.sh +++ b/tests/various/ezcmdline_plugin.sh @@ -4,5 +4,5 @@ DIR=$(cd "$(dirname "$0")" && pwd) BASEDIR=$(cd "$DIR/../.." && pwd) rm -f "$DIR/ezcmdline_plugin.so" chmod +x "$DIR/ezcmdline_dummy_solver" -"$BASEDIR/yosys-config" --build "$DIR/ezcmdline_plugin.so" "$DIR/ezcmdline_plugin.cc" +"$BASEDIR/yosys-config" --build "$DIR/ezcmdline_plugin.so" "$DIR/ezcmdline_plugin.cc" -I"$BASEDIR" "$BASEDIR/yosys" -m "$DIR/ezcmdline_plugin.so" -p "ezcmdline_test -cmd $DIR/ezcmdline_dummy_solver" | grep -q "ezcmdline_test passed!" From 9ed56ac72c3d391119174a9f9029a5b71caf8e70 Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Tue, 20 Jan 2026 10:44:47 -0800 Subject: [PATCH 085/291] Mimic pattern of how other tests build plugins Seems like using --build isn't supported in CI --- tests/various/ezcmdline_plugin.sh | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/tests/various/ezcmdline_plugin.sh b/tests/various/ezcmdline_plugin.sh index 58dc7d9c8..cad0475a8 100644 --- a/tests/various/ezcmdline_plugin.sh +++ b/tests/various/ezcmdline_plugin.sh @@ -4,5 +4,9 @@ DIR=$(cd "$(dirname "$0")" && pwd) BASEDIR=$(cd "$DIR/../.." && pwd) rm -f "$DIR/ezcmdline_plugin.so" chmod +x "$DIR/ezcmdline_dummy_solver" -"$BASEDIR/yosys-config" --build "$DIR/ezcmdline_plugin.so" "$DIR/ezcmdline_plugin.cc" -I"$BASEDIR" +CXXFLAGS=$("$BASEDIR/yosys-config" --cxxflags) +DATDIR=$("$BASEDIR/yosys-config" --datdir) +DATDIR=${DATDIR//\//\\\/} +CXXFLAGS=${CXXFLAGS//$DATDIR/..\/..\/share} +"$BASEDIR/yosys-config" --exec --cxx ${CXXFLAGS} -I"$BASEDIR" --ldflags -shared -o "$DIR/ezcmdline_plugin.so" "$DIR/ezcmdline_plugin.cc" "$BASEDIR/yosys" -m "$DIR/ezcmdline_plugin.so" -p "ezcmdline_test -cmd $DIR/ezcmdline_dummy_solver" | grep -q "ezcmdline_test passed!" From 57ac113b7f325085e0e9e1f5e992971d94391a5d Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 21 Jan 2026 00:27:51 +0000 Subject: [PATCH 086/291] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 8205bb3ed..5eba3eaad 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.61+39 +YOSYS_VER := 0.61+44 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 2c0448a81b83d24276c9997505dd0a036a3ba459 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Wed, 21 Jan 2026 03:30:17 +0000 Subject: [PATCH 087/291] Avoid spurious copy in `IdStringCollector::trace_named()` --- kernel/rtlil.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 0103cabfb..42d5f56b6 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -186,7 +186,7 @@ struct IdStringCollector { trace(selection_var.selected_modules); trace(selection_var.selected_members); } - void trace_named(const RTLIL::NamedObject named) { + void trace_named(const RTLIL::NamedObject &named) { trace_keys(named.attributes); trace(named.name); } From 2c12545cf39449fd05fded80aa37702b93935ee3 Mon Sep 17 00:00:00 2001 From: nella Date: Wed, 21 Jan 2026 10:08:44 +0100 Subject: [PATCH 088/291] opt_dff restructure. --- passes/opt/opt_dff.cc | 1261 +++++++++++++++++++++-------------------- 1 file changed, 657 insertions(+), 604 deletions(-) diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index 04bcec835..cf68a0e89 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -2,7 +2,6 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Claire Xenia Wolf - * Copyright (C) 2020 Marcelina KoÅ›cielnicka * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -45,34 +44,85 @@ struct OptDffOptions struct OptDffWorker { const OptDffOptions &opt; - Module *module; + + // Cell to port bit index typedef std::pair cell_int_t; - SigMap sigmap; + + SigMap sigmap; // Signal aliasing FfInitVals initvals; - dict bitusers; - dict bit2mux; + dict bitusers; // Signal sink count + dict bit2mux; // Signal bit to driving MUX typedef std::map pattern_t; typedef std::set patterns_t; typedef std::pair ctrl_t; typedef std::set ctrls_t; - // Used as a queue. std::vector dff_cells; - OptDffWorker(const OptDffOptions &opt, Module *mod) : opt(opt), module(mod), sigmap(mod), initvals(&sigmap, mod) { + bool is_active(SigBit sig, bool pol) const { + return sig == (pol ? State::S1 : State::S0); + } + + bool is_inactive(SigBit sig, bool pol) const { + return sig == (pol ? State::S0 : State::S1); + } + + bool is_always_active(SigBit sig, bool pol) const { + return is_active(sig, pol) || (!opt.keepdc && sig == State::Sx); + } + + bool is_always_inactive(SigBit sig, bool pol) const { + return is_inactive(sig, pol) || (!opt.keepdc && sig == State::Sx); + } + + SigSpec create_not(SigSpec a, bool is_fine) { + if (is_fine) + return module->NotGate(NEW_ID, a); + else + return module->Not(NEW_ID, a); + } + + SigSpec create_and(SigSpec a, SigSpec b, bool is_fine) { + if (is_fine) + return module->AndGate(NEW_ID, a, b); + else + return module->And(NEW_ID, a, b); + } + + void create_mux_to_output(SigSpec a, SigSpec b, SigSpec sel, SigSpec y, bool pol, bool is_fine) { + if (is_fine) { + if (pol) + module->addMuxGate(NEW_ID, a, b, sel, y); + else + module->addMuxGate(NEW_ID, b, a, sel, y); + } else { + if (pol) + module->addMux(NEW_ID, a, b, sel, y); + else + module->addMux(NEW_ID, b, a, sel, y); + } + } + + void maybe_simplemap(Cell *c, bool make_gates) { + if (make_gates) { + simplemap(module, c); + module->remove(c); + } + } + + OptDffWorker(const OptDffOptions &opt, Module *mod) + : opt(opt), module(mod), sigmap(mod), initvals(&sigmap, mod) + { // Gathering two kinds of information here for every sigmapped SigBit: - // - // - bitusers: how many users it has (muxes will only be merged into FFs if this is 1, making the FF the only user) + // - bitusers: how many users it has (muxes will only be merged into FFs if the FF is the only user) // - bit2mux: the mux cell and bit index that drives it, if any for (auto wire : module->wires()) - { if (wire->port_output) for (auto bit : sigmap(wire)) bitusers[bit]++; - } for (auto cell : module->cells()) { if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_))) { @@ -83,39 +133,36 @@ struct OptDffWorker for (auto conn : cell->connections()) { bool is_output = cell->output(conn.first); - if (!is_output || !cell->known()) { + if (!is_output || !cell->known()) for (auto bit : sigmap(conn.second)) bitusers[bit]++; - } } if (module->design->selected(module, cell) && cell->is_builtin_ff()) dff_cells.push_back(cell); } - } State combine_const(State a, State b) { - if (a == State::Sx && !opt.keepdc) - return b; - if (b == State::Sx && !opt.keepdc) - return a; - if (a == b) - return a; + // Combine constants: returns Sm if values conflict + if (a == State::Sx && !opt.keepdc) return b; + if (b == State::Sx && !opt.keepdc) return a; + if (a == b) return a; return State::Sm; } patterns_t find_muxtree_feedback_patterns(RTLIL::SigBit d, RTLIL::SigBit q, pattern_t path) { + // Find feedback paths D->Q through mux tree, replacing found paths with Sx patterns_t ret; if (d == q) { ret.insert(path); - return ret; + return ret; // Feedback found } if (bit2mux.count(d) == 0 || bitusers[d] > 1) - return ret; + return ret; // D not driven by MUX / MUX drives multiple loads cell_int_t mbit = bit2mux.at(d); RTLIL::SigSpec sig_a = sigmap(mbit.first->getPort(ID::A)); @@ -123,11 +170,10 @@ struct OptDffWorker RTLIL::SigSpec sig_s = sigmap(mbit.first->getPort(ID::S)); int width = GetSize(sig_a), index = mbit.second; - for (int i = 0; i < GetSize(sig_s); i++) - if (path.count(sig_s[i]) && path.at(sig_s[i])) - { + // Traverse MUX tree + for (int i = 0; i < GetSize(sig_s); i++) { + if (path.count(sig_s[i]) && path.at(sig_s[i])) { ret = find_muxtree_feedback_patterns(sig_b[i*width + index], q, path); - if (sig_b[i*width + index] == q) { RTLIL::SigSpec s = mbit.first->getPort(ID::B); s[i*width + index] = RTLIL::Sx; @@ -136,18 +182,19 @@ struct OptDffWorker return ret; } + } + // Specific path wasn't forced, explore the 0 branch pattern_t path_else = path; - - for (int i = 0; i < GetSize(sig_s); i++) - { + for (int i = 0; i < GetSize(sig_s); i++) { if (path.count(sig_s[i])) continue; pattern_t path_this = path; - path_else[sig_s[i]] = false; - path_this[sig_s[i]] = true; + path_else[sig_s[i]] = false; // Assume S=0 for 'else' path + path_this[sig_s[i]] = true; // Assume S=1 for 'this' path + // Selected when S=1 for (auto &pat : find_muxtree_feedback_patterns(sig_b[i*width + index], q, path_this)) ret.insert(pat); @@ -158,6 +205,7 @@ struct OptDffWorker } } + // Selected when S=0 for (auto &pat : find_muxtree_feedback_patterns(sig_a[index], q, path_else)) ret.insert(pat); @@ -173,22 +221,19 @@ struct OptDffWorker void simplify_patterns(patterns_t& patterns) { auto new_patterns = patterns; + auto find_comp = [](const auto& left, const auto& right) -> std::optional { std::optional ret; - for (const auto &pt: left) - if (right.count(pt.first) == 0) - return {}; - else if (right.at(pt.first) == pt.second) - continue; - else - if (ret) - return {}; - else - ret = pt.first; + for (const auto &pt: left) { + if (right.count(pt.first) == 0) return {}; + if (right.at(pt.first) == pt.second) continue; + if (ret) return {}; + ret = pt.first; + } return ret; }; - // remove complimentary patterns + // Remove complimentary patterns bool optimized; do { optimized = false; @@ -196,7 +241,6 @@ struct OptDffWorker for (auto j = std::next(i, 1); j != patterns.end(); j++) { const auto& left = (GetSize(*j) <= GetSize(*i)) ? *j : *i; auto right = (GetSize(*i) < GetSize(*j)) ? *j : *i; - const auto complimentary_var = find_comp(left, right); if (complimentary_var && new_patterns.count(right)) { @@ -210,13 +254,12 @@ struct OptDffWorker patterns = new_patterns; } while(optimized); - // remove redundant patterns + // Remove redundant patterns for (auto i = patterns.begin(); i != patterns.end(); ++i) { for (auto j = std::next(i, 1); j != patterns.end(); ++j) { const auto& left = (GetSize(*j) <= GetSize(*i)) ? *j : *i; const auto& right = (GetSize(*i) < GetSize(*j)) ? *j : *i; - - bool redundant = true; + bool redundant = true; for (const auto& pt : left) if (right.count(pt.first) == 0 || right.at(pt.first) != pt.second) @@ -225,20 +268,21 @@ struct OptDffWorker new_patterns.erase(right); } } + patterns = std::move(new_patterns); } ctrl_t make_patterns_logic(const patterns_t &patterns, const ctrls_t &ctrls, bool make_gates) { - if (patterns.empty() && GetSize(ctrls) == 1) { + if (patterns.empty() && GetSize(ctrls) == 1) return *ctrls.begin(); - } RTLIL::SigSpec or_input; - for (auto pat : patterns) - { + // Build logic for each feedback pattern + for (auto pat : patterns) { RTLIL::SigSpec s1, s2; + for (auto it : pat) { s1.append(it.first); s2.append(it.second); @@ -246,81 +290,500 @@ struct OptDffWorker RTLIL::SigSpec y = module->addWire(NEW_ID); RTLIL::Cell *c = module->addNe(NEW_ID, s1, s2, y); - - if (make_gates) { - simplemap(module, c); - module->remove(c); - } - + maybe_simplemap(c, make_gates); or_input.append(y); } + + // Add existing control signals for (auto item : ctrls) { if (item.second) or_input.append(item.first); - else if (make_gates) - or_input.append(module->NotGate(NEW_ID, item.first)); else - or_input.append(module->Not(NEW_ID, item.first)); + or_input.append(create_not(item.first, make_gates)); } - if (GetSize(or_input) == 0) - return ctrl_t(State::S1, true); - - if (GetSize(or_input) == 1) - return ctrl_t(or_input, true); + if (GetSize(or_input) == 0) return ctrl_t(State::S1, true); + if (GetSize(or_input) == 1) return ctrl_t(or_input, true); RTLIL::SigSpec y = module->addWire(NEW_ID); RTLIL::Cell *c = module->addReduceAnd(NEW_ID, or_input, y); - - if (make_gates) { - simplemap(module, c); - module->remove(c); - } - + maybe_simplemap(c, make_gates); return ctrl_t(y, true); } ctrl_t combine_resets(const ctrls_t &ctrls, bool make_gates) { - if (GetSize(ctrls) == 1) { + if (GetSize(ctrls) == 1) return *ctrls.begin(); - } - - RTLIL::SigSpec or_input; bool final_pol = false; - for (auto item : ctrls) { + for (auto item : ctrls) if (item.second) final_pol = true; - } + RTLIL::SigSpec or_input; for (auto item : ctrls) { if (item.second == final_pol) or_input.append(item.first); - else if (make_gates) - or_input.append(module->NotGate(NEW_ID, item.first)); else - or_input.append(module->Not(NEW_ID, item.first)); + or_input.append(create_not(item.first, make_gates)); } RTLIL::SigSpec y = module->addWire(NEW_ID); - RTLIL::Cell *c = final_pol ? module->addReduceOr(NEW_ID, or_input, y) : module->addReduceAnd(NEW_ID, or_input, y); - - if (make_gates) { - simplemap(module, c); - module->remove(c); - } - + RTLIL::Cell *c = final_pol + ? module->addReduceOr(NEW_ID, or_input, y) + : module->addReduceAnd(NEW_ID, or_input, y); + maybe_simplemap(c, make_gates); return ctrl_t(y, final_pol); } - bool run() { - // We have all the information we need, and the list of FFs to process as well. Do it. + bool signal_all_same(const SigSpec &sig) { + for (int i = 1; i < GetSize(sig); i++) + if (sig[i] != sig[0]) + return false; + return true; + } + + bool optimize_sr(FfData &ff, Cell *cell, bool &changed) + { + // Removes SR if CLR/SET are always active + // Converts SR to ARST if one pin is never active + // Converts SR to ARST if SET/CLR are inverses of eachother + bool sr_removed = false; + std::vector keep_bits; + + // Check for constant Set/Clear inputs + for (int i = 0; i < ff.width; i++) { + if (is_always_active(ff.sig_clr[i], ff.pol_clr)) { + initvals.remove_init(ff.sig_q[i]); + module->connect(ff.sig_q[i], State::S0); + log("Handling always-active CLR at position %d on %s (%s) from module %s (changing to const driver).\n", + i, log_id(cell), log_id(cell->type), log_id(module)); + sr_removed = true; + } else if (is_always_active(ff.sig_set[i], ff.pol_set)) { + initvals.remove_init(ff.sig_q[i]); + if (!ff.pol_clr) + module->connect(ff.sig_q[i], ff.sig_clr[i]); + else if (ff.is_fine) + module->addNotGate(NEW_ID, ff.sig_clr[i], ff.sig_q[i]); + else + module->addNot(NEW_ID, ff.sig_clr[i], ff.sig_q[i]); + log("Handling always-active SET at position %d on %s (%s) from module %s (changing to combinatorial circuit).\n", + i, log_id(cell), log_id(cell->type), log_id(module)); + sr_removed = true; + } else { + keep_bits.push_back(i); + } + } + + if (sr_removed) { + if (keep_bits.empty()) { + module->remove(cell); + return true; // FF fully removed + } + ff = ff.slice(keep_bits); + ff.cell = cell; + changed = true; + } + + // Try SR -> ARST conversion + bool clr_inactive = ff.pol_clr ? ff.sig_clr.is_fully_zero() : ff.sig_clr.is_fully_ones(); + bool set_inactive = ff.pol_set ? ff.sig_set.is_fully_zero() : ff.sig_set.is_fully_ones(); + + if (clr_inactive && signal_all_same(ff.sig_set)) { + log("Removing never-active CLR on %s (%s) from module %s.\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.has_sr = false; + ff.has_arst = true; + ff.pol_arst = ff.pol_set; + ff.sig_arst = ff.sig_set[0]; + ff.val_arst = Const(State::S1, ff.width); + changed = true; + } else if (set_inactive && signal_all_same(ff.sig_clr)) { + log("Removing never-active SET on %s (%s) from module %s.\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.has_sr = false; + ff.has_arst = true; + ff.pol_arst = ff.pol_clr; + ff.sig_arst = ff.sig_clr[0]; + ff.val_arst = Const(State::S0, ff.width); + changed = true; + } else if (ff.pol_clr == ff.pol_set) { + State val_neutral = ff.pol_set ? State::S0 : State::S1; + SigBit sig_arst = (ff.sig_clr[0] == val_neutral) ? ff.sig_set[0] : ff.sig_clr[0]; + + bool failed = false; + Const::Builder val_arst_builder(ff.width); + for (int i = 0; i < ff.width; i++) { + if (ff.sig_clr[i] == sig_arst && ff.sig_set[i] == val_neutral) + val_arst_builder.push_back(State::S0); + else if (ff.sig_set[i] == sig_arst && ff.sig_clr[i] == val_neutral) + val_arst_builder.push_back(State::S1); + else { + failed = true; + break; + } + } + + if (!failed) { + log("Converting CLR/SET to ARST on %s (%s) from module %s.\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.has_sr = false; + ff.has_arst = true; + ff.val_arst = val_arst_builder.build(); + ff.sig_arst = sig_arst; + ff.pol_arst = ff.pol_clr; + changed = true; + } + } + + return false; + } + + bool optimize_aload(FfData &ff, Cell *cell, bool &changed) + { + // Removes unused Async Load + // Converts constant Async Load to ARST + if (is_always_inactive(ff.sig_aload, ff.pol_aload)) { + log("Removing never-active async load on %s (%s) from module %s.\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.has_aload = false; + changed = true; + return false; + } + + if (is_active(ff.sig_aload, ff.pol_aload)) { + // ALOAD always active + log("Handling always-active async load on %s (%s) from module %s (changing to combinatorial circuit).\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.remove(); + + if (ff.has_sr) { + SigSpec tmp; + if (ff.is_fine) { + tmp = ff.pol_set + ? module->MuxGate(NEW_ID, ff.sig_ad, State::S1, ff.sig_set) + : module->MuxGate(NEW_ID, State::S1, ff.sig_ad, ff.sig_set); + + if (ff.pol_clr) + module->addMuxGate(NEW_ID, tmp, State::S0, ff.sig_clr, ff.sig_q); + else + module->addMuxGate(NEW_ID, State::S0, tmp, ff.sig_clr, ff.sig_q); + } else { + tmp = ff.pol_set + ? module->Or(NEW_ID, ff.sig_ad, ff.sig_set) + : module->Or(NEW_ID, ff.sig_ad, module->Not(NEW_ID, ff.sig_set)); + + if (ff.pol_clr) + module->addAnd(NEW_ID, tmp, module->Not(NEW_ID, ff.sig_clr), ff.sig_q); + else + module->addAnd(NEW_ID, tmp, ff.sig_clr, ff.sig_q); + } + } else if (ff.has_arst) { + create_mux_to_output(ff.sig_ad, ff.val_arst, ff.sig_arst, ff.sig_q, ff.pol_arst, ff.is_fine); + } else { + module->connect(ff.sig_q, ff.sig_ad); + } + return true; + } + + // AD is constant -> ARST + if (ff.sig_ad.is_fully_const() && !ff.has_arst && !ff.has_sr) { + log("Changing const-value async load to async reset on %s (%s) from module %s.\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.has_arst = true; + ff.has_aload = false; + ff.sig_arst = ff.sig_aload; + ff.pol_arst = ff.pol_aload; + ff.val_arst = ff.sig_ad.as_const(); + changed = true; + } + + return false; + } + + bool optimize_arst(FfData &ff, Cell *cell, bool &changed) + { + // Removes ARST if never active or replaces FF if always active + if (is_inactive(ff.sig_arst, ff.pol_arst)) { + log("Removing never-active ARST on %s (%s) from module %s.\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.has_arst = false; + changed = true; + } else if (is_always_active(ff.sig_arst, ff.pol_arst)) { + log("Handling always-active ARST on %s (%s) from module %s (changing to const driver).\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.remove(); + module->connect(ff.sig_q, ff.val_arst); + return true; + } + + return false; + } + + void optimize_srst(FfData &ff, Cell *cell, bool &changed) + { + // Removes SRST if never active or forces D to reset value if always active + if (is_inactive(ff.sig_srst, ff.pol_srst)) { + log("Removing never-active SRST on %s (%s) from module %s.\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.has_srst = false; + changed = true; + } else if (is_always_active(ff.sig_srst, ff.pol_srst)) { + log("Handling always-active SRST on %s (%s) from module %s (changing to const D).\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.has_srst = false; + if (!ff.ce_over_srst) + ff.has_ce = false; + + ff.sig_d = ff.val_srst; + changed = true; + } + } + + void optimize_ce(FfData &ff, Cell *cell, bool &changed) + { + if (is_always_inactive(ff.sig_ce, ff.pol_ce)) { + if (ff.has_srst && !ff.ce_over_srst) { + log("Handling never-active EN on %s (%s) from module %s (connecting SRST instead).\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.pol_ce = ff.pol_srst; + ff.sig_ce = ff.sig_srst; + ff.has_srst = false; + ff.sig_d = ff.val_srst; + changed = true; + } else if (!opt.keepdc || ff.val_init.is_fully_def()) { + log("Handling never-active EN on %s (%s) from module %s (removing D path).\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.has_ce = ff.has_clk = ff.has_srst = false; + changed = true; + } else { + ff.sig_d = ff.sig_q; + ff.has_ce = ff.has_srst = false; + changed = true; + } + } else if (is_active(ff.sig_ce, ff.pol_ce)) { + log("Removing always-active EN on %s (%s) from module %s.\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.has_ce = false; + changed = true; + } + } + + void optimize_const_clk(FfData &ff, Cell *cell, bool &changed) + { + if (!opt.keepdc || ff.val_init.is_fully_def()) { + log("Handling const CLK on %s (%s) from module %s (removing D path).\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.has_ce = ff.has_clk = ff.has_srst = false; + changed = true; + } else if (ff.has_ce || ff.has_srst || ff.sig_d != ff.sig_q) { + ff.sig_d = ff.sig_q; + ff.has_ce = ff.has_srst = false; + changed = true; + } + } + + void optimize_d_equals_q(FfData &ff, Cell *cell, bool &changed) + { + // Detect feedback loops where D is hardwired to Q + if (ff.has_clk && ff.has_srst) { + log("Handling D = Q on %s (%s) from module %s (conecting SRST instead).\n", + log_id(cell), log_id(cell->type), log_id(module)); + if (ff.has_ce && ff.ce_over_srst) { + SigSpec ce = ff.pol_ce ? ff.sig_ce : create_not(ff.sig_ce, ff.is_fine); + SigSpec srst = ff.pol_srst ? ff.sig_srst : create_not(ff.sig_srst, ff.is_fine); + ff.sig_ce = create_and(ce, srst, ff.is_fine); + ff.pol_ce = true; + } else { + ff.pol_ce = ff.pol_srst; + ff.sig_ce = ff.sig_srst; + } + + ff.has_ce = true; + ff.has_srst = false; + ff.sig_d = ff.val_srst; + changed = true; + } else if (!opt.keepdc || ff.val_init.is_fully_def()) { + log("Handling D = Q on %s (%s) from module %s (removing D path).\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.has_gclk = ff.has_clk = ff.has_ce = false; + changed = true; + } + } + + bool try_merge_srst(FfData &ff, Cell *cell, bool &changed) + { + std::map> groups; + std::vector remaining_indices; + Const::Builder val_srst_builder(ff.width); + + for (int i = 0; i < ff.width; i++) { + ctrls_t resets; + State reset_val = ff.has_srst ? ff.val_srst[i] : State::Sx; + + while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) { + cell_int_t mbit = bit2mux.at(ff.sig_d[i]); + if (GetSize(mbit.first->getPort(ID::S)) != 1) + break; + + SigBit s = mbit.first->getPort(ID::S); + SigBit a = mbit.first->getPort(ID::A)[mbit.second]; + SigBit b = mbit.first->getPort(ID::B)[mbit.second]; + + if ((a == State::S0 || a == State::S1) && (b == State::S0 || b == State::S1)) + break; + + bool b_const = (b == State::S0 || b == State::S1); + bool a_const = (a == State::S0 || a == State::S1); + + if (b_const && (b == reset_val || reset_val == State::Sx) && a != ff.sig_q[i]) { + reset_val = b.data; + resets.insert(ctrl_t(s, true)); + ff.sig_d[i] = a; + } else if (a_const && (a == reset_val || reset_val == State::Sx) && b != ff.sig_q[i]) { + reset_val = a.data; + resets.insert(ctrl_t(s, false)); + ff.sig_d[i] = b; + } else { + break; + } + } + + if (!resets.empty()) { + if (ff.has_srst) + resets.insert(ctrl_t(ff.sig_srst, ff.pol_srst)); + + groups[resets].push_back(i); + } else { + remaining_indices.push_back(i); + } + + val_srst_builder.push_back(reset_val); + } + + Const val_srst = val_srst_builder.build(); + + for (auto &it : groups) { + FfData new_ff = ff.slice(it.second); + Const::Builder new_val_srst_builder(new_ff.width); + for (int i = 0; i < new_ff.width; i++) + new_val_srst_builder.push_back(val_srst[it.second[i]]); + + new_ff.val_srst = new_val_srst_builder.build(); + + ctrl_t srst = combine_resets(it.first, ff.is_fine); + new_ff.has_srst = true; + new_ff.sig_srst = srst.first; + new_ff.pol_srst = srst.second; + if (new_ff.has_ce) + new_ff.ce_over_srst = true; + + Cell *new_cell = new_ff.emit(); + if (new_cell) + dff_cells.push_back(new_cell); + + log("Adding SRST signal on %s (%s) from module %s (D = %s, Q = %s, rval = %s).\n", + log_id(cell), log_id(cell->type), log_id(module), + log_signal(new_ff.sig_d), log_signal(new_ff.sig_q), log_signal(new_ff.val_srst)); + } + + if (remaining_indices.empty()) { + module->remove(cell); + return true; + } + + if (GetSize(remaining_indices) != ff.width) { + ff = ff.slice(remaining_indices); + ff.cell = cell; + changed = true; + } + + return false; + } + + bool try_merge_ce(FfData &ff, Cell *cell, bool &changed) + { + std::map, std::vector> groups; + std::vector remaining_indices; + + for (int i = 0; i < ff.width; i++) { + ctrls_t enables; + + while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) { + cell_int_t mbit = bit2mux.at(ff.sig_d[i]); + if (GetSize(mbit.first->getPort(ID::S)) != 1) + break; + + SigBit s = mbit.first->getPort(ID::S); + SigBit a = mbit.first->getPort(ID::A)[mbit.second]; + SigBit b = mbit.first->getPort(ID::B)[mbit.second]; + + if (a == ff.sig_q[i]) { + enables.insert(ctrl_t(s, true)); + ff.sig_d[i] = b; + } else if (b == ff.sig_q[i]) { + enables.insert(ctrl_t(s, false)); + ff.sig_d[i] = a; + } else { + break; + } + } + + patterns_t patterns; + if (!opt.simple_dffe) + patterns = find_muxtree_feedback_patterns(ff.sig_d[i], ff.sig_q[i], pattern_t()); + + if (!patterns.empty() || !enables.empty()) { + if (ff.has_ce) + enables.insert(ctrl_t(ff.sig_ce, ff.pol_ce)); + simplify_patterns(patterns); + groups[std::make_pair(patterns, enables)].push_back(i); + } else { + remaining_indices.push_back(i); + } + } + + for (auto &it : groups) { + FfData new_ff = ff.slice(it.second); + ctrl_t en = make_patterns_logic(it.first.first, it.first.second, ff.is_fine); + + new_ff.has_ce = true; + new_ff.sig_ce = en.first; + new_ff.pol_ce = en.second; + new_ff.ce_over_srst = false; + + Cell *new_cell = new_ff.emit(); + if (new_cell) + dff_cells.push_back(new_cell); + + log("Adding EN signal on %s (%s) from module %s (D = %s, Q = %s).\n", + log_id(cell), log_id(cell->type), log_id(module), + log_signal(new_ff.sig_d), log_signal(new_ff.sig_q)); + } + + if (remaining_indices.empty()) { + module->remove(cell); + return true; + } + + if (GetSize(remaining_indices) != ff.width) { + ff = ff.slice(remaining_indices); + ff.cell = cell; + changed = true; + } + + return false; + } + + bool run() + { bool did_something = false; + while (!dff_cells.empty()) { Cell *cell = dff_cells.back(); dff_cells.pop_back(); - // Break down the FF into pieces. + FfData ff(&initvals, cell); bool changed = false; @@ -330,301 +793,34 @@ struct OptDffWorker continue; } - if (ff.has_sr) { - bool sr_removed = false; - std::vector keep_bits; - // Check for always-active S/R bits. - for (int i = 0; i < ff.width; i++) { - if (ff.sig_clr[i] == (ff.pol_clr ? State::S1 : State::S0) || (!opt.keepdc && ff.sig_clr[i] == State::Sx)) { - // Always-active clear — connect Q bit to 0. - initvals.remove_init(ff.sig_q[i]); - module->connect(ff.sig_q[i], State::S0); - log("Handling always-active CLR at position %d on %s (%s) from module %s (changing to const driver).\n", - i, log_id(cell), log_id(cell->type), log_id(module)); - sr_removed = true; - } else if (ff.sig_set[i] == (ff.pol_set ? State::S1 : State::S0) || (!opt.keepdc && ff.sig_set[i] == State::Sx)) { - // Always-active set — connect Q bit to 1 if clear inactive, 0 if reset active. - initvals.remove_init(ff.sig_q[i]); - if (!ff.pol_clr) { - module->connect(ff.sig_q[i], ff.sig_clr[i]); - } else if (ff.is_fine) { - module->addNotGate(NEW_ID, ff.sig_clr[i], ff.sig_q[i]); - } else { - module->addNot(NEW_ID, ff.sig_clr[i], ff.sig_q[i]); - } - log("Handling always-active SET at position %d on %s (%s) from module %s (changing to combinatorial circuit).\n", - i, log_id(cell), log_id(cell->type), log_id(module)); - sr_removed = true; - } else { - keep_bits.push_back(i); - } - } - if (sr_removed) { - if (keep_bits.empty()) { - module->remove(cell); - did_something = true; - continue; - } - ff = ff.slice(keep_bits); - ff.cell = cell; - changed = true; - } - - if (ff.pol_clr ? ff.sig_clr.is_fully_zero() : ff.sig_clr.is_fully_ones()) { - // CLR is useless, try to kill it. - bool failed = false; - for (int i = 0; i < ff.width; i++) - if (ff.sig_set[i] != ff.sig_set[0]) - failed = true; - if (!failed) { - log("Removing never-active CLR on %s (%s) from module %s.\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.has_sr = false; - ff.has_arst = true; - ff.pol_arst = ff.pol_set; - ff.sig_arst = ff.sig_set[0]; - ff.val_arst = Const(State::S1, ff.width); - changed = true; - } - } else if (ff.pol_set ? ff.sig_set.is_fully_zero() : ff.sig_set.is_fully_ones()) { - // SET is useless, try to kill it. - bool failed = false; - for (int i = 0; i < ff.width; i++) - if (ff.sig_clr[i] != ff.sig_clr[0]) - failed = true; - if (!failed) { - log("Removing never-active SET on %s (%s) from module %s.\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.has_sr = false; - ff.has_arst = true; - ff.pol_arst = ff.pol_clr; - ff.sig_arst = ff.sig_clr[0]; - ff.val_arst = Const(State::S0, ff.width); - changed = true; - } - } else if (ff.pol_clr == ff.pol_set) { - // Try a more complex conversion to plain async reset. - State val_neutral = ff.pol_set ? State::S0 : State::S1; - SigBit sig_arst; - if (ff.sig_clr[0] == val_neutral) - sig_arst = ff.sig_set[0]; - else - sig_arst = ff.sig_clr[0]; - bool failed = false; - Const::Builder val_arst_builder(ff.width); - for (int i = 0; i < ff.width; i++) { - if (ff.sig_clr[i] == sig_arst && ff.sig_set[i] == val_neutral) - val_arst_builder.push_back(State::S0); - else if (ff.sig_set[i] == sig_arst && ff.sig_clr[i] == val_neutral) - val_arst_builder.push_back(State::S1); - else { - failed = true; - break; - } - } - if (!failed) { - log("Converting CLR/SET to ARST on %s (%s) from module %s.\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.has_sr = false; - ff.has_arst = true; - ff.val_arst = val_arst_builder.build(); - ff.sig_arst = sig_arst; - ff.pol_arst = ff.pol_clr; - changed = true; - } - } + // Control signal opt + if (ff.has_sr && optimize_sr(ff, cell, changed)) { + did_something = true; + continue; } - if (ff.has_aload) { - if (ff.sig_aload == (ff.pol_aload ? State::S0 : State::S1) || (!opt.keepdc && ff.sig_aload == State::Sx)) { - // Always-inactive enable — remove. - log("Removing never-active async load on %s (%s) from module %s.\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.has_aload = false; - changed = true; - } else if (ff.sig_aload == (ff.pol_aload ? State::S1 : State::S0)) { - // Always-active enable. Make a comb circuit, nuke the FF/latch. - log("Handling always-active async load on %s (%s) from module %s (changing to combinatorial circuit).\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.remove(); - if (ff.has_sr) { - SigSpec tmp; - if (ff.is_fine) { - if (ff.pol_set) - tmp = module->MuxGate(NEW_ID, ff.sig_ad, State::S1, ff.sig_set); - else - tmp = module->MuxGate(NEW_ID, State::S1, ff.sig_ad, ff.sig_set); - if (ff.pol_clr) - module->addMuxGate(NEW_ID, tmp, State::S0, ff.sig_clr, ff.sig_q); - else - module->addMuxGate(NEW_ID, State::S0, tmp, ff.sig_clr, ff.sig_q); - } else { - if (ff.pol_set) - tmp = module->Or(NEW_ID, ff.sig_ad, ff.sig_set); - else - tmp = module->Or(NEW_ID, ff.sig_ad, module->Not(NEW_ID, ff.sig_set)); - if (ff.pol_clr) - module->addAnd(NEW_ID, tmp, module->Not(NEW_ID, ff.sig_clr), ff.sig_q); - else - module->addAnd(NEW_ID, tmp, ff.sig_clr, ff.sig_q); - } - } else if (ff.has_arst) { - if (ff.is_fine) { - if (ff.pol_arst) - module->addMuxGate(NEW_ID, ff.sig_ad, ff.val_arst[0], ff.sig_arst, ff.sig_q); - else - module->addMuxGate(NEW_ID, ff.val_arst[0], ff.sig_ad, ff.sig_arst, ff.sig_q); - } else { - if (ff.pol_arst) - module->addMux(NEW_ID, ff.sig_ad, ff.val_arst, ff.sig_arst, ff.sig_q); - else - module->addMux(NEW_ID, ff.val_arst, ff.sig_ad, ff.sig_arst, ff.sig_q); - } - } else { - module->connect(ff.sig_q, ff.sig_ad); - } - did_something = true; - continue; - } else if (ff.sig_ad.is_fully_const() && !ff.has_arst && !ff.has_sr) { - log("Changing const-value async load to async reset on %s (%s) from module %s.\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.has_arst = true; - ff.has_aload = false; - ff.sig_arst = ff.sig_aload; - ff.pol_arst = ff.pol_aload; - ff.val_arst = ff.sig_ad.as_const(); - changed = true; - } + if (ff.has_aload && optimize_aload(ff, cell, changed)) { + did_something = true; + continue; } - if (ff.has_arst) { - if (ff.sig_arst == (ff.pol_arst ? State::S0 : State::S1)) { - // Always-inactive reset — remove. - log("Removing never-active ARST on %s (%s) from module %s.\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.has_arst = false; - changed = true; - } else if (ff.sig_arst == (ff.pol_arst ? State::S1 : State::S0) || (!opt.keepdc && ff.sig_arst == State::Sx)) { - // Always-active async reset — change to const driver. - log("Handling always-active ARST on %s (%s) from module %s (changing to const driver).\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.remove(); - module->connect(ff.sig_q, ff.val_arst); - did_something = true; - continue; - } + if (ff.has_arst && optimize_arst(ff, cell, changed)) { + did_something = true; + continue; } - if (ff.has_srst) { - if (ff.sig_srst == (ff.pol_srst ? State::S0 : State::S1)) { - // Always-inactive reset — remove. - log("Removing never-active SRST on %s (%s) from module %s.\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.has_srst = false; - changed = true; - } else if (ff.sig_srst == (ff.pol_srst ? State::S1 : State::S0) || (!opt.keepdc && ff.sig_srst == State::Sx)) { - // Always-active sync reset — connect to D instead. - log("Handling always-active SRST on %s (%s) from module %s (changing to const D).\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.has_srst = false; - if (!ff.ce_over_srst) - ff.has_ce = false; - ff.sig_d = ff.val_srst; - changed = true; - } - } + if (ff.has_srst) + optimize_srst(ff, cell, changed); - if (ff.has_ce) { - if (ff.sig_ce == (ff.pol_ce ? State::S0 : State::S1) || (!opt.keepdc && ff.sig_ce == State::Sx)) { - // Always-inactive enable — remove. - if (ff.has_srst && !ff.ce_over_srst) { - log("Handling never-active EN on %s (%s) from module %s (connecting SRST instead).\n", - log_id(cell), log_id(cell->type), log_id(module)); - // FF with sync reset — connect the sync reset to D instead. - ff.pol_ce = ff.pol_srst; - ff.sig_ce = ff.sig_srst; - ff.has_srst = false; - ff.sig_d = ff.val_srst; - changed = true; - } else if (!opt.keepdc || ff.val_init.is_fully_def()) { - log("Handling never-active EN on %s (%s) from module %s (removing D path).\n", - log_id(cell), log_id(cell->type), log_id(module)); - // The D input path is effectively useless, so remove it (this will be a D latch, SR latch, or a const driver). - ff.has_ce = ff.has_clk = ff.has_srst = false; - changed = true; - } else { - // We need to keep the undefined initival around as such - ff.sig_d = ff.sig_q; - ff.has_ce = ff.has_srst = false; - changed = true; - } - } else if (ff.sig_ce == (ff.pol_ce ? State::S1 : State::S0)) { - // Always-active enable. Just remove it. - // For FF, just remove the useless enable. - log("Removing always-active EN on %s (%s) from module %s.\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.has_ce = false; - changed = true; - } - } + if (ff.has_ce) + optimize_ce(ff, cell, changed); - if (ff.has_clk && ff.sig_clk.is_fully_const()) { - if (!opt.keepdc || ff.val_init.is_fully_def()) { - // Const clock — the D input path is effectively useless, so remove it (this will be a D latch, SR latch, or a const driver). - log("Handling const CLK on %s (%s) from module %s (removing D path).\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.has_ce = ff.has_clk = ff.has_srst = false; - changed = true; - } else { - // Const clock, but we need to keep the undefined initval around as such - if (ff.has_ce || ff.has_srst || ff.sig_d != ff.sig_q) { - ff.sig_d = ff.sig_q; - ff.has_ce = ff.has_srst = false; - changed = true; - } - } - } + if (ff.has_clk && ff.sig_clk.is_fully_const()) + optimize_const_clk(ff, cell, changed); - if ((ff.has_clk || ff.has_gclk) && ff.sig_d == ff.sig_q) { - // Q wrapped back to D, can be removed. - if (ff.has_clk && ff.has_srst) { - // FF with sync reset — connect the sync reset to D instead. - log("Handling D = Q on %s (%s) from module %s (conecting SRST instead).\n", - log_id(cell), log_id(cell->type), log_id(module)); - if (ff.has_ce && ff.ce_over_srst) { - if (!ff.pol_ce) { - if (ff.is_fine) - ff.sig_ce = module->NotGate(NEW_ID, ff.sig_ce); - else - ff.sig_ce = module->Not(NEW_ID, ff.sig_ce); - } - if (!ff.pol_srst) { - if (ff.is_fine) - ff.sig_srst = module->NotGate(NEW_ID, ff.sig_srst); - else - ff.sig_srst = module->Not(NEW_ID, ff.sig_srst); - } - if (ff.is_fine) - ff.sig_ce = module->AndGate(NEW_ID, ff.sig_ce, ff.sig_srst); - else - ff.sig_ce = module->And(NEW_ID, ff.sig_ce, ff.sig_srst); - ff.pol_ce = true; - } else { - ff.pol_ce = ff.pol_srst; - ff.sig_ce = ff.sig_srst; - } - ff.has_ce = true; - ff.has_srst = false; - ff.sig_d = ff.val_srst; - changed = true; - } else if (!opt.keepdc || ff.val_init.is_fully_def()) { - // The D input path is effectively useless, so remove it (this will be a const-input D latch, SR latch, or a const driver). - log("Handling D = Q on %s (%s) from module %s (removing D path).\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.has_gclk = ff.has_clk = ff.has_ce = false; - changed = true; - } - } + // Feedback (D=Q) opt + if ((ff.has_clk || ff.has_gclk) && ff.sig_d == ff.sig_q) + optimize_d_equals_q(ff, cell, changed); if (ff.has_aload && !ff.has_clk && ff.sig_ad == ff.sig_q) { log("Handling AD = Q on %s (%s) from module %s (removing async load path).\n", @@ -633,284 +829,155 @@ struct OptDffWorker changed = true; } - // The cell has been simplified as much as possible already. Now try to spice it up with enables / sync resets. + // Mux merging if (ff.has_clk && ff.sig_d != ff.sig_q) { - if (!ff.has_arst && !ff.has_sr && (!ff.has_srst || !ff.has_ce || ff.ce_over_srst) && !opt.nosdff) { - // Try to merge sync resets. - std::map> groups; - std::vector remaining_indices; - Const::Builder val_srst_builder(ff.width); + bool can_merge_srst = !ff.has_arst && !ff.has_sr && + (!ff.has_srst || !ff.has_ce || ff.ce_over_srst) && !opt.nosdff; - for (int i = 0 ; i < ff.width; i++) { - ctrls_t resets; - State reset_val = State::Sx; - if (ff.has_srst) - reset_val = ff.val_srst[i]; - while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) { - cell_int_t mbit = bit2mux.at(ff.sig_d[i]); - if (GetSize(mbit.first->getPort(ID::S)) != 1) - break; - SigBit s = mbit.first->getPort(ID::S); - SigBit a = mbit.first->getPort(ID::A)[mbit.second]; - SigBit b = mbit.first->getPort(ID::B)[mbit.second]; - // Workaround for funny memory WE pattern. - if ((a == State::S0 || a == State::S1) && (b == State::S0 || b == State::S1)) - break; - if ((b == State::S0 || b == State::S1) && (b == reset_val || reset_val == State::Sx)) { - // This is better handled by CE pattern. - if (a == ff.sig_q[i]) - break; - reset_val = b.data; - resets.insert(ctrl_t(s, true)); - ff.sig_d[i] = a; - } else if ((a == State::S0 || a == State::S1) && (a == reset_val || reset_val == State::Sx)) { - // This is better handled by CE pattern. - if (b == ff.sig_q[i]) - break; - reset_val = a.data; - resets.insert(ctrl_t(s, false)); - ff.sig_d[i] = b; - } else { - break; - } - } - - if (!resets.empty()) { - if (ff.has_srst) - resets.insert(ctrl_t(ff.sig_srst, ff.pol_srst)); - groups[resets].push_back(i); - } else - remaining_indices.push_back(i); - val_srst_builder.push_back(reset_val); - } - Const val_srst = val_srst_builder.build(); - - for (auto &it : groups) { - FfData new_ff = ff.slice(it.second); - Const::Builder new_val_srst_builder(new_ff.width); - for (int i = 0; i < new_ff.width; i++) { - int j = it.second[i]; - new_val_srst_builder.push_back(val_srst[j]); - } - new_ff.val_srst = new_val_srst_builder.build(); - ctrl_t srst = combine_resets(it.first, ff.is_fine); - - new_ff.has_srst = true; - new_ff.sig_srst = srst.first; - new_ff.pol_srst = srst.second; - if (new_ff.has_ce) - new_ff.ce_over_srst = true; - Cell *new_cell = new_ff.emit(); - if (new_cell) - dff_cells.push_back(new_cell); - log("Adding SRST signal on %s (%s) from module %s (D = %s, Q = %s, rval = %s).\n", - log_id(cell), log_id(cell->type), log_id(module), log_signal(new_ff.sig_d), log_signal(new_ff.sig_q), log_signal(new_ff.val_srst)); - } - - if (remaining_indices.empty()) { - module->remove(cell); - did_something = true; - continue; - } else if (GetSize(remaining_indices) != ff.width) { - ff = ff.slice(remaining_indices); - ff.cell = cell; - changed = true; - } + if (can_merge_srst && try_merge_srst(ff, cell, changed)) { + did_something = true; + continue; } - if ((!ff.has_srst || !ff.has_ce || !ff.ce_over_srst) && !opt.nodffe) { - // Try to merge enables. - std::map, std::vector> groups; - std::vector remaining_indices; - for (int i = 0 ; i < ff.width; i++) { - // First, eat up as many simple muxes as possible. - ctrls_t enables; - while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) { - cell_int_t mbit = bit2mux.at(ff.sig_d[i]); - if (GetSize(mbit.first->getPort(ID::S)) != 1) - break; - SigBit s = mbit.first->getPort(ID::S); - SigBit a = mbit.first->getPort(ID::A)[mbit.second]; - SigBit b = mbit.first->getPort(ID::B)[mbit.second]; - if (a == ff.sig_q[i]) { - enables.insert(ctrl_t(s, true)); - ff.sig_d[i] = b; - } else if (b == ff.sig_q[i]) { - enables.insert(ctrl_t(s, false)); - ff.sig_d[i] = a; - } else { - break; - } - } + bool can_merge_ce = (!ff.has_srst || !ff.has_ce || !ff.ce_over_srst) && !opt.nodffe; - patterns_t patterns; - if (!opt.simple_dffe) - patterns = find_muxtree_feedback_patterns(ff.sig_d[i], ff.sig_q[i], pattern_t()); - if (!patterns.empty() || !enables.empty()) { - if (ff.has_ce) - enables.insert(ctrl_t(ff.sig_ce, ff.pol_ce)); - simplify_patterns(patterns); - groups[std::make_pair(patterns, enables)].push_back(i); - } else - remaining_indices.push_back(i); - } - - for (auto &it : groups) { - FfData new_ff = ff.slice(it.second); - ctrl_t en = make_patterns_logic(it.first.first, it.first.second, ff.is_fine); - - new_ff.has_ce = true; - new_ff.sig_ce = en.first; - new_ff.pol_ce = en.second; - new_ff.ce_over_srst = false; - Cell *new_cell = new_ff.emit(); - if (new_cell) - dff_cells.push_back(new_cell); - log("Adding EN signal on %s (%s) from module %s (D = %s, Q = %s).\n", - log_id(cell), log_id(cell->type), log_id(module), log_signal(new_ff.sig_d), log_signal(new_ff.sig_q)); - } - - if (remaining_indices.empty()) { - module->remove(cell); - did_something = true; - continue; - } else if (GetSize(remaining_indices) != ff.width) { - ff = ff.slice(remaining_indices); - ff.cell = cell; - changed = true; - } + if (can_merge_ce && try_merge_ce(ff, cell, changed)) { + did_something = true; + continue; } } if (changed) { - // Rebuild the FF. ff.emit(); did_something = true; } } + return did_something; } - bool run_constbits() { + bool prove_const_with_sat(QuickConeSat &qcsat, ModWalker &modwalker, SigBit q, SigBit d, State val) + { + if (!modwalker.has_drivers(d)) + return false; + + if (val != State::S0 && val != State::S1) + return false; + + int init_sat_pi = qcsat.importSigBit(val); + int q_sat_pi = qcsat.importSigBit(q); + int d_sat_pi = qcsat.importSigBit(d); + qcsat.prepare(); + + return !qcsat.ez->solve( + qcsat.ez->IFF(q_sat_pi, init_sat_pi), + qcsat.ez->NOT(qcsat.ez->IFF(d_sat_pi, init_sat_pi))); + } + + State check_constbit(FfData &ff, int i) + { + State val = ff.val_init[i]; + if (ff.has_arst) val = combine_const(val, ff.val_arst[i]); + if (ff.has_srst) val = combine_const(val, ff.val_srst[i]); + if (ff.has_sr) { + if (ff.sig_clr[i] != (ff.pol_clr ? State::S0 : State::S1)) + val = combine_const(val, State::S0); + if (ff.sig_set[i] != (ff.pol_set ? State::S0 : State::S1)) + val = combine_const(val, State::S1); + } + + return val; + } + + bool run_constbits() + { ModWalker modwalker(module->design, module); QuickConeSat qcsat(modwalker); - // Defer mutating cells by removing them/emiting new flip flops so that - // cell references in modwalker are not invalidated std::vector cells_to_remove; std::vector ffs_to_emit; - bool did_something = false; + for (auto cell : module->selected_cells()) { if (!cell->is_builtin_ff()) continue; - FfData ff(&initvals, cell); - // Now check if any bit can be replaced by a constant. + FfData ff(&initvals, cell); pool removed_sigbits; + for (int i = 0; i < ff.width; i++) { - State val = ff.val_init[i]; - if (ff.has_arst) - val = combine_const(val, ff.val_arst[i]); - if (ff.has_srst) - val = combine_const(val, ff.val_srst[i]); - if (ff.has_sr) { - if (ff.sig_clr[i] != (ff.pol_clr ? State::S0 : State::S1)) - val = combine_const(val, State::S0); - if (ff.sig_set[i] != (ff.pol_set ? State::S0 : State::S1)) - val = combine_const(val, State::S1); - } + State val = check_constbit(ff, i); if (val == State::Sm) continue; + + // Check Synchronous input D if (ff.has_clk || ff.has_gclk) { if (!ff.sig_d[i].wire) { + // D is already a constant val = combine_const(val, ff.sig_d[i].data); - if (val == State::Sm) + if (val == State::Sm) continue; + } else if (opt.sat) { + // Try SAT proof for non-constant D wires + if (!prove_const_with_sat(qcsat, modwalker, ff.sig_q[i], ff.sig_d[i], val)) continue; } else { - if (!opt.sat) - continue; - // For each register bit, try to prove that it cannot change from the initial value. If so, remove it - if (!modwalker.has_drivers(ff.sig_d.extract(i))) - continue; - if (val != State::S0 && val != State::S1) - continue; - - int init_sat_pi = qcsat.importSigBit(val); - int q_sat_pi = qcsat.importSigBit(ff.sig_q[i]); - int d_sat_pi = qcsat.importSigBit(ff.sig_d[i]); - - qcsat.prepare(); - - // Try to find out whether the register bit can change under some circumstances - bool counter_example_found = qcsat.ez->solve(qcsat.ez->IFF(q_sat_pi, init_sat_pi), qcsat.ez->NOT(qcsat.ez->IFF(d_sat_pi, init_sat_pi))); - - // If the register bit cannot change, we can replace it with a constant - if (counter_example_found) - continue; + continue; } } + + // Check Async Load input AD if (ff.has_aload) { if (!ff.sig_ad[i].wire) { val = combine_const(val, ff.sig_ad[i].data); - if (val == State::Sm) + if (val == State::Sm) continue; + } else if (opt.sat) { + if (!prove_const_with_sat(qcsat, modwalker, ff.sig_q[i], ff.sig_ad[i], val)) continue; } else { - if (!opt.sat) - continue; - // For each register bit, try to prove that it cannot change from the initial value. If so, remove it - if (!modwalker.has_drivers(ff.sig_ad.extract(i))) - continue; - if (val != State::S0 && val != State::S1) - continue; - - int init_sat_pi = qcsat.importSigBit(val); - int q_sat_pi = qcsat.importSigBit(ff.sig_q[i]); - int d_sat_pi = qcsat.importSigBit(ff.sig_ad[i]); - - qcsat.prepare(); - - // Try to find out whether the register bit can change under some circumstances - bool counter_example_found = qcsat.ez->solve(qcsat.ez->IFF(q_sat_pi, init_sat_pi), qcsat.ez->NOT(qcsat.ez->IFF(d_sat_pi, init_sat_pi))); - - // If the register bit cannot change, we can replace it with a constant - if (counter_example_found) - continue; + continue; } } - log("Setting constant %d-bit at position %d on %s (%s) from module %s.\n", val ? 1 : 0, - i, log_id(cell), log_id(cell->type), log_id(module)); + log("Setting constant %d-bit at position %d on %s (%s) from module %s.\n", + val ? 1 : 0, i, log_id(cell), log_id(cell->type), log_id(module)); + + // Replace the Q output with the constant value initvals.remove_init(ff.sig_q[i]); module->connect(ff.sig_q[i], val); removed_sigbits.insert(i); } + + // Reconstruct FF with constant bits removed if (!removed_sigbits.empty()) { std::vector keep_bits; for (int i = 0; i < ff.width; i++) if (!removed_sigbits.count(i)) keep_bits.push_back(i); + if (keep_bits.empty()) { - cells_to_remove.emplace_back(cell); - did_something = true; - continue; + cells_to_remove.push_back(cell); + } else { + ff = ff.slice(keep_bits); + ff.cell = cell; + ffs_to_emit.push_back(ff); } - ff = ff.slice(keep_bits); - ff.cell = cell; - ffs_to_emit.emplace_back(ff); did_something = true; } } + for (auto* cell : cells_to_remove) module->remove(cell); + for (auto& ff : ffs_to_emit) ff.emit(); + return did_something; } }; struct OptDffPass : public Pass { OptDffPass() : Pass("opt_dff", "perform DFF optimizations") { } + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -948,6 +1015,7 @@ struct OptDffPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing OPT_DFF pass (perform DFF optimizations).\n"); + OptDffOptions opt; opt.nodffe = false; opt.nosdff = false; @@ -957,26 +1025,11 @@ struct OptDffPass : public Pass { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-nodffe") { - opt.nodffe = true; - continue; - } - if (args[argidx] == "-nosdff") { - opt.nosdff = true; - continue; - } - if (args[argidx] == "-simple-dffe") { - opt.simple_dffe = true; - continue; - } - if (args[argidx] == "-keepdc") { - opt.keepdc = true; - continue; - } - if (args[argidx] == "-sat") { - opt.sat = true; - continue; - } + if (args[argidx] == "-nodffe") { opt.nodffe = true; continue; } + if (args[argidx] == "-nosdff") { opt.nosdff = true; continue; } + if (args[argidx] == "-simple-dffe") { opt.simple_dffe = true; continue; } + if (args[argidx] == "-keepdc") { opt.keepdc = true; continue; } + if (args[argidx] == "-sat") { opt.sat = true; continue; } break; } extra_args(args, argidx, design); From f6eba53d1fb7c33e1f69412069b45f78a2b160ae Mon Sep 17 00:00:00 2001 From: nella Date: Wed, 21 Jan 2026 14:52:19 +0100 Subject: [PATCH 089/291] Fix copyright header. --- passes/opt/opt_dff.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index cf68a0e89..f11326a05 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -2,6 +2,7 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Claire Xenia Wolf + * Copyright (C) 2020 Marcelina KoÅ›cielnicka * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above From a6fc6955227cd69d0c509ec6d62906209022ee3d Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Thu, 22 Jan 2026 00:28:34 +0000 Subject: [PATCH 090/291] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 5eba3eaad..6fe4cb69d 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.61+44 +YOSYS_VER := 0.61+56 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From e87bb659569e0a2626c959adc645f649abb3fc21 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 22 Jan 2026 04:09:16 +0000 Subject: [PATCH 091/291] Move `Design::sort()` calls out of `opt` and `opt_clean` passes into the synth passes that need them. --- docs/source/code_examples/macro_commands/prep.ys | 1 + passes/opt/opt.cc | 1 - passes/opt/opt_clean.cc | 2 -- techlibs/common/prep.cc | 1 + techlibs/gowin/synth_gowin.cc | 1 + techlibs/xilinx/synth_xilinx.cc | 2 ++ 6 files changed, 5 insertions(+), 3 deletions(-) diff --git a/docs/source/code_examples/macro_commands/prep.ys b/docs/source/code_examples/macro_commands/prep.ys index 1bec907f6..7ec7c7af8 100644 --- a/docs/source/code_examples/macro_commands/prep.ys +++ b/docs/source/code_examples/macro_commands/prep.ys @@ -17,6 +17,7 @@ coarse: opt_clean memory_collect opt -noff -keepdc -fast + sort check: stat diff --git a/passes/opt/opt.cc b/passes/opt/opt.cc index ec5760cd9..983437e64 100644 --- a/passes/opt/opt.cc +++ b/passes/opt/opt.cc @@ -193,7 +193,6 @@ struct OptPass : public Pass { } design->optimize(); - design->sort(); design->check(); log_header(design, "Finished fast OPT passes.%s\n", fast_mode ? "" : " (There is nothing left to do.)"); diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 3892c7581..b91577b53 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -715,7 +715,6 @@ struct OptCleanPass : public Pass { log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires); design->optimize(); - design->sort(); design->check(); keep_cache.reset(); @@ -780,7 +779,6 @@ struct CleanPass : public Pass { log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires); design->optimize(); - design->sort(); design->check(); keep_cache.reset(); diff --git a/techlibs/common/prep.cc b/techlibs/common/prep.cc index a98619abd..6798f2a5d 100644 --- a/techlibs/common/prep.cc +++ b/techlibs/common/prep.cc @@ -211,6 +211,7 @@ struct PrepPass : public ScriptPass run("memory_collect"); } run(nokeepdc ? "opt -noff -fast" : "opt -noff -keepdc -fast"); + run("sort"); } if (check_label("check")) diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index b9902659c..36d827b7c 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -311,6 +311,7 @@ struct SynthGowinPass : public ScriptPass if (check_label("map_luts")) { + run("sort"); if (nowidelut && abc9) { run("read_verilog -icells -lib -specify +/abc9_model.v"); run("abc9 -maxlut 4 -W 500"); diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 46b30573c..c487206db 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -386,6 +386,8 @@ struct SynthXilinxPass : public ScriptPass run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')"); run("clean", " (skip if '-nosrl' and '-widemux=0')"); } + + run("sort"); } if (check_label("map_dsp", "(skip if '-nodsp')")) { From dcd7742d5220a2997eff9c80d699fd44ca2d2305 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Wed, 21 Jan 2026 04:02:02 +0000 Subject: [PATCH 092/291] Avoid scanning entire module if there are no wires to remove It's pretty common for `opt_clean` to find no wires to remove. In that case, there is no point scanning the entire design, which can be significantly expensive for huge designs. --- kernel/rtlil.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 42d5f56b6..eef1c319d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2990,6 +2990,8 @@ void RTLIL::Module::add(RTLIL::Binding *binding) void RTLIL::Module::remove(const pool &wires) { log_assert(refcount_wires_ == 0); + if (wires.empty()) + return; struct DeleteWireWorker { From 4f53612725ad1fe4b4d125fe53c85dedc05e1482 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Wed, 21 Jan 2026 03:18:12 +0000 Subject: [PATCH 093/291] Add `linux_perf` command to turn Linux perf recording on and off. This is extremely useful for profiling specific passes. --- passes/cmds/Makefile.inc | 1 + passes/cmds/linux_perf.cc | 96 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 97 insertions(+) create mode 100644 passes/cmds/linux_perf.cc diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index dc12c92c2..5e2994a53 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -37,6 +37,7 @@ OBJS += passes/cmds/chformal.o OBJS += passes/cmds/chtype.o OBJS += passes/cmds/blackbox.o OBJS += passes/cmds/ltp.o +OBJS += passes/cmds/linux_perf.o ifeq ($(DISABLE_SPAWN),0) OBJS += passes/cmds/bugpoint.o endif diff --git a/passes/cmds/linux_perf.cc b/passes/cmds/linux_perf.cc new file mode 100644 index 000000000..f57a887fb --- /dev/null +++ b/passes/cmds/linux_perf.cc @@ -0,0 +1,96 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2014 Claire Xenia Wolf + * Copyright (C) 2014 Johann Glaser + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/log_help.h" + +#include +#include + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +#ifdef __linux__ +struct LinuxPerf : public Pass { + LinuxPerf() : Pass("linux_perf", "turn linux perf recording off or on") { } + void help() override + { + log("This pass turns Linux 'perf' profiling on or off, when it has been configured to use control FIFOs.\n"); + log("\n"); + log("Example shell command line:\n"); + log("mkfifo /tmp/perf.fifo /tmp/perf-ack.fifo\n"); + log("YOSYS_PERF_CTL=/tmp/perf.fifo YOSYS_PERF_ACK=/tmp/perf-ack.fifo \\\n"); + log(" perf record --latency --delay=-1 \\\n"); + log(" --control=fifo:/tmp/perf.fifo,/tmp/perf-ack.fifo --call-graph=dwarf ./yosys -dt -p \\\n"); + log(" \"read_rtlil design.rtlil; linux_perf on; opt_clean; linux_perf off\"\n"); + log("\n"); + log(" linux_perf on\n"); + log("\n"); + log("Start perf recording. YOSYS_PERF_CTL and YOSYS_PERF_ACK must point to Linux perf control FIFOs.\n"); + log("\n"); + log(" linux_perf off\n"); + log("\n"); + log("Stop perf recording.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *) override + { + if (args.size() > 2) + cmd_error(args, 2, "Unexpected argument."); + + std::string_view ctl_msg; + if (args.size() == 2) { + if (args[1] == "on") + ctl_msg = "enable\n"; + else if (args[1] == "off") + ctl_msg = "disable\n"; + else + cmd_error(args, 1, "Unexpected argument."); + } + + const char *ctl_fifo = std::getenv("YOSYS_PERF_CTL"); + if (!ctl_fifo) + log_error("YOSYS_PERF_CTL environment variable not set."); + const char *ack_fifo = std::getenv("YOSYS_PERF_ACK"); + if (!ack_fifo) + log_error("YOSYS_PERF_ACK environment variable not set."); + + int ctl_fd = open(ctl_fifo, O_WRONLY); + if (ctl_fd < 0) + log_error("Failed to open YOSYS_PERF_CTL."); + int ack_fd = open(ack_fifo, O_RDONLY); + if (ack_fd < 0) + log_error("Failed to open YOSYS_PERF_ACK."); + int result = write(ctl_fd, ctl_msg.data(), ctl_msg.size()); + if (result != static_cast(ctl_msg.size())) + log_error("Failed to write to YOSYS_PERF_CTL."); + char buffer[64]; + result = read(ack_fd, buffer, sizeof(buffer)); + close(ctl_fd); + close(ack_fd); + if (result <= 0) + log_error("Failed to read from YOSYS_PERF_ACK."); + if (strcmp(buffer, "ack\n") != 0) + log_error("YOSYS_PERF_ACK did not return 'ack'."); + } +} LinuxPerf; +#endif + +PRIVATE_NAMESPACE_END From 0e4282d442e8395d724ef13c185ff4c1226b6673 Mon Sep 17 00:00:00 2001 From: nella Date: Fri, 23 Jan 2026 09:17:14 +0100 Subject: [PATCH 094/291] Add more opt_dff documentation. --- passes/opt/opt_dff.cc | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index f11326a05..c78145549 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -55,10 +55,11 @@ struct OptDffWorker dict bitusers; // Signal sink count dict bit2mux; // Signal bit to driving MUX - typedef std::map pattern_t; - typedef std::set patterns_t; - typedef std::pair ctrl_t; - typedef std::set ctrls_t; + // Eattern matching for clock enable + typedef std::map pattern_t; // Control signal -> required vals + typedef std::set patterns_t; // Alternative patterns (OR) + typedef std::pair ctrl_t; // Control signal + typedef std::set ctrls_t; // Control signals (AND) std::vector dff_cells; @@ -794,7 +795,7 @@ struct OptDffWorker continue; } - // Control signal opt + // Async control signal opt if (ff.has_sr && optimize_sr(ff, cell, changed)) { did_something = true; continue; @@ -810,6 +811,7 @@ struct OptDffWorker continue; } + // Sync control signal opt if (ff.has_srst) optimize_srst(ff, cell, changed); @@ -859,9 +861,9 @@ struct OptDffWorker bool prove_const_with_sat(QuickConeSat &qcsat, ModWalker &modwalker, SigBit q, SigBit d, State val) { + // Trivial non-const cases if (!modwalker.has_drivers(d)) return false; - if (val != State::S0 && val != State::S1) return false; @@ -870,6 +872,7 @@ struct OptDffWorker int d_sat_pi = qcsat.importSigBit(d); qcsat.prepare(); + // If no counterexample exists, FF is constant return !qcsat.ez->solve( qcsat.ez->IFF(q_sat_pi, init_sat_pi), qcsat.ez->NOT(qcsat.ez->IFF(d_sat_pi, init_sat_pi))); @@ -892,6 +895,7 @@ struct OptDffWorker bool run_constbits() { + // Find FFs that are provably constant ModWalker modwalker(module->design, module); QuickConeSat qcsat(modwalker); From 2468b391bfb146005569941835079e496fd32c3b Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Sat, 24 Jan 2026 01:48:15 +0000 Subject: [PATCH 095/291] Make `compare_signals` produce a total order. Currently when `s1` and `s2` are different bits of the same wire, it is possible for both `compare_signals(s1, s2)` and `compare_signals(s2, s1)` to return false. This means the calling code will call `assign_map.add()` for both `s1` and `s2`, which doesn't make much sense --- one of `s1` or `s2` should be consistently preferred. So fix that by preferring the `SigBit` with the smaller bit offset. --- passes/opt/opt_clean.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 3892c7581..661871d87 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -271,6 +271,9 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s, SigPoo return conns.check_any(s2); } + if (w1 == w2) + return s2.offset < s1.offset; + if (w1->port_output != w2->port_output) return w2->port_output; From 7d53d64a47b13e26105348961876c179a285a201 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Sat, 24 Jan 2026 01:51:34 +0000 Subject: [PATCH 096/291] Make the call to `compare_signals()` easier to read. The negation here is confusing. The intent of the code is "if `s1` is preferred over `s2` as the canonical `SigBit` for this signal, make `s1` the canonical `SigBit` in `assign_map`", so write the code that way instead of "if `s2` is not preferred over `s1` ...". This doesn't change any behavior now that `compare_signals()` is a total order, i.e. `s1` is preferred over `s2`, `s2` is preferred over `s1`, or `s1` and `s2` are equal. Now, when `s1` and `s2` are equal, we don't call `assign_map.add(s1)`, but that's already a noop in that case. --- passes/opt/opt_clean.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 661871d87..ccdcbf7f9 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -346,7 +346,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos RTLIL::Wire *wire = it.second; for (int i = 0; i < wire->width; i++) { RTLIL::SigBit s1 = RTLIL::SigBit(wire, i), s2 = assign_map(s1); - if (!compare_signals(s1, s2, register_signals, connected_signals, direct_wires)) + if (compare_signals(s2, s1, register_signals, connected_signals, direct_wires)) assign_map.add(s1); } } From 32e96605d468b632d3c51a0286b199a3ed5043a4 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Mon, 19 Jan 2026 02:44:54 +0000 Subject: [PATCH 097/291] Don't update `used_signals` for retained wires in `rmunused_module_signals`. These updates should not be necessary. In fact, if they were necessary, this code would be buggy, because the results would depend on the order in which wires are traversed: If wire A is retained, which causes an update to `used_signals`, which then causes wire B to be retained when it otherwise wouldn't be, then we would get different results depending on whether A is visited before B. These updates will also make it difficult to process these wires in parallel. --- passes/opt/opt_clean.cc | 2 -- tests/opt/opt_clean_standalone_wires.ys | 10 ++++++++++ 2 files changed, 10 insertions(+), 2 deletions(-) create mode 100644 tests/opt/opt_clean_standalone_wires.ys diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 3892c7581..76f425099 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -467,8 +467,6 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos wire->attributes.erase(ID::init); else wire->attributes.at(ID::init) = initval; - used_signals.add(new_conn.first); - used_signals.add(new_conn.second); module->connect(new_conn); } diff --git a/tests/opt/opt_clean_standalone_wires.ys b/tests/opt/opt_clean_standalone_wires.ys new file mode 100644 index 000000000..d6716d725 --- /dev/null +++ b/tests/opt/opt_clean_standalone_wires.ys @@ -0,0 +1,10 @@ +read_rtlil << EOT +module \test + wire \wire_a + wire \wire_f + connect \wire_f \wire_a +end +EOT + +opt_clean +select -assert-count 0 */* From f3c87610f51a20feecac94a37535f374fcfcbdca Mon Sep 17 00:00:00 2001 From: nataliakokoromyti Date: Sat, 24 Jan 2026 23:46:45 -0800 Subject: [PATCH 098/291] verific: allow mixed SV/VHDL in -f files --- frontends/verific/verific.cc | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 92df86fd5..67e70d5e7 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3744,10 +3744,28 @@ struct VerificPass : public Pass { veri_file::DefineMacro("VERIFIC"); veri_file::DefineMacro(is_formal ? "FORMAL" : "SYNTHESIS"); +#ifdef VERIFIC_VHDL_SUPPORT + int i; + FOREACH_ARRAY_ITEM(file_names, i, filename) { + std::string filename_str = filename; + if ((filename_str.substr(filename_str.find_last_of(".") + 1) == "vhd") || + (filename_str.substr(filename_str.find_last_of(".") + 1) == "vhdl")) { + vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2019").c_str()); + if (!vhdl_file::Analyze(filename, work.c_str(), vhdl_file::VHDL_2019)) { + verific_error_msg.clear(); + log_cmd_error("Reading VHDL sources failed.\n"); + } + } else if (!veri_file::Analyze(filename, analysis_mode, work.c_str())) { + verific_error_msg.clear(); + log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); + } + } +#else if (!veri_file::AnalyzeMultipleFiles(file_names, analysis_mode, work.c_str(), veri_file::MFCU)) { verific_error_msg.clear(); log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); } +#endif delete file_names; verific_import_pending = true; From 808ec8c04b37e0e6c73b8873d4051c19dc41fa25 Mon Sep 17 00:00:00 2001 From: Maxim Kudinov Date: Sun, 25 Jan 2026 22:10:08 +0300 Subject: [PATCH 099/291] gowin: synth_gowin: Add MULT inference for GW1N and GW2A --- techlibs/gowin/Makefile.inc | 1 + techlibs/gowin/dsp_map.v | 70 +++++++++++++++++++++++++++++++++++ techlibs/gowin/synth_gowin.cc | 44 +++++++++++++++++++++- 3 files changed, 114 insertions(+), 1 deletion(-) create mode 100644 techlibs/gowin/dsp_map.v diff --git a/techlibs/gowin/Makefile.inc b/techlibs/gowin/Makefile.inc index df1b79317..0744b1389 100644 --- a/techlibs/gowin/Makefile.inc +++ b/techlibs/gowin/Makefile.inc @@ -12,3 +12,4 @@ $(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_map_gw5a.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/brams.txt)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams_map.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams.txt)) +$(eval $(call add_share_file,share/gowin,techlibs/gowin/dsp_map.v)) diff --git a/techlibs/gowin/dsp_map.v b/techlibs/gowin/dsp_map.v new file mode 100644 index 000000000..dfde0b6a1 --- /dev/null +++ b/techlibs/gowin/dsp_map.v @@ -0,0 +1,70 @@ +module \$__MUL9X9 (input [8:0] A, input [8:0] B, output [17:0] Y); + + parameter A_WIDTH = 9; + parameter B_WIDTH = 9; + parameter Y_WIDTH = 18; + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + + MULT9X9 __TECHMAP_REPLACE__ ( + .CLK(1'b0), + .CE(1'b0), + .RESET(1'b0), + .A(A), + .SIA({A_WIDTH{1'b0}}), + .ASEL(1'b0), + .ASIGN(A_SIGNED ? 1'b1 : 1'b0), + .B(B), + .SIB({B_WIDTH{1'b0}}), + .BSEL(1'b0), + .BSIGN(B_SIGNED ? 1'b1 : 1'b0), + .DOUT(Y) + ); + +endmodule + +module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); + + parameter A_WIDTH = 18; + parameter B_WIDTH = 18; + parameter Y_WIDTH = 36; + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + + MULT18X18 __TECHMAP_REPLACE__ ( + .CLK(1'b0), + .CE(1'b0), + .RESET(1'b0), + .A(A), + .SIA({A_WIDTH{1'b0}}), + .ASEL(1'b0), + .ASIGN(A_SIGNED ? 1'b1 : 1'b0), + .B(B), + .SIB({B_WIDTH{1'b0}}), + .BSEL(1'b0), + .BSIGN(B_SIGNED ? 1'b1 : 1'b0), + .DOUT(Y) + ); + +endmodule + +module \$__MUL36X36 (input [35:0] A, input [35:0] B, output [71:0] Y); + + parameter A_WIDTH = 36; + parameter B_WIDTH = 36; + parameter Y_WIDTH = 72; + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + + MULT36X36 __TECHMAP_REPLACE__ ( + .CLK(1'b0), + .RESET(1'b0), + .CE(1'b0), + .A(A), + .ASIGN(A_SIGNED ? 1'b1 : 1'b0), + .B(B), + .BSIGN(B_SIGNED ? 1'b1 : 1'b0), + .DOUT(Y) + ); + +endmodule diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index b9902659c..9cc213945 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -29,6 +29,21 @@ struct SynthGowinPass : public ScriptPass { SynthGowinPass() : ScriptPass("synth_gowin", "synthesis for Gowin FPGAs") { } + struct DSPRule { + int a_maxwidth; + int b_maxwidth; + int a_minwidth; + int b_minwidth; + std::string prim; + }; + + const std::vector dsp_rules = { + {36, 36, 22, 22, "$__MUL36X36"}, + {18, 18, 10, 4, "$__MUL18X18"}, + {18, 18, 4, 10, "$__MUL18X18"}, + {9, 9, 4, 4, "$__MUL9X9"}, + }; + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -249,7 +264,34 @@ struct SynthGowinPass : public ScriptPass if (check_label("coarse")) { - run("synth -run coarse" + no_rw_check_opt); + run("proc"); + run("opt_expr"); + run("opt_clean"); + run("check"); + run("opt -nodffe -nosdff"); + run("fsm"); + run("opt"); + run("wreduce"); + run("peepopt"); + run("opt_clean"); + run("share"); + + if (help_mode) { + run("techmap -map +/mul2dsp.v [...]", "(if -family gw1n or gw2a)"); + run("techmap -map +/gowin/dsp_map.v", "(if -family gw1n or gw2a)"); + } else if (family == "gw1n" || family == "gw2a") { + for (const auto &rule : dsp_rules) { + run(stringf("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=%d -D DSP_B_MAXWIDTH=%d -D DSP_A_MINWIDTH=%d -D DSP_B_MINWIDTH=%d -D DSP_NAME=%s", + rule.a_maxwidth, rule.b_maxwidth, rule.a_minwidth, rule.b_minwidth, rule.prim)); + run("chtype -set $mul t:$__soft_mul"); + } + run("techmap -map +/gowin/dsp_map.v"); + } + + run("alumacc"); + run("opt"); + run("memory -nomap" + no_rw_check_opt); + run("opt_clean"); } if (check_label("map_ram")) From a75e0b2e9283b6947c5e144067da0794aac7ede4 Mon Sep 17 00:00:00 2001 From: nella Date: Mon, 26 Jan 2026 14:24:01 +0100 Subject: [PATCH 100/291] opt_dff minor cleanup, added tests for comp var. --- passes/opt/opt_dff.cc | 20 +- passes/opt/opt_dff_comp.h | 31 +++ .../opt/optDffFindComplementaryPatternTest.cc | 179 ++++++++++++++++++ 3 files changed, 215 insertions(+), 15 deletions(-) create mode 100644 passes/opt/opt_dff_comp.h create mode 100644 tests/unit/opt/optDffFindComplementaryPatternTest.cc diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index c78145549..ad891af90 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -27,6 +27,7 @@ #include "kernel/ffinit.h" #include "kernel/ff.h" #include "passes/techmap/simplemap.h" +#include "passes/opt/opt_dff_comp.h" #include #include @@ -55,7 +56,7 @@ struct OptDffWorker dict bitusers; // Signal sink count dict bit2mux; // Signal bit to driving MUX - // Eattern matching for clock enable + // Pattern matching for clock enable typedef std::map pattern_t; // Control signal -> required vals typedef std::set patterns_t; // Alternative patterns (OR) typedef std::pair ctrl_t; // Control signal @@ -224,17 +225,6 @@ struct OptDffWorker { auto new_patterns = patterns; - auto find_comp = [](const auto& left, const auto& right) -> std::optional { - std::optional ret; - for (const auto &pt: left) { - if (right.count(pt.first) == 0) return {}; - if (right.at(pt.first) == pt.second) continue; - if (ret) return {}; - ret = pt.first; - } - return ret; - }; - // Remove complimentary patterns bool optimized; do { @@ -243,7 +233,7 @@ struct OptDffWorker for (auto j = std::next(i, 1); j != patterns.end(); j++) { const auto& left = (GetSize(*j) <= GetSize(*i)) ? *j : *i; auto right = (GetSize(*i) < GetSize(*j)) ? *j : *i; - const auto complimentary_var = find_comp(left, right); + const auto complimentary_var = find_complementary_pattern_var(left, right); if (complimentary_var && new_patterns.count(right)) { new_patterns.erase(right); @@ -624,7 +614,7 @@ struct OptDffWorker ctrls_t resets; State reset_val = ff.has_srst ? ff.val_srst[i] : State::Sx; - while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) { + if (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) { cell_int_t mbit = bit2mux.at(ff.sig_d[i]); if (GetSize(mbit.first->getPort(ID::S)) != 1) break; @@ -712,7 +702,7 @@ struct OptDffWorker for (int i = 0; i < ff.width; i++) { ctrls_t enables; - while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) { + if (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) { cell_int_t mbit = bit2mux.at(ff.sig_d[i]); if (GetSize(mbit.first->getPort(ID::S)) != 1) break; diff --git a/passes/opt/opt_dff_comp.h b/passes/opt/opt_dff_comp.h new file mode 100644 index 000000000..edad8e6c1 --- /dev/null +++ b/passes/opt/opt_dff_comp.h @@ -0,0 +1,31 @@ +#ifndef OPT_DFF_COMP_H +#define OPT_DFF_COMP_H + +#include "kernel/rtlil.h" +#include +#include + +YOSYS_NAMESPACE_BEGIN + +typedef std::map pattern_t; + +inline std::optional find_complementary_pattern_var( + const pattern_t& left, + const pattern_t& right +) { + std::optional ret; + for (const auto &pt : left) { + if (right.count(pt.first) == 0) + return std::nullopt; + if (right.at(pt.first) == pt.second) + continue; + if (ret) + return std::nullopt; + ret = pt.first; + } + return ret; +} + +YOSYS_NAMESPACE_END + +#endif diff --git a/tests/unit/opt/optDffFindComplementaryPatternTest.cc b/tests/unit/opt/optDffFindComplementaryPatternTest.cc new file mode 100644 index 000000000..38fa4bd2d --- /dev/null +++ b/tests/unit/opt/optDffFindComplementaryPatternTest.cc @@ -0,0 +1,179 @@ +#include +#include "passes/opt/opt_dff_comp.h" + +YOSYS_NAMESPACE_BEGIN + +class FindComplementaryPatternVarTest : public ::testing::Test { +protected: + RTLIL::Design *design; + RTLIL::Module *module; + RTLIL::Wire *wire_a; + RTLIL::Wire *wire_b; + RTLIL::Wire *wire_c; + RTLIL::Wire *bus; + + void SetUp() override { + design = new RTLIL::Design; + module = design->addModule(ID(test_module)); + wire_a = module->addWire(ID(a)); + wire_b = module->addWire(ID(b)); + wire_c = module->addWire(ID(c)); + bus = module->addWire(ID(bus), 4); + } + + void TearDown() override { + delete design; + } + + RTLIL::SigBit bit(RTLIL::Wire *w, int offset = 0) { + return RTLIL::SigBit(w, offset); + } +}; + +TEST_F(FindComplementaryPatternVarTest, EmptyPatterns) { + pattern_t left, right; + + auto result = find_complementary_pattern_var(left, right); + EXPECT_FALSE(result.has_value()); +} + +TEST_F(FindComplementaryPatternVarTest, IdenticalSingleVar) { + pattern_t left, right; + left[bit(wire_a)] = true; + right[bit(wire_a)] = true; + + auto result = find_complementary_pattern_var(left, right); + EXPECT_FALSE(result.has_value()); +} + +TEST_F(FindComplementaryPatternVarTest, ComplementarySingleVar) { + pattern_t left, right; + left[bit(wire_a)] = true; + right[bit(wire_a)] = false; + + auto result = find_complementary_pattern_var(left, right); + ASSERT_TRUE(result.has_value()); + EXPECT_EQ(result.value(), bit(wire_a)); +} + +TEST_F(FindComplementaryPatternVarTest, MissingKeyInRight) { + pattern_t left, right; + left[bit(wire_a)] = true; + left[bit(wire_b)] = false; + right[bit(wire_a)] = true; + + auto result = find_complementary_pattern_var(left, right); + EXPECT_FALSE(result.has_value()); +} + +TEST_F(FindComplementaryPatternVarTest, TwoVarsOneComplementary) { + pattern_t left, right; + left[bit(wire_a)] = true; + left[bit(wire_b)] = false; + right[bit(wire_a)] = true; + right[bit(wire_b)] = true; + + auto result = find_complementary_pattern_var(left, right); + ASSERT_TRUE(result.has_value()); + EXPECT_EQ(result.value(), bit(wire_b)); +} + +TEST_F(FindComplementaryPatternVarTest, TwoVarsBothComplementary) { + pattern_t left, right; + left[bit(wire_a)] = true; + left[bit(wire_b)] = false; + right[bit(wire_a)] = false; + right[bit(wire_b)] = true; + + auto result = find_complementary_pattern_var(left, right); + EXPECT_FALSE(result.has_value()); +} + +TEST_F(FindComplementaryPatternVarTest, LeftSubsetOfRight) { + pattern_t left, right; + left[bit(wire_a)] = true; + left[bit(wire_b)] = false; + right[bit(wire_a)] = true; + right[bit(wire_b)] = true; + right[bit(wire_c)] = false; + + auto result = find_complementary_pattern_var(left, right); + ASSERT_TRUE(result.has_value()); + EXPECT_EQ(result.value(), bit(wire_b)); +} + +TEST_F(FindComplementaryPatternVarTest, ThreeVarsAllSame) { + pattern_t left, right; + left[bit(wire_a)] = true; + left[bit(wire_b)] = false; + left[bit(wire_c)] = true; + right[bit(wire_a)] = true; + right[bit(wire_b)] = false; + right[bit(wire_c)] = true; + + auto result = find_complementary_pattern_var(left, right); + EXPECT_FALSE(result.has_value()); +} + +TEST_F(FindComplementaryPatternVarTest, PracticalPatternSimplification) { + pattern_t pattern1, pattern2; + pattern1[bit(bus, 0)] = true; + pattern1[bit(bus, 1)] = true; + pattern2[bit(bus, 0)] = true; + pattern2[bit(bus, 1)] = false; + + auto result = find_complementary_pattern_var(pattern1, pattern2); + ASSERT_TRUE(result.has_value()); + EXPECT_EQ(result.value(), bit(bus, 1)); + + // Swapped args + auto result2 = find_complementary_pattern_var(pattern2, pattern1); + ASSERT_TRUE(result2.has_value()); + EXPECT_EQ(result2.value(), bit(bus, 1)); +} + +TEST_F(FindComplementaryPatternVarTest, MuxTreeClockEnableDetection) { + pattern_t feedback_path1, feedback_path2; + feedback_path1[bit(wire_a)] = true; + feedback_path1[bit(wire_b)] = true; + feedback_path2[bit(wire_a)] = true; + feedback_path2[bit(wire_b)] = false; + + auto comp = find_complementary_pattern_var(feedback_path1, feedback_path2); + ASSERT_TRUE(comp.has_value()); + EXPECT_EQ(comp.value(), bit(wire_b)); + + pattern_t simplified = feedback_path1; + simplified.erase(comp.value()); + + EXPECT_EQ(simplified.size(), 1); + EXPECT_TRUE(simplified.count(bit(wire_a))); + EXPECT_TRUE(simplified[bit(wire_a)]); +} + +TEST_F(FindComplementaryPatternVarTest, AsymmetricPatterns) { + pattern_t left, right; + left[bit(wire_a)] = true; + right[bit(wire_a)] = false; + right[bit(wire_b)] = true; + right[bit(wire_c)] = false; + + auto result = find_complementary_pattern_var(left, right); + ASSERT_TRUE(result.has_value()); + EXPECT_EQ(result.value(), bit(wire_a)); +} + +TEST_F(FindComplementaryPatternVarTest, WireOffsetDistinction) { + pattern_t left, right; + left[bit(bus, 0)] = true; + left[bit(bus, 1)] = false; + right[bit(bus, 0)] = true; + right[bit(bus, 1)] = true; + right[bit(bus, 2)] = false; + + auto result = find_complementary_pattern_var(left, right); + ASSERT_TRUE(result.has_value()); + EXPECT_EQ(result.value(), bit(bus, 1)); +} + +YOSYS_NAMESPACE_END From 8576055dea187b4dc6ddf6b706dc0bd712c2a034 Mon Sep 17 00:00:00 2001 From: nella Date: Mon, 26 Jan 2026 18:41:41 +0100 Subject: [PATCH 101/291] Fix tests. --- passes/opt/opt_dff.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index ad891af90..31260fd96 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -614,7 +614,7 @@ struct OptDffWorker ctrls_t resets; State reset_val = ff.has_srst ? ff.val_srst[i] : State::Sx; - if (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) { + while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) { cell_int_t mbit = bit2mux.at(ff.sig_d[i]); if (GetSize(mbit.first->getPort(ID::S)) != 1) break; @@ -702,7 +702,7 @@ struct OptDffWorker for (int i = 0; i < ff.width; i++) { ctrls_t enables; - if (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) { + while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) { cell_int_t mbit = bit2mux.at(ff.sig_d[i]); if (GetSize(mbit.first->getPort(ID::S)) != 1) break; From 5803461c24b8d1520cabce66cd9ba7c7994246a7 Mon Sep 17 00:00:00 2001 From: nella Date: Mon, 26 Jan 2026 22:10:10 +0100 Subject: [PATCH 102/291] opt_dff pattern extraction. --- kernel/pattern.h | 98 +++++++++++++++++++++++++++++++++++++++ passes/opt/opt_dff.cc | 48 +------------------ passes/opt/opt_dff_comp.h | 31 ------------- 3 files changed, 100 insertions(+), 77 deletions(-) create mode 100644 kernel/pattern.h delete mode 100644 passes/opt/opt_dff_comp.h diff --git a/kernel/pattern.h b/kernel/pattern.h new file mode 100644 index 000000000..13892ebc5 --- /dev/null +++ b/kernel/pattern.h @@ -0,0 +1,98 @@ +#ifndef OPT_DFF_COMP_H +#define OPT_DFF_COMP_H + +#include "kernel/rtlil.h" +#include +#include + +YOSYS_NAMESPACE_BEGIN + +/** + * Pattern matching utilities for control signal analysis. + * + * A pattern_t maps control signals to required values, representing a + * product term (conjunction): {A=1, B=0} means "A AND !B". + * + * A patterns_t is a set of patterns representing a sum-of-products: + * {{A=1, B=0}, {A=0, C=1}} means "(A AND !B) OR (!A AND C)". + * + * Used for analyzing MUX tree control paths in DFF optimization. + */ + +typedef std::map pattern_t; // Control signal -> required vals +typedef std::set patterns_t; // Alternative patterns (OR) + +/** + * Find if two patterns differ in exactly one variable. + * Example: {A=1,B=1} vs {A=1,B=0} returns B, allows simplification: (A&B) | (A&!B) => A + */ +inline std::optional find_complementary_pattern_var( + const pattern_t& left, + const pattern_t& right +) { + std::optional ret; + for (const auto &pt : left) { + // Left requires signal that right doesn't constrain - incompatible domains + if (right.count(pt.first) == 0) + return std::nullopt; + // Signal has same required value in both - not the complement variable + if (right.at(pt.first) == pt.second) + continue; + // Already found one differing signal, now found another - not simplifiable + if (ret) + return std::nullopt; + // First differing signal - candidate complement variable + ret = pt.first; + } + return ret; +} + +/** + * Simplify a sum-of-products by merging complementary patterns: (A&B) | (A&!B) => A, + * and removing redundant patterns: A | (A&B) => A + */ +inline void simplify_patterns(patterns_t& patterns) { + auto new_patterns = patterns; + + // Merge complementary patterns + bool optimized; + do { + optimized = false; + for (auto i = patterns.begin(); i != patterns.end(); i++) { + for (auto j = std::next(i, 1); j != patterns.end(); j++) { + const auto& left = (GetSize(*j) <= GetSize(*i)) ? *j : *i; + auto right = (GetSize(*i) < GetSize(*j)) ? *j : *i; + const auto complementary_var = find_complementary_pattern_var(left, right); + + if (complementary_var && new_patterns.count(right)) { + new_patterns.erase(right); + right.erase(complementary_var.value()); + new_patterns.insert(right); + optimized = true; + } + } + } + patterns = new_patterns; + } while(optimized); + + // Remove redundant patterns + for (auto i = patterns.begin(); i != patterns.end(); ++i) { + for (auto j = std::next(i, 1); j != patterns.end(); ++j) { + const auto& left = (GetSize(*j) <= GetSize(*i)) ? *j : *i; + const auto& right = (GetSize(*i) < GetSize(*j)) ? *j : *i; + bool redundant = true; + + for (const auto& pt : left) + if (right.count(pt.first) == 0 || right.at(pt.first) != pt.second) + redundant = false; + if (redundant) + new_patterns.erase(right); + } + } + + patterns = std::move(new_patterns); +} + +YOSYS_NAMESPACE_END + +#endif diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index 31260fd96..ff14d367f 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -26,8 +26,8 @@ #include "kernel/sigtools.h" #include "kernel/ffinit.h" #include "kernel/ff.h" +#include "kernel/pattern.h" #include "passes/techmap/simplemap.h" -#include "passes/opt/opt_dff_comp.h" #include #include @@ -57,8 +57,7 @@ struct OptDffWorker dict bit2mux; // Signal bit to driving MUX // Pattern matching for clock enable - typedef std::map pattern_t; // Control signal -> required vals - typedef std::set patterns_t; // Alternative patterns (OR) + typedef std::map pattern_t; typedef std::pair ctrl_t; // Control signal typedef std::set ctrls_t; // Control signals (AND) @@ -221,49 +220,6 @@ struct OptDffWorker return ret; } - void simplify_patterns(patterns_t& patterns) - { - auto new_patterns = patterns; - - // Remove complimentary patterns - bool optimized; - do { - optimized = false; - for (auto i = patterns.begin(); i != patterns.end(); i++) { - for (auto j = std::next(i, 1); j != patterns.end(); j++) { - const auto& left = (GetSize(*j) <= GetSize(*i)) ? *j : *i; - auto right = (GetSize(*i) < GetSize(*j)) ? *j : *i; - const auto complimentary_var = find_complementary_pattern_var(left, right); - - if (complimentary_var && new_patterns.count(right)) { - new_patterns.erase(right); - right.erase(complimentary_var.value()); - new_patterns.insert(right); - optimized = true; - } - } - } - patterns = new_patterns; - } while(optimized); - - // Remove redundant patterns - for (auto i = patterns.begin(); i != patterns.end(); ++i) { - for (auto j = std::next(i, 1); j != patterns.end(); ++j) { - const auto& left = (GetSize(*j) <= GetSize(*i)) ? *j : *i; - const auto& right = (GetSize(*i) < GetSize(*j)) ? *j : *i; - bool redundant = true; - - for (const auto& pt : left) - if (right.count(pt.first) == 0 || right.at(pt.first) != pt.second) - redundant = false; - if (redundant) - new_patterns.erase(right); - } - } - - patterns = std::move(new_patterns); - } - ctrl_t make_patterns_logic(const patterns_t &patterns, const ctrls_t &ctrls, bool make_gates) { if (patterns.empty() && GetSize(ctrls) == 1) diff --git a/passes/opt/opt_dff_comp.h b/passes/opt/opt_dff_comp.h deleted file mode 100644 index edad8e6c1..000000000 --- a/passes/opt/opt_dff_comp.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef OPT_DFF_COMP_H -#define OPT_DFF_COMP_H - -#include "kernel/rtlil.h" -#include -#include - -YOSYS_NAMESPACE_BEGIN - -typedef std::map pattern_t; - -inline std::optional find_complementary_pattern_var( - const pattern_t& left, - const pattern_t& right -) { - std::optional ret; - for (const auto &pt : left) { - if (right.count(pt.first) == 0) - return std::nullopt; - if (right.at(pt.first) == pt.second) - continue; - if (ret) - return std::nullopt; - ret = pt.first; - } - return ret; -} - -YOSYS_NAMESPACE_END - -#endif From 93670907633c385ed0bf8d469f10cc3adf1b3939 Mon Sep 17 00:00:00 2001 From: nella Date: Mon, 26 Jan 2026 22:19:36 +0100 Subject: [PATCH 103/291] OptDff more accurate ctrl/pattern desc. --- kernel/pattern.h | 6 +++++- passes/opt/opt_dff.cc | 5 ----- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/kernel/pattern.h b/kernel/pattern.h index 13892ebc5..bb794e9fa 100644 --- a/kernel/pattern.h +++ b/kernel/pattern.h @@ -19,8 +19,12 @@ YOSYS_NAMESPACE_BEGIN * Used for analyzing MUX tree control paths in DFF optimization. */ -typedef std::map pattern_t; // Control signal -> required vals +// Pattern matching for clock enable +// A pattern maps control signals to their required values for a MUX path +typedef std::map pattern_t; // Set of control signals that must ALL match required vals typedef std::set patterns_t; // Alternative patterns (OR) +typedef std::pair ctrl_t; // Control signal +typedef std::set ctrls_t; // Set of control signals that must ALL be active /** * Find if two patterns differ in exactly one variable. diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index ff14d367f..90ace69e5 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -56,11 +56,6 @@ struct OptDffWorker dict bitusers; // Signal sink count dict bit2mux; // Signal bit to driving MUX - // Pattern matching for clock enable - typedef std::map pattern_t; - typedef std::pair ctrl_t; // Control signal - typedef std::set ctrls_t; // Control signals (AND) - std::vector dff_cells; bool is_active(SigBit sig, bool pol) const { From a3c9716f187cb415cee83139b043782c714b6800 Mon Sep 17 00:00:00 2001 From: nella Date: Mon, 26 Jan 2026 22:35:25 +0100 Subject: [PATCH 104/291] OptDff fix unit tests. --- tests/unit/opt/optDffFindComplementaryPatternTest.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/unit/opt/optDffFindComplementaryPatternTest.cc b/tests/unit/opt/optDffFindComplementaryPatternTest.cc index 38fa4bd2d..7a89da6cd 100644 --- a/tests/unit/opt/optDffFindComplementaryPatternTest.cc +++ b/tests/unit/opt/optDffFindComplementaryPatternTest.cc @@ -1,5 +1,5 @@ #include -#include "passes/opt/opt_dff_comp.h" +#include "kernel/pattern.h" YOSYS_NAMESPACE_BEGIN From ef3b2b03803a9df681dd5a4fb490259ab420c3b6 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 26 Jan 2026 22:59:20 +0100 Subject: [PATCH 105/291] linux_perf: mark internal, fix help formatting --- passes/cmds/linux_perf.cc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/passes/cmds/linux_perf.cc b/passes/cmds/linux_perf.cc index f57a887fb..5c2c23b6a 100644 --- a/passes/cmds/linux_perf.cc +++ b/passes/cmds/linux_perf.cc @@ -29,9 +29,14 @@ PRIVATE_NAMESPACE_BEGIN #ifdef __linux__ struct LinuxPerf : public Pass { - LinuxPerf() : Pass("linux_perf", "turn linux perf recording off or on") { } + LinuxPerf() : Pass("linux_perf", "turn linux perf recording off or on") { + internal(); + } void help() override { + log("\n"); + log(" linux_perf [mode]\n"); + log("\n"); log("This pass turns Linux 'perf' profiling on or off, when it has been configured to use control FIFOs.\n"); log("\n"); log("Example shell command line:\n"); From 33e4b1d97f59eb6e3b1359b376ba2179b5d63ade Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 27 Jan 2026 00:28:42 +0000 Subject: [PATCH 106/291] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 6fe4cb69d..03a2ad64a 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.61+56 +YOSYS_VER := 0.61+80 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From c3ffb48a6b640a864ad703d05c1a742544896844 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Wed, 28 Jan 2026 07:45:58 +1300 Subject: [PATCH 107/291] Add and use fix_mod.py --- techlibs/fix_mod.py | 47 + techlibs/gowin/cells_xtra_gw1n.v | 106 +-- techlibs/gowin/cells_xtra_gw2a.v | 113 +-- techlibs/gowin/cells_xtra_gw5a.v | 181 ++-- techlibs/lattice/cells_bb_ecp5.v | 124 ++- techlibs/lattice/cells_bb_nexus.v | 469 +++++++--- techlibs/lattice/cells_bb_xo2.v | 41 +- techlibs/lattice/cells_bb_xo3.v | 41 +- techlibs/lattice/cells_bb_xo3d.v | 41 +- techlibs/xilinx/cells_xtra.v | 1365 ++++++++++++++++++++++------- 10 files changed, 1803 insertions(+), 725 deletions(-) create mode 100644 techlibs/fix_mod.py diff --git a/techlibs/fix_mod.py b/techlibs/fix_mod.py new file mode 100644 index 000000000..d6406108d --- /dev/null +++ b/techlibs/fix_mod.py @@ -0,0 +1,47 @@ +import sys +import subprocess +import re +import os + +def main(): + script = sys.argv.pop(0) + try: + verilog, yosys = sys.argv + except ValueError: + print(f"Expected to be called as 'python3 {script} '.") + exit(1) + + proc = subprocess.run([yosys, '-p', f'read_verilog -lib {verilog}; write_verilog -blackboxes -'], stdout=subprocess.PIPE) + modules = {} + in_mod = False + mod = "" + decl = "" + for line in proc.stdout.decode('utf-8').splitlines(keepends=True): + m = re.match(r'(module (\S+)\(.+)', line, re.S) + if m: + decl, mod = m.groups() + in_mod = True + elif in_mod: + decl += line + + if in_mod and decl.rstrip()[-1] == ';': + in_mod = False + modules[mod] = decl + + src = f'{verilog}.tmp' + os.rename(verilog, src) + dest = verilog + + with open(dest, 'w') as f_out: + with open(src, 'r') as f_in: + for line in f_in: + m = re.match(r'module (\S+) \(\.\.\.\)', line) + if m: + line = modules[m.group(1)] + print(line, end='', file=f_out) + + if src.endswith('.tmp'): + os.remove(src) + +if __name__ == "__main__": + main() diff --git a/techlibs/gowin/cells_xtra_gw1n.v b/techlibs/gowin/cells_xtra_gw1n.v index 436fda0fa..0ab375ec8 100644 --- a/techlibs/gowin/cells_xtra_gw1n.v +++ b/techlibs/gowin/cells_xtra_gw1n.v @@ -1,41 +1,41 @@ // Created by cells_xtra.py -module LUT5 (...); +module LUT5(I0, I1, I2, I3, I4, F); parameter INIT = 32'h00000000; input I0, I1, I2, I3, I4; output F; endmodule -module LUT6 (...); +module LUT6(I0, I1, I2, I3, I4, I5, F); parameter INIT = 64'h0000_0000_0000_0000; input I0, I1, I2, I3, I4, I5; output F; endmodule -module LUT7 (...); +module LUT7(I0, I1, I2, I3, I4, I5, I6, F); parameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000; input I0, I1, I2, I3, I4, I5, I6; output F; endmodule -module LUT8 (...); +module LUT8(I0, I1, I2, I3, I4, I5, I6, I7, F); parameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000; input I0, I1, I2, I3, I4, I5, I6, I7; output F; endmodule -module INV (...); +module INV(I, O); input I; output O; endmodule -module IODELAY (...); +module IODELAY(DI, SDTAP, SETN, VALUE, DF, DO); parameter C_STATIC_DLY = 0; input DI; input SDTAP; @@ -46,7 +46,7 @@ output DO; endmodule -module IEM (...); +module IEM(D, CLK, RESET, MCLK, LAG, LEAD); parameter WINSIZE = "SMALL"; parameter GSREN = "false"; parameter LSREN = "true"; @@ -55,14 +55,14 @@ output LAG, LEAD; endmodule -module ROM16 (...); +module ROM16(AD, DO); parameter INIT_0 = 16'h0000; input [3:0] AD; output DO; endmodule -module ROM (...); +module ROM(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH = 32; parameter BLK_SEL = 3'b000; @@ -141,7 +141,7 @@ output [31:0] DO; endmodule -module ROMX9 (...); +module ROMX9(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH = 36; parameter BLK_SEL = 3'b000; @@ -220,7 +220,7 @@ output [35:0] DO; endmodule -module pROM (...); +module pROM(CLK, CE, OCE, RESET, AD, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH = 32; parameter RESET_MODE = "SYNC"; @@ -296,7 +296,7 @@ output [31:0] DO; endmodule -module pROMX9 (...); +module pROMX9(CLK, CE, OCE, RESET, AD, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH = 36; parameter RESET_MODE = "SYNC"; @@ -372,7 +372,7 @@ output [35:0] DO; endmodule -module SDPB (...); +module SDPB(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, DI, BLKSELA, BLKSELB, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH_0 = 32; parameter BIT_WIDTH_1 = 32; @@ -453,7 +453,7 @@ output [31:0] DO; endmodule -module SDPX9B (...); +module SDPX9B(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, BLKSELA, BLKSELB, DI, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH_0 = 36; parameter BIT_WIDTH_1 = 36; @@ -534,7 +534,7 @@ output [35:0] DO; endmodule -module DPB (...); +module DPB(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, BLKSELA, BLKSELB, DIA, DIB, DOA, DOB); parameter READ_MODE0 = 1'b0; parameter READ_MODE1 = 1'b0; parameter WRITE_MODE0 = 2'b00; @@ -619,7 +619,7 @@ output [15:0] DOA, DOB; endmodule -module DPX9B (...); +module DPX9B(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, DIA, DIB, BLKSELA, BLKSELB, DOA, DOB); parameter READ_MODE0 = 1'b0; parameter READ_MODE1 = 1'b0; parameter WRITE_MODE0 = 2'b00; @@ -704,7 +704,7 @@ output [17:0] DOA, DOB; endmodule -module PADD18 (...); +module PADD18(A, B, ASEL, CE, CLK, RESET, SI, SBI, SO, SBO, DOUT); input [17:0] A; input [17:0] B; input ASEL; @@ -720,7 +720,7 @@ parameter BSEL_MODE = 1'b1; parameter SOREG = 1'b0; endmodule -module PADD9 (...); +module PADD9(A, B, ASEL, CE, CLK, RESET, SI, SBI, SO, SBO, DOUT); input [8:0] A; input [8:0] B; input ASEL; @@ -736,7 +736,7 @@ parameter BSEL_MODE = 1'b1; parameter SOREG = 1'b0; endmodule -module MULT9X9 (...); +module MULT9X9(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB); input [8:0] A,SIA; input [8:0] B,SIB; input ASIGN,BSIGN; @@ -756,7 +756,7 @@ parameter SOA_REG = 1'b0; parameter MULT_RESET_MODE = "SYNC"; endmodule -module MULT18X18 (...); +module MULT18X18(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB); input [17:0] A,SIA; input [17:0] B,SIB; input ASIGN,BSIGN; @@ -776,7 +776,7 @@ parameter SOA_REG = 1'b0; parameter MULT_RESET_MODE = "SYNC"; endmodule -module MULT36X36 (...); +module MULT36X36(A, B, ASIGN, BSIGN, CE, CLK, RESET, DOUT); input [35:0] A; input [35:0] B; input ASIGN,BSIGN; @@ -794,7 +794,7 @@ parameter BSIGN_REG = 1'b0; parameter MULT_RESET_MODE = "SYNC"; endmodule -module MULTALU36X18 (...); +module MULTALU36X18(A, B, C, ASIGN, BSIGN, ACCLOAD, CE, CLK, RESET, CASI, DOUT, CASO); input [17:0] A; input [35:0] B; input [53:0] C; @@ -819,7 +819,7 @@ parameter MULTALU36X18_MODE = 0; parameter C_ADD_SUB = 1'b0; endmodule -module MULTADDALU18X18 (...); +module MULTADDALU18X18(A0, B0, A1, B1, C, SIA, SIB, ASIGN, BSIGN, ASEL, BSEL, CASI, CE, CLK, RESET, ACCLOAD, DOUT, CASO, SOA, SOB); input [17:0] A0; input [17:0] B0; input [17:0] A1; @@ -857,7 +857,7 @@ parameter MULTADDALU18X18_MODE = 0; parameter MULT_RESET_MODE = "SYNC"; endmodule -module MULTALU18X18 (...); +module MULTALU18X18(A, B, CLK, CE, RESET, ASIGN, BSIGN, ACCLOAD, DSIGN, C, D, CASI, DOUT, CASO); input [17:0] A, B; input CLK,CE,RESET; input ASIGN, BSIGN; @@ -883,7 +883,7 @@ parameter C_ADD_SUB = 1'b0; parameter MULTALU18X18_MODE = 0; endmodule -module ALU54D (...); +module ALU54D(A, B, ASIGN, BSIGN, ACCLOAD, CASI, CLK, CE, RESET, DOUT, CASO); input [53:0] A, B; input ASIGN,BSIGN; input ACCLOAD; @@ -903,19 +903,19 @@ parameter ALUD_MODE = 0; parameter ALU_RESET_MODE = "SYNC"; endmodule -module BUFG (...); +module BUFG(O, I); output O; input I; endmodule -module BUFS (...); +module BUFS(O, I); output O; input I; endmodule -module PLL (...); +module PLL(CLKIN, CLKFB, RESET, RESET_P, RESET_I, RESET_S, FBDSEL, IDSEL, ODSEL, PSDA, FDLY, DUTYDA, CLKOUT, LOCK, CLKOUTP, CLKOUTD, CLKOUTD3); input CLKIN; input CLKFB; input RESET; @@ -956,39 +956,39 @@ parameter CLKOUTD3_SRC = "CLKOUT"; parameter DEVICE = "GW1N-4"; endmodule -module TLVDS_IBUF (...); +module TLVDS_IBUF(O, I, IB); output O; input I, IB; endmodule -module TLVDS_TBUF (...); +module TLVDS_TBUF(O, OB, I, OEN); output O, OB; input I, OEN; endmodule -module TLVDS_IOBUF (...); +module TLVDS_IOBUF(O, IO, IOB, I, OEN); output O; inout IO, IOB; input I, OEN; endmodule -module ELVDS_IBUF (...); +module ELVDS_IBUF(O, I, IB); output O; input I, IB; endmodule -module ELVDS_TBUF (...); +module ELVDS_TBUF(O, OB, I, OEN); output O, OB; input I, OEN; endmodule -module ELVDS_IOBUF (...); +module ELVDS_IOBUF(O, IO, IOB, I, OEN); output O; inout IO, IOB; input I, OEN; endmodule -module MIPI_IBUF (...); +module MIPI_IBUF(OH, OL, OB, IO, IOB, I, IB, OEN, OENB, HSREN); output OH, OL, OB; inout IO, IOB; input I, IB; @@ -996,40 +996,40 @@ input OEN, OENB; input HSREN; endmodule -module MIPI_IBUF_HS (...); +module MIPI_IBUF_HS(OH, I, IB); output OH; input I, IB; endmodule -module MIPI_IBUF_LP (...); +module MIPI_IBUF_LP(OL, OB, I, IB); output OL; output OB; input I; input IB; endmodule -module MIPI_OBUF (...); +module MIPI_OBUF(O, OB, I, IB, MODESEL); output O, OB; input I, IB, MODESEL; endmodule -module MIPI_OBUF_A (...); +module MIPI_OBUF_A(O, OB, I, IB, IL, MODESEL); output O, OB; input I, IB, IL, MODESEL; endmodule -module ELVDS_IBUF_MIPI (...); +module ELVDS_IBUF_MIPI(OH, OL, I, IB); output OH, OL; input I, IB; endmodule -module I3C_IOBUF (...); +module I3C_IOBUF(O, IO, I, MODESEL); output O; inout IO; input I, MODESEL; endmodule -module CLKDIV (...); +module CLKDIV(HCLKIN, RESETN, CALIB, CLKOUT); input HCLKIN; input RESETN; input CALIB; @@ -1038,12 +1038,12 @@ parameter DIV_MODE = "2"; parameter GSREN = "false"; endmodule -module DHCEN (...); +module DHCEN(CLKIN, CE, CLKOUT); input CLKIN,CE; output CLKOUT; endmodule -module DLLDLY (...); +module DLLDLY(CLKIN, DLLSTEP, DIR, LOADN, MOVE, CLKOUT, FLAG); input CLKIN; input [7:0] DLLSTEP; input DIR,LOADN,MOVE; @@ -1054,7 +1054,7 @@ parameter DLY_SIGN = 1'b0; parameter DLY_ADJ = 0; endmodule -module FLASH96K (...); +module FLASH96K(RA, CA, PA, MODE, SEQ, ACLK, PW, RESET, PE, OE, RMODE, WMODE, RBYTESEL, WBYTESEL, DIN, DOUT); input [5:0] RA,CA,PA; input [3:0] MODE; input [1:0] SEQ; @@ -1065,7 +1065,7 @@ input [31:0] DIN; output [31:0] DOUT; endmodule -module FLASH256K (...); +module FLASH256K(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, DIN, DOUT); input[6:0]XADR; input[5:0]YADR; input XE,YE,SE; @@ -1087,7 +1087,7 @@ parameter IDLE = 4'd0, RD_S2 = 4'd12; endmodule -module FLASH608K (...); +module FLASH608K(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, DIN, DOUT); input[8:0]XADR; input[5:0]YADR; input XE,YE,SE; @@ -1109,31 +1109,31 @@ parameter IDLE = 4'd0, RD_S2 = 4'd12; endmodule -module DCS (...); +module DCS(CLK0, CLK1, CLK2, CLK3, SELFORCE, CLKSEL, CLKOUT); input CLK0, CLK1, CLK2, CLK3, SELFORCE; input [3:0] CLKSEL; output CLKOUT; parameter DCS_MODE = "RISING"; endmodule -module DQCE (...); +module DQCE(CLKIN, CE, CLKOUT); input CLKIN; input CE; output CLKOUT; endmodule -module CLKDIV2 (...); +module CLKDIV2(HCLKIN, RESETN, CLKOUT); parameter GSREN = "false"; input HCLKIN, RESETN; output CLKOUT; endmodule -module DHCENC (...); +module DHCENC(CLKIN, CE, CLKOUT, CLKOUTN); input CLKIN, CE; output CLKOUT, CLKOUTN; endmodule -module FLASH64K (...); +module FLASH64K(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, SLEEP, DIN, DOUT); input[4:0]XADR; input[5:0]YADR; input XE,YE,SE; @@ -1156,7 +1156,7 @@ parameter IDLE = 4'd0, RD_S2 = 4'd12; endmodule -module FLASH64KZ (...); +module FLASH64KZ(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, DIN, DOUT); input[4:0]XADR; input[5:0]YADR; input XE,YE,SE; diff --git a/techlibs/gowin/cells_xtra_gw2a.v b/techlibs/gowin/cells_xtra_gw2a.v index 4df48ab64..643723db6 100644 --- a/techlibs/gowin/cells_xtra_gw2a.v +++ b/techlibs/gowin/cells_xtra_gw2a.v @@ -1,41 +1,41 @@ // Created by cells_xtra.py -module LUT5 (...); +module LUT5(I0, I1, I2, I3, I4, F); parameter INIT = 32'h00000000; input I0, I1, I2, I3, I4; output F; endmodule -module LUT6 (...); +module LUT6(I0, I1, I2, I3, I4, I5, F); parameter INIT = 64'h0000_0000_0000_0000; input I0, I1, I2, I3, I4, I5; output F; endmodule -module LUT7 (...); +module LUT7(I0, I1, I2, I3, I4, I5, I6, F); parameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000; input I0, I1, I2, I3, I4, I5, I6; output F; endmodule -module LUT8 (...); +module LUT8(I0, I1, I2, I3, I4, I5, I6, I7, F); parameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000; input I0, I1, I2, I3, I4, I5, I6, I7; output F; endmodule -module INV (...); +module INV(I, O); input I; output O; endmodule -module IDDR_MEM (...); +module IDDR_MEM(D, ICLK, PCLK, WADDR, RADDR, RESET, Q0, Q1); parameter GSREN = "false"; parameter LSREN = "true"; input D, ICLK, PCLK; @@ -46,7 +46,7 @@ output Q0,Q1; endmodule -module ODDR_MEM (...); +module ODDR_MEM(D0, D1, TX, PCLK, TCLK, RESET, Q0, Q1); parameter GSREN = "false"; parameter LSREN = "true"; parameter TCLK_SOURCE = "DQSW"; @@ -57,7 +57,7 @@ output Q0, Q1; endmodule -module IDES4_MEM (...); +module IDES4_MEM(D, ICLK, FCLK, PCLK, WADDR, RADDR, RESET, CALIB, Q0, Q1, Q2, Q3); parameter GSREN = "false"; parameter LSREN = "true"; input D, ICLK, FCLK, PCLK; @@ -68,7 +68,7 @@ output Q0,Q1,Q2,Q3; endmodule -module IDES8_MEM (...); +module IDES8_MEM(D, ICLK, FCLK, PCLK, WADDR, RADDR, RESET, CALIB, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7); parameter GSREN = "false"; parameter LSREN = "true"; input D, ICLK, FCLK, PCLK; @@ -79,7 +79,7 @@ output Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7; endmodule -module OSER4_MEM (...); +module OSER4_MEM(D0, D1, D2, D3, TX0, TX1, PCLK, FCLK, TCLK, RESET, Q0, Q1); parameter GSREN = "false"; parameter LSREN = "true"; parameter HWL = "false"; @@ -92,7 +92,7 @@ output Q0, Q1; endmodule -module OSER8_MEM (...); +module OSER8_MEM(D0, D1, D2, D3, D4, D5, D6, D7, TX0, TX1, TX2, TX3, PCLK, FCLK, TCLK, RESET, Q0, Q1); parameter GSREN = "false"; parameter LSREN = "true"; parameter HWL = "false"; @@ -105,7 +105,7 @@ output Q0, Q1; endmodule -module IODELAY (...); +module IODELAY(DI, SDTAP, SETN, VALUE, DF, DO); parameter C_STATIC_DLY = 0; input DI; input SDTAP; @@ -116,7 +116,7 @@ output DO; endmodule -module IEM (...); +module IEM(D, CLK, RESET, MCLK, LAG, LEAD); parameter WINSIZE = "SMALL"; parameter GSREN = "false"; parameter LSREN = "true"; @@ -125,14 +125,14 @@ output LAG, LEAD; endmodule -module ROM16 (...); +module ROM16(AD, DO); parameter INIT_0 = 16'h0000; input [3:0] AD; output DO; endmodule -module ROM (...); +module ROM(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH = 32; parameter BLK_SEL = 3'b000; @@ -211,7 +211,7 @@ output [31:0] DO; endmodule -module ROMX9 (...); +module ROMX9(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH = 36; parameter BLK_SEL = 3'b000; @@ -290,7 +290,7 @@ output [35:0] DO; endmodule -module pROM (...); +module pROM(CLK, CE, OCE, RESET, AD, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH = 32; parameter RESET_MODE = "SYNC"; @@ -366,7 +366,7 @@ output [31:0] DO; endmodule -module pROMX9 (...); +module pROMX9(CLK, CE, OCE, RESET, AD, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH = 36; parameter RESET_MODE = "SYNC"; @@ -442,7 +442,7 @@ output [35:0] DO; endmodule -module SDPB (...); +module SDPB(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, DI, BLKSELA, BLKSELB, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH_0 = 32; parameter BIT_WIDTH_1 = 32; @@ -523,7 +523,7 @@ output [31:0] DO; endmodule -module SDPX9B (...); +module SDPX9B(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, BLKSELA, BLKSELB, DI, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH_0 = 36; parameter BIT_WIDTH_1 = 36; @@ -604,7 +604,7 @@ output [35:0] DO; endmodule -module DPB (...); +module DPB(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, BLKSELA, BLKSELB, DIA, DIB, DOA, DOB); parameter READ_MODE0 = 1'b0; parameter READ_MODE1 = 1'b0; parameter WRITE_MODE0 = 2'b00; @@ -689,7 +689,7 @@ output [15:0] DOA, DOB; endmodule -module DPX9B (...); +module DPX9B(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, DIA, DIB, BLKSELA, BLKSELB, DOA, DOB); parameter READ_MODE0 = 1'b0; parameter READ_MODE1 = 1'b0; parameter WRITE_MODE0 = 2'b00; @@ -774,7 +774,7 @@ output [17:0] DOA, DOB; endmodule -module PADD18 (...); +module PADD18(A, B, ASEL, CE, CLK, RESET, SI, SBI, SO, SBO, DOUT); input [17:0] A; input [17:0] B; input ASEL; @@ -790,7 +790,7 @@ parameter BSEL_MODE = 1'b1; parameter SOREG = 1'b0; endmodule -module PADD9 (...); +module PADD9(A, B, ASEL, CE, CLK, RESET, SI, SBI, SO, SBO, DOUT); input [8:0] A; input [8:0] B; input ASEL; @@ -806,7 +806,7 @@ parameter BSEL_MODE = 1'b1; parameter SOREG = 1'b0; endmodule -module MULT9X9 (...); +module MULT9X9(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB); input [8:0] A,SIA; input [8:0] B,SIB; input ASIGN,BSIGN; @@ -826,7 +826,7 @@ parameter SOA_REG = 1'b0; parameter MULT_RESET_MODE = "SYNC"; endmodule -module MULT18X18 (...); +module MULT18X18(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB); input [17:0] A,SIA; input [17:0] B,SIB; input ASIGN,BSIGN; @@ -846,7 +846,7 @@ parameter SOA_REG = 1'b0; parameter MULT_RESET_MODE = "SYNC"; endmodule -module MULT36X36 (...); +module MULT36X36(A, B, ASIGN, BSIGN, CE, CLK, RESET, DOUT); input [35:0] A; input [35:0] B; input ASIGN,BSIGN; @@ -864,7 +864,7 @@ parameter BSIGN_REG = 1'b0; parameter MULT_RESET_MODE = "SYNC"; endmodule -module MULTALU36X18 (...); +module MULTALU36X18(A, B, C, ASIGN, BSIGN, ACCLOAD, CE, CLK, RESET, CASI, DOUT, CASO); input [17:0] A; input [35:0] B; input [53:0] C; @@ -889,7 +889,7 @@ parameter MULTALU36X18_MODE = 0; parameter C_ADD_SUB = 1'b0; endmodule -module MULTADDALU18X18 (...); +module MULTADDALU18X18(A0, B0, A1, B1, C, SIA, SIB, ASIGN, BSIGN, ASEL, BSEL, CASI, CE, CLK, RESET, ACCLOAD, DOUT, CASO, SOA, SOB); input [17:0] A0; input [17:0] B0; input [17:0] A1; @@ -927,7 +927,7 @@ parameter MULTADDALU18X18_MODE = 0; parameter MULT_RESET_MODE = "SYNC"; endmodule -module MULTALU18X18 (...); +module MULTALU18X18(A, B, CLK, CE, RESET, ASIGN, BSIGN, ACCLOAD, DSIGN, C, D, CASI, DOUT, CASO); input [17:0] A, B; input CLK,CE,RESET; input ASIGN, BSIGN; @@ -953,7 +953,7 @@ parameter C_ADD_SUB = 1'b0; parameter MULTALU18X18_MODE = 0; endmodule -module ALU54D (...); +module ALU54D(A, B, ASIGN, BSIGN, ACCLOAD, CASI, CLK, CE, RESET, DOUT, CASO); input [53:0] A, B; input ASIGN,BSIGN; input ACCLOAD; @@ -973,19 +973,19 @@ parameter ALUD_MODE = 0; parameter ALU_RESET_MODE = "SYNC"; endmodule -module BUFG (...); +module BUFG(O, I); output O; input I; endmodule -module BUFS (...); +module BUFS(O, I); output O; input I; endmodule -module PLL (...); +module PLL(CLKIN, CLKFB, RESET, RESET_P, RESET_I, RESET_S, FBDSEL, IDSEL, ODSEL, PSDA, FDLY, DUTYDA, CLKOUT, LOCK, CLKOUTP, CLKOUTD, CLKOUTD3); input CLKIN; input CLKFB; input RESET; @@ -1026,39 +1026,39 @@ parameter CLKOUTD3_SRC = "CLKOUT"; parameter DEVICE = "GW2A-18"; endmodule -module TLVDS_IBUF (...); +module TLVDS_IBUF(O, I, IB); output O; input I, IB; endmodule -module TLVDS_TBUF (...); +module TLVDS_TBUF(O, OB, I, OEN); output O, OB; input I, OEN; endmodule -module TLVDS_IOBUF (...); +module TLVDS_IOBUF(O, IO, IOB, I, OEN); output O; inout IO, IOB; input I, OEN; endmodule -module ELVDS_IBUF (...); +module ELVDS_IBUF(O, I, IB); output O; input I, IB; endmodule -module ELVDS_TBUF (...); +module ELVDS_TBUF(O, OB, I, OEN); output O, OB; input I, OEN; endmodule -module ELVDS_IOBUF (...); +module ELVDS_IOBUF(O, IO, IOB, I, OEN); output O; inout IO, IOB; input I, OEN; endmodule -module CLKDIV (...); +module CLKDIV(HCLKIN, RESETN, CALIB, CLKOUT); input HCLKIN; input RESETN; input CALIB; @@ -1067,12 +1067,13 @@ parameter DIV_MODE = "2"; parameter GSREN = "false"; endmodule -module DHCEN (...); +module DHCEN(CLKIN, CE, CLKOUT); input CLKIN,CE; output CLKOUT; endmodule -module DQS (...); +module DQS(DQSIN, PCLK, FCLK, RESET, READ, RCLKSEL, DLLSTEP, WSTEP, RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD, DQSR90, DQSW0, DQSW270, RPOINT, WPOINT, RVALID +, RBURST, RFLAG, WFLAG); input DQSIN,PCLK,FCLK,RESET; input [3:0] READ; input [2:0] RCLKSEL; @@ -1089,7 +1090,7 @@ output RVALID,RBURST, RFLAG, WFLAG; parameter GSREN = "false"; endmodule -module DLLDLY (...); +module DLLDLY(CLKIN, DLLSTEP, DIR, LOADN, MOVE, CLKOUT, FLAG); input CLKIN; input [7:0] DLLSTEP; input DIR,LOADN,MOVE; @@ -1100,67 +1101,67 @@ parameter DLY_SIGN = 1'b0; parameter DLY_ADJ = 0; endmodule -module DCS (...); +module DCS(CLK0, CLK1, CLK2, CLK3, SELFORCE, CLKSEL, CLKOUT); input CLK0, CLK1, CLK2, CLK3, SELFORCE; input [3:0] CLKSEL; output CLKOUT; parameter DCS_MODE = "RISING"; endmodule -module DQCE (...); +module DQCE(CLKIN, CE, CLKOUT); input CLKIN; input CE; output CLKOUT; endmodule -module CLKDIV2 (...); +module CLKDIV2(HCLKIN, RESETN, CLKOUT); parameter GSREN = "false"; input HCLKIN, RESETN; output CLKOUT; endmodule -module IBUF_R (...); +module IBUF_R(I, RTEN, O); input I; input RTEN; output O; endmodule -module IOBUF_R (...); +module IOBUF_R(I, OEN, RTEN, O, IO); input I,OEN; input RTEN; output O; inout IO; endmodule -module ELVDS_IBUF_R (...); +module ELVDS_IBUF_R(O, I, IB, RTEN); output O; input I, IB; input RTEN; endmodule -module ELVDS_IOBUF_R (...); +module ELVDS_IOBUF_R(O, IO, IOB, I, OEN, RTEN); output O; inout IO, IOB; input I, OEN; input RTEN; endmodule -module OTP (...); +module OTP(CSB, SCLK, DOUT); input CSB, SCLK; output DOUT; endmodule -module SAMB (...); +module SAMB(SPIAD, LOADN_SPIAD); input [23:0] SPIAD; input LOADN_SPIAD; endmodule -module ELVDS_IBUF_MIPI (...); +module ELVDS_IBUF_MIPI(OH, OL, I, IB); output OH, OL; input I, IB; endmodule -module MIPI_IBUF (...); +module MIPI_IBUF(OH, OL, OB, IO, IOB, I, IB, OEN, OENB, HSREN); output OH, OL, OB; inout IO, IOB; input I, IB; @@ -1168,7 +1169,7 @@ input OEN, OENB; input HSREN; endmodule -module I3C_IOBUF (...); +module I3C_IOBUF(O, IO, I, MODESEL); output O; inout IO; input I, MODESEL; diff --git a/techlibs/gowin/cells_xtra_gw5a.v b/techlibs/gowin/cells_xtra_gw5a.v index b2dc06236..dd6a540b3 100644 --- a/techlibs/gowin/cells_xtra_gw5a.v +++ b/techlibs/gowin/cells_xtra_gw5a.v @@ -1,75 +1,75 @@ // Created by cells_xtra.py -module LUT5 (...); +module LUT5(I0, I1, I2, I3, I4, F); parameter INIT = 32'h00000000; input I0, I1, I2, I3, I4; output F; endmodule -module LUT6 (...); +module LUT6(I0, I1, I2, I3, I4, I5, F); parameter INIT = 64'h0000_0000_0000_0000; input I0, I1, I2, I3, I4, I5; output F; endmodule -module LUT7 (...); +module LUT7(I0, I1, I2, I3, I4, I5, I6, F); parameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000; input I0, I1, I2, I3, I4, I5, I6; output F; endmodule -module LUT8 (...); +module LUT8(I0, I1, I2, I3, I4, I5, I6, I7, F); parameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000; input I0, I1, I2, I3, I4, I5, I6, I7; output F; endmodule -module ROM16 (...); +module ROM16(AD, DO); parameter INIT_0 = 16'h0000; input [3:0] AD; output DO; endmodule -module INV (...); +module INV(I, O); input I; output O; endmodule -module TLVDS_IBUF (...); +module TLVDS_IBUF(O, I, IB); output O; input I, IB; endmodule -module TLVDS_TBUF (...); +module TLVDS_TBUF(O, OB, I, OEN); output O, OB; input I, OEN; endmodule -module TLVDS_IOBUF (...); +module TLVDS_IOBUF(O, IO, IOB, I, OEN); output O; inout IO, IOB; input I, OEN; endmodule -module ELVDS_TBUF (...); +module ELVDS_TBUF(O, OB, I, OEN); output O, OB; input I, OEN; endmodule -module ELVDS_IOBUF (...); +module ELVDS_IOBUF(O, IO, IOB, I, OEN); output O; inout IO, IOB; input I, OEN; endmodule -module MIPI_IBUF (...); +module MIPI_IBUF(OH, OL, OB, IO, IOB, I, IB, OEN, OENB, HSEN, HSREN); output OH, OL, OB; inout IO, IOB; input I, IB; @@ -77,32 +77,33 @@ input OEN, OENB; input HSEN, HSREN; endmodule -module MIPI_OBUF_A (...); +module MIPI_OBUF_A(O, OB, I, IB, IL, MODESEL, IO, IOB, OEN, OENB); output O, OB; input I, IB, IL, MODESEL; inout IO, IOB; input OEN, OENB; endmodule -module ELVDS_IOBUF_R (...); +module ELVDS_IOBUF_R(O, IO, IOB, I, OEN, RTEN); output O; inout IO, IOB; input I, OEN; input RTEN; endmodule -module I3C_IOBUF (...); +module I3C_IOBUF(O, IO, I, MODESEL); output O; inout IO; input I, MODESEL; endmodule -module TLVDS_IBUF_ADC (...); +module TLVDS_IBUF_ADC(I, IB, ADCEN); input I, IB; input ADCEN; endmodule -module MIPI_CPHY_IBUF (...); +module MIPI_CPHY_IBUF(OH0, OL0, OB0, OH1, OL1, OB1, OH2, OL2, OB2, IO0, IOB0, IO1, IOB1, IO2, IOB2, I0, IB0, I1, IB1, I2, IB2 +, OEN, OENB, HSEN); output OH0, OL0, OB0, OH1, OL1, OB1, OH2, OL2, OB2; inout IO0, IOB0, IO1, IOB1, IO2, IOB2; input I0, IB0, I1, IB1, I2, IB2; @@ -110,14 +111,15 @@ input OEN, OENB; input HSEN; endmodule -module MIPI_CPHY_OBUF (...); +module MIPI_CPHY_OBUF(O0, OB0, O1, OB1, O2, OB2, I0, IB0, IL0, I1, IB1, IL1, I2, IB2, IL2, IO0, IOB0, IO1, IOB1, IO2, IOB2 +, OEN, OENB, MODESEL, VCOME); output O0, OB0, O1, OB1, O2, OB2; input I0, IB0, IL0, I1, IB1, IL1, I2, IB2, IL2; inout IO0, IOB0, IO1, IOB1, IO2, IOB2; input OEN, OENB, MODESEL, VCOME; endmodule -module SDPB (...); +module SDPB(CLKA, CEA, CLKB, CEB, OCE, RESET, ADA, ADB, DI, BLKSELA, BLKSELB, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH_0 = 32; parameter BIT_WIDTH_1 = 32; @@ -198,7 +200,7 @@ output [31:0] DO; endmodule -module SDPX9B (...); +module SDPX9B(CLKA, CEA, CLKB, CEB, OCE, RESET, ADA, ADB, BLKSELA, BLKSELB, DI, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH_0 = 36; parameter BIT_WIDTH_1 = 36; @@ -279,7 +281,7 @@ output [35:0] DO; endmodule -module DPB (...); +module DPB(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, BLKSELA, BLKSELB, DIA, DIB, DOA, DOB); parameter READ_MODE0 = 1'b0; parameter READ_MODE1 = 1'b0; parameter WRITE_MODE0 = 2'b00; @@ -364,7 +366,7 @@ output [15:0] DOA, DOB; endmodule -module DPX9B (...); +module DPX9B(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, DIA, DIB, BLKSELA, BLKSELB, DOA, DOB); parameter READ_MODE0 = 1'b0; parameter READ_MODE1 = 1'b0; parameter WRITE_MODE0 = 2'b00; @@ -449,7 +451,7 @@ output [17:0] DOA, DOB; endmodule -module pROM (...); +module pROM(CLK, CE, OCE, RESET, AD, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH = 32; parameter RESET_MODE = "SYNC"; @@ -525,7 +527,7 @@ output [31:0] DO; endmodule -module pROMX9 (...); +module pROMX9(CLK, CE, OCE, RESET, AD, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH = 36; parameter RESET_MODE = "SYNC"; @@ -601,7 +603,7 @@ output [35:0] DO; endmodule -module SDP36KE (...); +module SDP36KE(CLKA, CEA, CLKB, CEB, OCE, RESET, ADA, ADB, DI, DIP, BLKSELA, BLKSELB, DECCI, SECCI, DO, DOP, DECCO, SECCO, ECCP); parameter ECC_WRITE_EN="TRUE"; parameter ECC_READ_EN="TRUE"; parameter READ_MODE = 1'b0; @@ -768,7 +770,7 @@ output [7:0] ECCP; endmodule -module SDP136K (...); +module SDP136K(CLKA, CLKB, WE, RE, ADA, ADB, DI, DO); input CLKA, CLKB; input WE, RE; input [10:0] ADA, ADB; @@ -776,7 +778,7 @@ input [67:0] DI; output [67:0] DO; endmodule -module MULTADDALU12X12 (...); +module MULTADDALU12X12(DOUT, CASO, A0, B0, A1, B1, CASI, ACCSEL, CASISEL, ADDSUB, CLK, CE, RESET); parameter A0REG_CLK = "BYPASS"; parameter A0REG_CE = "CE0"; parameter A0REG_RESET = "RESET0"; @@ -842,7 +844,7 @@ input [1:0] ADDSUB; input [1:0] CLK, CE, RESET; endmodule -module MULTALU27X18 (...); +module MULTALU27X18(DOUT, CASO, SOA, A, SIA, B, C, D, CASI, ACCSEL, PSEL, ASEL, PADDSUB, CSEL, CASISEL, ADDSUB, CLK, CE, RESET); parameter AREG_CLK = "BYPASS"; parameter AREG_CE = "CE0"; parameter AREG_RESET = "RESET0"; @@ -937,7 +939,7 @@ input [1:0] ADDSUB; input [1:0] CLK, CE, RESET; endmodule -module MULT12X12 (...); +module MULT12X12(DOUT, A, B, CLK, CE, RESET); parameter AREG_CLK = "BYPASS"; parameter AREG_CE = "CE0"; parameter AREG_RESET = "RESET0"; @@ -956,7 +958,7 @@ input [11:0] A, B; input [1:0] CLK, CE, RESET; endmodule -module MULT27X36 (...); +module MULT27X36(DOUT, A, B, D, CLK, CE, RESET, PSEL, PADDSUB); parameter AREG_CLK = "BYPASS"; parameter AREG_CE = "CE0"; parameter AREG_RESET = "RESET0"; @@ -992,7 +994,7 @@ input PSEL; input PADDSUB; endmodule -module MULTACC (...); +module MULTACC(DATAO, CASO, CE, CLK, COFFIN0, COFFIN1, COFFIN2, DATAIN0, DATAIN1, DATAIN2, RSTN, CASI); output [23:0] DATAO, CASO; input CE, CLK; input [5:0] COFFIN0, COFFIN1, COFFIN2; @@ -1010,7 +1012,7 @@ parameter CASI_EN = "FALSE"; parameter CASO_EN = "FALSE"; endmodule -module IDDR_MEM (...); +module IDDR_MEM(D, ICLK, PCLK, WADDR, RADDR, RESET, Q0, Q1); input D, ICLK, PCLK; input [2:0] WADDR; input [2:0] RADDR; @@ -1019,7 +1021,7 @@ output Q0,Q1; endmodule -module ODDR_MEM (...); +module ODDR_MEM(D0, D1, TX, PCLK, TCLK, RESET, Q0, Q1); parameter TCLK_SOURCE = "DQSW"; parameter TXCLK_POL = 1'b0; input D0, D1; @@ -1028,7 +1030,7 @@ output Q0, Q1; endmodule -module IDES4_MEM (...); +module IDES4_MEM(PCLK, D, ICLK, FCLK, RESET, CALIB, WADDR, RADDR, Q0, Q1, Q2, Q3); input PCLK, D, ICLK, FCLK, RESET, CALIB; input [2:0] WADDR; input [2:0] RADDR; @@ -1036,7 +1038,7 @@ output Q0,Q1,Q2,Q3; endmodule -module IDES8_MEM (...); +module IDES8_MEM(PCLK, D, ICLK, FCLK, RESET, CALIB, WADDR, RADDR, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7); input PCLK, D, ICLK, FCLK, RESET, CALIB; input [2:0] WADDR; input [2:0] RADDR; @@ -1044,19 +1046,20 @@ output Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7; endmodule -module IDES14 (...); +module IDES14(D, FCLK, PCLK, CALIB, RESET, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13); input D, FCLK, PCLK, CALIB,RESET; output Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13; endmodule -module IDES32 (...); +module IDES32(D, FCLK, PCLK, CALIB, RESET, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 +, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31); input D, FCLK, PCLK, CALIB,RESET; output Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31; endmodule -module OSER4_MEM (...); +module OSER4_MEM(D0, D1, D2, D3, TX0, TX1, PCLK, FCLK, TCLK, RESET, Q0, Q1); parameter HWL = "false"; parameter TCLK_SOURCE = "DQSW"; parameter TXCLK_POL = 1'b0; @@ -1067,7 +1070,7 @@ output Q0, Q1; endmodule -module OSER8_MEM (...); +module OSER8_MEM(D0, D1, D2, D3, D4, D5, D6, D7, TX0, TX1, TX2, TX3, PCLK, FCLK, TCLK, RESET, Q0, Q1); parameter HWL = "false"; parameter TCLK_SOURCE = "DQSW"; parameter TXCLK_POL = 1'b0; @@ -1078,13 +1081,13 @@ output Q0, Q1; endmodule -module OSER14 (...); +module OSER14(D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, PCLK, FCLK, RESET, Q); input D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13; input PCLK, FCLK, RESET; output Q; endmodule -module IODELAY (...); +module IODELAY(DI, SDTAP, VALUE, DLYSTEP, DF, DO); parameter C_STATIC_DLY = 0; parameter DYN_DLY_EN = "FALSE"; parameter ADAPT_EN = "FALSE"; @@ -1097,7 +1100,7 @@ output DO; endmodule -module OSIDES32 (...); +module OSIDES32(Q, D, PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN, RESET, DF0, DF1, SDTAP0, SDTAP1, VALUE0, VALUE1, DLYSTEP0, DLYSTEP1); output [31:0] Q; input D; input PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN; @@ -1114,7 +1117,8 @@ parameter DYN_DLY_EN_1 = "FALSE"; parameter ADAPT_EN_1 = "FALSE"; endmodule -module OSIDES64 (...); +module OSIDES64(Q, D, PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN, RESET, DF0, DF1, DF2, DF3, SDTAP0, SDTAP1, SDTAP2, SDTAP3, VALUE0, VALUE1, VALUE2, VALUE3, DLYSTEP0 +, DLYSTEP1, DLYSTEP2, DLYSTEP3); output [63:0] Q; input D; input PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN; @@ -1137,20 +1141,20 @@ parameter DYN_DLY_EN_3 = "FALSE"; parameter ADAPT_EN_3 = "FALSE"; endmodule -module DCE (...); +module DCE(CLKIN, CE, CLKOUT); input CLKIN; input CE; output CLKOUT; endmodule -module DCS (...); +module DCS(CLKIN0, CLKIN1, CLKIN2, CLKIN3, SELFORCE, CLKSEL, CLKOUT); input CLKIN0, CLKIN1, CLKIN2, CLKIN3, SELFORCE; input [3:0] CLKSEL; output CLKOUT; parameter DCS_MODE = "RISING"; endmodule -module DDRDLL (...); +module DDRDLL(CLKIN, STOP, UPDNCNTL, RESET, STEP, LOCK); input CLKIN; input STOP; input UPDNCNTL; @@ -1163,7 +1167,7 @@ parameter SCAL_EN = "TRUE"; parameter DIV_SEL = 1'b0; endmodule -module DLLDLY (...); +module DLLDLY(CLKIN, DLLSTEP, CSTEP, LOADN, MOVE, CLKOUT, FLAG); input CLKIN; input [7:0] DLLSTEP, CSTEP; input LOADN,MOVE; @@ -1176,7 +1180,7 @@ parameter ADAPT_EN = "FALSE"; parameter STEP_SEL = 1'b0; endmodule -module CLKDIV (...); +module CLKDIV(HCLKIN, RESETN, CALIB, CLKOUT); input HCLKIN; input RESETN; input CALIB; @@ -1184,24 +1188,24 @@ output CLKOUT; parameter DIV_MODE = "2"; endmodule -module CLKDIV2 (...); +module CLKDIV2(HCLKIN, RESETN, CLKOUT); input HCLKIN, RESETN; output CLKOUT; endmodule -module DHCE (...); +module DHCE(CLKIN, CEN, CLKOUT); input CLKIN; input CEN; output CLKOUT; endmodule -module OSCA (...); +module OSCA(OSCOUT, OSCEN); parameter FREQ_DIV = 100; output OSCOUT; input OSCEN; endmodule -module OSCB (...); +module OSCB(OSCOUT, OSCREF, OSCEN, FMODE, RTRIM, RTCTRIM); parameter FREQ_MODE = "25"; parameter FREQ_DIV = 10; parameter DYN_TRIM_EN = "FALSE"; @@ -1212,7 +1216,9 @@ input [7:0] RTRIM; input [5:0] RTCTRIM; endmodule -module PLL (...); +module PLL(CLKIN, CLKFB, RESET, PLLPWD, RESET_I, RESET_O, FBDSEL, IDSEL, MDSEL, MDSEL_FRAC, ODSEL0, ODSEL0_FRAC, ODSEL1, ODSEL2, ODSEL3, ODSEL4, ODSEL5, ODSEL6, DT0, DT1, DT2 +, DT3, ICPSEL, LPFRES, LPFCAP, PSSEL, PSDIR, PSPULSE, ENCLK0, ENCLK1, ENCLK2, ENCLK3, ENCLK4, ENCLK5, ENCLK6, SSCPOL, SSCON, SSCMDSEL, SSCMDSEL_FRAC, LOCK, CLKOUT0, CLKOUT1 +, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, CLKOUT6, CLKFBOUT); input CLKIN; input CLKFB; input RESET; @@ -1354,7 +1360,8 @@ parameter LPF_CAP = 2'b00; parameter SSC_EN = "FALSE"; endmodule -module PLLA (...); +module PLLA(CLKIN, CLKFB, RESET, PLLPWD, RESET_I, RESET_O, PSSEL, PSDIR, PSPULSE, SSCPOL, SSCON, SSCMDSEL, SSCMDSEL_FRAC, MDCLK, MDOPC, MDAINC, MDWDI, MDRDO, LOCK, CLKOUT0, CLKOUT1 +, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, CLKOUT6, CLKFBOUT); input CLKIN; input CLKFB; input RESET; @@ -1462,7 +1469,14 @@ parameter LPF_CAP = 2'b00; parameter SSC_EN = "FALSE"; endmodule -module AE350_SOC (...); +module AE350_SOC(POR_N, HW_RSTN, CORE_CLK, DDR_CLK, AHB_CLK, APB_CLK, DBG_TCK, RTC_CLK, CORE_CE, AXI_CE, DDR_CE, AHB_CE, APB_CE, APB2AHB_CE, SCAN_TEST, SCAN_EN, PRESETN, HRESETN, DDR_RSTN, GP_INT, DMA_REQ +, DMA_ACK, CORE0_WFI_MODE, WAKEUP_IN, RTC_WAKEUP, TEST_CLK, TEST_MODE, TEST_RSTN, ROM_HADDR, ROM_HRDATA, ROM_HREADY, ROM_HRESP, ROM_HTRANS, ROM_HWRITE, APB_PADDR, APB_PENABLE, APB_PRDATA, APB_PREADY, APB_PSEL, APB_PWDATA, APB_PWRITE, APB_PSLVERR +, APB_PPROT, APB_PSTRB, EXTS_HRDATA, EXTS_HREADYIN, EXTS_HRESP, EXTS_HADDR, EXTS_HBURST, EXTS_HPROT, EXTS_HSEL, EXTS_HSIZE, EXTS_HTRANS, EXTS_HWDATA, EXTS_HWRITE, EXTM_HADDR, EXTM_HBURST, EXTM_HPROT, EXTM_HRDATA, EXTM_HREADY, EXTM_HREADYOUT, EXTM_HRESP, EXTM_HSEL +, EXTM_HSIZE, EXTM_HTRANS, EXTM_HWDATA, EXTM_HWRITE, DDR_HADDR, DDR_HBURST, DDR_HPROT, DDR_HRDATA, DDR_HREADY, DDR_HRESP, DDR_HSIZE, DDR_HTRANS, DDR_HWDATA, DDR_HWRITE, TMS_IN, TRST_IN, TDI_IN, TDO_OUT, TDO_OE, SPI2_HOLDN_IN, SPI2_WPN_IN +, SPI2_CLK_IN, SPI2_CSN_IN, SPI2_MISO_IN, SPI2_MOSI_IN, SPI2_HOLDN_OUT, SPI2_HOLDN_OE, SPI2_WPN_OUT, SPI2_WPN_OE, SPI2_CLK_OUT, SPI2_CLK_OE, SPI2_CSN_OUT, SPI2_CSN_OE, SPI2_MISO_OUT, SPI2_MISO_OE, SPI2_MOSI_OUT, SPI2_MOSI_OE, I2C_SCL_IN, I2C_SDA_IN, I2C_SCL, I2C_SDA, UART1_TXD +, UART1_RTSN, UART1_RXD, UART1_CTSN, UART1_DSRN, UART1_DCDN, UART1_RIN, UART1_DTRN, UART1_OUT1N, UART1_OUT2N, UART2_TXD, UART2_RTSN, UART2_RXD, UART2_CTSN, UART2_DCDN, UART2_DSRN, UART2_RIN, UART2_DTRN, UART2_OUT1N, UART2_OUT2N, CH0_PWM, CH0_PWMOE +, CH1_PWM, CH1_PWMOE, CH2_PWM, CH2_PWMOE, CH3_PWM, CH3_PWMOE, GPIO_IN, GPIO_OE, GPIO_OUT, SCAN_IN, INTEG_TCK, INTEG_TDI, INTEG_TMS, INTEG_TRST, INTEG_TDO, SCAN_OUT, PGEN_CHAIN_I, PRDYN_CHAIN_O, EMA, EMAW, EMAS +, RET1N, RET2N); input POR_N; input HW_RSTN; input CORE_CLK; @@ -1614,7 +1628,8 @@ input RET1N; input RET2N; endmodule -module AE350_RAM (...); +module AE350_RAM(POR_N, HW_RSTN, CORE_CLK, AHB_CLK, APB_CLK, RTC_CLK, CORE_CE, AXI_CE, AHB_CE, EXTM_HADDR, EXTM_HBURST, EXTM_HPROT, EXTM_HRDATA, EXTM_HREADY, EXTM_HREADYOUT, EXTM_HRESP, EXTM_HSEL, EXTM_HSIZE, EXTM_HTRANS, EXTM_HWDATA, EXTM_HWRITE +, EMA, EMAW, EMAS, RET1N, RET2N); input POR_N; input HW_RSTN; input CORE_CLK; @@ -1643,20 +1658,20 @@ input RET1N; input RET2N; endmodule -module SAMB (...); +module SAMB(SPIAD, LOAD, ADWSEL); parameter MODE = 2'b00; input [23:0] SPIAD; input LOAD; input ADWSEL; endmodule -module OTP (...); +module OTP(CLK, READ, SHIFT, DOUT); parameter MODE = 2'b01; input CLK, READ, SHIFT; output DOUT; endmodule -module CMSER (...); +module CMSER(RUNNING, CRCERR, CRCDONE, ECCCORR, ECCUNCORR, ERRLOC, ECCDEC, DSRRD, DSRWR, ASRRESET, ASRINC, REFCLK, CLK, SEREN, ERRINJECT, ERRINJLOC); output RUNNING; output CRCERR; output CRCDONE; @@ -1675,7 +1690,7 @@ input ERRINJECT; input [6:0] ERRINJLOC; endmodule -module CMSERA (...); +module CMSERA(RUNNING, CRCERR, CRCDONE, ECCCORR, ECCUNCORR, ERR0LOC, ERR1LOC, ECCDEC, DSRRD, DSRWR, ASRRESET, ASRINC, REFCLK, CLK, SEREN, ERR0INJECT, ERR1INJECT, ERRINJ0LOC, ERRINJ1LOC); output RUNNING; output CRCERR; output CRCDONE; @@ -1695,7 +1710,7 @@ input ERR0INJECT,ERR1INJECT; input [6:0] ERRINJ0LOC,ERRINJ1LOC; endmodule -module CMSERB (...); +module CMSERB(RUNNING, CRCERR, CRCDONE, ECCCORR, ECCUNCORR, ERRLOC, ECCDEC, DSRRD, DSRWR, ASRRESET, ASRINC, REFCLK, CLK, SEREN, ERR0INJECT, ERR1INJECT, ERRINJ0LOC, ERRINJ1LOC); output RUNNING; output CRCERR; output CRCDONE; @@ -1714,13 +1729,13 @@ input ERR0INJECT,ERR1INJECT; input [6:0] ERRINJ0LOC,ERRINJ1LOC; endmodule -module SAMBA (...); +module SAMBA(SPIAD, LOAD); parameter MODE = 2'b00; input SPIAD; input LOAD; endmodule -module LICD (...); +module LICD(); parameter STAGE_NUM = 2'b00; parameter ENCDEC_NUM = 2'b00; parameter CODE_WIDTH = 2'b00; @@ -1728,7 +1743,13 @@ module LICD (...); parameter INTERLEAVE_MODE = 3'b000; endmodule -module MIPI_DPHY (...); +module MIPI_DPHY(RX_CLK_O, TX_CLK_O, D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD, D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD, D3LN_HSRXD_VLD, D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN, DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N +, DI_LPRX3_P, DI_LPRXCK_N, DI_LPRXCK_P, CK_N, CK_P, D0_N, D0_P, D1_N, D1_P, D2_N, D2_P, D3_N, D3_P, HSRX_STOP, HSTXEN_LN0, HSTXEN_LN1, HSTXEN_LN2, HSTXEN_LN3, HSTXEN_LNCK, LPTXEN_LN0, LPTXEN_LN1 +, LPTXEN_LN2, LPTXEN_LN3, LPTXEN_LNCK, PWRON_RX, PWRON_TX, RESET, RX_CLK_1X, TX_CLK_1X, TXDPEN_LN0, TXDPEN_LN1, TXDPEN_LN2, TXDPEN_LN3, TXDPEN_LNCK, TXHCLK_EN, CKLN_HSTXD, D0LN_HSTXD, D1LN_HSTXD, D2LN_HSTXD, D3LN_HSTXD, HSTXD_VLD, CK0 +, CK90, CK180, CK270, DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P, HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK, HSRX_ODTEN_D0, HSRX_ODTEN_D1 +, HSRX_ODTEN_D2, HSRX_ODTEN_D3, LPRX_EN_CK, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3, RX_DRST_N, TX_DRST_N, WALIGN_DVLD, MRDATA, MA_INC, MCLK, MOPCODE, MWDATA, ALPEDO_LANE0, ALPEDO_LANE1, ALPEDO_LANE2, ALPEDO_LANE3, ALPEDO_LANECK, D1LN_DESKEW_DONE +, D2LN_DESKEW_DONE, D3LN_DESKEW_DONE, D0LN_DESKEW_DONE, D1LN_DESKEW_ERROR, D2LN_DESKEW_ERROR, D3LN_DESKEW_ERROR, D0LN_DESKEW_ERROR, D0LN_DESKEW_REQ, D1LN_DESKEW_REQ, D2LN_DESKEW_REQ, D3LN_DESKEW_REQ, HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1, HSRX_DLYDIR_LANE2, HSRX_DLYDIR_LANE3, HSRX_DLYDIR_LANECK, HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1, HSRX_DLYLDN_LANE2, HSRX_DLYLDN_LANE3, HSRX_DLYLDN_LANECK +, HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1, HSRX_DLYMV_LANE2, HSRX_DLYMV_LANE3, HSRX_DLYMV_LANECK, ALP_EDEN_LANE0, ALP_EDEN_LANE1, ALP_EDEN_LANE2, ALP_EDEN_LANE3, ALP_EDEN_LANECK, ALPEN_LN0, ALPEN_LN1, ALPEN_LN2, ALPEN_LN3, ALPEN_LNCK); output RX_CLK_O, TX_CLK_O; output [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD; output D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD; @@ -2024,7 +2045,13 @@ parameter TEST_P_IMP_LN3 = 1'b0 ; parameter TEST_P_IMP_LNCK = 1'b0 ; endmodule -module MIPI_DPHYA (...); +module MIPI_DPHYA(RX_CLK_O, TX_CLK_O, D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD, D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD, D3LN_HSRXD_VLD, D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN, DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N +, DI_LPRX3_P, DI_LPRXCK_N, DI_LPRXCK_P, CK_N, CK_P, D0_N, D0_P, D1_N, D1_P, D2_N, D2_P, D3_N, D3_P, HSRX_STOP, HSTXEN_LN0, HSTXEN_LN1, HSTXEN_LN2, HSTXEN_LN3, HSTXEN_LNCK, LPTXEN_LN0, LPTXEN_LN1 +, LPTXEN_LN2, LPTXEN_LN3, LPTXEN_LNCK, PWRON_RX, PWRON_TX, RESET, RX_CLK_1X, TX_CLK_1X, TXDPEN_LN0, TXDPEN_LN1, TXDPEN_LN2, TXDPEN_LN3, TXDPEN_LNCK, TXHCLK_EN, CKLN_HSTXD, D0LN_HSTXD, D1LN_HSTXD, D2LN_HSTXD, D3LN_HSTXD, HSTXD_VLD, CK0 +, CK90, CK180, CK270, DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P, HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK, HSRX_ODTEN_D0, HSRX_ODTEN_D1 +, HSRX_ODTEN_D2, HSRX_ODTEN_D3, LPRX_EN_CK, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3, RX_DRST_N, TX_DRST_N, WALIGN_DVLD, MRDATA, MA_INC, MCLK, MOPCODE, MWDATA, SPLL_CKN, SPLL_CKP, ALPEDO_LANE0, ALPEDO_LANE1, ALPEDO_LANE2, ALPEDO_LANE3 +, ALPEDO_LANECK, D1LN_DESKEW_DONE, D2LN_DESKEW_DONE, D3LN_DESKEW_DONE, D0LN_DESKEW_DONE, D1LN_DESKEW_ERROR, D2LN_DESKEW_ERROR, D3LN_DESKEW_ERROR, D0LN_DESKEW_ERROR, D0LN_DESKEW_REQ, D1LN_DESKEW_REQ, D2LN_DESKEW_REQ, D3LN_DESKEW_REQ, HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1, HSRX_DLYDIR_LANE2, HSRX_DLYDIR_LANE3, HSRX_DLYDIR_LANECK, HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1, HSRX_DLYLDN_LANE2 +, HSRX_DLYLDN_LANE3, HSRX_DLYLDN_LANECK, HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1, HSRX_DLYMV_LANE2, HSRX_DLYMV_LANE3, HSRX_DLYMV_LANECK, ALP_EDEN_LANE0, ALP_EDEN_LANE1, ALP_EDEN_LANE2, ALP_EDEN_LANE3, ALP_EDEN_LANECK, ALPEN_LN0, ALPEN_LN1, ALPEN_LN2, ALPEN_LN3, ALPEN_LNCK); output RX_CLK_O, TX_CLK_O; output [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD; output D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD; @@ -2323,7 +2350,12 @@ parameter TEST_P_IMP_LN3 = 1'b0 ; parameter TEST_P_IMP_LNCK = 1'b0 ; endmodule -module MIPI_CPHY (...); +module MIPI_CPHY(D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD, D0LN_HSRX_DEMAP_INVLD, D1LN_HSRX_DEMAP_INVLD, D2LN_HSRX_DEMAP_INVLD, D0LN_HSRX_FIFO_RDE_ERR, D0LN_HSRX_FIFO_WRF_ERR, D1LN_HSRX_FIFO_RDE_ERR, D1LN_HSRX_FIFO_WRF_ERR, D2LN_HSRX_FIFO_RDE_ERR, D2LN_HSRX_FIFO_WRF_ERR, D0LN_HSRX_WA, D1LN_HSRX_WA, D2LN_HSRX_WA, D0LN_RX_CLK_1X_O, D1LN_RX_CLK_1X_O, D2LN_RX_CLK_1X_O +, HSTX_FIFO_AE, HSTX_FIFO_AF, HSTX_FIFO_RDE_ERR, HSTX_FIFO_WRF_ERR, RX_CLK_MUXED, TX_CLK_1X_O, DI_LPRX0_A, DI_LPRX0_B, DI_LPRX0_C, DI_LPRX1_A, DI_LPRX1_B, DI_LPRX1_C, DI_LPRX2_A, DI_LPRX2_B, DI_LPRX2_C, MDRP_RDATA, D0A, D0B, D0C, D1A, D1B +, D1C, D2A, D2B, D2C, D0LN_HSRX_EN, D0LN_HSTX_EN, D1LN_HSRX_EN, D1LN_HSTX_EN, D2LN_HSRX_EN, D2LN_HSTX_EN, D0LN_HSTX_DATA, D1LN_HSTX_DATA, D2LN_HSTX_DATA, D0LN_HSTX_DATA_VLD, D1LN_HSTX_DATA_VLD, D2LN_HSTX_DATA_VLD, D0LN_HSTX_MAP_DIS, D1LN_HSTX_MAP_DIS, D2LN_HSTX_MAP_DIS, D0LN_RX_CLK_1X_I, D1LN_RX_CLK_1X_I +, D2LN_RX_CLK_1X_I, D0LN_RX_DRST_N, D0LN_TX_DRST_N, D1LN_RX_DRST_N, D1LN_TX_DRST_N, D2LN_RX_DRST_N, D2LN_TX_DRST_N, HSTX_ENLN0, HSTX_ENLN1, HSTX_ENLN2, LPTX_ENLN0, LPTX_ENLN1, LPTX_ENLN2, MDRP_A_D_I, MDRP_A_INC_I, MDRP_CLK_I, MDRP_OPCODE_I, PWRON_RX_LN0, PWRON_RX_LN1, PWRON_RX_LN2, PWRON_TX +, ARST_RXLN0, ARST_RXLN1, ARST_RXLN2, ARSTN_TX, RX_CLK_EN_LN0, RX_CLK_EN_LN1, RX_CLK_EN_LN2, TX_CLK_1X_I, TXDP_ENLN0, TXDP_ENLN1, TXDP_ENLN2, TXHCLK_EN, DO_LPTX_A_LN0, DO_LPTX_A_LN1, DO_LPTX_A_LN2, DO_LPTX_B_LN0, DO_LPTX_B_LN1, DO_LPTX_B_LN2, DO_LPTX_C_LN0, DO_LPTX_C_LN1, DO_LPTX_C_LN2 +, GPLL_CK0, GPLL_CK90, GPLL_CK180, GPLL_CK270, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_ODT_EN_D0, HSRX_ODT_EN_D1, HSRX_ODT_EN_D2, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, SPLL0_CKN, SPLL0_CKP, SPLL1_CKN, SPLL1_CKP); output [41:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD; output D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD; output [1:0] D0LN_HSRX_DEMAP_INVLD, D1LN_HSRX_DEMAP_INVLD, D2LN_HSRX_DEMAP_INVLD; @@ -2455,29 +2487,30 @@ parameter EQ_PBIAS_LN2 = 4'b0100; parameter EQ_ZLD_LN2 = 4'b1000; endmodule -module GTR12_QUAD (...); +module GTR12_QUAD(); parameter POSITION = "Q0"; endmodule -module GTR12_UPAR (...); +module GTR12_UPAR(); endmodule -module GTR12_PMAC (...); +module GTR12_PMAC(); endmodule -module GTR12_QUADA (...); +module GTR12_QUADA(); endmodule -module GTR12_UPARA (...); +module GTR12_UPARA(); endmodule -module GTR12_PMACA (...); +module GTR12_PMACA(); endmodule -module GTR12_QUADB (...); +module GTR12_QUADB(); endmodule -module DQS (...); +module DQS(DQSIN, PCLK, FCLK, RESET, READ, RCLKSEL, DLLSTEP, WSTEP, RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD, DQSR90, DQSW0, DQSW270, RPOINT, WPOINT, RVALID +, RBURST, RFLAG, WFLAG); input DQSIN,PCLK,FCLK,RESET; input [3:0] READ; input [2:0] RCLKSEL; diff --git a/techlibs/lattice/cells_bb_ecp5.v b/techlibs/lattice/cells_bb_ecp5.v index 1b1b9a1f4..61f3da502 100644 --- a/techlibs/lattice/cells_bb_ecp5.v +++ b/techlibs/lattice/cells_bb_ecp5.v @@ -1,24 +1,29 @@ // Created by cells_xtra.py from Lattice models (* blackbox *) (* keep *) -module GSR (...); +module GSR(GSR); input GSR; endmodule (* blackbox *) -module PUR (...); +module PUR(PUR); parameter RST_PULSE = 1; input PUR; endmodule (* blackbox *) (* keep *) -module SGSR (...); +module SGSR(GSR, CLK); input GSR; input CLK; endmodule (* blackbox *) -module PDPW16KD (...); +module PDPW16KD(DI35, DI34, DI33, DI32, DI31, DI30, DI29, DI28, DI27, DI26, DI25, DI24, DI23, DI22, DI21, DI20, DI19, DI18, DI17, DI16, DI15 +, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, ADW8, ADW7, ADW6, ADW5, ADW4, ADW3 +, ADW2, ADW1, ADW0, BE3, BE2, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0, ADR13, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5 +, ADR4, ADR3, ADR2, ADR1, ADR0, CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, DO35, DO34, DO33, DO32, DO31, DO30, DO29, DO28, DO27 +, DO26, DO25, DO24, DO23, DO22, DO21, DO20, DO19, DO18, DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6 +, DO5, DO4, DO3, DO2, DO1, DO0); parameter CLKRMUX = "CLKR"; parameter CLKWMUX = "CLKW"; parameter DATA_WIDTH_W = 36; @@ -208,7 +213,18 @@ module PDPW16KD (...); endmodule (* blackbox *) -module MULT18X18D (...); +module MULT18X18D(A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0, B17, B16, B15 +, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0, C17, C16, C15, C14, C13, C12 +, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0, SIGNEDA, SIGNEDB, SOURCEA, SOURCEB, CLK3, CLK2, CLK1, CLK0, CE3 +, CE2, CE1, CE0, RST3, RST2, RST1, RST0, SRIA17, SRIA16, SRIA15, SRIA14, SRIA13, SRIA12, SRIA11, SRIA10, SRIA9, SRIA8, SRIA7, SRIA6, SRIA5, SRIA4 +, SRIA3, SRIA2, SRIA1, SRIA0, SRIB17, SRIB16, SRIB15, SRIB14, SRIB13, SRIB12, SRIB11, SRIB10, SRIB9, SRIB8, SRIB7, SRIB6, SRIB5, SRIB4, SRIB3, SRIB2, SRIB1 +, SRIB0, SROA17, SROA16, SROA15, SROA14, SROA13, SROA12, SROA11, SROA10, SROA9, SROA8, SROA7, SROA6, SROA5, SROA4, SROA3, SROA2, SROA1, SROA0, SROB17, SROB16 +, SROB15, SROB14, SROB13, SROB12, SROB11, SROB10, SROB9, SROB8, SROB7, SROB6, SROB5, SROB4, SROB3, SROB2, SROB1, SROB0, ROA17, ROA16, ROA15, ROA14, ROA13 +, ROA12, ROA11, ROA10, ROA9, ROA8, ROA7, ROA6, ROA5, ROA4, ROA3, ROA2, ROA1, ROA0, ROB17, ROB16, ROB15, ROB14, ROB13, ROB12, ROB11, ROB10 +, ROB9, ROB8, ROB7, ROB6, ROB5, ROB4, ROB3, ROB2, ROB1, ROB0, ROC17, ROC16, ROC15, ROC14, ROC13, ROC12, ROC11, ROC10, ROC9, ROC8, ROC7 +, ROC6, ROC5, ROC4, ROC3, ROC2, ROC1, ROC0, P35, P34, P33, P32, P31, P30, P29, P28, P27, P26, P25, P24, P23, P22 +, P21, P20, P19, P18, P17, P16, P15, P14, P13, P12, P11, P10, P9, P8, P7, P6, P5, P4, P3, P2, P1 +, P0, SIGNEDP); parameter REG_INPUTA_CLK = "NONE"; parameter REG_INPUTA_CE = "CE0"; parameter REG_INPUTA_RST = "RST0"; @@ -470,7 +486,28 @@ module MULT18X18D (...); endmodule (* blackbox *) -module ALU54B (...); +module ALU54B(CE3, CE2, CE1, CE0, CLK3, CLK2, CLK1, CLK0, RST3, RST2, RST1, RST0, SIGNEDIA, SIGNEDIB, SIGNEDCIN, A35, A34, A33, A32, A31, A30 +, A29, A28, A27, A26, A25, A24, A23, A22, A21, A20, A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9 +, A8, A7, A6, A5, A4, A3, A2, A1, A0, B35, B34, B33, B32, B31, B30, B29, B28, B27, B26, B25, B24 +, B23, B22, B21, B20, B19, B18, B17, B16, B15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3 +, B2, B1, B0, C53, C52, C51, C50, C49, C48, C47, C46, C45, C44, C43, C42, C41, C40, C39, C38, C37, C36 +, C35, C34, C33, C32, C31, C30, C29, C28, C27, C26, C25, C24, C23, C22, C21, C20, C19, C18, C17, C16, C15 +, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0, CFB53, CFB52, CFB51, CFB50, CFB49, CFB48 +, CFB47, CFB46, CFB45, CFB44, CFB43, CFB42, CFB41, CFB40, CFB39, CFB38, CFB37, CFB36, CFB35, CFB34, CFB33, CFB32, CFB31, CFB30, CFB29, CFB28, CFB27 +, CFB26, CFB25, CFB24, CFB23, CFB22, CFB21, CFB20, CFB19, CFB18, CFB17, CFB16, CFB15, CFB14, CFB13, CFB12, CFB11, CFB10, CFB9, CFB8, CFB7, CFB6 +, CFB5, CFB4, CFB3, CFB2, CFB1, CFB0, MA35, MA34, MA33, MA32, MA31, MA30, MA29, MA28, MA27, MA26, MA25, MA24, MA23, MA22, MA21 +, MA20, MA19, MA18, MA17, MA16, MA15, MA14, MA13, MA12, MA11, MA10, MA9, MA8, MA7, MA6, MA5, MA4, MA3, MA2, MA1, MA0 +, MB35, MB34, MB33, MB32, MB31, MB30, MB29, MB28, MB27, MB26, MB25, MB24, MB23, MB22, MB21, MB20, MB19, MB18, MB17, MB16, MB15 +, MB14, MB13, MB12, MB11, MB10, MB9, MB8, MB7, MB6, MB5, MB4, MB3, MB2, MB1, MB0, CIN53, CIN52, CIN51, CIN50, CIN49, CIN48 +, CIN47, CIN46, CIN45, CIN44, CIN43, CIN42, CIN41, CIN40, CIN39, CIN38, CIN37, CIN36, CIN35, CIN34, CIN33, CIN32, CIN31, CIN30, CIN29, CIN28, CIN27 +, CIN26, CIN25, CIN24, CIN23, CIN22, CIN21, CIN20, CIN19, CIN18, CIN17, CIN16, CIN15, CIN14, CIN13, CIN12, CIN11, CIN10, CIN9, CIN8, CIN7, CIN6 +, CIN5, CIN4, CIN3, CIN2, CIN1, CIN0, OP10, OP9, OP8, OP7, OP6, OP5, OP4, OP3, OP2, OP1, OP0, R53, R52, R51, R50 +, R49, R48, R47, R46, R45, R44, R43, R42, R41, R40, R39, R38, R37, R36, R35, R34, R33, R32, R31, R30, R29 +, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17, R16, R15, R14, R13, R12, R11, R10, R9, R8 +, R7, R6, R5, R4, R3, R2, R1, R0, CO53, CO52, CO51, CO50, CO49, CO48, CO47, CO46, CO45, CO44, CO43, CO42, CO41 +, CO40, CO39, CO38, CO37, CO36, CO35, CO34, CO33, CO32, CO31, CO30, CO29, CO28, CO27, CO26, CO25, CO24, CO23, CO22, CO21, CO20 +, CO19, CO18, CO17, CO16, CO15, CO14, CO13, CO12, CO11, CO10, CO9, CO8, CO7, CO6, CO5, CO4, CO3, CO2, CO1, CO0, EQZ +, EQZM, EQOM, EQPAT, EQPATB, OVER, UNDER, OVERUNDER, SIGNEDR); parameter REG_INPUTC0_CLK = "NONE"; parameter REG_INPUTC0_CE = "CE0"; parameter REG_INPUTC0_RST = "RST0"; @@ -970,7 +1007,7 @@ module ALU54B (...); endmodule (* blackbox *) -module CLKDIVF (...); +module CLKDIVF(CLKI, RST, ALIGNWD, CDIVX); parameter GSR = "DISABLED"; parameter DIV = "2.0"; input CLKI; @@ -980,7 +1017,7 @@ module CLKDIVF (...); endmodule (* blackbox *) -module PCSCLKDIV (...); +module PCSCLKDIV(CLKI, RST, SEL2, SEL1, SEL0, CDIV1, CDIVX); parameter GSR = "DISABLED"; input CLKI; input RST; @@ -992,7 +1029,7 @@ module PCSCLKDIV (...); endmodule (* blackbox *) -module DCSC (...); +module DCSC(CLK1, CLK0, SEL1, SEL0, MODESEL, DCSOUT); parameter DCSMODE = "POS"; input CLK1; input CLK0; @@ -1003,21 +1040,21 @@ module DCSC (...); endmodule (* blackbox *) -module DCCA (...); +module DCCA(CLKI, CE, CLKO); input CLKI; input CE; output CLKO; endmodule (* blackbox *) -module ECLKSYNCB (...); +module ECLKSYNCB(ECLKI, STOP, ECLKO); input ECLKI; input STOP; output ECLKO; endmodule (* blackbox *) -module ECLKBRIDGECS (...); +module ECLKBRIDGECS(CLK0, CLK1, SEL, ECSOUT); input CLK0; input CLK1; input SEL; @@ -1025,7 +1062,7 @@ module ECLKBRIDGECS (...); endmodule (* blackbox *) -module DELAYF (...); +module DELAYF(A, LOADN, MOVE, DIRECTION, Z, CFLAG); parameter DEL_MODE = "USER_DEFINED"; parameter DEL_VALUE = 0; input A; @@ -1037,7 +1074,7 @@ module DELAYF (...); endmodule (* blackbox *) -module DELAYG (...); +module DELAYG(A, Z); parameter DEL_MODE = "USER_DEFINED"; parameter DEL_VALUE = 0; input A; @@ -1045,13 +1082,14 @@ module DELAYG (...); endmodule (* blackbox *) (* keep *) -module USRMCLK (...); +module USRMCLK(USRMCLKI, USRMCLKTS); input USRMCLKI; input USRMCLKTS; endmodule (* blackbox *) -module DQSBUFM (...); +module DQSBUFM(DQSI, READ1, READ0, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL, ECLK, SCLK, RST, DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4, DYNDELAY3, DYNDELAY2, DYNDELAY1, DYNDELAY0, PAUSE, RDLOADN, RDMOVE +, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, DQSR90, DQSW, DQSW270, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, DATAVALID, BURSTDET, RDCFLAG, WRCFLAG); parameter DQS_LI_DEL_VAL = 4; parameter DQS_LI_DEL_ADJ = "FACTORYONLY"; parameter DQS_LO_DEL_VAL = 0; @@ -1098,7 +1136,7 @@ module DQSBUFM (...); endmodule (* blackbox *) -module DDRDLLA (...); +module DDRDLLA(CLK, RST, UDDCNTLN, FREEZE, DDRDEL, LOCK, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1, DCNTL0); parameter FORCE_MAX_DELAY = "NO"; parameter GSR = "ENABLED"; input CLK; @@ -1118,7 +1156,7 @@ module DDRDLLA (...); endmodule (* blackbox *) -module DLLDELD (...); +module DLLDELD(A, DDRDEL, LOADN, MOVE, DIRECTION, Z, CFLAG); input A; input DDRDEL; input LOADN; @@ -1129,7 +1167,7 @@ module DLLDELD (...); endmodule (* blackbox *) -module IDDRX1F (...); +module IDDRX1F(D, SCLK, RST, Q0, Q1); parameter GSR = "ENABLED"; input D; input SCLK; @@ -1139,7 +1177,7 @@ module IDDRX1F (...); endmodule (* blackbox *) -module IDDRX2F (...); +module IDDRX2F(D, SCLK, ECLK, RST, ALIGNWD, Q3, Q2, Q1, Q0); parameter GSR = "ENABLED"; input D; input SCLK; @@ -1153,7 +1191,7 @@ module IDDRX2F (...); endmodule (* blackbox *) -module IDDR71B (...); +module IDDR71B(D, SCLK, ECLK, RST, ALIGNWD, Q6, Q5, Q4, Q3, Q2, Q1, Q0); parameter GSR = "ENABLED"; input D; input SCLK; @@ -1170,7 +1208,7 @@ module IDDR71B (...); endmodule (* blackbox *) -module IDDRX2DQA (...); +module IDDRX2DQA(SCLK, ECLK, DQSR90, D, RST, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, Q3, Q2, Q1, Q0, QWL); parameter GSR = "ENABLED"; input SCLK; input ECLK; @@ -1191,7 +1229,7 @@ module IDDRX2DQA (...); endmodule (* blackbox *) -module ODDRX1F (...); +module ODDRX1F(SCLK, RST, D0, D1, Q); parameter GSR = "ENABLED"; input SCLK; input RST; @@ -1201,7 +1239,7 @@ module ODDRX1F (...); endmodule (* blackbox *) -module ODDRX2F (...); +module ODDRX2F(SCLK, ECLK, RST, D3, D2, D1, D0, Q); parameter GSR = "ENABLED"; input SCLK; input ECLK; @@ -1214,7 +1252,7 @@ module ODDRX2F (...); endmodule (* blackbox *) -module ODDR71B (...); +module ODDR71B(SCLK, ECLK, RST, D6, D5, D4, D3, D2, D1, D0, Q); parameter GSR = "ENABLED"; input SCLK; input ECLK; @@ -1230,7 +1268,7 @@ module ODDR71B (...); endmodule (* blackbox *) -module OSHX2A (...); +module OSHX2A(D1, D0, SCLK, ECLK, RST, Q); parameter GSR = "ENABLED"; input D1; input D0; @@ -1241,7 +1279,7 @@ module OSHX2A (...); endmodule (* blackbox *) -module TSHX2DQA (...); +module TSHX2DQA(T1, T0, SCLK, ECLK, DQSW270, RST, Q); parameter GSR = "ENABLED"; parameter REGSET = "SET"; input T1; @@ -1254,7 +1292,7 @@ module TSHX2DQA (...); endmodule (* blackbox *) -module TSHX2DQSA (...); +module TSHX2DQSA(T1, T0, SCLK, ECLK, DQSW, RST, Q); parameter GSR = "ENABLED"; parameter REGSET = "SET"; input T1; @@ -1267,7 +1305,7 @@ module TSHX2DQSA (...); endmodule (* blackbox *) -module ODDRX2DQA (...); +module ODDRX2DQA(D3, D2, D1, D0, DQSW270, SCLK, ECLK, RST, Q); parameter GSR = "ENABLED"; input D3; input D2; @@ -1281,7 +1319,7 @@ module ODDRX2DQA (...); endmodule (* blackbox *) -module ODDRX2DQSB (...); +module ODDRX2DQSB(D3, D2, D1, D0, SCLK, ECLK, DQSW, RST, Q); parameter GSR = "ENABLED"; input D3; input D2; @@ -1295,7 +1333,8 @@ module ODDRX2DQSB (...); endmodule (* blackbox *) -module EHXPLLL (...); +module EHXPLLL(CLKI, CLKFB, PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, PHASELOADREG, STDBY, PLLWAKESYNC, RST, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK +, CLKINTFB); parameter CLKI_DIV = 1; parameter CLKFB_DIV = 1; parameter CLKOP_DIV = 8; @@ -1357,7 +1396,7 @@ module EHXPLLL (...); endmodule (* blackbox *) -module DTR (...); +module DTR(STARTPULSE, DTROUT7, DTROUT6, DTROUT5, DTROUT4, DTROUT3, DTROUT2, DTROUT1, DTROUT0); parameter DTR_TEMP = 25; input STARTPULSE; output DTROUT7; @@ -1371,13 +1410,13 @@ module DTR (...); endmodule (* blackbox *) -module OSCG (...); +module OSCG(OSC); parameter DIV = 128; output OSC; endmodule (* blackbox *) -module EXTREFB (...); +module EXTREFB(REFCLKP, REFCLKN, REFCLKO); parameter REFCK_PWDNB = "DONTCARE"; parameter REFCK_RTERM = "DONTCARE"; parameter REFCK_DCBIAS_EN = "DONTCARE"; @@ -1389,7 +1428,7 @@ module EXTREFB (...); endmodule (* blackbox *) (* keep *) -module JTAGG (...); +module JTAGG(TCK, TMS, TDI, JTDO2, JTDO1, TDO, JTDI, JTCK, JRTI2, JRTI1, JSHIFT, JUPDATE, JRSTN, JCE2, JCE1); parameter ER1 = "ENABLED"; parameter ER2 = "ENABLED"; (* iopad_external_pin *) @@ -1414,7 +1453,20 @@ module JTAGG (...); endmodule (* blackbox *) (* keep *) -module DCUA (...); +module DCUA(CH0_HDINP, CH1_HDINP, CH0_HDINN, CH1_HDINN, D_TXBIT_CLKP_FROM_ND, D_TXBIT_CLKN_FROM_ND, D_SYNC_ND, D_TXPLL_LOL_FROM_ND, CH0_RX_REFCLK, CH1_RX_REFCLK, CH0_FF_RXI_CLK, CH1_FF_RXI_CLK, CH0_FF_TXI_CLK, CH1_FF_TXI_CLK, CH0_FF_EBRD_CLK, CH1_FF_EBRD_CLK, CH0_FF_TX_D_0, CH1_FF_TX_D_0, CH0_FF_TX_D_1, CH1_FF_TX_D_1, CH0_FF_TX_D_2 +, CH1_FF_TX_D_2, CH0_FF_TX_D_3, CH1_FF_TX_D_3, CH0_FF_TX_D_4, CH1_FF_TX_D_4, CH0_FF_TX_D_5, CH1_FF_TX_D_5, CH0_FF_TX_D_6, CH1_FF_TX_D_6, CH0_FF_TX_D_7, CH1_FF_TX_D_7, CH0_FF_TX_D_8, CH1_FF_TX_D_8, CH0_FF_TX_D_9, CH1_FF_TX_D_9, CH0_FF_TX_D_10, CH1_FF_TX_D_10, CH0_FF_TX_D_11, CH1_FF_TX_D_11, CH0_FF_TX_D_12, CH1_FF_TX_D_12 +, CH0_FF_TX_D_13, CH1_FF_TX_D_13, CH0_FF_TX_D_14, CH1_FF_TX_D_14, CH0_FF_TX_D_15, CH1_FF_TX_D_15, CH0_FF_TX_D_16, CH1_FF_TX_D_16, CH0_FF_TX_D_17, CH1_FF_TX_D_17, CH0_FF_TX_D_18, CH1_FF_TX_D_18, CH0_FF_TX_D_19, CH1_FF_TX_D_19, CH0_FF_TX_D_20, CH1_FF_TX_D_20, CH0_FF_TX_D_21, CH1_FF_TX_D_21, CH0_FF_TX_D_22, CH1_FF_TX_D_22, CH0_FF_TX_D_23 +, CH1_FF_TX_D_23, CH0_FFC_EI_EN, CH1_FFC_EI_EN, CH0_FFC_PCIE_DET_EN, CH1_FFC_PCIE_DET_EN, CH0_FFC_PCIE_CT, CH1_FFC_PCIE_CT, CH0_FFC_SB_INV_RX, CH1_FFC_SB_INV_RX, CH0_FFC_ENABLE_CGALIGN, CH1_FFC_ENABLE_CGALIGN, CH0_FFC_SIGNAL_DETECT, CH1_FFC_SIGNAL_DETECT, CH0_FFC_FB_LOOPBACK, CH1_FFC_FB_LOOPBACK, CH0_FFC_SB_PFIFO_LP, CH1_FFC_SB_PFIFO_LP, CH0_FFC_PFIFO_CLR, CH1_FFC_PFIFO_CLR, CH0_FFC_RATE_MODE_RX, CH1_FFC_RATE_MODE_RX +, CH0_FFC_RATE_MODE_TX, CH1_FFC_RATE_MODE_TX, CH0_FFC_DIV11_MODE_RX, CH1_FFC_DIV11_MODE_RX, CH0_FFC_RX_GEAR_MODE, CH1_FFC_RX_GEAR_MODE, CH0_FFC_TX_GEAR_MODE, CH1_FFC_TX_GEAR_MODE, CH0_FFC_DIV11_MODE_TX, CH1_FFC_DIV11_MODE_TX, CH0_FFC_LDR_CORE2TX_EN, CH1_FFC_LDR_CORE2TX_EN, CH0_FFC_LANE_TX_RST, CH1_FFC_LANE_TX_RST, CH0_FFC_LANE_RX_RST, CH1_FFC_LANE_RX_RST, CH0_FFC_RRST, CH1_FFC_RRST, CH0_FFC_TXPWDNB, CH1_FFC_TXPWDNB, CH0_FFC_RXPWDNB +, CH1_FFC_RXPWDNB, CH0_LDR_CORE2TX, CH1_LDR_CORE2TX, D_SCIWDATA0, D_SCIWDATA1, D_SCIWDATA2, D_SCIWDATA3, D_SCIWDATA4, D_SCIWDATA5, D_SCIWDATA6, D_SCIWDATA7, D_SCIADDR0, D_SCIADDR1, D_SCIADDR2, D_SCIADDR3, D_SCIADDR4, D_SCIADDR5, D_SCIENAUX, D_SCISELAUX, CH0_SCIEN, CH1_SCIEN +, CH0_SCISEL, CH1_SCISEL, D_SCIRD, D_SCIWSTN, D_CYAWSTN, D_FFC_SYNC_TOGGLE, D_FFC_DUAL_RST, D_FFC_MACRO_RST, D_FFC_MACROPDB, D_FFC_TRST, CH0_FFC_CDR_EN_BITSLIP, CH1_FFC_CDR_EN_BITSLIP, D_SCAN_ENABLE, D_SCAN_IN_0, D_SCAN_IN_1, D_SCAN_IN_2, D_SCAN_IN_3, D_SCAN_IN_4, D_SCAN_IN_5, D_SCAN_IN_6, D_SCAN_IN_7 +, D_SCAN_MODE, D_SCAN_RESET, D_CIN0, D_CIN1, D_CIN2, D_CIN3, D_CIN4, D_CIN5, D_CIN6, D_CIN7, D_CIN8, D_CIN9, D_CIN10, D_CIN11, CH0_HDOUTP, CH1_HDOUTP, CH0_HDOUTN, CH1_HDOUTN, D_TXBIT_CLKP_TO_ND, D_TXBIT_CLKN_TO_ND, D_SYNC_PULSE2ND +, D_TXPLL_LOL_TO_ND, CH0_FF_RX_F_CLK, CH1_FF_RX_F_CLK, CH0_FF_RX_H_CLK, CH1_FF_RX_H_CLK, CH0_FF_TX_F_CLK, CH1_FF_TX_F_CLK, CH0_FF_TX_H_CLK, CH1_FF_TX_H_CLK, CH0_FF_RX_PCLK, CH1_FF_RX_PCLK, CH0_FF_TX_PCLK, CH1_FF_TX_PCLK, CH0_FF_RX_D_0, CH1_FF_RX_D_0, CH0_FF_RX_D_1, CH1_FF_RX_D_1, CH0_FF_RX_D_2, CH1_FF_RX_D_2, CH0_FF_RX_D_3, CH1_FF_RX_D_3 +, CH0_FF_RX_D_4, CH1_FF_RX_D_4, CH0_FF_RX_D_5, CH1_FF_RX_D_5, CH0_FF_RX_D_6, CH1_FF_RX_D_6, CH0_FF_RX_D_7, CH1_FF_RX_D_7, CH0_FF_RX_D_8, CH1_FF_RX_D_8, CH0_FF_RX_D_9, CH1_FF_RX_D_9, CH0_FF_RX_D_10, CH1_FF_RX_D_10, CH0_FF_RX_D_11, CH1_FF_RX_D_11, CH0_FF_RX_D_12, CH1_FF_RX_D_12, CH0_FF_RX_D_13, CH1_FF_RX_D_13, CH0_FF_RX_D_14 +, CH1_FF_RX_D_14, CH0_FF_RX_D_15, CH1_FF_RX_D_15, CH0_FF_RX_D_16, CH1_FF_RX_D_16, CH0_FF_RX_D_17, CH1_FF_RX_D_17, CH0_FF_RX_D_18, CH1_FF_RX_D_18, CH0_FF_RX_D_19, CH1_FF_RX_D_19, CH0_FF_RX_D_20, CH1_FF_RX_D_20, CH0_FF_RX_D_21, CH1_FF_RX_D_21, CH0_FF_RX_D_22, CH1_FF_RX_D_22, CH0_FF_RX_D_23, CH1_FF_RX_D_23, CH0_FFS_PCIE_DONE, CH1_FFS_PCIE_DONE +, CH0_FFS_PCIE_CON, CH1_FFS_PCIE_CON, CH0_FFS_RLOS, CH1_FFS_RLOS, CH0_FFS_LS_SYNC_STATUS, CH1_FFS_LS_SYNC_STATUS, CH0_FFS_CC_UNDERRUN, CH1_FFS_CC_UNDERRUN, CH0_FFS_CC_OVERRUN, CH1_FFS_CC_OVERRUN, CH0_FFS_RXFBFIFO_ERROR, CH1_FFS_RXFBFIFO_ERROR, CH0_FFS_TXFBFIFO_ERROR, CH1_FFS_TXFBFIFO_ERROR, CH0_FFS_RLOL, CH1_FFS_RLOL, CH0_FFS_SKP_ADDED, CH1_FFS_SKP_ADDED, CH0_FFS_SKP_DELETED, CH1_FFS_SKP_DELETED, CH0_LDR_RX2CORE +, CH1_LDR_RX2CORE, D_SCIRDATA0, D_SCIRDATA1, D_SCIRDATA2, D_SCIRDATA3, D_SCIRDATA4, D_SCIRDATA5, D_SCIRDATA6, D_SCIRDATA7, D_SCIINT, D_SCAN_OUT_0, D_SCAN_OUT_1, D_SCAN_OUT_2, D_SCAN_OUT_3, D_SCAN_OUT_4, D_SCAN_OUT_5, D_SCAN_OUT_6, D_SCAN_OUT_7, D_COUT0, D_COUT1, D_COUT2 +, D_COUT3, D_COUT4, D_COUT5, D_COUT6, D_COUT7, D_COUT8, D_COUT9, D_COUT10, D_COUT11, D_COUT12, D_COUT13, D_COUT14, D_COUT15, D_COUT16, D_COUT17, D_COUT18, D_COUT19, D_REFCLKI, D_FFS_PLOL); parameter D_MACROPDB = "DONTCARE"; parameter D_IB_PWDNB = "DONTCARE"; parameter D_XGE_MODE = "DONTCARE"; diff --git a/techlibs/lattice/cells_bb_nexus.v b/techlibs/lattice/cells_bb_nexus.v index 6cf3a645d..42da827d6 100644 --- a/techlibs/lattice/cells_bb_nexus.v +++ b/techlibs/lattice/cells_bb_nexus.v @@ -1,6 +1,7 @@ // Created by cells_xtra.py from Lattice models -module ACC54 (...); +module ACC54(SFTCTRL, DSPIN, PP, CINPUT, LOAD, M9ADDSUB, ADDSUB, CIN, CASIN, CEO, RSTO, CEC, RSTC, CLK, SIGNEDI, SUM1, SUM0, DSPOUT, CASCOUT, ROUNDEN, CECIN +, CECTRL, RSTCIN, RSTCTRL); parameter SIGN = "DISABLED"; parameter M9ADDSUB_CTRL = "ADDITION"; parameter ADDSUB_CTRL = "ADD_ADD_CTRL_54_BIT_ADDER"; @@ -60,7 +61,8 @@ module ACC54 (...); input RSTCTRL; endmodule -module ADC (...); +module ADC(DN0, DN1, DP0, DP1, ADCEN, CAL, CALRDY, CHAEN, CHASEL, CHBEN, CHBSEL, CLKDCLK, CLKFAB, COG, COMP1IN, COMP1IP, COMP1OL, COMP2IN, COMP2IP, COMP2OL, COMP3IN +, COMP3IP, COMP3OL, CONVSTOP, DA, DB, EOC, GPION, GPIOP, RESETN, RSTN, SOC, COMP1O, COMP2O, COMP3O); parameter ADC_ENP = "ENABLED"; parameter CLK_DIV = "2"; parameter CTLCOMPSW1 = "DISABLED"; @@ -120,7 +122,8 @@ module ADC (...); output COMP3O; endmodule -module ALUREG (...); +module ALUREG(ALUCLK, ALUFLAGC, ALUFLAGV, ALUFLAGZ, ALUFORWARDA, ALUFORWARDB, ALUIREGEN, ALUOREGEN, ALURST, DATAA, DATAB, DATAC, OPC, OPCCUSTOM, RADDRA, RADDRB, RDATAA, RDATAB, REGCLK, REGCLKEN, REGRST +, RESULT, WADDR, WDROTATE, WDSIGNEXT, WDSIZE, WDATA, WREN); parameter ALURST_ACTIVELOW = "DISABLE"; parameter GSR = "ENABLED"; parameter INREG = "DISABLE"; @@ -163,21 +166,21 @@ module ALUREG (...); endmodule (* keep *) -module BB_ADC (...); +module BB_ADC(IOPAD, INADC); (* iopad_external_pin *) inout IOPAD; output INADC; endmodule (* keep *) -module BB_CDR (...); +module BB_CDR(IOPAD, INADC); (* iopad_external_pin *) inout IOPAD; output INADC; endmodule (* keep *) -module BB_I3C_A (...); +module BB_I3C_A(IOPAD, PADDI, PADDO, PADDT, I3CRESEN, I3CWKPU); (* iopad_external_pin *) inout IOPAD; output PADDI; @@ -187,7 +190,7 @@ module BB_I3C_A (...); input I3CWKPU; endmodule -module BFD1P3KX (...); +module BFD1P3KX(DOUT, DIN, DT, CEOUT, CLKOUT, SROUT, CEIN, CLKIN, SRIN, QOUT, QIN, QT); parameter GSR = "ENABLED"; parameter OUTSET = "RESET"; parameter INSET = "RESET"; @@ -206,7 +209,7 @@ module BFD1P3KX (...); output QT; endmodule -module BFD1P3LX (...); +module BFD1P3LX(DOUT, DIN, DT, CEOUT, CLKOUT, SROUT, CEIN, CLKIN, SRIN, QOUT, QIN, QT); parameter GSR = "ENABLED"; parameter OUTSET = "RESET"; parameter INSET = "RESET"; @@ -226,7 +229,7 @@ module BFD1P3LX (...); endmodule (* keep *) -module BNKREF18 (...); +module BNKREF18(STDBYINR, STDBYDIF, PVTCODE); parameter BANK = "0b0000"; parameter STANDBY_DIFFIO = "DISABLED"; parameter STANDBY_INR = "DISABLED"; @@ -236,7 +239,7 @@ module BNKREF18 (...); endmodule (* keep *) -module CONFIG_LMMI (...); +module CONFIG_LMMI(LMMICLK, LMMIREQUEST, LMMIWRRD_N, LMMIOFFSET, LMMIWDATA, LMMIRDATA, LMMIREADY, LMMIRDATAVALID, LMMIRESETN, RSTSMCLK, SMCLK); parameter LMMI_EN = "DIS"; input LMMICLK; input LMMIREQUEST; @@ -251,7 +254,7 @@ module CONFIG_LMMI (...); input SMCLK; endmodule -module DDRDLL (...); +module DDRDLL(CODE, FREEZE, LOCK, CLKIN, RST, DCNTL, UDDCNTL_N); parameter GSR = "ENABLED"; parameter ENA_ROUNDOFF = "ENABLED"; parameter FORCE_MAX_DELAY = "CODE_OR_LOCK_FROM_DLL_LOOP"; @@ -264,7 +267,7 @@ module DDRDLL (...); input UDDCNTL_N; endmodule -module DELAYA (...); +module DELAYA(A, LOAD_N, MOVE, DIRECTION, COARSE0, COARSE1, RANKSELECT, RANKENABLE, RANK0UPDATE, RANK1UPDATE, Z, EDETERR, CFLAG); parameter DEL_MODE = "USER_DEFINED"; parameter DEL_VALUE = "0"; parameter COARSE_DELAY_MODE = "STATIC"; @@ -286,7 +289,7 @@ module DELAYA (...); output CFLAG; endmodule -module DELAYB (...); +module DELAYB(A, Z); parameter DEL_VALUE = "0"; parameter COARSE_DELAY = "0NS"; parameter DEL_MODE = "USER_DEFINED"; @@ -295,7 +298,7 @@ module DELAYB (...); endmodule (* keep *) -module DIFFIO18 (...); +module DIFFIO18(PADDO, DOLP, IOPAD, PADDI, INLP, PADDT, INADC, HSRXEN, HSTXEN); parameter PULLMODE = "DOWN"; parameter ENADC_IN = "DISABLED"; parameter MIPI = "DISABLED"; @@ -311,7 +314,7 @@ module DIFFIO18 (...); input HSTXEN; endmodule -module DLLDEL (...); +module DLLDEL(CLKIN, CLKOUT, CODE, COUT, DIR, LOAD_N, MOVE); parameter ADJUST = "0"; parameter DEL_ADJUST = "PLUS"; parameter ENABLE = "ENABLED"; @@ -324,7 +327,12 @@ module DLLDEL (...); input MOVE; endmodule -module DP16K_MODE (...); +module DP16K_MODE(DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, DIA9, DIA10, DIA11, DIA12, DIA13, DIA14, DIA15, DIA16, DIA17, DIB0, DIB1, DIB2 +, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, DIB9, DIB10, DIB11, DIB12, DIB13, DIB14, DIB15, DIB16, DIB17, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5 +, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, ADA13, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 +, ADB13, CLKA, CLKB, CEA, CEB, WEA, WEB, CSA0, CSA1, CSA2, CSB0, CSB1, CSB2, RSTA, RSTB, DOA0, DOA1, DOA2, DOA3, DOA4, DOA5 +, DOA6, DOA7, DOA8, DOA9, DOA10, DOA11, DOA12, DOA13, DOA14, DOA15, DOA16, DOA17, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 +, DOB9, DOB10, DOB11, DOB12, DOB13, DOB14, DOB15, DOB16, DOB17); parameter DATA_WIDTH_A = "X18"; parameter DATA_WIDTH_B = "X18"; parameter OUTREG_A = "BYPASSED"; @@ -517,7 +525,7 @@ module DP16K_MODE (...); output DOB17; endmodule -module DP16K (...); +module DP16K(DIA, DIB, ADA, ADB, CLKA, CLKB, CEA, CEB, WEA, WEB, CSA, CSB, RSTA, RSTB, DOA, DOB); parameter DATA_WIDTH_A = "X18"; parameter DATA_WIDTH_B = "X18"; parameter OUTREG_A = "BYPASSED"; @@ -613,7 +621,20 @@ module DP16K (...); endmodule (* keep *) -module DPHY (...); +module DPHY(LMMICLK, LMMIRESET_N, LMMIREQUEST, LMMIWRRD_N, LMMIOFFSET, LMMIWDATA, LMMIRDATA, LMMIRDATAVALID, LMMIREADY, BITCKEXT, CKN, CKP, CLKREF, D0ACTIVE, D0BYTCNT, D0ERRCNT, D0PASS, D0VALID, D1ACTIVE, D1BYTCNT, D1ERRCNT +, D1PASS, D1VALID, D2ACTIVE, D2BYTCNT, D2ERRCNT, D2PASS, D2VALID, D3ACTIVE, D3BYTCNT, D3ERRCNT, D3PASS, D3VALID, DCTSTOUT, DN0, DN1, DN2, DN3, DP0, DP1, DP2, DP3 +, LOCK, PDDPHY, PDPLL, SCCLKIN, UDIR, UED0THEN, UERCLP0, UERCLP1, UERCTRL, UERE, UERSTHS, UERSSHS, UERSE, UFRXMODE, UTXMDTX, URXACTHS, URXCKE, URXCKINE, URXDE, URXDHS, URXLPDTE +, URXSKCHS, URXDRX, URXSHS, URE0D3DP, URE1D3DN, URE2CKDP, URE3CKDN, URXULPSE, URXVDE, URXVDHS, USSTT, UTDIS, UTXCKE, UDE0D0TN, UDE1D1TN, UDE2D2TN, UDE3D3TN, UDE4CKTN, UDE5D0RN, UDE6D1RN, UDE7D2RN +, UTXDHS, UTXENER, UTXRRS, UTXRYP, UTXRYSK, UTXRD0EN, UTRD0SEN, UTXSKD0N, UTXTGE0, UTXTGE1, UTXTGE2, UTXTGE3, UTXULPSE, UTXUPSEX, UTXVDE, UTXWVDHS, UUSAN, U1DIR, U1ENTHEN, U1ERCLP0, U1ERCLP1 +, U1ERCTRL, U1ERE, U1ERSTHS, U1ERSSHS, U1ERSE, U1FRXMD, U1FTXST, U1RXATHS, U1RXCKE, U1RXDE, U1RXDHS, U1RXDTE, U1RXSKS, U1RXSK, U1RXSHS, U1RE0D, U1RE1CN, U1RE2D, U1RE3N, U1RXUPSE, U1RXVDE +, U1RXVDHS, U1SSTT, U1TDIS, U1TREQ, U1TDE0D3, U1TDE1CK, U1TDE2D0, U1TDE3D1, U1TDE4D2, U1TDE5D3, U1TDE6, U1TDE7, U1TXDHS, U1TXLPD, U1TXRYE, U1TXRY, U1TXRYSK, U1TXREQ, U1TXREQH, U1TXSK, U1TXTGE0 +, U1TXTGE1, U1TXTGE2, U1TXTGE3, U1TXUPSE, U1TXUPSX, U1TXVDE, U1TXWVHS, U1USAN, U2DIR, U2END2, U2ERCLP0, U2ERCLP1, U2ERCTRL, U2ERE, U2ERSTHS, U2ERSSHS, U2ERSE, U2FRXMD, U2FTXST, U2RXACHS, U2RXCKE +, U2RXDE, U2RXDHS, U2RPDTE, U2RXSK, U2RXSKC, U2RXSHS, U2RE0D2, U2RE1D2, U2RE2D3, U2RE3D3, U2RXUPSE, U2RXVDE, U2RXVDHS, U2SSTT, U2TDIS, U2TREQ, U2TDE0D0, U2TDE1D1, U2TDE2D2, U2TDE3D3, U2TDE4CK +, U2TDE5D0, U2TDE6D1, U2TDE7D2, U2TXDHS, U2TPDTE, U2TXRYE, U2TXRYH, U2TXRYSK, U2TXREQ, U2TXREQH, U2TXSKC, U2TXTGE0, U2TXTGE1, U2TXTGE2, U2TXTGE3, U2TXUPSE, U2TXUPSX, U2TXVDE, U2TXWVHS, U2USAN, U3DIR +, U3END3, U3ERCLP0, U3ERCLP1, U3ERCTRL, U3ERE, U3ERSTHS, U3ERSSHS, U3ERSE, U3FRXMD, U3FTXST, U3RXATHS, U3RXCKE, U3RXDE, U3RXDHS, U3RPDTE, U3RXSK, U3RXSKC, U3RXSHS, U3RE0CK, U3RE1CK, U3RE2 +, U3RE3, U3RXUPSE, U3RXVDE, U3RXVDHS, U3SSTT, U3TDISD2, U3TREQD2, U3TDE0D3, U3TDE1D0, U3TDE2D1, U3TDE3D2, U3TDE4D3, U3TDE5CK, U3TDE6, U3TDE7, U3TXDHS, U3TXLPDT, U3TXRY, U3TXRYHS, U3TXRYSK, U3TXREQ +, U3TXREQH, U3TXSKC, U3TXTGE0, U3TXTGE1, U3TXTGE2, U3TXTGE3, U3TXULPS, U3TXUPSX, U3TXVD3, U3TXWVHS, U3USAN, UCENCK, UCRXCKAT, UCRXUCKN, UCSSTT, UCTXREQH, UCTXUPSC, UCTXUPSX, UCUSAN, LTSTEN, LTSTLANE +, URWDCKHS, UTRNREQ, UTWDCKHS, UCRXWCHS, CLKLBACT); parameter GSR = "ENABLED"; parameter AUTO_PD_EN = "POWERED_UP"; parameter CFG_NUM_LANES = "ONE_LANE"; @@ -935,7 +956,8 @@ module DPHY (...); output CLKLBACT; endmodule -module DPSC512K (...); +module DPSC512K(DIA, DIB, ADA, ADB, CLK, CEA, CEB, WEA, WEB, CSA, CSB, RSTA, RSTB, BENA_N, BENB_N, CEOUTA, CEOUTB, DOA, DOB, ERRDECA, ERRDECB +); parameter OUTREG_A = "NO_REG"; parameter OUTREG_B = "NO_REG"; parameter GSR = "ENABLED"; @@ -1093,7 +1115,8 @@ module DPSC512K (...); output [1:0] ERRDECB; endmodule -module DQSBUF (...); +module DQSBUF(BTDETECT, BURSTDETECT, DATAVALID, DQSI, DQSW, DQSWRD, PAUSE, RDCLKSEL, RDDIR, RDLOADN, RDPNTR, READ, READCOUT, READMOVE, RST, SCLK, SELCLK, DQSR90, DQSW270, WRCOUT, WRDIR +, WRLOAD_N, WRLVCOUT, WRLVDIR, WRLVLOAD_N, WRLVMOVE, WRMOVE, WRPNTR, ECLKIN, RSTSMCNT, DLLCODE); parameter GSR = "ENABLED"; parameter ENABLE_FIFO = "DISABLED"; parameter FORCE_READ = "DISABLED"; @@ -1148,7 +1171,12 @@ module DQSBUF (...); input [8:0] DLLCODE; endmodule -module EBR_CORE (...); +module EBR_CORE(DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, DIA9, DIA10, DIA11, DIA12, DIA13, DIA14, DIA15, DIA16, DIA17, DIB0, DIB1, DIB2 +, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, DIB9, DIB10, DIB11, DIB12, DIB13, DIB14, DIB15, DIB16, DIB17, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5 +, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, ADA13, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 +, ADB13, CLKA, CLKB, WEA, WEB, CEA, CEB, RSTA, RSTB, CSA0, CSA1, CSA2, CSB0, CSB1, CSB2, FULLF, AFULL, EMPTYF, AEMPTY, DOA0, DOA1 +, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOA9, DOA10, DOA11, DOA12, DOA13, DOA14, DOA15, DOA16, DOA17, DOB0, DOB1, DOB2, DOB3, DOB4 +, DOB5, DOB6, DOB7, DOB8, DOB9, DOB10, DOB11, DOB12, DOB13, DOB14, DOB15, DOB16, DOB17, ONEERR, TWOERR); parameter INIT_DATA = "STATIC"; parameter DATA_WIDTH_A = "X36"; parameter DATA_WIDTH_B = "X36"; @@ -1354,7 +1382,8 @@ module EBR_CORE (...); output TWOERR; endmodule -module EBR (...); +module EBR(DIA, DIB, ADA, ADB, CLKA, CLKB, WEA, WEB, CEA, CEB, RSTA, RSTB, CSA, CSB, FULLF, AFULL, EMPTYF, AEMPTY, DOA, DOB, ONEERR +, TWOERR); parameter INIT_DATA = "STATIC"; parameter DATA_WIDTH_A = "X36"; parameter DATA_WIDTH_B = "X36"; @@ -1461,7 +1490,7 @@ module EBR (...); output TWOERR; endmodule -module ECLKDIV (...); +module ECLKDIV(DIVOUT, DIVRST, ECLKIN, SLIP); parameter ECLK_DIV = "DISABLE"; parameter GSR = "ENABLED"; output DIVOUT; @@ -1470,14 +1499,14 @@ module ECLKDIV (...); input SLIP; endmodule -module ECLKSYNC (...); +module ECLKSYNC(ECLKIN, ECLKOUT, STOP); parameter STOP_EN = "DISABLE"; input ECLKIN; output ECLKOUT; input STOP; endmodule -module FBMUX (...); +module FBMUX(ENEXT, FBKCK, LGYRDYN, INTLOCK, WKUPSYNC, FBKCLK); parameter INTFB = "IGNORED"; parameter SEL_FBK = "DIVA"; parameter CLKMUX_FB = "CMUX_CLKOP"; @@ -1490,7 +1519,11 @@ module FBMUX (...); input [15:0] FBKCLK; endmodule -module FIFO16K_MODE (...); +module FIFO16K_MODE(DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, DIA9, DIA10, DIA11, DIA12, DIA13, DIA14, DIA15, DIA16, DIA17, DIB0, DIB1, DIB2 +, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, DIB9, DIB10, DIB11, DIB12, DIB13, DIB14, DIB15, DIB16, DIB17, CKA, CKB, CEA, CEB, CSA0, CSA1 +, CSA2, CSB0, CSB1, CSB2, RSTA, RSTB, DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOA9, DOA10, DOA11, DOA12, DOA13, DOA14 +, DOA15, DOA16, DOA17, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, DOB9, DOB10, DOB11, DOB12, DOB13, DOB14, DOB15, DOB16, DOB17 +, ALMOSTFULL, FULL, ALMOSTEMPTY, EMPTY, ONEBITERR, TWOBITERR); parameter DATA_WIDTH_A = "X18"; parameter DATA_WIDTH_B = "X18"; parameter OUTREG_A = "BYPASSED"; @@ -1596,7 +1629,7 @@ module FIFO16K_MODE (...); output TWOBITERR; endmodule -module FIFO16K (...); +module FIFO16K(DIA, DIB, CKA, CKB, CEA, CEB, CSA, CSB, RSTA, RSTB, DOA, DOB, ALMOSTFULL, FULL, ALMOSTEMPTY, EMPTY, ONEBITERR, TWOBITERR); parameter DATA_WIDTH_A = "X18"; parameter DATA_WIDTH_B = "X18"; parameter OUTREG_A = "BYPASSED"; @@ -1630,7 +1663,7 @@ module FIFO16K (...); output TWOBITERR; endmodule -module HSE (...); +module HSE(LMMICLK, LMMIRESET_N, LMMIREQUEST, LMMIWRRD_N, LMMIOFFSET, LMMIWDATA, LMMIRDATA, LMMIRDATAVALID, LMMIREADY, ASFCLKI, ASFEMPTYO, ASFFULLO, ASFRDI, ASFRESETI, ASFWRI, CFG_CLK, HSE_CLK, HSELRSTN); parameter MCGLBGSRNDIS = "EN"; parameter MCHSEDISABLE = "EN"; parameter MCHSEOTPEN = "DIS"; @@ -1654,7 +1687,8 @@ module HSE (...); input HSELRSTN; endmodule -module I2CFIFO (...); +module I2CFIFO(LMMICLK, LMMIRESET_N, LMMIREQUEST, LMMIWRRD_N, LMMIOFFSET, LMMIWDATA, LMMIRDATA, LMMIRDATAVALID, LMMIREADY, ALTSCLIN, ALTSCLOEN, ALTSCLOUT, ALTSDAIN, ALTSDAOEN, ALTSDAOUT, BUSBUSY, FIFORESET, I2CLSRRSTN, INSLEEP, IRQ, MRDCMPL +, RXFIFOAF, RXFIFOE, RXFIFOF, SCLIN, SCLOE, SCLOEN, SCLOUT, SDAIN, SDAOE, SDAOEN, SDAOUT, SLVADDRMATCH, SLVADDRMATCHSCL, SRDWR, TXFIFOAE, TXFIFOE, TXFIFOF); parameter BRNBASEDELAY = "0b0000"; parameter CR1CKDIS = "EN"; parameter CR1FIFOMODE = "REG"; @@ -1733,7 +1767,7 @@ module I2CFIFO (...); output TXFIFOF; endmodule -module IDDR71 (...); +module IDDR71(D, SCLK, RST, ECLK, ALIGNWD, Q0, Q1, Q2, Q3, Q4, Q5, Q6); parameter GSR = "ENABLED"; input D; input SCLK; @@ -1749,7 +1783,7 @@ module IDDR71 (...); output Q6; endmodule -module IDDRX1 (...); +module IDDRX1(D, SCLK, RST, Q0, Q1); parameter GSR = "ENABLED"; input D; input SCLK; @@ -1758,7 +1792,7 @@ module IDDRX1 (...); output Q1; endmodule -module IDDRX2DQ (...); +module IDDRX2DQ(D, DQSR90, ECLK, SCLK, RST, RDPNTR0, RDPNTR1, RDPNTR2, WRPNTR0, WRPNTR1, WRPNTR2, Q0, Q1, Q2, Q3); parameter GSR = "ENABLED"; input D; input DQSR90; @@ -1777,7 +1811,7 @@ module IDDRX2DQ (...); output Q3; endmodule -module IDDRX2 (...); +module IDDRX2(D, SCLK, RST, ECLK, ALIGNWD, Q0, Q1, Q2, Q3); parameter GSR = "ENABLED"; input D; input SCLK; @@ -1790,7 +1824,7 @@ module IDDRX2 (...); output Q3; endmodule -module IDDRX4DQ (...); +module IDDRX4DQ(D, DQSR90, ECLK, SCLK, RST, RDPNTR0, RDPNTR1, RDPNTR2, WRPNTR0, WRPNTR1, WRPNTR2, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7); parameter GSR = "ENABLED"; input D; input DQSR90; @@ -1813,7 +1847,7 @@ module IDDRX4DQ (...); output Q7; endmodule -module IDDRX4 (...); +module IDDRX4(D, SCLK, RST, ECLK, ALIGNWD, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7); parameter GSR = "ENABLED"; input D; input SCLK; @@ -1830,7 +1864,7 @@ module IDDRX4 (...); output Q7; endmodule -module IDDRX5 (...); +module IDDRX5(D, SCLK, RST, ECLK, ALIGNWD, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9); parameter GSR = "ENABLED"; input D; input SCLK; @@ -1849,7 +1883,7 @@ module IDDRX5 (...); output Q9; endmodule -module IFD1P3BX (...); +module IFD1P3BX(D, SP, CK, PD, Q); parameter GSR = "ENABLED"; input D; input SP; @@ -1858,7 +1892,7 @@ module IFD1P3BX (...); output Q; endmodule -module IFD1P3DX (...); +module IFD1P3DX(D, SP, CK, CD, Q); parameter GSR = "ENABLED"; input D; input SP; @@ -1867,7 +1901,7 @@ module IFD1P3DX (...); output Q; endmodule -module IFD1P3IX (...); +module IFD1P3IX(D, SP, CK, CD, Q); parameter GSR = "ENABLED"; input D; input SP; @@ -1876,7 +1910,7 @@ module IFD1P3IX (...); output Q; endmodule -module IFD1P3JX (...); +module IFD1P3JX(D, SP, CK, PD, Q); parameter GSR = "ENABLED"; input D; input SP; @@ -1886,7 +1920,7 @@ module IFD1P3JX (...); endmodule (* keep *) -module JTAG (...); +module JTAG(JCE1, JCE2, JRSTN, JRTI1, JRTI2, JSHIFT, JTDI, JUPDATE, JTDO1, JTDO2, SMCLK, TCK, JTCK, TDI, TDO_OEN, TDO, TMS); parameter MCER1EXIST = "NEXIST"; parameter MCER2EXIST = "NEXIST"; output JCE1; @@ -1908,7 +1942,8 @@ module JTAG (...); input TMS; endmodule -module LRAM (...); +module LRAM(ADA, ADB, BENA_N, BENB_N, CEA, CEB, CLK, CSA, CSB, DIA, DIB, DOA, DOB, DPS, ERRDECA, ERRDECB, OCEA, OCEB, OEA, OEB, RSTA +, RSTB, WEA, WEB, ERRDET, LRAMREADY); parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; parameter INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; parameter INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; @@ -2077,7 +2112,7 @@ module LRAM (...); output LRAMREADY; endmodule -module M18X36 (...); +module M18X36(SFTCTRL, PH36, PL36, SGNED18H, SGNED18L, P72, ROUNDEN); parameter SFTEN = "DISABLED"; parameter MULT18X36 = "ENABLED"; parameter MULT36 = "DISABLED"; @@ -2094,7 +2129,7 @@ module M18X36 (...); input ROUNDEN; endmodule -module MULT18 (...); +module MULT18(SFTCTRL, ARHSIGN, BRHSIGN, ARH, BRH, ARL, BRL, PL18, PH18, SIGNED18, P36, ROUNDEN); parameter SFTEN = "DISABLED"; parameter MULT18X18 = "ENABLED"; parameter ROUNDHALFUP = "DISABLED"; @@ -2114,7 +2149,7 @@ module MULT18 (...); input ROUNDEN; endmodule -module MULT36 (...); +module MULT36(PH72, PL72, PML72, PMH72); parameter MULT36X36 = "ENABLED"; input [72:0] PH72; input [72:0] PL72; @@ -2122,7 +2157,7 @@ module MULT36 (...); output [71:0] PMH72; endmodule -module MULT9 (...); +module MULT9(A, ASIGNED, BR, AS1, AS2, ASSIGNED1, ASSIGNED2, BRSIGNED, CLK, CEA, RSTA, AO, BO, AOSIGNED, BOSIGNED, AR, ARSIGNED, P18, CEP, RSTP); parameter SIGNEDSTATIC_EN = "DISABLED"; parameter ASIGNED_OPERAND_EN = "DISABLED"; parameter BYPASS_MULT9 = "USED"; @@ -2155,7 +2190,8 @@ module MULT9 (...); input RSTP; endmodule -module MULTADDSUB18X18WIDE (...); +module MULTADDSUB18X18WIDE(A0, B0, A1, B1, C, CLK, CEA0, CEA1, RSTA0, RSTA1, CEB0, CEB1, RSTB0, RSTB1, CEC, RSTC, RSTCTRL, CECTRL, SIGNED, RSTPIPE, CEPIPE +, Z, RSTOUT, CEOUT, LOADC, ADDSUB); parameter REGINPUTAB0 = "REGISTER"; parameter REGINPUTAB1 = "REGISTER"; parameter REGINPUTC = "REGISTER"; @@ -2194,7 +2230,8 @@ module MULTADDSUB18X18WIDE (...); input [1:0] ADDSUB; endmodule -module MULTADDSUB9X9WIDE (...); +module MULTADDSUB9X9WIDE(A0, B0, A1, B1, A2, B2, A3, B3, C, CLK, CEA0A1, CEA2A3, RSTA0A1, RSTA2A3, CEB0B1, CEB2B3, RSTB0B1, RSTB2B3, CEC, RSTC, RSTCTRL +, CECTRL, SIGNED, RSTPIPE, CEPIPE, RSTOUT, CEOUT, LOADC, ADDSUB, Z); parameter REGINPUTAB0 = "REGISTER"; parameter REGINPUTAB1 = "REGISTER"; parameter REGINPUTAB2 = "REGISTER"; @@ -2240,14 +2277,14 @@ module MULTADDSUB9X9WIDE (...); endmodule (* keep *) -module MULTIBOOT (...); +module MULTIBOOT(AUTOREBOOT, MSPIMADDR); parameter MSPIADDR = "0b00000000000000000000000000000000"; parameter SOURCESEL = "DIS"; input AUTOREBOOT; input [31:0] MSPIMADDR; endmodule -module ODDR71 (...); +module ODDR71(D0, D1, D2, D3, D4, D5, D6, SCLK, RST, ECLK, Q); parameter GSR = "ENABLED"; input D0; input D1; @@ -2262,7 +2299,7 @@ module ODDR71 (...); output Q; endmodule -module ODDRX1 (...); +module ODDRX1(D0, D1, SCLK, RST, Q); parameter GSR = "ENABLED"; input D0; input D1; @@ -2271,7 +2308,7 @@ module ODDRX1 (...); output Q; endmodule -module ODDRX2DQS (...); +module ODDRX2DQS(D0, D1, D2, D3, DQSW, ECLK, SCLK, RST, Q); parameter GSR = "ENABLED"; input D0; input D1; @@ -2284,7 +2321,7 @@ module ODDRX2DQS (...); output Q; endmodule -module ODDRX2DQ (...); +module ODDRX2DQ(D0, D1, D2, D3, DQSW270, ECLK, SCLK, RST, Q); parameter GSR = "ENABLED"; input D0; input D1; @@ -2297,7 +2334,7 @@ module ODDRX2DQ (...); output Q; endmodule -module ODDRX2 (...); +module ODDRX2(D0, D1, D2, D3, SCLK, RST, ECLK, Q); parameter GSR = "ENABLED"; input D0; input D1; @@ -2309,7 +2346,7 @@ module ODDRX2 (...); output Q; endmodule -module ODDRX4DQS (...); +module ODDRX4DQS(D0, D1, D2, D3, D4, D5, D6, D7, DQSW, ECLK, SCLK, RST, Q); parameter GSR = "ENABLED"; input D0; input D1; @@ -2326,7 +2363,7 @@ module ODDRX4DQS (...); output Q; endmodule -module ODDRX4DQ (...); +module ODDRX4DQ(D0, D1, D2, D3, D4, D5, D6, D7, DQSW270, ECLK, SCLK, RST, Q); parameter GSR = "ENABLED"; input D0; input D1; @@ -2343,7 +2380,7 @@ module ODDRX4DQ (...); output Q; endmodule -module ODDRX4 (...); +module ODDRX4(D0, D1, D2, D3, D4, D5, D6, D7, SCLK, RST, ECLK, Q); parameter GSR = "ENABLED"; input D0; input D1; @@ -2359,7 +2396,7 @@ module ODDRX4 (...); output Q; endmodule -module ODDRX5 (...); +module ODDRX5(D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, SCLK, RST, ECLK, Q); parameter GSR = "ENABLED"; input D0; input D1; @@ -2377,7 +2414,7 @@ module ODDRX5 (...); output Q; endmodule -module OFD1P3BX (...); +module OFD1P3BX(D, SP, CK, PD, Q); parameter GSR = "ENABLED"; input D; input SP; @@ -2386,7 +2423,7 @@ module OFD1P3BX (...); output Q; endmodule -module OFD1P3DX (...); +module OFD1P3DX(D, SP, CK, CD, Q); parameter GSR = "ENABLED"; input D; input SP; @@ -2395,7 +2432,7 @@ module OFD1P3DX (...); output Q; endmodule -module OFD1P3IX (...); +module OFD1P3IX(D, SP, CK, CD, Q); parameter GSR = "ENABLED"; input D; input SP; @@ -2404,7 +2441,7 @@ module OFD1P3IX (...); output Q; endmodule -module OFD1P3JX (...); +module OFD1P3JX(D, SP, CK, PD, Q); parameter GSR = "ENABLED"; input D; input SP; @@ -2413,7 +2450,7 @@ module OFD1P3JX (...); output Q; endmodule -module OSHX2 (...); +module OSHX2(D0, D1, ECLK, SCLK, RST, Q); parameter GSR = "ENABLED"; input D0; input D1; @@ -2423,7 +2460,7 @@ module OSHX2 (...); output Q; endmodule -module OSHX4 (...); +module OSHX4(D0, D1, D2, D3, ECLK, SCLK, RST, Q); parameter GSR = "ENABLED"; input D0; input D1; @@ -2435,7 +2472,11 @@ module OSHX4 (...); output Q; endmodule -module PCIE (...); +module PCIE(LMMICLK, LMMIRESET_N, LMMIREQUEST, LMMIWRRD_N, LMMIOFFSET, LMMIWDATA, LMMIRDATA, LMMIRDATAVALID, LMMIREADY, ACJNOUT, ACJPOUT, AUXCK, CKUSRI, CKUSRO, ECKIN, ECKIND2, ECKINDO, ERSTN, ERSTND2, ERXCKD2, ERXCKDO +, ERXRSND2, ETXCKD2, ETXCKDO, ETXRSND2, FLR, FLRACK, MINTLEG, MINTO, PERSTN, PMCTRL, PMCTRLEN, PMDPAST, PRMSGSD, PRNOSNP, PRNSNPRE, PRSNOOP, PRSNPRE, PPBDREG, PPBDSEL, REXTCK, REXTRST +, RSTUSRN, UDLLKUP, ULTSDIS, UPLLKUP, UTLLKUP, UCFGADDR, UCFGF, UCFGRDD, UCFGRDE, UCFGRDY, UCFGSERD, UCFGVD, UCFGWRBE, UCFGWRD, UCFGWRDN, USERAUPD, USERTRS, VRXCMDD, VRXCINIT, VRXCNH, VRXCNINF +, VRXCRRE, VRXD, VRXDP, VRXEOP, VRXERR, VRXF, VRXRDY, VRXSEL, VRXSOP, VRXVD, VXCDINIT, VXCDNH, VTXCRRE, VXD, VXDP, VXEOP, VXEOPN, VXRDY, VXSOP, VXVD, TESTOUT +, S0REFCKN, S0REFCKP, S0REFRET, S0REXT, S0RXN, S0RXP, S0TXN, S0TXP, CLKREQI, CLKREQO, CLKREQOE); parameter ENABLE_USER_CFG = "DISABLED"; parameter PWDN_N = "DISABLED"; parameter GSR = "ENABLED"; @@ -3595,7 +3636,12 @@ module PCIE (...); output CLKREQOE; endmodule -module PDP16K_MODE (...); +module PDP16K_MODE(DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, DI18, DI19, DI20 +, DI21, DI22, DI23, DI24, DI25, DI26, DI27, DI28, DI29, DI30, DI31, DI32, DI33, DI34, DI35, ADW0, ADW1, ADW2, ADW3, ADW4, ADW5 +, ADW6, ADW7, ADW8, ADW9, ADW10, ADW11, ADW12, ADW13, ADR0, ADR1, ADR2, ADR3, ADR4, ADR5, ADR6, ADR7, ADR8, ADR9, ADR10, ADR11, ADR12 +, ADR13, CLKW, CLKR, CEW, CER, CSW0, CSW1, CSW2, CSR0, CSR1, CSR2, RST, DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8 +, DO9, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17, DO18, DO19, DO20, DO21, DO22, DO23, DO24, DO25, DO26, DO27, DO28, DO29 +, DO30, DO31, DO32, DO33, DO34, DO35, ONEBITERR, TWOBITERR); parameter DATA_WIDTH_W = "X36"; parameter DATA_WIDTH_R = "X36"; parameter OUTREG = "BYPASSED"; @@ -3785,7 +3831,7 @@ module PDP16K_MODE (...); output TWOBITERR; endmodule -module PDP16K (...); +module PDP16K(DI, ADW, ADR, CLKW, CLKR, CEW, CER, CSW, CSR, RST, DO, ONEBITERR, TWOBITERR); parameter DATA_WIDTH_W = "X36"; parameter DATA_WIDTH_R = "X36"; parameter OUTREG = "BYPASSED"; @@ -3875,7 +3921,12 @@ module PDP16K (...); output TWOBITERR; endmodule -module PDPSC16K_MODE (...); +module PDPSC16K_MODE(DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, DI18, DI19, DI20 +, DI21, DI22, DI23, DI24, DI25, DI26, DI27, DI28, DI29, DI30, DI31, DI32, DI33, DI34, DI35, ADW0, ADW1, ADW2, ADW3, ADW4, ADW5 +, ADW6, ADW7, ADW8, ADW9, ADW10, ADW11, ADW12, ADW13, ADR0, ADR1, ADR2, ADR3, ADR4, ADR5, ADR6, ADR7, ADR8, ADR9, ADR10, ADR11, ADR12 +, ADR13, CLK, CER, CEW, CSW0, CSW1, CSW2, CSR0, CSR1, CSR2, RST, DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9 +, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17, DO18, DO19, DO20, DO21, DO22, DO23, DO24, DO25, DO26, DO27, DO28, DO29, DO30 +, DO31, DO32, DO33, DO34, DO35, ONEBITERR, TWOBITERR); parameter DATA_WIDTH_W = "X36"; parameter DATA_WIDTH_R = "X36"; parameter OUTREG = "BYPASSED"; @@ -4064,7 +4115,7 @@ module PDPSC16K_MODE (...); output TWOBITERR; endmodule -module PDPSC16K (...); +module PDPSC16K(DI, ADW, ADR, CLK, CER, CEW, CSW, CSR, RST, DO, ONEBITERR, TWOBITERR); parameter DATA_WIDTH_W = "X36"; parameter DATA_WIDTH_R = "X36"; parameter OUTREG = "BYPASSED"; @@ -4153,7 +4204,7 @@ module PDPSC16K (...); output TWOBITERR; endmodule -module PDPSC512K (...); +module PDPSC512K(DI, ADW, ADR, CLK, CEW, CER, WE, CSW, CSR, RSTR, BYTEEN_N, DO, ERRDECA, ERRDECB); parameter OUTREG = "NO_REG"; parameter GSR = "ENABLED"; parameter RESETMODE = "SYNC"; @@ -4303,7 +4354,9 @@ module PDPSC512K (...); output [1:0] ERRDECB; endmodule -module PLL (...); +module PLL(INTFBKOP, INTFBKOS, INTFBKOS2, INTFBKOS3, INTFBKOS4, INTFBKOS5, DIR, DIRSEL, LOADREG, DYNROTATE, LMMICLK, LMMIRESET_N, LMMIREQUEST, LMMIWRRD_N, LMMIOFFSET, LMMIWDATA, LMMIRDATA, LMMIRDATAVALID, LMMIREADY, PLLPOWERDOWN_N, REFCK +, CLKOP, CLKOS, CLKOS2, CLKOS3, CLKOS4, CLKOS5, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, ENCLKOS4, ENCLKOS5, FBKCK, INTLOCK, LEGACY, LEGRDYN, LOCK, PFDDN, PFDUP, PLLRESET, STDBY +, REFMUXCK, REGQA, REGQB, REGQB1, CLKOUTDL, ROTDEL, DIRDEL, ROTDELP1, GRAYTEST, BINTEST, DIRDELP1, GRAYACT, BINACT); parameter BW_CTL_BIAS = "0b0101"; parameter CLKOP_TRIM = "0b0000"; parameter CLKOS_TRIM = "0b0000"; @@ -4478,7 +4531,8 @@ module PLL (...); input [1:0] BINACT; endmodule -module PREADD9 (...); +module PREADD9(B, BSIGNED, C, BRS1, BRS2, BLS1, BLS2, BRSS1, BRSS2, BLSS1, BLSS2, PRCASIN, CLK, RSTB, CEB, RSTCL, CECL, BRSO, BLSO, BRSOSGND, BLSOSGND +, PRCASOUT, BR, BRSIGNED); parameter SIGNEDSTATIC_EN = "DISABLED"; parameter SUBSTRACT_EN = "SUBTRACTION"; parameter CSIGNED = "DISABLED"; @@ -4520,7 +4574,7 @@ module PREADD9 (...); output BRSIGNED; endmodule -module REFMUX (...); +module REFMUX(REFCK, ZRSEL3, REFSEL, REFCLK1, REFCLK2); parameter REFSEL_ATT = "MC1"; parameter SEL1 = "SELECT_REFCLK1"; parameter SEL_REF2 = "REFCLK2_0"; @@ -4532,7 +4586,7 @@ module REFMUX (...); input [7:0] REFCLK2; endmodule -module REG18 (...); +module REG18(PM, PP, CEP, RSTP, CLK); parameter REGBYPS = "REGISTER"; parameter GSR = "ENABLED"; parameter RESET = "SYNC"; @@ -4544,7 +4598,7 @@ module REG18 (...); endmodule (* keep *) -module SEDC (...); +module SEDC(SEDENABLE, SEDCCOF, SEDCENABLE, SEDCMODE, SEDCSTART, SEDCBUSY, SEDCERR, SEDCERRC, SEDCERRCRC, SEDCERRM, SEDCFRMERRLOC, OSCCLKSEDC, RSTSEDC, SEDCDSRERRLOCCIB); parameter SEDCEN = "DIS"; input SEDENABLE; input SEDCCOF; @@ -4562,7 +4616,7 @@ module SEDC (...); output [12:0] SEDCDSRERRLOCCIB; endmodule -module SEIO18 (...); +module SEIO18(PADDO, DOLP, IOPAD, PADDI, INLP, PADDT, INADC); parameter PULLMODE = "DOWN"; parameter MIPI = "DISABLED"; parameter ENADC_IN = "DISABLED"; @@ -4576,7 +4630,7 @@ module SEIO18 (...); output INADC; endmodule -module SEIO33 (...); +module SEIO33(IOPAD, PADDI, PADDO, PADDT, I3CRESEN, I3CWKPU); parameter PULLMODE = "DOWN"; (* iopad_external_pin *) inout IOPAD; @@ -4587,7 +4641,7 @@ module SEIO33 (...); input I3CWKPU; endmodule -module SGMIICDR (...); +module SGMIICDR(LMMICLK, LMMIRESET_N, LMMIREQUEST, LMMIWRRD_N, LMMIOFFSET, LMMIWDATA, LMMIRDATA, LMMIRDATAVALID, LMMIREADY, DCALIRST, DFACQRST, RRST, SPCLK, SRCLK, SRXD, RSTBFBW, RSTBRXF, SGMIIIN, SREFCLK, CDRLOL); parameter GSR = "ENABLED"; parameter DCOITUNE4LSB = "0_PERCENT"; parameter DCOCTLGI = "0_PERCENT"; @@ -4644,7 +4698,9 @@ module SGMIICDR (...); output CDRLOL; endmodule -module SP16K_MODE (...); +module SP16K_MODE(DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, AD0, AD1, AD2 +, AD3, AD4, AD5, AD6, AD7, AD8, AD9, AD10, AD11, AD12, AD13, CLK, CE, WE, CS0, CS1, CS2, RST, DO0, DO1, DO2 +, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17); parameter DATA_WIDTH = "X18"; parameter OUTREG = "BYPASSED"; parameter RESETMODE = "SYNC"; @@ -4775,7 +4831,7 @@ module SP16K_MODE (...); output DO17; endmodule -module SP16K (...); +module SP16K(DI, AD, CLK, CE, WE, CS, RST, DO); parameter DATA_WIDTH = "X18"; parameter OUTREG = "BYPASSED"; parameter RESETMODE = "SYNC"; @@ -4857,7 +4913,7 @@ module SP16K (...); output [17:0] DO; endmodule -module SP512K (...); +module SP512K(DI, AD, CLK, CE, WE, CS, RSTOUT, CEOUT, BYTEEN_N, DO, ERRDECA, ERRDECB); parameter OUTREG = "NO_REG"; parameter GSR = "ENABLED"; parameter RESETMODE = "SYNC"; @@ -5005,7 +5061,7 @@ module SP512K (...); output [1:0] ERRDECB; endmodule -module TSHX2DQS (...); +module TSHX2DQS(T0, T1, DQSW, ECLK, SCLK, RST, Q); parameter GSR = "ENABLED"; input T0; input T1; @@ -5016,7 +5072,7 @@ module TSHX2DQS (...); output Q; endmodule -module TSHX2DQ (...); +module TSHX2DQ(T0, T1, DQSW270, ECLK, SCLK, RST, Q); parameter GSR = "ENABLED"; input T0; input T1; @@ -5027,7 +5083,7 @@ module TSHX2DQ (...); output Q; endmodule -module TSHX4DQS (...); +module TSHX4DQS(T0, T1, T2, T3, DQSW, ECLK, SCLK, RST, Q); parameter GSR = "ENABLED"; input T0; input T1; @@ -5040,7 +5096,7 @@ module TSHX4DQS (...); output Q; endmodule -module TSHX4DQ (...); +module TSHX4DQ(T0, T1, T2, T3, DQSW270, ECLK, SCLK, RST, Q); parameter GSR = "ENABLED"; input T0; input T1; @@ -5054,7 +5110,7 @@ module TSHX4DQ (...); endmodule (* keep *) -module WDT (...); +module WDT(WDTRELOAD, WDT_CLK, WDT_RST); parameter WDTEN = "DIS"; parameter WDTMODE = "SINGLE"; parameter WDTVALUE = "0b000000000000000000"; @@ -5063,7 +5119,7 @@ module WDT (...); input WDT_RST; endmodule -module MIPI (...); +module MIPI(BP, BN, AP, AN, TP, TN, IHS, HSRXEN, HSTXEN, OHS, OLSP, OLSN); parameter MIPI_ID = "0"; (* iopad_external_pin *) inout BP; @@ -5082,7 +5138,8 @@ module MIPI (...); endmodule (* keep *) -module CONFIG_IP_CORE (...); +module CONFIG_IP_CORE(CFGDONECIB, CIBTSALL, FREEZEIOCIB, LASTADDRCIB15, LASTADDRCIB14, LASTADDRCIB13, LASTADDRCIB12, LASTADDRCIB11, LASTADDRCIB10, LASTADDRCIB9, LASTADDRCIB8, LASTADDRCIB7, LASTADDRCIB6, LASTADDRCIB5, LASTADDRCIB4, LASTADDRCIB3, LASTADDRCIB2, LASTADDRCIB1, LASTADDRCIB0, MBISTENABLEN, MBISTRRMATCH +, MBISTTRRAEN); parameter DONEPHASE = "DIS"; parameter DSRFCTRL = "0b00"; parameter ENTSALL = "DIS"; @@ -5135,11 +5192,11 @@ module CONFIG_IP_CORE (...); input MBISTTRRAEN; endmodule -module TSALLA (...); +module TSALLA(TSALL); input TSALL; endmodule -module OSCA (...); +module OSCA(HFOUTEN, HFSDSCEN, HFCLKOUT, LFCLKOUT, HFCLKCFG, HFSDCOUT); parameter HF_CLK_DIV = "1"; parameter HF_SED_SEC_DIV = "1"; parameter HF_OSC_EN = "ENABLED"; @@ -5152,7 +5209,7 @@ module OSCA (...); output HFSDCOUT; endmodule -module OSC (...); +module OSC(HFCLKOUT, HFSDSCEN, LFCLKOUT, HFSDCOUT, HSE_CLK, JTAG_LRST_N, LMMI_CLK, LMMI_CLK_O, LMMI_LRST_N, LMMI_RST, SEDC_CLK, SEDC_LRST_N, SEDC_RST, CFG_CLK, SMCLK_RST, WDT_CLK, WDT_LRST_N, WDT_RST); parameter DTR_EN = "ENABLED"; parameter HF_CLK_DIV = "1"; parameter HF_SED_SEC_DIV = "1"; @@ -5187,7 +5244,22 @@ module OSC (...); output WDT_RST; endmodule -module ACC54_CORE (...); +module ACC54_CORE(SFTCTRL3, SFTCTRL2, SFTCTRL1, SFTCTRL0, DSPIN53, DSPIN52, DSPIN51, DSPIN50, DSPIN49, DSPIN48, DSPIN47, DSPIN46, DSPIN45, DSPIN44, DSPIN43, DSPIN42, DSPIN41, DSPIN40, DSPIN39, DSPIN38, DSPIN37 +, DSPIN36, DSPIN35, DSPIN34, DSPIN33, DSPIN32, DSPIN31, DSPIN30, DSPIN29, DSPIN28, DSPIN27, DSPIN26, DSPIN25, DSPIN24, DSPIN23, DSPIN22, DSPIN21, DSPIN20, DSPIN19, DSPIN18, DSPIN17, DSPIN16 +, DSPIN15, DSPIN14, DSPIN13, DSPIN12, DSPIN11, DSPIN10, DSPIN9, DSPIN8, DSPIN7, DSPIN6, DSPIN5, DSPIN4, DSPIN3, DSPIN2, DSPIN1, DSPIN0, PP71, PP70, PP69, PP68, PP67 +, PP66, PP65, PP64, PP63, PP62, PP61, PP60, PP59, PP58, PP57, PP56, PP55, PP54, PP53, PP52, PP51, PP50, PP49, PP48, PP47, PP46 +, PP45, PP44, PP43, PP42, PP41, PP40, PP39, PP38, PP37, PP36, PP35, PP34, PP33, PP32, PP31, PP30, PP29, PP28, PP27, PP26, PP25 +, PP24, PP23, PP22, PP21, PP20, PP19, PP18, PP17, PP16, PP15, PP14, PP13, PP12, PP11, PP10, PP9, PP8, PP7, PP6, PP5, PP4 +, PP3, PP2, PP1, PP0, CINPUT53, CINPUT52, CINPUT51, CINPUT50, CINPUT49, CINPUT48, CINPUT47, CINPUT46, CINPUT45, CINPUT44, CINPUT43, CINPUT42, CINPUT41, CINPUT40, CINPUT39, CINPUT38, CINPUT37 +, CINPUT36, CINPUT35, CINPUT34, CINPUT33, CINPUT32, CINPUT31, CINPUT30, CINPUT29, CINPUT28, CINPUT27, CINPUT26, CINPUT25, CINPUT24, CINPUT23, CINPUT22, CINPUT21, CINPUT20, CINPUT19, CINPUT18, CINPUT17, CINPUT16 +, CINPUT15, CINPUT14, CINPUT13, CINPUT12, CINPUT11, CINPUT10, CINPUT9, CINPUT8, CINPUT7, CINPUT6, CINPUT5, CINPUT4, CINPUT3, CINPUT2, CINPUT1, CINPUT0, LOAD, M9ADDSUB1, M9ADDSUB0, ADDSUB1, ADDSUB0 +, CIN, CASIN1, CASIN0, CEO, RSTO, CEC, RSTC, CLK, SIGNEDI, SUM135, SUM134, SUM133, SUM132, SUM131, SUM130, SUM129, SUM128, SUM127, SUM126, SUM125, SUM124 +, SUM123, SUM122, SUM121, SUM120, SUM119, SUM118, SUM117, SUM116, SUM115, SUM114, SUM113, SUM112, SUM111, SUM110, SUM19, SUM18, SUM17, SUM16, SUM15, SUM14, SUM13 +, SUM12, SUM11, SUM10, SUM035, SUM034, SUM033, SUM032, SUM031, SUM030, SUM029, SUM028, SUM027, SUM026, SUM025, SUM024, SUM023, SUM022, SUM021, SUM020, SUM019, SUM018 +, SUM017, SUM016, SUM015, SUM014, SUM013, SUM012, SUM011, SUM010, SUM09, SUM08, SUM07, SUM06, SUM05, SUM04, SUM03, SUM02, SUM01, SUM00, DSPOUT53, DSPOUT52, DSPOUT51 +, DSPOUT50, DSPOUT49, DSPOUT48, DSPOUT47, DSPOUT46, DSPOUT45, DSPOUT44, DSPOUT43, DSPOUT42, DSPOUT41, DSPOUT40, DSPOUT39, DSPOUT38, DSPOUT37, DSPOUT36, DSPOUT35, DSPOUT34, DSPOUT33, DSPOUT32, DSPOUT31, DSPOUT30 +, DSPOUT29, DSPOUT28, DSPOUT27, DSPOUT26, DSPOUT25, DSPOUT24, DSPOUT23, DSPOUT22, DSPOUT21, DSPOUT20, DSPOUT19, DSPOUT18, DSPOUT17, DSPOUT16, DSPOUT15, DSPOUT14, DSPOUT13, DSPOUT12, DSPOUT11, DSPOUT10, DSPOUT9 +, DSPOUT8, DSPOUT7, DSPOUT6, DSPOUT5, DSPOUT4, DSPOUT3, DSPOUT2, DSPOUT1, DSPOUT0, CASCOUT1, CASCOUT0, ROUNDEN, CECIN, CECTRL, RSTCIN, RSTCTRL); parameter SIGN = "DISABLED"; parameter M9ADDSUB_CTRL = "ADDITION"; parameter ADDSUB_CTRL = "ADD_ADD_CTRL_54_BIT_ADDER"; @@ -5554,7 +5626,11 @@ module ACC54_CORE (...); input RSTCTRL; endmodule -module ADC_CORE (...); +module ADC_CORE(ADCEN, CAL, CALRDY, CHAEN, CHASEL3, CHASEL2, CHASEL1, CHASEL0, CHBEN, CHBSEL3, CHBSEL2, CHBSEL1, CHBSEL0, CLKDCLK, CLKFAB, COG, COMP1IN, COMP1IP, COMP1OL, COMP2IN, COMP2IP +, COMP2OL, COMP3IN, COMP3IP, COMP3OL, CONVSTOP, DA11, DA10, DA9, DA8, DA7, DA6, DA5, DA4, DA3, DA2, DA1, DA0, DB11, DB10, DB9, DB8 +, DB7, DB6, DB5, DB4, DB3, DB2, DB1, DB0, DN1, DN0, DP1, DP0, EOC, GPION15, GPION14, GPION13, GPION12, GPION11, GPION10, GPION9, GPION8 +, GPION7, GPION6, GPION5, GPION4, GPION3, GPION2, GPION1, GPION0, GPIOP15, GPIOP14, GPIOP13, GPIOP12, GPIOP11, GPIOP10, GPIOP9, GPIOP8, GPIOP7, GPIOP6, GPIOP5, GPIOP4, GPIOP3 +, GPIOP2, GPIOP1, GPIOP0, RESETN, RSTN, RSVDH, RSVDL, SOC, COMP1O, COMP2O, COMP3O); parameter ADC_ENP = "ENABLED"; parameter CLK_DIV = "2"; parameter CTLCOMPSW1 = "DISABLED"; @@ -5674,7 +5750,18 @@ module ADC_CORE (...); output COMP3O; endmodule -module ALUREG_CORE (...); +module ALUREG_CORE(OPCGLOADCLK, ALUCLK, ALUFLAGC, ALUFLAGV, ALUFLAGZ, ALUFORWARDA, ALUFORWARDB, ALUIREGEN, ALUOREGEN, ALURST, DATAA31, DATAA30, DATAA29, DATAA28, DATAA27, DATAA26, DATAA25, DATAA24, DATAA23, DATAA22, DATAA21 +, DATAA20, DATAA19, DATAA18, DATAA17, DATAA16, DATAA15, DATAA14, DATAA13, DATAA12, DATAA11, DATAA10, DATAA9, DATAA8, DATAA7, DATAA6, DATAA5, DATAA4, DATAA3, DATAA2, DATAA1, DATAA0 +, DATAB31, DATAB30, DATAB29, DATAB28, DATAB27, DATAB26, DATAB25, DATAB24, DATAB23, DATAB22, DATAB21, DATAB20, DATAB19, DATAB18, DATAB17, DATAB16, DATAB15, DATAB14, DATAB13, DATAB12, DATAB11 +, DATAB10, DATAB9, DATAB8, DATAB7, DATAB6, DATAB5, DATAB4, DATAB3, DATAB2, DATAB1, DATAB0, DATAC4, DATAC3, DATAC2, DATAC1, DATAC0, OPC6, OPC5, OPC4, OPC3, OPC2 +, OPC1, OPC0, OPCCUSTOM, RADDRA4, RADDRA3, RADDRA2, RADDRA1, RADDRA0, RADDRB4, RADDRB3, RADDRB2, RADDRB1, RADDRB0, RDATAA31, RDATAA30, RDATAA29, RDATAA28, RDATAA27, RDATAA26, RDATAA25, RDATAA24 +, RDATAA23, RDATAA22, RDATAA21, RDATAA20, RDATAA19, RDATAA18, RDATAA17, RDATAA16, RDATAA15, RDATAA14, RDATAA13, RDATAA12, RDATAA11, RDATAA10, RDATAA9, RDATAA8, RDATAA7, RDATAA6, RDATAA5, RDATAA4, RDATAA3 +, RDATAA2, RDATAA1, RDATAA0, RDATAB31, RDATAB30, RDATAB29, RDATAB28, RDATAB27, RDATAB26, RDATAB25, RDATAB24, RDATAB23, RDATAB22, RDATAB21, RDATAB20, RDATAB19, RDATAB18, RDATAB17, RDATAB16, RDATAB15, RDATAB14 +, RDATAB13, RDATAB12, RDATAB11, RDATAB10, RDATAB9, RDATAB8, RDATAB7, RDATAB6, RDATAB5, RDATAB4, RDATAB3, RDATAB2, RDATAB1, RDATAB0, REGCLK, REGCLKEN, REGRST, RESULT31, RESULT30, RESULT29, RESULT28 +, RESULT27, RESULT26, RESULT25, RESULT24, RESULT23, RESULT22, RESULT21, RESULT20, RESULT19, RESULT18, RESULT17, RESULT16, RESULT15, RESULT14, RESULT13, RESULT12, RESULT11, RESULT10, RESULT9, RESULT8, RESULT7 +, RESULT6, RESULT5, RESULT4, RESULT3, RESULT2, RESULT1, RESULT0, SCANCLK, SCANRST, WADDR4, WADDR3, WADDR2, WADDR1, WADDR0, WDROTATE1, WDROTATE0, WDSIGNEXT, WDSIZE1, WDSIZE0, WDATA31, WDATA30 +, WDATA29, WDATA28, WDATA27, WDATA26, WDATA25, WDATA24, WDATA23, WDATA22, WDATA21, WDATA20, WDATA19, WDATA18, WDATA17, WDATA16, WDATA15, WDATA14, WDATA13, WDATA12, WDATA11, WDATA10, WDATA9 +, WDATA8, WDATA7, WDATA6, WDATA5, WDATA4, WDATA3, WDATA2, WDATA1, WDATA0, WREN); parameter ALURST_ACTIVELOW = "DISABLE"; parameter GSR = "ENABLED"; parameter INREG = "DISABLE"; @@ -5929,7 +6016,8 @@ module ALUREG_CORE (...); input WREN; endmodule -module BNKREF18_CORE (...); +module BNKREF18_CORE(STDBYINR, STDBYDIF, PVTSNKI6, PVTSNKI5, PVTSNKI4, PVTSNKI3, PVTSNKI2, PVTSNKI1, PVTSNKI0, PVTSRCI6, PVTSRCI5, PVTSRCI4, PVTSRCI3, PVTSRCI2, PVTSRCI1, PVTSRCI0, PVTCODE6, PVTCODE5, PVTCODE4, PVTCODE3, PVTCODE2 +, PVTCODE1, PVTCODE0, PVTSEL); parameter BANK = "0b0000"; parameter STANDBY_DIFFIO = "DISABLED"; parameter STANDBY_INR = "DISABLED"; @@ -5959,7 +6047,8 @@ module BNKREF18_CORE (...); input PVTSEL; endmodule -module BNKREF33_CORE (...); +module BNKREF33_CORE(PVTSEL, PVTSNKI6, PVTSNKI5, PVTSNKI4, PVTSNKI3, PVTSNKI2, PVTSNKI1, PVTSNKI0, PVTSRCI6, PVTSRCI5, PVTSRCI4, PVTSRCI3, PVTSRCI2, PVTSRCI1, PVTSRCI0, PVTCODE6, PVTCODE5, PVTCODE4, PVTCODE3, PVTCODE2, PVTCODE1 +, PVTCODE0); parameter BANK = "0b0000"; input PVTSEL; input PVTSNKI6; @@ -5985,7 +6074,7 @@ module BNKREF33_CORE (...); output PVTCODE0; endmodule -module DIFFIO18_CORE (...); +module DIFFIO18_CORE(I, DOLP, B, O, INLP, T, INADC, HSRXEN, HSTXEN); parameter MIPI_ID = "0"; parameter PULLMODE = "DOWN"; parameter ENADC_IN = "DISABLED"; @@ -6003,7 +6092,7 @@ module DIFFIO18_CORE (...); endmodule (* keep *) -module CONFIG_CLKRST_CORE (...); +module CONFIG_CLKRST_CORE(HSE_CLK, JTAG_LRST_N, LMMI_CLK, LMMI_CLK_O, LMMI_LRST_N, LMMI_RST, OSCCLK, SEDC_CLK, SEDC_LRST_N, SEDC_RST, CFG_CLK, SMCLK_RST, WDT_CLK, WDT_LRST_N, WDT_RST); parameter MCJTAGGSRNDIS = "EN"; parameter MCLMMIGSRNDIS = "EN"; parameter MCSEDCGSRNDIS = "EN"; @@ -6027,7 +6116,11 @@ module CONFIG_CLKRST_CORE (...); endmodule (* keep *) -module CONFIG_HSE_CORE (...); +module CONFIG_HSE_CORE(ASFCLKI, ASFEMPTYO, ASFFULLO, ASFRDI, ASFRESETI, ASFWRI, CFG_CLK, HSE_CLK, HSELRSTN, LMMICLK, LMMIOFFSET17, LMMIOFFSET16, LMMIOFFSET15, LMMIOFFSET14, LMMIOFFSET13, LMMIOFFSET12, LMMIOFFSET11, LMMIOFFSET10, LMMIOFFSET9, LMMIOFFSET8, LMMIOFFSET7 +, LMMIOFFSET6, LMMIOFFSET5, LMMIOFFSET4, LMMIOFFSET3, LMMIOFFSET2, LMMIOFFSET1, LMMIOFFSET0, LMMIRDATA31, LMMIRDATA30, LMMIRDATA29, LMMIRDATA28, LMMIRDATA27, LMMIRDATA26, LMMIRDATA25, LMMIRDATA24, LMMIRDATA23, LMMIRDATA22, LMMIRDATA21, LMMIRDATA20, LMMIRDATA19, LMMIRDATA18 +, LMMIRDATA17, LMMIRDATA16, LMMIRDATA15, LMMIRDATA14, LMMIRDATA13, LMMIRDATA12, LMMIRDATA11, LMMIRDATA10, LMMIRDATA9, LMMIRDATA8, LMMIRDATA7, LMMIRDATA6, LMMIRDATA5, LMMIRDATA4, LMMIRDATA3, LMMIRDATA2, LMMIRDATA1, LMMIRDATA0, LMMIRDATAVALID, LMMIREADY, LMMIREQUEST +, LMMIRESETN, LMMIWDATA31, LMMIWDATA30, LMMIWDATA29, LMMIWDATA28, LMMIWDATA27, LMMIWDATA26, LMMIWDATA25, LMMIWDATA24, LMMIWDATA23, LMMIWDATA22, LMMIWDATA21, LMMIWDATA20, LMMIWDATA19, LMMIWDATA18, LMMIWDATA17, LMMIWDATA16, LMMIWDATA15, LMMIWDATA14, LMMIWDATA13, LMMIWDATA12 +, LMMIWDATA11, LMMIWDATA10, LMMIWDATA9, LMMIWDATA8, LMMIWDATA7, LMMIWDATA6, LMMIWDATA5, LMMIWDATA4, LMMIWDATA3, LMMIWDATA2, LMMIWDATA1, LMMIWDATA0, LMMIWRRDN, OTM); parameter MCGLBGSRNDIS = "EN"; parameter MCHSEDISABLE = "EN"; parameter MCHSEOTPEN = "DIS"; @@ -6132,7 +6225,7 @@ module CONFIG_HSE_CORE (...); endmodule (* keep *) -module CONFIG_JTAG_CORE (...); +module CONFIG_JTAG_CORE(JCE1, JCE2, JRSTN, JRTI1, JRTI2, JSHIFT, JTDI, JUPDATE, JTDO1, JTDO2, SMCLK, TCK, JTCK, TDI, TDO_OEN, TDO, TMS); parameter MCER1EXIST = "NEXIST"; parameter MCER2EXIST = "NEXIST"; output JCE1; @@ -6155,7 +6248,8 @@ module CONFIG_JTAG_CORE (...); endmodule (* keep *) -module CONFIG_LMMI_CORE (...); +module CONFIG_LMMI_CORE(LMMIOFFSET7, LMMIOFFSET6, LMMIOFFSET5, LMMIOFFSET4, LMMIOFFSET3, LMMIOFFSET2, LMMIOFFSET1, LMMIOFFSET0, LMMICLK, LMMIRDATA7, LMMIRDATA6, LMMIRDATA5, LMMIRDATA4, LMMIRDATA3, LMMIRDATA2, LMMIRDATA1, LMMIRDATA0, LMMIRDATAVALID, LMMIREADY, LMMIRESETN, LMMIREQUEST +, LMMIWDATA7, LMMIWDATA6, LMMIWDATA5, LMMIWDATA4, LMMIWDATA3, LMMIWDATA2, LMMIWDATA1, LMMIWDATA0, LMMIWRRDN, RSTSMCLK, SMCLK); parameter LMMI_EN = "DIS"; input LMMIOFFSET7; input LMMIOFFSET6; @@ -6192,7 +6286,8 @@ module CONFIG_LMMI_CORE (...); endmodule (* keep *) -module CONFIG_MULTIBOOT_CORE (...); +module CONFIG_MULTIBOOT_CORE(CIBAUTOREBOOT, CIBMSPIMADDR31, CIBMSPIMADDR30, CIBMSPIMADDR29, CIBMSPIMADDR28, CIBMSPIMADDR27, CIBMSPIMADDR26, CIBMSPIMADDR25, CIBMSPIMADDR24, CIBMSPIMADDR23, CIBMSPIMADDR22, CIBMSPIMADDR21, CIBMSPIMADDR20, CIBMSPIMADDR19, CIBMSPIMADDR18, CIBMSPIMADDR17, CIBMSPIMADDR16, CIBMSPIMADDR15, CIBMSPIMADDR14, CIBMSPIMADDR13, CIBMSPIMADDR12 +, CIBMSPIMADDR11, CIBMSPIMADDR10, CIBMSPIMADDR9, CIBMSPIMADDR8, CIBMSPIMADDR7, CIBMSPIMADDR6, CIBMSPIMADDR5, CIBMSPIMADDR4, CIBMSPIMADDR3, CIBMSPIMADDR2, CIBMSPIMADDR1, CIBMSPIMADDR0); parameter MSPIADDR = "0b00000000000000000000000000000000"; parameter SOURCESEL = "DIS"; input CIBAUTOREBOOT; @@ -6231,7 +6326,8 @@ module CONFIG_MULTIBOOT_CORE (...); endmodule (* keep *) -module CONFIG_SEDC_CORE (...); +module CONFIG_SEDC_CORE(CIBSED1ENABLE, CIBSEDCCOF, CIBSEDCENABLE, CIBSEDCMODE, CIBSEDCSTART, OSCCLKSEDC, RSTSEDC, SEDCBUSYCIB, SEDCDSRERRLOCCIB12, SEDCDSRERRLOCCIB11, SEDCDSRERRLOCCIB10, SEDCDSRERRLOCCIB9, SEDCDSRERRLOCCIB8, SEDCDSRERRLOCCIB7, SEDCDSRERRLOCCIB6, SEDCDSRERRLOCCIB5, SEDCDSRERRLOCCIB4, SEDCDSRERRLOCCIB3, SEDCDSRERRLOCCIB2, SEDCDSRERRLOCCIB1, SEDCDSRERRLOCCIB0 +, SEDCERR1CIB, SEDCERRCCIB, SEDCERRCRCCIB, SEDCERRMCIB, SEDCFRMERRLOCCIB15, SEDCFRMERRLOCCIB14, SEDCFRMERRLOCCIB13, SEDCFRMERRLOCCIB12, SEDCFRMERRLOCCIB11, SEDCFRMERRLOCCIB10, SEDCFRMERRLOCCIB9, SEDCFRMERRLOCCIB8, SEDCFRMERRLOCCIB7, SEDCFRMERRLOCCIB6, SEDCFRMERRLOCCIB5, SEDCFRMERRLOCCIB4, SEDCFRMERRLOCCIB3, SEDCFRMERRLOCCIB2, SEDCFRMERRLOCCIB1, SEDCFRMERRLOCCIB0); parameter SEDCEN = "DIS"; input CIBSED1ENABLE; input CIBSEDCCOF; @@ -6277,7 +6373,7 @@ module CONFIG_SEDC_CORE (...); endmodule (* keep *) -module CONFIG_WDT_CORE (...); +module CONFIG_WDT_CORE(CIBWDTRELOAD, WDT_CLK, WDT_RST); parameter WDTEN = "DIS"; parameter WDTMODE = "SINGLE"; parameter WDTVALUE = "0b000000000000000000"; @@ -6286,7 +6382,8 @@ module CONFIG_WDT_CORE (...); input WDT_RST; endmodule -module DDRDLL_CORE (...); +module DDRDLL_CORE(CODE8, CODE7, CODE6, CODE5, CODE4, CODE3, CODE2, CODE1, CODE0, FREEZE, LOCK, CLKIN, RST, DCNTL8, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1 +, DCNTL0, UDDCNTL_N); parameter GSR = "ENABLED"; parameter ENA_ROUNDOFF = "ENABLED"; parameter FORCE_MAX_DELAY = "CODE_OR_LOCK_FROM_DLL_LOOP"; @@ -6315,7 +6412,7 @@ module DDRDLL_CORE (...); input UDDCNTL_N; endmodule -module DLLDEL_CORE (...); +module DLLDEL_CORE(CLKIN, CLKOUT, CODE8, CODE7, CODE6, CODE5, CODE4, CODE3, CODE2, CODE1, CODE0, COUT, DIR, LOAD_N, MOVE); parameter ADJUST = "0"; parameter DEL_ADJUST = "PLUS"; parameter ENABLE = "DISABLED"; @@ -6336,7 +6433,37 @@ module DLLDEL_CORE (...); input MOVE; endmodule -module DPHY_CORE (...); +module DPHY_CORE(BITCKEXT, CKN, CKP, CLKREF, D0ACTIVE1, D0ACTIVE0, D0BYTCNT9, D0BYTCNT8, D0BYTCNT7, D0BYTCNT6, D0BYTCNT5, D0BYTCNT4, D0BYTCNT3, D0BYTCNT2, D0BYTCNT1, D0BYTCNT0, D0ERRCNT9, D0ERRCNT8, D0ERRCNT7, D0ERRCNT6, D0ERRCNT5 +, D0ERRCNT4, D0ERRCNT3, D0ERRCNT2, D0ERRCNT1, D0ERRCNT0, D0PASS1, D0PASS0, D0VALID1, D0VALID0, D1ACTIVE1, D1ACTIVE0, D1BYTCNT9, D1BYTCNT8, D1BYTCNT7, D1BYTCNT6, D1BYTCNT5, D1BYTCNT4, D1BYTCNT3, D1BYTCNT2, D1BYTCNT1, D1BYTCNT0 +, D1ERRCNT9, D1ERRCNT8, D1ERRCNT7, D1ERRCNT6, D1ERRCNT5, D1ERRCNT4, D1ERRCNT3, D1ERRCNT2, D1ERRCNT1, D1ERRCNT0, D1PASS1, D1PASS0, D1VALID1, D1VALID0, D2ACTIVE1, D2ACTIVE0, D2BYTCNT9, D2BYTCNT8, D2BYTCNT7, D2BYTCNT6, D2BYTCNT5 +, D2BYTCNT4, D2BYTCNT3, D2BYTCNT2, D2BYTCNT1, D2BYTCNT0, D2ERRCNT9, D2ERRCNT8, D2ERRCNT7, D2ERRCNT6, D2ERRCNT5, D2ERRCNT4, D2ERRCNT3, D2ERRCNT2, D2ERRCNT1, D2ERRCNT0, D2PASS1, D2PASS0, D2VALID1, D2VALID0, D3ACTIVE1, D3ACTIVE0 +, D3BYTCNT9, D3BYTCNT8, D3BYTCNT7, D3BYTCNT6, D3BYTCNT5, D3BYTCNT4, D3BYTCNT3, D3BYTCNT2, D3BYTCNT1, D3BYTCNT0, D3ERRCNT9, D3ERRCNT8, D3ERRCNT7, D3ERRCNT6, D3ERRCNT5, D3ERRCNT4, D3ERRCNT3, D3ERRCNT2, D3ERRCNT1, D3ERRCNT0, D3PASS1 +, D3PASS0, D3VALID1, D3VALID0, DCTSTOUT9, DCTSTOUT8, DCTSTOUT7, DCTSTOUT6, DCTSTOUT5, DCTSTOUT4, DCTSTOUT3, DCTSTOUT2, DCTSTOUT1, DCTSTOUT0, DN0, DN1, DN2, DN3, DP0, DP1, DP2, DP3 +, LOCK, PDDPHY, PDPLL, SCCLKIN, SCRSTNIN, UDIR, UED0THEN, UERCLP0, UERCLP1, UERCTRL, UERE, UERSTHS, UERSSHS, UERSE, UFRXMODE, UTXMDTX, URXACTHS, URXCKE, URXCKINE, URXDE7, URXDE6 +, URXDE5, URXDE4, URXDE3, URXDE2, URXDE1, URXDE0, URXDHS15, URXDHS14, URXDHS13, URXDHS12, URXDHS11, URXDHS10, URXDHS9, URXDHS8, URXDHS7, URXDHS6, URXDHS5, URXDHS4, URXDHS3, URXDHS2, URXDHS1 +, URXDHS0, URXLPDTE, URXSKCHS, URXDRX, URXSHS3, URXSHS2, URXSHS1, URXSHS0, URE0D3DP, URE1D3DN, URE2CKDP, URE3CKDN, URXULPSE, URXVDE, URXVDHS3, URXVDHS2, URXVDHS1, URXVDHS0, USSTT, UTDIS, UTXCKE +, UDE0D0TN, UDE1D1TN, UDE2D2TN, UDE3D3TN, UDE4CKTN, UDE5D0RN, UDE6D1RN, UDE7D2RN, UTXDHS31, UTXDHS30, UTXDHS29, UTXDHS28, UTXDHS27, UTXDHS26, UTXDHS25, UTXDHS24, UTXDHS23, UTXDHS22, UTXDHS21, UTXDHS20, UTXDHS19 +, UTXDHS18, UTXDHS17, UTXDHS16, UTXDHS15, UTXDHS14, UTXDHS13, UTXDHS12, UTXDHS11, UTXDHS10, UTXDHS9, UTXDHS8, UTXDHS7, UTXDHS6, UTXDHS5, UTXDHS4, UTXDHS3, UTXDHS2, UTXDHS1, UTXDHS0, UTXENER, UTXRRS +, UTXRYP, UTXRYSK, UTXRD0EN, UTRD0SEN, UTXSKD0N, UTXTGE0, UTXTGE1, UTXTGE2, UTXTGE3, UTXULPSE, UTXUPSEX, UTXVDE, UTXWVDHS3, UTXWVDHS2, UTXWVDHS1, UTXWVDHS0, UUSAN, U1DIR, U1ENTHEN, U1ERCLP0, U1ERCLP1 +, U1ERCTRL, U1ERE, U1ERSTHS, U1ERSSHS, U1ERSE, U1FRXMD, U1FTXST, U1RXATHS, U1RXCKE, U1RXDE7, U1RXDE6, U1RXDE5, U1RXDE4, U1RXDE3, U1RXDE2, U1RXDE1, U1RXDE0, U1RXDHS15, U1RXDHS14, U1RXDHS13, U1RXDHS12 +, U1RXDHS11, U1RXDHS10, U1RXDHS9, U1RXDHS8, U1RXDHS7, U1RXDHS6, U1RXDHS5, U1RXDHS4, U1RXDHS3, U1RXDHS2, U1RXDHS1, U1RXDHS0, U1RXDTE, U1RXSKS, U1RXSK, U1RXSHS3, U1RXSHS2, U1RXSHS1, U1RXSHS0, U1RE0D, U1RE1CN +, U1RE2D, U1RE3N, U1RXUPSE, U1RXVDE, U1RXVDHS3, U1RXVDHS2, U1RXVDHS1, U1RXVDHS0, U1SSTT, U1TDIS, U1TREQ, U1TDE0D3, U1TDE1CK, U1TDE2D0, U1TDE3D1, U1TDE4D2, U1TDE5D3, U1TDE6, U1TDE7, U1TXDHS31, U1TXDHS30 +, U1TXDHS29, U1TXDHS28, U1TXDHS27, U1TXDHS26, U1TXDHS25, U1TXDHS24, U1TXDHS23, U1TXDHS22, U1TXDHS21, U1TXDHS20, U1TXDHS19, U1TXDHS18, U1TXDHS17, U1TXDHS16, U1TXDHS15, U1TXDHS14, U1TXDHS13, U1TXDHS12, U1TXDHS11, U1TXDHS10, U1TXDHS9 +, U1TXDHS8, U1TXDHS7, U1TXDHS6, U1TXDHS5, U1TXDHS4, U1TXDHS3, U1TXDHS2, U1TXDHS1, U1TXDHS0, U1TXLPD, U1TXRYE, U1TXRY, U1TXRYSK, U1TXREQ, U1TXREQH, U1TXSK, U1TXTGE0, U1TXTGE1, U1TXTGE2, U1TXTGE3, U1TXUPSE +, U1TXUPSX, U1TXVDE, U1TXWVHS3, U1TXWVHS2, U1TXWVHS1, U1TXWVHS0, U1USAN, U2DIR, U2END2, U2ERCLP0, U2ERCLP1, U2ERCTRL, U2ERE, U2ERSTHS, U2ERSSHS, U2ERSE, U2FRXMD, U2FTXST, U2RXACHS, U2RXCKE, U2RXDE7 +, U2RXDE6, U2RXDE5, U2RXDE4, U2RXDE3, U2RXDE2, U2RXDE1, U2RXDE0, U2RXDHS15, U2RXDHS14, U2RXDHS13, U2RXDHS12, U2RXDHS11, U2RXDHS10, U2RXDHS9, U2RXDHS8, U2RXDHS7, U2RXDHS6, U2RXDHS5, U2RXDHS4, U2RXDHS3, U2RXDHS2 +, U2RXDHS1, U2RXDHS0, U2RPDTE, U2RXSK, U2RXSKC, U2RXSHS3, U2RXSHS2, U2RXSHS1, U2RXSHS0, U2RE0D2, U2RE1D2, U2RE2D3, U2RE3D3, U2RXUPSE, U2RXVDE, U2RXVDHS3, U2RXVDHS2, U2RXVDHS1, U2RXVDHS0, U2SSTT, U2TDIS +, U2TREQ, U2TDE0D0, U2TDE1D1, U2TDE2D2, U2TDE3D3, U2TDE4CK, U2TDE5D0, U2TDE6D1, U2TDE7D2, U2TXDHS31, U2TXDHS30, U2TXDHS29, U2TXDHS28, U2TXDHS27, U2TXDHS26, U2TXDHS25, U2TXDHS24, U2TXDHS23, U2TXDHS22, U2TXDHS21, U2TXDHS20 +, U2TXDHS19, U2TXDHS18, U2TXDHS17, U2TXDHS16, U2TXDHS15, U2TXDHS14, U2TXDHS13, U2TXDHS12, U2TXDHS11, U2TXDHS10, U2TXDHS9, U2TXDHS8, U2TXDHS7, U2TXDHS6, U2TXDHS5, U2TXDHS4, U2TXDHS3, U2TXDHS2, U2TXDHS1, U2TXDHS0, U2TPDTE +, U2TXRYE, U2TXRYH, U2TXRYSK, U2TXREQ, U2TXREQH, U2TXSKC, U2TXTGE0, U2TXTGE1, U2TXTGE2, U2TXTGE3, U2TXUPSE, U2TXUPSX, U2TXVDE, U2TXWVHS3, U2TXWVHS2, U2TXWVHS1, U2TXWVHS0, U2USAN, U3DIR, U3END3, U3ERCLP0 +, U3ERCLP1, U3ERCTRL, U3ERE, U3ERSTHS, U3ERSSHS, U3ERSE, U3FRXMD, U3FTXST, U3RXATHS, U3RXCKE, U3RXDE7, U3RXDE6, U3RXDE5, U3RXDE4, U3RXDE3, U3RXDE2, U3RXDE1, U3RXDE0, U3RXDHS15, U3RXDHS14, U3RXDHS13 +, U3RXDHS12, U3RXDHS11, U3RXDHS10, U3RXDHS9, U3RXDHS8, U3RXDHS7, U3RXDHS6, U3RXDHS5, U3RXDHS4, U3RXDHS3, U3RXDHS2, U3RXDHS1, U3RXDHS0, U3RPDTE, U3RXSK, U3RXSKC, U3RXSHS3, U3RXSHS2, U3RXSHS1, U3RXSHS0, U3RE0CK +, U3RE1CK, U3RE2, U3RE3, U3RXUPSE, U3RXVDE, U3RXVDHS3, U3RXVDHS2, U3RXVDHS1, U3RXVDHS0, U3SSTT, U3TDISD2, U3TREQD2, U3TDE0D3, U3TDE1D0, U3TDE2D1, U3TDE3D2, U3TDE4D3, U3TDE5CK, U3TDE6, U3TDE7, U3TXDHS31 +, U3TXDHS30, U3TXDHS29, U3TXDHS28, U3TXDHS27, U3TXDHS26, U3TXDHS25, U3TXDHS24, U3TXDHS23, U3TXDHS22, U3TXDHS21, U3TXDHS20, U3TXDHS19, U3TXDHS18, U3TXDHS17, U3TXDHS16, U3TXDHS15, U3TXDHS14, U3TXDHS13, U3TXDHS12, U3TXDHS11, U3TXDHS10 +, U3TXDHS9, U3TXDHS8, U3TXDHS7, U3TXDHS6, U3TXDHS5, U3TXDHS4, U3TXDHS3, U3TXDHS2, U3TXDHS1, U3TXDHS0, U3TXLPDT, U3TXRY, U3TXRYHS, U3TXRYSK, U3TXREQ, U3TXREQH, U3TXSKC, U3TXTGE0, U3TXTGE1, U3TXTGE2, U3TXTGE3 +, U3TXULPS, U3TXUPSX, U3TXVD3, U3TXWVHS3, U3TXWVHS2, U3TXWVHS1, U3TXWVHS0, U3USAN, UCENCK, UCRXCKAT, UCRXUCKN, UCSSTT, UCTXREQH, UCTXUPSC, UCTXUPSX, UCUSAN, SCANCLK, SCANRST, LMMICLK, LMMIOFFSET4, LMMIOFFSET3 +, LMMIOFFSET2, LMMIOFFSET1, LMMIOFFSET0, LMMIRDATA3, LMMIRDATA2, LMMIRDATA1, LMMIRDATA0, LMMIRDATAVALID, LMMIREADY, LMMIREQUEST, LMMIRESETN, LMMIWDATA3, LMMIWDATA2, LMMIWDATA1, LMMIWDATA0, LMMIWRRDN, LTSTEN, LTSTLANE1, LTSTLANE0, URWDCKHS, UTRNREQ +, UTWDCKHS, UCRXWCHS, OPCGLDCK, CLKLBACT); parameter GSR = "ENABLED"; parameter AUTO_PD_EN = "POWERED_UP"; parameter CFG_NUM_LANES = "ONE_LANE"; @@ -7014,7 +7141,9 @@ module DPHY_CORE (...); output CLKLBACT; endmodule -module DQSBUF_CORE (...); +module DQSBUF_CORE(BTDETECT, BURSTDETECT, DATAVALID, DQSI, DQSW, DQSWRD, PAUSE, RDCLKSEL3, RDCLKSEL2, RDCLKSEL1, RDCLKSEL0, RDDIR, RDLOADN, RDPNTR2, RDPNTR1, RDPNTR0, READ3, READ2, READ1, READ0, READCOUT +, READMOVE, RST, SCLK, SELCLK, DQSR90, DQSW270, WRCOUT, WRDIR, WRLOAD_N, WRLVCOUT, WRLVDIR, WRLVLOAD_N, WRLVMOVE, WRMOVE, WRPNTR2, WRPNTR1, WRPNTR0, ECLKIN, RSTSMCNT, DLLCODE8, DLLCODE7 +, DLLCODE6, DLLCODE5, DLLCODE4, DLLCODE3, DLLCODE2, DLLCODE1, DLLCODE0); parameter GSR = "ENABLED"; parameter ENABLE_FIFO = "DISABLED"; parameter FORCE_READ = "DISABLED"; @@ -7087,7 +7216,7 @@ module DQSBUF_CORE (...); input DLLCODE0; endmodule -module ECLKDIV_CORE (...); +module ECLKDIV_CORE(DIVOUT, DIVRST, ECLKIN, SLIP, TESTINP3, TESTINP2, TESTINP1, TESTINP0); parameter ECLK_DIV = "DISABLE"; parameter GSR = "ENABLED"; output DIVOUT; @@ -7100,14 +7229,15 @@ module ECLKDIV_CORE (...); input TESTINP0; endmodule -module ECLKSYNC_CORE (...); +module ECLKSYNC_CORE(ECLKIN, ECLKOUT, STOP); parameter STOP_EN = "DISABLE"; input ECLKIN; output ECLKOUT; input STOP; endmodule -module FBMUX_CORE (...); +module FBMUX_CORE(ENEXT, FBKCK, LGYRDYN, INTLOCK, WKUPSYNC, FBKCLK15, FBKCLK14, FBKCLK13, FBKCLK12, FBKCLK11, FBKCLK10, FBKCLK9, FBKCLK8, FBKCLK7, FBKCLK6, FBKCLK5, FBKCLK4, FBKCLK3, FBKCLK2, FBKCLK1, FBKCLK0 +); parameter INTFB = "IGNORED"; parameter SEL_FBK = "DIVA"; parameter CLKMUX_FB = "CMUX_CLKOP"; @@ -7135,7 +7265,9 @@ module FBMUX_CORE (...); input FBKCLK0; endmodule -module I2CFIFO_CORE (...); +module I2CFIFO_CORE(ALTSCLIN, ALTSCLOEN, ALTSCLOUT, ALTSDAIN, ALTSDAOEN, ALTSDAOUT, BUSBUSY, FIFORESET, I2CLSRRSTN, INSLEEP, IRQ, LMMICLK, LMMIOFFSET5, LMMIOFFSET4, LMMIOFFSET3, LMMIOFFSET2, LMMIOFFSET1, LMMIOFFSET0, LMMIRDATA7, LMMIRDATA6, LMMIRDATA5 +, LMMIRDATA4, LMMIRDATA3, LMMIRDATA2, LMMIRDATA1, LMMIRDATA0, LMMIRDATAVALID, LMMIREADY, LMMIREQUEST, LMMIRESETN, LMMIWDATA7, LMMIWDATA6, LMMIWDATA5, LMMIWDATA4, LMMIWDATA3, LMMIWDATA2, LMMIWDATA1, LMMIWDATA0, LMMIWRRDN, MRDCMPL, OPCGLOADCLK, RXFIFOAF +, RXFIFOE, RXFIFOF, SCANCLK, SCANRST, SCLIN, SCLOE, SCLOEN, SCLOUT, SDAIN, SDAOE, SDAOEN, SDAOUT, SLEEPCLKSELN, SLVADDRMATCH, SLVADDRMATCHSCL, SRDWR, TXFIFOAE, TXFIFOE, TXFIFOF); parameter BRNBASEDELAY = "0b0000"; parameter CR1CKDIS = "EN"; parameter CR1FIFOMODE = "REG"; @@ -7237,7 +7369,16 @@ module I2CFIFO_CORE (...); output TXFIFOF; endmodule -module LRAM_CORE (...); +module LRAM_CORE(ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0, ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7 +, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0, BENA_N3, BENA_N2, BENA_N1, BENA_N0, BENB_N3, BENB_N2, BENB_N1, BENB_N0, CEA, CEB, CLK, CSA, CSB, DIA31 +, DIA30, DIA29, DIA28, DIA27, DIA26, DIA25, DIA24, DIA23, DIA22, DIA21, DIA20, DIA19, DIA18, DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10 +, DIA9, DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, DIB31, DIB30, DIB29, DIB28, DIB27, DIB26, DIB25, DIB24, DIB23, DIB22, DIB21 +, DIB20, DIB19, DIB18, DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0 +, DOA31, DOA30, DOA29, DOA28, DOA27, DOA26, DOA25, DOA24, DOA23, DOA22, DOA21, DOA20, DOA19, DOA18, DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11 +, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, DOB31, DOB30, DOB29, DOB28, DOB27, DOB26, DOB25, DOB24, DOB23, DOB22 +, DOB21, DOB20, DOB19, DOB18, DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1 +, DOB0, DPS, ERRDECA1, ERRDECA0, ERRDECB1, ERRDECB0, IGN, INITN, OCEA, OCEB, OEA, OEB, RSTA, RSTB, STDBYN, TBISTN, WEA, WEB, ERRDET, LRAMREADY, OPCGLOADCLK +, SCANCLK, SCANRST); parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; parameter INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; parameter INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; @@ -7571,7 +7712,12 @@ module LRAM_CORE (...); input SCANRST; endmodule -module MULT18_CORE (...); +module MULT18_CORE(SFTCTRL3, SFTCTRL2, SFTCTRL1, SFTCTRL0, ARHSIGN, BRHSIGN, ARH8, ARH7, ARH6, ARH5, ARH4, ARH3, ARH2, ARH1, ARH0, BRH8, BRH7, BRH6, BRH5, BRH4, BRH3 +, BRH2, BRH1, BRH0, ARL8, ARL7, ARL6, ARL5, ARL4, ARL3, ARL2, ARL1, ARL0, BRL8, BRL7, BRL6, BRL5, BRL4, BRL3, BRL2, BRL1, BRL0 +, PL1819, PL1818, PL1817, PL1816, PL1815, PL1814, PL1813, PL1812, PL1811, PL1810, PL189, PL188, PL187, PL186, PL185, PL184, PL183, PL182, PL181, PL180, PH1819 +, PH1818, PH1817, PH1816, PH1815, PH1814, PH1813, PH1812, PH1811, PH1810, PH189, PH188, PH187, PH186, PH185, PH184, PH183, PH182, PH181, PH180, SIGNED18, P3637 +, P3636, P3635, P3634, P3633, P3632, P3631, P3630, P3629, P3628, P3627, P3626, P3625, P3624, P3623, P3622, P3621, P3620, P3619, P3618, P3617, P3616 +, P3615, P3614, P3613, P3612, P3611, P3610, P369, P368, P367, P366, P365, P364, P363, P362, P361, P360, ROUNDEN); parameter SFTEN = "DISABLED"; parameter MULT18X18 = "ENABLED"; parameter ROUNDHALFUP = "DISABLED"; @@ -7701,7 +7847,14 @@ module MULT18_CORE (...); input ROUNDEN; endmodule -module MULT18X36_CORE (...); +module MULT18X36_CORE(SFTCTRL3, SFTCTRL2, SFTCTRL1, SFTCTRL0, PH3637, PH3636, PH3635, PH3634, PH3633, PH3632, PH3631, PH3630, PH3629, PH3628, PH3627, PH3626, PH3625, PH3624, PH3623, PH3622, PH3621 +, PH3620, PH3619, PH3618, PH3617, PH3616, PH3615, PH3614, PH3613, PH3612, PH3611, PH3610, PH369, PH368, PH367, PH366, PH365, PH364, PH363, PH362, PH361, PH360 +, PL3637, PL3636, PL3635, PL3634, PL3633, PL3632, PL3631, PL3630, PL3629, PL3628, PL3627, PL3626, PL3625, PL3624, PL3623, PL3622, PL3621, PL3620, PL3619, PL3618, PL3617 +, PL3616, PL3615, PL3614, PL3613, PL3612, PL3611, PL3610, PL369, PL368, PL367, PL366, PL365, PL364, PL363, PL362, PL361, PL360, SGNED18H, SGNED18L, P7272, P7271 +, P7270, P7269, P7268, P7267, P7266, P7265, P7264, P7263, P7262, P7261, P7260, P7259, P7258, P7257, P7256, P7255, P7254, P7253, P7252, P7251, P7250 +, P7249, P7248, P7247, P7246, P7245, P7244, P7243, P7242, P7241, P7240, P7239, P7238, P7237, P7236, P7235, P7234, P7233, P7232, P7231, P7230, P7229 +, P7228, P7227, P7226, P7225, P7224, P7223, P7222, P7221, P7220, P7219, P7218, P7217, P7216, P7215, P7214, P7213, P7212, P7211, P7210, P729, P728 +, P727, P726, P725, P724, P723, P722, P721, P720, ROUNDEN); parameter SFTEN = "DISABLED"; parameter MULT18X36 = "ENABLED"; parameter MULT36 = "DISABLED"; @@ -7867,7 +8020,20 @@ module MULT18X36_CORE (...); input ROUNDEN; endmodule -module MULT36_CORE (...); +module MULT36_CORE(PH7272, PH7271, PH7270, PH7269, PH7268, PH7267, PH7266, PH7265, PH7264, PH7263, PH7262, PH7261, PH7260, PH7259, PH7258, PH7257, PH7256, PH7255, PH7254, PH7253, PH7252 +, PH7251, PH7250, PH7249, PH7248, PH7247, PH7246, PH7245, PH7244, PH7243, PH7242, PH7241, PH7240, PH7239, PH7238, PH7237, PH7236, PH7235, PH7234, PH7233, PH7232, PH7231 +, PH7230, PH7229, PH7228, PH7227, PH7226, PH7225, PH7224, PH7223, PH7222, PH7221, PH7220, PH7219, PH7218, PH7217, PH7216, PH7215, PH7214, PH7213, PH7212, PH7211, PH7210 +, PH729, PH728, PH727, PH726, PH725, PH724, PH723, PH722, PH721, PH720, PL7272, PL7271, PL7270, PL7269, PL7268, PL7267, PL7266, PL7265, PL7264, PL7263, PL7262 +, PL7261, PL7260, PL7259, PL7258, PL7257, PL7256, PL7255, PL7254, PL7253, PL7252, PL7251, PL7250, PL7249, PL7248, PL7247, PL7246, PL7245, PL7244, PL7243, PL7242, PL7241 +, PL7240, PL7239, PL7238, PL7237, PL7236, PL7235, PL7234, PL7233, PL7232, PL7231, PL7230, PL7229, PL7228, PL7227, PL7226, PL7225, PL7224, PL7223, PL7222, PL7221, PL7220 +, PL7219, PL7218, PL7217, PL7216, PL7215, PL7214, PL7213, PL7212, PL7211, PL7210, PL729, PL728, PL727, PL726, PL725, PL724, PL723, PL722, PL721, PL720, PML7271 +, PML7270, PML7269, PML7268, PML7267, PML7266, PML7265, PML7264, PML7263, PML7262, PML7261, PML7260, PML7259, PML7258, PML7257, PML7256, PML7255, PML7254, PML7253, PML7252, PML7251, PML7250 +, PML7249, PML7248, PML7247, PML7246, PML7245, PML7244, PML7243, PML7242, PML7241, PML7240, PML7239, PML7238, PML7237, PML7236, PML7235, PML7234, PML7233, PML7232, PML7231, PML7230, PML7229 +, PML7228, PML7227, PML7226, PML7225, PML7224, PML7223, PML7222, PML7221, PML7220, PML7219, PML7218, PML7217, PML7216, PML7215, PML7214, PML7213, PML7212, PML7211, PML7210, PML729, PML728 +, PML727, PML726, PML725, PML724, PML723, PML722, PML721, PML720, PMH7271, PMH7270, PMH7269, PMH7268, PMH7267, PMH7266, PMH7265, PMH7264, PMH7263, PMH7262, PMH7261, PMH7260, PMH7259 +, PMH7258, PMH7257, PMH7256, PMH7255, PMH7254, PMH7253, PMH7252, PMH7251, PMH7250, PMH7249, PMH7248, PMH7247, PMH7246, PMH7245, PMH7244, PMH7243, PMH7242, PMH7241, PMH7240, PMH7239, PMH7238 +, PMH7237, PMH7236, PMH7235, PMH7234, PMH7233, PMH7232, PMH7231, PMH7230, PMH7229, PMH7228, PMH7227, PMH7226, PMH7225, PMH7224, PMH7223, PMH7222, PMH7221, PMH7220, PMH7219, PMH7218, PMH7217 +, PMH7216, PMH7215, PMH7214, PMH7213, PMH7212, PMH7211, PMH7210, PMH729, PMH728, PMH727, PMH726, PMH725, PMH724, PMH723, PMH722, PMH721, PMH720); parameter MULT36X36 = "ENABLED"; input PH7272; input PH7271; @@ -8161,7 +8327,11 @@ module MULT36_CORE (...); output PMH720; endmodule -module MULT9_CORE (...); +module MULT9_CORE(A8, A7, A6, A5, A4, A3, A2, A1, A0, ASIGNED, BR8, BR7, BR6, BR5, BR4, BR3, BR2, BR1, BR0, AS18, AS17 +, AS16, AS15, AS14, AS13, AS12, AS11, AS10, AS28, AS27, AS26, AS25, AS24, AS23, AS22, AS21, AS20, ASSIGNED1, ASSIGNED2, BRSIGNED, CLK, CEA +, RSTA, AO8, AO7, AO6, AO5, AO4, AO3, AO2, AO1, AO0, BO8, BO7, BO6, BO5, BO4, BO3, BO2, BO1, BO0, AOSIGNED, BOSIGNED +, AR8, AR7, AR6, AR5, AR4, AR3, AR2, AR1, AR0, ARSIGNED, P1819, P1818, P1817, P1816, P1815, P1814, P1813, P1812, P1811, P1810, P189 +, P188, P187, P186, P185, P184, P183, P182, P181, P180, CEP, RSTP); parameter SIGNEDSTATIC_EN = "DISABLED"; parameter ASIGNED_OPERAND_EN = "DISABLED"; parameter BYPASS_MULT9 = "USED"; @@ -8269,7 +8439,8 @@ module MULT9_CORE (...); input RSTP; endmodule -module OSC_CORE (...); +module OSC_CORE(HFCLKOUT, HFOUTEN, HFSDSCEN, HFTRMFAB8, HFTRMFAB7, HFTRMFAB6, HFTRMFAB5, HFTRMFAB4, HFTRMFAB3, HFTRMFAB2, HFTRMFAB1, HFTRMFAB0, LFCLKOUT, LFTRMFAB8, LFTRMFAB7, LFTRMFAB6, LFTRMFAB5, LFTRMFAB4, LFTRMFAB3, LFTRMFAB2, LFTRMFAB1 +, LFTRMFAB0, HFCLKCFG, HFSDCOUT); parameter DTR_EN = "ENABLED"; parameter HF_CLK_DIV = "1"; parameter HF_SED_SEC_DIV = "1"; @@ -8305,7 +8476,28 @@ module OSC_CORE (...); output HFSDCOUT; endmodule -module PCIE_CORE (...); +module PCIE_CORE(ACTACMD, ACTDR11, ACTEN, ACTHIGHZ, ACTMD, ACJNOUT, ACJPOUT, AUXCK, CKUSRI, CKUSRO, ECKIN, ECKIND2, ECKINDO, ERSTN, ERSTND2, ERXCKD2, ERXCKDO, ERXRSND2, ETXCKD2, ETXCKDO, ETXRSND2 +, FLR3, FLR2, FLR1, FLR0, FLRACK3, FLRACK2, FLRACK1, FLRACK0, MINTLEG3, MINTLEG2, MINTLEG1, MINTLEG0, MINTO, PERSTN, PMCTRL4, PMCTRL3, PMCTRL2, PMCTRL1, PMCTRL0, PMCTRLEN, PMDPAST4 +, PMDPAST3, PMDPAST2, PMDPAST1, PMDPAST0, PRMSGSD, PRNOSNP12, PRNOSNP11, PRNOSNP10, PRNOSNP9, PRNOSNP8, PRNOSNP7, PRNOSNP6, PRNOSNP5, PRNOSNP4, PRNOSNP3, PRNOSNP2, PRNOSNP1, PRNOSNP0, PRNSNPRE, PRSNOOP12, PRSNOOP11 +, PRSNOOP10, PRSNOOP9, PRSNOOP8, PRSNOOP7, PRSNOOP6, PRSNOOP5, PRSNOOP4, PRSNOOP3, PRSNOOP2, PRSNOOP1, PRSNOOP0, PRSNPRE, PPBDREG31, PPBDREG30, PPBDREG29, PPBDREG28, PPBDREG27, PPBDREG26, PPBDREG25, PPBDREG24, PPBDREG23 +, PPBDREG22, PPBDREG21, PPBDREG20, PPBDREG19, PPBDREG18, PPBDREG17, PPBDREG16, PPBDREG15, PPBDREG14, PPBDREG13, PPBDREG12, PPBDREG11, PPBDREG10, PPBDREG9, PPBDREG8, PPBDREG7, PPBDREG6, PPBDREG5, PPBDREG4, PPBDREG3, PPBDREG2 +, PPBDREG1, PPBDREG0, PPBDSEL7, PPBDSEL6, PPBDSEL5, PPBDSEL4, PPBDSEL3, PPBDSEL2, PPBDSEL1, PPBDSEL0, REXTCK, REXTRST, RSTUSRN, UDLLKUP, ULTSDIS, UPLLKUP, UTLLKUP, UCFGADDR11, UCFGADDR10, UCFGADDR9, UCFGADDR8 +, UCFGADDR7, UCFGADDR6, UCFGADDR5, UCFGADDR4, UCFGADDR3, UCFGADDR2, UCFGF2, UCFGF1, UCFGF0, UCFGRDD31, UCFGRDD30, UCFGRDD29, UCFGRDD28, UCFGRDD27, UCFGRDD26, UCFGRDD25, UCFGRDD24, UCFGRDD23, UCFGRDD22, UCFGRDD21, UCFGRDD20 +, UCFGRDD19, UCFGRDD18, UCFGRDD17, UCFGRDD16, UCFGRDD15, UCFGRDD14, UCFGRDD13, UCFGRDD12, UCFGRDD11, UCFGRDD10, UCFGRDD9, UCFGRDD8, UCFGRDD7, UCFGRDD6, UCFGRDD5, UCFGRDD4, UCFGRDD3, UCFGRDD2, UCFGRDD1, UCFGRDD0, UCFGRDE +, UCFGRDY, UCFGSERD, UCFGVD, UCFGWRBE3, UCFGWRBE2, UCFGWRBE1, UCFGWRBE0, UCFGWRD31, UCFGWRD30, UCFGWRD29, UCFGWRD28, UCFGWRD27, UCFGWRD26, UCFGWRD25, UCFGWRD24, UCFGWRD23, UCFGWRD22, UCFGWRD21, UCFGWRD20, UCFGWRD19, UCFGWRD18 +, UCFGWRD17, UCFGWRD16, UCFGWRD15, UCFGWRD14, UCFGWRD13, UCFGWRD12, UCFGWRD11, UCFGWRD10, UCFGWRD9, UCFGWRD8, UCFGWRD7, UCFGWRD6, UCFGWRD5, UCFGWRD4, UCFGWRD3, UCFGWRD2, UCFGWRD1, UCFGWRD0, UCFGWRDN, USERAUPD, USERTRS3 +, USERTRS2, USERTRS1, USERTRS0, LMMICLK, LMMIOFFSET16, LMMIOFFSET15, LMMIOFFSET14, LMMIOFFSET13, LMMIOFFSET12, LMMIOFFSET11, LMMIOFFSET10, LMMIOFFSET9, LMMIOFFSET8, LMMIOFFSET7, LMMIOFFSET6, LMMIOFFSET5, LMMIOFFSET4, LMMIOFFSET3, LMMIOFFSET2, LMMIRDATA31, LMMIRDATA30 +, LMMIRDATA29, LMMIRDATA28, LMMIRDATA27, LMMIRDATA26, LMMIRDATA25, LMMIRDATA24, LMMIRDATA23, LMMIRDATA22, LMMIRDATA21, LMMIRDATA20, LMMIRDATA19, LMMIRDATA18, LMMIRDATA17, LMMIRDATA16, LMMIRDATA15, LMMIRDATA14, LMMIRDATA13, LMMIRDATA12, LMMIRDATA11, LMMIRDATA10, LMMIRDATA9 +, LMMIRDATA8, LMMIRDATA7, LMMIRDATA6, LMMIRDATA5, LMMIRDATA4, LMMIRDATA3, LMMIRDATA2, LMMIRDATA1, LMMIRDATA0, LMMIRDATAVALID, LMMIREADY, LMMIREQUEST, LMMIRESETN, LMMIWDATA31, LMMIWDATA30, LMMIWDATA29, LMMIWDATA28, LMMIWDATA27, LMMIWDATA26, LMMIWDATA25, LMMIWDATA24 +, LMMIWDATA23, LMMIWDATA22, LMMIWDATA21, LMMIWDATA20, LMMIWDATA19, LMMIWDATA18, LMMIWDATA17, LMMIWDATA16, LMMIWDATA15, LMMIWDATA14, LMMIWDATA13, LMMIWDATA12, LMMIWDATA11, LMMIWDATA10, LMMIWDATA9, LMMIWDATA8, LMMIWDATA7, LMMIWDATA6, LMMIWDATA5, LMMIWDATA4, LMMIWDATA3 +, LMMIWDATA2, LMMIWDATA1, LMMIWDATA0, LMMIWRRDN, VRXCMDD12, VRXCMDD11, VRXCMDD10, VRXCMDD9, VRXCMDD8, VRXCMDD7, VRXCMDD6, VRXCMDD5, VRXCMDD4, VRXCMDD3, VRXCMDD2, VRXCMDD1, VRXCMDD0, VRXCINIT, VRXCNH11, VRXCNH10, VRXCNH9 +, VRXCNH8, VRXCNH7, VRXCNH6, VRXCNH5, VRXCNH4, VRXCNH3, VRXCNH2, VRXCNH1, VRXCNH0, VRXCNINF, VRXCRRE, VRXD31, VRXD30, VRXD29, VRXD28, VRXD27, VRXD26, VRXD25, VRXD24, VRXD23, VRXD22 +, VRXD21, VRXD20, VRXD19, VRXD18, VRXD17, VRXD16, VRXD15, VRXD14, VRXD13, VRXD12, VRXD11, VRXD10, VRXD9, VRXD8, VRXD7, VRXD6, VRXD5, VRXD4, VRXD3, VRXD2, VRXD1 +, VRXD0, VRXDP3, VRXDP2, VRXDP1, VRXDP0, VRXEOP, VRXERR, VRXF1, VRXF0, VRXRDY, VRXSEL1, VRXSEL0, VRXSOP, VRXVD, VXCDINIT, VXCDNH11, VXCDNH10, VXCDNH9, VXCDNH8, VXCDNH7, VXCDNH6 +, VXCDNH5, VXCDNH4, VXCDNH3, VXCDNH2, VXCDNH1, VXCDNH0, VTXCRRE, VXD31, VXD30, VXD29, VXD28, VXD27, VXD26, VXD25, VXD24, VXD23, VXD22, VXD21, VXD20, VXD19, VXD18 +, VXD17, VXD16, VXD15, VXD14, VXD13, VXD12, VXD11, VXD10, VXD9, VXD8, VXD7, VXD6, VXD5, VXD4, VXD3, VXD2, VXD1, VXD0, VXDP3, VXDP2, VXDP1 +, VXDP0, VXEOP, VXEOPN, VXRDY, VXSOP, VXVD, TESTOUT7, TESTOUT6, TESTOUT5, TESTOUT4, TESTOUT3, TESTOUT2, TESTOUT1, TESTOUT0, REFCLKNA, S0REFCKN, S0REFCKP, S0REFRET, S0REXT, S0RXN, S0RXP +, S0TXN, S0TXP, CLKREQI, CLKREQO, CLKREQOE, SCANCLK, SCANRST, OPCGLDCK, ALTCLKIN); parameter ENABLE_USER_CFG = "DISABLED"; parameter PWDN_N = "DISABLED"; parameter GSR = "ENABLED"; @@ -9820,7 +10012,11 @@ module PCIE_CORE (...); input ALTCLKIN; endmodule -module PLL_CORE (...); +module PLL_CORE(CIBDIR, CIBDSEL2, CIBDSEL1, CIBDSEL0, CIBLDREG, CIBROT, CLKOP, CLKOS, CLKOS2, CLKOS3, CLKOS4, CLKOS5, ENEXT, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, ENCLKOS4, ENCLKOS5, FBKCK, INTFBK5 +, INTFBK4, INTFBK3, INTFBK2, INTFBK1, INTFBK0, INTLOCK, LEGACY, LEGRDYN, LMMICLK, LMMIOFFSET6, LMMIOFFSET5, LMMIOFFSET4, LMMIOFFSET3, LMMIOFFSET2, LMMIOFFSET1, LMMIOFFSET0, LMMIRDATA7, LMMIRDATA6, LMMIRDATA5, LMMIRDATA4, LMMIRDATA3 +, LMMIRDATA2, LMMIRDATA1, LMMIRDATA0, LMMIRDATAVALID, LMMIREADY, LMMIREQUEST, LMMIRESETN, LMMIWDATA7, LMMIWDATA6, LMMIWDATA5, LMMIWDATA4, LMMIWDATA3, LMMIWDATA2, LMMIWDATA1, LMMIWDATA0, LMMIWRRDN, LOCK, PFDDN, PFDUP, PLLRESET, REFCK +, STDBY, ZRSEL3, REFMUXCK, PLLPDN, REGQA, REGQB, REGQB1, CLKOUTDL, ROTDEL, DIRDEL, ROTDELP1, GRAYTEST4, GRAYTEST3, GRAYTEST2, GRAYTEST1, GRAYTEST0, BINTEST1, BINTEST0, DIRDELP1, GRAYACT4, GRAYACT3 +, GRAYACT2, GRAYACT1, GRAYACT0, BINACT1, BINACT0, OPCGLDCK, SCANRST, SCANCLK); parameter BW_CTL_BIAS = "0b0101"; parameter CLKOP_TRIM = "0b0000"; parameter CLKOS_TRIM = "0b0000"; @@ -10032,7 +10228,11 @@ module PLL_CORE (...); input SCANCLK; endmodule -module PREADD9_CORE (...); +module PREADD9_CORE(B8, B7, B6, B5, B4, B3, B2, B1, B0, BSIGNED, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0, BRS18 +, BRS17, BRS16, BRS15, BRS14, BRS13, BRS12, BRS11, BRS10, BRS28, BRS27, BRS26, BRS25, BRS24, BRS23, BRS22, BRS21, BRS20, BLS18, BLS17, BLS16, BLS15 +, BLS14, BLS13, BLS12, BLS11, BLS10, BLS28, BLS27, BLS26, BLS25, BLS24, BLS23, BLS22, BLS21, BLS20, BRSS1, BRSS2, BLSS1, BLSS2, PRCASIN, CLK, RSTB +, CEB, RSTCL, CECL, BRSO8, BRSO7, BRSO6, BRSO5, BRSO4, BRSO3, BRSO2, BRSO1, BRSO0, BLSO8, BLSO7, BLSO6, BLSO5, BLSO4, BLSO3, BLSO2, BLSO1, BLSO0 +, BRSOSGND, BLSOSGND, PRCASOUT, BR8, BR7, BR6, BR5, BR4, BR3, BR2, BR1, BR0, BRSIGNED); parameter SIGNEDSTATIC_EN = "DISABLED"; parameter SUBSTRACT_EN = "SUBTRACTION"; parameter CSIGNED = "DISABLED"; @@ -10147,7 +10347,7 @@ module PREADD9_CORE (...); output BRSIGNED; endmodule -module REFMUX_CORE (...); +module REFMUX_CORE(REFCK, ZRSEL3, REFSEL, REFCLK17, REFCLK16, REFCLK15, REFCLK14, REFCLK13, REFCLK12, REFCLK11, REFCLK10, REFCLK27, REFCLK26, REFCLK25, REFCLK24, REFCLK23, REFCLK22, REFCLK21, REFCLK20); parameter REFSEL_ATT = "MC1"; parameter SEL1 = "SELECT_REFCLK1"; parameter SEL_REF2 = "REFCLK2_0"; @@ -10173,7 +10373,8 @@ module REFMUX_CORE (...); input REFCLK20; endmodule -module REG18_CORE (...); +module REG18_CORE(PM17, PM16, PM15, PM14, PM13, PM12, PM11, PM10, PM9, PM8, PM7, PM6, PM5, PM4, PM3, PM2, PM1, PM0, PP17, PP16, PP15 +, PP14, PP13, PP12, PP11, PP10, PP9, PP8, PP7, PP6, PP5, PP4, PP3, PP2, PP1, PP0, CEP, RSTP, CLK); parameter REGBYPS = "REGISTER"; parameter GSR = "ENABLED"; parameter RESET = "SYNC"; @@ -10218,7 +10419,7 @@ module REG18_CORE (...); input CLK; endmodule -module SEIO18_CORE (...); +module SEIO18_CORE(I, DOLP, B, O, INLP, T, INADC); parameter MIPI_ID = "0"; parameter PULLMODE = "DOWN"; parameter MIPI = "DISABLED"; @@ -10233,7 +10434,7 @@ module SEIO18_CORE (...); output INADC; endmodule -module SEIO33_CORE (...); +module SEIO33_CORE(B, O, I, T, I3CRESEN, I3CWKPU); parameter PULLMODE = "DOWN"; (* iopad_external_pin *) inout B; @@ -10244,7 +10445,9 @@ module SEIO33_CORE (...); input I3CWKPU; endmodule -module SGMIICDR_CORE (...); +module SGMIICDR_CORE(DCALIRST, DFACQRST, RRST, SPCLK, SRCLK, SRXD9, SRXD8, SRXD7, SRXD6, SRXD5, SRXD4, SRXD3, SRXD2, SRXD1, SRXD0, LMMICLK, LMMIREQUEST, LMMIWRRDN, LMMIOFFSET3, LMMIOFFSET2, LMMIOFFSET1 +, LMMIOFFSET0, LMMIWDATA7, LMMIWDATA6, LMMIWDATA5, LMMIWDATA4, LMMIWDATA3, LMMIWDATA2, LMMIWDATA1, LMMIWDATA0, LMMIRDATA7, LMMIRDATA6, LMMIRDATA5, LMMIRDATA4, LMMIRDATA3, LMMIRDATA2, LMMIRDATA1, LMMIRDATA0, LMMIRDATAVALID, LMMIREADY, LMMIRESETN, RSTBFBW +, RSTBRXF, SGMIIIN, SREFCLK, CDRLOL, OPCGLOADCLK, SCANCLK, SCANRST); parameter GSR = "ENABLED"; parameter DCOITUNE4LSB = "0_PERCENT"; parameter DCOCTLGI = "0_PERCENT"; @@ -10330,20 +10533,20 @@ module SGMIICDR_CORE (...); input SCANRST; endmodule -module GSR (...); +module GSR(GSR_N, CLK); parameter SYNCMODE = "ASYNC"; input GSR_N; input CLK; endmodule -module DCC (...); +module DCC(CE, CLKI, CLKO); parameter DCCEN = "0"; input CE; input CLKI; output CLKO; endmodule -module DCS (...); +module DCS(CLK0, CLK1, DCSOUT, SEL, SELFORCE); parameter DCSMODE = "GND"; input CLK0; input CLK1; @@ -10352,7 +10555,7 @@ module DCS (...); input SELFORCE; endmodule -module GSR_CORE (...); +module GSR_CORE(GSROUT, CLK, GSR_N); parameter GSR = "ENABLED"; parameter GSR_SYNC = "ASYNC"; output GSROUT; @@ -10360,7 +10563,7 @@ module GSR_CORE (...); input GSR_N; endmodule -module PCLKDIV (...); +module PCLKDIV(CLKIN, CLKOUT, LSRPDIV, PCLKDIVTESTINP2, PCLKDIVTESTINP1, PCLKDIVTESTINP0); parameter DIV_PCLKDIV = "X1"; parameter GSR = "ENABLED"; parameter TESTEN_PCLKDIV = "0"; @@ -10374,12 +10577,12 @@ module PCLKDIV (...); endmodule (* keep *) -module PUR (...); +module PUR(PUR); parameter RST_PULSE = "1"; input PUR; endmodule -module PCLKDIVSP (...); +module PCLKDIVSP(CLKIN, CLKOUT, LSRPDIV); parameter DIV_PCLKDIV = "X1"; parameter GSR = "ENABLED"; input CLKIN; diff --git a/techlibs/lattice/cells_bb_xo2.v b/techlibs/lattice/cells_bb_xo2.v index fdf8331b7..ad0b3da14 100644 --- a/techlibs/lattice/cells_bb_xo2.v +++ b/techlibs/lattice/cells_bb_xo2.v @@ -1,18 +1,21 @@ // Created by cells_xtra.py from Lattice models (* blackbox *) (* keep *) -module GSR (...); +module GSR(GSR); input GSR; endmodule (* blackbox *) (* keep *) -module SGSR (...); +module SGSR(GSR, CLK); input GSR; input CLK; endmodule (* blackbox *) -module DP8KC (...); +module DP8KC(DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1 +, ADA0, CEA, OCEA, CLKA, WEA, CSA2, CSA1, CSA0, RSTA, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0, ADB12, ADB11, ADB10 +, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0, CEB, OCEB, CLKB, WEB, CSB2, CSB1, CSB0, RSTB, DOA8, DOA7, DOA6 +, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0); parameter DATA_WIDTH_A = 9; parameter DATA_WIDTH_B = 9; parameter REGMODE_A = "NOREG"; @@ -138,7 +141,10 @@ module DP8KC (...); endmodule (* blackbox *) -module PDPW8KC (...); +module PDPW8KC(DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, ADW8, ADW7, ADW6 +, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5 +, ADR4, ADR3, ADR2, ADR1, ADR0, CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9 +, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0); parameter DATA_WIDTH_W = 18; parameter DATA_WIDTH_R = 9; parameter REGMODE = "NOREG"; @@ -255,7 +261,8 @@ module PDPW8KC (...); endmodule (* blackbox *) -module SP8KC (...); +module SP8KC(DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1 +, AD0, CE, OCE, CLK, WE, CS2, CS1, CS0, RST, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0); parameter DATA_WIDTH = 9; parameter REGMODE = "NOREG"; parameter CSDECODE = "0b000"; @@ -338,7 +345,9 @@ module SP8KC (...); endmodule (* blackbox *) -module FIFO8KB (...); +module FIFO8KB(DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, CSW0, CSW1, CSR0 +, CSR1, WE, RE, ORE, CLKW, CLKR, RST, RPRST, FULLI, EMPTYI, DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10 +, DO11, DO12, DO13, DO14, DO15, DO16, DO17, EF, AEF, AFF, FF); parameter DATA_WIDTH_W = 18; parameter DATA_WIDTH_R = 18; parameter REGMODE = "NOREG"; @@ -409,7 +418,7 @@ module FIFO8KB (...); endmodule (* blackbox *) -module CLKDIVC (...); +module CLKDIVC(RST, CLKI, ALIGNWD, CDIV1, CDIVX); parameter GSR = "DISABLED"; parameter DIV = "2.0"; input RST; @@ -420,7 +429,7 @@ module CLKDIVC (...); endmodule (* blackbox *) -module DCMA (...); +module DCMA(CLK0, CLK1, SEL, DCMOUT); input CLK0; input CLK1; input SEL; @@ -428,14 +437,14 @@ module DCMA (...); endmodule (* blackbox *) -module ECLKSYNCA (...); +module ECLKSYNCA(ECLKI, STOP, ECLKO); input ECLKI; input STOP; output ECLKO; endmodule (* blackbox *) -module ECLKBRIDGECS (...); +module ECLKBRIDGECS(CLK0, CLK1, SEL, ECSOUT); input CLK0; input CLK1; input SEL; @@ -443,19 +452,21 @@ module ECLKBRIDGECS (...); endmodule (* blackbox *) -module DCCA (...); +module DCCA(CLKI, CE, CLKO); input CLKI; input CE; output CLKO; endmodule (* blackbox *) (* keep *) -module START (...); +module START(STARTCLK); input STARTCLK; endmodule (* blackbox *) -module EHXPLLJ (...); +module EHXPLLJ(CLKI, CLKFB, PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE +, PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0, PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0, CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK, PLLDATO7 +, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0, PLLACK, DPHSRC, CLKINTFB); parameter CLKI_DIV = 1; parameter CLKFB_DIV = 1; parameter CLKOP_DIV = 8; @@ -557,7 +568,7 @@ module EHXPLLJ (...); endmodule (* blackbox *) -module OSCH (...); +module OSCH(STDBY, OSC, SEDSTDBY); parameter NOM_FREQ = "2.08"; input STDBY; output OSC; @@ -565,7 +576,7 @@ module OSCH (...); endmodule (* blackbox *) (* keep *) -module TSALL (...); +module TSALL(TSALL); input TSALL; endmodule diff --git a/techlibs/lattice/cells_bb_xo3.v b/techlibs/lattice/cells_bb_xo3.v index fdf8331b7..ad0b3da14 100644 --- a/techlibs/lattice/cells_bb_xo3.v +++ b/techlibs/lattice/cells_bb_xo3.v @@ -1,18 +1,21 @@ // Created by cells_xtra.py from Lattice models (* blackbox *) (* keep *) -module GSR (...); +module GSR(GSR); input GSR; endmodule (* blackbox *) (* keep *) -module SGSR (...); +module SGSR(GSR, CLK); input GSR; input CLK; endmodule (* blackbox *) -module DP8KC (...); +module DP8KC(DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1 +, ADA0, CEA, OCEA, CLKA, WEA, CSA2, CSA1, CSA0, RSTA, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0, ADB12, ADB11, ADB10 +, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0, CEB, OCEB, CLKB, WEB, CSB2, CSB1, CSB0, RSTB, DOA8, DOA7, DOA6 +, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0); parameter DATA_WIDTH_A = 9; parameter DATA_WIDTH_B = 9; parameter REGMODE_A = "NOREG"; @@ -138,7 +141,10 @@ module DP8KC (...); endmodule (* blackbox *) -module PDPW8KC (...); +module PDPW8KC(DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, ADW8, ADW7, ADW6 +, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5 +, ADR4, ADR3, ADR2, ADR1, ADR0, CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9 +, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0); parameter DATA_WIDTH_W = 18; parameter DATA_WIDTH_R = 9; parameter REGMODE = "NOREG"; @@ -255,7 +261,8 @@ module PDPW8KC (...); endmodule (* blackbox *) -module SP8KC (...); +module SP8KC(DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1 +, AD0, CE, OCE, CLK, WE, CS2, CS1, CS0, RST, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0); parameter DATA_WIDTH = 9; parameter REGMODE = "NOREG"; parameter CSDECODE = "0b000"; @@ -338,7 +345,9 @@ module SP8KC (...); endmodule (* blackbox *) -module FIFO8KB (...); +module FIFO8KB(DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, CSW0, CSW1, CSR0 +, CSR1, WE, RE, ORE, CLKW, CLKR, RST, RPRST, FULLI, EMPTYI, DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10 +, DO11, DO12, DO13, DO14, DO15, DO16, DO17, EF, AEF, AFF, FF); parameter DATA_WIDTH_W = 18; parameter DATA_WIDTH_R = 18; parameter REGMODE = "NOREG"; @@ -409,7 +418,7 @@ module FIFO8KB (...); endmodule (* blackbox *) -module CLKDIVC (...); +module CLKDIVC(RST, CLKI, ALIGNWD, CDIV1, CDIVX); parameter GSR = "DISABLED"; parameter DIV = "2.0"; input RST; @@ -420,7 +429,7 @@ module CLKDIVC (...); endmodule (* blackbox *) -module DCMA (...); +module DCMA(CLK0, CLK1, SEL, DCMOUT); input CLK0; input CLK1; input SEL; @@ -428,14 +437,14 @@ module DCMA (...); endmodule (* blackbox *) -module ECLKSYNCA (...); +module ECLKSYNCA(ECLKI, STOP, ECLKO); input ECLKI; input STOP; output ECLKO; endmodule (* blackbox *) -module ECLKBRIDGECS (...); +module ECLKBRIDGECS(CLK0, CLK1, SEL, ECSOUT); input CLK0; input CLK1; input SEL; @@ -443,19 +452,21 @@ module ECLKBRIDGECS (...); endmodule (* blackbox *) -module DCCA (...); +module DCCA(CLKI, CE, CLKO); input CLKI; input CE; output CLKO; endmodule (* blackbox *) (* keep *) -module START (...); +module START(STARTCLK); input STARTCLK; endmodule (* blackbox *) -module EHXPLLJ (...); +module EHXPLLJ(CLKI, CLKFB, PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE +, PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0, PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0, CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK, PLLDATO7 +, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0, PLLACK, DPHSRC, CLKINTFB); parameter CLKI_DIV = 1; parameter CLKFB_DIV = 1; parameter CLKOP_DIV = 8; @@ -557,7 +568,7 @@ module EHXPLLJ (...); endmodule (* blackbox *) -module OSCH (...); +module OSCH(STDBY, OSC, SEDSTDBY); parameter NOM_FREQ = "2.08"; input STDBY; output OSC; @@ -565,7 +576,7 @@ module OSCH (...); endmodule (* blackbox *) (* keep *) -module TSALL (...); +module TSALL(TSALL); input TSALL; endmodule diff --git a/techlibs/lattice/cells_bb_xo3d.v b/techlibs/lattice/cells_bb_xo3d.v index 84d7d9601..e6208e6b4 100644 --- a/techlibs/lattice/cells_bb_xo3d.v +++ b/techlibs/lattice/cells_bb_xo3d.v @@ -1,18 +1,21 @@ // Created by cells_xtra.py from Lattice models (* blackbox *) (* keep *) -module GSR (...); +module GSR(GSR); input GSR; endmodule (* blackbox *) (* keep *) -module SGSR (...); +module SGSR(GSR, CLK); input GSR; input CLK; endmodule (* blackbox *) -module DP8KC (...); +module DP8KC(DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1 +, ADA0, CEA, OCEA, CLKA, WEA, CSA2, CSA1, CSA0, RSTA, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0, ADB12, ADB11, ADB10 +, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0, CEB, OCEB, CLKB, WEB, CSB2, CSB1, CSB0, RSTB, DOA8, DOA7, DOA6 +, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0); parameter DATA_WIDTH_A = 9; parameter DATA_WIDTH_B = 9; parameter REGMODE_A = "NOREG"; @@ -138,7 +141,10 @@ module DP8KC (...); endmodule (* blackbox *) -module PDPW8KC (...); +module PDPW8KC(DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, ADW8, ADW7, ADW6 +, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5 +, ADR4, ADR3, ADR2, ADR1, ADR0, CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9 +, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0); parameter DATA_WIDTH_W = 18; parameter DATA_WIDTH_R = 9; parameter REGMODE = "NOREG"; @@ -255,7 +261,8 @@ module PDPW8KC (...); endmodule (* blackbox *) -module SP8KC (...); +module SP8KC(DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1 +, AD0, CE, OCE, CLK, WE, CS2, CS1, CS0, RST, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0); parameter DATA_WIDTH = 9; parameter REGMODE = "NOREG"; parameter CSDECODE = "0b000"; @@ -338,7 +345,9 @@ module SP8KC (...); endmodule (* blackbox *) -module FIFO8KB (...); +module FIFO8KB(DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, CSW0, CSW1, CSR0 +, CSR1, WE, RE, ORE, CLKW, CLKR, RST, RPRST, FULLI, EMPTYI, DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10 +, DO11, DO12, DO13, DO14, DO15, DO16, DO17, EF, AEF, AFF, FF); parameter DATA_WIDTH_W = 18; parameter DATA_WIDTH_R = 18; parameter REGMODE = "NOREG"; @@ -409,7 +418,7 @@ module FIFO8KB (...); endmodule (* blackbox *) -module CLKDIVC (...); +module CLKDIVC(RST, CLKI, ALIGNWD, CDIV1, CDIVX); parameter GSR = "DISABLED"; parameter DIV = "2.0"; input RST; @@ -420,7 +429,7 @@ module CLKDIVC (...); endmodule (* blackbox *) -module DCMA (...); +module DCMA(CLK0, CLK1, SEL, DCMOUT); input CLK0; input CLK1; input SEL; @@ -428,14 +437,14 @@ module DCMA (...); endmodule (* blackbox *) -module ECLKSYNCA (...); +module ECLKSYNCA(ECLKI, STOP, ECLKO); input ECLKI; input STOP; output ECLKO; endmodule (* blackbox *) -module ECLKBRIDGECS (...); +module ECLKBRIDGECS(CLK0, CLK1, SEL, ECSOUT); input CLK0; input CLK1; input SEL; @@ -443,19 +452,21 @@ module ECLKBRIDGECS (...); endmodule (* blackbox *) -module DCCA (...); +module DCCA(CLKI, CE, CLKO); input CLKI; input CE; output CLKO; endmodule (* blackbox *) (* keep *) -module START (...); +module START(STARTCLK); input STARTCLK; endmodule (* blackbox *) -module EHXPLLJ (...); +module EHXPLLJ(CLKI, CLKFB, PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE +, PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0, PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0, CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK, PLLDATO7 +, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0, PLLACK, DPHSRC, CLKINTFB); parameter CLKI_DIV = 1; parameter CLKFB_DIV = 1; parameter CLKOP_DIV = 8; @@ -557,7 +568,7 @@ module EHXPLLJ (...); endmodule (* blackbox *) -module OSCJ (...); +module OSCJ(STDBY, OSC, SEDSTDBY, OSCESB); parameter NOM_FREQ = "2.08"; input STDBY; output OSC; @@ -566,7 +577,7 @@ module OSCJ (...); endmodule (* blackbox *) (* keep *) -module TSALL (...); +module TSALL(TSALL); input TSALL; endmodule diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index 8dc74b16e..e1736b14e 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -1,6 +1,6 @@ // Created by cells_xtra.py from Xilinx models -module RAMB4_S1 (...); +module RAMB4_S1(DO, ADDR, DI, EN, CLK, WE, RST); parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -27,7 +27,7 @@ module RAMB4_S1 (...); input RST; endmodule -module RAMB4_S2 (...); +module RAMB4_S2(DO, ADDR, DI, EN, CLK, WE, RST); parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -54,7 +54,7 @@ module RAMB4_S2 (...); input RST; endmodule -module RAMB4_S4 (...); +module RAMB4_S4(DO, ADDR, DI, EN, CLK, WE, RST); parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -81,7 +81,7 @@ module RAMB4_S4 (...); input RST; endmodule -module RAMB4_S8 (...); +module RAMB4_S8(DO, ADDR, DI, EN, CLK, WE, RST); parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -108,7 +108,7 @@ module RAMB4_S8 (...); input RST; endmodule -module RAMB4_S16 (...); +module RAMB4_S16(DO, ADDR, DI, EN, CLK, WE, RST); parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -135,7 +135,7 @@ module RAMB4_S16 (...); input RST; endmodule -module RAMB4_S1_S1 (...); +module RAMB4_S1_S1(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -171,7 +171,7 @@ module RAMB4_S1_S1 (...); input RSTB; endmodule -module RAMB4_S1_S2 (...); +module RAMB4_S1_S2(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -207,7 +207,7 @@ module RAMB4_S1_S2 (...); input RSTB; endmodule -module RAMB4_S1_S4 (...); +module RAMB4_S1_S4(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -243,7 +243,7 @@ module RAMB4_S1_S4 (...); input RSTB; endmodule -module RAMB4_S1_S8 (...); +module RAMB4_S1_S8(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -279,7 +279,7 @@ module RAMB4_S1_S8 (...); input RSTB; endmodule -module RAMB4_S1_S16 (...); +module RAMB4_S1_S16(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -315,7 +315,7 @@ module RAMB4_S1_S16 (...); input RSTB; endmodule -module RAMB4_S2_S2 (...); +module RAMB4_S2_S2(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -351,7 +351,7 @@ module RAMB4_S2_S2 (...); input RSTB; endmodule -module RAMB4_S2_S4 (...); +module RAMB4_S2_S4(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -387,7 +387,7 @@ module RAMB4_S2_S4 (...); input RSTB; endmodule -module RAMB4_S2_S8 (...); +module RAMB4_S2_S8(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -423,7 +423,7 @@ module RAMB4_S2_S8 (...); input RSTB; endmodule -module RAMB4_S2_S16 (...); +module RAMB4_S2_S16(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -459,7 +459,7 @@ module RAMB4_S2_S16 (...); input RSTB; endmodule -module RAMB4_S4_S4 (...); +module RAMB4_S4_S4(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -495,7 +495,7 @@ module RAMB4_S4_S4 (...); input RSTB; endmodule -module RAMB4_S4_S8 (...); +module RAMB4_S4_S8(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -531,7 +531,7 @@ module RAMB4_S4_S8 (...); input RSTB; endmodule -module RAMB4_S4_S16 (...); +module RAMB4_S4_S16(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -567,7 +567,7 @@ module RAMB4_S4_S16 (...); input RSTB; endmodule -module RAMB4_S8_S8 (...); +module RAMB4_S8_S8(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -603,7 +603,7 @@ module RAMB4_S8_S8 (...); input RSTB; endmodule -module RAMB4_S8_S16 (...); +module RAMB4_S8_S16(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -639,7 +639,7 @@ module RAMB4_S8_S16 (...); input RSTB; endmodule -module RAMB4_S16_S16 (...); +module RAMB4_S16_S16(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -675,7 +675,7 @@ module RAMB4_S16_S16 (...); input RSTB; endmodule -module RAMB16_S1 (...); +module RAMB16_S1(DO, ADDR, DI, EN, CLK, WE, SSR); parameter [0:0] INIT = 1'h0; parameter [0:0] SRVAL = 1'h0; parameter WRITE_MODE = "WRITE_FIRST"; @@ -753,7 +753,7 @@ module RAMB16_S1 (...); input SSR; endmodule -module RAMB16_S2 (...); +module RAMB16_S2(DO, ADDR, DI, EN, CLK, WE, SSR); parameter [1:0] INIT = 2'h0; parameter [1:0] SRVAL = 2'h0; parameter WRITE_MODE = "WRITE_FIRST"; @@ -831,7 +831,7 @@ module RAMB16_S2 (...); input SSR; endmodule -module RAMB16_S4 (...); +module RAMB16_S4(DO, ADDR, DI, EN, CLK, WE, SSR); parameter [3:0] INIT = 4'h0; parameter [3:0] SRVAL = 4'h0; parameter WRITE_MODE = "WRITE_FIRST"; @@ -909,7 +909,7 @@ module RAMB16_S4 (...); input SSR; endmodule -module RAMB16_S9 (...); +module RAMB16_S9(DO, DOP, ADDR, DI, DIP, EN, CLK, WE, SSR); parameter [8:0] INIT = 9'h0; parameter [8:0] SRVAL = 9'h0; parameter WRITE_MODE = "WRITE_FIRST"; @@ -997,7 +997,7 @@ module RAMB16_S9 (...); input SSR; endmodule -module RAMB16_S18 (...); +module RAMB16_S18(DO, DOP, ADDR, DI, DIP, EN, CLK, WE, SSR); parameter [17:0] INIT = 18'h0; parameter [17:0] SRVAL = 18'h0; parameter WRITE_MODE = "WRITE_FIRST"; @@ -1085,7 +1085,7 @@ module RAMB16_S18 (...); input SSR; endmodule -module RAMB16_S36 (...); +module RAMB16_S36(DO, DOP, ADDR, DI, DIP, EN, CLK, WE, SSR); parameter [35:0] INIT = 36'h0; parameter [35:0] SRVAL = 36'h0; parameter WRITE_MODE = "WRITE_FIRST"; @@ -1173,7 +1173,7 @@ module RAMB16_S36 (...); input SSR; endmodule -module RAMB16_S1_S1 (...); +module RAMB16_S1_S1(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, ADDRB, DIB, ENB, CLKB, WEB, SSRB); parameter [0:0] INIT_A = 1'h0; parameter [0:0] INIT_B = 1'h0; parameter [0:0] SRVAL_A = 1'h0; @@ -1263,7 +1263,7 @@ module RAMB16_S1_S1 (...); input SSRB; endmodule -module RAMB16_S1_S2 (...); +module RAMB16_S1_S2(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, ADDRB, DIB, ENB, CLKB, WEB, SSRB); parameter [0:0] INIT_A = 1'h0; parameter [1:0] INIT_B = 2'h0; parameter [0:0] SRVAL_A = 1'h0; @@ -1353,7 +1353,7 @@ module RAMB16_S1_S2 (...); input SSRB; endmodule -module RAMB16_S1_S4 (...); +module RAMB16_S1_S4(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, ADDRB, DIB, ENB, CLKB, WEB, SSRB); parameter [0:0] INIT_A = 1'h0; parameter [3:0] INIT_B = 4'h0; parameter [0:0] SRVAL_A = 1'h0; @@ -1443,7 +1443,7 @@ module RAMB16_S1_S4 (...); input SSRB; endmodule -module RAMB16_S1_S9 (...); +module RAMB16_S1_S9(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [0:0] INIT_A = 1'h0; parameter [8:0] INIT_B = 9'h0; parameter [0:0] SRVAL_A = 1'h0; @@ -1543,7 +1543,7 @@ module RAMB16_S1_S9 (...); input SSRB; endmodule -module RAMB16_S1_S18 (...); +module RAMB16_S1_S18(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [0:0] INIT_A = 1'h0; parameter [17:0] INIT_B = 18'h0; parameter [0:0] SRVAL_A = 1'h0; @@ -1643,7 +1643,7 @@ module RAMB16_S1_S18 (...); input SSRB; endmodule -module RAMB16_S1_S36 (...); +module RAMB16_S1_S36(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [0:0] INIT_A = 1'h0; parameter [35:0] INIT_B = 36'h0; parameter [0:0] SRVAL_A = 1'h0; @@ -1743,7 +1743,7 @@ module RAMB16_S1_S36 (...); input SSRB; endmodule -module RAMB16_S2_S2 (...); +module RAMB16_S2_S2(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, ADDRB, DIB, ENB, CLKB, WEB, SSRB); parameter [1:0] INIT_A = 2'h0; parameter [1:0] INIT_B = 2'h0; parameter [1:0] SRVAL_A = 2'h0; @@ -1833,7 +1833,7 @@ module RAMB16_S2_S2 (...); input SSRB; endmodule -module RAMB16_S2_S4 (...); +module RAMB16_S2_S4(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, ADDRB, DIB, ENB, CLKB, WEB, SSRB); parameter [1:0] INIT_A = 2'h0; parameter [3:0] INIT_B = 4'h0; parameter [1:0] SRVAL_A = 2'h0; @@ -1923,7 +1923,7 @@ module RAMB16_S2_S4 (...); input SSRB; endmodule -module RAMB16_S2_S9 (...); +module RAMB16_S2_S9(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [1:0] INIT_A = 2'h0; parameter [8:0] INIT_B = 9'h0; parameter [1:0] SRVAL_A = 2'h0; @@ -2023,7 +2023,7 @@ module RAMB16_S2_S9 (...); input SSRB; endmodule -module RAMB16_S2_S18 (...); +module RAMB16_S2_S18(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [1:0] INIT_A = 2'h0; parameter [17:0] INIT_B = 18'h0; parameter [1:0] SRVAL_A = 2'h0; @@ -2123,7 +2123,7 @@ module RAMB16_S2_S18 (...); input SSRB; endmodule -module RAMB16_S2_S36 (...); +module RAMB16_S2_S36(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [1:0] INIT_A = 2'h0; parameter [35:0] INIT_B = 36'h0; parameter [1:0] SRVAL_A = 2'h0; @@ -2223,7 +2223,7 @@ module RAMB16_S2_S36 (...); input SSRB; endmodule -module RAMB16_S4_S4 (...); +module RAMB16_S4_S4(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, ADDRB, DIB, ENB, CLKB, WEB, SSRB); parameter [3:0] INIT_A = 4'h0; parameter [3:0] INIT_B = 4'h0; parameter [3:0] SRVAL_A = 4'h0; @@ -2313,7 +2313,7 @@ module RAMB16_S4_S4 (...); input SSRB; endmodule -module RAMB16_S4_S9 (...); +module RAMB16_S4_S9(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [3:0] INIT_A = 4'h0; parameter [8:0] INIT_B = 9'h0; parameter [3:0] SRVAL_A = 4'h0; @@ -2413,7 +2413,7 @@ module RAMB16_S4_S9 (...); input SSRB; endmodule -module RAMB16_S4_S18 (...); +module RAMB16_S4_S18(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [3:0] INIT_A = 4'h0; parameter [17:0] INIT_B = 18'h0; parameter [3:0] SRVAL_A = 4'h0; @@ -2513,7 +2513,7 @@ module RAMB16_S4_S18 (...); input SSRB; endmodule -module RAMB16_S4_S36 (...); +module RAMB16_S4_S36(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [3:0] INIT_A = 4'h0; parameter [35:0] INIT_B = 36'h0; parameter [3:0] SRVAL_A = 4'h0; @@ -2613,7 +2613,7 @@ module RAMB16_S4_S36 (...); input SSRB; endmodule -module RAMB16_S9_S9 (...); +module RAMB16_S9_S9(DOA, DOPA, ADDRA, DIA, DIPA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [8:0] INIT_A = 9'h0; parameter [8:0] INIT_B = 9'h0; parameter [8:0] SRVAL_A = 9'h0; @@ -2715,7 +2715,7 @@ module RAMB16_S9_S9 (...); input SSRB; endmodule -module RAMB16_S9_S18 (...); +module RAMB16_S9_S18(DOA, DOPA, ADDRA, DIA, DIPA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [8:0] INIT_A = 9'h0; parameter [17:0] INIT_B = 18'h0; parameter [8:0] SRVAL_A = 9'h0; @@ -2817,7 +2817,7 @@ module RAMB16_S9_S18 (...); input SSRB; endmodule -module RAMB16_S9_S36 (...); +module RAMB16_S9_S36(DOA, DOPA, ADDRA, DIA, DIPA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [8:0] INIT_A = 9'h0; parameter [35:0] INIT_B = 36'h0; parameter [8:0] SRVAL_A = 9'h0; @@ -2919,7 +2919,7 @@ module RAMB16_S9_S36 (...); input SSRB; endmodule -module RAMB16_S18_S18 (...); +module RAMB16_S18_S18(DOA, DOPA, ADDRA, DIA, DIPA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [17:0] INIT_A = 18'h0; parameter [17:0] INIT_B = 18'h0; parameter [17:0] SRVAL_A = 18'h0; @@ -3021,7 +3021,7 @@ module RAMB16_S18_S18 (...); input SSRB; endmodule -module RAMB16_S18_S36 (...); +module RAMB16_S18_S36(DOA, DOPA, ADDRA, DIA, DIPA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [17:0] INIT_A = 18'h0; parameter [35:0] INIT_B = 36'h0; parameter [17:0] SRVAL_A = 18'h0; @@ -3123,7 +3123,7 @@ module RAMB16_S18_S36 (...); input SSRB; endmodule -module RAMB16_S36_S36 (...); +module RAMB16_S36_S36(DOA, DOPA, ADDRA, DIA, DIPA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [35:0] INIT_A = 36'h0; parameter [35:0] INIT_B = 36'h0; parameter [35:0] SRVAL_A = 36'h0; @@ -3225,7 +3225,7 @@ module RAMB16_S36_S36 (...); input SSRB; endmodule -module RAMB16BWE_S18 (...); +module RAMB16BWE_S18(DO, DOP, CLK, EN, SSR, WE, DI, DIP, ADDR); parameter [17:0] INIT = 18'h0; parameter [255:0] INITP_00 = 256'h0; parameter [255:0] INITP_01 = 256'h0; @@ -3313,7 +3313,7 @@ module RAMB16BWE_S18 (...); input [9:0] ADDR; endmodule -module RAMB16BWE_S36 (...); +module RAMB16BWE_S36(DO, DOP, CLK, EN, SSR, WE, DI, DIP, ADDR); parameter [35:0] INIT = 36'h0; parameter [255:0] INITP_00 = 256'h0; parameter [255:0] INITP_01 = 256'h0; @@ -3401,7 +3401,7 @@ module RAMB16BWE_S36 (...); input [8:0] ADDR; endmodule -module RAMB16BWE_S18_S9 (...); +module RAMB16BWE_S18_S9(DOA, DOB, DOPA, DOPB, CLKA, CLKB, ENA, ENB, SSRA, SSRB, WEB, WEA, DIA, DIB, DIPA, DIPB, ADDRA, ADDRB); parameter [255:0] INITP_00 = 256'h0; parameter [255:0] INITP_01 = 256'h0; parameter [255:0] INITP_02 = 256'h0; @@ -3503,7 +3503,7 @@ module RAMB16BWE_S18_S9 (...); input [10:0] ADDRB; endmodule -module RAMB16BWE_S18_S18 (...); +module RAMB16BWE_S18_S18(DOA, DOB, DOPA, DOPB, CLKA, CLKB, ENA, ENB, SSRA, SSRB, WEB, WEA, DIA, DIB, DIPA, DIPB, ADDRA, ADDRB); parameter [255:0] INITP_00 = 256'h0; parameter [255:0] INITP_01 = 256'h0; parameter [255:0] INITP_02 = 256'h0; @@ -3605,7 +3605,7 @@ module RAMB16BWE_S18_S18 (...); input [9:0] ADDRB; endmodule -module RAMB16BWE_S36_S9 (...); +module RAMB16BWE_S36_S9(DOA, DOPA, DOB, DOPB, CLKA, CLKB, ENA, ENB, SSRA, SSRB, WEA, WEB, DIA, DIPA, DIB, DIPB, ADDRA, ADDRB); parameter [255:0] INITP_00 = 256'h0; parameter [255:0] INITP_01 = 256'h0; parameter [255:0] INITP_02 = 256'h0; @@ -3707,7 +3707,7 @@ module RAMB16BWE_S36_S9 (...); input [10:0] ADDRB; endmodule -module RAMB16BWE_S36_S18 (...); +module RAMB16BWE_S36_S18(DOA, DOPA, DOB, DOPB, CLKA, CLKB, ENA, ENB, SSRA, SSRB, WEA, WEB, DIA, DIPA, DIB, DIPB, ADDRA, ADDRB); parameter [255:0] INITP_00 = 256'h0; parameter [255:0] INITP_01 = 256'h0; parameter [255:0] INITP_02 = 256'h0; @@ -3809,7 +3809,7 @@ module RAMB16BWE_S36_S18 (...); input [9:0] ADDRB; endmodule -module RAMB16BWE_S36_S36 (...); +module RAMB16BWE_S36_S36(DOA, DOPA, DOB, DOPB, CLKA, CLKB, ENA, ENB, SSRA, SSRB, WEA, WEB, DIA, DIPA, DIB, DIPB, ADDRA, ADDRB); parameter [255:0] INITP_00 = 256'h0; parameter [255:0] INITP_01 = 256'h0; parameter [255:0] INITP_02 = 256'h0; @@ -3911,7 +3911,7 @@ module RAMB16BWE_S36_S36 (...); input [8:0] ADDRB; endmodule -module RAMB16BWER (...); +module RAMB16BWER(DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, REGCEA, REGCEB, RSTA, RSTB, WEA, WEB); parameter integer DATA_WIDTH_A = 0; parameter integer DATA_WIDTH_B = 0; parameter integer DOA_REG = 0; @@ -4028,7 +4028,7 @@ module RAMB16BWER (...); input [3:0] WEB; endmodule -module RAMB8BWER (...); +module RAMB8BWER(DOADO, DOBDO, DOPADOP, DOPBDOP, ADDRAWRADDR, ADDRBRDADDR, CLKAWRCLK, CLKBRDCLK, DIADI, DIBDI, DIPADIP, DIPBDIP, ENAWREN, ENBRDEN, REGCEA, REGCEBREGCE, RSTA, RSTBRST, WEAWEL, WEBWEU); parameter integer DATA_WIDTH_A = 0; parameter integer DATA_WIDTH_B = 0; parameter integer DOA_REG = 0; @@ -4109,7 +4109,7 @@ module RAMB8BWER (...); input [1:0] WEBWEU; endmodule -module FIFO16 (...); +module FIFO16(ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN); parameter [11:0] ALMOST_FULL_OFFSET = 12'h080; parameter [11:0] ALMOST_EMPTY_OFFSET = 12'h080; parameter integer DATA_WIDTH = 36; @@ -4135,7 +4135,8 @@ module FIFO16 (...); input WREN; endmodule -module RAMB16 (...); +module RAMB16(CASCADEOUTA, CASCADEOUTB, DOA, DOB, DOPA, DOPB, ENA, CLKA, SSRA, CASCADEINA, REGCEA, ENB, CLKB, SSRB, CASCADEINB, REGCEB, ADDRA, ADDRB, DIA, DIB, DIPA +, DIPB, WEA, WEB); parameter integer DOA_REG = 0; parameter integer DOB_REG = 0; parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -4254,7 +4255,7 @@ module RAMB16 (...); input [3:0] WEB; endmodule -module RAMB32_S64_ECC (...); +module RAMB32_S64_ECC(STATUS, DO, RDCLK, RDEN, SSR, WRCLK, WREN, DI, RDADDR, WRADDR); parameter DO_REG = 0; parameter SIM_COLLISION_CHECK = "ALL"; output [1:0] STATUS; @@ -4271,7 +4272,7 @@ module RAMB32_S64_ECC (...); input [8:0] WRADDR; endmodule -module FIFO18 (...); +module FIFO18(ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN); parameter [11:0] ALMOST_EMPTY_OFFSET = 12'h080; parameter [11:0] ALMOST_FULL_OFFSET = 12'h080; parameter integer DATA_WIDTH = 4; @@ -4300,7 +4301,7 @@ module FIFO18 (...); input WREN; endmodule -module FIFO18_36 (...); +module FIFO18_36(ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN); parameter [8:0] ALMOST_EMPTY_OFFSET = 9'h080; parameter [8:0] ALMOST_FULL_OFFSET = 9'h080; parameter integer DO_REG = 1; @@ -4328,7 +4329,7 @@ module FIFO18_36 (...); input WREN; endmodule -module FIFO36 (...); +module FIFO36(ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN); parameter [12:0] ALMOST_EMPTY_OFFSET = 13'h080; parameter [12:0] ALMOST_FULL_OFFSET = 13'h080; parameter integer DATA_WIDTH = 4; @@ -4357,7 +4358,7 @@ module FIFO36 (...); input WREN; endmodule -module FIFO36_72 (...); +module FIFO36_72(ALMOSTEMPTY, ALMOSTFULL, DBITERR, DO, DOP, ECCPARITY, EMPTY, FULL, RDCOUNT, RDERR, SBITERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN); parameter [8:0] ALMOST_EMPTY_OFFSET = 9'h080; parameter [8:0] ALMOST_FULL_OFFSET = 9'h080; parameter integer DO_REG = 1; @@ -4390,7 +4391,7 @@ module FIFO36_72 (...); input WREN; endmodule -module RAMB18 (...); +module RAMB18(DOA, DOB, DOPA, DOPB, ENA, CLKA, SSRA, REGCEA, ENB, CLKB, SSRB, REGCEB, ADDRA, ADDRB, DIA, DIB, DIPA, DIPB, WEA, WEB); parameter integer DOA_REG = 0; parameter integer DOB_REG = 0; parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -4502,7 +4503,8 @@ module RAMB18 (...); input [1:0] WEB; endmodule -module RAMB36 (...); +module RAMB36(CASCADEOUTLATA, CASCADEOUTREGA, CASCADEOUTLATB, CASCADEOUTREGB, DOA, DOB, DOPA, DOPB, ENA, CLKA, SSRA, CASCADEINLATA, CASCADEINREGA, REGCEA, ENB, CLKB, SSRB, CASCADEINLATB, CASCADEINREGB, REGCEB, ADDRA +, ADDRB, DIA, DIB, DIPA, DIPB, WEA, WEB); parameter integer DOA_REG = 0; parameter integer DOB_REG = 0; parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -4696,7 +4698,7 @@ module RAMB36 (...); input [3:0] WEB; endmodule -module RAMB18SDP (...); +module RAMB18SDP(DO, DOP, RDCLK, RDEN, REGCE, SSR, WRCLK, WREN, WRADDR, RDADDR, DI, DIP, WE); parameter integer DO_REG = 0; parameter [35:0] INIT = 36'h0; parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -4792,7 +4794,7 @@ module RAMB18SDP (...); input [3:0] WE; endmodule -module RAMB36SDP (...); +module RAMB36SDP(DBITERR, SBITERR, DO, DOP, ECCPARITY, RDCLK, RDEN, REGCE, SSR, WRCLK, WREN, WRADDR, RDADDR, DI, DIP, WE); parameter integer DO_REG = 0; parameter EN_ECC_READ = "FALSE"; parameter EN_ECC_SCRUB = "FALSE"; @@ -4966,7 +4968,7 @@ module RAMB36SDP (...); input [7:0] WE; endmodule -module FIFO18E1 (...); +module FIFO18E1(ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, REGCE, RST, RSTREG, WRCLK, WREN); parameter ALMOST_EMPTY_OFFSET = 13'h0080; parameter ALMOST_FULL_OFFSET = 13'h0080; parameter integer DATA_WIDTH = 4; @@ -5012,7 +5014,8 @@ module FIFO18E1 (...); input WREN; endmodule -module FIFO36E1 (...); +module FIFO36E1(ALMOSTEMPTY, ALMOSTFULL, DBITERR, DO, DOP, ECCPARITY, EMPTY, FULL, RDCOUNT, RDERR, SBITERR, WRCOUNT, WRERR, DI, DIP, INJECTDBITERR, INJECTSBITERR, RDCLK, RDEN, REGCE, RST +, RSTREG, WRCLK, WREN); parameter ALMOST_EMPTY_OFFSET = 13'h0080; parameter ALMOST_FULL_OFFSET = 13'h0080; parameter integer DATA_WIDTH = 4; @@ -5065,7 +5068,8 @@ module FIFO36E1 (...); input WREN; endmodule -module FIFO18E2 (...); +module FIFO18E2(CASDOUT, CASDOUTP, CASNXTEMPTY, CASPRVRDEN, DOUT, DOUTP, EMPTY, FULL, PROGEMPTY, PROGFULL, RDCOUNT, RDERR, RDRSTBUSY, WRCOUNT, WRERR, WRRSTBUSY, CASDIN, CASDINP, CASDOMUX, CASDOMUXEN, CASNXTRDEN +, CASOREGIMUX, CASOREGIMUXEN, CASPRVEMPTY, DIN, DINP, RDCLK, RDEN, REGCE, RST, RSTREG, SLEEP, WRCLK, WREN); parameter CASCADE_ORDER = "NONE"; parameter CLOCK_DOMAINS = "INDEPENDENT"; parameter FIRST_WORD_FALL_THROUGH = "FALSE"; @@ -5130,7 +5134,8 @@ module FIFO18E2 (...); input WREN; endmodule -module FIFO36E2 (...); +module FIFO36E2(CASDOUT, CASDOUTP, CASNXTEMPTY, CASPRVRDEN, DBITERR, DOUT, DOUTP, ECCPARITY, EMPTY, FULL, PROGEMPTY, PROGFULL, RDCOUNT, RDERR, RDRSTBUSY, SBITERR, WRCOUNT, WRERR, WRRSTBUSY, CASDIN, CASDINP +, CASDOMUX, CASDOMUXEN, CASNXTRDEN, CASOREGIMUX, CASOREGIMUXEN, CASPRVEMPTY, DIN, DINP, INJECTDBITERR, INJECTSBITERR, RDCLK, RDEN, REGCE, RST, RSTREG, SLEEP, WRCLK, WREN); parameter CASCADE_ORDER = "NONE"; parameter CLOCK_DOMAINS = "INDEPENDENT"; parameter EN_ECC_PIPE = "FALSE"; @@ -5203,7 +5208,9 @@ module FIFO36E2 (...); input WREN; endmodule -module RAMB18E2 (...); +module RAMB18E2(CASDOUTA, CASDOUTB, CASDOUTPA, CASDOUTPB, DOUTADOUT, DOUTBDOUT, DOUTPADOUTP, DOUTPBDOUTP, ADDRARDADDR, ADDRBWRADDR, ADDRENA, ADDRENB, CASDIMUXA, CASDIMUXB, CASDINA, CASDINB, CASDINPA, CASDINPB, CASDOMUXA, CASDOMUXB, CASDOMUXEN_A +, CASDOMUXEN_B, CASOREGIMUXA, CASOREGIMUXB, CASOREGIMUXEN_A, CASOREGIMUXEN_B, CLKARDCLK, CLKBWRCLK, DINADIN, DINBDIN, DINPADINP, DINPBDINP, ENARDEN, ENBWREN, REGCEAREGCE, REGCEB, RSTRAMARSTRAM, RSTRAMB, RSTREGARSTREG, RSTREGB, SLEEP, WEA +, WEBWE); parameter CASCADE_ORDER_A = "NONE"; parameter CASCADE_ORDER_B = "NONE"; parameter CLOCK_DOMAINS = "INDEPENDENT"; @@ -5363,7 +5370,9 @@ module RAMB18E2 (...); input [3:0] WEBWE; endmodule -module RAMB36E2 (...); +module RAMB36E2(CASDOUTA, CASDOUTB, CASDOUTPA, CASDOUTPB, CASOUTDBITERR, CASOUTSBITERR, DBITERR, DOUTADOUT, DOUTBDOUT, DOUTPADOUTP, DOUTPBDOUTP, ECCPARITY, RDADDRECC, SBITERR, ADDRARDADDR, ADDRBWRADDR, ADDRENA, ADDRENB, CASDIMUXA, CASDIMUXB, CASDINA +, CASDINB, CASDINPA, CASDINPB, CASDOMUXA, CASDOMUXB, CASDOMUXEN_A, CASDOMUXEN_B, CASINDBITERR, CASINSBITERR, CASOREGIMUXA, CASOREGIMUXB, CASOREGIMUXEN_A, CASOREGIMUXEN_B, CLKARDCLK, CLKBWRCLK, DINADIN, DINBDIN, DINPADINP, DINPBDINP, ECCPIPECE, ENARDEN +, ENBWREN, INJECTDBITERR, INJECTSBITERR, REGCEAREGCE, REGCEB, RSTRAMARSTRAM, RSTRAMB, RSTREGARSTREG, RSTREGB, SLEEP, WEA, WEBWE); parameter CASCADE_ORDER_A = "NONE"; parameter CASCADE_ORDER_B = "NONE"; parameter CLOCK_DOMAINS = "INDEPENDENT"; @@ -5609,7 +5618,10 @@ module RAMB36E2 (...); input [7:0] WEBWE; endmodule -module URAM288 (...); +module URAM288(CAS_OUT_ADDR_A, CAS_OUT_ADDR_B, CAS_OUT_BWE_A, CAS_OUT_BWE_B, CAS_OUT_DBITERR_A, CAS_OUT_DBITERR_B, CAS_OUT_DIN_A, CAS_OUT_DIN_B, CAS_OUT_DOUT_A, CAS_OUT_DOUT_B, CAS_OUT_EN_A, CAS_OUT_EN_B, CAS_OUT_RDACCESS_A, CAS_OUT_RDACCESS_B, CAS_OUT_RDB_WR_A, CAS_OUT_RDB_WR_B, CAS_OUT_SBITERR_A, CAS_OUT_SBITERR_B, DBITERR_A, DBITERR_B, DOUT_A +, DOUT_B, RDACCESS_A, RDACCESS_B, SBITERR_A, SBITERR_B, ADDR_A, ADDR_B, BWE_A, BWE_B, CAS_IN_ADDR_A, CAS_IN_ADDR_B, CAS_IN_BWE_A, CAS_IN_BWE_B, CAS_IN_DBITERR_A, CAS_IN_DBITERR_B, CAS_IN_DIN_A, CAS_IN_DIN_B, CAS_IN_DOUT_A, CAS_IN_DOUT_B, CAS_IN_EN_A, CAS_IN_EN_B +, CAS_IN_RDACCESS_A, CAS_IN_RDACCESS_B, CAS_IN_RDB_WR_A, CAS_IN_RDB_WR_B, CAS_IN_SBITERR_A, CAS_IN_SBITERR_B, CLK, DIN_A, DIN_B, EN_A, EN_B, INJECT_DBITERR_A, INJECT_DBITERR_B, INJECT_SBITERR_A, INJECT_SBITERR_B, OREG_CE_A, OREG_CE_B, OREG_ECC_CE_A, OREG_ECC_CE_B, RDB_WR_A, RDB_WR_B +, RST_A, RST_B, SLEEP); parameter integer AUTO_SLEEP_LATENCY = 8; parameter integer AVG_CONS_INACTIVE_CYCLES = 10; parameter BWE_MODE_A = "PARITY_INTERLEAVED"; @@ -5724,7 +5736,8 @@ module URAM288 (...); input SLEEP; endmodule -module URAM288_BASE (...); +module URAM288_BASE(DBITERR_A, DBITERR_B, DOUT_A, DOUT_B, SBITERR_A, SBITERR_B, ADDR_A, ADDR_B, BWE_A, BWE_B, CLK, DIN_A, DIN_B, EN_A, EN_B, INJECT_DBITERR_A, INJECT_DBITERR_B, INJECT_SBITERR_A, INJECT_SBITERR_B, OREG_CE_A, OREG_CE_B +, OREG_ECC_CE_A, OREG_ECC_CE_B, RDB_WR_A, RDB_WR_B, RST_A, RST_B, SLEEP); parameter integer AUTO_SLEEP_LATENCY = 8; parameter integer AVG_CONS_INACTIVE_CYCLES = 10; parameter BWE_MODE_A = "PARITY_INTERLEAVED"; @@ -5789,7 +5802,9 @@ module URAM288_BASE (...); input SLEEP; endmodule -module DSP48E (...); +module DSP48E(ACOUT, BCOUT, CARRYCASCOUT, CARRYOUT, MULTSIGNOUT, OVERFLOW, P, PATTERNBDETECT, PATTERNDETECT, PCOUT, UNDERFLOW, A, ACIN, ALUMODE, B, BCIN, C, CARRYCASCIN, CARRYIN, CARRYINSEL, CEA1 +, CEA2, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL, CEM, CEMULTCARRYIN, CEP, CLK, MULTSIGNIN, OPMODE, PCIN, RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTM +, RSTP); parameter SIM_MODE = "SAFE"; parameter integer ACASCREG = 1; parameter integer ALUMODEREG = 1; @@ -5861,7 +5876,9 @@ module DSP48E (...); input RSTP; endmodule -module DSP48E2 (...); +module DSP48E2(ACOUT, BCOUT, CARRYCASCOUT, CARRYOUT, MULTSIGNOUT, OVERFLOW, P, PATTERNBDETECT, PATTERNDETECT, PCOUT, UNDERFLOW, XOROUT, A, ACIN, ALUMODE, B, BCIN, C, CARRYCASCIN, CARRYIN, CARRYINSEL +, CEA1, CEA2, CEAD, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL, CED, CEINMODE, CEM, CEP, CLK, D, INMODE, MULTSIGNIN, OPMODE, PCIN, RSTA, RSTALLCARRYIN +, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP); parameter integer ACASCREG = 1; parameter integer ADREG = 1; parameter integer ALUMODEREG = 1; @@ -5976,7 +5993,7 @@ module DSP48E2 (...); input RSTP; endmodule -module FDDRCPE (...); +module FDDRCPE(C0, C1, CE, D0, D1, CLR, PRE, Q); parameter INIT = 1'b0; (* clkbuf_sink *) input C0; @@ -5990,7 +6007,7 @@ module FDDRCPE (...); output Q; endmodule -module FDDRRSE (...); +module FDDRRSE(Q, C0, C1, CE, D0, D1, R, S); parameter INIT = 1'b0; output Q; (* clkbuf_sink *) @@ -6004,7 +6021,7 @@ module FDDRRSE (...); input S; endmodule -module IFDDRCPE (...); +module IFDDRCPE(Q0, Q1, C0, C1, CE, CLR, D, PRE); output Q0; output Q1; (* clkbuf_sink *) @@ -6018,7 +6035,7 @@ module IFDDRCPE (...); input PRE; endmodule -module IFDDRRSE (...); +module IFDDRRSE(Q0, Q1, C0, C1, CE, D, R, S); output Q0; output Q1; (* clkbuf_sink *) @@ -6032,7 +6049,7 @@ module IFDDRRSE (...); input S; endmodule -module OFDDRCPE (...); +module OFDDRCPE(Q, C0, C1, CE, CLR, D0, D1, PRE); (* iopad_external_pin *) output Q; (* clkbuf_sink *) @@ -6046,7 +6063,7 @@ module OFDDRCPE (...); input PRE; endmodule -module OFDDRRSE (...); +module OFDDRRSE(Q, C0, C1, CE, D0, D1, R, S); (* iopad_external_pin *) output Q; (* clkbuf_sink *) @@ -6060,7 +6077,7 @@ module OFDDRRSE (...); input S; endmodule -module OFDDRTCPE (...); +module OFDDRTCPE(O, C0, C1, CE, CLR, D0, D1, PRE, T); (* iopad_external_pin *) output O; (* clkbuf_sink *) @@ -6075,7 +6092,7 @@ module OFDDRTCPE (...); input T; endmodule -module OFDDRTRSE (...); +module OFDDRTRSE(O, C0, C1, CE, D0, D1, R, S, T); (* iopad_external_pin *) output O; (* clkbuf_sink *) @@ -6090,7 +6107,7 @@ module OFDDRTRSE (...); input T; endmodule -module IDDR2 (...); +module IDDR2(Q0, Q1, C0, C1, CE, D, R, S); parameter DDR_ALIGNMENT = "NONE"; parameter [0:0] INIT_Q0 = 1'b0; parameter [0:0] INIT_Q1 = 1'b0; @@ -6107,7 +6124,7 @@ module IDDR2 (...); input S; endmodule -module ODDR2 (...); +module ODDR2(Q, C0, C1, CE, D0, D1, R, S); parameter DDR_ALIGNMENT = "NONE"; parameter [0:0] INIT = 1'b0; parameter SRTYPE = "SYNC"; @@ -6123,7 +6140,7 @@ module ODDR2 (...); input S; endmodule -module IDDR (...); +module IDDR(Q1, Q2, C, CE, D, R, S); parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; parameter INIT_Q1 = 1'b0; parameter INIT_Q2 = 1'b0; @@ -6144,7 +6161,7 @@ module IDDR (...); input S; endmodule -module IDDR_2CLK (...); +module IDDR_2CLK(Q1, Q2, C, CB, CE, D, R, S); parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; parameter INIT_Q1 = 1'b0; parameter INIT_Q2 = 1'b0; @@ -6167,7 +6184,7 @@ module IDDR_2CLK (...); input S; endmodule -module ODDR (...); +module ODDR(Q, C, CE, D1, D2, R, S); parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; parameter INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; @@ -6190,7 +6207,7 @@ module ODDR (...); endmodule (* keep *) -module IDELAYCTRL (...); +module IDELAYCTRL(RDY, REFCLK, RST); parameter SIM_DEVICE = "7SERIES"; output RDY; (* clkbuf_sink *) @@ -6198,7 +6215,7 @@ module IDELAYCTRL (...); input RST; endmodule -module IDELAY (...); +module IDELAY(O, C, CE, I, INC, RST); parameter IOBDELAY_TYPE = "DEFAULT"; parameter integer IOBDELAY_VALUE = 0; output O; @@ -6210,7 +6227,8 @@ module IDELAY (...); input RST; endmodule -module ISERDES (...); +module ISERDES(O, Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2, BITSLIP, CE1, CE2, CLK, CLKDIV, D, DLYCE, DLYINC, DLYRST, OCLK, REV, SHIFTIN1 +, SHIFTIN2, SR); parameter BITSLIP_ENABLE = "FALSE"; parameter DATA_RATE = "DDR"; parameter integer DATA_WIDTH = 4; @@ -6259,7 +6277,8 @@ module ISERDES (...); input SR; endmodule -module OSERDES (...); +module OSERDES(OQ, SHIFTOUT1, SHIFTOUT2, TQ, CLK, CLKDIV, D1, D2, D3, D4, D5, D6, OCE, REV, SHIFTIN1, SHIFTIN2, SR, T1, T2, T3, T4 +, TCE); parameter DATA_RATE_OQ = "DDR"; parameter DATA_RATE_TQ = "DDR"; parameter integer DATA_WIDTH = 4; @@ -6295,7 +6314,7 @@ module OSERDES (...); input TCE; endmodule -module IODELAY (...); +module IODELAY(DATAOUT, C, CE, DATAIN, IDATAIN, INC, ODATAIN, RST, T); parameter DELAY_SRC = "I"; parameter HIGH_PERFORMANCE_MODE = "TRUE"; parameter IDELAY_TYPE = "DEFAULT"; @@ -6315,7 +6334,7 @@ module IODELAY (...); input T; endmodule -module ISERDES_NODELAY (...); +module ISERDES_NODELAY(Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2, BITSLIP, CE1, CE2, CLK, CLKB, CLKDIV, D, OCLK, RST, SHIFTIN1, SHIFTIN2); parameter BITSLIP_ENABLE = "FALSE"; parameter DATA_RATE = "DDR"; parameter integer DATA_WIDTH = 4; @@ -6351,7 +6370,7 @@ module ISERDES_NODELAY (...); input SHIFTIN2; endmodule -module IODELAYE1 (...); +module IODELAYE1(CNTVALUEOUT, DATAOUT, C, CE, CINVCTRL, CLKIN, CNTVALUEIN, DATAIN, IDATAIN, INC, ODATAIN, RST, T); parameter CINVCTRL_SEL = "FALSE"; parameter DELAY_SRC = "I"; parameter HIGH_PERFORMANCE_MODE = "FALSE"; @@ -6377,7 +6396,8 @@ module IODELAYE1 (...); input T; endmodule -module ISERDESE1 (...); +module ISERDESE1(O, Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2, BITSLIP, CE1, CE2, CLK, CLKB, CLKDIV, D, DDLY, DYNCLKDIVSEL, DYNCLKSEL, OCLK, OFB +, RST, SHIFTIN1, SHIFTIN2); parameter DATA_RATE = "DDR"; parameter integer DATA_WIDTH = 4; parameter DYN_CLKDIV_INV_EN = "FALSE"; @@ -6425,7 +6445,8 @@ module ISERDESE1 (...); input SHIFTIN2; endmodule -module OSERDESE1 (...); +module OSERDESE1(OCBEXTEND, OFB, OQ, SHIFTOUT1, SHIFTOUT2, TFB, TQ, CLK, CLKDIV, CLKPERF, CLKPERFDELAY, D1, D2, D3, D4, D5, D6, OCE, ODV, RST, SHIFTIN1 +, SHIFTIN2, T1, T2, T3, T4, TCE, WC); parameter DATA_RATE_OQ = "DDR"; parameter DATA_RATE_TQ = "DDR"; parameter integer DATA_WIDTH = 4; @@ -6470,7 +6491,7 @@ module OSERDESE1 (...); input WC; endmodule -module IDELAYE2 (...); +module IDELAYE2(CNTVALUEOUT, DATAOUT, C, CE, CINVCTRL, CNTVALUEIN, DATAIN, IDATAIN, INC, LD, LDPIPEEN, REGRST); parameter CINVCTRL_SEL = "FALSE"; parameter DELAY_SRC = "IDATAIN"; parameter HIGH_PERFORMANCE_MODE = "FALSE"; @@ -6501,7 +6522,7 @@ module IDELAYE2 (...); input REGRST; endmodule -module ODELAYE2 (...); +module ODELAYE2(CNTVALUEOUT, DATAOUT, C, CE, CINVCTRL, CLKIN, CNTVALUEIN, INC, LD, LDPIPEEN, ODATAIN, REGRST); parameter CINVCTRL_SEL = "FALSE"; parameter DELAY_SRC = "ODATAIN"; parameter HIGH_PERFORMANCE_MODE = "FALSE"; @@ -6530,7 +6551,8 @@ module ODELAYE2 (...); input REGRST; endmodule -module ISERDESE2 (...); +module ISERDESE2(O, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, SHIFTOUT1, SHIFTOUT2, BITSLIP, CE1, CE2, CLK, CLKB, CLKDIV, CLKDIVP, D, DDLY, DYNCLKDIVSEL +, DYNCLKSEL, OCLK, OCLKB, OFB, RST, SHIFTIN1, SHIFTIN2); parameter DATA_RATE = "DDR"; parameter integer DATA_WIDTH = 4; parameter DYN_CLKDIV_INV_EN = "FALSE"; @@ -6598,7 +6620,8 @@ module ISERDESE2 (...); input SHIFTIN2; endmodule -module OSERDESE2 (...); +module OSERDESE2(OFB, OQ, SHIFTOUT1, SHIFTOUT2, TBYTEOUT, TFB, TQ, CLK, CLKDIV, D1, D2, D3, D4, D5, D6, D7, D8, OCE, RST, SHIFTIN1, SHIFTIN2 +, T1, T2, T3, T4, TBYTEIN, TCE); parameter DATA_RATE_OQ = "DDR"; parameter DATA_RATE_TQ = "DDR"; parameter integer DATA_WIDTH = 4; @@ -6670,7 +6693,7 @@ module OSERDESE2 (...); endmodule (* keep *) -module PHASER_IN (...); +module PHASER_IN(FINEOVERFLOW, ICLK, ICLKDIV, ISERDESRST, RCLK, COUNTERREADVAL, COUNTERLOADEN, COUNTERREADEN, DIVIDERST, EDGEADV, FINEENABLE, FINEINC, FREQREFCLK, MEMREFCLK, PHASEREFCLK, RST, SYNCIN, SYSCLK, RANKSEL, COUNTERLOADVAL); parameter integer CLKOUT_DIV = 4; parameter DQS_BIAS_MODE = "FALSE"; parameter EN_ISERDES_RST = "FALSE"; @@ -6707,7 +6730,8 @@ module PHASER_IN (...); endmodule (* keep *) -module PHASER_IN_PHY (...); +module PHASER_IN_PHY(DQSFOUND, DQSOUTOFRANGE, FINEOVERFLOW, ICLK, ICLKDIV, ISERDESRST, PHASELOCKED, RCLK, WRENABLE, COUNTERREADVAL, BURSTPENDINGPHY, COUNTERLOADEN, COUNTERREADEN, FINEENABLE, FINEINC, FREQREFCLK, MEMREFCLK, PHASEREFCLK, RST, RSTDQSFIND, SYNCIN +, SYSCLK, ENCALIBPHY, RANKSELPHY, COUNTERLOADVAL); parameter BURST_MODE = "FALSE"; parameter integer CLKOUT_DIV = 4; parameter [0:0] DQS_AUTO_RECAL = 1'b1; @@ -6752,7 +6776,8 @@ module PHASER_IN_PHY (...); endmodule (* keep *) -module PHASER_OUT (...); +module PHASER_OUT(COARSEOVERFLOW, FINEOVERFLOW, OCLK, OCLKDELAYED, OCLKDIV, OSERDESRST, COUNTERREADVAL, COARSEENABLE, COARSEINC, COUNTERLOADEN, COUNTERREADEN, DIVIDERST, EDGEADV, FINEENABLE, FINEINC, FREQREFCLK, MEMREFCLK, PHASEREFCLK, RST, SELFINEOCLKDELAY, SYNCIN +, SYSCLK, COUNTERLOADVAL); parameter integer CLKOUT_DIV = 4; parameter COARSE_BYPASS = "FALSE"; parameter integer COARSE_DELAY = 0; @@ -6794,7 +6819,8 @@ module PHASER_OUT (...); endmodule (* keep *) -module PHASER_OUT_PHY (...); +module PHASER_OUT_PHY(COARSEOVERFLOW, FINEOVERFLOW, OCLK, OCLKDELAYED, OCLKDIV, OSERDESRST, RDENABLE, CTSBUS, DQSBUS, DTSBUS, COUNTERREADVAL, BURSTPENDINGPHY, COARSEENABLE, COARSEINC, COUNTERLOADEN, COUNTERREADEN, FINEENABLE, FINEINC, FREQREFCLK, MEMREFCLK, PHASEREFCLK +, RST, SELFINEOCLKDELAY, SYNCIN, SYSCLK, ENCALIBPHY, COUNTERLOADVAL); parameter integer CLKOUT_DIV = 4; parameter COARSE_BYPASS = "FALSE"; parameter integer COARSE_DELAY = 0; @@ -6841,7 +6867,7 @@ module PHASER_OUT_PHY (...); endmodule (* keep *) -module PHASER_REF (...); +module PHASER_REF(LOCKED, CLKIN, PWRDWN, RST); parameter [0:0] IS_RST_INVERTED = 1'b0; parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; output LOCKED; @@ -6853,7 +6879,8 @@ module PHASER_REF (...); endmodule (* keep *) -module PHY_CONTROL (...); +module PHY_CONTROL(PHYCTLALMOSTFULL, PHYCTLEMPTY, PHYCTLFULL, PHYCTLREADY, INRANKA, INRANKB, INRANKC, INRANKD, PCENABLECALIB, AUXOUTPUT, INBURSTPENDING, OUTBURSTPENDING, MEMREFCLK, PHYCLK, PHYCTLMSTREMPTY, PHYCTLWRENABLE, PLLLOCK, READCALIBENABLE, REFDLLLOCK, RESET, SYNCIN +, WRITECALIBENABLE, PHYCTLWD); parameter integer AO_TOGGLE = 0; parameter [3:0] AO_WRLVL_EN = 4'b0000; parameter BURST_MODE = "FALSE"; @@ -6913,7 +6940,7 @@ module PHY_CONTROL (...); input [31:0] PHYCTLWD; endmodule -module IDDRE1 (...); +module IDDRE1(Q1, Q2, C, CB, D, R); parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; parameter [0:0] IS_CB_INVERTED = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; @@ -6929,7 +6956,7 @@ module IDDRE1 (...); input R; endmodule -module ODDRE1 (...); +module ODDRE1(Q, C, D1, D2, SR); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D1_INVERTED = 1'b0; parameter [0:0] IS_D2_INVERTED = 1'b0; @@ -6946,7 +6973,7 @@ module ODDRE1 (...); input SR; endmodule -module IDELAYE3 (...); +module IDELAYE3(CASC_OUT, CNTVALUEOUT, DATAOUT, CASC_IN, CASC_RETURN, CE, CLK, CNTVALUEIN, DATAIN, EN_VTC, IDATAIN, INC, LOAD, RST); parameter CASCADE = "NONE"; parameter DELAY_FORMAT = "TIME"; parameter DELAY_SRC = "IDATAIN"; @@ -6978,7 +7005,7 @@ module IDELAYE3 (...); input RST; endmodule -module ODELAYE3 (...); +module ODELAYE3(CASC_OUT, CNTVALUEOUT, DATAOUT, CASC_IN, CASC_RETURN, CE, CLK, CNTVALUEIN, EN_VTC, INC, LOAD, ODATAIN, RST); parameter CASCADE = "NONE"; parameter DELAY_FORMAT = "TIME"; parameter DELAY_TYPE = "FIXED"; @@ -7007,7 +7034,7 @@ module ODELAYE3 (...); input RST; endmodule -module ISERDESE3 (...); +module ISERDESE3(FIFO_EMPTY, INTERNAL_DIVCLK, Q, CLK, CLKDIV, CLK_B, D, FIFO_RD_CLK, FIFO_RD_EN, RST); parameter integer DATA_WIDTH = 8; parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; parameter FIFO_ENABLE = "FALSE"; @@ -7037,7 +7064,7 @@ module ISERDESE3 (...); input RST; endmodule -module OSERDESE3 (...); +module OSERDESE3(OQ, T_OUT, CLK, CLKDIV, D, RST, T); parameter integer DATA_WIDTH = 8; parameter [0:0] INIT = 1'b0; parameter [0:0] IS_CLKDIV_INVERTED = 1'b0; @@ -7063,7 +7090,9 @@ module OSERDESE3 (...); endmodule (* keep *) -module BITSLICE_CONTROL (...); +module BITSLICE_CONTROL(CLK_TO_EXT_NORTH, CLK_TO_EXT_SOUTH, DLY_RDY, DYN_DCI, NCLK_NIBBLE_OUT, PCLK_NIBBLE_OUT, RIU_RD_DATA, RIU_VALID, RX_BIT_CTRL_OUT0, RX_BIT_CTRL_OUT1, RX_BIT_CTRL_OUT2, RX_BIT_CTRL_OUT3, RX_BIT_CTRL_OUT4, RX_BIT_CTRL_OUT5, RX_BIT_CTRL_OUT6, TX_BIT_CTRL_OUT0, TX_BIT_CTRL_OUT1, TX_BIT_CTRL_OUT2, TX_BIT_CTRL_OUT3, TX_BIT_CTRL_OUT4, TX_BIT_CTRL_OUT5 +, TX_BIT_CTRL_OUT6, TX_BIT_CTRL_OUT_TRI, VTC_RDY, CLK_FROM_EXT, EN_VTC, NCLK_NIBBLE_IN, PCLK_NIBBLE_IN, PHY_RDCS0, PHY_RDCS1, PHY_RDEN, PHY_WRCS0, PHY_WRCS1, PLL_CLK, REFCLK, RIU_ADDR, RIU_CLK, RIU_NIBBLE_SEL, RIU_WR_DATA, RIU_WR_EN, RST, RX_BIT_CTRL_IN0 +, RX_BIT_CTRL_IN1, RX_BIT_CTRL_IN2, RX_BIT_CTRL_IN3, RX_BIT_CTRL_IN4, RX_BIT_CTRL_IN5, RX_BIT_CTRL_IN6, TBYTE_IN, TX_BIT_CTRL_IN0, TX_BIT_CTRL_IN1, TX_BIT_CTRL_IN2, TX_BIT_CTRL_IN3, TX_BIT_CTRL_IN4, TX_BIT_CTRL_IN5, TX_BIT_CTRL_IN6, TX_BIT_CTRL_IN_TRI); parameter CTRL_CLK = "EXTERNAL"; parameter DIV_MODE = "DIV2"; parameter EN_CLK_TO_EXT_NORTH = "DISABLE"; @@ -7148,7 +7177,7 @@ module BITSLICE_CONTROL (...); endmodule (* keep *) -module RIU_OR (...); +module RIU_OR(RIU_RD_DATA, RIU_RD_VALID, RIU_RD_DATA_LOW, RIU_RD_DATA_UPP, RIU_RD_VALID_LOW, RIU_RD_VALID_UPP); parameter SIM_DEVICE = "ULTRASCALE"; parameter real SIM_VERSION = 2.0; output [15:0] RIU_RD_DATA; @@ -7159,7 +7188,8 @@ module RIU_OR (...); input RIU_RD_VALID_UPP; endmodule -module RX_BITSLICE (...); +module RX_BITSLICE(CNTVALUEOUT, CNTVALUEOUT_EXT, FIFO_EMPTY, FIFO_WRCLK_OUT, Q, RX_BIT_CTRL_OUT, TX_BIT_CTRL_OUT, CE, CE_EXT, CLK, CLK_EXT, CNTVALUEIN, CNTVALUEIN_EXT, DATAIN, EN_VTC, EN_VTC_EXT, FIFO_RD_CLK, FIFO_RD_EN, INC, INC_EXT, LOAD +, LOAD_EXT, RST, RST_DLY, RST_DLY_EXT, RX_BIT_CTRL_IN, TX_BIT_CTRL_IN); parameter CASCADE = "TRUE"; parameter DATA_TYPE = "NONE"; parameter integer DATA_WIDTH = 8; @@ -7212,7 +7242,8 @@ module RX_BITSLICE (...); input [39:0] TX_BIT_CTRL_IN; endmodule -module RXTX_BITSLICE (...); +module RXTX_BITSLICE(FIFO_EMPTY, FIFO_WRCLK_OUT, O, Q, RX_BIT_CTRL_OUT, RX_CNTVALUEOUT, TX_BIT_CTRL_OUT, TX_CNTVALUEOUT, T_OUT, D, DATAIN, FIFO_RD_CLK, FIFO_RD_EN, RX_BIT_CTRL_IN, RX_CE, RX_CLK, RX_CNTVALUEIN, RX_EN_VTC, RX_INC, RX_LOAD, RX_RST +, RX_RST_DLY, T, TBYTE_IN, TX_BIT_CTRL_IN, TX_CE, TX_CLK, TX_CNTVALUEIN, TX_EN_VTC, TX_INC, TX_LOAD, TX_RST, TX_RST_DLY); parameter FIFO_SYNC_MODE = "FALSE"; parameter [0:0] INIT = 1'b1; parameter [0:0] IS_RX_CLK_INVERTED = 1'b0; @@ -7282,7 +7313,7 @@ module RXTX_BITSLICE (...); input TX_RST_DLY; endmodule -module TX_BITSLICE (...); +module TX_BITSLICE(CNTVALUEOUT, O, RX_BIT_CTRL_OUT, TX_BIT_CTRL_OUT, T_OUT, CE, CLK, CNTVALUEIN, D, EN_VTC, INC, LOAD, RST, RST_DLY, RX_BIT_CTRL_IN, T, TBYTE_IN, TX_BIT_CTRL_IN); parameter integer DATA_WIDTH = 8; parameter DELAY_FORMAT = "TIME"; parameter DELAY_TYPE = "FIXED"; @@ -7322,7 +7353,7 @@ module TX_BITSLICE (...); input [39:0] TX_BIT_CTRL_IN; endmodule -module TX_BITSLICE_TRI (...); +module TX_BITSLICE_TRI(BIT_CTRL_OUT, CNTVALUEOUT, TRI_OUT, BIT_CTRL_IN, CE, CLK, CNTVALUEIN, EN_VTC, INC, LOAD, RST, RST_DLY); parameter integer DATA_WIDTH = 8; parameter DELAY_FORMAT = "TIME"; parameter DELAY_TYPE = "FIXED"; @@ -7354,7 +7385,7 @@ module TX_BITSLICE_TRI (...); input RST_DLY; endmodule -module IODELAY2 (...); +module IODELAY2(BUSY, DATAOUT2, DATAOUT, DOUT, TOUT, CAL, CE, CLK, IDATAIN, INC, IOCLK0, IOCLK1, ODATAIN, RST, T); parameter COUNTER_WRAPAROUND = "WRAPAROUND"; parameter DATA_RATE = "SDR"; parameter DELAY_SRC = "IO"; @@ -7385,7 +7416,7 @@ module IODELAY2 (...); input T; endmodule -module IODRP2 (...); +module IODRP2(DATAOUT2, DATAOUT, DOUT, SDO, TOUT, ADD, BKST, CLK, CS, IDATAIN, IOCLK0, IOCLK1, ODATAIN, SDI, T); parameter DATA_RATE = "SDR"; parameter integer SIM_TAPDELAY_VALUE = 75; output DATAOUT2; @@ -7408,7 +7439,8 @@ module IODRP2 (...); input T; endmodule -module IODRP2_MCB (...); +module IODRP2_MCB(AUXSDO, DATAOUT2, DATAOUT, DOUT, DQSOUTN, DQSOUTP, SDO, TOUT, ADD, AUXSDOIN, BKST, CLK, CS, IDATAIN, IOCLK0, IOCLK1, MEMUPDATE, ODATAIN, SDI, T, AUXADDR +); parameter DATA_RATE = "SDR"; parameter integer IDELAY_VALUE = 0; parameter integer MCB_ADDRESS = 0; @@ -7441,7 +7473,7 @@ module IODRP2_MCB (...); input [4:0] AUXADDR; endmodule -module ISERDES2 (...); +module ISERDES2(CFB0, CFB1, DFB, FABRICOUT, INCDEC, Q1, Q2, Q3, Q4, SHIFTOUT, VALID, BITSLIP, CE0, CLK0, CLK1, CLKDIV, D, IOCE, RST, SHIFTIN); parameter BITSLIP_ENABLE = "FALSE"; parameter DATA_RATE = "SDR"; parameter integer DATA_WIDTH = 1; @@ -7472,7 +7504,8 @@ module ISERDES2 (...); input SHIFTIN; endmodule -module OSERDES2 (...); +module OSERDES2(OQ, SHIFTOUT1, SHIFTOUT2, SHIFTOUT3, SHIFTOUT4, TQ, CLK0, CLK1, CLKDIV, D1, D2, D3, D4, IOCE, OCE, RST, SHIFTIN1, SHIFTIN2, SHIFTIN3, SHIFTIN4, T1 +, T2, T3, T4, TCE, TRAIN); parameter BYPASS_GCLK_FF = "FALSE"; parameter DATA_RATE_OQ = "DDR"; parameter DATA_RATE_OT = "DDR"; @@ -7511,7 +7544,7 @@ module OSERDES2 (...); input TRAIN; endmodule -module IBUF_DLY_ADJ (...); +module IBUF_DLY_ADJ(O, I, S); parameter DELAY_OFFSET = "OFF"; parameter IOSTANDARD = "DEFAULT"; output O; @@ -7520,7 +7553,7 @@ module IBUF_DLY_ADJ (...); input [2:0] S; endmodule -module IBUF_IBUFDISABLE (...); +module IBUF_IBUFDISABLE(O, I, IBUFDISABLE); parameter IBUF_LOW_PWR = "TRUE"; parameter IOSTANDARD = "DEFAULT"; parameter SIM_DEVICE = "7SERIES"; @@ -7531,7 +7564,7 @@ module IBUF_IBUFDISABLE (...); input IBUFDISABLE; endmodule -module IBUF_INTERMDISABLE (...); +module IBUF_INTERMDISABLE(O, I, IBUFDISABLE, INTERMDISABLE); parameter IBUF_LOW_PWR = "TRUE"; parameter IOSTANDARD = "DEFAULT"; parameter SIM_DEVICE = "7SERIES"; @@ -7543,13 +7576,13 @@ module IBUF_INTERMDISABLE (...); input INTERMDISABLE; endmodule -module IBUF_ANALOG (...); +module IBUF_ANALOG(O, I); output O; (* iopad_external_pin *) input I; endmodule -module IBUFE3 (...); +module IBUFE3(O, I, IBUFDISABLE, OSC, OSC_EN, VREF); parameter CCIO_EN = "TRUE"; parameter IBUF_LOW_PWR = "TRUE"; parameter IOSTANDARD = "DEFAULT"; @@ -7565,7 +7598,7 @@ module IBUFE3 (...); input VREF; endmodule -module IBUFDS (...); +module IBUFDS(O, I, IB); parameter CAPACITANCE = "DONT_CARE"; parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; @@ -7580,7 +7613,7 @@ module IBUFDS (...); input IB; endmodule -module IBUFDS_DLY_ADJ (...); +module IBUFDS_DLY_ADJ(O, I, IB, S); parameter DELAY_OFFSET = "OFF"; parameter DIFF_TERM = "FALSE"; parameter IOSTANDARD = "DEFAULT"; @@ -7592,7 +7625,7 @@ module IBUFDS_DLY_ADJ (...); input [2:0] S; endmodule -module IBUFDS_IBUFDISABLE (...); +module IBUFDS_IBUFDISABLE(O, I, IB, IBUFDISABLE); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7607,7 +7640,7 @@ module IBUFDS_IBUFDISABLE (...); input IBUFDISABLE; endmodule -module IBUFDS_INTERMDISABLE (...); +module IBUFDS_INTERMDISABLE(O, I, IB, IBUFDISABLE, INTERMDISABLE); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7623,7 +7656,7 @@ module IBUFDS_INTERMDISABLE (...); input INTERMDISABLE; endmodule -module IBUFDS_DIFF_OUT (...); +module IBUFDS_DIFF_OUT(O, OB, I, IB); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7636,7 +7669,7 @@ module IBUFDS_DIFF_OUT (...); input IB; endmodule -module IBUFDS_DIFF_OUT_IBUFDISABLE (...); +module IBUFDS_DIFF_OUT_IBUFDISABLE(O, OB, I, IB, IBUFDISABLE); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7652,7 +7685,7 @@ module IBUFDS_DIFF_OUT_IBUFDISABLE (...); input IBUFDISABLE; endmodule -module IBUFDS_DIFF_OUT_INTERMDISABLE (...); +module IBUFDS_DIFF_OUT_INTERMDISABLE(O, OB, I, IB, IBUFDISABLE, INTERMDISABLE); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7669,7 +7702,7 @@ module IBUFDS_DIFF_OUT_INTERMDISABLE (...); input INTERMDISABLE; endmodule -module IBUFDSE3 (...); +module IBUFDSE3(O, I, IB, IBUFDISABLE, OSC, OSC_EN); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7686,7 +7719,7 @@ module IBUFDSE3 (...); input [1:0] OSC_EN; endmodule -module IBUFDS_DPHY (...); +module IBUFDS_DPHY(HSRX_O, LPRX_O_N, LPRX_O_P, HSRX_DISABLE, I, IB, LPRX_DISABLE); parameter DIFF_TERM = "TRUE"; parameter IOSTANDARD = "DEFAULT"; output HSRX_O; @@ -7700,7 +7733,7 @@ module IBUFDS_DPHY (...); input LPRX_DISABLE; endmodule -module IBUFGDS (...); +module IBUFGDS(O, I, IB); parameter CAPACITANCE = "DONT_CARE"; parameter DIFF_TERM = "FALSE"; parameter IBUF_DELAY_VALUE = "0"; @@ -7713,7 +7746,7 @@ module IBUFGDS (...); input IB; endmodule -module IBUFGDS_DIFF_OUT (...); +module IBUFGDS_DIFF_OUT(O, OB, I, IB); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7726,7 +7759,7 @@ module IBUFGDS_DIFF_OUT (...); input IB; endmodule -module IOBUF_DCIEN (...); +module IOBUF_DCIEN(O, IO, DCITERMDISABLE, I, IBUFDISABLE, T); parameter integer DRIVE = 12; parameter IBUF_LOW_PWR = "TRUE"; parameter IOSTANDARD = "DEFAULT"; @@ -7742,7 +7775,7 @@ module IOBUF_DCIEN (...); input T; endmodule -module IOBUF_INTERMDISABLE (...); +module IOBUF_INTERMDISABLE(O, IO, I, IBUFDISABLE, INTERMDISABLE, T); parameter integer DRIVE = 12; parameter IBUF_LOW_PWR = "TRUE"; parameter IOSTANDARD = "DEFAULT"; @@ -7758,7 +7791,7 @@ module IOBUF_INTERMDISABLE (...); input T; endmodule -module IOBUFE3 (...); +module IOBUFE3(O, IO, DCITERMDISABLE, I, IBUFDISABLE, OSC, OSC_EN, T, VREF); parameter integer DRIVE = 12; parameter IBUF_LOW_PWR = "TRUE"; parameter IOSTANDARD = "DEFAULT"; @@ -7777,7 +7810,7 @@ module IOBUFE3 (...); input VREF; endmodule -module IOBUFDS (...); +module IOBUFDS(O, IO, IOB, I, T); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7792,7 +7825,7 @@ module IOBUFDS (...); input T; endmodule -module IOBUFDS_DCIEN (...); +module IOBUFDS_DCIEN(O, IO, IOB, DCITERMDISABLE, I, IBUFDISABLE, T); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7811,7 +7844,7 @@ module IOBUFDS_DCIEN (...); input T; endmodule -module IOBUFDS_INTERMDISABLE (...); +module IOBUFDS_INTERMDISABLE(O, IO, IOB, I, IBUFDISABLE, INTERMDISABLE, T); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7830,7 +7863,7 @@ module IOBUFDS_INTERMDISABLE (...); input T; endmodule -module IOBUFDS_DIFF_OUT (...); +module IOBUFDS_DIFF_OUT(O, OB, IO, IOB, I, TM, TS); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7846,7 +7879,7 @@ module IOBUFDS_DIFF_OUT (...); input TS; endmodule -module IOBUFDS_DIFF_OUT_DCIEN (...); +module IOBUFDS_DIFF_OUT_DCIEN(O, OB, IO, IOB, DCITERMDISABLE, I, IBUFDISABLE, TM, TS); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7866,7 +7899,7 @@ module IOBUFDS_DIFF_OUT_DCIEN (...); input TS; endmodule -module IOBUFDS_DIFF_OUT_INTERMDISABLE (...); +module IOBUFDS_DIFF_OUT_INTERMDISABLE(O, OB, IO, IOB, I, IBUFDISABLE, INTERMDISABLE, TM, TS); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7886,7 +7919,7 @@ module IOBUFDS_DIFF_OUT_INTERMDISABLE (...); input TS; endmodule -module IOBUFDSE3 (...); +module IOBUFDSE3(O, IO, IOB, DCITERMDISABLE, I, IBUFDISABLE, OSC, OSC_EN, T); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7906,7 +7939,7 @@ module IOBUFDSE3 (...); input T; endmodule -module OBUFDS (...); +module OBUFDS(O, OB, I); parameter CAPACITANCE = "DONT_CARE"; parameter IOSTANDARD = "DEFAULT"; parameter SLEW = "SLOW"; @@ -7917,7 +7950,7 @@ module OBUFDS (...); input I; endmodule -module OBUFDS_DPHY (...); +module OBUFDS_DPHY(O, OB, HSTX_I, HSTX_T, LPTX_I_N, LPTX_I_P, LPTX_T); parameter IOSTANDARD = "DEFAULT"; (* iopad_external_pin *) output O; @@ -7930,7 +7963,7 @@ module OBUFDS_DPHY (...); input LPTX_T; endmodule -module OBUFTDS (...); +module OBUFTDS(O, OB, I, T); parameter CAPACITANCE = "DONT_CARE"; parameter IOSTANDARD = "DEFAULT"; parameter SLEW = "SLOW"; @@ -7942,32 +7975,32 @@ module OBUFTDS (...); input T; endmodule -module KEEPER (...); +module KEEPER(O); inout O; endmodule -module PULLDOWN (...); +module PULLDOWN(O); output O; endmodule -module PULLUP (...); +module PULLUP(O); output O; endmodule (* keep *) -module DCIRESET (...); +module DCIRESET(LOCKED, RST); output LOCKED; input RST; endmodule (* keep *) -module HPIO_VREF (...); +module HPIO_VREF(VREF, FABRIC_VREF_TUNE); parameter VREF_CNTR = "OFF"; output VREF; input [6:0] FABRIC_VREF_TUNE; endmodule -module BUFGCE (...); +module BUFGCE(O, CE, I); parameter CE_TYPE = "SYNC"; parameter [0:0] IS_CE_INVERTED = 1'b0; parameter [0:0] IS_I_INVERTED = 1'b0; @@ -7981,14 +8014,14 @@ module BUFGCE (...); input I; endmodule -module BUFGCE_1 (...); +module BUFGCE_1(O, CE, I); (* clkbuf_driver *) output O; input CE; input I; endmodule -module BUFGMUX (...); +module BUFGMUX(O, I0, I1, S); parameter CLK_SEL_TYPE = "SYNC"; (* clkbuf_driver *) output O; @@ -7997,7 +8030,7 @@ module BUFGMUX (...); input S; endmodule -module BUFGMUX_1 (...); +module BUFGMUX_1(O, I0, I1, S); parameter CLK_SEL_TYPE = "SYNC"; (* clkbuf_driver *) output O; @@ -8006,7 +8039,7 @@ module BUFGMUX_1 (...); input S; endmodule -module BUFGMUX_CTRL (...); +module BUFGMUX_CTRL(O, I0, I1, S); (* clkbuf_driver *) output O; input I0; @@ -8014,7 +8047,7 @@ module BUFGMUX_CTRL (...); input S; endmodule -module BUFGMUX_VIRTEX4 (...); +module BUFGMUX_VIRTEX4(O, I0, I1, S); (* clkbuf_driver *) output O; input I0; @@ -8022,7 +8055,7 @@ module BUFGMUX_VIRTEX4 (...); input S; endmodule -module BUFG_GT (...); +module BUFG_GT(O, CE, CEMASK, CLR, CLRMASK, DIV, I); parameter SIM_DEVICE = "ULTRASCALE"; parameter STARTUP_SYNC = "FALSE"; (* clkbuf_driver *) @@ -8035,7 +8068,7 @@ module BUFG_GT (...); input I; endmodule -module BUFG_GT_SYNC (...); +module BUFG_GT_SYNC(CESYNC, CLRSYNC, CE, CLK, CLR); output CESYNC; output CLRSYNC; input CE; @@ -8043,7 +8076,7 @@ module BUFG_GT_SYNC (...); input CLR; endmodule -module BUFG_PS (...); +module BUFG_PS(O, I); parameter SIM_DEVICE = "ULTRASCALE_PLUS"; parameter STARTUP_SYNC = "FALSE"; (* clkbuf_driver *) @@ -8051,7 +8084,7 @@ module BUFG_PS (...); input I; endmodule -module BUFGCE_DIV (...); +module BUFGCE_DIV(O, CE, CLR, I); parameter integer BUFGCE_DIVIDE = 1; parameter CE_TYPE = "SYNC"; parameter HARDSYNC_CLR = "FALSE"; @@ -8070,13 +8103,13 @@ module BUFGCE_DIV (...); input I; endmodule -module BUFH (...); +module BUFH(O, I); (* clkbuf_driver *) output O; input I; endmodule -module BUFIO2 (...); +module BUFIO2(DIVCLK, IOCLK, SERDESSTROBE, I); parameter DIVIDE_BYPASS = "TRUE"; parameter integer DIVIDE = 1; parameter I_INVERT = "FALSE"; @@ -8089,7 +8122,7 @@ module BUFIO2 (...); input I; endmodule -module BUFIO2_2CLK (...); +module BUFIO2_2CLK(DIVCLK, IOCLK, SERDESSTROBE, I, IB); parameter integer DIVIDE = 2; (* clkbuf_driver *) output DIVCLK; @@ -8100,14 +8133,14 @@ module BUFIO2_2CLK (...); input IB; endmodule -module BUFIO2FB (...); +module BUFIO2FB(O, I); parameter DIVIDE_BYPASS = "TRUE"; (* clkbuf_driver *) output O; input I; endmodule -module BUFPLL (...); +module BUFPLL(IOCLK, LOCK, SERDESSTROBE, GCLK, LOCKED, PLLIN); parameter integer DIVIDE = 1; parameter ENABLE_SYNC = "TRUE"; (* clkbuf_driver *) @@ -8119,7 +8152,7 @@ module BUFPLL (...); input PLLIN; endmodule -module BUFPLL_MCB (...); +module BUFPLL_MCB(IOCLK0, IOCLK1, LOCK, SERDESSTROBE0, SERDESSTROBE1, GCLK, LOCKED, PLLIN0, PLLIN1); parameter integer DIVIDE = 2; parameter LOCK_SRC = "LOCK_TO_0"; (* clkbuf_driver *) @@ -8135,13 +8168,13 @@ module BUFPLL_MCB (...); input PLLIN1; endmodule -module BUFIO (...); +module BUFIO(O, I); (* clkbuf_driver *) output O; input I; endmodule -module BUFIODQS (...); +module BUFIODQS(O, DQSMASK, I); parameter DQSMASK_ENABLE = "FALSE"; (* clkbuf_driver *) output O; @@ -8149,7 +8182,7 @@ module BUFIODQS (...); input I; endmodule -module BUFR (...); +module BUFR(O, CE, CLR, I); parameter BUFR_DIVIDE = "BYPASS"; parameter SIM_DEVICE = "7SERIES"; (* clkbuf_driver *) @@ -8159,13 +8192,13 @@ module BUFR (...); input I; endmodule -module BUFMR (...); +module BUFMR(O, I); (* clkbuf_driver *) output O; input I; endmodule -module BUFMRCE (...); +module BUFMRCE(O, CE, I); parameter CE_TYPE = "SYNC"; parameter integer INIT_OUT = 0; parameter [0:0] IS_CE_INVERTED = 1'b0; @@ -8176,7 +8209,7 @@ module BUFMRCE (...); input I; endmodule -module DCM (...); +module DCM(CLKFB, CLKIN, DSSEN, PSCLK, PSEN, PSINCDEC, RST, CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE, STATUS); parameter real CLKDV_DIVIDE = 2.0; parameter integer CLKFX_DIVIDE = 1; parameter integer CLKFX_MULTIPLY = 4; @@ -8214,7 +8247,7 @@ module DCM (...); output [7:0] STATUS; endmodule -module DCM_SP (...); +module DCM_SP(CLKFB, CLKIN, DSSEN, PSCLK, PSEN, PSINCDEC, RST, CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE, STATUS); parameter real CLKDV_DIVIDE = 2.0; parameter integer CLKFX_DIVIDE = 1; parameter integer CLKFX_MULTIPLY = 4; @@ -8251,7 +8284,7 @@ module DCM_SP (...); output [7:0] STATUS; endmodule -module DCM_CLKGEN (...); +module DCM_CLKGEN(CLKFX180, CLKFX, CLKFXDV, LOCKED, PROGDONE, STATUS, CLKIN, FREEZEDCM, PROGCLK, PROGDATA, PROGEN, RST); parameter SPREAD_SPECTRUM = "NONE"; parameter STARTUP_WAIT = "FALSE"; parameter integer CLKFXDV_DIVIDE = 2; @@ -8273,7 +8306,8 @@ module DCM_CLKGEN (...); input RST; endmodule -module DCM_ADV (...); +module DCM_ADV(CLK0, CLK180, CLK270, CLK2X180, CLK2X, CLK90, CLKDV, CLKFX180, CLKFX, DRDY, LOCKED, PSDONE, DO, CLKFB, CLKIN, DCLK, DEN, DWE, PSCLK, PSEN, PSINCDEC +, RST, DI, DADDR); parameter real CLKDV_DIVIDE = 2.0; parameter integer CLKFX_DIVIDE = 1; parameter integer CLKFX_MULTIPLY = 4; @@ -8317,7 +8351,7 @@ module DCM_ADV (...); input [6:0] DADDR; endmodule -module DCM_BASE (...); +module DCM_BASE(CLK0, CLK180, CLK270, CLK2X180, CLK2X, CLK90, CLKDV, CLKFX180, CLKFX, LOCKED, CLKFB, CLKIN, RST); parameter real CLKDV_DIVIDE = 2.0; parameter integer CLKFX_DIVIDE = 1; parameter integer CLKFX_MULTIPLY = 4; @@ -8349,7 +8383,7 @@ module DCM_BASE (...); input RST; endmodule -module DCM_PS (...); +module DCM_PS(CLK0, CLK180, CLK270, CLK2X180, CLK2X, CLK90, CLKDV, CLKFX180, CLKFX, LOCKED, PSDONE, DO, CLKFB, CLKIN, PSCLK, PSEN, PSINCDEC, RST); parameter real CLKDV_DIVIDE = 2.0; parameter integer CLKFX_DIVIDE = 1; parameter integer CLKFX_MULTIPLY = 4; @@ -8386,7 +8420,7 @@ module DCM_PS (...); input RST; endmodule -module PMCD (...); +module PMCD(CLKA1, CLKA1D2, CLKA1D4, CLKA1D8, CLKB1, CLKC1, CLKD1, CLKA, CLKB, CLKC, CLKD, REL, RST); parameter EN_REL = "FALSE"; parameter RST_DEASSERT_CLK = "CLKA"; output CLKA1; @@ -8404,7 +8438,8 @@ module PMCD (...); input RST; endmodule -module PLL_ADV (...); +module PLL_ADV(CLKFBDCM, CLKFBOUT, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, CLKOUTDCM0, CLKOUTDCM1, CLKOUTDCM2, CLKOUTDCM3, CLKOUTDCM4, CLKOUTDCM5, DRDY, LOCKED, DO, CLKFBIN, CLKIN1, CLKIN2, CLKINSEL +, DCLK, DEN, DWE, REL, RST, DI, DADDR); parameter BANDWIDTH = "OPTIMIZED"; parameter CLK_FEEDBACK = "CLKFBOUT"; parameter CLKFBOUT_DESKEW_ADJUST = "NONE"; @@ -8480,7 +8515,7 @@ module PLL_ADV (...); input [4:0] DADDR; endmodule -module PLL_BASE (...); +module PLL_BASE(CLKFBOUT, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, LOCKED, CLKFBIN, CLKIN, RST); parameter BANDWIDTH = "OPTIMIZED"; parameter integer CLKFBOUT_MULT = 1; parameter real CLKFBOUT_PHASE = 0.0; @@ -8521,7 +8556,8 @@ module PLL_BASE (...); input RST; endmodule -module MMCM_ADV (...); +module MMCM_ADV(CLKFBOUT, CLKFBOUTB, CLKFBSTOPPED, CLKINSTOPPED, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUT2, CLKOUT2B, CLKOUT3, CLKOUT3B, CLKOUT4, CLKOUT5, CLKOUT6, DRDY, LOCKED, PSDONE, DO, CLKFBIN, CLKIN1 +, CLKIN2, CLKINSEL, DCLK, DEN, DWE, PSCLK, PSEN, PSINCDEC, PWRDWN, RST, DI, DADDR); parameter BANDWIDTH = "OPTIMIZED"; parameter CLKFBOUT_USE_FINE_PS = "FALSE"; parameter CLKOUT0_USE_FINE_PS = "FALSE"; @@ -8604,7 +8640,7 @@ module MMCM_ADV (...); input [6:0] DADDR; endmodule -module MMCM_BASE (...); +module MMCM_BASE(CLKFBOUT, CLKFBOUTB, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUT2, CLKOUT2B, CLKOUT3, CLKOUT3B, CLKOUT4, CLKOUT5, CLKOUT6, LOCKED, CLKFBIN, CLKIN1, PWRDWN, RST); parameter BANDWIDTH = "OPTIMIZED"; parameter real CLKFBOUT_MULT_F = 5.000; parameter real CLKFBOUT_PHASE = 0.000; @@ -8655,7 +8691,8 @@ module MMCM_BASE (...); input RST; endmodule -module MMCME2_ADV (...); +module MMCME2_ADV(CLKFBOUT, CLKFBOUTB, CLKFBSTOPPED, CLKINSTOPPED, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUT2, CLKOUT2B, CLKOUT3, CLKOUT3B, CLKOUT4, CLKOUT5, CLKOUT6, DO, DRDY, LOCKED, PSDONE, CLKFBIN, CLKIN1 +, CLKIN2, CLKINSEL, DADDR, DCLK, DEN, DI, DWE, PSCLK, PSEN, PSINCDEC, PWRDWN, RST); parameter real CLKIN_FREQ_MAX = 1066.000; parameter real CLKIN_FREQ_MIN = 10.000; parameter real CLKPFD_FREQ_MAX = 550.000; @@ -8750,7 +8787,7 @@ module MMCME2_ADV (...); input RST; endmodule -module MMCME2_BASE (...); +module MMCME2_BASE(CLKFBOUT, CLKFBOUTB, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUT2, CLKOUT2B, CLKOUT3, CLKOUT3B, CLKOUT4, CLKOUT5, CLKOUT6, LOCKED, CLKFBIN, CLKIN1, PWRDWN, RST); parameter BANDWIDTH = "OPTIMIZED"; parameter real CLKFBOUT_MULT_F = 5.000; parameter real CLKFBOUT_PHASE = 0.000; @@ -8800,7 +8837,8 @@ module MMCME2_BASE (...); input RST; endmodule -module PLLE2_ADV (...); +module PLLE2_ADV(CLKFBOUT, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, DRDY, LOCKED, DO, CLKFBIN, CLKIN1, CLKIN2, CLKINSEL, DCLK, DEN, DWE, PWRDWN, RST, DI, DADDR +); parameter BANDWIDTH = "OPTIMIZED"; parameter COMPENSATION = "ZHOLD"; parameter STARTUP_WAIT = "FALSE"; @@ -8864,7 +8902,7 @@ module PLLE2_ADV (...); input [6:0] DADDR; endmodule -module PLLE2_BASE (...); +module PLLE2_BASE(CLKFBOUT, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, LOCKED, CLKFBIN, CLKIN1, PWRDWN, RST); parameter BANDWIDTH = "OPTIMIZED"; parameter integer CLKFBOUT_MULT = 5; parameter real CLKFBOUT_PHASE = 0.000; @@ -8904,7 +8942,8 @@ module PLLE2_BASE (...); input RST; endmodule -module MMCME3_ADV (...); +module MMCME3_ADV(CDDCDONE, CLKFBOUT, CLKFBOUTB, CLKFBSTOPPED, CLKINSTOPPED, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUT2, CLKOUT2B, CLKOUT3, CLKOUT3B, CLKOUT4, CLKOUT5, CLKOUT6, DO, DRDY, LOCKED, PSDONE, CDDCREQ +, CLKFBIN, CLKIN1, CLKIN2, CLKINSEL, DADDR, DCLK, DEN, DI, DWE, PSCLK, PSEN, PSINCDEC, PWRDWN, RST); parameter real CLKIN_FREQ_MAX = 1066.000; parameter real CLKIN_FREQ_MIN = 10.000; parameter real CLKPFD_FREQ_MAX = 550.000; @@ -9007,7 +9046,7 @@ module MMCME3_ADV (...); input RST; endmodule -module MMCME3_BASE (...); +module MMCME3_BASE(CLKFBOUT, CLKFBOUTB, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUT2, CLKOUT2B, CLKOUT3, CLKOUT3B, CLKOUT4, CLKOUT5, CLKOUT6, LOCKED, CLKFBIN, CLKIN1, PWRDWN, RST); parameter BANDWIDTH = "OPTIMIZED"; parameter real CLKFBOUT_MULT_F = 5.000; parameter real CLKFBOUT_PHASE = 0.000; @@ -9065,7 +9104,7 @@ module MMCME3_BASE (...); input RST; endmodule -module PLLE3_ADV (...); +module PLLE3_ADV(CLKFBOUT, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUTPHY, DO, DRDY, LOCKED, CLKFBIN, CLKIN, CLKOUTPHYEN, DADDR, DCLK, DEN, DI, DWE, PWRDWN, RST); parameter real CLKIN_FREQ_MAX = 1066.000; parameter real CLKIN_FREQ_MIN = 70.000; parameter real CLKPFD_FREQ_MAX = 667.500; @@ -9115,7 +9154,7 @@ module PLLE3_ADV (...); input RST; endmodule -module PLLE3_BASE (...); +module PLLE3_BASE(CLKFBOUT, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUTPHY, LOCKED, CLKFBIN, CLKIN, CLKOUTPHYEN, PWRDWN, RST); parameter integer CLKFBOUT_MULT = 5; parameter real CLKFBOUT_PHASE = 0.000; parameter real CLKIN_PERIOD = 0.000; @@ -9151,7 +9190,8 @@ module PLLE3_BASE (...); input RST; endmodule -module MMCME4_ADV (...); +module MMCME4_ADV(CDDCDONE, CLKFBOUT, CLKFBOUTB, CLKFBSTOPPED, CLKINSTOPPED, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUT2, CLKOUT2B, CLKOUT3, CLKOUT3B, CLKOUT4, CLKOUT5, CLKOUT6, DO, DRDY, LOCKED, PSDONE, CDDCREQ +, CLKFBIN, CLKIN1, CLKIN2, CLKINSEL, DADDR, DCLK, DEN, DI, DWE, PSCLK, PSEN, PSINCDEC, PWRDWN, RST); parameter real CLKIN_FREQ_MAX = 1066.000; parameter real CLKIN_FREQ_MIN = 10.000; parameter real CLKPFD_FREQ_MAX = 550.000; @@ -9254,7 +9294,7 @@ module MMCME4_ADV (...); input RST; endmodule -module MMCME4_BASE (...); +module MMCME4_BASE(CLKFBOUT, CLKFBOUTB, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUT2, CLKOUT2B, CLKOUT3, CLKOUT3B, CLKOUT4, CLKOUT5, CLKOUT6, LOCKED, CLKFBIN, CLKIN1, PWRDWN, RST); parameter BANDWIDTH = "OPTIMIZED"; parameter real CLKFBOUT_MULT_F = 5.000; parameter real CLKFBOUT_PHASE = 0.000; @@ -9312,7 +9352,7 @@ module MMCME4_BASE (...); input RST; endmodule -module PLLE4_ADV (...); +module PLLE4_ADV(CLKFBOUT, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUTPHY, DO, DRDY, LOCKED, CLKFBIN, CLKIN, CLKOUTPHYEN, DADDR, DCLK, DEN, DI, DWE, PWRDWN, RST); parameter real CLKIN_FREQ_MAX = 1066.000; parameter real CLKIN_FREQ_MIN = 70.000; parameter real CLKPFD_FREQ_MAX = 667.500; @@ -9362,7 +9402,7 @@ module PLLE4_ADV (...); input RST; endmodule -module PLLE4_BASE (...); +module PLLE4_BASE(CLKFBOUT, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUTPHY, LOCKED, CLKFBIN, CLKIN, CLKOUTPHYEN, PWRDWN, RST); parameter integer CLKFBOUT_MULT = 5; parameter real CLKFBOUT_PHASE = 0.000; parameter real CLKIN_PERIOD = 0.000; @@ -9398,13 +9438,14 @@ module PLLE4_BASE (...); input RST; endmodule -module BUFT (...); +module BUFT(O, I, T); output O; input I; input T; endmodule -module IN_FIFO (...); +module IN_FIFO(ALMOSTEMPTY, ALMOSTFULL, EMPTY, FULL, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, RDCLK, RDEN, RESET, WRCLK, WREN, D0, D1 +, D2, D3, D4, D7, D8, D9, D5, D6); parameter integer ALMOST_EMPTY_VALUE = 1; parameter integer ALMOST_FULL_VALUE = 1; parameter ARRAY_MODE = "ARRAY_MODE_4_X_8"; @@ -9442,7 +9483,8 @@ module IN_FIFO (...); input [7:0] D6; endmodule -module OUT_FIFO (...); +module OUT_FIFO(ALMOSTEMPTY, ALMOSTFULL, EMPTY, FULL, Q0, Q1, Q2, Q3, Q4, Q7, Q8, Q9, Q5, Q6, RDCLK, RDEN, RESET, WRCLK, WREN, D0, D1 +, D2, D3, D4, D5, D6, D7, D8, D9); parameter integer ALMOST_EMPTY_VALUE = 1; parameter integer ALMOST_FULL_VALUE = 1; parameter ARRAY_MODE = "ARRAY_MODE_8_X_4"; @@ -9481,7 +9523,7 @@ module OUT_FIFO (...); input [7:0] D9; endmodule -module HARD_SYNC (...); +module HARD_SYNC(DOUT, CLK, DIN); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_CLK_INVERTED = 1'b0; parameter integer LATENCY = 2; @@ -9493,14 +9535,14 @@ module HARD_SYNC (...); endmodule (* keep *) -module STARTUP_SPARTAN3 (...); +module STARTUP_SPARTAN3(CLK, GSR, GTS); input CLK; input GSR; input GTS; endmodule (* keep *) -module STARTUP_SPARTAN3E (...); +module STARTUP_SPARTAN3E(CLK, GSR, GTS, MBT); input CLK; input GSR; input GTS; @@ -9508,14 +9550,14 @@ module STARTUP_SPARTAN3E (...); endmodule (* keep *) -module STARTUP_SPARTAN3A (...); +module STARTUP_SPARTAN3A(CLK, GSR, GTS); input CLK; input GSR; input GTS; endmodule (* keep *) -module STARTUP_SPARTAN6 (...); +module STARTUP_SPARTAN6(CFGCLK, CFGMCLK, EOS, CLK, GSR, GTS, KEYCLEARB); output CFGCLK; output CFGMCLK; output EOS; @@ -9526,7 +9568,7 @@ module STARTUP_SPARTAN6 (...); endmodule (* keep *) -module STARTUP_VIRTEX4 (...); +module STARTUP_VIRTEX4(EOS, CLK, GSR, GTS, USRCCLKO, USRCCLKTS, USRDONEO, USRDONETS); output EOS; input CLK; input GSR; @@ -9538,7 +9580,7 @@ module STARTUP_VIRTEX4 (...); endmodule (* keep *) -module STARTUP_VIRTEX5 (...); +module STARTUP_VIRTEX5(CFGCLK, CFGMCLK, DINSPI, EOS, TCKSPI, CLK, GSR, GTS, USRCCLKO, USRCCLKTS, USRDONEO, USRDONETS); output CFGCLK; output CFGMCLK; output DINSPI; @@ -9554,7 +9596,7 @@ module STARTUP_VIRTEX5 (...); endmodule (* keep *) -module STARTUP_VIRTEX6 (...); +module STARTUP_VIRTEX6(CFGCLK, CFGMCLK, DINSPI, EOS, PREQ, TCKSPI, CLK, GSR, GTS, KEYCLEARB, PACK, USRCCLKO, USRCCLKTS, USRDONEO, USRDONETS); parameter PROG_USR = "FALSE"; output CFGCLK; output CFGMCLK; @@ -9574,7 +9616,7 @@ module STARTUP_VIRTEX6 (...); endmodule (* keep *) -module STARTUPE2 (...); +module STARTUPE2(CFGCLK, CFGMCLK, EOS, PREQ, CLK, GSR, GTS, KEYCLEARB, PACK, USRCCLKO, USRCCLKTS, USRDONEO, USRDONETS); parameter PROG_USR = "FALSE"; parameter real SIM_CCLK_FREQ = 0.0; output CFGCLK; @@ -9593,7 +9635,7 @@ module STARTUPE2 (...); endmodule (* keep *) -module STARTUPE3 (...); +module STARTUPE3(CFGCLK, CFGMCLK, DI, EOS, PREQ, DO, DTS, FCSBO, FCSBTS, GSR, GTS, KEYCLEARB, PACK, USRCCLKO, USRCCLKTS, USRDONEO, USRDONETS); parameter PROG_USR = "FALSE"; parameter real SIM_CCLK_FREQ = 0.0; output CFGCLK; @@ -9616,49 +9658,49 @@ module STARTUPE3 (...); endmodule (* keep *) -module CAPTURE_SPARTAN3 (...); +module CAPTURE_SPARTAN3(CAP, CLK); parameter ONESHOT = "FALSE"; input CAP; input CLK; endmodule (* keep *) -module CAPTURE_SPARTAN3A (...); +module CAPTURE_SPARTAN3A(CAP, CLK); parameter ONESHOT = "TRUE"; input CAP; input CLK; endmodule (* keep *) -module CAPTURE_VIRTEX4 (...); +module CAPTURE_VIRTEX4(CAP, CLK); parameter ONESHOT = "TRUE"; input CAP; input CLK; endmodule (* keep *) -module CAPTURE_VIRTEX5 (...); +module CAPTURE_VIRTEX5(CAP, CLK); parameter ONESHOT = "TRUE"; input CAP; input CLK; endmodule (* keep *) -module CAPTURE_VIRTEX6 (...); +module CAPTURE_VIRTEX6(CAP, CLK); parameter ONESHOT = "TRUE"; input CAP; input CLK; endmodule (* keep *) -module CAPTUREE2 (...); +module CAPTUREE2(CAP, CLK); parameter ONESHOT = "TRUE"; input CAP; input CLK; endmodule (* keep *) -module ICAP_SPARTAN3A (...); +module ICAP_SPARTAN3A(BUSY, O, CE, CLK, WRITE, I); output BUSY; output [7:0] O; input CE; @@ -9668,7 +9710,7 @@ module ICAP_SPARTAN3A (...); endmodule (* keep *) -module ICAP_SPARTAN6 (...); +module ICAP_SPARTAN6(BUSY, O, CLK, CE, WRITE, I); parameter DEVICE_ID = 32'h04000093; parameter SIM_CFG_FILE_NAME = "NONE"; output BUSY; @@ -9680,7 +9722,7 @@ module ICAP_SPARTAN6 (...); endmodule (* keep *) -module ICAP_VIRTEX4 (...); +module ICAP_VIRTEX4(BUSY, O, CE, CLK, WRITE, I); parameter ICAP_WIDTH = "X8"; output BUSY; output [31:0] O; @@ -9691,7 +9733,7 @@ module ICAP_VIRTEX4 (...); endmodule (* keep *) -module ICAP_VIRTEX5 (...); +module ICAP_VIRTEX5(BUSY, O, CE, CLK, WRITE, I); parameter ICAP_WIDTH = "X8"; output BUSY; output [31:0] O; @@ -9702,7 +9744,7 @@ module ICAP_VIRTEX5 (...); endmodule (* keep *) -module ICAP_VIRTEX6 (...); +module ICAP_VIRTEX6(BUSY, O, CLK, CSB, RDWRB, I); parameter [31:0] DEVICE_ID = 32'h04244093; parameter ICAP_WIDTH = "X8"; parameter SIM_CFG_FILE_NAME = "NONE"; @@ -9715,7 +9757,7 @@ module ICAP_VIRTEX6 (...); endmodule (* keep *) -module ICAPE2 (...); +module ICAPE2(O, CLK, CSIB, RDWRB, I); parameter [31:0] DEVICE_ID = 32'h04244093; parameter ICAP_WIDTH = "X32"; parameter SIM_CFG_FILE_NAME = "NONE"; @@ -9727,7 +9769,7 @@ module ICAPE2 (...); endmodule (* keep *) -module ICAPE3 (...); +module ICAPE3(AVAIL, O, PRDONE, PRERROR, CLK, CSIB, RDWRB, I); parameter [31:0] DEVICE_ID = 32'h03628093; parameter ICAP_AUTO_SWITCH = "DISABLE"; parameter SIM_CFG_FILE_NAME = "NONE"; @@ -9742,7 +9784,7 @@ module ICAPE3 (...); endmodule (* keep *) -module BSCAN_SPARTAN3 (...); +module BSCAN_SPARTAN3(CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE, TDO1, TDO2); output CAPTURE; output DRCK1; output DRCK2; @@ -9757,7 +9799,7 @@ module BSCAN_SPARTAN3 (...); endmodule (* keep *) -module BSCAN_SPARTAN3A (...); +module BSCAN_SPARTAN3A(CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TCK, TDI, TMS, UPDATE, TDO1, TDO2); output CAPTURE; output DRCK1; output DRCK2; @@ -9774,7 +9816,7 @@ module BSCAN_SPARTAN3A (...); endmodule (* keep *) -module BSCAN_SPARTAN6 (...); +module BSCAN_SPARTAN6(CAPTURE, DRCK, RESET, RUNTEST, SEL, SHIFT, TCK, TDI, TMS, UPDATE, TDO); parameter integer JTAG_CHAIN = 1; output CAPTURE; output DRCK; @@ -9790,7 +9832,7 @@ module BSCAN_SPARTAN6 (...); endmodule (* keep *) -module BSCAN_VIRTEX4 (...); +module BSCAN_VIRTEX4(CAPTURE, DRCK, RESET, SEL, SHIFT, TDI, UPDATE, TDO); parameter integer JTAG_CHAIN = 1; output CAPTURE; output DRCK; @@ -9803,7 +9845,7 @@ module BSCAN_VIRTEX4 (...); endmodule (* keep *) -module BSCAN_VIRTEX5 (...); +module BSCAN_VIRTEX5(CAPTURE, DRCK, RESET, SEL, SHIFT, TDI, UPDATE, TDO); parameter integer JTAG_CHAIN = 1; output CAPTURE; output DRCK; @@ -9816,7 +9858,7 @@ module BSCAN_VIRTEX5 (...); endmodule (* keep *) -module BSCAN_VIRTEX6 (...); +module BSCAN_VIRTEX6(CAPTURE, DRCK, RESET, RUNTEST, SEL, SHIFT, TCK, TDI, TMS, UPDATE, TDO); parameter DISABLE_JTAG = "FALSE"; parameter integer JTAG_CHAIN = 1; output CAPTURE; @@ -9833,7 +9875,7 @@ module BSCAN_VIRTEX6 (...); endmodule (* keep *) -module BSCANE2 (...); +module BSCANE2(CAPTURE, DRCK, RESET, RUNTEST, SEL, SHIFT, TCK, TDI, TMS, UPDATE, TDO); parameter DISABLE_JTAG = "FALSE"; parameter integer JTAG_CHAIN = 1; output CAPTURE; @@ -9849,7 +9891,7 @@ module BSCANE2 (...); input TDO; endmodule -module DNA_PORT (...); +module DNA_PORT(DOUT, CLK, DIN, READ, SHIFT); parameter [56:0] SIM_DNA_VALUE = 57'h0; output DOUT; input CLK; @@ -9858,7 +9900,7 @@ module DNA_PORT (...); input SHIFT; endmodule -module DNA_PORTE2 (...); +module DNA_PORTE2(DOUT, CLK, DIN, READ, SHIFT); parameter [95:0] SIM_DNA_VALUE = 96'h000000000000000000000000; output DOUT; input CLK; @@ -9867,20 +9909,20 @@ module DNA_PORTE2 (...); input SHIFT; endmodule -module FRAME_ECC_VIRTEX4 (...); +module FRAME_ECC_VIRTEX4(ERROR, SYNDROME, SYNDROMEVALID); output ERROR; output [11:0] SYNDROME; output SYNDROMEVALID; endmodule -module FRAME_ECC_VIRTEX5 (...); +module FRAME_ECC_VIRTEX5(CRCERROR, ECCERROR, SYNDROMEVALID, SYNDROME); output CRCERROR; output ECCERROR; output SYNDROMEVALID; output [11:0] SYNDROME; endmodule -module FRAME_ECC_VIRTEX6 (...); +module FRAME_ECC_VIRTEX6(CRCERROR, ECCERROR, ECCERRORSINGLE, SYNDROMEVALID, SYNDROME, FAR, SYNBIT, SYNWORD); parameter FARSRC = "EFAR"; parameter FRAME_RBT_IN_FILENAME = "NONE"; output CRCERROR; @@ -9893,7 +9935,7 @@ module FRAME_ECC_VIRTEX6 (...); output [6:0] SYNWORD; endmodule -module FRAME_ECCE2 (...); +module FRAME_ECCE2(CRCERROR, ECCERROR, ECCERRORSINGLE, SYNDROMEVALID, SYNDROME, FAR, SYNBIT, SYNWORD); parameter FARSRC = "EFAR"; parameter FRAME_RBT_IN_FILENAME = "NONE"; output CRCERROR; @@ -9906,7 +9948,7 @@ module FRAME_ECCE2 (...); output [6:0] SYNWORD; endmodule -module FRAME_ECCE3 (...); +module FRAME_ECCE3(CRCERROR, ECCERRORNOTSINGLE, ECCERRORSINGLE, ENDOFFRAME, ENDOFSCAN, FAR, FARSEL, ICAPBOTCLK, ICAPTOPCLK); output CRCERROR; output ECCERRORNOTSINGLE; output ECCERRORSINGLE; @@ -9918,7 +9960,7 @@ module FRAME_ECCE3 (...); input ICAPTOPCLK; endmodule -module FRAME_ECCE4 (...); +module FRAME_ECCE4(CRCERROR, ECCERRORNOTSINGLE, ECCERRORSINGLE, ENDOFFRAME, ENDOFSCAN, FAR, FARSEL, ICAPBOTCLK, ICAPTOPCLK); output CRCERROR; output ECCERRORNOTSINGLE; output ECCERRORSINGLE; @@ -9930,47 +9972,47 @@ module FRAME_ECCE4 (...); input ICAPTOPCLK; endmodule -module USR_ACCESS_VIRTEX4 (...); +module USR_ACCESS_VIRTEX4(DATA, DATAVALID); output [31:0] DATA; output DATAVALID; endmodule -module USR_ACCESS_VIRTEX5 (...); +module USR_ACCESS_VIRTEX5(CFGCLK, DATA, DATAVALID); output CFGCLK; output [31:0] DATA; output DATAVALID; endmodule -module USR_ACCESS_VIRTEX6 (...); +module USR_ACCESS_VIRTEX6(CFGCLK, DATA, DATAVALID); output CFGCLK; output [31:0] DATA; output DATAVALID; endmodule -module USR_ACCESSE2 (...); +module USR_ACCESSE2(CFGCLK, DATAVALID, DATA); output CFGCLK; output DATAVALID; output [31:0] DATA; endmodule -module POST_CRC_INTERNAL (...); +module POST_CRC_INTERNAL(CRCERROR); output CRCERROR; endmodule (* keep *) -module SUSPEND_SYNC (...); +module SUSPEND_SYNC(SREQ, CLK, SACK); output SREQ; input CLK; input SACK; endmodule (* keep *) -module KEY_CLEAR (...); +module KEY_CLEAR(KEYCLEARB); input KEYCLEARB; endmodule (* keep *) -module MASTER_JTAG (...); +module MASTER_JTAG(TDO, TCK, TDI, TMS); output TDO; input TCK; input TDI; @@ -9978,7 +10020,7 @@ module MASTER_JTAG (...); endmodule (* keep *) -module SPI_ACCESS (...); +module SPI_ACCESS(MISO, CLK, CSB, MOSI); parameter SIM_DELAY_TYPE = "SCALED"; parameter SIM_DEVICE = "3S1400AN"; parameter SIM_FACTORY_ID = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; @@ -9990,13 +10032,14 @@ module SPI_ACCESS (...); input MOSI; endmodule -module EFUSE_USR (...); +module EFUSE_USR(EFUSEUSR); parameter [31:0] SIM_EFUSE_VALUE = 32'h00000000; output [31:0] EFUSEUSR; endmodule (* keep *) -module SYSMON (...); +module SYSMON(BUSY, DRDY, EOC, EOS, JTAGBUSY, JTAGLOCKED, JTAGMODIFIED, OT, DO, ALM, CHANNEL, CONVST, CONVSTCLK, DCLK, DEN, DWE, RESET, VN, VP, DI, VAUXN +, VAUXP, DADDR); parameter [15:0] INIT_40 = 16'h0; parameter [15:0] INIT_41 = 16'h0; parameter [15:0] INIT_42 = 16'h0800; @@ -10049,7 +10092,8 @@ module SYSMON (...); endmodule (* keep *) -module XADC (...); +module XADC(BUSY, DRDY, EOC, EOS, JTAGBUSY, JTAGLOCKED, JTAGMODIFIED, OT, DO, ALM, CHANNEL, MUXADDR, CONVST, CONVSTCLK, DCLK, DEN, DWE, RESET, VN, VP, DI +, VAUXN, VAUXP, DADDR); parameter [15:0] INIT_40 = 16'h0; parameter [15:0] INIT_41 = 16'h0; parameter [15:0] INIT_42 = 16'h0800; @@ -10115,7 +10159,8 @@ module XADC (...); endmodule (* keep *) -module SYSMONE1 (...); +module SYSMONE1(ALM, BUSY, CHANNEL, DO, DRDY, EOC, EOS, I2C_SCLK_TS, I2C_SDA_TS, JTAGBUSY, JTAGLOCKED, JTAGMODIFIED, MUXADDR, OT, CONVST, CONVSTCLK, DADDR, DCLK, DEN, DI, DWE +, I2C_SCLK, I2C_SDA, RESET, VAUXN, VAUXP, VN, VP); parameter [15:0] INIT_40 = 16'h0; parameter [15:0] INIT_41 = 16'h0; parameter [15:0] INIT_42 = 16'h0; @@ -10224,7 +10269,8 @@ module SYSMONE1 (...); endmodule (* keep *) -module SYSMONE4 (...); +module SYSMONE4(ADC_DATA, ALM, BUSY, CHANNEL, DO, DRDY, EOC, EOS, I2C_SCLK_TS, I2C_SDA_TS, JTAGBUSY, JTAGLOCKED, JTAGMODIFIED, MUXADDR, OT, SMBALERT_TS, CONVST, CONVSTCLK, DADDR, DCLK, DEN +, DI, DWE, I2C_SCLK, I2C_SDA, RESET, VAUXN, VAUXP, VN, VP); parameter [15:0] COMMON_N_SOURCE = 16'hFFFF; parameter [15:0] INIT_40 = 16'h0000; parameter [15:0] INIT_41 = 16'h0000; @@ -10336,7 +10382,17 @@ module SYSMONE4 (...); input VP; endmodule -module GTPA1_DUAL (...); +module GTPA1_DUAL(DRDY, PHYSTATUS0, PHYSTATUS1, PLLLKDET0, PLLLKDET1, REFCLKOUT0, REFCLKOUT1, REFCLKPLL0, REFCLKPLL1, RESETDONE0, RESETDONE1, RXBYTEISALIGNED0, RXBYTEISALIGNED1, RXBYTEREALIGN0, RXBYTEREALIGN1, RXCHANBONDSEQ0, RXCHANBONDSEQ1, RXCHANISALIGNED0, RXCHANISALIGNED1, RXCHANREALIGN0, RXCHANREALIGN1 +, RXCOMMADET0, RXCOMMADET1, RXELECIDLE0, RXELECIDLE1, RXPRBSERR0, RXPRBSERR1, RXRECCLK0, RXRECCLK1, RXVALID0, RXVALID1, TXN0, TXN1, TXOUTCLK0, TXOUTCLK1, TXP0, TXP1, DRPDO, GTPCLKFBEAST, GTPCLKFBWEST, GTPCLKOUT0, GTPCLKOUT1 +, RXLOSSOFSYNC0, RXLOSSOFSYNC1, TXBUFSTATUS0, TXBUFSTATUS1, RXBUFSTATUS0, RXBUFSTATUS1, RXCHBONDO, RXCLKCORCNT0, RXCLKCORCNT1, RXSTATUS0, RXSTATUS1, RXDATA0, RXDATA1, RXCHARISCOMMA0, RXCHARISCOMMA1, RXCHARISK0, RXCHARISK1, RXDISPERR0, RXDISPERR1, RXNOTINTABLE0, RXNOTINTABLE1 +, RXRUNDISP0, RXRUNDISP1, TXKERR0, TXKERR1, TXRUNDISP0, TXRUNDISP1, RCALOUTEAST, RCALOUTWEST, TSTOUT0, TSTOUT1, CLK00, CLK01, CLK10, CLK11, CLKINEAST0, CLKINEAST1, CLKINWEST0, CLKINWEST1, DCLK, DEN, DWE +, GATERXELECIDLE0, GATERXELECIDLE1, GCLK00, GCLK01, GCLK10, GCLK11, GTPRESET0, GTPRESET1, IGNORESIGDET0, IGNORESIGDET1, INTDATAWIDTH0, INTDATAWIDTH1, PLLCLK00, PLLCLK01, PLLCLK10, PLLCLK11, PLLLKDETEN0, PLLLKDETEN1, PLLPOWERDOWN0, PLLPOWERDOWN1, PRBSCNTRESET0 +, PRBSCNTRESET1, REFCLKPWRDNB0, REFCLKPWRDNB1, RXBUFRESET0, RXBUFRESET1, RXCDRRESET0, RXCDRRESET1, RXCHBONDMASTER0, RXCHBONDMASTER1, RXCHBONDSLAVE0, RXCHBONDSLAVE1, RXCOMMADETUSE0, RXCOMMADETUSE1, RXDEC8B10BUSE0, RXDEC8B10BUSE1, RXENCHANSYNC0, RXENCHANSYNC1, RXENMCOMMAALIGN0, RXENMCOMMAALIGN1, RXENPCOMMAALIGN0, RXENPCOMMAALIGN1 +, RXENPMAPHASEALIGN0, RXENPMAPHASEALIGN1, RXN0, RXN1, RXP0, RXP1, RXPMASETPHASE0, RXPMASETPHASE1, RXPOLARITY0, RXPOLARITY1, RXRESET0, RXRESET1, RXSLIDE0, RXSLIDE1, RXUSRCLK0, RXUSRCLK1, RXUSRCLK20, RXUSRCLK21, TSTCLK0, TSTCLK1, TXCOMSTART0 +, TXCOMSTART1, TXCOMTYPE0, TXCOMTYPE1, TXDETECTRX0, TXDETECTRX1, TXELECIDLE0, TXELECIDLE1, TXENC8B10BUSE0, TXENC8B10BUSE1, TXENPMAPHASEALIGN0, TXENPMAPHASEALIGN1, TXINHIBIT0, TXINHIBIT1, TXPDOWNASYNCH0, TXPDOWNASYNCH1, TXPMASETPHASE0, TXPMASETPHASE1, TXPOLARITY0, TXPOLARITY1, TXPRBSFORCEERR0, TXPRBSFORCEERR1 +, TXRESET0, TXRESET1, TXUSRCLK0, TXUSRCLK1, TXUSRCLK20, TXUSRCLK21, USRCODEERR0, USRCODEERR1, TSTIN0, TSTIN1, DI, GTPCLKFBSEL0EAST, GTPCLKFBSEL0WEST, GTPCLKFBSEL1EAST, GTPCLKFBSEL1WEST, RXDATAWIDTH0, RXDATAWIDTH1, RXEQMIX0, RXEQMIX1, RXPOWERDOWN0, RXPOWERDOWN1 +, TXDATAWIDTH0, TXDATAWIDTH1, TXPOWERDOWN0, TXPOWERDOWN1, LOOPBACK0, LOOPBACK1, REFSELDYPLL0, REFSELDYPLL1, RXCHBONDI, RXENPRBSTST0, RXENPRBSTST1, TXBUFDIFFCTRL0, TXBUFDIFFCTRL1, TXENPRBSTST0, TXENPRBSTST1, TXPREEMPHASIS0, TXPREEMPHASIS1, TXDATA0, TXDATA1, TXBYPASS8B10B0, TXBYPASS8B10B1 +, TXCHARDISPMODE0, TXCHARDISPMODE1, TXCHARDISPVAL0, TXCHARDISPVAL1, TXCHARISK0, TXCHARISK1, TXDIFFCTRL0, TXDIFFCTRL1, RCALINEAST, RCALINWEST, DADDR, GTPTEST0, GTPTEST1); parameter AC_CAP_DIS_0 = "TRUE"; parameter AC_CAP_DIS_1 = "TRUE"; parameter integer ALIGN_COMMA_WORD_0 = 1; @@ -10788,7 +10844,11 @@ module GTPA1_DUAL (...); input [7:0] GTPTEST1; endmodule -module GT11_CUSTOM (...); +module GT11_CUSTOM(DRDY, RXBUFERR, RXCALFAIL, RXCOMMADET, RXCYCLELIMIT, RXLOCK, RXMCLK, RXPCSHCLKOUT, RXREALIGN, RXRECCLK1, RXRECCLK2, RXSIGDET, TX1N, TX1P, TXBUFERR, TXCALFAIL, TXCYCLELIMIT, TXLOCK, TXOUTCLK1, TXOUTCLK2, TXPCSHCLKOUT +, DO, RXLOSSOFSYNC, RXCRCOUT, TXCRCOUT, CHBONDO, RXSTATUS, RXDATA, RXCHARISCOMMA, RXCHARISK, RXDISPERR, RXNOTINTABLE, RXRUNDISP, TXKERR, TXRUNDISP, DCLK, DEN, DWE, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, GREFCLK +, POWERDOWN, REFCLK1, REFCLK2, RX1N, RX1P, RXBLOCKSYNC64B66BUSE, RXCLKSTABLE, RXCOMMADETUSE, RXCRCCLK, RXCRCDATAVALID, RXCRCINIT, RXCRCINTCLK, RXCRCPD, RXCRCRESET, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXPMARESET, RXPOLARITY, RXRESET +, RXSLIDE, RXSYNC, RXUSRCLK2, RXUSRCLK, TXCLKSTABLE, TXCRCCLK, TXCRCDATAVALID, TXCRCINIT, TXCRCINTCLK, TXCRCPD, TXCRCRESET, TXENC64B66BUSE, TXENC8B10BUSE, TXENOOB, TXGEARBOX64B66BUSE, TXINHIBIT, TXPMARESET, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXSYNC +, TXUSRCLK2, TXUSRCLK, DI, LOOPBACK, RXDATAWIDTH, RXINTDATAWIDTH, TXDATAWIDTH, TXINTDATAWIDTH, RXCRCDATAWIDTH, TXCRCDATAWIDTH, CHBONDI, RXCRCIN, TXCRCIN, TXDATA, DADDR, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK); parameter ALIGN_COMMA_WORD = 1; parameter BANDGAPSEL = "FALSE"; parameter BIASRESSEL = "TRUE"; @@ -11060,7 +11120,16 @@ module GT11_CUSTOM (...); input [7:0] TXCHARISK; endmodule -module GT11_DUAL (...); +module GT11_DUAL(DRDYA, DRDYB, RXBUFERRA, RXBUFERRB, RXCALFAILA, RXCALFAILB, RXCOMMADETA, RXCOMMADETB, RXCYCLELIMITA, RXCYCLELIMITB, RXLOCKA, RXLOCKB, RXMCLKA, RXMCLKB, RXPCSHCLKOUTA, RXPCSHCLKOUTB, RXREALIGNA, RXREALIGNB, RXRECCLK1A, RXRECCLK1B, RXRECCLK2A +, RXRECCLK2B, RXSIGDETA, RXSIGDETB, TX1NA, TX1NB, TX1PA, TX1PB, TXBUFERRA, TXBUFERRB, TXCALFAILA, TXCALFAILB, TXCYCLELIMITA, TXCYCLELIMITB, TXLOCKA, TXLOCKB, TXOUTCLK1A, TXOUTCLK1B, TXOUTCLK2A, TXOUTCLK2B, TXPCSHCLKOUTA, TXPCSHCLKOUTB +, DOA, DOB, RXLOSSOFSYNCA, RXLOSSOFSYNCB, RXCRCOUTA, RXCRCOUTB, TXCRCOUTA, TXCRCOUTB, CHBONDOA, CHBONDOB, RXSTATUSA, RXSTATUSB, RXDATAA, RXDATAB, RXCHARISCOMMAA, RXCHARISCOMMAB, RXCHARISKA, RXCHARISKB, RXDISPERRA, RXDISPERRB, RXNOTINTABLEA +, RXNOTINTABLEB, RXRUNDISPA, RXRUNDISPB, TXKERRA, TXKERRB, TXRUNDISPA, TXRUNDISPB, DCLKA, DCLKB, DENA, DENB, DWEA, DWEB, ENCHANSYNCA, ENCHANSYNCB, ENMCOMMAALIGNA, ENMCOMMAALIGNB, ENPCOMMAALIGNA, ENPCOMMAALIGNB, GREFCLKA, GREFCLKB +, POWERDOWNA, POWERDOWNB, REFCLK1A, REFCLK1B, REFCLK2A, REFCLK2B, RX1NA, RX1NB, RX1PA, RX1PB, RXBLOCKSYNC64B66BUSEA, RXBLOCKSYNC64B66BUSEB, RXCLKSTABLEA, RXCLKSTABLEB, RXCOMMADETUSEA, RXCOMMADETUSEB, RXCRCCLKA, RXCRCCLKB, RXCRCDATAVALIDA, RXCRCDATAVALIDB, RXCRCINITA +, RXCRCINITB, RXCRCINTCLKA, RXCRCINTCLKB, RXCRCPDA, RXCRCPDB, RXCRCRESETA, RXCRCRESETB, RXDEC64B66BUSEA, RXDEC64B66BUSEB, RXDEC8B10BUSEA, RXDEC8B10BUSEB, RXDESCRAM64B66BUSEA, RXDESCRAM64B66BUSEB, RXIGNOREBTFA, RXIGNOREBTFB, RXPMARESETA, RXPMARESETB, RXPOLARITYA, RXPOLARITYB, RXRESETA, RXRESETB +, RXSLIDEA, RXSLIDEB, RXSYNCA, RXSYNCB, RXUSRCLK2A, RXUSRCLK2B, RXUSRCLKA, RXUSRCLKB, TXCLKSTABLEA, TXCLKSTABLEB, TXCRCCLKA, TXCRCCLKB, TXCRCDATAVALIDA, TXCRCDATAVALIDB, TXCRCINITA, TXCRCINITB, TXCRCINTCLKA, TXCRCINTCLKB, TXCRCPDA, TXCRCPDB, TXCRCRESETA +, TXCRCRESETB, TXENC64B66BUSEA, TXENC64B66BUSEB, TXENC8B10BUSEA, TXENC8B10BUSEB, TXENOOBA, TXENOOBB, TXGEARBOX64B66BUSEA, TXGEARBOX64B66BUSEB, TXINHIBITA, TXINHIBITB, TXPMARESETA, TXPMARESETB, TXPOLARITYA, TXPOLARITYB, TXRESETA, TXRESETB, TXSCRAM64B66BUSEA, TXSCRAM64B66BUSEB, TXSYNCA, TXSYNCB +, TXUSRCLK2A, TXUSRCLK2B, TXUSRCLKA, TXUSRCLKB, DIA, DIB, LOOPBACKA, LOOPBACKB, RXDATAWIDTHA, RXDATAWIDTHB, RXINTDATAWIDTHA, RXINTDATAWIDTHB, TXDATAWIDTHA, TXDATAWIDTHB, TXINTDATAWIDTHA, TXINTDATAWIDTHB, RXCRCDATAWIDTHA, RXCRCDATAWIDTHB, TXCRCDATAWIDTHA, TXCRCDATAWIDTHB, CHBONDIA +, CHBONDIB, RXCRCINA, RXCRCINB, TXCRCINA, TXCRCINB, TXDATAA, TXDATAB, DADDRA, DADDRB, TXBYPASS8B10BA, TXBYPASS8B10BB, TXCHARDISPMODEA, TXCHARDISPMODEB, TXCHARDISPVALA, TXCHARDISPVALB, TXCHARISKA, TXCHARISKB); parameter ALIGN_COMMA_WORD_A = 1; parameter ALIGN_COMMA_WORD_B = 1; parameter BANDGAPSEL_A = "FALSE"; @@ -11601,7 +11670,7 @@ module GT11_DUAL (...); input [7:0] TXCHARISKB; endmodule -module GT11CLK (...); +module GT11CLK(SYNCLK1OUT, SYNCLK2OUT, MGTCLKN, MGTCLKP, REFCLK, RXBCLK, SYNCLK1IN, SYNCLK2IN); parameter REFCLKSEL = "MGTCLK"; parameter SYNCLK1OUTEN = "ENABLE"; parameter SYNCLK2OUTEN = "DISABLE"; @@ -11615,7 +11684,7 @@ module GT11CLK (...); input SYNCLK2IN; endmodule -module GT11CLK_MGT (...); +module GT11CLK_MGT(SYNCLK1OUT, SYNCLK2OUT, MGTCLKN, MGTCLKP); parameter SYNCLK1OUTEN = "ENABLE"; parameter SYNCLK2OUTEN = "DISABLE"; output SYNCLK1OUT; @@ -11624,7 +11693,15 @@ module GT11CLK_MGT (...); input MGTCLKP; endmodule -module GTP_DUAL (...); +module GTP_DUAL(DRDY, PHYSTATUS0, PHYSTATUS1, PLLLKDET, REFCLKOUT, RESETDONE0, RESETDONE1, RXBYTEISALIGNED0, RXBYTEISALIGNED1, RXBYTEREALIGN0, RXBYTEREALIGN1, RXCHANBONDSEQ0, RXCHANBONDSEQ1, RXCHANISALIGNED0, RXCHANISALIGNED1, RXCHANREALIGN0, RXCHANREALIGN1, RXCOMMADET0, RXCOMMADET1, RXELECIDLE0, RXELECIDLE1 +, RXOVERSAMPLEERR0, RXOVERSAMPLEERR1, RXPRBSERR0, RXPRBSERR1, RXRECCLK0, RXRECCLK1, RXVALID0, RXVALID1, TXN0, TXN1, TXOUTCLK0, TXOUTCLK1, TXP0, TXP1, DO, RXDATA0, RXDATA1, RXCHARISCOMMA0, RXCHARISCOMMA1, RXCHARISK0, RXCHARISK1 +, RXDISPERR0, RXDISPERR1, RXLOSSOFSYNC0, RXLOSSOFSYNC1, RXNOTINTABLE0, RXNOTINTABLE1, RXRUNDISP0, RXRUNDISP1, TXBUFSTATUS0, TXBUFSTATUS1, TXKERR0, TXKERR1, TXRUNDISP0, TXRUNDISP1, RXBUFSTATUS0, RXBUFSTATUS1, RXCHBONDO0, RXCHBONDO1, RXCLKCORCNT0, RXCLKCORCNT1, RXSTATUS0 +, RXSTATUS1, CLKIN, DCLK, DEN, DWE, GTPRESET, INTDATAWIDTH, PLLLKDETEN, PLLPOWERDOWN, PRBSCNTRESET0, PRBSCNTRESET1, REFCLKPWRDNB, RXBUFRESET0, RXBUFRESET1, RXCDRRESET0, RXCDRRESET1, RXCOMMADETUSE0, RXCOMMADETUSE1, RXDATAWIDTH0, RXDATAWIDTH1, RXDEC8B10BUSE0 +, RXDEC8B10BUSE1, RXELECIDLERESET0, RXELECIDLERESET1, RXENCHANSYNC0, RXENCHANSYNC1, RXENELECIDLERESETB, RXENEQB0, RXENEQB1, RXENMCOMMAALIGN0, RXENMCOMMAALIGN1, RXENPCOMMAALIGN0, RXENPCOMMAALIGN1, RXENSAMPLEALIGN0, RXENSAMPLEALIGN1, RXN0, RXN1, RXP0, RXP1, RXPMASETPHASE0, RXPMASETPHASE1, RXPOLARITY0 +, RXPOLARITY1, RXRESET0, RXRESET1, RXSLIDE0, RXSLIDE1, RXUSRCLK0, RXUSRCLK1, RXUSRCLK20, RXUSRCLK21, TXCOMSTART0, TXCOMSTART1, TXCOMTYPE0, TXCOMTYPE1, TXDATAWIDTH0, TXDATAWIDTH1, TXDETECTRX0, TXDETECTRX1, TXELECIDLE0, TXELECIDLE1, TXENC8B10BUSE0, TXENC8B10BUSE1 +, TXENPMAPHASEALIGN, TXINHIBIT0, TXINHIBIT1, TXPMASETPHASE, TXPOLARITY0, TXPOLARITY1, TXRESET0, TXRESET1, TXUSRCLK0, TXUSRCLK1, TXUSRCLK20, TXUSRCLK21, DI, TXDATA0, TXDATA1, RXENPRBSTST0, RXENPRBSTST1, RXEQMIX0, RXEQMIX1, RXPOWERDOWN0, RXPOWERDOWN1 +, TXBYPASS8B10B0, TXBYPASS8B10B1, TXCHARDISPMODE0, TXCHARDISPMODE1, TXCHARDISPVAL0, TXCHARDISPVAL1, TXCHARISK0, TXCHARISK1, TXENPRBSTST0, TXENPRBSTST1, TXPOWERDOWN0, TXPOWERDOWN1, LOOPBACK0, LOOPBACK1, RXCHBONDI0, RXCHBONDI1, TXBUFDIFFCTRL0, TXBUFDIFFCTRL1, TXDIFFCTRL0, TXDIFFCTRL1, TXPREEMPHASIS0 +, TXPREEMPHASIS1, GTPTEST, RXEQPOLE0, RXEQPOLE1, DADDR); parameter AC_CAP_DIS_0 = "TRUE"; parameter AC_CAP_DIS_1 = "TRUE"; parameter CHAN_BOND_MODE_0 = "OFF"; @@ -11981,7 +12058,17 @@ module GTP_DUAL (...); input [6:0] DADDR; endmodule -module GTX_DUAL (...); +module GTX_DUAL(DRDY, PHYSTATUS0, PHYSTATUS1, PLLLKDET, REFCLKOUT, RESETDONE0, RESETDONE1, RXBYTEISALIGNED0, RXBYTEISALIGNED1, RXBYTEREALIGN0, RXBYTEREALIGN1, RXCHANBONDSEQ0, RXCHANBONDSEQ1, RXCHANISALIGNED0, RXCHANISALIGNED1, RXCHANREALIGN0, RXCHANREALIGN1, RXCOMMADET0, RXCOMMADET1, RXDATAVALID0, RXDATAVALID1 +, RXELECIDLE0, RXELECIDLE1, RXHEADERVALID0, RXHEADERVALID1, RXOVERSAMPLEERR0, RXOVERSAMPLEERR1, RXPRBSERR0, RXPRBSERR1, RXRECCLK0, RXRECCLK1, RXSTARTOFSEQ0, RXSTARTOFSEQ1, RXVALID0, RXVALID1, TXGEARBOXREADY0, TXGEARBOXREADY1, TXN0, TXN1, TXOUTCLK0, TXOUTCLK1, TXP0 +, TXP1, DO, RXLOSSOFSYNC0, RXLOSSOFSYNC1, TXBUFSTATUS0, TXBUFSTATUS1, DFESENSCAL0, DFESENSCAL1, RXBUFSTATUS0, RXBUFSTATUS1, RXCLKCORCNT0, RXCLKCORCNT1, RXHEADER0, RXHEADER1, RXSTATUS0, RXSTATUS1, RXDATA0, RXDATA1, DFETAP3MONITOR0, DFETAP3MONITOR1, DFETAP4MONITOR0 +, DFETAP4MONITOR1, RXCHARISCOMMA0, RXCHARISCOMMA1, RXCHARISK0, RXCHARISK1, RXCHBONDO0, RXCHBONDO1, RXDISPERR0, RXDISPERR1, RXNOTINTABLE0, RXNOTINTABLE1, RXRUNDISP0, RXRUNDISP1, TXKERR0, TXKERR1, TXRUNDISP0, TXRUNDISP1, DFEEYEDACMONITOR0, DFEEYEDACMONITOR1, DFETAP1MONITOR0, DFETAP1MONITOR1 +, DFETAP2MONITOR0, DFETAP2MONITOR1, DFECLKDLYADJMONITOR0, DFECLKDLYADJMONITOR1, CLKIN, DCLK, DEN, DWE, GTXRESET, INTDATAWIDTH, PLLLKDETEN, PLLPOWERDOWN, PRBSCNTRESET0, PRBSCNTRESET1, REFCLKPWRDNB, RXBUFRESET0, RXBUFRESET1, RXCDRRESET0, RXCDRRESET1, RXCOMMADETUSE0, RXCOMMADETUSE1 +, RXDEC8B10BUSE0, RXDEC8B10BUSE1, RXENCHANSYNC0, RXENCHANSYNC1, RXENEQB0, RXENEQB1, RXENMCOMMAALIGN0, RXENMCOMMAALIGN1, RXENPCOMMAALIGN0, RXENPCOMMAALIGN1, RXENPMAPHASEALIGN0, RXENPMAPHASEALIGN1, RXENSAMPLEALIGN0, RXENSAMPLEALIGN1, RXGEARBOXSLIP0, RXGEARBOXSLIP1, RXN0, RXN1, RXP0, RXP1, RXPMASETPHASE0 +, RXPMASETPHASE1, RXPOLARITY0, RXPOLARITY1, RXRESET0, RXRESET1, RXSLIDE0, RXSLIDE1, RXUSRCLK0, RXUSRCLK1, RXUSRCLK20, RXUSRCLK21, TXCOMSTART0, TXCOMSTART1, TXCOMTYPE0, TXCOMTYPE1, TXDETECTRX0, TXDETECTRX1, TXELECIDLE0, TXELECIDLE1, TXENC8B10BUSE0, TXENC8B10BUSE1 +, TXENPMAPHASEALIGN0, TXENPMAPHASEALIGN1, TXINHIBIT0, TXINHIBIT1, TXPMASETPHASE0, TXPMASETPHASE1, TXPOLARITY0, TXPOLARITY1, TXRESET0, TXRESET1, TXSTARTSEQ0, TXSTARTSEQ1, TXUSRCLK0, TXUSRCLK1, TXUSRCLK20, TXUSRCLK21, GTXTEST, DI, RXDATAWIDTH0, RXDATAWIDTH1, RXENPRBSTST0 +, RXENPRBSTST1, RXEQMIX0, RXEQMIX1, RXPOWERDOWN0, RXPOWERDOWN1, TXDATAWIDTH0, TXDATAWIDTH1, TXENPRBSTST0, TXENPRBSTST1, TXPOWERDOWN0, TXPOWERDOWN1, LOOPBACK0, LOOPBACK1, TXBUFDIFFCTRL0, TXBUFDIFFCTRL1, TXDIFFCTRL0, TXDIFFCTRL1, TXHEADER0, TXHEADER1, TXDATA0, TXDATA1 +, DFETAP30, DFETAP31, DFETAP40, DFETAP41, RXCHBONDI0, RXCHBONDI1, RXEQPOLE0, RXEQPOLE1, TXBYPASS8B10B0, TXBYPASS8B10B1, TXCHARDISPMODE0, TXCHARDISPMODE1, TXCHARDISPVAL0, TXCHARDISPVAL1, TXCHARISK0, TXCHARISK1, TXPREEMPHASIS0, TXPREEMPHASIS1, DFETAP10, DFETAP11, DFETAP20 +, DFETAP21, DFECLKDLYADJ0, DFECLKDLYADJ1, DADDR, TXSEQUENCE0, TXSEQUENCE1); parameter STEPPING = "0"; parameter AC_CAP_DIS_0 = "TRUE"; parameter AC_CAP_DIS_1 = "TRUE"; @@ -12417,7 +12504,7 @@ module GTX_DUAL (...); input [6:0] TXSEQUENCE1; endmodule -module CRC32 (...); +module CRC32(CRCOUT, CRCCLK, CRCDATAVALID, CRCDATAWIDTH, CRCIN, CRCRESET); parameter CRC_INIT = 32'hFFFFFFFF; output [31:0] CRCOUT; (* clkbuf_sink *) @@ -12428,7 +12515,7 @@ module CRC32 (...); input CRCRESET; endmodule -module CRC64 (...); +module CRC64(CRCOUT, CRCCLK, CRCDATAVALID, CRCDATAWIDTH, CRCIN, CRCRESET); parameter CRC_INIT = 32'hFFFFFFFF; output [31:0] CRCOUT; (* clkbuf_sink *) @@ -12439,7 +12526,15 @@ module CRC64 (...); input CRCRESET; endmodule -module GTHE1_QUAD (...); +module GTHE1_QUAD(DRDY, GTHINITDONE, MGMTPCSRDACK, RXCTRLACK0, RXCTRLACK1, RXCTRLACK2, RXCTRLACK3, RXDATATAP0, RXDATATAP1, RXDATATAP2, RXDATATAP3, RXPCSCLKSMPL0, RXPCSCLKSMPL1, RXPCSCLKSMPL2, RXPCSCLKSMPL3, RXUSERCLKOUT0, RXUSERCLKOUT1, RXUSERCLKOUT2, RXUSERCLKOUT3, TSTPATH, TSTREFCLKFAB +, TSTREFCLKOUT, TXCTRLACK0, TXCTRLACK1, TXCTRLACK2, TXCTRLACK3, TXDATATAP10, TXDATATAP11, TXDATATAP12, TXDATATAP13, TXDATATAP20, TXDATATAP21, TXDATATAP22, TXDATATAP23, TXN0, TXN1, TXN2, TXN3, TXP0, TXP1, TXP2, TXP3 +, TXPCSCLKSMPL0, TXPCSCLKSMPL1, TXPCSCLKSMPL2, TXPCSCLKSMPL3, TXUSERCLKOUT0, TXUSERCLKOUT1, TXUSERCLKOUT2, TXUSERCLKOUT3, DRPDO, MGMTPCSRDDATA, RXDATA0, RXDATA1, RXDATA2, RXDATA3, RXCODEERR0, RXCODEERR1, RXCODEERR2, RXCODEERR3, RXCTRL0, RXCTRL1, RXCTRL2 +, RXCTRL3, RXDISPERR0, RXDISPERR1, RXDISPERR2, RXDISPERR3, RXVALID0, RXVALID1, RXVALID2, RXVALID3, DCLK, DEN, DFETRAINCTRL0, DFETRAINCTRL1, DFETRAINCTRL2, DFETRAINCTRL3, DISABLEDRP, DWE, GTHINIT, GTHRESET, GTHX2LANE01, GTHX2LANE23 +, GTHX4LANE, MGMTPCSREGRD, MGMTPCSREGWR, POWERDOWN0, POWERDOWN1, POWERDOWN2, POWERDOWN3, REFCLK, RXBUFRESET0, RXBUFRESET1, RXBUFRESET2, RXBUFRESET3, RXENCOMMADET0, RXENCOMMADET1, RXENCOMMADET2, RXENCOMMADET3, RXN0, RXN1, RXN2, RXN3, RXP0 +, RXP1, RXP2, RXP3, RXPOLARITY0, RXPOLARITY1, RXPOLARITY2, RXPOLARITY3, RXSLIP0, RXSLIP1, RXSLIP2, RXSLIP3, RXUSERCLKIN0, RXUSERCLKIN1, RXUSERCLKIN2, RXUSERCLKIN3, TXBUFRESET0, TXBUFRESET1, TXBUFRESET2, TXBUFRESET3, TXDEEMPH0, TXDEEMPH1 +, TXDEEMPH2, TXDEEMPH3, TXUSERCLKIN0, TXUSERCLKIN1, TXUSERCLKIN2, TXUSERCLKIN3, DADDR, DI, MGMTPCSREGADDR, MGMTPCSWRDATA, RXPOWERDOWN0, RXPOWERDOWN1, RXPOWERDOWN2, RXPOWERDOWN3, RXRATE0, RXRATE1, RXRATE2, RXRATE3, TXPOWERDOWN0, TXPOWERDOWN1, TXPOWERDOWN2 +, TXPOWERDOWN3, TXRATE0, TXRATE1, TXRATE2, TXRATE3, PLLREFCLKSEL, SAMPLERATE0, SAMPLERATE1, SAMPLERATE2, SAMPLERATE3, TXMARGIN0, TXMARGIN1, TXMARGIN2, TXMARGIN3, MGMTPCSLANESEL, MGMTPCSMMDADDR, PLLPCSCLKDIV, TXDATA0, TXDATA1, TXDATA2, TXDATA3 +, TXCTRL0, TXCTRL1, TXCTRL2, TXCTRL3, TXDATAMSB0, TXDATAMSB1, TXDATAMSB2, TXDATAMSB3); parameter [15:0] BER_CONST_PTRN0 = 16'h0000; parameter [15:0] BER_CONST_PTRN1 = 16'h0000; parameter [15:0] BUFFER_CONFIG_LANE0 = 16'h4004; @@ -12907,7 +13002,15 @@ module GTHE1_QUAD (...); input [7:0] TXDATAMSB3; endmodule -module GTXE1 (...); +module GTXE1(COMFINISH, COMINITDET, COMSASDET, COMWAKEDET, DRDY, PHYSTATUS, RXBYTEISALIGNED, RXBYTEREALIGN, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCOMMADET, RXDATAVALID, RXELECIDLE, RXHEADERVALID, RXOVERSAMPLEERR, RXPLLLKDET, RXPRBSERR, RXRATEDONE, RXRECCLK, RXRECCLKPCS +, RXRESETDONE, RXSTARTOFSEQ, RXVALID, TXGEARBOXREADY, TXN, TXOUTCLK, TXOUTCLKPCS, TXP, TXPLLLKDET, TXRATEDONE, TXRESETDONE, DRPDO, MGTREFCLKFAB, RXLOSSOFSYNC, TXBUFSTATUS, DFESENSCAL, RXBUFSTATUS, RXCLKCORCNT, RXHEADER, RXSTATUS, RXDATA +, DFETAP3MONITOR, DFETAP4MONITOR, RXCHARISCOMMA, RXCHARISK, RXCHBONDO, RXDISPERR, RXNOTINTABLE, RXRUNDISP, TXKERR, TXRUNDISP, DFEEYEDACMON, DFETAP1MONITOR, DFETAP2MONITOR, DFECLKDLYADJMON, RXDLYALIGNMONITOR, TXDLYALIGNMONITOR, TSTOUT, DCLK, DEN, DFEDLYOVRD, DFETAPOVRD +, DWE, GATERXELECIDLE, GREFCLKRX, GREFCLKTX, GTXRXRESET, GTXTXRESET, IGNORESIGDET, PERFCLKRX, PERFCLKTX, PLLRXRESET, PLLTXRESET, PRBSCNTRESET, RXBUFRESET, RXCDRRESET, RXCHBONDMASTER, RXCHBONDSLAVE, RXCOMMADETUSE, RXDEC8B10BUSE, RXDLYALIGNDISABLE, RXDLYALIGNMONENB, RXDLYALIGNOVERRIDE +, RXDLYALIGNRESET, RXDLYALIGNSWPPRECURB, RXDLYALIGNUPDSW, RXENCHANSYNC, RXENMCOMMAALIGN, RXENPCOMMAALIGN, RXENPMAPHASEALIGN, RXENSAMPLEALIGN, RXGEARBOXSLIP, RXN, RXP, RXPLLLKDETEN, RXPLLPOWERDOWN, RXPMASETPHASE, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK2, RXUSRCLK, TSTCLK0, TSTCLK1 +, TXCOMINIT, TXCOMSAS, TXCOMWAKE, TXDEEMPH, TXDETECTRX, TXDLYALIGNDISABLE, TXDLYALIGNMONENB, TXDLYALIGNOVERRIDE, TXDLYALIGNRESET, TXDLYALIGNUPDSW, TXELECIDLE, TXENC8B10BUSE, TXENPMAPHASEALIGN, TXINHIBIT, TXPDOWNASYNCH, TXPLLLKDETEN, TXPLLPOWERDOWN, TXPMASETPHASE, TXPOLARITY, TXPRBSFORCEERR, TXRESET +, TXSTARTSEQ, TXSWING, TXUSRCLK2, TXUSRCLK, USRCODEERR, GTXTEST, DI, TSTIN, MGTREFCLKRX, MGTREFCLKTX, NORTHREFCLKRX, NORTHREFCLKTX, RXPOWERDOWN, RXRATE, SOUTHREFCLKRX, SOUTHREFCLKTX, TXPOWERDOWN, TXRATE, LOOPBACK, RXCHBONDLEVEL, RXENPRBSTST +, RXPLLREFSELDY, TXBUFDIFFCTRL, TXENPRBSTST, TXHEADER, TXMARGIN, TXPLLREFSELDY, TXDATA, DFETAP3, DFETAP4, RXCHBONDI, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDIFFCTRL, TXPREEMPHASIS, DFETAP1, DFETAP2, TXPOSTEMPHASIS, DFECLKDLYADJ, TXSEQUENCE +, DADDR, RXEQMIX); parameter AC_CAP_DIS = "TRUE"; parameter integer ALIGN_COMMA_WORD = 1; parameter [1:0] BGTEST_CFG = 2'b00; @@ -13259,7 +13362,7 @@ module GTXE1 (...); input [9:0] RXEQMIX; endmodule -module IBUFDS_GTXE1 (...); +module IBUFDS_GTXE1(O, ODIV2, CEB, I, IB); parameter CLKCM_CFG = "TRUE"; parameter CLKRCV_TRST = "TRUE"; parameter [9:0] REFCLKOUT_DLY = 10'b0000000000; @@ -13272,7 +13375,7 @@ module IBUFDS_GTXE1 (...); input IB; endmodule -module IBUFDS_GTHE1 (...); +module IBUFDS_GTHE1(O, I, IB); output O; (* iopad_external_pin *) input I; @@ -13280,7 +13383,20 @@ module IBUFDS_GTHE1 (...); input IB; endmodule -module GTHE2_CHANNEL (...); +module GTHE2_CHANNEL(CPLLFBCLKLOST, CPLLLOCK, CPLLREFCLKLOST, DRPRDY, EYESCANDATAERROR, GTHTXN, GTHTXP, GTREFCLKMONITOR, PHYSTATUS, RSOSINTDONE, RXBYTEISALIGNED, RXBYTEREALIGN, RXCDRLOCK, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCOMINITDET, RXCOMMADET, RXCOMSASDET, RXCOMWAKEDET, RXDFESLIDETAPSTARTED +, RXDFESLIDETAPSTROBEDONE, RXDFESLIDETAPSTROBESTARTED, RXDFESTADAPTDONE, RXDLYSRESETDONE, RXELECIDLE, RXOSINTSTARTED, RXOSINTSTROBEDONE, RXOSINTSTROBESTARTED, RXOUTCLK, RXOUTCLKFABRIC, RXOUTCLKPCS, RXPHALIGNDONE, RXPMARESETDONE, RXPRBSERR, RXQPISENN, RXQPISENP, RXRATEDONE, RXRESETDONE, RXSYNCDONE, RXSYNCOUT, RXVALID +, TXCOMFINISH, TXDLYSRESETDONE, TXGEARBOXREADY, TXOUTCLK, TXOUTCLKFABRIC, TXOUTCLKPCS, TXPHALIGNDONE, TXPHINITDONE, TXPMARESETDONE, TXQPISENN, TXQPISENP, TXRATEDONE, TXRESETDONE, TXSYNCDONE, TXSYNCOUT, DMONITOROUT, DRPDO, PCSRSVDOUT, RXCLKCORCNT, RXDATAVALID, RXHEADERVALID +, RXSTARTOFSEQ, TXBUFSTATUS, RXBUFSTATUS, RXSTATUS, RXCHBONDO, RXPHMONITOR, RXPHSLIPMONITOR, RXHEADER, RXDATA, RXMONITOROUT, RXCHARISCOMMA, RXCHARISK, RXDISPERR, RXNOTINTABLE, CFGRESET, CLKRSVD0, CLKRSVD1, CPLLLOCKDETCLK, CPLLLOCKEN, CPLLPD, CPLLRESET +, DMONFIFORESET, DMONITORCLK, DRPCLK, DRPEN, DRPWE, EYESCANMODE, EYESCANRESET, EYESCANTRIGGER, GTGREFCLK, GTHRXN, GTHRXP, GTNORTHREFCLK0, GTNORTHREFCLK1, GTREFCLK0, GTREFCLK1, GTRESETSEL, GTRXRESET, GTSOUTHREFCLK0, GTSOUTHREFCLK1, GTTXRESET, QPLLCLK +, QPLLREFCLK, RESETOVRD, RX8B10BEN, RXBUFRESET, RXCDRFREQRESET, RXCDRHOLD, RXCDROVRDEN, RXCDRRESET, RXCDRRESETRSV, RXCHBONDEN, RXCHBONDMASTER, RXCHBONDSLAVE, RXCOMMADETEN, RXDDIEN, RXDFEAGCHOLD, RXDFEAGCOVRDEN, RXDFECM1EN, RXDFELFHOLD, RXDFELFOVRDEN, RXDFELPMRESET, RXDFESLIDETAPADAPTEN +, RXDFESLIDETAPHOLD, RXDFESLIDETAPINITOVRDEN, RXDFESLIDETAPONLYADAPTEN, RXDFESLIDETAPOVRDEN, RXDFESLIDETAPSTROBE, RXDFETAP2HOLD, RXDFETAP2OVRDEN, RXDFETAP3HOLD, RXDFETAP3OVRDEN, RXDFETAP4HOLD, RXDFETAP4OVRDEN, RXDFETAP5HOLD, RXDFETAP5OVRDEN, RXDFETAP6HOLD, RXDFETAP6OVRDEN, RXDFETAP7HOLD, RXDFETAP7OVRDEN, RXDFEUTHOLD, RXDFEUTOVRDEN, RXDFEVPHOLD, RXDFEVPOVRDEN +, RXDFEVSEN, RXDFEXYDEN, RXDLYBYPASS, RXDLYEN, RXDLYOVRDEN, RXDLYSRESET, RXGEARBOXSLIP, RXLPMEN, RXLPMHFHOLD, RXLPMHFOVRDEN, RXLPMLFHOLD, RXLPMLFKLOVRDEN, RXMCOMMAALIGNEN, RXOOBRESET, RXOSCALRESET, RXOSHOLD, RXOSINTEN, RXOSINTHOLD, RXOSINTNTRLEN, RXOSINTOVRDEN, RXOSINTSTROBE +, RXOSINTTESTOVRDEN, RXOSOVRDEN, RXPCOMMAALIGNEN, RXPCSRESET, RXPHALIGN, RXPHALIGNEN, RXPHDLYPD, RXPHDLYRESET, RXPHOVRDEN, RXPMARESET, RXPOLARITY, RXPRBSCNTRESET, RXQPIEN, RXRATEMODE, RXSLIDE, RXSYNCALLIN, RXSYNCIN, RXSYNCMODE, RXUSERRDY, RXUSRCLK2, RXUSRCLK +, SETERRSTATUS, SIGVALIDCLK, TX8B10BEN, TXCOMINIT, TXCOMSAS, TXCOMWAKE, TXDEEMPH, TXDETECTRX, TXDIFFPD, TXDLYBYPASS, TXDLYEN, TXDLYHOLD, TXDLYOVRDEN, TXDLYSRESET, TXDLYUPDOWN, TXELECIDLE, TXINHIBIT, TXPCSRESET, TXPDELECIDLEMODE, TXPHALIGN, TXPHALIGNEN +, TXPHDLYPD, TXPHDLYRESET, TXPHDLYTSTCLK, TXPHINIT, TXPHOVRDEN, TXPIPPMEN, TXPIPPMOVRDEN, TXPIPPMPD, TXPIPPMSEL, TXPISOPD, TXPMARESET, TXPOLARITY, TXPOSTCURSORINV, TXPRBSFORCEERR, TXPRECURSORINV, TXQPIBIASEN, TXQPISTRONGPDOWN, TXQPIWEAKPUP, TXRATEMODE, TXSTARTSEQ, TXSWING +, TXSYNCALLIN, TXSYNCIN, TXSYNCMODE, TXUSERRDY, TXUSRCLK2, TXUSRCLK, RXADAPTSELTEST, DRPDI, GTRSVD, PCSRSVDIN, TSTIN, RXELECIDLEMODE, RXMONITORSEL, RXPD, RXSYSCLKSEL, TXPD, TXSYSCLKSEL, CPLLREFCLKSEL, LOOPBACK, RXCHBONDLEVEL, RXOUTCLKSEL +, RXPRBSSEL, RXRATE, TXBUFDIFFCTRL, TXHEADER, TXMARGIN, TXOUTCLKSEL, TXPRBSSEL, TXRATE, RXOSINTCFG, RXOSINTID0, TXDIFFCTRL, PCSRSVDIN2, PMARSVDIN, RXCHBONDI, RXDFEAGCTRL, RXDFESLIDETAP, TXPIPPMSTEPSIZE, TXPOSTCURSOR, TXPRECURSOR, RXDFESLIDETAPID, TXDATA +, TXMAINCURSOR, TXSEQUENCE, TX8B10BBYPASS, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, DRPADDR); parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; parameter [0:0] ACJTAG_MODE = 1'b0; parameter [0:0] ACJTAG_RESET = 1'b0; @@ -13843,7 +13959,8 @@ module GTHE2_CHANNEL (...); input [8:0] DRPADDR; endmodule -module GTHE2_COMMON (...); +module GTHE2_COMMON(DRPRDY, QPLLFBCLKLOST, QPLLLOCK, QPLLOUTCLK, QPLLOUTREFCLK, QPLLREFCLKLOST, REFCLKOUTMONITOR, DRPDO, PMARSVDOUT, QPLLDMONITOR, BGBYPASSB, BGMONITORENB, BGPDB, BGRCALOVRDENB, DRPCLK, DRPEN, DRPWE, GTGREFCLK, GTNORTHREFCLK0, GTNORTHREFCLK1, GTREFCLK0 +, GTREFCLK1, GTSOUTHREFCLK0, GTSOUTHREFCLK1, QPLLLOCKDETCLK, QPLLLOCKEN, QPLLOUTRESET, QPLLPD, QPLLRESET, RCALENB, DRPDI, QPLLRSVD1, QPLLREFCLKSEL, BGRCALOVRD, QPLLRSVD2, DRPADDR, PMARSVD); parameter [63:0] BIAS_CFG = 64'h0000040000001000; parameter [31:0] COMMON_CFG = 32'h0000001C; parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; @@ -13913,7 +14030,17 @@ module GTHE2_COMMON (...); input [7:0] PMARSVD; endmodule -module GTPE2_CHANNEL (...); +module GTPE2_CHANNEL(DRPRDY, EYESCANDATAERROR, GTPTXN, GTPTXP, PHYSTATUS, PMARSVDOUT0, PMARSVDOUT1, RXBYTEISALIGNED, RXBYTEREALIGN, RXCDRLOCK, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCOMINITDET, RXCOMMADET, RXCOMSASDET, RXCOMWAKEDET, RXDLYSRESETDONE, RXELECIDLE, RXHEADERVALID, RXOSINTDONE +, RXOSINTSTARTED, RXOSINTSTROBEDONE, RXOSINTSTROBESTARTED, RXOUTCLK, RXOUTCLKFABRIC, RXOUTCLKPCS, RXPHALIGNDONE, RXPMARESETDONE, RXPRBSERR, RXRATEDONE, RXRESETDONE, RXSYNCDONE, RXSYNCOUT, RXVALID, TXCOMFINISH, TXDLYSRESETDONE, TXGEARBOXREADY, TXOUTCLK, TXOUTCLKFABRIC, TXOUTCLKPCS, TXPHALIGNDONE +, TXPHINITDONE, TXPMARESETDONE, TXRATEDONE, TXRESETDONE, TXSYNCDONE, TXSYNCOUT, DMONITOROUT, DRPDO, PCSRSVDOUT, RXCLKCORCNT, RXDATAVALID, RXSTARTOFSEQ, TXBUFSTATUS, RXBUFSTATUS, RXHEADER, RXSTATUS, RXDATA, RXCHARISCOMMA, RXCHARISK, RXCHBONDO, RXDISPERR +, RXNOTINTABLE, RXPHMONITOR, RXPHSLIPMONITOR, CFGRESET, CLKRSVD0, CLKRSVD1, DMONFIFORESET, DMONITORCLK, DRPCLK, DRPEN, DRPWE, EYESCANMODE, EYESCANRESET, EYESCANTRIGGER, GTPRXN, GTPRXP, GTRESETSEL, GTRXRESET, GTTXRESET, PLL0CLK, PLL0REFCLK +, PLL1CLK, PLL1REFCLK, PMARSVDIN0, PMARSVDIN1, PMARSVDIN2, PMARSVDIN3, PMARSVDIN4, RESETOVRD, RX8B10BEN, RXBUFRESET, RXCDRFREQRESET, RXCDRHOLD, RXCDROVRDEN, RXCDRRESET, RXCDRRESETRSV, RXCHBONDEN, RXCHBONDMASTER, RXCHBONDSLAVE, RXCOMMADETEN, RXDDIEN, RXDFEXYDEN +, RXDLYBYPASS, RXDLYEN, RXDLYOVRDEN, RXDLYSRESET, RXGEARBOXSLIP, RXLPMHFHOLD, RXLPMHFOVRDEN, RXLPMLFHOLD, RXLPMLFOVRDEN, RXLPMOSINTNTRLEN, RXLPMRESET, RXMCOMMAALIGNEN, RXOOBRESET, RXOSCALRESET, RXOSHOLD, RXOSINTEN, RXOSINTHOLD, RXOSINTNTRLEN, RXOSINTOVRDEN, RXOSINTPD, RXOSINTSTROBE +, RXOSINTTESTOVRDEN, RXOSOVRDEN, RXPCOMMAALIGNEN, RXPCSRESET, RXPHALIGN, RXPHALIGNEN, RXPHDLYPD, RXPHDLYRESET, RXPHOVRDEN, RXPMARESET, RXPOLARITY, RXPRBSCNTRESET, RXRATEMODE, RXSLIDE, RXSYNCALLIN, RXSYNCIN, RXSYNCMODE, RXUSERRDY, RXUSRCLK2, RXUSRCLK, SETERRSTATUS +, SIGVALIDCLK, TX8B10BEN, TXCOMINIT, TXCOMSAS, TXCOMWAKE, TXDEEMPH, TXDETECTRX, TXDIFFPD, TXDLYBYPASS, TXDLYEN, TXDLYHOLD, TXDLYOVRDEN, TXDLYSRESET, TXDLYUPDOWN, TXELECIDLE, TXINHIBIT, TXPCSRESET, TXPDELECIDLEMODE, TXPHALIGN, TXPHALIGNEN, TXPHDLYPD +, TXPHDLYRESET, TXPHDLYTSTCLK, TXPHINIT, TXPHOVRDEN, TXPIPPMEN, TXPIPPMOVRDEN, TXPIPPMPD, TXPIPPMSEL, TXPISOPD, TXPMARESET, TXPOLARITY, TXPOSTCURSORINV, TXPRBSFORCEERR, TXPRECURSORINV, TXRATEMODE, TXSTARTSEQ, TXSWING, TXSYNCALLIN, TXSYNCIN, TXSYNCMODE, TXUSERRDY +, TXUSRCLK2, TXUSRCLK, RXADAPTSELTEST, DRPDI, GTRSVD, PCSRSVDIN, TSTIN, RXELECIDLEMODE, RXPD, RXSYSCLKSEL, TXPD, TXSYSCLKSEL, LOOPBACK, RXCHBONDLEVEL, RXOUTCLKSEL, RXPRBSSEL, RXRATE, TXBUFDIFFCTRL, TXHEADER, TXMARGIN, TXOUTCLKSEL +, TXPRBSSEL, TXRATE, TXDATA, RXCHBONDI, RXOSINTCFG, RXOSINTID0, TX8B10BBYPASS, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDIFFCTRL, TXPIPPMSTEPSIZE, TXPOSTCURSOR, TXPRECURSOR, TXMAINCURSOR, TXSEQUENCE, DRPADDR); parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; parameter [0:0] ACJTAG_MODE = 1'b0; parameter [0:0] ACJTAG_RESET = 1'b0; @@ -14395,7 +14522,9 @@ module GTPE2_CHANNEL (...); input [8:0] DRPADDR; endmodule -module GTPE2_COMMON (...); +module GTPE2_COMMON(DRPRDY, PLL0FBCLKLOST, PLL0LOCK, PLL0OUTCLK, PLL0OUTREFCLK, PLL0REFCLKLOST, PLL1FBCLKLOST, PLL1LOCK, PLL1OUTCLK, PLL1OUTREFCLK, PLL1REFCLKLOST, REFCLKOUTMONITOR0, REFCLKOUTMONITOR1, DRPDO, PMARSVDOUT, DMONITOROUT, BGBYPASSB, BGMONITORENB, BGPDB, BGRCALOVRDENB, DRPCLK +, DRPEN, DRPWE, GTEASTREFCLK0, GTEASTREFCLK1, GTGREFCLK0, GTGREFCLK1, GTREFCLK0, GTREFCLK1, GTWESTREFCLK0, GTWESTREFCLK1, PLL0LOCKDETCLK, PLL0LOCKEN, PLL0PD, PLL0RESET, PLL1LOCKDETCLK, PLL1LOCKEN, PLL1PD, PLL1RESET, RCALENB, DRPDI, PLLRSVD1 +, PLL0REFCLKSEL, PLL1REFCLKSEL, BGRCALOVRD, PLLRSVD2, DRPADDR, PMARSVD); parameter [63:0] BIAS_CFG = 64'h0000000000000000; parameter [31:0] COMMON_CFG = 32'h00000000; parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; @@ -14479,7 +14608,17 @@ module GTPE2_COMMON (...); input [7:0] PMARSVD; endmodule -module GTXE2_CHANNEL (...); +module GTXE2_CHANNEL(CPLLFBCLKLOST, CPLLLOCK, CPLLREFCLKLOST, DRPRDY, EYESCANDATAERROR, GTREFCLKMONITOR, GTXTXN, GTXTXP, PHYSTATUS, RXBYTEISALIGNED, RXBYTEREALIGN, RXCDRLOCK, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCOMINITDET, RXCOMMADET, RXCOMSASDET, RXCOMWAKEDET, RXDATAVALID, RXDLYSRESETDONE +, RXELECIDLE, RXHEADERVALID, RXOUTCLK, RXOUTCLKFABRIC, RXOUTCLKPCS, RXPHALIGNDONE, RXPRBSERR, RXQPISENN, RXQPISENP, RXRATEDONE, RXRESETDONE, RXSTARTOFSEQ, RXVALID, TXCOMFINISH, TXDLYSRESETDONE, TXGEARBOXREADY, TXOUTCLK, TXOUTCLKFABRIC, TXOUTCLKPCS, TXPHALIGNDONE, TXPHINITDONE +, TXQPISENN, TXQPISENP, TXRATEDONE, TXRESETDONE, DRPDO, PCSRSVDOUT, RXCLKCORCNT, TXBUFSTATUS, RXBUFSTATUS, RXHEADER, RXSTATUS, RXCHBONDO, RXPHMONITOR, RXPHSLIPMONITOR, RXDATA, RXMONITOROUT, DMONITOROUT, RXCHARISCOMMA, RXCHARISK, RXDISPERR, RXNOTINTABLE +, TSTOUT, CFGRESET, CPLLLOCKDETCLK, CPLLLOCKEN, CPLLPD, CPLLRESET, DRPCLK, DRPEN, DRPWE, EYESCANMODE, EYESCANRESET, EYESCANTRIGGER, GTGREFCLK, GTNORTHREFCLK0, GTNORTHREFCLK1, GTREFCLK0, GTREFCLK1, GTRESETSEL, GTRXRESET, GTSOUTHREFCLK0, GTSOUTHREFCLK1 +, GTTXRESET, GTXRXN, GTXRXP, QPLLCLK, QPLLREFCLK, RESETOVRD, RX8B10BEN, RXBUFRESET, RXCDRFREQRESET, RXCDRHOLD, RXCDROVRDEN, RXCDRRESET, RXCDRRESETRSV, RXCHBONDEN, RXCHBONDMASTER, RXCHBONDSLAVE, RXCOMMADETEN, RXDDIEN, RXDFEAGCHOLD, RXDFEAGCOVRDEN, RXDFECM1EN +, RXDFELFHOLD, RXDFELFOVRDEN, RXDFELPMRESET, RXDFETAP2HOLD, RXDFETAP2OVRDEN, RXDFETAP3HOLD, RXDFETAP3OVRDEN, RXDFETAP4HOLD, RXDFETAP4OVRDEN, RXDFETAP5HOLD, RXDFETAP5OVRDEN, RXDFEUTHOLD, RXDFEUTOVRDEN, RXDFEVPHOLD, RXDFEVPOVRDEN, RXDFEVSEN, RXDFEXYDEN, RXDFEXYDHOLD, RXDFEXYDOVRDEN, RXDLYBYPASS, RXDLYEN +, RXDLYOVRDEN, RXDLYSRESET, RXGEARBOXSLIP, RXLPMEN, RXLPMHFHOLD, RXLPMHFOVRDEN, RXLPMLFHOLD, RXLPMLFKLOVRDEN, RXMCOMMAALIGNEN, RXOOBRESET, RXOSHOLD, RXOSOVRDEN, RXPCOMMAALIGNEN, RXPCSRESET, RXPHALIGN, RXPHALIGNEN, RXPHDLYPD, RXPHDLYRESET, RXPHOVRDEN, RXPMARESET, RXPOLARITY +, RXPRBSCNTRESET, RXQPIEN, RXSLIDE, RXUSERRDY, RXUSRCLK2, RXUSRCLK, SETERRSTATUS, TX8B10BEN, TXCOMINIT, TXCOMSAS, TXCOMWAKE, TXDEEMPH, TXDETECTRX, TXDIFFPD, TXDLYBYPASS, TXDLYEN, TXDLYHOLD, TXDLYOVRDEN, TXDLYSRESET, TXDLYUPDOWN, TXELECIDLE +, TXINHIBIT, TXPCSRESET, TXPDELECIDLEMODE, TXPHALIGN, TXPHALIGNEN, TXPHDLYPD, TXPHDLYRESET, TXPHDLYTSTCLK, TXPHINIT, TXPHOVRDEN, TXPISOPD, TXPMARESET, TXPOLARITY, TXPOSTCURSORINV, TXPRBSFORCEERR, TXPRECURSORINV, TXQPIBIASEN, TXQPISTRONGPDOWN, TXQPIWEAKPUP, TXSTARTSEQ, TXSWING +, TXUSERRDY, TXUSRCLK2, TXUSRCLK, DRPDI, GTRSVD, PCSRSVDIN, TSTIN, RXELECIDLEMODE, RXMONITORSEL, RXPD, RXSYSCLKSEL, TXPD, TXSYSCLKSEL, CPLLREFCLKSEL, LOOPBACK, RXCHBONDLEVEL, RXOUTCLKSEL, RXPRBSSEL, RXRATE, TXBUFDIFFCTRL, TXHEADER +, TXMARGIN, TXOUTCLKSEL, TXPRBSSEL, TXRATE, CLKRSVD, TXDIFFCTRL, PCSRSVDIN2, PMARSVDIN2, PMARSVDIN, RXCHBONDI, TXPOSTCURSOR, TXPRECURSOR, TXDATA, TXMAINCURSOR, TXSEQUENCE, TX8B10BBYPASS, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, DRPADDR); parameter ALIGN_COMMA_DOUBLE = "FALSE"; parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; parameter integer ALIGN_COMMA_WORD = 1; @@ -14927,7 +15066,8 @@ module GTXE2_CHANNEL (...); input [8:0] DRPADDR; endmodule -module GTXE2_COMMON (...); +module GTXE2_COMMON(DRPRDY, QPLLFBCLKLOST, QPLLLOCK, QPLLOUTCLK, QPLLOUTREFCLK, QPLLREFCLKLOST, REFCLKOUTMONITOR, DRPDO, QPLLDMONITOR, BGBYPASSB, BGMONITORENB, BGPDB, DRPCLK, DRPEN, DRPWE, GTGREFCLK, GTNORTHREFCLK0, GTNORTHREFCLK1, GTREFCLK0, GTREFCLK1, GTSOUTHREFCLK0 +, GTSOUTHREFCLK1, QPLLLOCKDETCLK, QPLLLOCKEN, QPLLOUTRESET, QPLLPD, QPLLRESET, RCALENB, DRPDI, QPLLRSVD1, QPLLREFCLKSEL, BGRCALOVRD, QPLLRSVD2, DRPADDR, PMARSVD); parameter [63:0] BIAS_CFG = 64'h0000040000001000; parameter [31:0] COMMON_CFG = 32'h00000000; parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; @@ -14990,7 +15130,7 @@ module GTXE2_COMMON (...); input [7:0] PMARSVD; endmodule -module IBUFDS_GTE2 (...); +module IBUFDS_GTE2(O, ODIV2, CEB, I, IB); parameter CLKCM_CFG = "TRUE"; parameter CLKRCV_TRST = "TRUE"; parameter CLKSWING_CFG = "TRUE"; @@ -15003,7 +15143,22 @@ module IBUFDS_GTE2 (...); input IB; endmodule -module GTHE3_CHANNEL (...); +module GTHE3_CHANNEL(BUFGTCE, BUFGTCEMASK, BUFGTDIV, BUFGTRESET, BUFGTRSTMASK, CPLLFBCLKLOST, CPLLLOCK, CPLLREFCLKLOST, DMONITOROUT, DRPDO, DRPRDY, EYESCANDATAERROR, GTHTXN, GTHTXP, GTPOWERGOOD, GTREFCLKMONITOR, PCIERATEGEN3, PCIERATEIDLE, PCIERATEQPLLPD, PCIERATEQPLLRESET, PCIESYNCTXSYNCDONE +, PCIEUSERGEN3RDY, PCIEUSERPHYSTATUSRST, PCIEUSERRATESTART, PCSRSVDOUT, PHYSTATUS, PINRSRVDAS, RESETEXCEPTION, RXBUFSTATUS, RXBYTEISALIGNED, RXBYTEREALIGN, RXCDRLOCK, RXCDRPHDONE, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCHBONDO, RXCLKCORCNT, RXCOMINITDET, RXCOMMADET, RXCOMSASDET, RXCOMWAKEDET +, RXCTRL0, RXCTRL1, RXCTRL2, RXCTRL3, RXDATA, RXDATAEXTENDRSVD, RXDATAVALID, RXDLYSRESETDONE, RXELECIDLE, RXHEADER, RXHEADERVALID, RXMONITOROUT, RXOSINTDONE, RXOSINTSTARTED, RXOSINTSTROBEDONE, RXOSINTSTROBESTARTED, RXOUTCLK, RXOUTCLKFABRIC, RXOUTCLKPCS, RXPHALIGNDONE, RXPHALIGNERR +, RXPMARESETDONE, RXPRBSERR, RXPRBSLOCKED, RXPRGDIVRESETDONE, RXQPISENN, RXQPISENP, RXRATEDONE, RXRECCLKOUT, RXRESETDONE, RXSLIDERDY, RXSLIPDONE, RXSLIPOUTCLKRDY, RXSLIPPMARDY, RXSTARTOFSEQ, RXSTATUS, RXSYNCDONE, RXSYNCOUT, RXVALID, TXBUFSTATUS, TXCOMFINISH, TXDLYSRESETDONE +, TXOUTCLK, TXOUTCLKFABRIC, TXOUTCLKPCS, TXPHALIGNDONE, TXPHINITDONE, TXPMARESETDONE, TXPRGDIVRESETDONE, TXQPISENN, TXQPISENP, TXRATEDONE, TXRESETDONE, TXSYNCDONE, TXSYNCOUT, CFGRESET, CLKRSVD0, CLKRSVD1, CPLLLOCKDETCLK, CPLLLOCKEN, CPLLPD, CPLLREFCLKSEL, CPLLRESET +, DMONFIFORESET, DMONITORCLK, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, EVODDPHICALDONE, EVODDPHICALSTART, EVODDPHIDRDEN, EVODDPHIDWREN, EVODDPHIXRDEN, EVODDPHIXWREN, EYESCANMODE, EYESCANRESET, EYESCANTRIGGER, GTGREFCLK, GTHRXN, GTHRXP, GTNORTHREFCLK0, GTNORTHREFCLK1 +, GTREFCLK0, GTREFCLK1, GTRESETSEL, GTRSVD, GTRXRESET, GTSOUTHREFCLK0, GTSOUTHREFCLK1, GTTXRESET, LOOPBACK, LPBKRXTXSEREN, LPBKTXRXSEREN, PCIEEQRXEQADAPTDONE, PCIERSTIDLE, PCIERSTTXSYNCSTART, PCIEUSERRATEDONE, PCSRSVDIN, PCSRSVDIN2, PMARSVDIN, QPLL0CLK, QPLL0REFCLK, QPLL1CLK +, QPLL1REFCLK, RESETOVRD, RSTCLKENTX, RX8B10BEN, RXBUFRESET, RXCDRFREQRESET, RXCDRHOLD, RXCDROVRDEN, RXCDRRESET, RXCDRRESETRSV, RXCHBONDEN, RXCHBONDI, RXCHBONDLEVEL, RXCHBONDMASTER, RXCHBONDSLAVE, RXCOMMADETEN, RXDFEAGCCTRL, RXDFEAGCHOLD, RXDFEAGCOVRDEN, RXDFELFHOLD, RXDFELFOVRDEN +, RXDFELPMRESET, RXDFETAP10HOLD, RXDFETAP10OVRDEN, RXDFETAP11HOLD, RXDFETAP11OVRDEN, RXDFETAP12HOLD, RXDFETAP12OVRDEN, RXDFETAP13HOLD, RXDFETAP13OVRDEN, RXDFETAP14HOLD, RXDFETAP14OVRDEN, RXDFETAP15HOLD, RXDFETAP15OVRDEN, RXDFETAP2HOLD, RXDFETAP2OVRDEN, RXDFETAP3HOLD, RXDFETAP3OVRDEN, RXDFETAP4HOLD, RXDFETAP4OVRDEN, RXDFETAP5HOLD, RXDFETAP5OVRDEN +, RXDFETAP6HOLD, RXDFETAP6OVRDEN, RXDFETAP7HOLD, RXDFETAP7OVRDEN, RXDFETAP8HOLD, RXDFETAP8OVRDEN, RXDFETAP9HOLD, RXDFETAP9OVRDEN, RXDFEUTHOLD, RXDFEUTOVRDEN, RXDFEVPHOLD, RXDFEVPOVRDEN, RXDFEVSEN, RXDFEXYDEN, RXDLYBYPASS, RXDLYEN, RXDLYOVRDEN, RXDLYSRESET, RXELECIDLEMODE, RXGEARBOXSLIP, RXLATCLK +, RXLPMEN, RXLPMGCHOLD, RXLPMGCOVRDEN, RXLPMHFHOLD, RXLPMHFOVRDEN, RXLPMLFHOLD, RXLPMLFKLOVRDEN, RXLPMOSHOLD, RXLPMOSOVRDEN, RXMCOMMAALIGNEN, RXMONITORSEL, RXOOBRESET, RXOSCALRESET, RXOSHOLD, RXOSINTCFG, RXOSINTEN, RXOSINTHOLD, RXOSINTOVRDEN, RXOSINTSTROBE, RXOSINTTESTOVRDEN, RXOSOVRDEN +, RXOUTCLKSEL, RXPCOMMAALIGNEN, RXPCSRESET, RXPD, RXPHALIGN, RXPHALIGNEN, RXPHDLYPD, RXPHDLYRESET, RXPHOVRDEN, RXPLLCLKSEL, RXPMARESET, RXPOLARITY, RXPRBSCNTRESET, RXPRBSSEL, RXPROGDIVRESET, RXQPIEN, RXRATE, RXRATEMODE, RXSLIDE, RXSLIPOUTCLK, RXSLIPPMA +, RXSYNCALLIN, RXSYNCIN, RXSYNCMODE, RXSYSCLKSEL, RXUSERRDY, RXUSRCLK, RXUSRCLK2, SIGVALIDCLK, TSTIN, TX8B10BBYPASS, TX8B10BEN, TXBUFDIFFCTRL, TXCOMINIT, TXCOMSAS, TXCOMWAKE, TXCTRL0, TXCTRL1, TXCTRL2, TXDATA, TXDATAEXTENDRSVD, TXDEEMPH +, TXDETECTRX, TXDIFFCTRL, TXDIFFPD, TXDLYBYPASS, TXDLYEN, TXDLYHOLD, TXDLYOVRDEN, TXDLYSRESET, TXDLYUPDOWN, TXELECIDLE, TXHEADER, TXINHIBIT, TXLATCLK, TXMAINCURSOR, TXMARGIN, TXOUTCLKSEL, TXPCSRESET, TXPD, TXPDELECIDLEMODE, TXPHALIGN, TXPHALIGNEN +, TXPHDLYPD, TXPHDLYRESET, TXPHDLYTSTCLK, TXPHINIT, TXPHOVRDEN, TXPIPPMEN, TXPIPPMOVRDEN, TXPIPPMPD, TXPIPPMSEL, TXPIPPMSTEPSIZE, TXPISOPD, TXPLLCLKSEL, TXPMARESET, TXPOLARITY, TXPOSTCURSOR, TXPOSTCURSORINV, TXPRBSFORCEERR, TXPRBSSEL, TXPRECURSOR, TXPRECURSORINV, TXPROGDIVRESET +, TXQPIBIASEN, TXQPISTRONGPDOWN, TXQPIWEAKPUP, TXRATE, TXRATEMODE, TXSEQUENCE, TXSWING, TXSYNCALLIN, TXSYNCIN, TXSYNCMODE, TXSYSCLKSEL, TXUSERRDY, TXUSRCLK, TXUSRCLK2); parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; parameter [0:0] ACJTAG_MODE = 1'b0; parameter [0:0] ACJTAG_RESET = 1'b0; @@ -15723,7 +15878,10 @@ module GTHE3_CHANNEL (...); input TXUSRCLK2; endmodule -module GTHE3_COMMON (...); +module GTHE3_COMMON(DRPDO, DRPRDY, PMARSVDOUT0, PMARSVDOUT1, QPLL0FBCLKLOST, QPLL0LOCK, QPLL0OUTCLK, QPLL0OUTREFCLK, QPLL0REFCLKLOST, QPLL1FBCLKLOST, QPLL1LOCK, QPLL1OUTCLK, QPLL1OUTREFCLK, QPLL1REFCLKLOST, QPLLDMONITOR0, QPLLDMONITOR1, REFCLKOUTMONITOR0, REFCLKOUTMONITOR1, RXRECCLK0_SEL, RXRECCLK1_SEL, BGBYPASSB +, BGMONITORENB, BGPDB, BGRCALOVRD, BGRCALOVRDENB, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, GTGREFCLK0, GTGREFCLK1, GTNORTHREFCLK00, GTNORTHREFCLK01, GTNORTHREFCLK10, GTNORTHREFCLK11, GTREFCLK00, GTREFCLK01, GTREFCLK10, GTREFCLK11, GTSOUTHREFCLK00, GTSOUTHREFCLK01 +, GTSOUTHREFCLK10, GTSOUTHREFCLK11, PMARSVD0, PMARSVD1, QPLL0CLKRSVD0, QPLL0CLKRSVD1, QPLL0LOCKDETCLK, QPLL0LOCKEN, QPLL0PD, QPLL0REFCLKSEL, QPLL0RESET, QPLL1CLKRSVD0, QPLL1CLKRSVD1, QPLL1LOCKDETCLK, QPLL1LOCKEN, QPLL1PD, QPLL1REFCLKSEL, QPLL1RESET, QPLLRSVD1, QPLLRSVD2, QPLLRSVD3 +, QPLLRSVD4, RCALENB); parameter [15:0] BIAS_CFG0 = 16'h0000; parameter [15:0] BIAS_CFG1 = 16'h0000; parameter [15:0] BIAS_CFG2 = 16'h0000; @@ -15865,7 +16023,22 @@ module GTHE3_COMMON (...); input RCALENB; endmodule -module GTYE3_CHANNEL (...); +module GTYE3_CHANNEL(BUFGTCE, BUFGTCEMASK, BUFGTDIV, BUFGTRESET, BUFGTRSTMASK, CPLLFBCLKLOST, CPLLLOCK, CPLLREFCLKLOST, DMONITOROUT, DRPDO, DRPRDY, EYESCANDATAERROR, GTPOWERGOOD, GTREFCLKMONITOR, GTYTXN, GTYTXP, PCIERATEGEN3, PCIERATEIDLE, PCIERATEQPLLPD, PCIERATEQPLLRESET, PCIESYNCTXSYNCDONE +, PCIEUSERGEN3RDY, PCIEUSERPHYSTATUSRST, PCIEUSERRATESTART, PCSRSVDOUT, PHYSTATUS, PINRSRVDAS, RESETEXCEPTION, RXBUFSTATUS, RXBYTEISALIGNED, RXBYTEREALIGN, RXCDRLOCK, RXCDRPHDONE, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCHBONDO, RXCKCALDONE, RXCLKCORCNT, RXCOMINITDET, RXCOMMADET, RXCOMSASDET +, RXCOMWAKEDET, RXCTRL0, RXCTRL1, RXCTRL2, RXCTRL3, RXDATA, RXDATAEXTENDRSVD, RXDATAVALID, RXDLYSRESETDONE, RXELECIDLE, RXHEADER, RXHEADERVALID, RXMONITOROUT, RXOSINTDONE, RXOSINTSTARTED, RXOSINTSTROBEDONE, RXOSINTSTROBESTARTED, RXOUTCLK, RXOUTCLKFABRIC, RXOUTCLKPCS, RXPHALIGNDONE +, RXPHALIGNERR, RXPMARESETDONE, RXPRBSERR, RXPRBSLOCKED, RXPRGDIVRESETDONE, RXRATEDONE, RXRECCLKOUT, RXRESETDONE, RXSLIDERDY, RXSLIPDONE, RXSLIPOUTCLKRDY, RXSLIPPMARDY, RXSTARTOFSEQ, RXSTATUS, RXSYNCDONE, RXSYNCOUT, RXVALID, TXBUFSTATUS, TXCOMFINISH, TXDCCDONE, TXDLYSRESETDONE +, TXOUTCLK, TXOUTCLKFABRIC, TXOUTCLKPCS, TXPHALIGNDONE, TXPHINITDONE, TXPMARESETDONE, TXPRGDIVRESETDONE, TXRATEDONE, TXRESETDONE, TXSYNCDONE, TXSYNCOUT, CDRSTEPDIR, CDRSTEPSQ, CDRSTEPSX, CFGRESET, CLKRSVD0, CLKRSVD1, CPLLLOCKDETCLK, CPLLLOCKEN, CPLLPD, CPLLREFCLKSEL +, CPLLRESET, DMONFIFORESET, DMONITORCLK, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, ELPCALDVORWREN, ELPCALPAORWREN, EVODDPHICALDONE, EVODDPHICALSTART, EVODDPHIDRDEN, EVODDPHIDWREN, EVODDPHIXRDEN, EVODDPHIXWREN, EYESCANMODE, EYESCANRESET, EYESCANTRIGGER, GTGREFCLK, GTNORTHREFCLK0 +, GTNORTHREFCLK1, GTREFCLK0, GTREFCLK1, GTRESETSEL, GTRSVD, GTRXRESET, GTSOUTHREFCLK0, GTSOUTHREFCLK1, GTTXRESET, GTYRXN, GTYRXP, LOOPBACK, LOOPRSVD, LPBKRXTXSEREN, LPBKTXRXSEREN, PCIEEQRXEQADAPTDONE, PCIERSTIDLE, PCIERSTTXSYNCSTART, PCIEUSERRATEDONE, PCSRSVDIN, PCSRSVDIN2 +, PMARSVDIN, QPLL0CLK, QPLL0REFCLK, QPLL1CLK, QPLL1REFCLK, RESETOVRD, RSTCLKENTX, RX8B10BEN, RXBUFRESET, RXCDRFREQRESET, RXCDRHOLD, RXCDROVRDEN, RXCDRRESET, RXCDRRESETRSV, RXCHBONDEN, RXCHBONDI, RXCHBONDLEVEL, RXCHBONDMASTER, RXCHBONDSLAVE, RXCKCALRESET, RXCOMMADETEN +, RXDCCFORCESTART, RXDFEAGCHOLD, RXDFEAGCOVRDEN, RXDFELFHOLD, RXDFELFOVRDEN, RXDFELPMRESET, RXDFETAP10HOLD, RXDFETAP10OVRDEN, RXDFETAP11HOLD, RXDFETAP11OVRDEN, RXDFETAP12HOLD, RXDFETAP12OVRDEN, RXDFETAP13HOLD, RXDFETAP13OVRDEN, RXDFETAP14HOLD, RXDFETAP14OVRDEN, RXDFETAP15HOLD, RXDFETAP15OVRDEN, RXDFETAP2HOLD, RXDFETAP2OVRDEN, RXDFETAP3HOLD +, RXDFETAP3OVRDEN, RXDFETAP4HOLD, RXDFETAP4OVRDEN, RXDFETAP5HOLD, RXDFETAP5OVRDEN, RXDFETAP6HOLD, RXDFETAP6OVRDEN, RXDFETAP7HOLD, RXDFETAP7OVRDEN, RXDFETAP8HOLD, RXDFETAP8OVRDEN, RXDFETAP9HOLD, RXDFETAP9OVRDEN, RXDFEUTHOLD, RXDFEUTOVRDEN, RXDFEVPHOLD, RXDFEVPOVRDEN, RXDFEVSEN, RXDFEXYDEN, RXDLYBYPASS, RXDLYEN +, RXDLYOVRDEN, RXDLYSRESET, RXELECIDLEMODE, RXGEARBOXSLIP, RXLATCLK, RXLPMEN, RXLPMGCHOLD, RXLPMGCOVRDEN, RXLPMHFHOLD, RXLPMHFOVRDEN, RXLPMLFHOLD, RXLPMLFKLOVRDEN, RXLPMOSHOLD, RXLPMOSOVRDEN, RXMCOMMAALIGNEN, RXMONITORSEL, RXOOBRESET, RXOSCALRESET, RXOSHOLD, RXOSINTCFG, RXOSINTEN +, RXOSINTHOLD, RXOSINTOVRDEN, RXOSINTSTROBE, RXOSINTTESTOVRDEN, RXOSOVRDEN, RXOUTCLKSEL, RXPCOMMAALIGNEN, RXPCSRESET, RXPD, RXPHALIGN, RXPHALIGNEN, RXPHDLYPD, RXPHDLYRESET, RXPHOVRDEN, RXPLLCLKSEL, RXPMARESET, RXPOLARITY, RXPRBSCNTRESET, RXPRBSSEL, RXPROGDIVRESET, RXRATE +, RXRATEMODE, RXSLIDE, RXSLIPOUTCLK, RXSLIPPMA, RXSYNCALLIN, RXSYNCIN, RXSYNCMODE, RXSYSCLKSEL, RXUSERRDY, RXUSRCLK, RXUSRCLK2, SIGVALIDCLK, TSTIN, TX8B10BBYPASS, TX8B10BEN, TXBUFDIFFCTRL, TXCOMINIT, TXCOMSAS, TXCOMWAKE, TXCTRL0, TXCTRL1 +, TXCTRL2, TXDATA, TXDATAEXTENDRSVD, TXDCCFORCESTART, TXDCCRESET, TXDEEMPH, TXDETECTRX, TXDIFFCTRL, TXDIFFPD, TXDLYBYPASS, TXDLYEN, TXDLYHOLD, TXDLYOVRDEN, TXDLYSRESET, TXDLYUPDOWN, TXELECIDLE, TXELFORCESTART, TXHEADER, TXINHIBIT, TXLATCLK, TXMAINCURSOR +, TXMARGIN, TXOUTCLKSEL, TXPCSRESET, TXPD, TXPDELECIDLEMODE, TXPHALIGN, TXPHALIGNEN, TXPHDLYPD, TXPHDLYRESET, TXPHDLYTSTCLK, TXPHINIT, TXPHOVRDEN, TXPIPPMEN, TXPIPPMOVRDEN, TXPIPPMPD, TXPIPPMSEL, TXPIPPMSTEPSIZE, TXPISOPD, TXPLLCLKSEL, TXPMARESET, TXPOLARITY +, TXPOSTCURSOR, TXPRBSFORCEERR, TXPRBSSEL, TXPRECURSOR, TXPROGDIVRESET, TXRATE, TXRATEMODE, TXSEQUENCE, TXSWING, TXSYNCALLIN, TXSYNCIN, TXSYNCMODE, TXSYSCLKSEL, TXUSERRDY, TXUSRCLK, TXUSRCLK2); parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; parameter [0:0] ACJTAG_MODE = 1'b0; parameter [0:0] ACJTAG_RESET = 1'b0; @@ -16666,7 +16839,10 @@ module GTYE3_CHANNEL (...); input TXUSRCLK2; endmodule -module GTYE3_COMMON (...); +module GTYE3_COMMON(DRPDO, DRPRDY, PMARSVDOUT0, PMARSVDOUT1, QPLL0FBCLKLOST, QPLL0LOCK, QPLL0OUTCLK, QPLL0OUTREFCLK, QPLL0REFCLKLOST, QPLL1FBCLKLOST, QPLL1LOCK, QPLL1OUTCLK, QPLL1OUTREFCLK, QPLL1REFCLKLOST, QPLLDMONITOR0, QPLLDMONITOR1, REFCLKOUTMONITOR0, REFCLKOUTMONITOR1, RXRECCLK0_SEL, RXRECCLK1_SEL, SDM0FINALOUT +, SDM0TESTDATA, SDM1FINALOUT, SDM1TESTDATA, BGBYPASSB, BGMONITORENB, BGPDB, BGRCALOVRD, BGRCALOVRDENB, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, GTGREFCLK0, GTGREFCLK1, GTNORTHREFCLK00, GTNORTHREFCLK01, GTNORTHREFCLK10, GTNORTHREFCLK11, GTREFCLK00, GTREFCLK01 +, GTREFCLK10, GTREFCLK11, GTSOUTHREFCLK00, GTSOUTHREFCLK01, GTSOUTHREFCLK10, GTSOUTHREFCLK11, PMARSVD0, PMARSVD1, QPLL0CLKRSVD0, QPLL0LOCKDETCLK, QPLL0LOCKEN, QPLL0PD, QPLL0REFCLKSEL, QPLL0RESET, QPLL1CLKRSVD0, QPLL1LOCKDETCLK, QPLL1LOCKEN, QPLL1PD, QPLL1REFCLKSEL, QPLL1RESET, QPLLRSVD1 +, QPLLRSVD2, QPLLRSVD3, QPLLRSVD4, RCALENB, SDM0DATA, SDM0RESET, SDM0WIDTH, SDM1DATA, SDM1RESET, SDM1WIDTH); parameter [15:0] A_SDM1DATA1_0 = 16'b0000000000000000; parameter [8:0] A_SDM1DATA1_1 = 9'b000000000; parameter [15:0] BIAS_CFG0 = 16'h0000; @@ -16814,7 +16990,7 @@ module GTYE3_COMMON (...); input [1:0] SDM1WIDTH; endmodule -module IBUFDS_GTE3 (...); +module IBUFDS_GTE3(O, ODIV2, CEB, I, IB); parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00; parameter [1:0] REFCLK_ICNTL_RX = 2'b00; @@ -16827,7 +17003,7 @@ module IBUFDS_GTE3 (...); input IB; endmodule -module OBUFDS_GTE3 (...); +module OBUFDS_GTE3(O, OB, CEB, I); parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; (* iopad_external_pin *) @@ -16838,7 +17014,7 @@ module OBUFDS_GTE3 (...); input I; endmodule -module OBUFDS_GTE3_ADV (...); +module OBUFDS_GTE3_ADV(O, OB, CEB, I, RXRECCLK_SEL); parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; (* iopad_external_pin *) @@ -16850,7 +17026,23 @@ module OBUFDS_GTE3_ADV (...); input [1:0] RXRECCLK_SEL; endmodule -module GTHE4_CHANNEL (...); +module GTHE4_CHANNEL(BUFGTCE, BUFGTCEMASK, BUFGTDIV, BUFGTRESET, BUFGTRSTMASK, CPLLFBCLKLOST, CPLLLOCK, CPLLREFCLKLOST, DMONITOROUT, DMONITOROUTCLK, DRPDO, DRPRDY, EYESCANDATAERROR, GTHTXN, GTHTXP, GTPOWERGOOD, GTREFCLKMONITOR, PCIERATEGEN3, PCIERATEIDLE, PCIERATEQPLLPD, PCIERATEQPLLRESET +, PCIESYNCTXSYNCDONE, PCIEUSERGEN3RDY, PCIEUSERPHYSTATUSRST, PCIEUSERRATESTART, PCSRSVDOUT, PHYSTATUS, PINRSRVDAS, POWERPRESENT, RESETEXCEPTION, RXBUFSTATUS, RXBYTEISALIGNED, RXBYTEREALIGN, RXCDRLOCK, RXCDRPHDONE, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCHBONDO, RXCKCALDONE, RXCLKCORCNT, RXCOMINITDET +, RXCOMMADET, RXCOMSASDET, RXCOMWAKEDET, RXCTRL0, RXCTRL1, RXCTRL2, RXCTRL3, RXDATA, RXDATAEXTENDRSVD, RXDATAVALID, RXDLYSRESETDONE, RXELECIDLE, RXHEADER, RXHEADERVALID, RXLFPSTRESETDET, RXLFPSU2LPEXITDET, RXLFPSU3WAKEDET, RXMONITOROUT, RXOSINTDONE, RXOSINTSTARTED, RXOSINTSTROBEDONE +, RXOSINTSTROBESTARTED, RXOUTCLK, RXOUTCLKFABRIC, RXOUTCLKPCS, RXPHALIGNDONE, RXPHALIGNERR, RXPMARESETDONE, RXPRBSERR, RXPRBSLOCKED, RXPRGDIVRESETDONE, RXQPISENN, RXQPISENP, RXRATEDONE, RXRECCLKOUT, RXRESETDONE, RXSLIDERDY, RXSLIPDONE, RXSLIPOUTCLKRDY, RXSLIPPMARDY, RXSTARTOFSEQ, RXSTATUS +, RXSYNCDONE, RXSYNCOUT, RXVALID, TXBUFSTATUS, TXCOMFINISH, TXDCCDONE, TXDLYSRESETDONE, TXOUTCLK, TXOUTCLKFABRIC, TXOUTCLKPCS, TXPHALIGNDONE, TXPHINITDONE, TXPMARESETDONE, TXPRGDIVRESETDONE, TXQPISENN, TXQPISENP, TXRATEDONE, TXRESETDONE, TXSYNCDONE, TXSYNCOUT, CDRSTEPDIR +, CDRSTEPSQ, CDRSTEPSX, CFGRESET, CLKRSVD0, CLKRSVD1, CPLLFREQLOCK, CPLLLOCKDETCLK, CPLLLOCKEN, CPLLPD, CPLLREFCLKSEL, CPLLRESET, DMONFIFORESET, DMONITORCLK, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPRST, DRPWE, EYESCANRESET, EYESCANTRIGGER +, FREQOS, GTGREFCLK, GTHRXN, GTHRXP, GTNORTHREFCLK0, GTNORTHREFCLK1, GTREFCLK0, GTREFCLK1, GTRSVD, GTRXRESET, GTRXRESETSEL, GTSOUTHREFCLK0, GTSOUTHREFCLK1, GTTXRESET, GTTXRESETSEL, INCPCTRL, LOOPBACK, PCIEEQRXEQADAPTDONE, PCIERSTIDLE, PCIERSTTXSYNCSTART, PCIEUSERRATEDONE +, PCSRSVDIN, QPLL0CLK, QPLL0FREQLOCK, QPLL0REFCLK, QPLL1CLK, QPLL1FREQLOCK, QPLL1REFCLK, RESETOVRD, RX8B10BEN, RXAFECFOKEN, RXBUFRESET, RXCDRFREQRESET, RXCDRHOLD, RXCDROVRDEN, RXCDRRESET, RXCHBONDEN, RXCHBONDI, RXCHBONDLEVEL, RXCHBONDMASTER, RXCHBONDSLAVE, RXCKCALRESET +, RXCKCALSTART, RXCOMMADETEN, RXDFEAGCCTRL, RXDFEAGCHOLD, RXDFEAGCOVRDEN, RXDFECFOKFCNUM, RXDFECFOKFEN, RXDFECFOKFPULSE, RXDFECFOKHOLD, RXDFECFOKOVREN, RXDFEKHHOLD, RXDFEKHOVRDEN, RXDFELFHOLD, RXDFELFOVRDEN, RXDFELPMRESET, RXDFETAP10HOLD, RXDFETAP10OVRDEN, RXDFETAP11HOLD, RXDFETAP11OVRDEN, RXDFETAP12HOLD, RXDFETAP12OVRDEN +, RXDFETAP13HOLD, RXDFETAP13OVRDEN, RXDFETAP14HOLD, RXDFETAP14OVRDEN, RXDFETAP15HOLD, RXDFETAP15OVRDEN, RXDFETAP2HOLD, RXDFETAP2OVRDEN, RXDFETAP3HOLD, RXDFETAP3OVRDEN, RXDFETAP4HOLD, RXDFETAP4OVRDEN, RXDFETAP5HOLD, RXDFETAP5OVRDEN, RXDFETAP6HOLD, RXDFETAP6OVRDEN, RXDFETAP7HOLD, RXDFETAP7OVRDEN, RXDFETAP8HOLD, RXDFETAP8OVRDEN, RXDFETAP9HOLD +, RXDFETAP9OVRDEN, RXDFEUTHOLD, RXDFEUTOVRDEN, RXDFEVPHOLD, RXDFEVPOVRDEN, RXDFEXYDEN, RXDLYBYPASS, RXDLYEN, RXDLYOVRDEN, RXDLYSRESET, RXELECIDLEMODE, RXEQTRAINING, RXGEARBOXSLIP, RXLATCLK, RXLPMEN, RXLPMGCHOLD, RXLPMGCOVRDEN, RXLPMHFHOLD, RXLPMHFOVRDEN, RXLPMLFHOLD, RXLPMLFKLOVRDEN +, RXLPMOSHOLD, RXLPMOSOVRDEN, RXMCOMMAALIGNEN, RXMONITORSEL, RXOOBRESET, RXOSCALRESET, RXOSHOLD, RXOSOVRDEN, RXOUTCLKSEL, RXPCOMMAALIGNEN, RXPCSRESET, RXPD, RXPHALIGN, RXPHALIGNEN, RXPHDLYPD, RXPHDLYRESET, RXPHOVRDEN, RXPLLCLKSEL, RXPMARESET, RXPOLARITY, RXPRBSCNTRESET +, RXPRBSSEL, RXPROGDIVRESET, RXQPIEN, RXRATE, RXRATEMODE, RXSLIDE, RXSLIPOUTCLK, RXSLIPPMA, RXSYNCALLIN, RXSYNCIN, RXSYNCMODE, RXSYSCLKSEL, RXTERMINATION, RXUSERRDY, RXUSRCLK, RXUSRCLK2, SIGVALIDCLK, TSTIN, TX8B10BBYPASS, TX8B10BEN, TXCOMINIT +, TXCOMSAS, TXCOMWAKE, TXCTRL0, TXCTRL1, TXCTRL2, TXDATA, TXDATAEXTENDRSVD, TXDCCFORCESTART, TXDCCRESET, TXDEEMPH, TXDETECTRX, TXDIFFCTRL, TXDLYBYPASS, TXDLYEN, TXDLYHOLD, TXDLYOVRDEN, TXDLYSRESET, TXDLYUPDOWN, TXELECIDLE, TXHEADER, TXINHIBIT +, TXLATCLK, TXLFPSTRESET, TXLFPSU2LPEXIT, TXLFPSU3WAKE, TXMAINCURSOR, TXMARGIN, TXMUXDCDEXHOLD, TXMUXDCDORWREN, TXONESZEROS, TXOUTCLKSEL, TXPCSRESET, TXPD, TXPDELECIDLEMODE, TXPHALIGN, TXPHALIGNEN, TXPHDLYPD, TXPHDLYRESET, TXPHDLYTSTCLK, TXPHINIT, TXPHOVRDEN, TXPIPPMEN +, TXPIPPMOVRDEN, TXPIPPMPD, TXPIPPMSEL, TXPIPPMSTEPSIZE, TXPISOPD, TXPLLCLKSEL, TXPMARESET, TXPOLARITY, TXPOSTCURSOR, TXPRBSFORCEERR, TXPRBSSEL, TXPRECURSOR, TXPROGDIVRESET, TXQPIBIASEN, TXQPIWEAKPUP, TXRATE, TXRATEMODE, TXSEQUENCE, TXSWING, TXSYNCALLIN, TXSYNCIN +, TXSYNCMODE, TXSYSCLKSEL, TXUSERRDY, TXUSRCLK, TXUSRCLK2); parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; parameter [0:0] ACJTAG_MODE = 1'b0; parameter [0:0] ACJTAG_RESET = 1'b0; @@ -17698,7 +17890,11 @@ module GTHE4_CHANNEL (...); input TXUSRCLK2; endmodule -module GTHE4_COMMON (...); +module GTHE4_COMMON(DRPDO, DRPRDY, PMARSVDOUT0, PMARSVDOUT1, QPLL0FBCLKLOST, QPLL0LOCK, QPLL0OUTCLK, QPLL0OUTREFCLK, QPLL0REFCLKLOST, QPLL1FBCLKLOST, QPLL1LOCK, QPLL1OUTCLK, QPLL1OUTREFCLK, QPLL1REFCLKLOST, QPLLDMONITOR0, QPLLDMONITOR1, REFCLKOUTMONITOR0, REFCLKOUTMONITOR1, RXRECCLK0SEL, RXRECCLK1SEL, SDM0FINALOUT +, SDM0TESTDATA, SDM1FINALOUT, SDM1TESTDATA, TCONGPO, TCONRSVDOUT0, BGBYPASSB, BGMONITORENB, BGPDB, BGRCALOVRD, BGRCALOVRDENB, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, GTGREFCLK0, GTGREFCLK1, GTNORTHREFCLK00, GTNORTHREFCLK01, GTNORTHREFCLK10, GTNORTHREFCLK11 +, GTREFCLK00, GTREFCLK01, GTREFCLK10, GTREFCLK11, GTSOUTHREFCLK00, GTSOUTHREFCLK01, GTSOUTHREFCLK10, GTSOUTHREFCLK11, PCIERATEQPLL0, PCIERATEQPLL1, PMARSVD0, PMARSVD1, QPLL0CLKRSVD0, QPLL0CLKRSVD1, QPLL0FBDIV, QPLL0LOCKDETCLK, QPLL0LOCKEN, QPLL0PD, QPLL0REFCLKSEL, QPLL0RESET, QPLL1CLKRSVD0 +, QPLL1CLKRSVD1, QPLL1FBDIV, QPLL1LOCKDETCLK, QPLL1LOCKEN, QPLL1PD, QPLL1REFCLKSEL, QPLL1RESET, QPLLRSVD1, QPLLRSVD2, QPLLRSVD3, QPLLRSVD4, RCALENB, SDM0DATA, SDM0RESET, SDM0TOGGLE, SDM0WIDTH, SDM1DATA, SDM1RESET, SDM1TOGGLE, SDM1WIDTH, TCONGPI +, TCONPOWERUP, TCONRESET, TCONRSVDIN1); parameter [0:0] AEN_QPLL0_FBDIV = 1'b1; parameter [0:0] AEN_QPLL1_FBDIV = 1'b1; parameter [0:0] AEN_SDM0TOGGLE = 1'b0; @@ -17870,7 +18066,22 @@ module GTHE4_COMMON (...); input [1:0] TCONRSVDIN1; endmodule -module GTYE4_CHANNEL (...); +module GTYE4_CHANNEL(BUFGTCE, BUFGTCEMASK, BUFGTDIV, BUFGTRESET, BUFGTRSTMASK, CPLLFBCLKLOST, CPLLLOCK, CPLLREFCLKLOST, DMONITOROUT, DMONITOROUTCLK, DRPDO, DRPRDY, EYESCANDATAERROR, GTPOWERGOOD, GTREFCLKMONITOR, GTYTXN, GTYTXP, PCIERATEGEN3, PCIERATEIDLE, PCIERATEQPLLPD, PCIERATEQPLLRESET +, PCIESYNCTXSYNCDONE, PCIEUSERGEN3RDY, PCIEUSERPHYSTATUSRST, PCIEUSERRATESTART, PCSRSVDOUT, PHYSTATUS, PINRSRVDAS, POWERPRESENT, RESETEXCEPTION, RXBUFSTATUS, RXBYTEISALIGNED, RXBYTEREALIGN, RXCDRLOCK, RXCDRPHDONE, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCHBONDO, RXCKCALDONE, RXCLKCORCNT, RXCOMINITDET +, RXCOMMADET, RXCOMSASDET, RXCOMWAKEDET, RXCTRL0, RXCTRL1, RXCTRL2, RXCTRL3, RXDATA, RXDATAEXTENDRSVD, RXDATAVALID, RXDLYSRESETDONE, RXELECIDLE, RXHEADER, RXHEADERVALID, RXLFPSTRESETDET, RXLFPSU2LPEXITDET, RXLFPSU3WAKEDET, RXMONITOROUT, RXOSINTDONE, RXOSINTSTARTED, RXOSINTSTROBEDONE +, RXOSINTSTROBESTARTED, RXOUTCLK, RXOUTCLKFABRIC, RXOUTCLKPCS, RXPHALIGNDONE, RXPHALIGNERR, RXPMARESETDONE, RXPRBSERR, RXPRBSLOCKED, RXPRGDIVRESETDONE, RXRATEDONE, RXRECCLKOUT, RXRESETDONE, RXSLIDERDY, RXSLIPDONE, RXSLIPOUTCLKRDY, RXSLIPPMARDY, RXSTARTOFSEQ, RXSTATUS, RXSYNCDONE, RXSYNCOUT +, RXVALID, TXBUFSTATUS, TXCOMFINISH, TXDCCDONE, TXDLYSRESETDONE, TXOUTCLK, TXOUTCLKFABRIC, TXOUTCLKPCS, TXPHALIGNDONE, TXPHINITDONE, TXPMARESETDONE, TXPRGDIVRESETDONE, TXRATEDONE, TXRESETDONE, TXSYNCDONE, TXSYNCOUT, CDRSTEPDIR, CDRSTEPSQ, CDRSTEPSX, CFGRESET, CLKRSVD0 +, CLKRSVD1, CPLLFREQLOCK, CPLLLOCKDETCLK, CPLLLOCKEN, CPLLPD, CPLLREFCLKSEL, CPLLRESET, DMONFIFORESET, DMONITORCLK, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPRST, DRPWE, EYESCANRESET, EYESCANTRIGGER, FREQOS, GTGREFCLK, GTNORTHREFCLK0, GTNORTHREFCLK1 +, GTREFCLK0, GTREFCLK1, GTRSVD, GTRXRESET, GTRXRESETSEL, GTSOUTHREFCLK0, GTSOUTHREFCLK1, GTTXRESET, GTTXRESETSEL, GTYRXN, GTYRXP, INCPCTRL, LOOPBACK, PCIEEQRXEQADAPTDONE, PCIERSTIDLE, PCIERSTTXSYNCSTART, PCIEUSERRATEDONE, PCSRSVDIN, QPLL0CLK, QPLL0FREQLOCK, QPLL0REFCLK +, QPLL1CLK, QPLL1FREQLOCK, QPLL1REFCLK, RESETOVRD, RX8B10BEN, RXAFECFOKEN, RXBUFRESET, RXCDRFREQRESET, RXCDRHOLD, RXCDROVRDEN, RXCDRRESET, RXCHBONDEN, RXCHBONDI, RXCHBONDLEVEL, RXCHBONDMASTER, RXCHBONDSLAVE, RXCKCALRESET, RXCKCALSTART, RXCOMMADETEN, RXDFEAGCHOLD, RXDFEAGCOVRDEN +, RXDFECFOKFCNUM, RXDFECFOKFEN, RXDFECFOKFPULSE, RXDFECFOKHOLD, RXDFECFOKOVREN, RXDFEKHHOLD, RXDFEKHOVRDEN, RXDFELFHOLD, RXDFELFOVRDEN, RXDFELPMRESET, RXDFETAP10HOLD, RXDFETAP10OVRDEN, RXDFETAP11HOLD, RXDFETAP11OVRDEN, RXDFETAP12HOLD, RXDFETAP12OVRDEN, RXDFETAP13HOLD, RXDFETAP13OVRDEN, RXDFETAP14HOLD, RXDFETAP14OVRDEN, RXDFETAP15HOLD +, RXDFETAP15OVRDEN, RXDFETAP2HOLD, RXDFETAP2OVRDEN, RXDFETAP3HOLD, RXDFETAP3OVRDEN, RXDFETAP4HOLD, RXDFETAP4OVRDEN, RXDFETAP5HOLD, RXDFETAP5OVRDEN, RXDFETAP6HOLD, RXDFETAP6OVRDEN, RXDFETAP7HOLD, RXDFETAP7OVRDEN, RXDFETAP8HOLD, RXDFETAP8OVRDEN, RXDFETAP9HOLD, RXDFETAP9OVRDEN, RXDFEUTHOLD, RXDFEUTOVRDEN, RXDFEVPHOLD, RXDFEVPOVRDEN +, RXDFEXYDEN, RXDLYBYPASS, RXDLYEN, RXDLYOVRDEN, RXDLYSRESET, RXELECIDLEMODE, RXEQTRAINING, RXGEARBOXSLIP, RXLATCLK, RXLPMEN, RXLPMGCHOLD, RXLPMGCOVRDEN, RXLPMHFHOLD, RXLPMHFOVRDEN, RXLPMLFHOLD, RXLPMLFKLOVRDEN, RXLPMOSHOLD, RXLPMOSOVRDEN, RXMCOMMAALIGNEN, RXMONITORSEL, RXOOBRESET +, RXOSCALRESET, RXOSHOLD, RXOSOVRDEN, RXOUTCLKSEL, RXPCOMMAALIGNEN, RXPCSRESET, RXPD, RXPHALIGN, RXPHALIGNEN, RXPHDLYPD, RXPHDLYRESET, RXPLLCLKSEL, RXPMARESET, RXPOLARITY, RXPRBSCNTRESET, RXPRBSSEL, RXPROGDIVRESET, RXRATE, RXRATEMODE, RXSLIDE, RXSLIPOUTCLK +, RXSLIPPMA, RXSYNCALLIN, RXSYNCIN, RXSYNCMODE, RXSYSCLKSEL, RXTERMINATION, RXUSERRDY, RXUSRCLK, RXUSRCLK2, SIGVALIDCLK, TSTIN, TX8B10BBYPASS, TX8B10BEN, TXCOMINIT, TXCOMSAS, TXCOMWAKE, TXCTRL0, TXCTRL1, TXCTRL2, TXDATA, TXDATAEXTENDRSVD +, TXDCCFORCESTART, TXDCCRESET, TXDEEMPH, TXDETECTRX, TXDIFFCTRL, TXDLYBYPASS, TXDLYEN, TXDLYHOLD, TXDLYOVRDEN, TXDLYSRESET, TXDLYUPDOWN, TXELECIDLE, TXHEADER, TXINHIBIT, TXLATCLK, TXLFPSTRESET, TXLFPSU2LPEXIT, TXLFPSU3WAKE, TXMAINCURSOR, TXMARGIN, TXMUXDCDEXHOLD +, TXMUXDCDORWREN, TXONESZEROS, TXOUTCLKSEL, TXPCSRESET, TXPD, TXPDELECIDLEMODE, TXPHALIGN, TXPHALIGNEN, TXPHDLYPD, TXPHDLYRESET, TXPHDLYTSTCLK, TXPHINIT, TXPHOVRDEN, TXPIPPMEN, TXPIPPMOVRDEN, TXPIPPMPD, TXPIPPMSEL, TXPIPPMSTEPSIZE, TXPISOPD, TXPLLCLKSEL, TXPMARESET +, TXPOLARITY, TXPOSTCURSOR, TXPRBSFORCEERR, TXPRBSSEL, TXPRECURSOR, TXPROGDIVRESET, TXRATE, TXRATEMODE, TXSEQUENCE, TXSWING, TXSYNCALLIN, TXSYNCIN, TXSYNCMODE, TXSYSCLKSEL, TXUSERRDY, TXUSRCLK, TXUSRCLK2); parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; parameter [0:0] ACJTAG_MODE = 1'b0; parameter [0:0] ACJTAG_RESET = 1'b0; @@ -18696,7 +18907,11 @@ module GTYE4_CHANNEL (...); input TXUSRCLK2; endmodule -module GTYE4_COMMON (...); +module GTYE4_COMMON(DRPDO, DRPRDY, PMARSVDOUT0, PMARSVDOUT1, QPLL0FBCLKLOST, QPLL0LOCK, QPLL0OUTCLK, QPLL0OUTREFCLK, QPLL0REFCLKLOST, QPLL1FBCLKLOST, QPLL1LOCK, QPLL1OUTCLK, QPLL1OUTREFCLK, QPLL1REFCLKLOST, QPLLDMONITOR0, QPLLDMONITOR1, REFCLKOUTMONITOR0, REFCLKOUTMONITOR1, RXRECCLK0SEL, RXRECCLK1SEL, SDM0FINALOUT +, SDM0TESTDATA, SDM1FINALOUT, SDM1TESTDATA, UBDADDR, UBDEN, UBDI, UBDWE, UBMDMTDO, UBRSVDOUT, UBTXUART, BGBYPASSB, BGMONITORENB, BGPDB, BGRCALOVRD, BGRCALOVRDENB, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, GTGREFCLK0 +, GTGREFCLK1, GTNORTHREFCLK00, GTNORTHREFCLK01, GTNORTHREFCLK10, GTNORTHREFCLK11, GTREFCLK00, GTREFCLK01, GTREFCLK10, GTREFCLK11, GTSOUTHREFCLK00, GTSOUTHREFCLK01, GTSOUTHREFCLK10, GTSOUTHREFCLK11, PCIERATEQPLL0, PCIERATEQPLL1, PMARSVD0, PMARSVD1, QPLL0CLKRSVD0, QPLL0CLKRSVD1, QPLL0FBDIV, QPLL0LOCKDETCLK +, QPLL0LOCKEN, QPLL0PD, QPLL0REFCLKSEL, QPLL0RESET, QPLL1CLKRSVD0, QPLL1CLKRSVD1, QPLL1FBDIV, QPLL1LOCKDETCLK, QPLL1LOCKEN, QPLL1PD, QPLL1REFCLKSEL, QPLL1RESET, QPLLRSVD1, QPLLRSVD2, QPLLRSVD3, QPLLRSVD4, RCALENB, SDM0DATA, SDM0RESET, SDM0TOGGLE, SDM0WIDTH +, SDM1DATA, SDM1RESET, SDM1TOGGLE, SDM1WIDTH, UBCFGSTREAMEN, UBDO, UBDRDY, UBENABLE, UBGPI, UBINTR, UBIOLMBRST, UBMBRST, UBMDMCAPTURE, UBMDMDBGRST, UBMDMDBGUPDATE, UBMDMREGEN, UBMDMSHIFT, UBMDMSYSRST, UBMDMTCK, UBMDMTDI); parameter [0:0] AEN_QPLL0_FBDIV = 1'b1; parameter [0:0] AEN_QPLL1_FBDIV = 1'b1; parameter [0:0] AEN_SDM0TOGGLE = 1'b0; @@ -18892,7 +19107,7 @@ module GTYE4_COMMON (...); input UBMDMTDI; endmodule -module IBUFDS_GTE4 (...); +module IBUFDS_GTE4(O, ODIV2, CEB, I, IB); parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00; parameter [1:0] REFCLK_ICNTL_RX = 2'b00; @@ -18905,7 +19120,7 @@ module IBUFDS_GTE4 (...); input IB; endmodule -module OBUFDS_GTE4 (...); +module OBUFDS_GTE4(O, OB, CEB, I); parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; (* iopad_external_pin *) @@ -18916,7 +19131,7 @@ module OBUFDS_GTE4 (...); input I; endmodule -module OBUFDS_GTE4_ADV (...); +module OBUFDS_GTE4_ADV(O, OB, CEB, I, RXRECCLK_SEL); parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; (* iopad_external_pin *) @@ -18928,7 +19143,20 @@ module OBUFDS_GTE4_ADV (...); input [1:0] RXRECCLK_SEL; endmodule -module GTM_DUAL (...); +module GTM_DUAL(CH0_AXISTDATA, CH0_AXISTLAST, CH0_AXISTVALID, CH0_DMONITOROUT, CH0_DMONITOROUTCLK, CH0_GTMTXN, CH0_GTMTXP, CH0_PCSRSVDOUT, CH0_PMARSVDOUT, CH0_RESETEXCEPTION, CH0_RXBUFSTATUS, CH0_RXDATA, CH0_RXDATAFLAGS, CH0_RXDATAISAM, CH0_RXDATASTART, CH0_RXOUTCLK, CH0_RXPMARESETDONE, CH0_RXPRBSERR, CH0_RXPRBSLOCKED, CH0_RXPRGDIVRESETDONE, CH0_RXPROGDIVCLK +, CH0_RXRESETDONE, CH0_TXBUFSTATUS, CH0_TXOUTCLK, CH0_TXPMARESETDONE, CH0_TXPRGDIVRESETDONE, CH0_TXPROGDIVCLK, CH0_TXRESETDONE, CH1_AXISTDATA, CH1_AXISTLAST, CH1_AXISTVALID, CH1_DMONITOROUT, CH1_DMONITOROUTCLK, CH1_GTMTXN, CH1_GTMTXP, CH1_PCSRSVDOUT, CH1_PMARSVDOUT, CH1_RESETEXCEPTION, CH1_RXBUFSTATUS, CH1_RXDATA, CH1_RXDATAFLAGS, CH1_RXDATAISAM +, CH1_RXDATASTART, CH1_RXOUTCLK, CH1_RXPMARESETDONE, CH1_RXPRBSERR, CH1_RXPRBSLOCKED, CH1_RXPRGDIVRESETDONE, CH1_RXPROGDIVCLK, CH1_RXRESETDONE, CH1_TXBUFSTATUS, CH1_TXOUTCLK, CH1_TXPMARESETDONE, CH1_TXPRGDIVRESETDONE, CH1_TXPROGDIVCLK, CH1_TXRESETDONE, CLKTESTSIG2PAD, DMONITOROUTPLLCLK, DRPDO, DRPRDY, FECRX0ALIGNED, FECRX0CORRCWINC, FECRX0CWINC +, FECRX0UNCORRCWINC, FECRX1ALIGNED, FECRX1CORRCWINC, FECRX1CWINC, FECRX1UNCORRCWINC, FECRXLN0BITERR0TO1INC, FECRXLN0BITERR1TO0INC, FECRXLN0DLY, FECRXLN0ERRCNTINC, FECRXLN0MAPPING, FECRXLN1BITERR0TO1INC, FECRXLN1BITERR1TO0INC, FECRXLN1DLY, FECRXLN1ERRCNTINC, FECRXLN1MAPPING, FECRXLN2BITERR0TO1INC, FECRXLN2BITERR1TO0INC, FECRXLN2DLY, FECRXLN2ERRCNTINC, FECRXLN2MAPPING, FECRXLN3BITERR0TO1INC +, FECRXLN3BITERR1TO0INC, FECRXLN3DLY, FECRXLN3ERRCNTINC, FECRXLN3MAPPING, FECTRXLN0LOCK, FECTRXLN1LOCK, FECTRXLN2LOCK, FECTRXLN3LOCK, GTPOWERGOOD, PLLFBCLKLOST, PLLLOCK, PLLREFCLKLOST, PLLREFCLKMONITOR, PLLRESETDONE, PLLRSVDOUT, RCALCMP, RCALOUT, RXRECCLK0, RXRECCLK1, BGBYPASSB, BGMONITORENB +, BGPDB, BGRCALOVRD, BGRCALOVRDENB, CH0_AXISEN, CH0_AXISRST, CH0_AXISTRDY, CH0_CFGRESET, CH0_DMONFIFORESET, CH0_DMONITORCLK, CH0_GTMRXN, CH0_GTMRXP, CH0_GTRXRESET, CH0_GTTXRESET, CH0_LOOPBACK, CH0_PCSRSVDIN, CH0_PMARSVDIN, CH0_RESETOVRD, CH0_RXADAPTRESET, CH0_RXADCCALRESET, CH0_RXADCCLKGENRESET, CH0_RXBUFRESET +, CH0_RXCDRFREQOS, CH0_RXCDRFRRESET, CH0_RXCDRHOLD, CH0_RXCDRINCPCTRL, CH0_RXCDROVRDEN, CH0_RXCDRPHRESET, CH0_RXDFERESET, CH0_RXDSPRESET, CH0_RXEQTRAINING, CH0_RXEYESCANRESET, CH0_RXFECRESET, CH0_RXOUTCLKSEL, CH0_RXPCSRESET, CH0_RXPCSRESETMASK, CH0_RXPMARESET, CH0_RXPMARESETMASK, CH0_RXPOLARITY, CH0_RXPRBSCNTSTOP, CH0_RXPRBSCSCNTRST, CH0_RXPRBSPTN, CH0_RXPROGDIVRESET +, CH0_RXQPRBSEN, CH0_RXRESETMODE, CH0_RXSPCSEQADV, CH0_RXUSRCLK, CH0_RXUSRCLK2, CH0_RXUSRRDY, CH0_RXUSRSTART, CH0_RXUSRSTOP, CH0_TXCKALRESET, CH0_TXCTLFIRDAT, CH0_TXDATA, CH0_TXDATASTART, CH0_TXDRVAMP, CH0_TXEMPMAIN, CH0_TXEMPPOST, CH0_TXEMPPRE, CH0_TXEMPPRE2, CH0_TXFECRESET, CH0_TXINHIBIT, CH0_TXMUXDCDEXHOLD, CH0_TXMUXDCDORWREN +, CH0_TXOUTCLKSEL, CH0_TXPCSRESET, CH0_TXPCSRESETMASK, CH0_TXPMARESET, CH0_TXPMARESETMASK, CH0_TXPOLARITY, CH0_TXPRBSINERR, CH0_TXPRBSPTN, CH0_TXPROGDIVRESET, CH0_TXQPRBSEN, CH0_TXRESETMODE, CH0_TXSPCSEQADV, CH0_TXUSRCLK, CH0_TXUSRCLK2, CH0_TXUSRRDY, CH1_AXISEN, CH1_AXISRST, CH1_AXISTRDY, CH1_CFGRESET, CH1_DMONFIFORESET, CH1_DMONITORCLK +, CH1_GTMRXN, CH1_GTMRXP, CH1_GTRXRESET, CH1_GTTXRESET, CH1_LOOPBACK, CH1_PCSRSVDIN, CH1_PMARSVDIN, CH1_RESETOVRD, CH1_RXADAPTRESET, CH1_RXADCCALRESET, CH1_RXADCCLKGENRESET, CH1_RXBUFRESET, CH1_RXCDRFREQOS, CH1_RXCDRFRRESET, CH1_RXCDRHOLD, CH1_RXCDRINCPCTRL, CH1_RXCDROVRDEN, CH1_RXCDRPHRESET, CH1_RXDFERESET, CH1_RXDSPRESET, CH1_RXEQTRAINING +, CH1_RXEYESCANRESET, CH1_RXFECRESET, CH1_RXOUTCLKSEL, CH1_RXPCSRESET, CH1_RXPCSRESETMASK, CH1_RXPMARESET, CH1_RXPMARESETMASK, CH1_RXPOLARITY, CH1_RXPRBSCNTSTOP, CH1_RXPRBSCSCNTRST, CH1_RXPRBSPTN, CH1_RXPROGDIVRESET, CH1_RXQPRBSEN, CH1_RXRESETMODE, CH1_RXSPCSEQADV, CH1_RXUSRCLK, CH1_RXUSRCLK2, CH1_RXUSRRDY, CH1_RXUSRSTART, CH1_RXUSRSTOP, CH1_TXCKALRESET +, CH1_TXCTLFIRDAT, CH1_TXDATA, CH1_TXDATASTART, CH1_TXDRVAMP, CH1_TXEMPMAIN, CH1_TXEMPPOST, CH1_TXEMPPRE, CH1_TXEMPPRE2, CH1_TXFECRESET, CH1_TXINHIBIT, CH1_TXMUXDCDEXHOLD, CH1_TXMUXDCDORWREN, CH1_TXOUTCLKSEL, CH1_TXPCSRESET, CH1_TXPCSRESETMASK, CH1_TXPMARESET, CH1_TXPMARESETMASK, CH1_TXPOLARITY, CH1_TXPRBSINERR, CH1_TXPRBSPTN, CH1_TXPROGDIVRESET +, CH1_TXQPRBSEN, CH1_TXRESETMODE, CH1_TXSPCSEQADV, CH1_TXUSRCLK, CH1_TXUSRCLK2, CH1_TXUSRRDY, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPRST, DRPWE, FECCTRLRX0BITSLIPFS, FECCTRLRX1BITSLIPFS, GTGREFCLK2PLL, GTNORTHREFCLK, GTREFCLK, GTSOUTHREFCLK, PLLFBDIV, PLLMONCLK, PLLPD +, PLLREFCLKSEL, PLLRESET, PLLRESETBYPASSMODE, PLLRESETMASK, PLLRSVDIN, RCALENB, SDMDATA, SDMTOGGLE); parameter [15:0] A_CFG = 16'b0000100001000000; parameter [15:0] A_SDM_DATA_CFG0 = 16'b0000000011010000; parameter [15:0] A_SDM_DATA_CFG1 = 16'b0000000011010000; @@ -19575,7 +19803,7 @@ module GTM_DUAL (...); input SDMTOGGLE; endmodule -module IBUFDS_GTM (...); +module IBUFDS_GTM(O, ODIV2, CEB, I, IB); parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; parameter integer REFCLK_HROW_CK_SEL = 0; parameter integer REFCLK_ICNTL_RX = 0; @@ -19588,7 +19816,7 @@ module IBUFDS_GTM (...); input IB; endmodule -module OBUFDS_GTM (...); +module OBUFDS_GTM(O, OB, CEB, I); parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; parameter integer REFCLK_ICNTL_TX = 0; (* iopad_external_pin *) @@ -19599,7 +19827,7 @@ module OBUFDS_GTM (...); input I; endmodule -module OBUFDS_GTM_ADV (...); +module OBUFDS_GTM_ADV(O, OB, CEB, I); parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; parameter integer REFCLK_ICNTL_TX = 0; parameter [1:0] RXRECCLK_SEL = 2'b00; @@ -19611,7 +19839,9 @@ module OBUFDS_GTM_ADV (...); input [3:0] I; endmodule -module HSDAC (...); +module HSDAC(CLK_DAC, DOUT, DRDY, PLL_DMON_OUT, PLL_REFCLK_OUT, STATUS_COMMON, STATUS_DAC0, STATUS_DAC1, STATUS_DAC2, STATUS_DAC3, SYSREF_OUT_NORTH, SYSREF_OUT_SOUTH, VOUT0_N, VOUT0_P, VOUT1_N, VOUT1_P, VOUT2_N, VOUT2_P, VOUT3_N, VOUT3_P, CLK_FIFO_LM +, CONTROL_COMMON, CONTROL_DAC0, CONTROL_DAC1, CONTROL_DAC2, CONTROL_DAC3, DAC_CLK_N, DAC_CLK_P, DADDR, DATA_DAC0, DATA_DAC1, DATA_DAC2, DATA_DAC3, DCLK, DEN, DI, DWE, FABRIC_CLK, PLL_MONCLK, PLL_REFCLK_IN, SYSREF_IN_NORTH, SYSREF_IN_SOUTH +, SYSREF_N, SYSREF_P); parameter SIM_DEVICE = "ULTRASCALE_PLUS"; parameter integer XPA_CFG0 = 0; parameter integer XPA_CFG1 = 0; @@ -19665,7 +19895,9 @@ module HSDAC (...); input SYSREF_P; endmodule -module HSADC (...); +module HSADC(CLK_ADC, DATA_ADC0, DATA_ADC1, DATA_ADC2, DATA_ADC3, DOUT, DRDY, PLL_DMON_OUT, PLL_REFCLK_OUT, STATUS_ADC0, STATUS_ADC1, STATUS_ADC2, STATUS_ADC3, STATUS_COMMON, SYSREF_OUT_NORTH, SYSREF_OUT_SOUTH, ADC_CLK_N, ADC_CLK_P, CLK_FIFO_LM, CONTROL_ADC0, CONTROL_ADC1 +, CONTROL_ADC2, CONTROL_ADC3, CONTROL_COMMON, DADDR, DCLK, DEN, DI, DWE, FABRIC_CLK, PLL_MONCLK, PLL_REFCLK_IN, SYSREF_IN_NORTH, SYSREF_IN_SOUTH, SYSREF_N, SYSREF_P, VIN0_N, VIN0_P, VIN1_N, VIN1_P, VIN2_N, VIN2_P +, VIN3_N, VIN3_P, VIN_I01_N, VIN_I01_P, VIN_I23_N, VIN_I23_P); parameter SIM_DEVICE = "ULTRASCALE_PLUS"; parameter integer XPA_CFG0 = 0; parameter integer XPA_CFG1 = 0; @@ -19723,7 +19955,9 @@ module HSADC (...); input VIN_I23_P; endmodule -module RFDAC (...); +module RFDAC(CLK_DAC, CLK_DIST_OUT_NORTH, CLK_DIST_OUT_SOUTH, DOUT, DRDY, PLL_DMON_OUT, PLL_REFCLK_OUT, STATUS_COMMON, STATUS_DAC0, STATUS_DAC1, STATUS_DAC2, STATUS_DAC3, SYSREF_OUT_NORTH, SYSREF_OUT_SOUTH, T1_ALLOWED_SOUTH, VOUT0_N, VOUT0_P, VOUT1_N, VOUT1_P, VOUT2_N, VOUT2_P +, VOUT3_N, VOUT3_P, CLK_DIST_IN_NORTH, CLK_DIST_IN_SOUTH, CLK_FIFO_LM, CONTROL_COMMON, CONTROL_DAC0, CONTROL_DAC1, CONTROL_DAC2, CONTROL_DAC3, DAC_CLK_N, DAC_CLK_P, DADDR, DATA_DAC0, DATA_DAC1, DATA_DAC2, DATA_DAC3, DCLK, DEN, DI, DWE +, FABRIC_CLK, PLL_MONCLK, PLL_REFCLK_IN, SYSREF_IN_NORTH, SYSREF_IN_SOUTH, SYSREF_N, SYSREF_P, T1_ALLOWED_NORTH); parameter integer LD_DEVICE = 0; parameter integer OPT_CLK_DIST = 0; parameter SIM_DEVICE = "ULTRASCALE_PLUS"; @@ -19787,7 +20021,9 @@ module RFDAC (...); input T1_ALLOWED_NORTH; endmodule -module RFADC (...); +module RFADC(CLK_ADC, CLK_DIST_OUT_NORTH, CLK_DIST_OUT_SOUTH, DATA_ADC0, DATA_ADC1, DATA_ADC2, DATA_ADC3, DOUT, DRDY, PLL_DMON_OUT, PLL_REFCLK_OUT, STATUS_ADC0, STATUS_ADC1, STATUS_ADC2, STATUS_ADC3, STATUS_COMMON, SYSREF_OUT_NORTH, SYSREF_OUT_SOUTH, T1_ALLOWED_SOUTH, ADC_CLK_N, ADC_CLK_P +, CLK_DIST_IN_NORTH, CLK_DIST_IN_SOUTH, CLK_FIFO_LM, CONTROL_ADC0, CONTROL_ADC1, CONTROL_ADC2, CONTROL_ADC3, CONTROL_COMMON, DADDR, DCLK, DEN, DI, DWE, FABRIC_CLK, PLL_MONCLK, PLL_REFCLK_IN, SYSREF_IN_NORTH, SYSREF_IN_SOUTH, SYSREF_N, SYSREF_P, T1_ALLOWED_NORTH +, VIN0_N, VIN0_P, VIN1_N, VIN1_P, VIN2_N, VIN2_P, VIN3_N, VIN3_P, VIN_I01_N, VIN_I01_P, VIN_I23_N, VIN_I23_P); parameter integer LD_DEVICE = 0; parameter integer OPT_ANALOG = 0; parameter integer OPT_CLK_DIST = 0; @@ -19856,7 +20092,14 @@ module RFADC (...); input VIN_I23_P; endmodule -module PCIE_A1 (...); +module PCIE_A1(CFGCOMMANDBUSMASTERENABLE, CFGCOMMANDINTERRUPTDISABLE, CFGCOMMANDIOENABLE, CFGCOMMANDMEMENABLE, CFGCOMMANDSERREN, CFGDEVCONTROLAUXPOWEREN, CFGDEVCONTROLCORRERRREPORTINGEN, CFGDEVCONTROLENABLERO, CFGDEVCONTROLEXTTAGEN, CFGDEVCONTROLFATALERRREPORTINGEN, CFGDEVCONTROLNONFATALREPORTINGEN, CFGDEVCONTROLNOSNOOPEN, CFGDEVCONTROLPHANTOMEN, CFGDEVCONTROLURERRREPORTINGEN, CFGDEVSTATUSCORRERRDETECTED, CFGDEVSTATUSFATALERRDETECTED, CFGDEVSTATUSNONFATALERRDETECTED, CFGDEVSTATUSURDETECTED, CFGERRCPLRDYN, CFGINTERRUPTMSIENABLE, CFGINTERRUPTRDYN +, CFGLINKCONTOLRCB, CFGLINKCONTROLCOMMONCLOCK, CFGLINKCONTROLEXTENDEDSYNC, CFGRDWRDONEN, CFGTOTURNOFFN, DBGBADDLLPSTATUS, DBGBADTLPLCRC, DBGBADTLPSEQNUM, DBGBADTLPSTATUS, DBGDLPROTOCOLSTATUS, DBGFCPROTOCOLERRSTATUS, DBGMLFRMDLENGTH, DBGMLFRMDMPS, DBGMLFRMDTCVC, DBGMLFRMDTLPSTATUS, DBGMLFRMDUNRECTYPE, DBGPOISTLPSTATUS, DBGRCVROVERFLOWSTATUS, DBGREGDETECTEDCORRECTABLE, DBGREGDETECTEDFATAL, DBGREGDETECTEDNONFATAL +, DBGREGDETECTEDUNSUPPORTED, DBGRPLYROLLOVERSTATUS, DBGRPLYTIMEOUTSTATUS, DBGURNOBARHIT, DBGURPOISCFGWR, DBGURSTATUS, DBGURUNSUPMSG, MIMRXREN, MIMRXWEN, MIMTXREN, MIMTXWEN, PIPEGTTXELECIDLEA, PIPEGTTXELECIDLEB, PIPERXPOLARITYA, PIPERXPOLARITYB, PIPERXRESETA, PIPERXRESETB, PIPETXRCVRDETA, PIPETXRCVRDETB, RECEIVEDHOTRESET, TRNLNKUPN +, TRNREOFN, TRNRERRFWDN, TRNRSOFN, TRNRSRCDSCN, TRNRSRCRDYN, TRNTCFGREQN, TRNTDSTRDYN, TRNTERRDROPN, USERRSTN, MIMRXRADDR, MIMRXWADDR, MIMTXRADDR, MIMTXWADDR, TRNFCCPLD, TRNFCNPD, TRNFCPD, PIPETXDATAA, PIPETXDATAB, CFGLINKCONTROLASPMCONTROL, PIPEGTPOWERDOWNA, PIPEGTPOWERDOWNB +, PIPETXCHARDISPMODEA, PIPETXCHARDISPMODEB, PIPETXCHARDISPVALA, PIPETXCHARDISPVALB, PIPETXCHARISKA, PIPETXCHARISKB, CFGDEVCONTROLMAXPAYLOAD, CFGDEVCONTROLMAXREADREQ, CFGFUNCTIONNUMBER, CFGINTERRUPTMMENABLE, CFGPCIELINKSTATEN, CFGDO, TRNRD, MIMRXWDATA, MIMTXWDATA, CFGDEVICENUMBER, CFGLTSSMSTATE, TRNTBUFAV, TRNRBARHITN, CFGBUSNUMBER, CFGINTERRUPTDO +, TRNFCCPLH, TRNFCNPH, TRNFCPH, CFGERRCORN, CFGERRCPLABORTN, CFGERRCPLTIMEOUTN, CFGERRECRCN, CFGERRLOCKEDN, CFGERRPOSTEDN, CFGERRURN, CFGINTERRUPTASSERTN, CFGINTERRUPTN, CFGPMWAKEN, CFGRDENN, CFGTRNPENDINGN, CFGTURNOFFOKN, CLOCKLOCKED, MGTCLK, PIPEGTRESETDONEA, PIPEGTRESETDONEB, PIPEPHYSTATUSA +, PIPEPHYSTATUSB, PIPERXENTERELECIDLEA, PIPERXENTERELECIDLEB, SYSRESETN, TRNRDSTRDYN, TRNRNPOKN, TRNTCFGGNTN, TRNTEOFN, TRNTERRFWDN, TRNTSOFN, TRNTSRCDSCN, TRNTSRCRDYN, TRNTSTRN, USERCLK, CFGDEVID, CFGSUBSYSID, CFGSUBSYSVENID, CFGVENID, PIPERXDATAA, PIPERXDATAB, PIPERXCHARISKA +, PIPERXCHARISKB, PIPERXSTATUSA, PIPERXSTATUSB, TRNFCSEL, TRNTD, MIMRXRDATA, MIMTXRDATA, CFGERRTLPCPLHEADER, CFGDSN, CFGINTERRUPTDI, CFGREVID, CFGDWADDR); parameter [31:0] BAR0 = 32'h00000000; parameter [31:0] BAR1 = 32'h00000000; parameter [31:0] BAR2 = 32'h00000000; @@ -20099,7 +20342,20 @@ module PCIE_A1 (...); input [9:0] CFGDWADDR; endmodule -module PCIE_EP (...); +module PCIE_EP(BUSMASTERENABLE, CRMDOHOTRESETN, CRMPWRSOFTRESETN, DLLTXPMDLLPOUTSTANDING, INTERRUPTDISABLE, IOSPACEENABLE, L0CFGLOOPBACKACK, L0DLLRXACKOUTSTANDING, L0DLLTXNONFCOUTSTANDING, L0DLLTXOUTSTANDING, L0FIRSTCFGWRITEOCCURRED, L0MACENTEREDL0, L0MACLINKTRAINING, L0MACLINKUP, L0MACNEWSTATEACK, L0MACRXL0SSTATE, L0MSIENABLE0, L0PMEACK, L0PMEEN, L0PMEREQOUT, L0PWRL1STATE +, L0PWRL23READYSTATE, L0PWRTURNOFFREQ, L0PWRTXL0SSTATE, L0RXDLLPM, L0STATSCFGOTHERRECEIVED, L0STATSCFGOTHERTRANSMITTED, L0STATSCFGRECEIVED, L0STATSCFGTRANSMITTED, L0STATSDLLPRECEIVED, L0STATSDLLPTRANSMITTED, L0STATSOSRECEIVED, L0STATSOSTRANSMITTED, L0STATSTLPRECEIVED, L0STATSTLPTRANSMITTED, L0UNLOCKRECEIVED, LLKRXEOFN, LLKRXEOPN, LLKRXSOFN, LLKRXSOPN, LLKRXSRCLASTREQN, LLKRXSRCRDYN +, LLKTXCONFIGREADYN, LLKTXDSTRDYN, MEMSPACEENABLE, MIMDLLBREN, MIMDLLBWEN, MIMRXBREN, MIMRXBWEN, MIMTXBREN, MIMTXBWEN, PARITYERRORRESPONSE, PIPEDESKEWLANESL0, PIPEDESKEWLANESL1, PIPEDESKEWLANESL2, PIPEDESKEWLANESL3, PIPEDESKEWLANESL4, PIPEDESKEWLANESL5, PIPEDESKEWLANESL6, PIPEDESKEWLANESL7, PIPERESETL0, PIPERESETL1, PIPERESETL2 +, PIPERESETL3, PIPERESETL4, PIPERESETL5, PIPERESETL6, PIPERESETL7, PIPERXPOLARITYL0, PIPERXPOLARITYL1, PIPERXPOLARITYL2, PIPERXPOLARITYL3, PIPERXPOLARITYL4, PIPERXPOLARITYL5, PIPERXPOLARITYL6, PIPERXPOLARITYL7, PIPETXCOMPLIANCEL0, PIPETXCOMPLIANCEL1, PIPETXCOMPLIANCEL2, PIPETXCOMPLIANCEL3, PIPETXCOMPLIANCEL4, PIPETXCOMPLIANCEL5, PIPETXCOMPLIANCEL6, PIPETXCOMPLIANCEL7 +, PIPETXDATAKL0, PIPETXDATAKL1, PIPETXDATAKL2, PIPETXDATAKL3, PIPETXDATAKL4, PIPETXDATAKL5, PIPETXDATAKL6, PIPETXDATAKL7, PIPETXDETECTRXLOOPBACKL0, PIPETXDETECTRXLOOPBACKL1, PIPETXDETECTRXLOOPBACKL2, PIPETXDETECTRXLOOPBACKL3, PIPETXDETECTRXLOOPBACKL4, PIPETXDETECTRXLOOPBACKL5, PIPETXDETECTRXLOOPBACKL6, PIPETXDETECTRXLOOPBACKL7, PIPETXELECIDLEL0, PIPETXELECIDLEL1, PIPETXELECIDLEL2, PIPETXELECIDLEL3, PIPETXELECIDLEL4 +, PIPETXELECIDLEL5, PIPETXELECIDLEL6, PIPETXELECIDLEL7, SERRENABLE, URREPORTINGENABLE, MGMTSTATSCREDIT, MIMDLLBRADD, MIMDLLBWADD, L0COMPLETERID, MIMRXBRADD, MIMRXBWADD, MIMTXBRADD, MIMTXBWADD, LLKRXPREFERREDTYPE, MGMTPSO, L0PWRSTATE0, L0RXMACLINKERROR, LLKRXVALIDN, PIPEPOWERDOWNL0, PIPEPOWERDOWNL1, PIPEPOWERDOWNL2 +, PIPEPOWERDOWNL3, PIPEPOWERDOWNL4, PIPEPOWERDOWNL5, PIPEPOWERDOWNL6, PIPEPOWERDOWNL7, L0MULTIMSGEN0, L0RXDLLPMTYPE, MAXPAYLOADSIZE, MAXREADREQUESTSIZE, MGMTRDATA, L0LTSSMSTATE, L0MACNEGOTIATEDLINKWIDTH, LLKRXDATA, MIMDLLBWDATA, MIMRXBWDATA, MIMTXBWDATA, L0DLLERRORVECTOR, L0DLLVCSTATUS, L0DLUPDOWN, LLKRXCHCOMPLETIONAVAILABLEN, LLKRXCHNONPOSTEDAVAILABLEN +, LLKRXCHPOSTEDAVAILABLEN, LLKTCSTATUS, LLKTXCHCOMPLETIONREADYN, LLKTXCHNONPOSTEDREADYN, LLKTXCHPOSTEDREADYN, PIPETXDATAL0, PIPETXDATAL1, PIPETXDATAL2, PIPETXDATAL3, PIPETXDATAL4, PIPETXDATAL5, PIPETXDATAL6, PIPETXDATAL7, LLKTXCHANSPACE, AUXPOWER, COMPLIANCEAVOID, CRMCORECLK, CRMCORECLKDLO, CRMCORECLKRXO, CRMCORECLKTXO, CRMLINKRSTN +, CRMMACRSTN, CRMMGMTRSTN, CRMNVRSTN, CRMURSTN, CRMUSERCFGRSTN, CRMUSERCLK, CRMUSERCLKRXO, CRMUSERCLKTXO, L0CFGDISABLESCRAMBLE, L0CFGLOOPBACKMASTER, L0LEGACYINTFUNCT0, L0PMEREQIN, L0SETCOMPLETERABORTERROR, L0SETCOMPLETIONTIMEOUTCORRERROR, L0SETCOMPLETIONTIMEOUTUNCORRERROR, L0SETDETECTEDCORRERROR, L0SETDETECTEDFATALERROR, L0SETDETECTEDNONFATALERROR, L0SETUNEXPECTEDCOMPLETIONCORRERROR, L0SETUNEXPECTEDCOMPLETIONUNCORRERROR, L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR +, L0SETUNSUPPORTEDREQUESTOTHERERROR, L0SETUSERDETECTEDPARITYERROR, L0SETUSERMASTERDATAPARITY, L0SETUSERRECEIVEDMASTERABORT, L0SETUSERRECEIVEDTARGETABORT, L0SETUSERSIGNALLEDTARGETABORT, L0SETUSERSYSTEMERROR, L0TRANSACTIONSPENDING, LLKRXDSTCONTREQN, LLKRXDSTREQN, LLKTXEOFN, LLKTXEOPN, LLKTXSOFN, LLKTXSOPN, LLKTXSRCDSCN, LLKTXSRCRDYN, MGMTRDEN, MGMTWREN, PIPEPHYSTATUSL0, PIPEPHYSTATUSL1, PIPEPHYSTATUSL2 +, PIPEPHYSTATUSL3, PIPEPHYSTATUSL4, PIPEPHYSTATUSL5, PIPEPHYSTATUSL6, PIPEPHYSTATUSL7, PIPERXCHANISALIGNEDL0, PIPERXCHANISALIGNEDL1, PIPERXCHANISALIGNEDL2, PIPERXCHANISALIGNEDL3, PIPERXCHANISALIGNEDL4, PIPERXCHANISALIGNEDL5, PIPERXCHANISALIGNEDL6, PIPERXCHANISALIGNEDL7, PIPERXDATAKL0, PIPERXDATAKL1, PIPERXDATAKL2, PIPERXDATAKL3, PIPERXDATAKL4, PIPERXDATAKL5, PIPERXDATAKL6, PIPERXDATAKL7 +, PIPERXELECIDLEL0, PIPERXELECIDLEL1, PIPERXELECIDLEL2, PIPERXELECIDLEL3, PIPERXELECIDLEL4, PIPERXELECIDLEL5, PIPERXELECIDLEL6, PIPERXELECIDLEL7, PIPERXVALIDL0, PIPERXVALIDL1, PIPERXVALIDL2, PIPERXVALIDL3, PIPERXVALIDL4, PIPERXVALIDL5, PIPERXVALIDL6, PIPERXVALIDL7, MGMTADDR, L0PACKETHEADERFROMUSER, LLKRXCHFIFO, LLKTXCHFIFO, LLKTXENABLEN +, LLKRXCHTC, LLKTXCHTC, PIPERXSTATUSL0, PIPERXSTATUSL1, PIPERXSTATUSL2, PIPERXSTATUSL3, PIPERXSTATUSL4, PIPERXSTATUSL5, PIPERXSTATUSL6, PIPERXSTATUSL7, MGMTWDATA, L0MSIREQUEST0, MGMTBWREN, LLKTXDATA, MIMDLLBRDATA, MIMRXBRDATA, MIMTXBRDATA, MGMTSTATSCREDITSEL, PIPERXDATAL0, PIPERXDATAL1, PIPERXDATAL2 +, PIPERXDATAL3, PIPERXDATAL4, PIPERXDATAL5, PIPERXDATAL6, PIPERXDATAL7); parameter BAR0EXIST = "TRUE"; parameter BAR0PREFETCHABLE = "TRUE"; parameter BAR1EXIST = "FALSE"; @@ -20540,7 +20796,23 @@ module PCIE_EP (...); input [7:0] PIPERXDATAL7; endmodule -module PCIE_2_0 (...); +module PCIE_2_0(CFGAERECRCCHECKEN, CFGAERECRCGENEN, CFGCOMMANDBUSMASTERENABLE, CFGCOMMANDINTERRUPTDISABLE, CFGCOMMANDIOENABLE, CFGCOMMANDMEMENABLE, CFGCOMMANDSERREN, CFGDEVCONTROL2CPLTIMEOUTDIS, CFGDEVCONTROLAUXPOWEREN, CFGDEVCONTROLCORRERRREPORTINGEN, CFGDEVCONTROLENABLERO, CFGDEVCONTROLEXTTAGEN, CFGDEVCONTROLFATALERRREPORTINGEN, CFGDEVCONTROLNONFATALREPORTINGEN, CFGDEVCONTROLNOSNOOPEN, CFGDEVCONTROLPHANTOMEN, CFGDEVCONTROLURERRREPORTINGEN, CFGDEVSTATUSCORRERRDETECTED, CFGDEVSTATUSFATALERRDETECTED, CFGDEVSTATUSNONFATALERRDETECTED, CFGDEVSTATUSURDETECTED +, CFGERRAERHEADERLOGSETN, CFGERRCPLRDYN, CFGINTERRUPTMSIENABLE, CFGINTERRUPTMSIXENABLE, CFGINTERRUPTMSIXFM, CFGINTERRUPTRDYN, CFGLINKCONTROLAUTOBANDWIDTHINTEN, CFGLINKCONTROLBANDWIDTHINTEN, CFGLINKCONTROLCLOCKPMEN, CFGLINKCONTROLCOMMONCLOCK, CFGLINKCONTROLEXTENDEDSYNC, CFGLINKCONTROLHWAUTOWIDTHDIS, CFGLINKCONTROLLINKDISABLE, CFGLINKCONTROLRCB, CFGLINKCONTROLRETRAINLINK, CFGLINKSTATUSAUTOBANDWIDTHSTATUS, CFGLINKSTATUSBANDWITHSTATUS, CFGLINKSTATUSDLLACTIVE, CFGLINKSTATUSLINKTRAINING, CFGMSGRECEIVED, CFGMSGRECEIVEDASSERTINTA +, CFGMSGRECEIVEDASSERTINTB, CFGMSGRECEIVEDASSERTINTC, CFGMSGRECEIVEDASSERTINTD, CFGMSGRECEIVEDDEASSERTINTA, CFGMSGRECEIVEDDEASSERTINTB, CFGMSGRECEIVEDDEASSERTINTC, CFGMSGRECEIVEDDEASSERTINTD, CFGMSGRECEIVEDERRCOR, CFGMSGRECEIVEDERRFATAL, CFGMSGRECEIVEDERRNONFATAL, CFGMSGRECEIVEDPMASNAK, CFGMSGRECEIVEDPMETO, CFGMSGRECEIVEDPMETOACK, CFGMSGRECEIVEDPMPME, CFGMSGRECEIVEDSETSLOTPOWERLIMIT, CFGMSGRECEIVEDUNLOCK, CFGPMCSRPMEEN, CFGPMCSRPMESTATUS, CFGPMRCVASREQL1N, CFGPMRCVENTERL1N, CFGPMRCVENTERL23N +, CFGPMRCVREQACKN, CFGRDWRDONEN, CFGSLOTCONTROLELECTROMECHILCTLPULSE, CFGTRANSACTION, CFGTRANSACTIONTYPE, DBGSCLRA, DBGSCLRB, DBGSCLRC, DBGSCLRD, DBGSCLRE, DBGSCLRF, DBGSCLRG, DBGSCLRH, DBGSCLRI, DBGSCLRJ, DBGSCLRK, DRPDRDY, LL2BADDLLPERRN, LL2BADTLPERRN, LL2PROTOCOLERRN, LL2REPLAYROERRN +, LL2REPLAYTOERRN, LL2SUSPENDOKN, LL2TFCINIT1SEQN, LL2TFCINIT2SEQN, LNKCLKEN, MIMRXRCE, MIMRXREN, MIMRXWEN, MIMTXRCE, MIMTXREN, MIMTXWEN, PIPERX0POLARITY, PIPERX1POLARITY, PIPERX2POLARITY, PIPERX3POLARITY, PIPERX4POLARITY, PIPERX5POLARITY, PIPERX6POLARITY, PIPERX7POLARITY, PIPETX0COMPLIANCE, PIPETX0ELECIDLE +, PIPETX1COMPLIANCE, PIPETX1ELECIDLE, PIPETX2COMPLIANCE, PIPETX2ELECIDLE, PIPETX3COMPLIANCE, PIPETX3ELECIDLE, PIPETX4COMPLIANCE, PIPETX4ELECIDLE, PIPETX5COMPLIANCE, PIPETX5ELECIDLE, PIPETX6COMPLIANCE, PIPETX6ELECIDLE, PIPETX7COMPLIANCE, PIPETX7ELECIDLE, PIPETXDEEMPH, PIPETXRATE, PIPETXRCVRDET, PIPETXRESET, PL2LINKUPN, PL2RECEIVERERRN, PL2RECOVERYN +, PL2RXELECIDLE, PL2SUSPENDOK, PLLINKGEN2CAP, PLLINKPARTNERGEN2SUPPORTED, PLLINKUPCFGCAP, PLPHYLNKUPN, PLRECEIVEDHOTRST, PLSELLNKRATE, RECEIVEDFUNCLVLRSTN, TL2ASPMSUSPENDCREDITCHECKOKN, TL2ASPMSUSPENDREQN, TL2PPMSUSPENDOKN, TRNLNKUPN, TRNRDLLPSRCRDYN, TRNRECRCERRN, TRNREOFN, TRNRERRFWDN, TRNRREMN, TRNRSOFN, TRNRSRCDSCN, TRNRSRCRDYN +, TRNTCFGREQN, TRNTDLLPDSTRDYN, TRNTDSTRDYN, TRNTERRDROPN, USERRSTN, DBGVECC, PLDBGVEC, TRNFCCPLD, TRNFCNPD, TRNFCPD, MIMRXRADDR, MIMRXWADDR, MIMTXRADDR, MIMTXWADDR, CFGMSGDATA, DRPDO, PIPETX0DATA, PIPETX1DATA, PIPETX2DATA, PIPETX3DATA, PIPETX4DATA +, PIPETX5DATA, PIPETX6DATA, PIPETX7DATA, CFGLINKCONTROLASPMCONTROL, CFGLINKSTATUSCURRENTSPEED, CFGPMCSRPOWERSTATE, PIPETX0CHARISK, PIPETX0POWERDOWN, PIPETX1CHARISK, PIPETX1POWERDOWN, PIPETX2CHARISK, PIPETX2POWERDOWN, PIPETX3CHARISK, PIPETX3POWERDOWN, PIPETX4CHARISK, PIPETX4POWERDOWN, PIPETX5CHARISK, PIPETX5POWERDOWN, PIPETX6CHARISK, PIPETX6POWERDOWN, PIPETX7CHARISK +, PIPETX7POWERDOWN, PLLANEREVERSALMODE, PLRXPMSTATE, PLSELLNKWIDTH, CFGDEVCONTROLMAXPAYLOAD, CFGDEVCONTROLMAXREADREQ, CFGINTERRUPTMMENABLE, CFGPCIELINKSTATE, PIPETXMARGIN, PLINITIALLINKWIDTH, PLTXPMSTATE, CFGDO, TRNRDLLPDATA, CFGDEVCONTROL2CPLTIMEOUTVAL, CFGLINKSTATUSNEGOTIATEDWIDTH, PLLTSSMSTATE, TRNTBUFAV, DBGVECA, DBGVECB, TRNRD, MIMRXWDATA +, MIMTXWDATA, CFGTRANSACTIONADDR, CFGVCTCVCMAP, TRNRBARHITN, CFGINTERRUPTDO, TRNFCCPLH, TRNFCNPH, TRNFCPH, CFGERRACSN, CFGERRCORN, CFGERRCPLABORTN, CFGERRCPLTIMEOUTN, CFGERRCPLUNEXPECTN, CFGERRECRCN, CFGERRLOCKEDN, CFGERRPOSTEDN, CFGERRURN, CFGINTERRUPTASSERTN, CFGINTERRUPTN, CFGPMDIRECTASPML1N, CFGPMSENDPMACKN +, CFGPMSENDPMETON, CFGPMSENDPMNAKN, CFGPMTURNOFFOKN, CFGPMWAKEN, CFGRDENN, CFGTRNPENDINGN, CFGWRENN, CFGWRREADONLYN, CFGWRRW1CASRWN, CMRSTN, CMSTICKYRSTN, DBGSUBMODE, DLRSTN, DRPCLK, DRPDEN, DRPDWE, FUNCLVLRSTN, LL2SENDASREQL1N, LL2SENDENTERL1N, LL2SENDENTERL23N, LL2SUSPENDNOWN +, LL2TLPRCVN, PIPECLK, PIPERX0CHANISALIGNED, PIPERX0ELECIDLE, PIPERX0PHYSTATUS, PIPERX0VALID, PIPERX1CHANISALIGNED, PIPERX1ELECIDLE, PIPERX1PHYSTATUS, PIPERX1VALID, PIPERX2CHANISALIGNED, PIPERX2ELECIDLE, PIPERX2PHYSTATUS, PIPERX2VALID, PIPERX3CHANISALIGNED, PIPERX3ELECIDLE, PIPERX3PHYSTATUS, PIPERX3VALID, PIPERX4CHANISALIGNED, PIPERX4ELECIDLE, PIPERX4PHYSTATUS +, PIPERX4VALID, PIPERX5CHANISALIGNED, PIPERX5ELECIDLE, PIPERX5PHYSTATUS, PIPERX5VALID, PIPERX6CHANISALIGNED, PIPERX6ELECIDLE, PIPERX6PHYSTATUS, PIPERX6VALID, PIPERX7CHANISALIGNED, PIPERX7ELECIDLE, PIPERX7PHYSTATUS, PIPERX7VALID, PLDIRECTEDLINKAUTON, PLDIRECTEDLINKSPEED, PLDOWNSTREAMDEEMPHSOURCE, PLRSTN, PLTRANSMITHOTRST, PLUPSTREAMPREFERDEEMPH, SYSRSTN, TL2ASPMSUSPENDCREDITCHECKN +, TL2PPMSUSPENDREQN, TLRSTN, TRNRDSTRDYN, TRNRNPOKN, TRNTCFGGNTN, TRNTDLLPSRCRDYN, TRNTECRCGENN, TRNTEOFN, TRNTERRFWDN, TRNTREMN, TRNTSOFN, TRNTSRCDSCN, TRNTSRCRDYN, TRNTSTRN, USERCLK, CFGERRAERHEADERLOG, DRPDI, PIPERX0DATA, PIPERX1DATA, PIPERX2DATA, PIPERX3DATA +, PIPERX4DATA, PIPERX5DATA, PIPERX6DATA, PIPERX7DATA, DBGMODE, PIPERX0CHARISK, PIPERX1CHARISK, PIPERX2CHARISK, PIPERX3CHARISK, PIPERX4CHARISK, PIPERX5CHARISK, PIPERX6CHARISK, PIPERX7CHARISK, PLDIRECTEDLINKCHANGE, PLDIRECTEDLINKWIDTH, CFGDSFUNCTIONNUMBER, PIPERX0STATUS, PIPERX1STATUS, PIPERX2STATUS, PIPERX3STATUS, PIPERX4STATUS +, PIPERX5STATUS, PIPERX6STATUS, PIPERX7STATUS, PLDBGMODE, TRNFCSEL, CFGDI, TRNTDLLPDATA, CFGBYTEENN, CFGERRTLPCPLHEADER, CFGDSDEVICENUMBER, PL2DIRECTEDLSTATE, CFGDSN, TRNTD, MIMRXRDATA, MIMTXRDATA, CFGDSBUSNUMBER, CFGINTERRUPTDI, CFGPORTNUMBER, DRPDADDR, CFGDWADDR); parameter [11:0] AER_BASE_PTR = 12'h128; parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; @@ -21135,7 +21407,26 @@ module PCIE_2_0 (...); input [9:0] CFGDWADDR; endmodule -module PCIE_2_1 (...); +module PCIE_2_1(CFGAERECRCCHECKEN, CFGAERECRCGENEN, CFGAERROOTERRCORRERRRECEIVED, CFGAERROOTERRCORRERRREPORTINGEN, CFGAERROOTERRFATALERRRECEIVED, CFGAERROOTERRFATALERRREPORTINGEN, CFGAERROOTERRNONFATALERRRECEIVED, CFGAERROOTERRNONFATALERRREPORTINGEN, CFGBRIDGESERREN, CFGCOMMANDBUSMASTERENABLE, CFGCOMMANDINTERRUPTDISABLE, CFGCOMMANDIOENABLE, CFGCOMMANDMEMENABLE, CFGCOMMANDSERREN, CFGDEVCONTROL2ARIFORWARDEN, CFGDEVCONTROL2ATOMICEGRESSBLOCK, CFGDEVCONTROL2ATOMICREQUESTEREN, CFGDEVCONTROL2CPLTIMEOUTDIS, CFGDEVCONTROL2IDOCPLEN, CFGDEVCONTROL2IDOREQEN, CFGDEVCONTROL2LTREN +, CFGDEVCONTROL2TLPPREFIXBLOCK, CFGDEVCONTROLAUXPOWEREN, CFGDEVCONTROLCORRERRREPORTINGEN, CFGDEVCONTROLENABLERO, CFGDEVCONTROLEXTTAGEN, CFGDEVCONTROLFATALERRREPORTINGEN, CFGDEVCONTROLNONFATALREPORTINGEN, CFGDEVCONTROLNOSNOOPEN, CFGDEVCONTROLPHANTOMEN, CFGDEVCONTROLURERRREPORTINGEN, CFGDEVSTATUSCORRERRDETECTED, CFGDEVSTATUSFATALERRDETECTED, CFGDEVSTATUSNONFATALERRDETECTED, CFGDEVSTATUSURDETECTED, CFGERRAERHEADERLOGSETN, CFGERRCPLRDYN, CFGINTERRUPTMSIENABLE, CFGINTERRUPTMSIXENABLE, CFGINTERRUPTMSIXFM, CFGINTERRUPTRDYN, CFGLINKCONTROLAUTOBANDWIDTHINTEN +, CFGLINKCONTROLBANDWIDTHINTEN, CFGLINKCONTROLCLOCKPMEN, CFGLINKCONTROLCOMMONCLOCK, CFGLINKCONTROLEXTENDEDSYNC, CFGLINKCONTROLHWAUTOWIDTHDIS, CFGLINKCONTROLLINKDISABLE, CFGLINKCONTROLRCB, CFGLINKCONTROLRETRAINLINK, CFGLINKSTATUSAUTOBANDWIDTHSTATUS, CFGLINKSTATUSBANDWIDTHSTATUS, CFGLINKSTATUSDLLACTIVE, CFGLINKSTATUSLINKTRAINING, CFGMGMTRDWRDONEN, CFGMSGRECEIVED, CFGMSGRECEIVEDASSERTINTA, CFGMSGRECEIVEDASSERTINTB, CFGMSGRECEIVEDASSERTINTC, CFGMSGRECEIVEDASSERTINTD, CFGMSGRECEIVEDDEASSERTINTA, CFGMSGRECEIVEDDEASSERTINTB, CFGMSGRECEIVEDDEASSERTINTC +, CFGMSGRECEIVEDDEASSERTINTD, CFGMSGRECEIVEDERRCOR, CFGMSGRECEIVEDERRFATAL, CFGMSGRECEIVEDERRNONFATAL, CFGMSGRECEIVEDPMASNAK, CFGMSGRECEIVEDPMETO, CFGMSGRECEIVEDPMETOACK, CFGMSGRECEIVEDPMPME, CFGMSGRECEIVEDSETSLOTPOWERLIMIT, CFGMSGRECEIVEDUNLOCK, CFGPMCSRPMEEN, CFGPMCSRPMESTATUS, CFGPMRCVASREQL1N, CFGPMRCVENTERL1N, CFGPMRCVENTERL23N, CFGPMRCVREQACKN, CFGROOTCONTROLPMEINTEN, CFGROOTCONTROLSYSERRCORRERREN, CFGROOTCONTROLSYSERRFATALERREN, CFGROOTCONTROLSYSERRNONFATALERREN, CFGSLOTCONTROLELECTROMECHILCTLPULSE +, CFGTRANSACTION, CFGTRANSACTIONTYPE, DBGSCLRA, DBGSCLRB, DBGSCLRC, DBGSCLRD, DBGSCLRE, DBGSCLRF, DBGSCLRG, DBGSCLRH, DBGSCLRI, DBGSCLRJ, DBGSCLRK, DRPRDY, LL2BADDLLPERR, LL2BADTLPERR, LL2PROTOCOLERR, LL2RECEIVERERR, LL2REPLAYROERR, LL2REPLAYTOERR, LL2SUSPENDOK +, LL2TFCINIT1SEQ, LL2TFCINIT2SEQ, LL2TXIDLE, LNKCLKEN, MIMRXREN, MIMRXWEN, MIMTXREN, MIMTXWEN, PIPERX0POLARITY, PIPERX1POLARITY, PIPERX2POLARITY, PIPERX3POLARITY, PIPERX4POLARITY, PIPERX5POLARITY, PIPERX6POLARITY, PIPERX7POLARITY, PIPETX0COMPLIANCE, PIPETX0ELECIDLE, PIPETX1COMPLIANCE, PIPETX1ELECIDLE, PIPETX2COMPLIANCE +, PIPETX2ELECIDLE, PIPETX3COMPLIANCE, PIPETX3ELECIDLE, PIPETX4COMPLIANCE, PIPETX4ELECIDLE, PIPETX5COMPLIANCE, PIPETX5ELECIDLE, PIPETX6COMPLIANCE, PIPETX6ELECIDLE, PIPETX7COMPLIANCE, PIPETX7ELECIDLE, PIPETXDEEMPH, PIPETXRATE, PIPETXRCVRDET, PIPETXRESET, PL2L0REQ, PL2LINKUP, PL2RECEIVERERR, PL2RECOVERY, PL2RXELECIDLE, PL2SUSPENDOK +, PLDIRECTEDCHANGEDONE, PLLINKGEN2CAP, PLLINKPARTNERGEN2SUPPORTED, PLLINKUPCFGCAP, PLPHYLNKUPN, PLRECEIVEDHOTRST, PLSELLNKRATE, RECEIVEDFUNCLVLRSTN, TL2ASPMSUSPENDCREDITCHECKOK, TL2ASPMSUSPENDREQ, TL2ERRFCPE, TL2ERRMALFORMED, TL2ERRRXOVERFLOW, TL2PPMSUSPENDOK, TRNLNKUP, TRNRECRCERR, TRNREOF, TRNRERRFWD, TRNRSOF, TRNRSRCDSC, TRNRSRCRDY +, TRNTCFGREQ, TRNTDLLPDSTRDY, TRNTERRDROP, USERRSTN, DBGVECC, PLDBGVEC, TRNFCCPLD, TRNFCNPD, TRNFCPD, TRNRD, MIMRXRADDR, MIMRXWADDR, MIMTXRADDR, MIMTXWADDR, CFGMSGDATA, DRPDO, PIPETX0DATA, PIPETX1DATA, PIPETX2DATA, PIPETX3DATA, PIPETX4DATA +, PIPETX5DATA, PIPETX6DATA, PIPETX7DATA, CFGLINKCONTROLASPMCONTROL, CFGLINKSTATUSCURRENTSPEED, CFGPMCSRPOWERSTATE, PIPETX0CHARISK, PIPETX0POWERDOWN, PIPETX1CHARISK, PIPETX1POWERDOWN, PIPETX2CHARISK, PIPETX2POWERDOWN, PIPETX3CHARISK, PIPETX3POWERDOWN, PIPETX4CHARISK, PIPETX4POWERDOWN, PIPETX5CHARISK, PIPETX5POWERDOWN, PIPETX6CHARISK, PIPETX6POWERDOWN, PIPETX7CHARISK +, PIPETX7POWERDOWN, PL2RXPMSTATE, PLLANEREVERSALMODE, PLRXPMSTATE, PLSELLNKWIDTH, TRNRDLLPSRCRDY, TRNRREM, CFGDEVCONTROLMAXPAYLOAD, CFGDEVCONTROLMAXREADREQ, CFGINTERRUPTMMENABLE, CFGPCIELINKSTATE, PIPETXMARGIN, PLINITIALLINKWIDTH, PLTXPMSTATE, CFGMGMTDO, CFGDEVCONTROL2CPLTIMEOUTVAL, CFGLINKSTATUSNEGOTIATEDWIDTH, TRNTDSTRDY, LL2LINKSTATUS, PLLTSSMSTATE, TRNTBUFAV +, DBGVECA, DBGVECB, TL2ERRHDR, TRNRDLLPDATA, MIMRXWDATA, MIMTXWDATA, CFGTRANSACTIONADDR, CFGVCTCVCMAP, CFGINTERRUPTDO, TRNFCCPLH, TRNFCNPH, TRNFCPH, TRNRBARHIT, CFGERRACSN, CFGERRATOMICEGRESSBLOCKEDN, CFGERRCORN, CFGERRCPLABORTN, CFGERRCPLTIMEOUTN, CFGERRCPLUNEXPECTN, CFGERRECRCN, CFGERRINTERNALCORN +, CFGERRINTERNALUNCORN, CFGERRLOCKEDN, CFGERRMALFORMEDN, CFGERRMCBLOCKEDN, CFGERRNORECOVERYN, CFGERRPOISONEDN, CFGERRPOSTEDN, CFGERRURN, CFGFORCECOMMONCLOCKOFF, CFGFORCEEXTENDEDSYNCON, CFGINTERRUPTASSERTN, CFGINTERRUPTN, CFGINTERRUPTSTATN, CFGMGMTRDENN, CFGMGMTWRENN, CFGMGMTWRREADONLYN, CFGMGMTWRRW1CASRWN, CFGPMFORCESTATEENN, CFGPMHALTASPML0SN, CFGPMHALTASPML1N, CFGPMSENDPMETON +, CFGPMTURNOFFOKN, CFGPMWAKEN, CFGTRNPENDINGN, CMRSTN, CMSTICKYRSTN, DBGSUBMODE, DLRSTN, DRPCLK, DRPEN, DRPWE, FUNCLVLRSTN, LL2SENDASREQL1, LL2SENDENTERL1, LL2SENDENTERL23, LL2SENDPMACK, LL2SUSPENDNOW, LL2TLPRCV, PIPECLK, PIPERX0CHANISALIGNED, PIPERX0ELECIDLE, PIPERX0PHYSTATUS +, PIPERX0VALID, PIPERX1CHANISALIGNED, PIPERX1ELECIDLE, PIPERX1PHYSTATUS, PIPERX1VALID, PIPERX2CHANISALIGNED, PIPERX2ELECIDLE, PIPERX2PHYSTATUS, PIPERX2VALID, PIPERX3CHANISALIGNED, PIPERX3ELECIDLE, PIPERX3PHYSTATUS, PIPERX3VALID, PIPERX4CHANISALIGNED, PIPERX4ELECIDLE, PIPERX4PHYSTATUS, PIPERX4VALID, PIPERX5CHANISALIGNED, PIPERX5ELECIDLE, PIPERX5PHYSTATUS, PIPERX5VALID +, PIPERX6CHANISALIGNED, PIPERX6ELECIDLE, PIPERX6PHYSTATUS, PIPERX6VALID, PIPERX7CHANISALIGNED, PIPERX7ELECIDLE, PIPERX7PHYSTATUS, PIPERX7VALID, PLDIRECTEDLINKAUTON, PLDIRECTEDLINKSPEED, PLDIRECTEDLTSSMNEWVLD, PLDIRECTEDLTSSMSTALL, PLDOWNSTREAMDEEMPHSOURCE, PLRSTN, PLTRANSMITHOTRST, PLUPSTREAMPREFERDEEMPH, SYSRSTN, TL2ASPMSUSPENDCREDITCHECK, TL2PPMSUSPENDREQ, TLRSTN, TRNRDSTRDY +, TRNRFCPRET, TRNRNPOK, TRNRNPREQ, TRNTCFGGNT, TRNTDLLPSRCRDY, TRNTECRCGEN, TRNTEOF, TRNTERRFWD, TRNTSOF, TRNTSRCDSC, TRNTSRCRDY, TRNTSTR, USERCLK2, USERCLK, CFGERRAERHEADERLOG, TRNTD, CFGDEVID, CFGSUBSYSID, CFGSUBSYSVENDID, CFGVENDID, DRPDI +, PIPERX0DATA, PIPERX1DATA, PIPERX2DATA, PIPERX3DATA, PIPERX4DATA, PIPERX5DATA, PIPERX6DATA, PIPERX7DATA, CFGPMFORCESTATE, DBGMODE, PIPERX0CHARISK, PIPERX1CHARISK, PIPERX2CHARISK, PIPERX3CHARISK, PIPERX4CHARISK, PIPERX5CHARISK, PIPERX6CHARISK, PIPERX7CHARISK, PLDIRECTEDLINKCHANGE, PLDIRECTEDLINKWIDTH, TRNTREM +, CFGDSFUNCTIONNUMBER, CFGFORCEMPS, PIPERX0STATUS, PIPERX1STATUS, PIPERX2STATUS, PIPERX3STATUS, PIPERX4STATUS, PIPERX5STATUS, PIPERX6STATUS, PIPERX7STATUS, PLDBGMODE, TRNFCSEL, CFGMGMTDI, TRNTDLLPDATA, CFGMGMTBYTEENN, CFGERRTLPCPLHEADER, CFGAERINTERRUPTMSGNUM, CFGDSDEVICENUMBER, CFGPCIECAPINTERRUPTMSGNUM, PL2DIRECTEDLSTATE, PLDIRECTEDLTSSMNEW +, CFGDSN, MIMRXRDATA, MIMTXRDATA, CFGDSBUSNUMBER, CFGINTERRUPTDI, CFGPORTNUMBER, CFGREVID, DRPADDR, CFGMGMTDWADDR); parameter [11:0] AER_BASE_PTR = 12'h140; parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; @@ -21830,7 +22121,29 @@ module PCIE_2_1 (...); input [9:0] CFGMGMTDWADDR; endmodule -module PCIE_3_0 (...); +module PCIE_3_0(CFGERRCOROUT, CFGERRFATALOUT, CFGERRNONFATALOUT, CFGEXTREADRECEIVED, CFGEXTWRITERECEIVED, CFGHOTRESETOUT, CFGINPUTUPDATEDONE, CFGINTERRUPTAOUTPUT, CFGINTERRUPTBOUTPUT, CFGINTERRUPTCOUTPUT, CFGINTERRUPTDOUTPUT, CFGINTERRUPTMSIFAIL, CFGINTERRUPTMSIMASKUPDATE, CFGINTERRUPTMSISENT, CFGINTERRUPTMSIXFAIL, CFGINTERRUPTMSIXSENT, CFGINTERRUPTSENT, CFGLOCALERROR, CFGLTRENABLE, CFGMCUPDATEDONE, CFGMGMTREADWRITEDONE +, CFGMSGRECEIVED, CFGMSGTRANSMITDONE, CFGPERFUNCTIONUPDATEDONE, CFGPHYLINKDOWN, CFGPLSTATUSCHANGE, CFGPOWERSTATECHANGEINTERRUPT, CFGTPHSTTREADENABLE, CFGTPHSTTWRITEENABLE, DRPRDY, MAXISCQTLAST, MAXISCQTVALID, MAXISRCTLAST, MAXISRCTVALID, PCIERQSEQNUMVLD, PCIERQTAGVLD, PIPERX0POLARITY, PIPERX1POLARITY, PIPERX2POLARITY, PIPERX3POLARITY, PIPERX4POLARITY, PIPERX5POLARITY +, PIPERX6POLARITY, PIPERX7POLARITY, PIPETX0COMPLIANCE, PIPETX0DATAVALID, PIPETX0ELECIDLE, PIPETX0STARTBLOCK, PIPETX1COMPLIANCE, PIPETX1DATAVALID, PIPETX1ELECIDLE, PIPETX1STARTBLOCK, PIPETX2COMPLIANCE, PIPETX2DATAVALID, PIPETX2ELECIDLE, PIPETX2STARTBLOCK, PIPETX3COMPLIANCE, PIPETX3DATAVALID, PIPETX3ELECIDLE, PIPETX3STARTBLOCK, PIPETX4COMPLIANCE, PIPETX4DATAVALID, PIPETX4ELECIDLE +, PIPETX4STARTBLOCK, PIPETX5COMPLIANCE, PIPETX5DATAVALID, PIPETX5ELECIDLE, PIPETX5STARTBLOCK, PIPETX6COMPLIANCE, PIPETX6DATAVALID, PIPETX6ELECIDLE, PIPETX6STARTBLOCK, PIPETX7COMPLIANCE, PIPETX7DATAVALID, PIPETX7ELECIDLE, PIPETX7STARTBLOCK, PIPETXDEEMPH, PIPETXRCVRDET, PIPETXRESET, PIPETXSWING, PLEQINPROGRESS, CFGFCCPLD, CFGFCNPD, CFGFCPD +, CFGVFSTATUS, MIREPLAYRAMWRITEDATA, MIREQUESTRAMWRITEDATA, CFGPERFUNCSTATUSDATA, DBGDATAOUT, DRPDO, CFGVFPOWERSTATE, CFGVFTPHSTMODE, CFGDPASUBSTATECHANGE, CFGFLRINPROCESS, CFGINTERRUPTMSIENABLE, CFGINTERRUPTMSIXENABLE, CFGINTERRUPTMSIXMASK, CFGLINKPOWERSTATE, CFGOBFFENABLE, CFGPHYLINKSTATUS, CFGRCBSTATUS, CFGTPHREQUESTERENABLE, MIREPLAYRAMREADENABLE, MIREPLAYRAMWRITEENABLE, PCIERQTAGAV +, PCIETFCNPDAV, PCIETFCNPHAV, PIPERX0EQCONTROL, PIPERX1EQCONTROL, PIPERX2EQCONTROL, PIPERX3EQCONTROL, PIPERX4EQCONTROL, PIPERX5EQCONTROL, PIPERX6EQCONTROL, PIPERX7EQCONTROL, PIPETX0CHARISK, PIPETX0EQCONTROL, PIPETX0POWERDOWN, PIPETX0SYNCHEADER, PIPETX1CHARISK, PIPETX1EQCONTROL, PIPETX1POWERDOWN, PIPETX1SYNCHEADER, PIPETX2CHARISK, PIPETX2EQCONTROL, PIPETX2POWERDOWN +, PIPETX2SYNCHEADER, PIPETX3CHARISK, PIPETX3EQCONTROL, PIPETX3POWERDOWN, PIPETX3SYNCHEADER, PIPETX4CHARISK, PIPETX4EQCONTROL, PIPETX4POWERDOWN, PIPETX4SYNCHEADER, PIPETX5CHARISK, PIPETX5EQCONTROL, PIPETX5POWERDOWN, PIPETX5SYNCHEADER, PIPETX6CHARISK, PIPETX6EQCONTROL, PIPETX6POWERDOWN, PIPETX6SYNCHEADER, PIPETX7CHARISK, PIPETX7EQCONTROL, PIPETX7POWERDOWN, PIPETX7SYNCHEADER +, PIPETXRATE, PLEQPHASE, MAXISCQTDATA, MAXISRCTDATA, CFGCURRENTSPEED, CFGMAXPAYLOAD, CFGMAXREADREQ, CFGTPHFUNCTIONNUM, PIPERX0EQPRESET, PIPERX1EQPRESET, PIPERX2EQPRESET, PIPERX3EQPRESET, PIPERX4EQPRESET, PIPERX5EQPRESET, PIPERX6EQPRESET, PIPERX7EQPRESET, PIPETXMARGIN, CFGEXTWRITEDATA, CFGINTERRUPTMSIDATA, CFGMGMTREADDATA, CFGTPHSTTWRITEDATA +, PIPETX0DATA, PIPETX1DATA, PIPETX2DATA, PIPETX3DATA, PIPETX4DATA, PIPETX5DATA, PIPETX6DATA, PIPETX7DATA, CFGEXTWRITEBYTEENABLE, CFGNEGOTIATEDWIDTH, CFGTPHSTTWRITEBYTEVALID, MICOMPLETIONRAMREADENABLEL, MICOMPLETIONRAMREADENABLEU, MICOMPLETIONRAMWRITEENABLEL, MICOMPLETIONRAMWRITEENABLEU, MIREQUESTRAMREADENABLE, MIREQUESTRAMWRITEENABLE, PCIERQSEQNUM, PIPERX0EQLPTXPRESET, PIPERX1EQLPTXPRESET, PIPERX2EQLPTXPRESET +, PIPERX3EQLPTXPRESET, PIPERX4EQLPTXPRESET, PIPERX5EQLPTXPRESET, PIPERX6EQLPTXPRESET, PIPERX7EQLPTXPRESET, PIPETX0EQPRESET, PIPETX1EQPRESET, PIPETX2EQPRESET, PIPETX3EQPRESET, PIPETX4EQPRESET, PIPETX5EQPRESET, PIPETX6EQPRESET, PIPETX7EQPRESET, SAXISCCTREADY, SAXISRQTREADY, CFGMSGRECEIVEDTYPE, CFGTPHSTTADDRESS, CFGFUNCTIONPOWERSTATE, CFGINTERRUPTMSIMMENABLE, CFGINTERRUPTMSIVFENABLE, CFGINTERRUPTMSIXVFENABLE +, CFGINTERRUPTMSIXVFMASK, CFGLTSSMSTATE, CFGTPHSTMODE, CFGVFFLRINPROCESS, CFGVFTPHREQUESTERENABLE, PCIECQNPREQCOUNT, PCIERQTAG, PIPERX0EQLPLFFS, PIPERX1EQLPLFFS, PIPERX2EQLPLFFS, PIPERX3EQLPLFFS, PIPERX4EQLPLFFS, PIPERX5EQLPLFFS, PIPERX6EQLPLFFS, PIPERX7EQLPLFFS, PIPETX0EQDEEMPH, PIPETX1EQDEEMPH, PIPETX2EQDEEMPH, PIPETX3EQDEEMPH, PIPETX4EQDEEMPH, PIPETX5EQDEEMPH +, PIPETX6EQDEEMPH, PIPETX7EQDEEMPH, MICOMPLETIONRAMWRITEDATAL, MICOMPLETIONRAMWRITEDATAU, MAXISRCTUSER, CFGEXTFUNCTIONNUMBER, CFGFCCPLH, CFGFCNPH, CFGFCPH, CFGFUNCTIONSTATUS, CFGMSGRECEIVEDDATA, MAXISCQTKEEP, MAXISRCTKEEP, PLGEN3PCSRXSLIDE, MAXISCQTUSER, MIREPLAYRAMADDRESS, MIREQUESTRAMREADADDRESSA, MIREQUESTRAMREADADDRESSB, MIREQUESTRAMWRITEADDRESSA, MIREQUESTRAMWRITEADDRESSB, CFGEXTREGISTERNUMBER +, MICOMPLETIONRAMREADADDRESSAL, MICOMPLETIONRAMREADADDRESSAU, MICOMPLETIONRAMREADADDRESSBL, MICOMPLETIONRAMREADADDRESSBU, MICOMPLETIONRAMWRITEADDRESSAL, MICOMPLETIONRAMWRITEADDRESSAU, MICOMPLETIONRAMWRITEADDRESSBL, MICOMPLETIONRAMWRITEADDRESSBU, CFGCONFIGSPACEENABLE, CFGERRCORIN, CFGERRUNCORIN, CFGEXTREADDATAVALID, CFGHOTRESETIN, CFGINPUTUPDATEREQUEST, CFGINTERRUPTMSITPHPRESENT, CFGINTERRUPTMSIXINT, CFGLINKTRAININGENABLE, CFGMCUPDATEREQUEST, CFGMGMTREAD, CFGMGMTTYPE1CFGREGACCESS, CFGMGMTWRITE +, CFGMSGTRANSMIT, CFGPERFUNCTIONOUTPUTREQUEST, CFGPOWERSTATECHANGEACK, CFGREQPMTRANSITIONL23READY, CFGTPHSTTREADDATAVALID, CORECLK, CORECLKMICOMPLETIONRAML, CORECLKMICOMPLETIONRAMU, CORECLKMIREPLAYRAM, CORECLKMIREQUESTRAM, DRPCLK, DRPEN, DRPWE, MGMTRESETN, MGMTSTICKYRESETN, PCIECQNPREQ, PIPECLK, PIPERESETN, PIPERX0DATAVALID, PIPERX0ELECIDLE, PIPERX0EQDONE +, PIPERX0EQLPADAPTDONE, PIPERX0EQLPLFFSSEL, PIPERX0PHYSTATUS, PIPERX0STARTBLOCK, PIPERX0VALID, PIPERX1DATAVALID, PIPERX1ELECIDLE, PIPERX1EQDONE, PIPERX1EQLPADAPTDONE, PIPERX1EQLPLFFSSEL, PIPERX1PHYSTATUS, PIPERX1STARTBLOCK, PIPERX1VALID, PIPERX2DATAVALID, PIPERX2ELECIDLE, PIPERX2EQDONE, PIPERX2EQLPADAPTDONE, PIPERX2EQLPLFFSSEL, PIPERX2PHYSTATUS, PIPERX2STARTBLOCK, PIPERX2VALID +, PIPERX3DATAVALID, PIPERX3ELECIDLE, PIPERX3EQDONE, PIPERX3EQLPADAPTDONE, PIPERX3EQLPLFFSSEL, PIPERX3PHYSTATUS, PIPERX3STARTBLOCK, PIPERX3VALID, PIPERX4DATAVALID, PIPERX4ELECIDLE, PIPERX4EQDONE, PIPERX4EQLPADAPTDONE, PIPERX4EQLPLFFSSEL, PIPERX4PHYSTATUS, PIPERX4STARTBLOCK, PIPERX4VALID, PIPERX5DATAVALID, PIPERX5ELECIDLE, PIPERX5EQDONE, PIPERX5EQLPADAPTDONE, PIPERX5EQLPLFFSSEL +, PIPERX5PHYSTATUS, PIPERX5STARTBLOCK, PIPERX5VALID, PIPERX6DATAVALID, PIPERX6ELECIDLE, PIPERX6EQDONE, PIPERX6EQLPADAPTDONE, PIPERX6EQLPLFFSSEL, PIPERX6PHYSTATUS, PIPERX6STARTBLOCK, PIPERX6VALID, PIPERX7DATAVALID, PIPERX7ELECIDLE, PIPERX7EQDONE, PIPERX7EQLPADAPTDONE, PIPERX7EQLPLFFSSEL, PIPERX7PHYSTATUS, PIPERX7STARTBLOCK, PIPERX7VALID, PIPETX0EQDONE, PIPETX1EQDONE +, PIPETX2EQDONE, PIPETX3EQDONE, PIPETX4EQDONE, PIPETX5EQDONE, PIPETX6EQDONE, PIPETX7EQDONE, PLDISABLESCRAMBLER, PLEQRESETEIEOSCOUNT, PLGEN3PCSDISABLE, RECCLK, RESETN, SAXISCCTLAST, SAXISCCTVALID, SAXISRQTLAST, SAXISRQTVALID, USERCLK, DRPADDR, MICOMPLETIONRAMREADDATA, MIREPLAYRAMREADDATA, MIREQUESTRAMREADDATA, CFGDEVID +, CFGSUBSYSID, CFGSUBSYSVENDID, CFGVENDID, DRPDI, PIPERX0EQLPNEWTXCOEFFORPRESET, PIPERX1EQLPNEWTXCOEFFORPRESET, PIPERX2EQLPNEWTXCOEFFORPRESET, PIPERX3EQLPNEWTXCOEFFORPRESET, PIPERX4EQLPNEWTXCOEFFORPRESET, PIPERX5EQLPNEWTXCOEFFORPRESET, PIPERX6EQLPNEWTXCOEFFORPRESET, PIPERX7EQLPNEWTXCOEFFORPRESET, PIPETX0EQCOEFF, PIPETX1EQCOEFF, PIPETX2EQCOEFF, PIPETX3EQCOEFF, PIPETX4EQCOEFF, PIPETX5EQCOEFF, PIPETX6EQCOEFF, PIPETX7EQCOEFF, CFGMGMTADDR +, CFGFLRDONE, CFGINTERRUPTMSITPHTYPE, CFGINTERRUPTPENDING, PIPERX0CHARISK, PIPERX0SYNCHEADER, PIPERX1CHARISK, PIPERX1SYNCHEADER, PIPERX2CHARISK, PIPERX2SYNCHEADER, PIPERX3CHARISK, PIPERX3SYNCHEADER, PIPERX4CHARISK, PIPERX4SYNCHEADER, PIPERX5CHARISK, PIPERX5SYNCHEADER, PIPERX6CHARISK, PIPERX6SYNCHEADER, PIPERX7CHARISK, PIPERX7SYNCHEADER, MAXISCQTREADY, MAXISRCTREADY +, SAXISCCTDATA, SAXISRQTDATA, CFGDSFUNCTIONNUMBER, CFGFCSEL, CFGINTERRUPTMSIATTR, CFGINTERRUPTMSIFUNCTIONNUMBER, CFGMSGTRANSMITTYPE, CFGPERFUNCSTATUSCONTROL, CFGPERFUNCTIONNUMBER, PIPERX0STATUS, PIPERX1STATUS, PIPERX2STATUS, PIPERX3STATUS, PIPERX4STATUS, PIPERX5STATUS, PIPERX6STATUS, PIPERX7STATUS, CFGEXTREADDATA, CFGINTERRUPTMSIINT, CFGINTERRUPTMSIXDATA, CFGMGMTWRITEDATA +, CFGMSGTRANSMITDATA, CFGTPHSTTREADDATA, PIPERX0DATA, PIPERX1DATA, PIPERX2DATA, PIPERX3DATA, PIPERX4DATA, PIPERX5DATA, PIPERX6DATA, PIPERX7DATA, SAXISCCTUSER, CFGINTERRUPTINT, CFGINTERRUPTMSISELECT, CFGMGMTBYTEENABLE, CFGDSDEVICENUMBER, SAXISRQTUSER, CFGVFFLRDONE, PIPEEQFS, PIPEEQLF, CFGDSN, CFGINTERRUPTMSIPENDINGSTATUS +, CFGINTERRUPTMSIXADDRESS, CFGDSBUSNUMBER, CFGDSPORTNUMBER, CFGREVID, PLGEN3PCSRXSYNCDONE, SAXISCCTKEEP, SAXISRQTKEEP, CFGINTERRUPTMSITPHSTTAG); parameter ARI_CAP_ENABLE = "FALSE"; parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE"; parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE"; @@ -22736,7 +23049,33 @@ module PCIE_3_0 (...); input [8:0] CFGINTERRUPTMSITPHSTTAG; endmodule -module PCIE_3_1 (...); +module PCIE_3_1(CFGCURRENTSPEED, CFGDPASUBSTATECHANGE, CFGERRCOROUT, CFGERRFATALOUT, CFGERRNONFATALOUT, CFGEXTFUNCTIONNUMBER, CFGEXTREADRECEIVED, CFGEXTREGISTERNUMBER, CFGEXTWRITEBYTEENABLE, CFGEXTWRITEDATA, CFGEXTWRITERECEIVED, CFGFCCPLD, CFGFCCPLH, CFGFCNPD, CFGFCNPH, CFGFCPD, CFGFCPH, CFGFLRINPROCESS, CFGFUNCTIONPOWERSTATE, CFGFUNCTIONSTATUS, CFGHOTRESETOUT +, CFGINTERRUPTMSIDATA, CFGINTERRUPTMSIENABLE, CFGINTERRUPTMSIFAIL, CFGINTERRUPTMSIMASKUPDATE, CFGINTERRUPTMSIMMENABLE, CFGINTERRUPTMSISENT, CFGINTERRUPTMSIVFENABLE, CFGINTERRUPTMSIXENABLE, CFGINTERRUPTMSIXFAIL, CFGINTERRUPTMSIXMASK, CFGINTERRUPTMSIXSENT, CFGINTERRUPTMSIXVFENABLE, CFGINTERRUPTMSIXVFMASK, CFGINTERRUPTSENT, CFGLINKPOWERSTATE, CFGLOCALERROR, CFGLTRENABLE, CFGLTSSMSTATE, CFGMAXPAYLOAD, CFGMAXREADREQ, CFGMGMTREADDATA +, CFGMGMTREADWRITEDONE, CFGMSGRECEIVED, CFGMSGRECEIVEDDATA, CFGMSGRECEIVEDTYPE, CFGMSGTRANSMITDONE, CFGNEGOTIATEDWIDTH, CFGOBFFENABLE, CFGPERFUNCSTATUSDATA, CFGPERFUNCTIONUPDATEDONE, CFGPHYLINKDOWN, CFGPHYLINKSTATUS, CFGPLSTATUSCHANGE, CFGPOWERSTATECHANGEINTERRUPT, CFGRCBSTATUS, CFGTPHFUNCTIONNUM, CFGTPHREQUESTERENABLE, CFGTPHSTMODE, CFGTPHSTTADDRESS, CFGTPHSTTREADENABLE, CFGTPHSTTWRITEBYTEVALID, CFGTPHSTTWRITEDATA +, CFGTPHSTTWRITEENABLE, CFGVFFLRINPROCESS, CFGVFPOWERSTATE, CFGVFSTATUS, CFGVFTPHREQUESTERENABLE, CFGVFTPHSTMODE, CONFMCAPDESIGNSWITCH, CONFMCAPEOS, CONFMCAPINUSEBYPCIE, CONFREQREADY, CONFRESPRDATA, CONFRESPVALID, DBGDATAOUT, DBGMCAPCSB, DBGMCAPDATA, DBGMCAPEOS, DBGMCAPERROR, DBGMCAPMODE, DBGMCAPRDATAVALID, DBGMCAPRDWRB, DBGMCAPRESET +, DBGPLDATABLOCKRECEIVEDAFTEREDS, DBGPLGEN3FRAMINGERRORDETECTED, DBGPLGEN3SYNCHEADERERRORDETECTED, DBGPLINFERREDRXELECTRICALIDLE, DRPDO, DRPRDY, LL2LMMASTERTLPSENT0, LL2LMMASTERTLPSENT1, LL2LMMASTERTLPSENTTLPID0, LL2LMMASTERTLPSENTTLPID1, LL2LMMAXISRXTDATA, LL2LMMAXISRXTUSER, LL2LMMAXISRXTVALID, LL2LMSAXISTXTREADY, MAXISCQTDATA, MAXISCQTKEEP, MAXISCQTLAST, MAXISCQTUSER, MAXISCQTVALID, MAXISRCTDATA, MAXISRCTKEEP +, MAXISRCTLAST, MAXISRCTUSER, MAXISRCTVALID, MICOMPLETIONRAMREADADDRESSAL, MICOMPLETIONRAMREADADDRESSAU, MICOMPLETIONRAMREADADDRESSBL, MICOMPLETIONRAMREADADDRESSBU, MICOMPLETIONRAMREADENABLEL, MICOMPLETIONRAMREADENABLEU, MICOMPLETIONRAMWRITEADDRESSAL, MICOMPLETIONRAMWRITEADDRESSAU, MICOMPLETIONRAMWRITEADDRESSBL, MICOMPLETIONRAMWRITEADDRESSBU, MICOMPLETIONRAMWRITEDATAL, MICOMPLETIONRAMWRITEDATAU, MICOMPLETIONRAMWRITEENABLEL, MICOMPLETIONRAMWRITEENABLEU, MIREPLAYRAMADDRESS, MIREPLAYRAMREADENABLE, MIREPLAYRAMWRITEDATA, MIREPLAYRAMWRITEENABLE +, MIREQUESTRAMREADADDRESSA, MIREQUESTRAMREADADDRESSB, MIREQUESTRAMREADENABLE, MIREQUESTRAMWRITEADDRESSA, MIREQUESTRAMWRITEADDRESSB, MIREQUESTRAMWRITEDATA, MIREQUESTRAMWRITEENABLE, PCIECQNPREQCOUNT, PCIEPERST0B, PCIEPERST1B, PCIERQSEQNUM, PCIERQSEQNUMVLD, PCIERQTAG, PCIERQTAGAV, PCIERQTAGVLD, PCIETFCNPDAV, PCIETFCNPHAV, PIPERX0EQCONTROL, PIPERX0EQLPLFFS, PIPERX0EQLPTXPRESET, PIPERX0EQPRESET +, PIPERX0POLARITY, PIPERX1EQCONTROL, PIPERX1EQLPLFFS, PIPERX1EQLPTXPRESET, PIPERX1EQPRESET, PIPERX1POLARITY, PIPERX2EQCONTROL, PIPERX2EQLPLFFS, PIPERX2EQLPTXPRESET, PIPERX2EQPRESET, PIPERX2POLARITY, PIPERX3EQCONTROL, PIPERX3EQLPLFFS, PIPERX3EQLPTXPRESET, PIPERX3EQPRESET, PIPERX3POLARITY, PIPERX4EQCONTROL, PIPERX4EQLPLFFS, PIPERX4EQLPTXPRESET, PIPERX4EQPRESET, PIPERX4POLARITY +, PIPERX5EQCONTROL, PIPERX5EQLPLFFS, PIPERX5EQLPTXPRESET, PIPERX5EQPRESET, PIPERX5POLARITY, PIPERX6EQCONTROL, PIPERX6EQLPLFFS, PIPERX6EQLPTXPRESET, PIPERX6EQPRESET, PIPERX6POLARITY, PIPERX7EQCONTROL, PIPERX7EQLPLFFS, PIPERX7EQLPTXPRESET, PIPERX7EQPRESET, PIPERX7POLARITY, PIPETX0CHARISK, PIPETX0COMPLIANCE, PIPETX0DATA, PIPETX0DATAVALID, PIPETX0DEEMPH, PIPETX0ELECIDLE +, PIPETX0EQCONTROL, PIPETX0EQDEEMPH, PIPETX0EQPRESET, PIPETX0MARGIN, PIPETX0POWERDOWN, PIPETX0RATE, PIPETX0RCVRDET, PIPETX0RESET, PIPETX0STARTBLOCK, PIPETX0SWING, PIPETX0SYNCHEADER, PIPETX1CHARISK, PIPETX1COMPLIANCE, PIPETX1DATA, PIPETX1DATAVALID, PIPETX1DEEMPH, PIPETX1ELECIDLE, PIPETX1EQCONTROL, PIPETX1EQDEEMPH, PIPETX1EQPRESET, PIPETX1MARGIN +, PIPETX1POWERDOWN, PIPETX1RATE, PIPETX1RCVRDET, PIPETX1RESET, PIPETX1STARTBLOCK, PIPETX1SWING, PIPETX1SYNCHEADER, PIPETX2CHARISK, PIPETX2COMPLIANCE, PIPETX2DATA, PIPETX2DATAVALID, PIPETX2DEEMPH, PIPETX2ELECIDLE, PIPETX2EQCONTROL, PIPETX2EQDEEMPH, PIPETX2EQPRESET, PIPETX2MARGIN, PIPETX2POWERDOWN, PIPETX2RATE, PIPETX2RCVRDET, PIPETX2RESET +, PIPETX2STARTBLOCK, PIPETX2SWING, PIPETX2SYNCHEADER, PIPETX3CHARISK, PIPETX3COMPLIANCE, PIPETX3DATA, PIPETX3DATAVALID, PIPETX3DEEMPH, PIPETX3ELECIDLE, PIPETX3EQCONTROL, PIPETX3EQDEEMPH, PIPETX3EQPRESET, PIPETX3MARGIN, PIPETX3POWERDOWN, PIPETX3RATE, PIPETX3RCVRDET, PIPETX3RESET, PIPETX3STARTBLOCK, PIPETX3SWING, PIPETX3SYNCHEADER, PIPETX4CHARISK +, PIPETX4COMPLIANCE, PIPETX4DATA, PIPETX4DATAVALID, PIPETX4DEEMPH, PIPETX4ELECIDLE, PIPETX4EQCONTROL, PIPETX4EQDEEMPH, PIPETX4EQPRESET, PIPETX4MARGIN, PIPETX4POWERDOWN, PIPETX4RATE, PIPETX4RCVRDET, PIPETX4RESET, PIPETX4STARTBLOCK, PIPETX4SWING, PIPETX4SYNCHEADER, PIPETX5CHARISK, PIPETX5COMPLIANCE, PIPETX5DATA, PIPETX5DATAVALID, PIPETX5DEEMPH +, PIPETX5ELECIDLE, PIPETX5EQCONTROL, PIPETX5EQDEEMPH, PIPETX5EQPRESET, PIPETX5MARGIN, PIPETX5POWERDOWN, PIPETX5RATE, PIPETX5RCVRDET, PIPETX5RESET, PIPETX5STARTBLOCK, PIPETX5SWING, PIPETX5SYNCHEADER, PIPETX6CHARISK, PIPETX6COMPLIANCE, PIPETX6DATA, PIPETX6DATAVALID, PIPETX6DEEMPH, PIPETX6ELECIDLE, PIPETX6EQCONTROL, PIPETX6EQDEEMPH, PIPETX6EQPRESET +, PIPETX6MARGIN, PIPETX6POWERDOWN, PIPETX6RATE, PIPETX6RCVRDET, PIPETX6RESET, PIPETX6STARTBLOCK, PIPETX6SWING, PIPETX6SYNCHEADER, PIPETX7CHARISK, PIPETX7COMPLIANCE, PIPETX7DATA, PIPETX7DATAVALID, PIPETX7DEEMPH, PIPETX7ELECIDLE, PIPETX7EQCONTROL, PIPETX7EQDEEMPH, PIPETX7EQPRESET, PIPETX7MARGIN, PIPETX7POWERDOWN, PIPETX7RATE, PIPETX7RCVRDET +, PIPETX7RESET, PIPETX7STARTBLOCK, PIPETX7SWING, PIPETX7SYNCHEADER, PLEQINPROGRESS, PLEQPHASE, SAXISCCTREADY, SAXISRQTREADY, SPAREOUT, CFGCONFIGSPACEENABLE, CFGDEVID, CFGDSBUSNUMBER, CFGDSDEVICENUMBER, CFGDSFUNCTIONNUMBER, CFGDSN, CFGDSPORTNUMBER, CFGERRCORIN, CFGERRUNCORIN, CFGEXTREADDATA, CFGEXTREADDATAVALID, CFGFCSEL +, CFGFLRDONE, CFGHOTRESETIN, CFGINTERRUPTINT, CFGINTERRUPTMSIATTR, CFGINTERRUPTMSIFUNCTIONNUMBER, CFGINTERRUPTMSIINT, CFGINTERRUPTMSIPENDINGSTATUS, CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM, CFGINTERRUPTMSISELECT, CFGINTERRUPTMSITPHPRESENT, CFGINTERRUPTMSITPHSTTAG, CFGINTERRUPTMSITPHTYPE, CFGINTERRUPTMSIXADDRESS, CFGINTERRUPTMSIXDATA, CFGINTERRUPTMSIXINT, CFGINTERRUPTPENDING, CFGLINKTRAININGENABLE, CFGMGMTADDR, CFGMGMTBYTEENABLE, CFGMGMTREAD +, CFGMGMTTYPE1CFGREGACCESS, CFGMGMTWRITE, CFGMGMTWRITEDATA, CFGMSGTRANSMIT, CFGMSGTRANSMITDATA, CFGMSGTRANSMITTYPE, CFGPERFUNCSTATUSCONTROL, CFGPERFUNCTIONNUMBER, CFGPERFUNCTIONOUTPUTREQUEST, CFGPOWERSTATECHANGEACK, CFGREQPMTRANSITIONL23READY, CFGREVID, CFGSUBSYSID, CFGSUBSYSVENDID, CFGTPHSTTREADDATA, CFGTPHSTTREADDATAVALID, CFGVENDID, CFGVFFLRDONE, CONFMCAPREQUESTBYCONF, CONFREQDATA, CONFREQREGNUM +, CONFREQTYPE, CONFREQVALID, CORECLK, CORECLKMICOMPLETIONRAML, CORECLKMICOMPLETIONRAMU, CORECLKMIREPLAYRAM, CORECLKMIREQUESTRAM, DBGCFGLOCALMGMTREGOVERRIDE, DBGDATASEL, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, LL2LMSAXISTXTUSER, LL2LMSAXISTXTVALID, LL2LMTXTLPID0, LL2LMTXTLPID1, MAXISCQTREADY, MAXISRCTREADY, MCAPCLK +, MCAPPERST0B, MCAPPERST1B, MGMTRESETN, MGMTSTICKYRESETN, MICOMPLETIONRAMREADDATA, MIREPLAYRAMREADDATA, MIREQUESTRAMREADDATA, PCIECQNPREQ, PIPECLK, PIPEEQFS, PIPEEQLF, PIPERESETN, PIPERX0CHARISK, PIPERX0DATA, PIPERX0DATAVALID, PIPERX0ELECIDLE, PIPERX0EQDONE, PIPERX0EQLPADAPTDONE, PIPERX0EQLPLFFSSEL, PIPERX0EQLPNEWTXCOEFFORPRESET, PIPERX0PHYSTATUS +, PIPERX0STARTBLOCK, PIPERX0STATUS, PIPERX0SYNCHEADER, PIPERX0VALID, PIPERX1CHARISK, PIPERX1DATA, PIPERX1DATAVALID, PIPERX1ELECIDLE, PIPERX1EQDONE, PIPERX1EQLPADAPTDONE, PIPERX1EQLPLFFSSEL, PIPERX1EQLPNEWTXCOEFFORPRESET, PIPERX1PHYSTATUS, PIPERX1STARTBLOCK, PIPERX1STATUS, PIPERX1SYNCHEADER, PIPERX1VALID, PIPERX2CHARISK, PIPERX2DATA, PIPERX2DATAVALID, PIPERX2ELECIDLE +, PIPERX2EQDONE, PIPERX2EQLPADAPTDONE, PIPERX2EQLPLFFSSEL, PIPERX2EQLPNEWTXCOEFFORPRESET, PIPERX2PHYSTATUS, PIPERX2STARTBLOCK, PIPERX2STATUS, PIPERX2SYNCHEADER, PIPERX2VALID, PIPERX3CHARISK, PIPERX3DATA, PIPERX3DATAVALID, PIPERX3ELECIDLE, PIPERX3EQDONE, PIPERX3EQLPADAPTDONE, PIPERX3EQLPLFFSSEL, PIPERX3EQLPNEWTXCOEFFORPRESET, PIPERX3PHYSTATUS, PIPERX3STARTBLOCK, PIPERX3STATUS, PIPERX3SYNCHEADER +, PIPERX3VALID, PIPERX4CHARISK, PIPERX4DATA, PIPERX4DATAVALID, PIPERX4ELECIDLE, PIPERX4EQDONE, PIPERX4EQLPADAPTDONE, PIPERX4EQLPLFFSSEL, PIPERX4EQLPNEWTXCOEFFORPRESET, PIPERX4PHYSTATUS, PIPERX4STARTBLOCK, PIPERX4STATUS, PIPERX4SYNCHEADER, PIPERX4VALID, PIPERX5CHARISK, PIPERX5DATA, PIPERX5DATAVALID, PIPERX5ELECIDLE, PIPERX5EQDONE, PIPERX5EQLPADAPTDONE, PIPERX5EQLPLFFSSEL +, PIPERX5EQLPNEWTXCOEFFORPRESET, PIPERX5PHYSTATUS, PIPERX5STARTBLOCK, PIPERX5STATUS, PIPERX5SYNCHEADER, PIPERX5VALID, PIPERX6CHARISK, PIPERX6DATA, PIPERX6DATAVALID, PIPERX6ELECIDLE, PIPERX6EQDONE, PIPERX6EQLPADAPTDONE, PIPERX6EQLPLFFSSEL, PIPERX6EQLPNEWTXCOEFFORPRESET, PIPERX6PHYSTATUS, PIPERX6STARTBLOCK, PIPERX6STATUS, PIPERX6SYNCHEADER, PIPERX6VALID, PIPERX7CHARISK, PIPERX7DATA +, PIPERX7DATAVALID, PIPERX7ELECIDLE, PIPERX7EQDONE, PIPERX7EQLPADAPTDONE, PIPERX7EQLPLFFSSEL, PIPERX7EQLPNEWTXCOEFFORPRESET, PIPERX7PHYSTATUS, PIPERX7STARTBLOCK, PIPERX7STATUS, PIPERX7SYNCHEADER, PIPERX7VALID, PIPETX0EQCOEFF, PIPETX0EQDONE, PIPETX1EQCOEFF, PIPETX1EQDONE, PIPETX2EQCOEFF, PIPETX2EQDONE, PIPETX3EQCOEFF, PIPETX3EQDONE, PIPETX4EQCOEFF, PIPETX4EQDONE +, PIPETX5EQCOEFF, PIPETX5EQDONE, PIPETX6EQCOEFF, PIPETX6EQDONE, PIPETX7EQCOEFF, PIPETX7EQDONE, PLEQRESETEIEOSCOUNT, PLGEN2UPSTREAMPREFERDEEMPH, RESETN, SAXISCCTDATA, SAXISCCTKEEP, SAXISCCTLAST, SAXISCCTUSER, SAXISCCTVALID, SAXISRQTDATA, SAXISRQTKEEP, SAXISRQTLAST, SAXISRQTUSER, SAXISRQTVALID, SPAREIN, USERCLK +); parameter ARI_CAP_ENABLE = "FALSE"; parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE"; parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE"; @@ -24004,7 +24343,40 @@ module PCIE_3_1 (...); input USERCLK; endmodule -module PCIE40E4 (...); +module PCIE40E4(AXIUSEROUT, CFGBUSNUMBER, CFGCURRENTSPEED, CFGERRCOROUT, CFGERRFATALOUT, CFGERRNONFATALOUT, CFGEXTFUNCTIONNUMBER, CFGEXTREADRECEIVED, CFGEXTREGISTERNUMBER, CFGEXTWRITEBYTEENABLE, CFGEXTWRITEDATA, CFGEXTWRITERECEIVED, CFGFCCPLD, CFGFCCPLH, CFGFCNPD, CFGFCNPH, CFGFCPD, CFGFCPH, CFGFLRINPROCESS, CFGFUNCTIONPOWERSTATE, CFGFUNCTIONSTATUS +, CFGHOTRESETOUT, CFGINTERRUPTMSIDATA, CFGINTERRUPTMSIENABLE, CFGINTERRUPTMSIFAIL, CFGINTERRUPTMSIMASKUPDATE, CFGINTERRUPTMSIMMENABLE, CFGINTERRUPTMSISENT, CFGINTERRUPTMSIXENABLE, CFGINTERRUPTMSIXMASK, CFGINTERRUPTMSIXVECPENDINGSTATUS, CFGINTERRUPTSENT, CFGLINKPOWERSTATE, CFGLOCALERROROUT, CFGLOCALERRORVALID, CFGLTRENABLE, CFGLTSSMSTATE, CFGMAXPAYLOAD, CFGMAXREADREQ, CFGMGMTREADDATA, CFGMGMTREADWRITEDONE, CFGMSGRECEIVED +, CFGMSGRECEIVEDDATA, CFGMSGRECEIVEDTYPE, CFGMSGTRANSMITDONE, CFGMSIXRAMADDRESS, CFGMSIXRAMREADENABLE, CFGMSIXRAMWRITEBYTEENABLE, CFGMSIXRAMWRITEDATA, CFGNEGOTIATEDWIDTH, CFGOBFFENABLE, CFGPHYLINKDOWN, CFGPHYLINKSTATUS, CFGPLSTATUSCHANGE, CFGPOWERSTATECHANGEINTERRUPT, CFGRCBSTATUS, CFGRXPMSTATE, CFGTPHRAMADDRESS, CFGTPHRAMREADENABLE, CFGTPHRAMWRITEBYTEENABLE, CFGTPHRAMWRITEDATA, CFGTPHREQUESTERENABLE, CFGTPHSTMODE +, CFGTXPMSTATE, CONFMCAPDESIGNSWITCH, CONFMCAPEOS, CONFMCAPINUSEBYPCIE, CONFREQREADY, CONFRESPRDATA, CONFRESPVALID, DBGCTRL0OUT, DBGCTRL1OUT, DBGDATA0OUT, DBGDATA1OUT, DRPDO, DRPRDY, MAXISCQTDATA, MAXISCQTKEEP, MAXISCQTLAST, MAXISCQTUSER, MAXISCQTVALID, MAXISRCTDATA, MAXISRCTKEEP, MAXISRCTLAST +, MAXISRCTUSER, MAXISRCTVALID, MIREPLAYRAMADDRESS0, MIREPLAYRAMADDRESS1, MIREPLAYRAMREADENABLE0, MIREPLAYRAMREADENABLE1, MIREPLAYRAMWRITEDATA0, MIREPLAYRAMWRITEDATA1, MIREPLAYRAMWRITEENABLE0, MIREPLAYRAMWRITEENABLE1, MIRXCOMPLETIONRAMREADADDRESS0, MIRXCOMPLETIONRAMREADADDRESS1, MIRXCOMPLETIONRAMREADENABLE0, MIRXCOMPLETIONRAMREADENABLE1, MIRXCOMPLETIONRAMWRITEADDRESS0, MIRXCOMPLETIONRAMWRITEADDRESS1, MIRXCOMPLETIONRAMWRITEDATA0, MIRXCOMPLETIONRAMWRITEDATA1, MIRXCOMPLETIONRAMWRITEENABLE0, MIRXCOMPLETIONRAMWRITEENABLE1, MIRXPOSTEDREQUESTRAMREADADDRESS0 +, MIRXPOSTEDREQUESTRAMREADADDRESS1, MIRXPOSTEDREQUESTRAMREADENABLE0, MIRXPOSTEDREQUESTRAMREADENABLE1, MIRXPOSTEDREQUESTRAMWRITEADDRESS0, MIRXPOSTEDREQUESTRAMWRITEADDRESS1, MIRXPOSTEDREQUESTRAMWRITEDATA0, MIRXPOSTEDREQUESTRAMWRITEDATA1, MIRXPOSTEDREQUESTRAMWRITEENABLE0, MIRXPOSTEDREQUESTRAMWRITEENABLE1, PCIECQNPREQCOUNT, PCIEPERST0B, PCIEPERST1B, PCIERQSEQNUM0, PCIERQSEQNUM1, PCIERQSEQNUMVLD0, PCIERQSEQNUMVLD1, PCIERQTAG0, PCIERQTAG1, PCIERQTAGAV, PCIERQTAGVLD0, PCIERQTAGVLD1 +, PCIETFCNPDAV, PCIETFCNPHAV, PIPERX00EQCONTROL, PIPERX00POLARITY, PIPERX01EQCONTROL, PIPERX01POLARITY, PIPERX02EQCONTROL, PIPERX02POLARITY, PIPERX03EQCONTROL, PIPERX03POLARITY, PIPERX04EQCONTROL, PIPERX04POLARITY, PIPERX05EQCONTROL, PIPERX05POLARITY, PIPERX06EQCONTROL, PIPERX06POLARITY, PIPERX07EQCONTROL, PIPERX07POLARITY, PIPERX08EQCONTROL, PIPERX08POLARITY, PIPERX09EQCONTROL +, PIPERX09POLARITY, PIPERX10EQCONTROL, PIPERX10POLARITY, PIPERX11EQCONTROL, PIPERX11POLARITY, PIPERX12EQCONTROL, PIPERX12POLARITY, PIPERX13EQCONTROL, PIPERX13POLARITY, PIPERX14EQCONTROL, PIPERX14POLARITY, PIPERX15EQCONTROL, PIPERX15POLARITY, PIPERXEQLPLFFS, PIPERXEQLPTXPRESET, PIPETX00CHARISK, PIPETX00COMPLIANCE, PIPETX00DATA, PIPETX00DATAVALID, PIPETX00ELECIDLE, PIPETX00EQCONTROL +, PIPETX00EQDEEMPH, PIPETX00POWERDOWN, PIPETX00STARTBLOCK, PIPETX00SYNCHEADER, PIPETX01CHARISK, PIPETX01COMPLIANCE, PIPETX01DATA, PIPETX01DATAVALID, PIPETX01ELECIDLE, PIPETX01EQCONTROL, PIPETX01EQDEEMPH, PIPETX01POWERDOWN, PIPETX01STARTBLOCK, PIPETX01SYNCHEADER, PIPETX02CHARISK, PIPETX02COMPLIANCE, PIPETX02DATA, PIPETX02DATAVALID, PIPETX02ELECIDLE, PIPETX02EQCONTROL, PIPETX02EQDEEMPH +, PIPETX02POWERDOWN, PIPETX02STARTBLOCK, PIPETX02SYNCHEADER, PIPETX03CHARISK, PIPETX03COMPLIANCE, PIPETX03DATA, PIPETX03DATAVALID, PIPETX03ELECIDLE, PIPETX03EQCONTROL, PIPETX03EQDEEMPH, PIPETX03POWERDOWN, PIPETX03STARTBLOCK, PIPETX03SYNCHEADER, PIPETX04CHARISK, PIPETX04COMPLIANCE, PIPETX04DATA, PIPETX04DATAVALID, PIPETX04ELECIDLE, PIPETX04EQCONTROL, PIPETX04EQDEEMPH, PIPETX04POWERDOWN +, PIPETX04STARTBLOCK, PIPETX04SYNCHEADER, PIPETX05CHARISK, PIPETX05COMPLIANCE, PIPETX05DATA, PIPETX05DATAVALID, PIPETX05ELECIDLE, PIPETX05EQCONTROL, PIPETX05EQDEEMPH, PIPETX05POWERDOWN, PIPETX05STARTBLOCK, PIPETX05SYNCHEADER, PIPETX06CHARISK, PIPETX06COMPLIANCE, PIPETX06DATA, PIPETX06DATAVALID, PIPETX06ELECIDLE, PIPETX06EQCONTROL, PIPETX06EQDEEMPH, PIPETX06POWERDOWN, PIPETX06STARTBLOCK +, PIPETX06SYNCHEADER, PIPETX07CHARISK, PIPETX07COMPLIANCE, PIPETX07DATA, PIPETX07DATAVALID, PIPETX07ELECIDLE, PIPETX07EQCONTROL, PIPETX07EQDEEMPH, PIPETX07POWERDOWN, PIPETX07STARTBLOCK, PIPETX07SYNCHEADER, PIPETX08CHARISK, PIPETX08COMPLIANCE, PIPETX08DATA, PIPETX08DATAVALID, PIPETX08ELECIDLE, PIPETX08EQCONTROL, PIPETX08EQDEEMPH, PIPETX08POWERDOWN, PIPETX08STARTBLOCK, PIPETX08SYNCHEADER +, PIPETX09CHARISK, PIPETX09COMPLIANCE, PIPETX09DATA, PIPETX09DATAVALID, PIPETX09ELECIDLE, PIPETX09EQCONTROL, PIPETX09EQDEEMPH, PIPETX09POWERDOWN, PIPETX09STARTBLOCK, PIPETX09SYNCHEADER, PIPETX10CHARISK, PIPETX10COMPLIANCE, PIPETX10DATA, PIPETX10DATAVALID, PIPETX10ELECIDLE, PIPETX10EQCONTROL, PIPETX10EQDEEMPH, PIPETX10POWERDOWN, PIPETX10STARTBLOCK, PIPETX10SYNCHEADER, PIPETX11CHARISK +, PIPETX11COMPLIANCE, PIPETX11DATA, PIPETX11DATAVALID, PIPETX11ELECIDLE, PIPETX11EQCONTROL, PIPETX11EQDEEMPH, PIPETX11POWERDOWN, PIPETX11STARTBLOCK, PIPETX11SYNCHEADER, PIPETX12CHARISK, PIPETX12COMPLIANCE, PIPETX12DATA, PIPETX12DATAVALID, PIPETX12ELECIDLE, PIPETX12EQCONTROL, PIPETX12EQDEEMPH, PIPETX12POWERDOWN, PIPETX12STARTBLOCK, PIPETX12SYNCHEADER, PIPETX13CHARISK, PIPETX13COMPLIANCE +, PIPETX13DATA, PIPETX13DATAVALID, PIPETX13ELECIDLE, PIPETX13EQCONTROL, PIPETX13EQDEEMPH, PIPETX13POWERDOWN, PIPETX13STARTBLOCK, PIPETX13SYNCHEADER, PIPETX14CHARISK, PIPETX14COMPLIANCE, PIPETX14DATA, PIPETX14DATAVALID, PIPETX14ELECIDLE, PIPETX14EQCONTROL, PIPETX14EQDEEMPH, PIPETX14POWERDOWN, PIPETX14STARTBLOCK, PIPETX14SYNCHEADER, PIPETX15CHARISK, PIPETX15COMPLIANCE, PIPETX15DATA +, PIPETX15DATAVALID, PIPETX15ELECIDLE, PIPETX15EQCONTROL, PIPETX15EQDEEMPH, PIPETX15POWERDOWN, PIPETX15STARTBLOCK, PIPETX15SYNCHEADER, PIPETXDEEMPH, PIPETXMARGIN, PIPETXRATE, PIPETXRCVRDET, PIPETXRESET, PIPETXSWING, PLEQINPROGRESS, PLEQPHASE, PLGEN34EQMISMATCH, SAXISCCTREADY, SAXISRQTREADY, USERSPAREOUT, AXIUSERIN, CFGCONFIGSPACEENABLE +, CFGDEVIDPF0, CFGDEVIDPF1, CFGDEVIDPF2, CFGDEVIDPF3, CFGDSBUSNUMBER, CFGDSDEVICENUMBER, CFGDSFUNCTIONNUMBER, CFGDSN, CFGDSPORTNUMBER, CFGERRCORIN, CFGERRUNCORIN, CFGEXTREADDATA, CFGEXTREADDATAVALID, CFGFCSEL, CFGFLRDONE, CFGHOTRESETIN, CFGINTERRUPTINT, CFGINTERRUPTMSIATTR, CFGINTERRUPTMSIFUNCTIONNUMBER, CFGINTERRUPTMSIINT, CFGINTERRUPTMSIPENDINGSTATUS +, CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM, CFGINTERRUPTMSISELECT, CFGINTERRUPTMSITPHPRESENT, CFGINTERRUPTMSITPHSTTAG, CFGINTERRUPTMSITPHTYPE, CFGINTERRUPTMSIXADDRESS, CFGINTERRUPTMSIXDATA, CFGINTERRUPTMSIXINT, CFGINTERRUPTMSIXVECPENDING, CFGINTERRUPTPENDING, CFGLINKTRAININGENABLE, CFGMGMTADDR, CFGMGMTBYTEENABLE, CFGMGMTDEBUGACCESS, CFGMGMTFUNCTIONNUMBER, CFGMGMTREAD, CFGMGMTWRITE, CFGMGMTWRITEDATA, CFGMSGTRANSMIT, CFGMSGTRANSMITDATA +, CFGMSGTRANSMITTYPE, CFGMSIXRAMREADDATA, CFGPMASPML1ENTRYREJECT, CFGPMASPMTXL0SENTRYDISABLE, CFGPOWERSTATECHANGEACK, CFGREQPMTRANSITIONL23READY, CFGREVIDPF0, CFGREVIDPF1, CFGREVIDPF2, CFGREVIDPF3, CFGSUBSYSIDPF0, CFGSUBSYSIDPF1, CFGSUBSYSIDPF2, CFGSUBSYSIDPF3, CFGSUBSYSVENDID, CFGTPHRAMREADDATA, CFGVENDID, CFGVFFLRDONE, CFGVFFLRFUNCNUM, CONFMCAPREQUESTBYCONF, CONFREQDATA +, CONFREQREGNUM, CONFREQTYPE, CONFREQVALID, CORECLK, CORECLKMIREPLAYRAM0, CORECLKMIREPLAYRAM1, CORECLKMIRXCOMPLETIONRAM0, CORECLKMIRXCOMPLETIONRAM1, CORECLKMIRXPOSTEDREQUESTRAM0, CORECLKMIRXPOSTEDREQUESTRAM1, DBGSEL0, DBGSEL1, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, MAXISCQTREADY, MAXISRCTREADY, MCAPCLK, MCAPPERST0B +, MCAPPERST1B, MGMTRESETN, MGMTSTICKYRESETN, MIREPLAYRAMERRCOR, MIREPLAYRAMERRUNCOR, MIREPLAYRAMREADDATA0, MIREPLAYRAMREADDATA1, MIRXCOMPLETIONRAMERRCOR, MIRXCOMPLETIONRAMERRUNCOR, MIRXCOMPLETIONRAMREADDATA0, MIRXCOMPLETIONRAMREADDATA1, MIRXPOSTEDREQUESTRAMERRCOR, MIRXPOSTEDREQUESTRAMERRUNCOR, MIRXPOSTEDREQUESTRAMREADDATA0, MIRXPOSTEDREQUESTRAMREADDATA1, PCIECOMPLDELIVERED, PCIECOMPLDELIVEREDTAG0, PCIECOMPLDELIVEREDTAG1, PCIECQNPREQ, PCIECQNPUSERCREDITRCVD, PCIECQPIPELINEEMPTY +, PCIEPOSTEDREQDELIVERED, PIPECLK, PIPECLKEN, PIPEEQFS, PIPEEQLF, PIPERESETN, PIPERX00CHARISK, PIPERX00DATA, PIPERX00DATAVALID, PIPERX00ELECIDLE, PIPERX00EQDONE, PIPERX00EQLPADAPTDONE, PIPERX00EQLPLFFSSEL, PIPERX00EQLPNEWTXCOEFFORPRESET, PIPERX00PHYSTATUS, PIPERX00STARTBLOCK, PIPERX00STATUS, PIPERX00SYNCHEADER, PIPERX00VALID, PIPERX01CHARISK, PIPERX01DATA +, PIPERX01DATAVALID, PIPERX01ELECIDLE, PIPERX01EQDONE, PIPERX01EQLPADAPTDONE, PIPERX01EQLPLFFSSEL, PIPERX01EQLPNEWTXCOEFFORPRESET, PIPERX01PHYSTATUS, PIPERX01STARTBLOCK, PIPERX01STATUS, PIPERX01SYNCHEADER, PIPERX01VALID, PIPERX02CHARISK, PIPERX02DATA, PIPERX02DATAVALID, PIPERX02ELECIDLE, PIPERX02EQDONE, PIPERX02EQLPADAPTDONE, PIPERX02EQLPLFFSSEL, PIPERX02EQLPNEWTXCOEFFORPRESET, PIPERX02PHYSTATUS, PIPERX02STARTBLOCK +, PIPERX02STATUS, PIPERX02SYNCHEADER, PIPERX02VALID, PIPERX03CHARISK, PIPERX03DATA, PIPERX03DATAVALID, PIPERX03ELECIDLE, PIPERX03EQDONE, PIPERX03EQLPADAPTDONE, PIPERX03EQLPLFFSSEL, PIPERX03EQLPNEWTXCOEFFORPRESET, PIPERX03PHYSTATUS, PIPERX03STARTBLOCK, PIPERX03STATUS, PIPERX03SYNCHEADER, PIPERX03VALID, PIPERX04CHARISK, PIPERX04DATA, PIPERX04DATAVALID, PIPERX04ELECIDLE, PIPERX04EQDONE +, PIPERX04EQLPADAPTDONE, PIPERX04EQLPLFFSSEL, PIPERX04EQLPNEWTXCOEFFORPRESET, PIPERX04PHYSTATUS, PIPERX04STARTBLOCK, PIPERX04STATUS, PIPERX04SYNCHEADER, PIPERX04VALID, PIPERX05CHARISK, PIPERX05DATA, PIPERX05DATAVALID, PIPERX05ELECIDLE, PIPERX05EQDONE, PIPERX05EQLPADAPTDONE, PIPERX05EQLPLFFSSEL, PIPERX05EQLPNEWTXCOEFFORPRESET, PIPERX05PHYSTATUS, PIPERX05STARTBLOCK, PIPERX05STATUS, PIPERX05SYNCHEADER, PIPERX05VALID +, PIPERX06CHARISK, PIPERX06DATA, PIPERX06DATAVALID, PIPERX06ELECIDLE, PIPERX06EQDONE, PIPERX06EQLPADAPTDONE, PIPERX06EQLPLFFSSEL, PIPERX06EQLPNEWTXCOEFFORPRESET, PIPERX06PHYSTATUS, PIPERX06STARTBLOCK, PIPERX06STATUS, PIPERX06SYNCHEADER, PIPERX06VALID, PIPERX07CHARISK, PIPERX07DATA, PIPERX07DATAVALID, PIPERX07ELECIDLE, PIPERX07EQDONE, PIPERX07EQLPADAPTDONE, PIPERX07EQLPLFFSSEL, PIPERX07EQLPNEWTXCOEFFORPRESET +, PIPERX07PHYSTATUS, PIPERX07STARTBLOCK, PIPERX07STATUS, PIPERX07SYNCHEADER, PIPERX07VALID, PIPERX08CHARISK, PIPERX08DATA, PIPERX08DATAVALID, PIPERX08ELECIDLE, PIPERX08EQDONE, PIPERX08EQLPADAPTDONE, PIPERX08EQLPLFFSSEL, PIPERX08EQLPNEWTXCOEFFORPRESET, PIPERX08PHYSTATUS, PIPERX08STARTBLOCK, PIPERX08STATUS, PIPERX08SYNCHEADER, PIPERX08VALID, PIPERX09CHARISK, PIPERX09DATA, PIPERX09DATAVALID +, PIPERX09ELECIDLE, PIPERX09EQDONE, PIPERX09EQLPADAPTDONE, PIPERX09EQLPLFFSSEL, PIPERX09EQLPNEWTXCOEFFORPRESET, PIPERX09PHYSTATUS, PIPERX09STARTBLOCK, PIPERX09STATUS, PIPERX09SYNCHEADER, PIPERX09VALID, PIPERX10CHARISK, PIPERX10DATA, PIPERX10DATAVALID, PIPERX10ELECIDLE, PIPERX10EQDONE, PIPERX10EQLPADAPTDONE, PIPERX10EQLPLFFSSEL, PIPERX10EQLPNEWTXCOEFFORPRESET, PIPERX10PHYSTATUS, PIPERX10STARTBLOCK, PIPERX10STATUS +, PIPERX10SYNCHEADER, PIPERX10VALID, PIPERX11CHARISK, PIPERX11DATA, PIPERX11DATAVALID, PIPERX11ELECIDLE, PIPERX11EQDONE, PIPERX11EQLPADAPTDONE, PIPERX11EQLPLFFSSEL, PIPERX11EQLPNEWTXCOEFFORPRESET, PIPERX11PHYSTATUS, PIPERX11STARTBLOCK, PIPERX11STATUS, PIPERX11SYNCHEADER, PIPERX11VALID, PIPERX12CHARISK, PIPERX12DATA, PIPERX12DATAVALID, PIPERX12ELECIDLE, PIPERX12EQDONE, PIPERX12EQLPADAPTDONE +, PIPERX12EQLPLFFSSEL, PIPERX12EQLPNEWTXCOEFFORPRESET, PIPERX12PHYSTATUS, PIPERX12STARTBLOCK, PIPERX12STATUS, PIPERX12SYNCHEADER, PIPERX12VALID, PIPERX13CHARISK, PIPERX13DATA, PIPERX13DATAVALID, PIPERX13ELECIDLE, PIPERX13EQDONE, PIPERX13EQLPADAPTDONE, PIPERX13EQLPLFFSSEL, PIPERX13EQLPNEWTXCOEFFORPRESET, PIPERX13PHYSTATUS, PIPERX13STARTBLOCK, PIPERX13STATUS, PIPERX13SYNCHEADER, PIPERX13VALID, PIPERX14CHARISK +, PIPERX14DATA, PIPERX14DATAVALID, PIPERX14ELECIDLE, PIPERX14EQDONE, PIPERX14EQLPADAPTDONE, PIPERX14EQLPLFFSSEL, PIPERX14EQLPNEWTXCOEFFORPRESET, PIPERX14PHYSTATUS, PIPERX14STARTBLOCK, PIPERX14STATUS, PIPERX14SYNCHEADER, PIPERX14VALID, PIPERX15CHARISK, PIPERX15DATA, PIPERX15DATAVALID, PIPERX15ELECIDLE, PIPERX15EQDONE, PIPERX15EQLPADAPTDONE, PIPERX15EQLPLFFSSEL, PIPERX15EQLPNEWTXCOEFFORPRESET, PIPERX15PHYSTATUS +, PIPERX15STARTBLOCK, PIPERX15STATUS, PIPERX15SYNCHEADER, PIPERX15VALID, PIPETX00EQCOEFF, PIPETX00EQDONE, PIPETX01EQCOEFF, PIPETX01EQDONE, PIPETX02EQCOEFF, PIPETX02EQDONE, PIPETX03EQCOEFF, PIPETX03EQDONE, PIPETX04EQCOEFF, PIPETX04EQDONE, PIPETX05EQCOEFF, PIPETX05EQDONE, PIPETX06EQCOEFF, PIPETX06EQDONE, PIPETX07EQCOEFF, PIPETX07EQDONE, PIPETX08EQCOEFF +, PIPETX08EQDONE, PIPETX09EQCOEFF, PIPETX09EQDONE, PIPETX10EQCOEFF, PIPETX10EQDONE, PIPETX11EQCOEFF, PIPETX11EQDONE, PIPETX12EQCOEFF, PIPETX12EQDONE, PIPETX13EQCOEFF, PIPETX13EQDONE, PIPETX14EQCOEFF, PIPETX14EQDONE, PIPETX15EQCOEFF, PIPETX15EQDONE, PLEQRESETEIEOSCOUNT, PLGEN2UPSTREAMPREFERDEEMPH, PLGEN34REDOEQSPEED, PLGEN34REDOEQUALIZATION, RESETN, SAXISCCTDATA +, SAXISCCTKEEP, SAXISCCTLAST, SAXISCCTUSER, SAXISCCTVALID, SAXISRQTDATA, SAXISRQTKEEP, SAXISRQTLAST, SAXISRQTUSER, SAXISRQTVALID, USERCLK, USERCLK2, USERCLKEN, USERSPAREIN); parameter ARI_CAP_ENABLE = "FALSE"; parameter AUTO_FLR_RESPONSE = "FALSE"; parameter [1:0] AXISTEN_IF_CC_ALIGNMENT_MODE = 2'h0; @@ -25233,7 +25605,41 @@ module PCIE40E4 (...); input [31:0] USERSPAREIN; endmodule -module PCIE4CE4 (...); +module PCIE4CE4(AXIUSEROUT, CCIXTXCREDIT, CFGBUSNUMBER, CFGCURRENTSPEED, CFGERRCOROUT, CFGERRFATALOUT, CFGERRNONFATALOUT, CFGEXTFUNCTIONNUMBER, CFGEXTREADRECEIVED, CFGEXTREGISTERNUMBER, CFGEXTWRITEBYTEENABLE, CFGEXTWRITEDATA, CFGEXTWRITERECEIVED, CFGFCCPLD, CFGFCCPLH, CFGFCNPD, CFGFCNPH, CFGFCPD, CFGFCPH, CFGFLRINPROCESS, CFGFUNCTIONPOWERSTATE +, CFGFUNCTIONSTATUS, CFGHOTRESETOUT, CFGINTERRUPTMSIDATA, CFGINTERRUPTMSIENABLE, CFGINTERRUPTMSIFAIL, CFGINTERRUPTMSIMASKUPDATE, CFGINTERRUPTMSIMMENABLE, CFGINTERRUPTMSISENT, CFGINTERRUPTMSIXENABLE, CFGINTERRUPTMSIXMASK, CFGINTERRUPTMSIXVECPENDINGSTATUS, CFGINTERRUPTSENT, CFGLINKPOWERSTATE, CFGLOCALERROROUT, CFGLOCALERRORVALID, CFGLTRENABLE, CFGLTSSMSTATE, CFGMAXPAYLOAD, CFGMAXREADREQ, CFGMGMTREADDATA, CFGMGMTREADWRITEDONE +, CFGMSGRECEIVED, CFGMSGRECEIVEDDATA, CFGMSGRECEIVEDTYPE, CFGMSGTRANSMITDONE, CFGMSIXRAMADDRESS, CFGMSIXRAMREADENABLE, CFGMSIXRAMWRITEBYTEENABLE, CFGMSIXRAMWRITEDATA, CFGNEGOTIATEDWIDTH, CFGOBFFENABLE, CFGPHYLINKDOWN, CFGPHYLINKSTATUS, CFGPLSTATUSCHANGE, CFGPOWERSTATECHANGEINTERRUPT, CFGRCBSTATUS, CFGRXPMSTATE, CFGTPHRAMADDRESS, CFGTPHRAMREADENABLE, CFGTPHRAMWRITEBYTEENABLE, CFGTPHRAMWRITEDATA, CFGTPHREQUESTERENABLE +, CFGTPHSTMODE, CFGTXPMSTATE, CFGVC1ENABLE, CFGVC1NEGOTIATIONPENDING, CONFMCAPDESIGNSWITCH, CONFMCAPEOS, CONFMCAPINUSEBYPCIE, CONFREQREADY, CONFRESPRDATA, CONFRESPVALID, DBGCCIXOUT, DBGCTRL0OUT, DBGCTRL1OUT, DBGDATA0OUT, DBGDATA1OUT, DRPDO, DRPRDY, MAXISCCIXRXTUSER, MAXISCCIXRXTVALID, MAXISCQTDATA, MAXISCQTKEEP +, MAXISCQTLAST, MAXISCQTUSER, MAXISCQTVALID, MAXISRCTDATA, MAXISRCTKEEP, MAXISRCTLAST, MAXISRCTUSER, MAXISRCTVALID, MIREPLAYRAMADDRESS0, MIREPLAYRAMADDRESS1, MIREPLAYRAMREADENABLE0, MIREPLAYRAMREADENABLE1, MIREPLAYRAMWRITEDATA0, MIREPLAYRAMWRITEDATA1, MIREPLAYRAMWRITEENABLE0, MIREPLAYRAMWRITEENABLE1, MIRXCOMPLETIONRAMREADADDRESS0, MIRXCOMPLETIONRAMREADADDRESS1, MIRXCOMPLETIONRAMREADENABLE0, MIRXCOMPLETIONRAMREADENABLE1, MIRXCOMPLETIONRAMWRITEADDRESS0 +, MIRXCOMPLETIONRAMWRITEADDRESS1, MIRXCOMPLETIONRAMWRITEDATA0, MIRXCOMPLETIONRAMWRITEDATA1, MIRXCOMPLETIONRAMWRITEENABLE0, MIRXCOMPLETIONRAMWRITEENABLE1, MIRXPOSTEDREQUESTRAMREADADDRESS0, MIRXPOSTEDREQUESTRAMREADADDRESS1, MIRXPOSTEDREQUESTRAMREADENABLE0, MIRXPOSTEDREQUESTRAMREADENABLE1, MIRXPOSTEDREQUESTRAMWRITEADDRESS0, MIRXPOSTEDREQUESTRAMWRITEADDRESS1, MIRXPOSTEDREQUESTRAMWRITEDATA0, MIRXPOSTEDREQUESTRAMWRITEDATA1, MIRXPOSTEDREQUESTRAMWRITEENABLE0, MIRXPOSTEDREQUESTRAMWRITEENABLE1, PCIECQNPREQCOUNT, PCIEPERST0B, PCIEPERST1B, PCIERQSEQNUM0, PCIERQSEQNUM1, PCIERQSEQNUMVLD0 +, PCIERQSEQNUMVLD1, PCIERQTAG0, PCIERQTAG1, PCIERQTAGAV, PCIERQTAGVLD0, PCIERQTAGVLD1, PCIETFCNPDAV, PCIETFCNPHAV, PIPERX00EQCONTROL, PIPERX00POLARITY, PIPERX01EQCONTROL, PIPERX01POLARITY, PIPERX02EQCONTROL, PIPERX02POLARITY, PIPERX03EQCONTROL, PIPERX03POLARITY, PIPERX04EQCONTROL, PIPERX04POLARITY, PIPERX05EQCONTROL, PIPERX05POLARITY, PIPERX06EQCONTROL +, PIPERX06POLARITY, PIPERX07EQCONTROL, PIPERX07POLARITY, PIPERX08EQCONTROL, PIPERX08POLARITY, PIPERX09EQCONTROL, PIPERX09POLARITY, PIPERX10EQCONTROL, PIPERX10POLARITY, PIPERX11EQCONTROL, PIPERX11POLARITY, PIPERX12EQCONTROL, PIPERX12POLARITY, PIPERX13EQCONTROL, PIPERX13POLARITY, PIPERX14EQCONTROL, PIPERX14POLARITY, PIPERX15EQCONTROL, PIPERX15POLARITY, PIPERXEQLPLFFS, PIPERXEQLPTXPRESET +, PIPETX00CHARISK, PIPETX00COMPLIANCE, PIPETX00DATA, PIPETX00DATAVALID, PIPETX00ELECIDLE, PIPETX00EQCONTROL, PIPETX00EQDEEMPH, PIPETX00POWERDOWN, PIPETX00STARTBLOCK, PIPETX00SYNCHEADER, PIPETX01CHARISK, PIPETX01COMPLIANCE, PIPETX01DATA, PIPETX01DATAVALID, PIPETX01ELECIDLE, PIPETX01EQCONTROL, PIPETX01EQDEEMPH, PIPETX01POWERDOWN, PIPETX01STARTBLOCK, PIPETX01SYNCHEADER, PIPETX02CHARISK +, PIPETX02COMPLIANCE, PIPETX02DATA, PIPETX02DATAVALID, PIPETX02ELECIDLE, PIPETX02EQCONTROL, PIPETX02EQDEEMPH, PIPETX02POWERDOWN, PIPETX02STARTBLOCK, PIPETX02SYNCHEADER, PIPETX03CHARISK, PIPETX03COMPLIANCE, PIPETX03DATA, PIPETX03DATAVALID, PIPETX03ELECIDLE, PIPETX03EQCONTROL, PIPETX03EQDEEMPH, PIPETX03POWERDOWN, PIPETX03STARTBLOCK, PIPETX03SYNCHEADER, PIPETX04CHARISK, PIPETX04COMPLIANCE +, PIPETX04DATA, PIPETX04DATAVALID, PIPETX04ELECIDLE, PIPETX04EQCONTROL, PIPETX04EQDEEMPH, PIPETX04POWERDOWN, PIPETX04STARTBLOCK, PIPETX04SYNCHEADER, PIPETX05CHARISK, PIPETX05COMPLIANCE, PIPETX05DATA, PIPETX05DATAVALID, PIPETX05ELECIDLE, PIPETX05EQCONTROL, PIPETX05EQDEEMPH, PIPETX05POWERDOWN, PIPETX05STARTBLOCK, PIPETX05SYNCHEADER, PIPETX06CHARISK, PIPETX06COMPLIANCE, PIPETX06DATA +, PIPETX06DATAVALID, PIPETX06ELECIDLE, PIPETX06EQCONTROL, PIPETX06EQDEEMPH, PIPETX06POWERDOWN, PIPETX06STARTBLOCK, PIPETX06SYNCHEADER, PIPETX07CHARISK, PIPETX07COMPLIANCE, PIPETX07DATA, PIPETX07DATAVALID, PIPETX07ELECIDLE, PIPETX07EQCONTROL, PIPETX07EQDEEMPH, PIPETX07POWERDOWN, PIPETX07STARTBLOCK, PIPETX07SYNCHEADER, PIPETX08CHARISK, PIPETX08COMPLIANCE, PIPETX08DATA, PIPETX08DATAVALID +, PIPETX08ELECIDLE, PIPETX08EQCONTROL, PIPETX08EQDEEMPH, PIPETX08POWERDOWN, PIPETX08STARTBLOCK, PIPETX08SYNCHEADER, PIPETX09CHARISK, PIPETX09COMPLIANCE, PIPETX09DATA, PIPETX09DATAVALID, PIPETX09ELECIDLE, PIPETX09EQCONTROL, PIPETX09EQDEEMPH, PIPETX09POWERDOWN, PIPETX09STARTBLOCK, PIPETX09SYNCHEADER, PIPETX10CHARISK, PIPETX10COMPLIANCE, PIPETX10DATA, PIPETX10DATAVALID, PIPETX10ELECIDLE +, PIPETX10EQCONTROL, PIPETX10EQDEEMPH, PIPETX10POWERDOWN, PIPETX10STARTBLOCK, PIPETX10SYNCHEADER, PIPETX11CHARISK, PIPETX11COMPLIANCE, PIPETX11DATA, PIPETX11DATAVALID, PIPETX11ELECIDLE, PIPETX11EQCONTROL, PIPETX11EQDEEMPH, PIPETX11POWERDOWN, PIPETX11STARTBLOCK, PIPETX11SYNCHEADER, PIPETX12CHARISK, PIPETX12COMPLIANCE, PIPETX12DATA, PIPETX12DATAVALID, PIPETX12ELECIDLE, PIPETX12EQCONTROL +, PIPETX12EQDEEMPH, PIPETX12POWERDOWN, PIPETX12STARTBLOCK, PIPETX12SYNCHEADER, PIPETX13CHARISK, PIPETX13COMPLIANCE, PIPETX13DATA, PIPETX13DATAVALID, PIPETX13ELECIDLE, PIPETX13EQCONTROL, PIPETX13EQDEEMPH, PIPETX13POWERDOWN, PIPETX13STARTBLOCK, PIPETX13SYNCHEADER, PIPETX14CHARISK, PIPETX14COMPLIANCE, PIPETX14DATA, PIPETX14DATAVALID, PIPETX14ELECIDLE, PIPETX14EQCONTROL, PIPETX14EQDEEMPH +, PIPETX14POWERDOWN, PIPETX14STARTBLOCK, PIPETX14SYNCHEADER, PIPETX15CHARISK, PIPETX15COMPLIANCE, PIPETX15DATA, PIPETX15DATAVALID, PIPETX15ELECIDLE, PIPETX15EQCONTROL, PIPETX15EQDEEMPH, PIPETX15POWERDOWN, PIPETX15STARTBLOCK, PIPETX15SYNCHEADER, PIPETXDEEMPH, PIPETXMARGIN, PIPETXRATE, PIPETXRCVRDET, PIPETXRESET, PIPETXSWING, PLEQINPROGRESS, PLEQPHASE +, PLGEN34EQMISMATCH, SAXISCCTREADY, SAXISRQTREADY, USERSPAREOUT, AXIUSERIN, CCIXOPTIMIZEDTLPTXANDRXENABLE, CCIXRXCORRECTABLEERRORDETECTED, CCIXRXFIFOOVERFLOW, CCIXRXTLPFORWARDED0, CCIXRXTLPFORWARDED1, CCIXRXTLPFORWARDEDLENGTH0, CCIXRXTLPFORWARDEDLENGTH1, CCIXRXUNCORRECTABLEERRORDETECTED, CFGCONFIGSPACEENABLE, CFGDEVIDPF0, CFGDEVIDPF1, CFGDEVIDPF2, CFGDEVIDPF3, CFGDSBUSNUMBER, CFGDSDEVICENUMBER, CFGDSFUNCTIONNUMBER +, CFGDSN, CFGDSPORTNUMBER, CFGERRCORIN, CFGERRUNCORIN, CFGEXTREADDATA, CFGEXTREADDATAVALID, CFGFCSEL, CFGFCVCSEL, CFGFLRDONE, CFGHOTRESETIN, CFGINTERRUPTINT, CFGINTERRUPTMSIATTR, CFGINTERRUPTMSIFUNCTIONNUMBER, CFGINTERRUPTMSIINT, CFGINTERRUPTMSIPENDINGSTATUS, CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM, CFGINTERRUPTMSISELECT, CFGINTERRUPTMSITPHPRESENT, CFGINTERRUPTMSITPHSTTAG, CFGINTERRUPTMSITPHTYPE +, CFGINTERRUPTMSIXADDRESS, CFGINTERRUPTMSIXDATA, CFGINTERRUPTMSIXINT, CFGINTERRUPTMSIXVECPENDING, CFGINTERRUPTPENDING, CFGLINKTRAININGENABLE, CFGMGMTADDR, CFGMGMTBYTEENABLE, CFGMGMTDEBUGACCESS, CFGMGMTFUNCTIONNUMBER, CFGMGMTREAD, CFGMGMTWRITE, CFGMGMTWRITEDATA, CFGMSGTRANSMIT, CFGMSGTRANSMITDATA, CFGMSGTRANSMITTYPE, CFGMSIXRAMREADDATA, CFGPMASPML1ENTRYREJECT, CFGPMASPMTXL0SENTRYDISABLE, CFGPOWERSTATECHANGEACK, CFGREQPMTRANSITIONL23READY +, CFGREVIDPF0, CFGREVIDPF1, CFGREVIDPF2, CFGREVIDPF3, CFGSUBSYSIDPF0, CFGSUBSYSIDPF1, CFGSUBSYSIDPF2, CFGSUBSYSIDPF3, CFGSUBSYSVENDID, CFGTPHRAMREADDATA, CFGVENDID, CFGVFFLRDONE, CFGVFFLRFUNCNUM, CONFMCAPREQUESTBYCONF, CONFREQDATA, CONFREQREGNUM, CONFREQTYPE, CONFREQVALID, CORECLK, CORECLKCCIX, CORECLKMIREPLAYRAM0 +, CORECLKMIREPLAYRAM1, CORECLKMIRXCOMPLETIONRAM0, CORECLKMIRXCOMPLETIONRAM1, CORECLKMIRXPOSTEDREQUESTRAM0, CORECLKMIRXPOSTEDREQUESTRAM1, DBGSEL0, DBGSEL1, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, MAXISCQTREADY, MAXISRCTREADY, MCAPCLK, MCAPPERST0B, MCAPPERST1B, MGMTRESETN, MGMTSTICKYRESETN, MIREPLAYRAMERRCOR, MIREPLAYRAMERRUNCOR +, MIREPLAYRAMREADDATA0, MIREPLAYRAMREADDATA1, MIRXCOMPLETIONRAMERRCOR, MIRXCOMPLETIONRAMERRUNCOR, MIRXCOMPLETIONRAMREADDATA0, MIRXCOMPLETIONRAMREADDATA1, MIRXPOSTEDREQUESTRAMERRCOR, MIRXPOSTEDREQUESTRAMERRUNCOR, MIRXPOSTEDREQUESTRAMREADDATA0, MIRXPOSTEDREQUESTRAMREADDATA1, PCIECOMPLDELIVERED, PCIECOMPLDELIVEREDTAG0, PCIECOMPLDELIVEREDTAG1, PCIECQNPREQ, PCIECQNPUSERCREDITRCVD, PCIECQPIPELINEEMPTY, PCIEPOSTEDREQDELIVERED, PIPECLK, PIPECLKEN, PIPEEQFS, PIPEEQLF +, PIPERESETN, PIPERX00CHARISK, PIPERX00DATA, PIPERX00DATAVALID, PIPERX00ELECIDLE, PIPERX00EQDONE, PIPERX00EQLPADAPTDONE, PIPERX00EQLPLFFSSEL, PIPERX00EQLPNEWTXCOEFFORPRESET, PIPERX00PHYSTATUS, PIPERX00STARTBLOCK, PIPERX00STATUS, PIPERX00SYNCHEADER, PIPERX00VALID, PIPERX01CHARISK, PIPERX01DATA, PIPERX01DATAVALID, PIPERX01ELECIDLE, PIPERX01EQDONE, PIPERX01EQLPADAPTDONE, PIPERX01EQLPLFFSSEL +, PIPERX01EQLPNEWTXCOEFFORPRESET, PIPERX01PHYSTATUS, PIPERX01STARTBLOCK, PIPERX01STATUS, PIPERX01SYNCHEADER, PIPERX01VALID, PIPERX02CHARISK, PIPERX02DATA, PIPERX02DATAVALID, PIPERX02ELECIDLE, PIPERX02EQDONE, PIPERX02EQLPADAPTDONE, PIPERX02EQLPLFFSSEL, PIPERX02EQLPNEWTXCOEFFORPRESET, PIPERX02PHYSTATUS, PIPERX02STARTBLOCK, PIPERX02STATUS, PIPERX02SYNCHEADER, PIPERX02VALID, PIPERX03CHARISK, PIPERX03DATA +, PIPERX03DATAVALID, PIPERX03ELECIDLE, PIPERX03EQDONE, PIPERX03EQLPADAPTDONE, PIPERX03EQLPLFFSSEL, PIPERX03EQLPNEWTXCOEFFORPRESET, PIPERX03PHYSTATUS, PIPERX03STARTBLOCK, PIPERX03STATUS, PIPERX03SYNCHEADER, PIPERX03VALID, PIPERX04CHARISK, PIPERX04DATA, PIPERX04DATAVALID, PIPERX04ELECIDLE, PIPERX04EQDONE, PIPERX04EQLPADAPTDONE, PIPERX04EQLPLFFSSEL, PIPERX04EQLPNEWTXCOEFFORPRESET, PIPERX04PHYSTATUS, PIPERX04STARTBLOCK +, PIPERX04STATUS, PIPERX04SYNCHEADER, PIPERX04VALID, PIPERX05CHARISK, PIPERX05DATA, PIPERX05DATAVALID, PIPERX05ELECIDLE, PIPERX05EQDONE, PIPERX05EQLPADAPTDONE, PIPERX05EQLPLFFSSEL, PIPERX05EQLPNEWTXCOEFFORPRESET, PIPERX05PHYSTATUS, PIPERX05STARTBLOCK, PIPERX05STATUS, PIPERX05SYNCHEADER, PIPERX05VALID, PIPERX06CHARISK, PIPERX06DATA, PIPERX06DATAVALID, PIPERX06ELECIDLE, PIPERX06EQDONE +, PIPERX06EQLPADAPTDONE, PIPERX06EQLPLFFSSEL, PIPERX06EQLPNEWTXCOEFFORPRESET, PIPERX06PHYSTATUS, PIPERX06STARTBLOCK, PIPERX06STATUS, PIPERX06SYNCHEADER, PIPERX06VALID, PIPERX07CHARISK, PIPERX07DATA, PIPERX07DATAVALID, PIPERX07ELECIDLE, PIPERX07EQDONE, PIPERX07EQLPADAPTDONE, PIPERX07EQLPLFFSSEL, PIPERX07EQLPNEWTXCOEFFORPRESET, PIPERX07PHYSTATUS, PIPERX07STARTBLOCK, PIPERX07STATUS, PIPERX07SYNCHEADER, PIPERX07VALID +, PIPERX08CHARISK, PIPERX08DATA, PIPERX08DATAVALID, PIPERX08ELECIDLE, PIPERX08EQDONE, PIPERX08EQLPADAPTDONE, PIPERX08EQLPLFFSSEL, PIPERX08EQLPNEWTXCOEFFORPRESET, PIPERX08PHYSTATUS, PIPERX08STARTBLOCK, PIPERX08STATUS, PIPERX08SYNCHEADER, PIPERX08VALID, PIPERX09CHARISK, PIPERX09DATA, PIPERX09DATAVALID, PIPERX09ELECIDLE, PIPERX09EQDONE, PIPERX09EQLPADAPTDONE, PIPERX09EQLPLFFSSEL, PIPERX09EQLPNEWTXCOEFFORPRESET +, PIPERX09PHYSTATUS, PIPERX09STARTBLOCK, PIPERX09STATUS, PIPERX09SYNCHEADER, PIPERX09VALID, PIPERX10CHARISK, PIPERX10DATA, PIPERX10DATAVALID, PIPERX10ELECIDLE, PIPERX10EQDONE, PIPERX10EQLPADAPTDONE, PIPERX10EQLPLFFSSEL, PIPERX10EQLPNEWTXCOEFFORPRESET, PIPERX10PHYSTATUS, PIPERX10STARTBLOCK, PIPERX10STATUS, PIPERX10SYNCHEADER, PIPERX10VALID, PIPERX11CHARISK, PIPERX11DATA, PIPERX11DATAVALID +, PIPERX11ELECIDLE, PIPERX11EQDONE, PIPERX11EQLPADAPTDONE, PIPERX11EQLPLFFSSEL, PIPERX11EQLPNEWTXCOEFFORPRESET, PIPERX11PHYSTATUS, PIPERX11STARTBLOCK, PIPERX11STATUS, PIPERX11SYNCHEADER, PIPERX11VALID, PIPERX12CHARISK, PIPERX12DATA, PIPERX12DATAVALID, PIPERX12ELECIDLE, PIPERX12EQDONE, PIPERX12EQLPADAPTDONE, PIPERX12EQLPLFFSSEL, PIPERX12EQLPNEWTXCOEFFORPRESET, PIPERX12PHYSTATUS, PIPERX12STARTBLOCK, PIPERX12STATUS +, PIPERX12SYNCHEADER, PIPERX12VALID, PIPERX13CHARISK, PIPERX13DATA, PIPERX13DATAVALID, PIPERX13ELECIDLE, PIPERX13EQDONE, PIPERX13EQLPADAPTDONE, PIPERX13EQLPLFFSSEL, PIPERX13EQLPNEWTXCOEFFORPRESET, PIPERX13PHYSTATUS, PIPERX13STARTBLOCK, PIPERX13STATUS, PIPERX13SYNCHEADER, PIPERX13VALID, PIPERX14CHARISK, PIPERX14DATA, PIPERX14DATAVALID, PIPERX14ELECIDLE, PIPERX14EQDONE, PIPERX14EQLPADAPTDONE +, PIPERX14EQLPLFFSSEL, PIPERX14EQLPNEWTXCOEFFORPRESET, PIPERX14PHYSTATUS, PIPERX14STARTBLOCK, PIPERX14STATUS, PIPERX14SYNCHEADER, PIPERX14VALID, PIPERX15CHARISK, PIPERX15DATA, PIPERX15DATAVALID, PIPERX15ELECIDLE, PIPERX15EQDONE, PIPERX15EQLPADAPTDONE, PIPERX15EQLPLFFSSEL, PIPERX15EQLPNEWTXCOEFFORPRESET, PIPERX15PHYSTATUS, PIPERX15STARTBLOCK, PIPERX15STATUS, PIPERX15SYNCHEADER, PIPERX15VALID, PIPETX00EQCOEFF +, PIPETX00EQDONE, PIPETX01EQCOEFF, PIPETX01EQDONE, PIPETX02EQCOEFF, PIPETX02EQDONE, PIPETX03EQCOEFF, PIPETX03EQDONE, PIPETX04EQCOEFF, PIPETX04EQDONE, PIPETX05EQCOEFF, PIPETX05EQDONE, PIPETX06EQCOEFF, PIPETX06EQDONE, PIPETX07EQCOEFF, PIPETX07EQDONE, PIPETX08EQCOEFF, PIPETX08EQDONE, PIPETX09EQCOEFF, PIPETX09EQDONE, PIPETX10EQCOEFF, PIPETX10EQDONE +, PIPETX11EQCOEFF, PIPETX11EQDONE, PIPETX12EQCOEFF, PIPETX12EQDONE, PIPETX13EQCOEFF, PIPETX13EQDONE, PIPETX14EQCOEFF, PIPETX14EQDONE, PIPETX15EQCOEFF, PIPETX15EQDONE, PLEQRESETEIEOSCOUNT, PLGEN2UPSTREAMPREFERDEEMPH, PLGEN34REDOEQSPEED, PLGEN34REDOEQUALIZATION, RESETN, SAXISCCIXTXTDATA, SAXISCCIXTXTUSER, SAXISCCIXTXTVALID, SAXISCCTDATA, SAXISCCTKEEP, SAXISCCTLAST +, SAXISCCTUSER, SAXISCCTVALID, SAXISRQTDATA, SAXISRQTKEEP, SAXISRQTLAST, SAXISRQTUSER, SAXISRQTVALID, USERCLK, USERCLK2, USERCLKEN, USERSPAREIN); parameter ARI_CAP_ENABLE = "FALSE"; parameter AUTO_FLR_RESPONSE = "FALSE"; parameter [7:0] AXISTEN_IF_CCIX_RX_CREDIT_LIMIT = 8'h08; @@ -26539,7 +26945,14 @@ module PCIE4CE4 (...); input [31:0] USERSPAREIN; endmodule -module EMAC (...); +module EMAC(DCRHOSTDONEIR, EMAC0CLIENTANINTERRUPT, EMAC0CLIENTRXBADFRAME, EMAC0CLIENTRXCLIENTCLKOUT, EMAC0CLIENTRXDVLD, EMAC0CLIENTRXDVLDMSW, EMAC0CLIENTRXDVREG6, EMAC0CLIENTRXFRAMEDROP, EMAC0CLIENTRXGOODFRAME, EMAC0CLIENTRXSTATSBYTEVLD, EMAC0CLIENTRXSTATSVLD, EMAC0CLIENTTXACK, EMAC0CLIENTTXCLIENTCLKOUT, EMAC0CLIENTTXCOLLISION, EMAC0CLIENTTXGMIIMIICLKOUT, EMAC0CLIENTTXRETRANSMIT, EMAC0CLIENTTXSTATS, EMAC0CLIENTTXSTATSBYTEVLD, EMAC0CLIENTTXSTATSVLD, EMAC0PHYENCOMMAALIGN, EMAC0PHYLOOPBACKMSB +, EMAC0PHYMCLKOUT, EMAC0PHYMDOUT, EMAC0PHYMDTRI, EMAC0PHYMGTRXRESET, EMAC0PHYMGTTXRESET, EMAC0PHYPOWERDOWN, EMAC0PHYSYNCACQSTATUS, EMAC0PHYTXCHARDISPMODE, EMAC0PHYTXCHARDISPVAL, EMAC0PHYTXCHARISK, EMAC0PHYTXCLK, EMAC0PHYTXEN, EMAC0PHYTXER, EMAC1CLIENTANINTERRUPT, EMAC1CLIENTRXBADFRAME, EMAC1CLIENTRXCLIENTCLKOUT, EMAC1CLIENTRXDVLD, EMAC1CLIENTRXDVLDMSW, EMAC1CLIENTRXDVREG6, EMAC1CLIENTRXFRAMEDROP, EMAC1CLIENTRXGOODFRAME +, EMAC1CLIENTRXSTATSBYTEVLD, EMAC1CLIENTRXSTATSVLD, EMAC1CLIENTTXACK, EMAC1CLIENTTXCLIENTCLKOUT, EMAC1CLIENTTXCOLLISION, EMAC1CLIENTTXGMIIMIICLKOUT, EMAC1CLIENTTXRETRANSMIT, EMAC1CLIENTTXSTATS, EMAC1CLIENTTXSTATSBYTEVLD, EMAC1CLIENTTXSTATSVLD, EMAC1PHYENCOMMAALIGN, EMAC1PHYLOOPBACKMSB, EMAC1PHYMCLKOUT, EMAC1PHYMDOUT, EMAC1PHYMDTRI, EMAC1PHYMGTRXRESET, EMAC1PHYMGTTXRESET, EMAC1PHYPOWERDOWN, EMAC1PHYSYNCACQSTATUS, EMAC1PHYTXCHARDISPMODE, EMAC1PHYTXCHARDISPVAL +, EMAC1PHYTXCHARISK, EMAC1PHYTXCLK, EMAC1PHYTXEN, EMAC1PHYTXER, EMACDCRACK, HOSTMIIMRDY, EMACDCRDBUS, EMAC0CLIENTRXD, EMAC1CLIENTRXD, HOSTRDDATA, EMAC0CLIENTRXSTATS, EMAC1CLIENTRXSTATS, EMAC0PHYTXD, EMAC1PHYTXD, CLIENTEMAC0DCMLOCKED, CLIENTEMAC0PAUSEREQ, CLIENTEMAC0RXCLIENTCLKIN, CLIENTEMAC0TXCLIENTCLKIN, CLIENTEMAC0TXDVLD, CLIENTEMAC0TXDVLDMSW, CLIENTEMAC0TXFIRSTBYTE +, CLIENTEMAC0TXGMIIMIICLKIN, CLIENTEMAC0TXUNDERRUN, CLIENTEMAC1DCMLOCKED, CLIENTEMAC1PAUSEREQ, CLIENTEMAC1RXCLIENTCLKIN, CLIENTEMAC1TXCLIENTCLKIN, CLIENTEMAC1TXDVLD, CLIENTEMAC1TXDVLDMSW, CLIENTEMAC1TXFIRSTBYTE, CLIENTEMAC1TXGMIIMIICLKIN, CLIENTEMAC1TXUNDERRUN, DCREMACCLK, DCREMACENABLE, DCREMACREAD, DCREMACWRITE, HOSTCLK, HOSTEMAC1SEL, HOSTMIIMSEL, HOSTREQ, PHYEMAC0COL, PHYEMAC0CRS +, PHYEMAC0GTXCLK, PHYEMAC0MCLKIN, PHYEMAC0MDIN, PHYEMAC0MIITXCLK, PHYEMAC0RXBUFERR, PHYEMAC0RXCHARISCOMMA, PHYEMAC0RXCHARISK, PHYEMAC0RXCHECKINGCRC, PHYEMAC0RXCLK, PHYEMAC0RXCOMMADET, PHYEMAC0RXDISPERR, PHYEMAC0RXDV, PHYEMAC0RXER, PHYEMAC0RXNOTINTABLE, PHYEMAC0RXRUNDISP, PHYEMAC0SIGNALDET, PHYEMAC0TXBUFERR, PHYEMAC1COL, PHYEMAC1CRS, PHYEMAC1GTXCLK, PHYEMAC1MCLKIN +, PHYEMAC1MDIN, PHYEMAC1MIITXCLK, PHYEMAC1RXBUFERR, PHYEMAC1RXCHARISCOMMA, PHYEMAC1RXCHARISK, PHYEMAC1RXCHECKINGCRC, PHYEMAC1RXCLK, PHYEMAC1RXCOMMADET, PHYEMAC1RXDISPERR, PHYEMAC1RXDV, PHYEMAC1RXER, PHYEMAC1RXNOTINTABLE, PHYEMAC1RXRUNDISP, PHYEMAC1SIGNALDET, PHYEMAC1TXBUFERR, RESET, DCREMACDBUS, CLIENTEMAC0PAUSEVAL, CLIENTEMAC0TXD, CLIENTEMAC1PAUSEVAL, CLIENTEMAC1TXD +, HOSTOPCODE, PHYEMAC0RXBUFSTATUS, PHYEMAC0RXLOSSOFSYNC, PHYEMAC1RXBUFSTATUS, PHYEMAC1RXLOSSOFSYNC, PHYEMAC0RXCLKCORCNT, PHYEMAC1RXCLKCORCNT, HOSTWRDATA, TIEEMAC0UNICASTADDR, TIEEMAC1UNICASTADDR, PHYEMAC0PHYAD, PHYEMAC1PHYAD, TIEEMAC0CONFIGVEC, TIEEMAC1CONFIGVEC, CLIENTEMAC0TXIFGDELAY, CLIENTEMAC1TXIFGDELAY, PHYEMAC0RXD, PHYEMAC1RXD, DCREMACABUS, HOSTADDR); parameter EMAC0_MODE = "RGMII"; parameter EMAC1_MODE = "RGMII"; output DCRHOSTDONEIR; @@ -26711,7 +27124,14 @@ module EMAC (...); input [9:0] HOSTADDR; endmodule -module TEMAC (...); +module TEMAC(DCRHOSTDONEIR, EMAC0CLIENTANINTERRUPT, EMAC0CLIENTRXBADFRAME, EMAC0CLIENTRXCLIENTCLKOUT, EMAC0CLIENTRXDVLD, EMAC0CLIENTRXDVLDMSW, EMAC0CLIENTRXFRAMEDROP, EMAC0CLIENTRXGOODFRAME, EMAC0CLIENTRXSTATSBYTEVLD, EMAC0CLIENTRXSTATSVLD, EMAC0CLIENTTXACK, EMAC0CLIENTTXCLIENTCLKOUT, EMAC0CLIENTTXCOLLISION, EMAC0CLIENTTXRETRANSMIT, EMAC0CLIENTTXSTATS, EMAC0CLIENTTXSTATSBYTEVLD, EMAC0CLIENTTXSTATSVLD, EMAC0PHYENCOMMAALIGN, EMAC0PHYLOOPBACKMSB, EMAC0PHYMCLKOUT, EMAC0PHYMDOUT +, EMAC0PHYMDTRI, EMAC0PHYMGTRXRESET, EMAC0PHYMGTTXRESET, EMAC0PHYPOWERDOWN, EMAC0PHYSYNCACQSTATUS, EMAC0PHYTXCHARDISPMODE, EMAC0PHYTXCHARDISPVAL, EMAC0PHYTXCHARISK, EMAC0PHYTXCLK, EMAC0PHYTXEN, EMAC0PHYTXER, EMAC0PHYTXGMIIMIICLKOUT, EMAC0SPEEDIS10100, EMAC1CLIENTANINTERRUPT, EMAC1CLIENTRXBADFRAME, EMAC1CLIENTRXCLIENTCLKOUT, EMAC1CLIENTRXDVLD, EMAC1CLIENTRXDVLDMSW, EMAC1CLIENTRXFRAMEDROP, EMAC1CLIENTRXGOODFRAME, EMAC1CLIENTRXSTATSBYTEVLD +, EMAC1CLIENTRXSTATSVLD, EMAC1CLIENTTXACK, EMAC1CLIENTTXCLIENTCLKOUT, EMAC1CLIENTTXCOLLISION, EMAC1CLIENTTXRETRANSMIT, EMAC1CLIENTTXSTATS, EMAC1CLIENTTXSTATSBYTEVLD, EMAC1CLIENTTXSTATSVLD, EMAC1PHYENCOMMAALIGN, EMAC1PHYLOOPBACKMSB, EMAC1PHYMCLKOUT, EMAC1PHYMDOUT, EMAC1PHYMDTRI, EMAC1PHYMGTRXRESET, EMAC1PHYMGTTXRESET, EMAC1PHYPOWERDOWN, EMAC1PHYSYNCACQSTATUS, EMAC1PHYTXCHARDISPMODE, EMAC1PHYTXCHARDISPVAL, EMAC1PHYTXCHARISK, EMAC1PHYTXCLK +, EMAC1PHYTXEN, EMAC1PHYTXER, EMAC1PHYTXGMIIMIICLKOUT, EMAC1SPEEDIS10100, EMACDCRACK, HOSTMIIMRDY, EMACDCRDBUS, EMAC0CLIENTRXD, EMAC1CLIENTRXD, HOSTRDDATA, EMAC0CLIENTRXSTATS, EMAC1CLIENTRXSTATS, EMAC0PHYTXD, EMAC1PHYTXD, CLIENTEMAC0DCMLOCKED, CLIENTEMAC0PAUSEREQ, CLIENTEMAC0RXCLIENTCLKIN, CLIENTEMAC0TXCLIENTCLKIN, CLIENTEMAC0TXDVLD, CLIENTEMAC0TXDVLDMSW, CLIENTEMAC0TXFIRSTBYTE +, CLIENTEMAC0TXUNDERRUN, CLIENTEMAC1DCMLOCKED, CLIENTEMAC1PAUSEREQ, CLIENTEMAC1RXCLIENTCLKIN, CLIENTEMAC1TXCLIENTCLKIN, CLIENTEMAC1TXDVLD, CLIENTEMAC1TXDVLDMSW, CLIENTEMAC1TXFIRSTBYTE, CLIENTEMAC1TXUNDERRUN, DCREMACCLK, DCREMACENABLE, DCREMACREAD, DCREMACWRITE, HOSTCLK, HOSTEMAC1SEL, HOSTMIIMSEL, HOSTREQ, PHYEMAC0COL, PHYEMAC0CRS, PHYEMAC0GTXCLK, PHYEMAC0MCLKIN +, PHYEMAC0MDIN, PHYEMAC0MIITXCLK, PHYEMAC0RXBUFERR, PHYEMAC0RXCHARISCOMMA, PHYEMAC0RXCHARISK, PHYEMAC0RXCHECKINGCRC, PHYEMAC0RXCLK, PHYEMAC0RXCOMMADET, PHYEMAC0RXDISPERR, PHYEMAC0RXDV, PHYEMAC0RXER, PHYEMAC0RXNOTINTABLE, PHYEMAC0RXRUNDISP, PHYEMAC0SIGNALDET, PHYEMAC0TXBUFERR, PHYEMAC0TXGMIIMIICLKIN, PHYEMAC1COL, PHYEMAC1CRS, PHYEMAC1GTXCLK, PHYEMAC1MCLKIN, PHYEMAC1MDIN +, PHYEMAC1MIITXCLK, PHYEMAC1RXBUFERR, PHYEMAC1RXCHARISCOMMA, PHYEMAC1RXCHARISK, PHYEMAC1RXCHECKINGCRC, PHYEMAC1RXCLK, PHYEMAC1RXCOMMADET, PHYEMAC1RXDISPERR, PHYEMAC1RXDV, PHYEMAC1RXER, PHYEMAC1RXNOTINTABLE, PHYEMAC1RXRUNDISP, PHYEMAC1SIGNALDET, PHYEMAC1TXBUFERR, PHYEMAC1TXGMIIMIICLKIN, RESET, DCREMACDBUS, DCREMACABUS, CLIENTEMAC0PAUSEVAL, CLIENTEMAC0TXD, CLIENTEMAC1PAUSEVAL +, CLIENTEMAC1TXD, HOSTOPCODE, PHYEMAC0RXBUFSTATUS, PHYEMAC0RXLOSSOFSYNC, PHYEMAC1RXBUFSTATUS, PHYEMAC1RXLOSSOFSYNC, PHYEMAC0RXCLKCORCNT, PHYEMAC1RXCLKCORCNT, HOSTWRDATA, PHYEMAC0PHYAD, PHYEMAC1PHYAD, CLIENTEMAC0TXIFGDELAY, CLIENTEMAC1TXIFGDELAY, PHYEMAC0RXD, PHYEMAC1RXD, HOSTADDR); parameter EMAC0_1000BASEX_ENABLE = "FALSE"; parameter EMAC0_ADDRFILTER_ENABLE = "FALSE"; parameter EMAC0_BYTEPHY = "FALSE"; @@ -26957,7 +27377,11 @@ module TEMAC (...); input [9:0] HOSTADDR; endmodule -module TEMAC_SINGLE (...); +module TEMAC_SINGLE(DCRHOSTDONEIR, EMACCLIENTANINTERRUPT, EMACCLIENTRXBADFRAME, EMACCLIENTRXCLIENTCLKOUT, EMACCLIENTRXDVLD, EMACCLIENTRXDVLDMSW, EMACCLIENTRXFRAMEDROP, EMACCLIENTRXGOODFRAME, EMACCLIENTRXSTATSBYTEVLD, EMACCLIENTRXSTATSVLD, EMACCLIENTTXACK, EMACCLIENTTXCLIENTCLKOUT, EMACCLIENTTXCOLLISION, EMACCLIENTTXRETRANSMIT, EMACCLIENTTXSTATS, EMACCLIENTTXSTATSBYTEVLD, EMACCLIENTTXSTATSVLD, EMACDCRACK, EMACPHYENCOMMAALIGN, EMACPHYLOOPBACKMSB, EMACPHYMCLKOUT +, EMACPHYMDOUT, EMACPHYMDTRI, EMACPHYMGTRXRESET, EMACPHYMGTTXRESET, EMACPHYPOWERDOWN, EMACPHYSYNCACQSTATUS, EMACPHYTXCHARDISPMODE, EMACPHYTXCHARDISPVAL, EMACPHYTXCHARISK, EMACPHYTXCLK, EMACPHYTXEN, EMACPHYTXER, EMACPHYTXGMIIMIICLKOUT, EMACSPEEDIS10100, HOSTMIIMRDY, EMACDCRDBUS, EMACCLIENTRXD, HOSTRDDATA, EMACCLIENTRXSTATS, EMACPHYTXD, CLIENTEMACDCMLOCKED +, CLIENTEMACPAUSEREQ, CLIENTEMACRXCLIENTCLKIN, CLIENTEMACTXCLIENTCLKIN, CLIENTEMACTXDVLD, CLIENTEMACTXDVLDMSW, CLIENTEMACTXFIRSTBYTE, CLIENTEMACTXUNDERRUN, DCREMACCLK, DCREMACENABLE, DCREMACREAD, DCREMACWRITE, HOSTCLK, HOSTMIIMSEL, HOSTREQ, PHYEMACCOL, PHYEMACCRS, PHYEMACGTXCLK, PHYEMACMCLKIN, PHYEMACMDIN, PHYEMACMIITXCLK, PHYEMACRXCHARISCOMMA +, PHYEMACRXCHARISK, PHYEMACRXCLK, PHYEMACRXDISPERR, PHYEMACRXDV, PHYEMACRXER, PHYEMACRXNOTINTABLE, PHYEMACRXRUNDISP, PHYEMACSIGNALDET, PHYEMACTXBUFERR, PHYEMACTXGMIIMIICLKIN, RESET, DCREMACDBUS, DCREMACABUS, CLIENTEMACPAUSEVAL, CLIENTEMACTXD, HOSTOPCODE, PHYEMACRXBUFSTATUS, PHYEMACRXCLKCORCNT, HOSTWRDATA, PHYEMACPHYAD, CLIENTEMACTXIFGDELAY +, PHYEMACRXD, HOSTADDR); parameter EMAC_1000BASEX_ENABLE = "FALSE"; parameter EMAC_ADDRFILTER_ENABLE = "FALSE"; parameter EMAC_BYTEPHY = "FALSE"; @@ -27088,7 +27512,24 @@ module TEMAC_SINGLE (...); input [9:0] HOSTADDR; endmodule -module CMAC (...); +module CMAC(DRP_DO, DRP_RDY, RX_DATAOUT0, RX_DATAOUT1, RX_DATAOUT2, RX_DATAOUT3, RX_ENAOUT0, RX_ENAOUT1, RX_ENAOUT2, RX_ENAOUT3, RX_EOPOUT0, RX_EOPOUT1, RX_EOPOUT2, RX_EOPOUT3, RX_ERROUT0, RX_ERROUT1, RX_ERROUT2, RX_ERROUT3, RX_LANE_ALIGNER_FILL_0, RX_LANE_ALIGNER_FILL_1, RX_LANE_ALIGNER_FILL_10 +, RX_LANE_ALIGNER_FILL_11, RX_LANE_ALIGNER_FILL_12, RX_LANE_ALIGNER_FILL_13, RX_LANE_ALIGNER_FILL_14, RX_LANE_ALIGNER_FILL_15, RX_LANE_ALIGNER_FILL_16, RX_LANE_ALIGNER_FILL_17, RX_LANE_ALIGNER_FILL_18, RX_LANE_ALIGNER_FILL_19, RX_LANE_ALIGNER_FILL_2, RX_LANE_ALIGNER_FILL_3, RX_LANE_ALIGNER_FILL_4, RX_LANE_ALIGNER_FILL_5, RX_LANE_ALIGNER_FILL_6, RX_LANE_ALIGNER_FILL_7, RX_LANE_ALIGNER_FILL_8, RX_LANE_ALIGNER_FILL_9, RX_MTYOUT0, RX_MTYOUT1, RX_MTYOUT2, RX_MTYOUT3 +, RX_PTP_PCSLANE_OUT, RX_PTP_TSTAMP_OUT, RX_SOPOUT0, RX_SOPOUT1, RX_SOPOUT2, RX_SOPOUT3, STAT_RX_ALIGNED, STAT_RX_ALIGNED_ERR, STAT_RX_BAD_CODE, STAT_RX_BAD_FCS, STAT_RX_BAD_PREAMBLE, STAT_RX_BAD_SFD, STAT_RX_BIP_ERR_0, STAT_RX_BIP_ERR_1, STAT_RX_BIP_ERR_10, STAT_RX_BIP_ERR_11, STAT_RX_BIP_ERR_12, STAT_RX_BIP_ERR_13, STAT_RX_BIP_ERR_14, STAT_RX_BIP_ERR_15, STAT_RX_BIP_ERR_16 +, STAT_RX_BIP_ERR_17, STAT_RX_BIP_ERR_18, STAT_RX_BIP_ERR_19, STAT_RX_BIP_ERR_2, STAT_RX_BIP_ERR_3, STAT_RX_BIP_ERR_4, STAT_RX_BIP_ERR_5, STAT_RX_BIP_ERR_6, STAT_RX_BIP_ERR_7, STAT_RX_BIP_ERR_8, STAT_RX_BIP_ERR_9, STAT_RX_BLOCK_LOCK, STAT_RX_BROADCAST, STAT_RX_FRAGMENT, STAT_RX_FRAMING_ERR_0, STAT_RX_FRAMING_ERR_1, STAT_RX_FRAMING_ERR_10, STAT_RX_FRAMING_ERR_11, STAT_RX_FRAMING_ERR_12, STAT_RX_FRAMING_ERR_13, STAT_RX_FRAMING_ERR_14 +, STAT_RX_FRAMING_ERR_15, STAT_RX_FRAMING_ERR_16, STAT_RX_FRAMING_ERR_17, STAT_RX_FRAMING_ERR_18, STAT_RX_FRAMING_ERR_19, STAT_RX_FRAMING_ERR_2, STAT_RX_FRAMING_ERR_3, STAT_RX_FRAMING_ERR_4, STAT_RX_FRAMING_ERR_5, STAT_RX_FRAMING_ERR_6, STAT_RX_FRAMING_ERR_7, STAT_RX_FRAMING_ERR_8, STAT_RX_FRAMING_ERR_9, STAT_RX_FRAMING_ERR_VALID_0, STAT_RX_FRAMING_ERR_VALID_1, STAT_RX_FRAMING_ERR_VALID_10, STAT_RX_FRAMING_ERR_VALID_11, STAT_RX_FRAMING_ERR_VALID_12, STAT_RX_FRAMING_ERR_VALID_13, STAT_RX_FRAMING_ERR_VALID_14, STAT_RX_FRAMING_ERR_VALID_15 +, STAT_RX_FRAMING_ERR_VALID_16, STAT_RX_FRAMING_ERR_VALID_17, STAT_RX_FRAMING_ERR_VALID_18, STAT_RX_FRAMING_ERR_VALID_19, STAT_RX_FRAMING_ERR_VALID_2, STAT_RX_FRAMING_ERR_VALID_3, STAT_RX_FRAMING_ERR_VALID_4, STAT_RX_FRAMING_ERR_VALID_5, STAT_RX_FRAMING_ERR_VALID_6, STAT_RX_FRAMING_ERR_VALID_7, STAT_RX_FRAMING_ERR_VALID_8, STAT_RX_FRAMING_ERR_VALID_9, STAT_RX_GOT_SIGNAL_OS, STAT_RX_HI_BER, STAT_RX_INRANGEERR, STAT_RX_INTERNAL_LOCAL_FAULT, STAT_RX_JABBER, STAT_RX_LANE0_VLM_BIP7, STAT_RX_LANE0_VLM_BIP7_VALID, STAT_RX_LOCAL_FAULT, STAT_RX_MF_ERR +, STAT_RX_MF_LEN_ERR, STAT_RX_MF_REPEAT_ERR, STAT_RX_MISALIGNED, STAT_RX_MULTICAST, STAT_RX_OVERSIZE, STAT_RX_PACKET_1024_1518_BYTES, STAT_RX_PACKET_128_255_BYTES, STAT_RX_PACKET_1519_1522_BYTES, STAT_RX_PACKET_1523_1548_BYTES, STAT_RX_PACKET_1549_2047_BYTES, STAT_RX_PACKET_2048_4095_BYTES, STAT_RX_PACKET_256_511_BYTES, STAT_RX_PACKET_4096_8191_BYTES, STAT_RX_PACKET_512_1023_BYTES, STAT_RX_PACKET_64_BYTES, STAT_RX_PACKET_65_127_BYTES, STAT_RX_PACKET_8192_9215_BYTES, STAT_RX_PACKET_BAD_FCS, STAT_RX_PACKET_LARGE, STAT_RX_PACKET_SMALL, STAT_RX_PAUSE +, STAT_RX_PAUSE_QUANTA0, STAT_RX_PAUSE_QUANTA1, STAT_RX_PAUSE_QUANTA2, STAT_RX_PAUSE_QUANTA3, STAT_RX_PAUSE_QUANTA4, STAT_RX_PAUSE_QUANTA5, STAT_RX_PAUSE_QUANTA6, STAT_RX_PAUSE_QUANTA7, STAT_RX_PAUSE_QUANTA8, STAT_RX_PAUSE_REQ, STAT_RX_PAUSE_VALID, STAT_RX_RECEIVED_LOCAL_FAULT, STAT_RX_REMOTE_FAULT, STAT_RX_STATUS, STAT_RX_STOMPED_FCS, STAT_RX_SYNCED, STAT_RX_SYNCED_ERR, STAT_RX_TEST_PATTERN_MISMATCH, STAT_RX_TOOLONG, STAT_RX_TOTAL_BYTES, STAT_RX_TOTAL_GOOD_BYTES +, STAT_RX_TOTAL_GOOD_PACKETS, STAT_RX_TOTAL_PACKETS, STAT_RX_TRUNCATED, STAT_RX_UNDERSIZE, STAT_RX_UNICAST, STAT_RX_USER_PAUSE, STAT_RX_VLAN, STAT_RX_VL_DEMUXED, STAT_RX_VL_NUMBER_0, STAT_RX_VL_NUMBER_1, STAT_RX_VL_NUMBER_10, STAT_RX_VL_NUMBER_11, STAT_RX_VL_NUMBER_12, STAT_RX_VL_NUMBER_13, STAT_RX_VL_NUMBER_14, STAT_RX_VL_NUMBER_15, STAT_RX_VL_NUMBER_16, STAT_RX_VL_NUMBER_17, STAT_RX_VL_NUMBER_18, STAT_RX_VL_NUMBER_19, STAT_RX_VL_NUMBER_2 +, STAT_RX_VL_NUMBER_3, STAT_RX_VL_NUMBER_4, STAT_RX_VL_NUMBER_5, STAT_RX_VL_NUMBER_6, STAT_RX_VL_NUMBER_7, STAT_RX_VL_NUMBER_8, STAT_RX_VL_NUMBER_9, STAT_TX_BAD_FCS, STAT_TX_BROADCAST, STAT_TX_FRAME_ERROR, STAT_TX_LOCAL_FAULT, STAT_TX_MULTICAST, STAT_TX_PACKET_1024_1518_BYTES, STAT_TX_PACKET_128_255_BYTES, STAT_TX_PACKET_1519_1522_BYTES, STAT_TX_PACKET_1523_1548_BYTES, STAT_TX_PACKET_1549_2047_BYTES, STAT_TX_PACKET_2048_4095_BYTES, STAT_TX_PACKET_256_511_BYTES, STAT_TX_PACKET_4096_8191_BYTES, STAT_TX_PACKET_512_1023_BYTES +, STAT_TX_PACKET_64_BYTES, STAT_TX_PACKET_65_127_BYTES, STAT_TX_PACKET_8192_9215_BYTES, STAT_TX_PACKET_LARGE, STAT_TX_PACKET_SMALL, STAT_TX_PAUSE, STAT_TX_PAUSE_VALID, STAT_TX_PTP_FIFO_READ_ERROR, STAT_TX_PTP_FIFO_WRITE_ERROR, STAT_TX_TOTAL_BYTES, STAT_TX_TOTAL_GOOD_BYTES, STAT_TX_TOTAL_GOOD_PACKETS, STAT_TX_TOTAL_PACKETS, STAT_TX_UNICAST, STAT_TX_USER_PAUSE, STAT_TX_VLAN, TX_OVFOUT, TX_PTP_PCSLANE_OUT, TX_PTP_TSTAMP_OUT, TX_PTP_TSTAMP_TAG_OUT, TX_PTP_TSTAMP_VALID_OUT +, TX_RDYOUT, TX_SERDES_ALT_DATA0, TX_SERDES_ALT_DATA1, TX_SERDES_ALT_DATA2, TX_SERDES_ALT_DATA3, TX_SERDES_DATA0, TX_SERDES_DATA1, TX_SERDES_DATA2, TX_SERDES_DATA3, TX_SERDES_DATA4, TX_SERDES_DATA5, TX_SERDES_DATA6, TX_SERDES_DATA7, TX_SERDES_DATA8, TX_SERDES_DATA9, TX_UNFOUT, CTL_CAUI4_MODE, CTL_RX_CHECK_ETYPE_GCP, CTL_RX_CHECK_ETYPE_GPP, CTL_RX_CHECK_ETYPE_PCP, CTL_RX_CHECK_ETYPE_PPP +, CTL_RX_CHECK_MCAST_GCP, CTL_RX_CHECK_MCAST_GPP, CTL_RX_CHECK_MCAST_PCP, CTL_RX_CHECK_MCAST_PPP, CTL_RX_CHECK_OPCODE_GCP, CTL_RX_CHECK_OPCODE_GPP, CTL_RX_CHECK_OPCODE_PCP, CTL_RX_CHECK_OPCODE_PPP, CTL_RX_CHECK_SA_GCP, CTL_RX_CHECK_SA_GPP, CTL_RX_CHECK_SA_PCP, CTL_RX_CHECK_SA_PPP, CTL_RX_CHECK_UCAST_GCP, CTL_RX_CHECK_UCAST_GPP, CTL_RX_CHECK_UCAST_PCP, CTL_RX_CHECK_UCAST_PPP, CTL_RX_ENABLE, CTL_RX_ENABLE_GCP, CTL_RX_ENABLE_GPP, CTL_RX_ENABLE_PCP, CTL_RX_ENABLE_PPP +, CTL_RX_FORCE_RESYNC, CTL_RX_PAUSE_ACK, CTL_RX_PAUSE_ENABLE, CTL_RX_SYSTEMTIMERIN, CTL_RX_TEST_PATTERN, CTL_TX_ENABLE, CTL_TX_LANE0_VLM_BIP7_OVERRIDE, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE, CTL_TX_PAUSE_ENABLE, CTL_TX_PAUSE_QUANTA0, CTL_TX_PAUSE_QUANTA1, CTL_TX_PAUSE_QUANTA2, CTL_TX_PAUSE_QUANTA3, CTL_TX_PAUSE_QUANTA4, CTL_TX_PAUSE_QUANTA5, CTL_TX_PAUSE_QUANTA6, CTL_TX_PAUSE_QUANTA7, CTL_TX_PAUSE_QUANTA8, CTL_TX_PAUSE_REFRESH_TIMER0, CTL_TX_PAUSE_REFRESH_TIMER1, CTL_TX_PAUSE_REFRESH_TIMER2 +, CTL_TX_PAUSE_REFRESH_TIMER3, CTL_TX_PAUSE_REFRESH_TIMER4, CTL_TX_PAUSE_REFRESH_TIMER5, CTL_TX_PAUSE_REFRESH_TIMER6, CTL_TX_PAUSE_REFRESH_TIMER7, CTL_TX_PAUSE_REFRESH_TIMER8, CTL_TX_PAUSE_REQ, CTL_TX_PTP_VLANE_ADJUST_MODE, CTL_TX_RESEND_PAUSE, CTL_TX_SEND_IDLE, CTL_TX_SEND_RFI, CTL_TX_SYSTEMTIMERIN, CTL_TX_TEST_PATTERN, DRP_ADDR, DRP_CLK, DRP_DI, DRP_EN, DRP_WE, RX_CLK, RX_RESET, RX_SERDES_ALT_DATA0 +, RX_SERDES_ALT_DATA1, RX_SERDES_ALT_DATA2, RX_SERDES_ALT_DATA3, RX_SERDES_CLK, RX_SERDES_DATA0, RX_SERDES_DATA1, RX_SERDES_DATA2, RX_SERDES_DATA3, RX_SERDES_DATA4, RX_SERDES_DATA5, RX_SERDES_DATA6, RX_SERDES_DATA7, RX_SERDES_DATA8, RX_SERDES_DATA9, RX_SERDES_RESET, TX_CLK, TX_DATAIN0, TX_DATAIN1, TX_DATAIN2, TX_DATAIN3, TX_ENAIN0 +, TX_ENAIN1, TX_ENAIN2, TX_ENAIN3, TX_EOPIN0, TX_EOPIN1, TX_EOPIN2, TX_EOPIN3, TX_ERRIN0, TX_ERRIN1, TX_ERRIN2, TX_ERRIN3, TX_MTYIN0, TX_MTYIN1, TX_MTYIN2, TX_MTYIN3, TX_PTP_1588OP_IN, TX_PTP_CHKSUM_OFFSET_IN, TX_PTP_RXTSTAMP_IN, TX_PTP_TAG_FIELD_IN, TX_PTP_TSTAMP_OFFSET_IN, TX_PTP_UPD_CHKSUM_IN +, TX_RESET, TX_SOPIN0, TX_SOPIN1, TX_SOPIN2, TX_SOPIN3); parameter CTL_PTP_TRANSPCLK_MODE = "FALSE"; parameter CTL_RX_CHECK_ACK = "TRUE"; parameter CTL_RX_CHECK_PREAMBLE = "FALSE"; @@ -27533,7 +27974,26 @@ module CMAC (...); input TX_SOPIN3; endmodule -module CMACE4 (...); +module CMACE4(DRP_DO, DRP_RDY, RSFEC_BYPASS_RX_DOUT, RSFEC_BYPASS_RX_DOUT_CW_START, RSFEC_BYPASS_RX_DOUT_VALID, RSFEC_BYPASS_TX_DOUT, RSFEC_BYPASS_TX_DOUT_CW_START, RSFEC_BYPASS_TX_DOUT_VALID, RX_DATAOUT0, RX_DATAOUT1, RX_DATAOUT2, RX_DATAOUT3, RX_ENAOUT0, RX_ENAOUT1, RX_ENAOUT2, RX_ENAOUT3, RX_EOPOUT0, RX_EOPOUT1, RX_EOPOUT2, RX_EOPOUT3, RX_ERROUT0 +, RX_ERROUT1, RX_ERROUT2, RX_ERROUT3, RX_LANE_ALIGNER_FILL_0, RX_LANE_ALIGNER_FILL_1, RX_LANE_ALIGNER_FILL_10, RX_LANE_ALIGNER_FILL_11, RX_LANE_ALIGNER_FILL_12, RX_LANE_ALIGNER_FILL_13, RX_LANE_ALIGNER_FILL_14, RX_LANE_ALIGNER_FILL_15, RX_LANE_ALIGNER_FILL_16, RX_LANE_ALIGNER_FILL_17, RX_LANE_ALIGNER_FILL_18, RX_LANE_ALIGNER_FILL_19, RX_LANE_ALIGNER_FILL_2, RX_LANE_ALIGNER_FILL_3, RX_LANE_ALIGNER_FILL_4, RX_LANE_ALIGNER_FILL_5, RX_LANE_ALIGNER_FILL_6, RX_LANE_ALIGNER_FILL_7 +, RX_LANE_ALIGNER_FILL_8, RX_LANE_ALIGNER_FILL_9, RX_MTYOUT0, RX_MTYOUT1, RX_MTYOUT2, RX_MTYOUT3, RX_OTN_BIP8_0, RX_OTN_BIP8_1, RX_OTN_BIP8_2, RX_OTN_BIP8_3, RX_OTN_BIP8_4, RX_OTN_DATA_0, RX_OTN_DATA_1, RX_OTN_DATA_2, RX_OTN_DATA_3, RX_OTN_DATA_4, RX_OTN_ENA, RX_OTN_LANE0, RX_OTN_VLMARKER, RX_PREOUT, RX_PTP_PCSLANE_OUT +, RX_PTP_TSTAMP_OUT, RX_SOPOUT0, RX_SOPOUT1, RX_SOPOUT2, RX_SOPOUT3, STAT_RX_ALIGNED, STAT_RX_ALIGNED_ERR, STAT_RX_BAD_CODE, STAT_RX_BAD_FCS, STAT_RX_BAD_PREAMBLE, STAT_RX_BAD_SFD, STAT_RX_BIP_ERR_0, STAT_RX_BIP_ERR_1, STAT_RX_BIP_ERR_10, STAT_RX_BIP_ERR_11, STAT_RX_BIP_ERR_12, STAT_RX_BIP_ERR_13, STAT_RX_BIP_ERR_14, STAT_RX_BIP_ERR_15, STAT_RX_BIP_ERR_16, STAT_RX_BIP_ERR_17 +, STAT_RX_BIP_ERR_18, STAT_RX_BIP_ERR_19, STAT_RX_BIP_ERR_2, STAT_RX_BIP_ERR_3, STAT_RX_BIP_ERR_4, STAT_RX_BIP_ERR_5, STAT_RX_BIP_ERR_6, STAT_RX_BIP_ERR_7, STAT_RX_BIP_ERR_8, STAT_RX_BIP_ERR_9, STAT_RX_BLOCK_LOCK, STAT_RX_BROADCAST, STAT_RX_FRAGMENT, STAT_RX_FRAMING_ERR_0, STAT_RX_FRAMING_ERR_1, STAT_RX_FRAMING_ERR_10, STAT_RX_FRAMING_ERR_11, STAT_RX_FRAMING_ERR_12, STAT_RX_FRAMING_ERR_13, STAT_RX_FRAMING_ERR_14, STAT_RX_FRAMING_ERR_15 +, STAT_RX_FRAMING_ERR_16, STAT_RX_FRAMING_ERR_17, STAT_RX_FRAMING_ERR_18, STAT_RX_FRAMING_ERR_19, STAT_RX_FRAMING_ERR_2, STAT_RX_FRAMING_ERR_3, STAT_RX_FRAMING_ERR_4, STAT_RX_FRAMING_ERR_5, STAT_RX_FRAMING_ERR_6, STAT_RX_FRAMING_ERR_7, STAT_RX_FRAMING_ERR_8, STAT_RX_FRAMING_ERR_9, STAT_RX_FRAMING_ERR_VALID_0, STAT_RX_FRAMING_ERR_VALID_1, STAT_RX_FRAMING_ERR_VALID_10, STAT_RX_FRAMING_ERR_VALID_11, STAT_RX_FRAMING_ERR_VALID_12, STAT_RX_FRAMING_ERR_VALID_13, STAT_RX_FRAMING_ERR_VALID_14, STAT_RX_FRAMING_ERR_VALID_15, STAT_RX_FRAMING_ERR_VALID_16 +, STAT_RX_FRAMING_ERR_VALID_17, STAT_RX_FRAMING_ERR_VALID_18, STAT_RX_FRAMING_ERR_VALID_19, STAT_RX_FRAMING_ERR_VALID_2, STAT_RX_FRAMING_ERR_VALID_3, STAT_RX_FRAMING_ERR_VALID_4, STAT_RX_FRAMING_ERR_VALID_5, STAT_RX_FRAMING_ERR_VALID_6, STAT_RX_FRAMING_ERR_VALID_7, STAT_RX_FRAMING_ERR_VALID_8, STAT_RX_FRAMING_ERR_VALID_9, STAT_RX_GOT_SIGNAL_OS, STAT_RX_HI_BER, STAT_RX_INRANGEERR, STAT_RX_INTERNAL_LOCAL_FAULT, STAT_RX_JABBER, STAT_RX_LANE0_VLM_BIP7, STAT_RX_LANE0_VLM_BIP7_VALID, STAT_RX_LOCAL_FAULT, STAT_RX_MF_ERR, STAT_RX_MF_LEN_ERR +, STAT_RX_MF_REPEAT_ERR, STAT_RX_MISALIGNED, STAT_RX_MULTICAST, STAT_RX_OVERSIZE, STAT_RX_PACKET_1024_1518_BYTES, STAT_RX_PACKET_128_255_BYTES, STAT_RX_PACKET_1519_1522_BYTES, STAT_RX_PACKET_1523_1548_BYTES, STAT_RX_PACKET_1549_2047_BYTES, STAT_RX_PACKET_2048_4095_BYTES, STAT_RX_PACKET_256_511_BYTES, STAT_RX_PACKET_4096_8191_BYTES, STAT_RX_PACKET_512_1023_BYTES, STAT_RX_PACKET_64_BYTES, STAT_RX_PACKET_65_127_BYTES, STAT_RX_PACKET_8192_9215_BYTES, STAT_RX_PACKET_BAD_FCS, STAT_RX_PACKET_LARGE, STAT_RX_PACKET_SMALL, STAT_RX_PAUSE, STAT_RX_PAUSE_QUANTA0 +, STAT_RX_PAUSE_QUANTA1, STAT_RX_PAUSE_QUANTA2, STAT_RX_PAUSE_QUANTA3, STAT_RX_PAUSE_QUANTA4, STAT_RX_PAUSE_QUANTA5, STAT_RX_PAUSE_QUANTA6, STAT_RX_PAUSE_QUANTA7, STAT_RX_PAUSE_QUANTA8, STAT_RX_PAUSE_REQ, STAT_RX_PAUSE_VALID, STAT_RX_RECEIVED_LOCAL_FAULT, STAT_RX_REMOTE_FAULT, STAT_RX_RSFEC_AM_LOCK0, STAT_RX_RSFEC_AM_LOCK1, STAT_RX_RSFEC_AM_LOCK2, STAT_RX_RSFEC_AM_LOCK3, STAT_RX_RSFEC_CORRECTED_CW_INC, STAT_RX_RSFEC_CW_INC, STAT_RX_RSFEC_ERR_COUNT0_INC, STAT_RX_RSFEC_ERR_COUNT1_INC, STAT_RX_RSFEC_ERR_COUNT2_INC +, STAT_RX_RSFEC_ERR_COUNT3_INC, STAT_RX_RSFEC_HI_SER, STAT_RX_RSFEC_LANE_ALIGNMENT_STATUS, STAT_RX_RSFEC_LANE_FILL_0, STAT_RX_RSFEC_LANE_FILL_1, STAT_RX_RSFEC_LANE_FILL_2, STAT_RX_RSFEC_LANE_FILL_3, STAT_RX_RSFEC_LANE_MAPPING, STAT_RX_RSFEC_RSVD, STAT_RX_RSFEC_UNCORRECTED_CW_INC, STAT_RX_STATUS, STAT_RX_STOMPED_FCS, STAT_RX_SYNCED, STAT_RX_SYNCED_ERR, STAT_RX_TEST_PATTERN_MISMATCH, STAT_RX_TOOLONG, STAT_RX_TOTAL_BYTES, STAT_RX_TOTAL_GOOD_BYTES, STAT_RX_TOTAL_GOOD_PACKETS, STAT_RX_TOTAL_PACKETS, STAT_RX_TRUNCATED +, STAT_RX_UNDERSIZE, STAT_RX_UNICAST, STAT_RX_USER_PAUSE, STAT_RX_VLAN, STAT_RX_VL_DEMUXED, STAT_RX_VL_NUMBER_0, STAT_RX_VL_NUMBER_1, STAT_RX_VL_NUMBER_10, STAT_RX_VL_NUMBER_11, STAT_RX_VL_NUMBER_12, STAT_RX_VL_NUMBER_13, STAT_RX_VL_NUMBER_14, STAT_RX_VL_NUMBER_15, STAT_RX_VL_NUMBER_16, STAT_RX_VL_NUMBER_17, STAT_RX_VL_NUMBER_18, STAT_RX_VL_NUMBER_19, STAT_RX_VL_NUMBER_2, STAT_RX_VL_NUMBER_3, STAT_RX_VL_NUMBER_4, STAT_RX_VL_NUMBER_5 +, STAT_RX_VL_NUMBER_6, STAT_RX_VL_NUMBER_7, STAT_RX_VL_NUMBER_8, STAT_RX_VL_NUMBER_9, STAT_TX_BAD_FCS, STAT_TX_BROADCAST, STAT_TX_FRAME_ERROR, STAT_TX_LOCAL_FAULT, STAT_TX_MULTICAST, STAT_TX_PACKET_1024_1518_BYTES, STAT_TX_PACKET_128_255_BYTES, STAT_TX_PACKET_1519_1522_BYTES, STAT_TX_PACKET_1523_1548_BYTES, STAT_TX_PACKET_1549_2047_BYTES, STAT_TX_PACKET_2048_4095_BYTES, STAT_TX_PACKET_256_511_BYTES, STAT_TX_PACKET_4096_8191_BYTES, STAT_TX_PACKET_512_1023_BYTES, STAT_TX_PACKET_64_BYTES, STAT_TX_PACKET_65_127_BYTES, STAT_TX_PACKET_8192_9215_BYTES +, STAT_TX_PACKET_LARGE, STAT_TX_PACKET_SMALL, STAT_TX_PAUSE, STAT_TX_PAUSE_VALID, STAT_TX_PTP_FIFO_READ_ERROR, STAT_TX_PTP_FIFO_WRITE_ERROR, STAT_TX_TOTAL_BYTES, STAT_TX_TOTAL_GOOD_BYTES, STAT_TX_TOTAL_GOOD_PACKETS, STAT_TX_TOTAL_PACKETS, STAT_TX_UNICAST, STAT_TX_USER_PAUSE, STAT_TX_VLAN, TX_OVFOUT, TX_PTP_PCSLANE_OUT, TX_PTP_TSTAMP_OUT, TX_PTP_TSTAMP_TAG_OUT, TX_PTP_TSTAMP_VALID_OUT, TX_RDYOUT, TX_SERDES_ALT_DATA0, TX_SERDES_ALT_DATA1 +, TX_SERDES_ALT_DATA2, TX_SERDES_ALT_DATA3, TX_SERDES_DATA0, TX_SERDES_DATA1, TX_SERDES_DATA2, TX_SERDES_DATA3, TX_SERDES_DATA4, TX_SERDES_DATA5, TX_SERDES_DATA6, TX_SERDES_DATA7, TX_SERDES_DATA8, TX_SERDES_DATA9, TX_UNFOUT, CTL_CAUI4_MODE, CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, CTL_RSFEC_IEEE_ERROR_INDICATION_MODE, CTL_RX_CHECK_ETYPE_GCP, CTL_RX_CHECK_ETYPE_GPP, CTL_RX_CHECK_ETYPE_PCP, CTL_RX_CHECK_ETYPE_PPP, CTL_RX_CHECK_MCAST_GCP +, CTL_RX_CHECK_MCAST_GPP, CTL_RX_CHECK_MCAST_PCP, CTL_RX_CHECK_MCAST_PPP, CTL_RX_CHECK_OPCODE_GCP, CTL_RX_CHECK_OPCODE_GPP, CTL_RX_CHECK_OPCODE_PCP, CTL_RX_CHECK_OPCODE_PPP, CTL_RX_CHECK_SA_GCP, CTL_RX_CHECK_SA_GPP, CTL_RX_CHECK_SA_PCP, CTL_RX_CHECK_SA_PPP, CTL_RX_CHECK_UCAST_GCP, CTL_RX_CHECK_UCAST_GPP, CTL_RX_CHECK_UCAST_PCP, CTL_RX_CHECK_UCAST_PPP, CTL_RX_ENABLE, CTL_RX_ENABLE_GCP, CTL_RX_ENABLE_GPP, CTL_RX_ENABLE_PCP, CTL_RX_ENABLE_PPP, CTL_RX_FORCE_RESYNC +, CTL_RX_PAUSE_ACK, CTL_RX_PAUSE_ENABLE, CTL_RX_RSFEC_ENABLE, CTL_RX_RSFEC_ENABLE_CORRECTION, CTL_RX_RSFEC_ENABLE_INDICATION, CTL_RX_SYSTEMTIMERIN, CTL_RX_TEST_PATTERN, CTL_TX_ENABLE, CTL_TX_LANE0_VLM_BIP7_OVERRIDE, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE, CTL_TX_PAUSE_ENABLE, CTL_TX_PAUSE_QUANTA0, CTL_TX_PAUSE_QUANTA1, CTL_TX_PAUSE_QUANTA2, CTL_TX_PAUSE_QUANTA3, CTL_TX_PAUSE_QUANTA4, CTL_TX_PAUSE_QUANTA5, CTL_TX_PAUSE_QUANTA6, CTL_TX_PAUSE_QUANTA7, CTL_TX_PAUSE_QUANTA8, CTL_TX_PAUSE_REFRESH_TIMER0 +, CTL_TX_PAUSE_REFRESH_TIMER1, CTL_TX_PAUSE_REFRESH_TIMER2, CTL_TX_PAUSE_REFRESH_TIMER3, CTL_TX_PAUSE_REFRESH_TIMER4, CTL_TX_PAUSE_REFRESH_TIMER5, CTL_TX_PAUSE_REFRESH_TIMER6, CTL_TX_PAUSE_REFRESH_TIMER7, CTL_TX_PAUSE_REFRESH_TIMER8, CTL_TX_PAUSE_REQ, CTL_TX_PTP_VLANE_ADJUST_MODE, CTL_TX_RESEND_PAUSE, CTL_TX_RSFEC_ENABLE, CTL_TX_SEND_IDLE, CTL_TX_SEND_LFI, CTL_TX_SEND_RFI, CTL_TX_SYSTEMTIMERIN, CTL_TX_TEST_PATTERN, DRP_ADDR, DRP_CLK, DRP_DI, DRP_EN +, DRP_WE, RSFEC_BYPASS_RX_DIN, RSFEC_BYPASS_RX_DIN_CW_START, RSFEC_BYPASS_TX_DIN, RSFEC_BYPASS_TX_DIN_CW_START, RX_CLK, RX_RESET, RX_SERDES_ALT_DATA0, RX_SERDES_ALT_DATA1, RX_SERDES_ALT_DATA2, RX_SERDES_ALT_DATA3, RX_SERDES_CLK, RX_SERDES_DATA0, RX_SERDES_DATA1, RX_SERDES_DATA2, RX_SERDES_DATA3, RX_SERDES_DATA4, RX_SERDES_DATA5, RX_SERDES_DATA6, RX_SERDES_DATA7, RX_SERDES_DATA8 +, RX_SERDES_DATA9, RX_SERDES_RESET, TX_CLK, TX_DATAIN0, TX_DATAIN1, TX_DATAIN2, TX_DATAIN3, TX_ENAIN0, TX_ENAIN1, TX_ENAIN2, TX_ENAIN3, TX_EOPIN0, TX_EOPIN1, TX_EOPIN2, TX_EOPIN3, TX_ERRIN0, TX_ERRIN1, TX_ERRIN2, TX_ERRIN3, TX_MTYIN0, TX_MTYIN1 +, TX_MTYIN2, TX_MTYIN3, TX_PREIN, TX_PTP_1588OP_IN, TX_PTP_CHKSUM_OFFSET_IN, TX_PTP_RXTSTAMP_IN, TX_PTP_TAG_FIELD_IN, TX_PTP_TSTAMP_OFFSET_IN, TX_PTP_UPD_CHKSUM_IN, TX_RESET, TX_SOPIN0, TX_SOPIN1, TX_SOPIN2, TX_SOPIN3); parameter CTL_PTP_TRANSPCLK_MODE = "FALSE"; parameter CTL_RX_CHECK_ACK = "TRUE"; parameter CTL_RX_CHECK_PREAMBLE = "FALSE"; @@ -28033,7 +28493,16 @@ module CMACE4 (...); input TX_SOPIN3; endmodule -module MCB (...); +module MCB(CAS, CKE, DQIOWEN0, DQSIOWEN90N, DQSIOWEN90P, IOIDRPADD, IOIDRPBROADCAST, IOIDRPCLK, IOIDRPCS, IOIDRPSDO, IOIDRPTRAIN, IOIDRPUPDATE, LDMN, LDMP, ODT, P0CMDEMPTY, P0CMDFULL, P0RDEMPTY, P0RDERROR, P0RDFULL, P0RDOVERFLOW +, P0WREMPTY, P0WRERROR, P0WRFULL, P0WRUNDERRUN, P1CMDEMPTY, P1CMDFULL, P1RDEMPTY, P1RDERROR, P1RDFULL, P1RDOVERFLOW, P1WREMPTY, P1WRERROR, P1WRFULL, P1WRUNDERRUN, P2CMDEMPTY, P2CMDFULL, P2EMPTY, P2ERROR, P2FULL, P2RDOVERFLOW, P2WRUNDERRUN +, P3CMDEMPTY, P3CMDFULL, P3EMPTY, P3ERROR, P3FULL, P3RDOVERFLOW, P3WRUNDERRUN, P4CMDEMPTY, P4CMDFULL, P4EMPTY, P4ERROR, P4FULL, P4RDOVERFLOW, P4WRUNDERRUN, P5CMDEMPTY, P5CMDFULL, P5EMPTY, P5ERROR, P5FULL, P5RDOVERFLOW, P5WRUNDERRUN +, RAS, RST, SELFREFRESHMODE, UDMN, UDMP, UOCALSTART, UOCMDREADYIN, UODATAVALID, UODONECAL, UOREFRSHFLAG, UOSDO, WE, ADDR, DQON, DQOP, BA, P0RDDATA, P1RDDATA, P2RDDATA, P3RDDATA, P4RDDATA +, P5RDDATA, STATUS, IOIDRPADDR, P0RDCOUNT, P0WRCOUNT, P1RDCOUNT, P1WRCOUNT, P2COUNT, P3COUNT, P4COUNT, P5COUNT, UODATA, DQSIOIN, DQSIOIP, IOIDRPSDI, P0ARBEN, P0CMDCLK, P0CMDEN, P0RDCLK, P0RDEN, P0WRCLK +, P0WREN, P1ARBEN, P1CMDCLK, P1CMDEN, P1RDCLK, P1RDEN, P1WRCLK, P1WREN, P2ARBEN, P2CLK, P2CMDCLK, P2CMDEN, P2EN, P3ARBEN, P3CLK, P3CMDCLK, P3CMDEN, P3EN, P4ARBEN, P4CLK, P4CMDCLK +, P4CMDEN, P4EN, P5ARBEN, P5CLK, P5CMDCLK, P5CMDEN, P5EN, PLLLOCK, RECAL, SELFREFRESHENTER, SYSRST, UDQSIOIN, UDQSIOIP, UIADD, UIBROADCAST, UICLK, UICMD, UICMDEN, UICMDIN, UICS, UIDONECAL +, UIDQLOWERDEC, UIDQLOWERINC, UIDQUPPERDEC, UIDQUPPERINC, UIDRPUPDATE, UILDQSDEC, UILDQSINC, UIREAD, UISDI, UIUDQSDEC, UIUDQSINC, P0CMDCA, P1CMDCA, P2CMDCA, P3CMDCA, P4CMDCA, P5CMDCA, P0CMDRA, P1CMDRA, P2CMDRA, P3CMDRA +, P4CMDRA, P5CMDRA, DQI, PLLCE, PLLCLK, P0CMDBA, P0CMDINSTR, P1CMDBA, P1CMDINSTR, P2CMDBA, P2CMDINSTR, P3CMDBA, P3CMDINSTR, P4CMDBA, P4CMDINSTR, P5CMDBA, P5CMDINSTR, P0WRDATA, P1WRDATA, P2WRDATA, P3WRDATA +, P4WRDATA, P5WRDATA, P0RWRMASK, P1RWRMASK, P2WRMASK, P3WRMASK, P4WRMASK, P5WRMASK, UIDQCOUNT, UIADDR, P0CMDBL, P1CMDBL, P2CMDBL, P3CMDBL, P4CMDBL, P5CMDBL); parameter integer ARB_NUM_TIME_SLOTS = 12; parameter [17:0] ARB_TIME_SLOT_0 = 18'b111111111111111111; parameter [17:0] ARB_TIME_SLOT_1 = 18'b111111111111111111; @@ -28297,12 +28766,12 @@ module MCB (...); endmodule (* keep *) -module HBM_REF_CLK (...); +module HBM_REF_CLK(REF_CLK); input REF_CLK; endmodule (* keep *) -module HBM_SNGLBLI_INTF_APB (...); +module HBM_SNGLBLI_INTF_APB(CATTRIP_PIPE, PRDATA_PIPE, PREADY_PIPE, PSLVERR_PIPE, TEMP_PIPE, PADDR, PCLK, PENABLE, PRESET_N, PSEL, PWDATA, PWRITE); parameter CLK_SEL = "FALSE"; parameter [0:0] IS_PCLK_INVERTED = 1'b0; parameter [0:0] IS_PRESET_N_INVERTED = 1'b0; @@ -28327,7 +28796,9 @@ module HBM_SNGLBLI_INTF_APB (...); endmodule (* keep *) -module HBM_SNGLBLI_INTF_AXI (...); +module HBM_SNGLBLI_INTF_AXI(ARREADY_PIPE, AWREADY_PIPE, BID_PIPE, BRESP_PIPE, BVALID_PIPE, DFI_AW_AERR_N_PIPE, DFI_CLK_BUF, DFI_CTRLUPD_ACK_PIPE, DFI_DBI_BYTE_DISABLE_PIPE, DFI_DW_RDDATA_DBI_PIPE, DFI_DW_RDDATA_DERR_PIPE, DFI_DW_RDDATA_PAR_VALID_PIPE, DFI_DW_RDDATA_VALID_PIPE, DFI_INIT_COMPLETE_PIPE, DFI_PHYUPD_REQ_PIPE, DFI_PHYUPD_TYPE_PIPE, DFI_PHY_LP_STATE_PIPE, DFI_RST_N_BUF, MC_STATUS, PHY_STATUS, RDATA_PARITY_PIPE +, RDATA_PIPE, RID_PIPE, RLAST_PIPE, RRESP_PIPE, RVALID_PIPE, STATUS, WREADY_PIPE, ACLK, ARADDR, ARBURST, ARESET_N, ARID, ARLEN, ARSIZE, ARVALID, AWADDR, AWBURST, AWID, AWLEN, AWSIZE, AWVALID +, BREADY, BSCAN_CK, DFI_LP_PWR_X_REQ, MBIST_EN, RREADY, WDATA, WDATA_PARITY, WLAST, WSTRB, WVALID); parameter CLK_SEL = "FALSE"; parameter integer DATARATE = 1800; parameter [0:0] IS_ACLK_INVERTED = 1'b0; @@ -28395,7 +28866,42 @@ module HBM_SNGLBLI_INTF_AXI (...); endmodule (* keep *) -module HBM_ONE_STACK_INTF (...); +module HBM_ONE_STACK_INTF(APB_0_PRDATA, APB_0_PREADY, APB_0_PSLVERR, AXI_00_ARREADY, AXI_00_AWREADY, AXI_00_BID, AXI_00_BRESP, AXI_00_BVALID, AXI_00_DFI_AW_AERR_N, AXI_00_DFI_CLK_BUF, AXI_00_DFI_DBI_BYTE_DISABLE, AXI_00_DFI_DW_RDDATA_DBI, AXI_00_DFI_DW_RDDATA_DERR, AXI_00_DFI_DW_RDDATA_VALID, AXI_00_DFI_INIT_COMPLETE, AXI_00_DFI_PHYUPD_REQ, AXI_00_DFI_PHY_LP_STATE, AXI_00_DFI_RST_N_BUF, AXI_00_MC_STATUS, AXI_00_PHY_STATUS, AXI_00_RDATA +, AXI_00_RDATA_PARITY, AXI_00_RID, AXI_00_RLAST, AXI_00_RRESP, AXI_00_RVALID, AXI_00_WREADY, AXI_01_ARREADY, AXI_01_AWREADY, AXI_01_BID, AXI_01_BRESP, AXI_01_BVALID, AXI_01_DFI_AW_AERR_N, AXI_01_DFI_CLK_BUF, AXI_01_DFI_DBI_BYTE_DISABLE, AXI_01_DFI_DW_RDDATA_DBI, AXI_01_DFI_DW_RDDATA_DERR, AXI_01_DFI_DW_RDDATA_VALID, AXI_01_DFI_INIT_COMPLETE, AXI_01_DFI_PHYUPD_REQ, AXI_01_DFI_PHY_LP_STATE, AXI_01_DFI_RST_N_BUF +, AXI_01_RDATA, AXI_01_RDATA_PARITY, AXI_01_RID, AXI_01_RLAST, AXI_01_RRESP, AXI_01_RVALID, AXI_01_WREADY, AXI_02_ARREADY, AXI_02_AWREADY, AXI_02_BID, AXI_02_BRESP, AXI_02_BVALID, AXI_02_DFI_AW_AERR_N, AXI_02_DFI_CLK_BUF, AXI_02_DFI_DBI_BYTE_DISABLE, AXI_02_DFI_DW_RDDATA_DBI, AXI_02_DFI_DW_RDDATA_DERR, AXI_02_DFI_DW_RDDATA_VALID, AXI_02_DFI_INIT_COMPLETE, AXI_02_DFI_PHYUPD_REQ, AXI_02_DFI_PHY_LP_STATE +, AXI_02_DFI_RST_N_BUF, AXI_02_MC_STATUS, AXI_02_PHY_STATUS, AXI_02_RDATA, AXI_02_RDATA_PARITY, AXI_02_RID, AXI_02_RLAST, AXI_02_RRESP, AXI_02_RVALID, AXI_02_WREADY, AXI_03_ARREADY, AXI_03_AWREADY, AXI_03_BID, AXI_03_BRESP, AXI_03_BVALID, AXI_03_DFI_AW_AERR_N, AXI_03_DFI_CLK_BUF, AXI_03_DFI_DBI_BYTE_DISABLE, AXI_03_DFI_DW_RDDATA_DBI, AXI_03_DFI_DW_RDDATA_DERR, AXI_03_DFI_DW_RDDATA_VALID +, AXI_03_DFI_INIT_COMPLETE, AXI_03_DFI_PHYUPD_REQ, AXI_03_DFI_PHY_LP_STATE, AXI_03_DFI_RST_N_BUF, AXI_03_RDATA, AXI_03_RDATA_PARITY, AXI_03_RID, AXI_03_RLAST, AXI_03_RRESP, AXI_03_RVALID, AXI_03_WREADY, AXI_04_ARREADY, AXI_04_AWREADY, AXI_04_BID, AXI_04_BRESP, AXI_04_BVALID, AXI_04_DFI_AW_AERR_N, AXI_04_DFI_CLK_BUF, AXI_04_DFI_DBI_BYTE_DISABLE, AXI_04_DFI_DW_RDDATA_DBI, AXI_04_DFI_DW_RDDATA_DERR +, AXI_04_DFI_DW_RDDATA_VALID, AXI_04_DFI_INIT_COMPLETE, AXI_04_DFI_PHYUPD_REQ, AXI_04_DFI_PHY_LP_STATE, AXI_04_DFI_RST_N_BUF, AXI_04_MC_STATUS, AXI_04_PHY_STATUS, AXI_04_RDATA, AXI_04_RDATA_PARITY, AXI_04_RID, AXI_04_RLAST, AXI_04_RRESP, AXI_04_RVALID, AXI_04_WREADY, AXI_05_ARREADY, AXI_05_AWREADY, AXI_05_BID, AXI_05_BRESP, AXI_05_BVALID, AXI_05_DFI_AW_AERR_N, AXI_05_DFI_CLK_BUF +, AXI_05_DFI_DBI_BYTE_DISABLE, AXI_05_DFI_DW_RDDATA_DBI, AXI_05_DFI_DW_RDDATA_DERR, AXI_05_DFI_DW_RDDATA_VALID, AXI_05_DFI_INIT_COMPLETE, AXI_05_DFI_PHYUPD_REQ, AXI_05_DFI_PHY_LP_STATE, AXI_05_DFI_RST_N_BUF, AXI_05_RDATA, AXI_05_RDATA_PARITY, AXI_05_RID, AXI_05_RLAST, AXI_05_RRESP, AXI_05_RVALID, AXI_05_WREADY, AXI_06_ARREADY, AXI_06_AWREADY, AXI_06_BID, AXI_06_BRESP, AXI_06_BVALID, AXI_06_DFI_AW_AERR_N +, AXI_06_DFI_CLK_BUF, AXI_06_DFI_DBI_BYTE_DISABLE, AXI_06_DFI_DW_RDDATA_DBI, AXI_06_DFI_DW_RDDATA_DERR, AXI_06_DFI_DW_RDDATA_VALID, AXI_06_DFI_INIT_COMPLETE, AXI_06_DFI_PHYUPD_REQ, AXI_06_DFI_PHY_LP_STATE, AXI_06_DFI_RST_N_BUF, AXI_06_MC_STATUS, AXI_06_PHY_STATUS, AXI_06_RDATA, AXI_06_RDATA_PARITY, AXI_06_RID, AXI_06_RLAST, AXI_06_RRESP, AXI_06_RVALID, AXI_06_WREADY, AXI_07_ARREADY, AXI_07_AWREADY, AXI_07_BID +, AXI_07_BRESP, AXI_07_BVALID, AXI_07_DFI_AW_AERR_N, AXI_07_DFI_CLK_BUF, AXI_07_DFI_DBI_BYTE_DISABLE, AXI_07_DFI_DW_RDDATA_DBI, AXI_07_DFI_DW_RDDATA_DERR, AXI_07_DFI_DW_RDDATA_VALID, AXI_07_DFI_INIT_COMPLETE, AXI_07_DFI_PHYUPD_REQ, AXI_07_DFI_PHY_LP_STATE, AXI_07_DFI_RST_N_BUF, AXI_07_RDATA, AXI_07_RDATA_PARITY, AXI_07_RID, AXI_07_RLAST, AXI_07_RRESP, AXI_07_RVALID, AXI_07_WREADY, AXI_08_ARREADY, AXI_08_AWREADY +, AXI_08_BID, AXI_08_BRESP, AXI_08_BVALID, AXI_08_DFI_AW_AERR_N, AXI_08_DFI_CLK_BUF, AXI_08_DFI_DBI_BYTE_DISABLE, AXI_08_DFI_DW_RDDATA_DBI, AXI_08_DFI_DW_RDDATA_DERR, AXI_08_DFI_DW_RDDATA_VALID, AXI_08_DFI_INIT_COMPLETE, AXI_08_DFI_PHYUPD_REQ, AXI_08_DFI_PHY_LP_STATE, AXI_08_DFI_RST_N_BUF, AXI_08_MC_STATUS, AXI_08_PHY_STATUS, AXI_08_RDATA, AXI_08_RDATA_PARITY, AXI_08_RID, AXI_08_RLAST, AXI_08_RRESP, AXI_08_RVALID +, AXI_08_WREADY, AXI_09_ARREADY, AXI_09_AWREADY, AXI_09_BID, AXI_09_BRESP, AXI_09_BVALID, AXI_09_DFI_AW_AERR_N, AXI_09_DFI_CLK_BUF, AXI_09_DFI_DBI_BYTE_DISABLE, AXI_09_DFI_DW_RDDATA_DBI, AXI_09_DFI_DW_RDDATA_DERR, AXI_09_DFI_DW_RDDATA_VALID, AXI_09_DFI_INIT_COMPLETE, AXI_09_DFI_PHYUPD_REQ, AXI_09_DFI_PHY_LP_STATE, AXI_09_DFI_RST_N_BUF, AXI_09_RDATA, AXI_09_RDATA_PARITY, AXI_09_RID, AXI_09_RLAST, AXI_09_RRESP +, AXI_09_RVALID, AXI_09_WREADY, AXI_10_ARREADY, AXI_10_AWREADY, AXI_10_BID, AXI_10_BRESP, AXI_10_BVALID, AXI_10_DFI_AW_AERR_N, AXI_10_DFI_CLK_BUF, AXI_10_DFI_DBI_BYTE_DISABLE, AXI_10_DFI_DW_RDDATA_DBI, AXI_10_DFI_DW_RDDATA_DERR, AXI_10_DFI_DW_RDDATA_VALID, AXI_10_DFI_INIT_COMPLETE, AXI_10_DFI_PHYUPD_REQ, AXI_10_DFI_PHY_LP_STATE, AXI_10_DFI_RST_N_BUF, AXI_10_MC_STATUS, AXI_10_PHY_STATUS, AXI_10_RDATA, AXI_10_RDATA_PARITY +, AXI_10_RID, AXI_10_RLAST, AXI_10_RRESP, AXI_10_RVALID, AXI_10_WREADY, AXI_11_ARREADY, AXI_11_AWREADY, AXI_11_BID, AXI_11_BRESP, AXI_11_BVALID, AXI_11_DFI_AW_AERR_N, AXI_11_DFI_CLK_BUF, AXI_11_DFI_DBI_BYTE_DISABLE, AXI_11_DFI_DW_RDDATA_DBI, AXI_11_DFI_DW_RDDATA_DERR, AXI_11_DFI_DW_RDDATA_VALID, AXI_11_DFI_INIT_COMPLETE, AXI_11_DFI_PHYUPD_REQ, AXI_11_DFI_PHY_LP_STATE, AXI_11_DFI_RST_N_BUF, AXI_11_RDATA +, AXI_11_RDATA_PARITY, AXI_11_RID, AXI_11_RLAST, AXI_11_RRESP, AXI_11_RVALID, AXI_11_WREADY, AXI_12_ARREADY, AXI_12_AWREADY, AXI_12_BID, AXI_12_BRESP, AXI_12_BVALID, AXI_12_DFI_AW_AERR_N, AXI_12_DFI_CLK_BUF, AXI_12_DFI_DBI_BYTE_DISABLE, AXI_12_DFI_DW_RDDATA_DBI, AXI_12_DFI_DW_RDDATA_DERR, AXI_12_DFI_DW_RDDATA_VALID, AXI_12_DFI_INIT_COMPLETE, AXI_12_DFI_PHYUPD_REQ, AXI_12_DFI_PHY_LP_STATE, AXI_12_DFI_RST_N_BUF +, AXI_12_MC_STATUS, AXI_12_PHY_STATUS, AXI_12_RDATA, AXI_12_RDATA_PARITY, AXI_12_RID, AXI_12_RLAST, AXI_12_RRESP, AXI_12_RVALID, AXI_12_WREADY, AXI_13_ARREADY, AXI_13_AWREADY, AXI_13_BID, AXI_13_BRESP, AXI_13_BVALID, AXI_13_DFI_AW_AERR_N, AXI_13_DFI_CLK_BUF, AXI_13_DFI_DBI_BYTE_DISABLE, AXI_13_DFI_DW_RDDATA_DBI, AXI_13_DFI_DW_RDDATA_DERR, AXI_13_DFI_DW_RDDATA_VALID, AXI_13_DFI_INIT_COMPLETE +, AXI_13_DFI_PHYUPD_REQ, AXI_13_DFI_PHY_LP_STATE, AXI_13_DFI_RST_N_BUF, AXI_13_RDATA, AXI_13_RDATA_PARITY, AXI_13_RID, AXI_13_RLAST, AXI_13_RRESP, AXI_13_RVALID, AXI_13_WREADY, AXI_14_ARREADY, AXI_14_AWREADY, AXI_14_BID, AXI_14_BRESP, AXI_14_BVALID, AXI_14_DFI_AW_AERR_N, AXI_14_DFI_CLK_BUF, AXI_14_DFI_DBI_BYTE_DISABLE, AXI_14_DFI_DW_RDDATA_DBI, AXI_14_DFI_DW_RDDATA_DERR, AXI_14_DFI_DW_RDDATA_VALID +, AXI_14_DFI_INIT_COMPLETE, AXI_14_DFI_PHYUPD_REQ, AXI_14_DFI_PHY_LP_STATE, AXI_14_DFI_RST_N_BUF, AXI_14_MC_STATUS, AXI_14_PHY_STATUS, AXI_14_RDATA, AXI_14_RDATA_PARITY, AXI_14_RID, AXI_14_RLAST, AXI_14_RRESP, AXI_14_RVALID, AXI_14_WREADY, AXI_15_ARREADY, AXI_15_AWREADY, AXI_15_BID, AXI_15_BRESP, AXI_15_BVALID, AXI_15_DFI_AW_AERR_N, AXI_15_DFI_CLK_BUF, AXI_15_DFI_DBI_BYTE_DISABLE +, AXI_15_DFI_DW_RDDATA_DBI, AXI_15_DFI_DW_RDDATA_DERR, AXI_15_DFI_DW_RDDATA_VALID, AXI_15_DFI_INIT_COMPLETE, AXI_15_DFI_PHYUPD_REQ, AXI_15_DFI_PHY_LP_STATE, AXI_15_DFI_RST_N_BUF, AXI_15_RDATA, AXI_15_RDATA_PARITY, AXI_15_RID, AXI_15_RLAST, AXI_15_RRESP, AXI_15_RVALID, AXI_15_WREADY, DRAM_0_STAT_CATTRIP, DRAM_0_STAT_TEMP, APB_0_PADDR, APB_0_PCLK, APB_0_PENABLE, APB_0_PRESET_N, APB_0_PSEL +, APB_0_PWDATA, APB_0_PWRITE, AXI_00_ACLK, AXI_00_ARADDR, AXI_00_ARBURST, AXI_00_ARESET_N, AXI_00_ARID, AXI_00_ARLEN, AXI_00_ARSIZE, AXI_00_ARVALID, AXI_00_AWADDR, AXI_00_AWBURST, AXI_00_AWID, AXI_00_AWLEN, AXI_00_AWSIZE, AXI_00_AWVALID, AXI_00_BREADY, AXI_00_DFI_LP_PWR_X_REQ, AXI_00_RREADY, AXI_00_WDATA, AXI_00_WDATA_PARITY +, AXI_00_WLAST, AXI_00_WSTRB, AXI_00_WVALID, AXI_01_ACLK, AXI_01_ARADDR, AXI_01_ARBURST, AXI_01_ARESET_N, AXI_01_ARID, AXI_01_ARLEN, AXI_01_ARSIZE, AXI_01_ARVALID, AXI_01_AWADDR, AXI_01_AWBURST, AXI_01_AWID, AXI_01_AWLEN, AXI_01_AWSIZE, AXI_01_AWVALID, AXI_01_BREADY, AXI_01_DFI_LP_PWR_X_REQ, AXI_01_RREADY, AXI_01_WDATA +, AXI_01_WDATA_PARITY, AXI_01_WLAST, AXI_01_WSTRB, AXI_01_WVALID, AXI_02_ACLK, AXI_02_ARADDR, AXI_02_ARBURST, AXI_02_ARESET_N, AXI_02_ARID, AXI_02_ARLEN, AXI_02_ARSIZE, AXI_02_ARVALID, AXI_02_AWADDR, AXI_02_AWBURST, AXI_02_AWID, AXI_02_AWLEN, AXI_02_AWSIZE, AXI_02_AWVALID, AXI_02_BREADY, AXI_02_DFI_LP_PWR_X_REQ, AXI_02_RREADY +, AXI_02_WDATA, AXI_02_WDATA_PARITY, AXI_02_WLAST, AXI_02_WSTRB, AXI_02_WVALID, AXI_03_ACLK, AXI_03_ARADDR, AXI_03_ARBURST, AXI_03_ARESET_N, AXI_03_ARID, AXI_03_ARLEN, AXI_03_ARSIZE, AXI_03_ARVALID, AXI_03_AWADDR, AXI_03_AWBURST, AXI_03_AWID, AXI_03_AWLEN, AXI_03_AWSIZE, AXI_03_AWVALID, AXI_03_BREADY, AXI_03_DFI_LP_PWR_X_REQ +, AXI_03_RREADY, AXI_03_WDATA, AXI_03_WDATA_PARITY, AXI_03_WLAST, AXI_03_WSTRB, AXI_03_WVALID, AXI_04_ACLK, AXI_04_ARADDR, AXI_04_ARBURST, AXI_04_ARESET_N, AXI_04_ARID, AXI_04_ARLEN, AXI_04_ARSIZE, AXI_04_ARVALID, AXI_04_AWADDR, AXI_04_AWBURST, AXI_04_AWID, AXI_04_AWLEN, AXI_04_AWSIZE, AXI_04_AWVALID, AXI_04_BREADY +, AXI_04_DFI_LP_PWR_X_REQ, AXI_04_RREADY, AXI_04_WDATA, AXI_04_WDATA_PARITY, AXI_04_WLAST, AXI_04_WSTRB, AXI_04_WVALID, AXI_05_ACLK, AXI_05_ARADDR, AXI_05_ARBURST, AXI_05_ARESET_N, AXI_05_ARID, AXI_05_ARLEN, AXI_05_ARSIZE, AXI_05_ARVALID, AXI_05_AWADDR, AXI_05_AWBURST, AXI_05_AWID, AXI_05_AWLEN, AXI_05_AWSIZE, AXI_05_AWVALID +, AXI_05_BREADY, AXI_05_DFI_LP_PWR_X_REQ, AXI_05_RREADY, AXI_05_WDATA, AXI_05_WDATA_PARITY, AXI_05_WLAST, AXI_05_WSTRB, AXI_05_WVALID, AXI_06_ACLK, AXI_06_ARADDR, AXI_06_ARBURST, AXI_06_ARESET_N, AXI_06_ARID, AXI_06_ARLEN, AXI_06_ARSIZE, AXI_06_ARVALID, AXI_06_AWADDR, AXI_06_AWBURST, AXI_06_AWID, AXI_06_AWLEN, AXI_06_AWSIZE +, AXI_06_AWVALID, AXI_06_BREADY, AXI_06_DFI_LP_PWR_X_REQ, AXI_06_RREADY, AXI_06_WDATA, AXI_06_WDATA_PARITY, AXI_06_WLAST, AXI_06_WSTRB, AXI_06_WVALID, AXI_07_ACLK, AXI_07_ARADDR, AXI_07_ARBURST, AXI_07_ARESET_N, AXI_07_ARID, AXI_07_ARLEN, AXI_07_ARSIZE, AXI_07_ARVALID, AXI_07_AWADDR, AXI_07_AWBURST, AXI_07_AWID, AXI_07_AWLEN +, AXI_07_AWSIZE, AXI_07_AWVALID, AXI_07_BREADY, AXI_07_DFI_LP_PWR_X_REQ, AXI_07_RREADY, AXI_07_WDATA, AXI_07_WDATA_PARITY, AXI_07_WLAST, AXI_07_WSTRB, AXI_07_WVALID, AXI_08_ACLK, AXI_08_ARADDR, AXI_08_ARBURST, AXI_08_ARESET_N, AXI_08_ARID, AXI_08_ARLEN, AXI_08_ARSIZE, AXI_08_ARVALID, AXI_08_AWADDR, AXI_08_AWBURST, AXI_08_AWID +, AXI_08_AWLEN, AXI_08_AWSIZE, AXI_08_AWVALID, AXI_08_BREADY, AXI_08_DFI_LP_PWR_X_REQ, AXI_08_RREADY, AXI_08_WDATA, AXI_08_WDATA_PARITY, AXI_08_WLAST, AXI_08_WSTRB, AXI_08_WVALID, AXI_09_ACLK, AXI_09_ARADDR, AXI_09_ARBURST, AXI_09_ARESET_N, AXI_09_ARID, AXI_09_ARLEN, AXI_09_ARSIZE, AXI_09_ARVALID, AXI_09_AWADDR, AXI_09_AWBURST +, AXI_09_AWID, AXI_09_AWLEN, AXI_09_AWSIZE, AXI_09_AWVALID, AXI_09_BREADY, AXI_09_DFI_LP_PWR_X_REQ, AXI_09_RREADY, AXI_09_WDATA, AXI_09_WDATA_PARITY, AXI_09_WLAST, AXI_09_WSTRB, AXI_09_WVALID, AXI_10_ACLK, AXI_10_ARADDR, AXI_10_ARBURST, AXI_10_ARESET_N, AXI_10_ARID, AXI_10_ARLEN, AXI_10_ARSIZE, AXI_10_ARVALID, AXI_10_AWADDR +, AXI_10_AWBURST, AXI_10_AWID, AXI_10_AWLEN, AXI_10_AWSIZE, AXI_10_AWVALID, AXI_10_BREADY, AXI_10_DFI_LP_PWR_X_REQ, AXI_10_RREADY, AXI_10_WDATA, AXI_10_WDATA_PARITY, AXI_10_WLAST, AXI_10_WSTRB, AXI_10_WVALID, AXI_11_ACLK, AXI_11_ARADDR, AXI_11_ARBURST, AXI_11_ARESET_N, AXI_11_ARID, AXI_11_ARLEN, AXI_11_ARSIZE, AXI_11_ARVALID +, AXI_11_AWADDR, AXI_11_AWBURST, AXI_11_AWID, AXI_11_AWLEN, AXI_11_AWSIZE, AXI_11_AWVALID, AXI_11_BREADY, AXI_11_DFI_LP_PWR_X_REQ, AXI_11_RREADY, AXI_11_WDATA, AXI_11_WDATA_PARITY, AXI_11_WLAST, AXI_11_WSTRB, AXI_11_WVALID, AXI_12_ACLK, AXI_12_ARADDR, AXI_12_ARBURST, AXI_12_ARESET_N, AXI_12_ARID, AXI_12_ARLEN, AXI_12_ARSIZE +, AXI_12_ARVALID, AXI_12_AWADDR, AXI_12_AWBURST, AXI_12_AWID, AXI_12_AWLEN, AXI_12_AWSIZE, AXI_12_AWVALID, AXI_12_BREADY, AXI_12_DFI_LP_PWR_X_REQ, AXI_12_RREADY, AXI_12_WDATA, AXI_12_WDATA_PARITY, AXI_12_WLAST, AXI_12_WSTRB, AXI_12_WVALID, AXI_13_ACLK, AXI_13_ARADDR, AXI_13_ARBURST, AXI_13_ARESET_N, AXI_13_ARID, AXI_13_ARLEN +, AXI_13_ARSIZE, AXI_13_ARVALID, AXI_13_AWADDR, AXI_13_AWBURST, AXI_13_AWID, AXI_13_AWLEN, AXI_13_AWSIZE, AXI_13_AWVALID, AXI_13_BREADY, AXI_13_DFI_LP_PWR_X_REQ, AXI_13_RREADY, AXI_13_WDATA, AXI_13_WDATA_PARITY, AXI_13_WLAST, AXI_13_WSTRB, AXI_13_WVALID, AXI_14_ACLK, AXI_14_ARADDR, AXI_14_ARBURST, AXI_14_ARESET_N, AXI_14_ARID +, AXI_14_ARLEN, AXI_14_ARSIZE, AXI_14_ARVALID, AXI_14_AWADDR, AXI_14_AWBURST, AXI_14_AWID, AXI_14_AWLEN, AXI_14_AWSIZE, AXI_14_AWVALID, AXI_14_BREADY, AXI_14_DFI_LP_PWR_X_REQ, AXI_14_RREADY, AXI_14_WDATA, AXI_14_WDATA_PARITY, AXI_14_WLAST, AXI_14_WSTRB, AXI_14_WVALID, AXI_15_ACLK, AXI_15_ARADDR, AXI_15_ARBURST, AXI_15_ARESET_N +, AXI_15_ARID, AXI_15_ARLEN, AXI_15_ARSIZE, AXI_15_ARVALID, AXI_15_AWADDR, AXI_15_AWBURST, AXI_15_AWID, AXI_15_AWLEN, AXI_15_AWSIZE, AXI_15_AWVALID, AXI_15_BREADY, AXI_15_DFI_LP_PWR_X_REQ, AXI_15_RREADY, AXI_15_WDATA, AXI_15_WDATA_PARITY, AXI_15_WLAST, AXI_15_WSTRB, AXI_15_WVALID, BSCAN_DRCK, BSCAN_TCK, HBM_REF_CLK +, MBIST_EN_00, MBIST_EN_01, MBIST_EN_02, MBIST_EN_03, MBIST_EN_04, MBIST_EN_05, MBIST_EN_06, MBIST_EN_07); parameter CLK_SEL_00 = "FALSE"; parameter CLK_SEL_01 = "FALSE"; parameter CLK_SEL_02 = "FALSE"; @@ -29298,7 +29804,77 @@ module HBM_ONE_STACK_INTF (...); endmodule (* keep *) -module HBM_TWO_STACK_INTF (...); +module HBM_TWO_STACK_INTF(APB_0_PRDATA, APB_0_PREADY, APB_0_PSLVERR, APB_1_PRDATA, APB_1_PREADY, APB_1_PSLVERR, AXI_00_ARREADY, AXI_00_AWREADY, AXI_00_BID, AXI_00_BRESP, AXI_00_BVALID, AXI_00_DFI_AW_AERR_N, AXI_00_DFI_CLK_BUF, AXI_00_DFI_DBI_BYTE_DISABLE, AXI_00_DFI_DW_RDDATA_DBI, AXI_00_DFI_DW_RDDATA_DERR, AXI_00_DFI_DW_RDDATA_VALID, AXI_00_DFI_INIT_COMPLETE, AXI_00_DFI_PHYUPD_REQ, AXI_00_DFI_PHY_LP_STATE, AXI_00_DFI_RST_N_BUF +, AXI_00_MC_STATUS, AXI_00_PHY_STATUS, AXI_00_RDATA, AXI_00_RDATA_PARITY, AXI_00_RID, AXI_00_RLAST, AXI_00_RRESP, AXI_00_RVALID, AXI_00_WREADY, AXI_01_ARREADY, AXI_01_AWREADY, AXI_01_BID, AXI_01_BRESP, AXI_01_BVALID, AXI_01_DFI_AW_AERR_N, AXI_01_DFI_CLK_BUF, AXI_01_DFI_DBI_BYTE_DISABLE, AXI_01_DFI_DW_RDDATA_DBI, AXI_01_DFI_DW_RDDATA_DERR, AXI_01_DFI_DW_RDDATA_VALID, AXI_01_DFI_INIT_COMPLETE +, AXI_01_DFI_PHYUPD_REQ, AXI_01_DFI_PHY_LP_STATE, AXI_01_DFI_RST_N_BUF, AXI_01_RDATA, AXI_01_RDATA_PARITY, AXI_01_RID, AXI_01_RLAST, AXI_01_RRESP, AXI_01_RVALID, AXI_01_WREADY, AXI_02_ARREADY, AXI_02_AWREADY, AXI_02_BID, AXI_02_BRESP, AXI_02_BVALID, AXI_02_DFI_AW_AERR_N, AXI_02_DFI_CLK_BUF, AXI_02_DFI_DBI_BYTE_DISABLE, AXI_02_DFI_DW_RDDATA_DBI, AXI_02_DFI_DW_RDDATA_DERR, AXI_02_DFI_DW_RDDATA_VALID +, AXI_02_DFI_INIT_COMPLETE, AXI_02_DFI_PHYUPD_REQ, AXI_02_DFI_PHY_LP_STATE, AXI_02_DFI_RST_N_BUF, AXI_02_MC_STATUS, AXI_02_PHY_STATUS, AXI_02_RDATA, AXI_02_RDATA_PARITY, AXI_02_RID, AXI_02_RLAST, AXI_02_RRESP, AXI_02_RVALID, AXI_02_WREADY, AXI_03_ARREADY, AXI_03_AWREADY, AXI_03_BID, AXI_03_BRESP, AXI_03_BVALID, AXI_03_DFI_AW_AERR_N, AXI_03_DFI_CLK_BUF, AXI_03_DFI_DBI_BYTE_DISABLE +, AXI_03_DFI_DW_RDDATA_DBI, AXI_03_DFI_DW_RDDATA_DERR, AXI_03_DFI_DW_RDDATA_VALID, AXI_03_DFI_INIT_COMPLETE, AXI_03_DFI_PHYUPD_REQ, AXI_03_DFI_PHY_LP_STATE, AXI_03_DFI_RST_N_BUF, AXI_03_RDATA, AXI_03_RDATA_PARITY, AXI_03_RID, AXI_03_RLAST, AXI_03_RRESP, AXI_03_RVALID, AXI_03_WREADY, AXI_04_ARREADY, AXI_04_AWREADY, AXI_04_BID, AXI_04_BRESP, AXI_04_BVALID, AXI_04_DFI_AW_AERR_N, AXI_04_DFI_CLK_BUF +, AXI_04_DFI_DBI_BYTE_DISABLE, AXI_04_DFI_DW_RDDATA_DBI, AXI_04_DFI_DW_RDDATA_DERR, AXI_04_DFI_DW_RDDATA_VALID, AXI_04_DFI_INIT_COMPLETE, AXI_04_DFI_PHYUPD_REQ, AXI_04_DFI_PHY_LP_STATE, AXI_04_DFI_RST_N_BUF, AXI_04_MC_STATUS, AXI_04_PHY_STATUS, AXI_04_RDATA, AXI_04_RDATA_PARITY, AXI_04_RID, AXI_04_RLAST, AXI_04_RRESP, AXI_04_RVALID, AXI_04_WREADY, AXI_05_ARREADY, AXI_05_AWREADY, AXI_05_BID, AXI_05_BRESP +, AXI_05_BVALID, AXI_05_DFI_AW_AERR_N, AXI_05_DFI_CLK_BUF, AXI_05_DFI_DBI_BYTE_DISABLE, AXI_05_DFI_DW_RDDATA_DBI, AXI_05_DFI_DW_RDDATA_DERR, AXI_05_DFI_DW_RDDATA_VALID, AXI_05_DFI_INIT_COMPLETE, AXI_05_DFI_PHYUPD_REQ, AXI_05_DFI_PHY_LP_STATE, AXI_05_DFI_RST_N_BUF, AXI_05_RDATA, AXI_05_RDATA_PARITY, AXI_05_RID, AXI_05_RLAST, AXI_05_RRESP, AXI_05_RVALID, AXI_05_WREADY, AXI_06_ARREADY, AXI_06_AWREADY, AXI_06_BID +, AXI_06_BRESP, AXI_06_BVALID, AXI_06_DFI_AW_AERR_N, AXI_06_DFI_CLK_BUF, AXI_06_DFI_DBI_BYTE_DISABLE, AXI_06_DFI_DW_RDDATA_DBI, AXI_06_DFI_DW_RDDATA_DERR, AXI_06_DFI_DW_RDDATA_VALID, AXI_06_DFI_INIT_COMPLETE, AXI_06_DFI_PHYUPD_REQ, AXI_06_DFI_PHY_LP_STATE, AXI_06_DFI_RST_N_BUF, AXI_06_MC_STATUS, AXI_06_PHY_STATUS, AXI_06_RDATA, AXI_06_RDATA_PARITY, AXI_06_RID, AXI_06_RLAST, AXI_06_RRESP, AXI_06_RVALID, AXI_06_WREADY +, AXI_07_ARREADY, AXI_07_AWREADY, AXI_07_BID, AXI_07_BRESP, AXI_07_BVALID, AXI_07_DFI_AW_AERR_N, AXI_07_DFI_CLK_BUF, AXI_07_DFI_DBI_BYTE_DISABLE, AXI_07_DFI_DW_RDDATA_DBI, AXI_07_DFI_DW_RDDATA_DERR, AXI_07_DFI_DW_RDDATA_VALID, AXI_07_DFI_INIT_COMPLETE, AXI_07_DFI_PHYUPD_REQ, AXI_07_DFI_PHY_LP_STATE, AXI_07_DFI_RST_N_BUF, AXI_07_RDATA, AXI_07_RDATA_PARITY, AXI_07_RID, AXI_07_RLAST, AXI_07_RRESP, AXI_07_RVALID +, AXI_07_WREADY, AXI_08_ARREADY, AXI_08_AWREADY, AXI_08_BID, AXI_08_BRESP, AXI_08_BVALID, AXI_08_DFI_AW_AERR_N, AXI_08_DFI_CLK_BUF, AXI_08_DFI_DBI_BYTE_DISABLE, AXI_08_DFI_DW_RDDATA_DBI, AXI_08_DFI_DW_RDDATA_DERR, AXI_08_DFI_DW_RDDATA_VALID, AXI_08_DFI_INIT_COMPLETE, AXI_08_DFI_PHYUPD_REQ, AXI_08_DFI_PHY_LP_STATE, AXI_08_DFI_RST_N_BUF, AXI_08_MC_STATUS, AXI_08_PHY_STATUS, AXI_08_RDATA, AXI_08_RDATA_PARITY, AXI_08_RID +, AXI_08_RLAST, AXI_08_RRESP, AXI_08_RVALID, AXI_08_WREADY, AXI_09_ARREADY, AXI_09_AWREADY, AXI_09_BID, AXI_09_BRESP, AXI_09_BVALID, AXI_09_DFI_AW_AERR_N, AXI_09_DFI_CLK_BUF, AXI_09_DFI_DBI_BYTE_DISABLE, AXI_09_DFI_DW_RDDATA_DBI, AXI_09_DFI_DW_RDDATA_DERR, AXI_09_DFI_DW_RDDATA_VALID, AXI_09_DFI_INIT_COMPLETE, AXI_09_DFI_PHYUPD_REQ, AXI_09_DFI_PHY_LP_STATE, AXI_09_DFI_RST_N_BUF, AXI_09_RDATA, AXI_09_RDATA_PARITY +, AXI_09_RID, AXI_09_RLAST, AXI_09_RRESP, AXI_09_RVALID, AXI_09_WREADY, AXI_10_ARREADY, AXI_10_AWREADY, AXI_10_BID, AXI_10_BRESP, AXI_10_BVALID, AXI_10_DFI_AW_AERR_N, AXI_10_DFI_CLK_BUF, AXI_10_DFI_DBI_BYTE_DISABLE, AXI_10_DFI_DW_RDDATA_DBI, AXI_10_DFI_DW_RDDATA_DERR, AXI_10_DFI_DW_RDDATA_VALID, AXI_10_DFI_INIT_COMPLETE, AXI_10_DFI_PHYUPD_REQ, AXI_10_DFI_PHY_LP_STATE, AXI_10_DFI_RST_N_BUF, AXI_10_MC_STATUS +, AXI_10_PHY_STATUS, AXI_10_RDATA, AXI_10_RDATA_PARITY, AXI_10_RID, AXI_10_RLAST, AXI_10_RRESP, AXI_10_RVALID, AXI_10_WREADY, AXI_11_ARREADY, AXI_11_AWREADY, AXI_11_BID, AXI_11_BRESP, AXI_11_BVALID, AXI_11_DFI_AW_AERR_N, AXI_11_DFI_CLK_BUF, AXI_11_DFI_DBI_BYTE_DISABLE, AXI_11_DFI_DW_RDDATA_DBI, AXI_11_DFI_DW_RDDATA_DERR, AXI_11_DFI_DW_RDDATA_VALID, AXI_11_DFI_INIT_COMPLETE, AXI_11_DFI_PHYUPD_REQ +, AXI_11_DFI_PHY_LP_STATE, AXI_11_DFI_RST_N_BUF, AXI_11_RDATA, AXI_11_RDATA_PARITY, AXI_11_RID, AXI_11_RLAST, AXI_11_RRESP, AXI_11_RVALID, AXI_11_WREADY, AXI_12_ARREADY, AXI_12_AWREADY, AXI_12_BID, AXI_12_BRESP, AXI_12_BVALID, AXI_12_DFI_AW_AERR_N, AXI_12_DFI_CLK_BUF, AXI_12_DFI_DBI_BYTE_DISABLE, AXI_12_DFI_DW_RDDATA_DBI, AXI_12_DFI_DW_RDDATA_DERR, AXI_12_DFI_DW_RDDATA_VALID, AXI_12_DFI_INIT_COMPLETE +, AXI_12_DFI_PHYUPD_REQ, AXI_12_DFI_PHY_LP_STATE, AXI_12_DFI_RST_N_BUF, AXI_12_MC_STATUS, AXI_12_PHY_STATUS, AXI_12_RDATA, AXI_12_RDATA_PARITY, AXI_12_RID, AXI_12_RLAST, AXI_12_RRESP, AXI_12_RVALID, AXI_12_WREADY, AXI_13_ARREADY, AXI_13_AWREADY, AXI_13_BID, AXI_13_BRESP, AXI_13_BVALID, AXI_13_DFI_AW_AERR_N, AXI_13_DFI_CLK_BUF, AXI_13_DFI_DBI_BYTE_DISABLE, AXI_13_DFI_DW_RDDATA_DBI +, AXI_13_DFI_DW_RDDATA_DERR, AXI_13_DFI_DW_RDDATA_VALID, AXI_13_DFI_INIT_COMPLETE, AXI_13_DFI_PHYUPD_REQ, AXI_13_DFI_PHY_LP_STATE, AXI_13_DFI_RST_N_BUF, AXI_13_RDATA, AXI_13_RDATA_PARITY, AXI_13_RID, AXI_13_RLAST, AXI_13_RRESP, AXI_13_RVALID, AXI_13_WREADY, AXI_14_ARREADY, AXI_14_AWREADY, AXI_14_BID, AXI_14_BRESP, AXI_14_BVALID, AXI_14_DFI_AW_AERR_N, AXI_14_DFI_CLK_BUF, AXI_14_DFI_DBI_BYTE_DISABLE +, AXI_14_DFI_DW_RDDATA_DBI, AXI_14_DFI_DW_RDDATA_DERR, AXI_14_DFI_DW_RDDATA_VALID, AXI_14_DFI_INIT_COMPLETE, AXI_14_DFI_PHYUPD_REQ, AXI_14_DFI_PHY_LP_STATE, AXI_14_DFI_RST_N_BUF, AXI_14_MC_STATUS, AXI_14_PHY_STATUS, AXI_14_RDATA, AXI_14_RDATA_PARITY, AXI_14_RID, AXI_14_RLAST, AXI_14_RRESP, AXI_14_RVALID, AXI_14_WREADY, AXI_15_ARREADY, AXI_15_AWREADY, AXI_15_BID, AXI_15_BRESP, AXI_15_BVALID +, AXI_15_DFI_AW_AERR_N, AXI_15_DFI_CLK_BUF, AXI_15_DFI_DBI_BYTE_DISABLE, AXI_15_DFI_DW_RDDATA_DBI, AXI_15_DFI_DW_RDDATA_DERR, AXI_15_DFI_DW_RDDATA_VALID, AXI_15_DFI_INIT_COMPLETE, AXI_15_DFI_PHYUPD_REQ, AXI_15_DFI_PHY_LP_STATE, AXI_15_DFI_RST_N_BUF, AXI_15_RDATA, AXI_15_RDATA_PARITY, AXI_15_RID, AXI_15_RLAST, AXI_15_RRESP, AXI_15_RVALID, AXI_15_WREADY, AXI_16_ARREADY, AXI_16_AWREADY, AXI_16_BID, AXI_16_BRESP +, AXI_16_BVALID, AXI_16_DFI_AW_AERR_N, AXI_16_DFI_CLK_BUF, AXI_16_DFI_DBI_BYTE_DISABLE, AXI_16_DFI_DW_RDDATA_DBI, AXI_16_DFI_DW_RDDATA_DERR, AXI_16_DFI_DW_RDDATA_VALID, AXI_16_DFI_INIT_COMPLETE, AXI_16_DFI_PHYUPD_REQ, AXI_16_DFI_PHY_LP_STATE, AXI_16_DFI_RST_N_BUF, AXI_16_MC_STATUS, AXI_16_PHY_STATUS, AXI_16_RDATA, AXI_16_RDATA_PARITY, AXI_16_RID, AXI_16_RLAST, AXI_16_RRESP, AXI_16_RVALID, AXI_16_WREADY, AXI_17_ARREADY +, AXI_17_AWREADY, AXI_17_BID, AXI_17_BRESP, AXI_17_BVALID, AXI_17_DFI_AW_AERR_N, AXI_17_DFI_CLK_BUF, AXI_17_DFI_DBI_BYTE_DISABLE, AXI_17_DFI_DW_RDDATA_DBI, AXI_17_DFI_DW_RDDATA_DERR, AXI_17_DFI_DW_RDDATA_VALID, AXI_17_DFI_INIT_COMPLETE, AXI_17_DFI_PHYUPD_REQ, AXI_17_DFI_PHY_LP_STATE, AXI_17_DFI_RST_N_BUF, AXI_17_RDATA, AXI_17_RDATA_PARITY, AXI_17_RID, AXI_17_RLAST, AXI_17_RRESP, AXI_17_RVALID, AXI_17_WREADY +, AXI_18_ARREADY, AXI_18_AWREADY, AXI_18_BID, AXI_18_BRESP, AXI_18_BVALID, AXI_18_DFI_AW_AERR_N, AXI_18_DFI_CLK_BUF, AXI_18_DFI_DBI_BYTE_DISABLE, AXI_18_DFI_DW_RDDATA_DBI, AXI_18_DFI_DW_RDDATA_DERR, AXI_18_DFI_DW_RDDATA_VALID, AXI_18_DFI_INIT_COMPLETE, AXI_18_DFI_PHYUPD_REQ, AXI_18_DFI_PHY_LP_STATE, AXI_18_DFI_RST_N_BUF, AXI_18_MC_STATUS, AXI_18_PHY_STATUS, AXI_18_RDATA, AXI_18_RDATA_PARITY, AXI_18_RID, AXI_18_RLAST +, AXI_18_RRESP, AXI_18_RVALID, AXI_18_WREADY, AXI_19_ARREADY, AXI_19_AWREADY, AXI_19_BID, AXI_19_BRESP, AXI_19_BVALID, AXI_19_DFI_AW_AERR_N, AXI_19_DFI_CLK_BUF, AXI_19_DFI_DBI_BYTE_DISABLE, AXI_19_DFI_DW_RDDATA_DBI, AXI_19_DFI_DW_RDDATA_DERR, AXI_19_DFI_DW_RDDATA_VALID, AXI_19_DFI_INIT_COMPLETE, AXI_19_DFI_PHYUPD_REQ, AXI_19_DFI_PHY_LP_STATE, AXI_19_DFI_RST_N_BUF, AXI_19_RDATA, AXI_19_RDATA_PARITY, AXI_19_RID +, AXI_19_RLAST, AXI_19_RRESP, AXI_19_RVALID, AXI_19_WREADY, AXI_20_ARREADY, AXI_20_AWREADY, AXI_20_BID, AXI_20_BRESP, AXI_20_BVALID, AXI_20_DFI_AW_AERR_N, AXI_20_DFI_CLK_BUF, AXI_20_DFI_DBI_BYTE_DISABLE, AXI_20_DFI_DW_RDDATA_DBI, AXI_20_DFI_DW_RDDATA_DERR, AXI_20_DFI_DW_RDDATA_VALID, AXI_20_DFI_INIT_COMPLETE, AXI_20_DFI_PHYUPD_REQ, AXI_20_DFI_PHY_LP_STATE, AXI_20_DFI_RST_N_BUF, AXI_20_MC_STATUS, AXI_20_PHY_STATUS +, AXI_20_RDATA, AXI_20_RDATA_PARITY, AXI_20_RID, AXI_20_RLAST, AXI_20_RRESP, AXI_20_RVALID, AXI_20_WREADY, AXI_21_ARREADY, AXI_21_AWREADY, AXI_21_BID, AXI_21_BRESP, AXI_21_BVALID, AXI_21_DFI_AW_AERR_N, AXI_21_DFI_CLK_BUF, AXI_21_DFI_DBI_BYTE_DISABLE, AXI_21_DFI_DW_RDDATA_DBI, AXI_21_DFI_DW_RDDATA_DERR, AXI_21_DFI_DW_RDDATA_VALID, AXI_21_DFI_INIT_COMPLETE, AXI_21_DFI_PHYUPD_REQ, AXI_21_DFI_PHY_LP_STATE +, AXI_21_DFI_RST_N_BUF, AXI_21_RDATA, AXI_21_RDATA_PARITY, AXI_21_RID, AXI_21_RLAST, AXI_21_RRESP, AXI_21_RVALID, AXI_21_WREADY, AXI_22_ARREADY, AXI_22_AWREADY, AXI_22_BID, AXI_22_BRESP, AXI_22_BVALID, AXI_22_DFI_AW_AERR_N, AXI_22_DFI_CLK_BUF, AXI_22_DFI_DBI_BYTE_DISABLE, AXI_22_DFI_DW_RDDATA_DBI, AXI_22_DFI_DW_RDDATA_DERR, AXI_22_DFI_DW_RDDATA_VALID, AXI_22_DFI_INIT_COMPLETE, AXI_22_DFI_PHYUPD_REQ +, AXI_22_DFI_PHY_LP_STATE, AXI_22_DFI_RST_N_BUF, AXI_22_MC_STATUS, AXI_22_PHY_STATUS, AXI_22_RDATA, AXI_22_RDATA_PARITY, AXI_22_RID, AXI_22_RLAST, AXI_22_RRESP, AXI_22_RVALID, AXI_22_WREADY, AXI_23_ARREADY, AXI_23_AWREADY, AXI_23_BID, AXI_23_BRESP, AXI_23_BVALID, AXI_23_DFI_AW_AERR_N, AXI_23_DFI_CLK_BUF, AXI_23_DFI_DBI_BYTE_DISABLE, AXI_23_DFI_DW_RDDATA_DBI, AXI_23_DFI_DW_RDDATA_DERR +, AXI_23_DFI_DW_RDDATA_VALID, AXI_23_DFI_INIT_COMPLETE, AXI_23_DFI_PHYUPD_REQ, AXI_23_DFI_PHY_LP_STATE, AXI_23_DFI_RST_N_BUF, AXI_23_RDATA, AXI_23_RDATA_PARITY, AXI_23_RID, AXI_23_RLAST, AXI_23_RRESP, AXI_23_RVALID, AXI_23_WREADY, AXI_24_ARREADY, AXI_24_AWREADY, AXI_24_BID, AXI_24_BRESP, AXI_24_BVALID, AXI_24_DFI_AW_AERR_N, AXI_24_DFI_CLK_BUF, AXI_24_DFI_DBI_BYTE_DISABLE, AXI_24_DFI_DW_RDDATA_DBI +, AXI_24_DFI_DW_RDDATA_DERR, AXI_24_DFI_DW_RDDATA_VALID, AXI_24_DFI_INIT_COMPLETE, AXI_24_DFI_PHYUPD_REQ, AXI_24_DFI_PHY_LP_STATE, AXI_24_DFI_RST_N_BUF, AXI_24_MC_STATUS, AXI_24_PHY_STATUS, AXI_24_RDATA, AXI_24_RDATA_PARITY, AXI_24_RID, AXI_24_RLAST, AXI_24_RRESP, AXI_24_RVALID, AXI_24_WREADY, AXI_25_ARREADY, AXI_25_AWREADY, AXI_25_BID, AXI_25_BRESP, AXI_25_BVALID, AXI_25_DFI_AW_AERR_N +, AXI_25_DFI_CLK_BUF, AXI_25_DFI_DBI_BYTE_DISABLE, AXI_25_DFI_DW_RDDATA_DBI, AXI_25_DFI_DW_RDDATA_DERR, AXI_25_DFI_DW_RDDATA_VALID, AXI_25_DFI_INIT_COMPLETE, AXI_25_DFI_PHYUPD_REQ, AXI_25_DFI_PHY_LP_STATE, AXI_25_DFI_RST_N_BUF, AXI_25_RDATA, AXI_25_RDATA_PARITY, AXI_25_RID, AXI_25_RLAST, AXI_25_RRESP, AXI_25_RVALID, AXI_25_WREADY, AXI_26_ARREADY, AXI_26_AWREADY, AXI_26_BID, AXI_26_BRESP, AXI_26_BVALID +, AXI_26_DFI_AW_AERR_N, AXI_26_DFI_CLK_BUF, AXI_26_DFI_DBI_BYTE_DISABLE, AXI_26_DFI_DW_RDDATA_DBI, AXI_26_DFI_DW_RDDATA_DERR, AXI_26_DFI_DW_RDDATA_VALID, AXI_26_DFI_INIT_COMPLETE, AXI_26_DFI_PHYUPD_REQ, AXI_26_DFI_PHY_LP_STATE, AXI_26_DFI_RST_N_BUF, AXI_26_MC_STATUS, AXI_26_PHY_STATUS, AXI_26_RDATA, AXI_26_RDATA_PARITY, AXI_26_RID, AXI_26_RLAST, AXI_26_RRESP, AXI_26_RVALID, AXI_26_WREADY, AXI_27_ARREADY, AXI_27_AWREADY +, AXI_27_BID, AXI_27_BRESP, AXI_27_BVALID, AXI_27_DFI_AW_AERR_N, AXI_27_DFI_CLK_BUF, AXI_27_DFI_DBI_BYTE_DISABLE, AXI_27_DFI_DW_RDDATA_DBI, AXI_27_DFI_DW_RDDATA_DERR, AXI_27_DFI_DW_RDDATA_VALID, AXI_27_DFI_INIT_COMPLETE, AXI_27_DFI_PHYUPD_REQ, AXI_27_DFI_PHY_LP_STATE, AXI_27_DFI_RST_N_BUF, AXI_27_RDATA, AXI_27_RDATA_PARITY, AXI_27_RID, AXI_27_RLAST, AXI_27_RRESP, AXI_27_RVALID, AXI_27_WREADY, AXI_28_ARREADY +, AXI_28_AWREADY, AXI_28_BID, AXI_28_BRESP, AXI_28_BVALID, AXI_28_DFI_AW_AERR_N, AXI_28_DFI_CLK_BUF, AXI_28_DFI_DBI_BYTE_DISABLE, AXI_28_DFI_DW_RDDATA_DBI, AXI_28_DFI_DW_RDDATA_DERR, AXI_28_DFI_DW_RDDATA_VALID, AXI_28_DFI_INIT_COMPLETE, AXI_28_DFI_PHYUPD_REQ, AXI_28_DFI_PHY_LP_STATE, AXI_28_DFI_RST_N_BUF, AXI_28_MC_STATUS, AXI_28_PHY_STATUS, AXI_28_RDATA, AXI_28_RDATA_PARITY, AXI_28_RID, AXI_28_RLAST, AXI_28_RRESP +, AXI_28_RVALID, AXI_28_WREADY, AXI_29_ARREADY, AXI_29_AWREADY, AXI_29_BID, AXI_29_BRESP, AXI_29_BVALID, AXI_29_DFI_AW_AERR_N, AXI_29_DFI_CLK_BUF, AXI_29_DFI_DBI_BYTE_DISABLE, AXI_29_DFI_DW_RDDATA_DBI, AXI_29_DFI_DW_RDDATA_DERR, AXI_29_DFI_DW_RDDATA_VALID, AXI_29_DFI_INIT_COMPLETE, AXI_29_DFI_PHYUPD_REQ, AXI_29_DFI_PHY_LP_STATE, AXI_29_DFI_RST_N_BUF, AXI_29_RDATA, AXI_29_RDATA_PARITY, AXI_29_RID, AXI_29_RLAST +, AXI_29_RRESP, AXI_29_RVALID, AXI_29_WREADY, AXI_30_ARREADY, AXI_30_AWREADY, AXI_30_BID, AXI_30_BRESP, AXI_30_BVALID, AXI_30_DFI_AW_AERR_N, AXI_30_DFI_CLK_BUF, AXI_30_DFI_DBI_BYTE_DISABLE, AXI_30_DFI_DW_RDDATA_DBI, AXI_30_DFI_DW_RDDATA_DERR, AXI_30_DFI_DW_RDDATA_VALID, AXI_30_DFI_INIT_COMPLETE, AXI_30_DFI_PHYUPD_REQ, AXI_30_DFI_PHY_LP_STATE, AXI_30_DFI_RST_N_BUF, AXI_30_MC_STATUS, AXI_30_PHY_STATUS, AXI_30_RDATA +, AXI_30_RDATA_PARITY, AXI_30_RID, AXI_30_RLAST, AXI_30_RRESP, AXI_30_RVALID, AXI_30_WREADY, AXI_31_ARREADY, AXI_31_AWREADY, AXI_31_BID, AXI_31_BRESP, AXI_31_BVALID, AXI_31_DFI_AW_AERR_N, AXI_31_DFI_CLK_BUF, AXI_31_DFI_DBI_BYTE_DISABLE, AXI_31_DFI_DW_RDDATA_DBI, AXI_31_DFI_DW_RDDATA_DERR, AXI_31_DFI_DW_RDDATA_VALID, AXI_31_DFI_INIT_COMPLETE, AXI_31_DFI_PHYUPD_REQ, AXI_31_DFI_PHY_LP_STATE, AXI_31_DFI_RST_N_BUF +, AXI_31_RDATA, AXI_31_RDATA_PARITY, AXI_31_RID, AXI_31_RLAST, AXI_31_RRESP, AXI_31_RVALID, AXI_31_WREADY, DRAM_0_STAT_CATTRIP, DRAM_0_STAT_TEMP, DRAM_1_STAT_CATTRIP, DRAM_1_STAT_TEMP, APB_0_PADDR, APB_0_PCLK, APB_0_PENABLE, APB_0_PRESET_N, APB_0_PSEL, APB_0_PWDATA, APB_0_PWRITE, APB_1_PADDR, APB_1_PCLK, APB_1_PENABLE +, APB_1_PRESET_N, APB_1_PSEL, APB_1_PWDATA, APB_1_PWRITE, AXI_00_ACLK, AXI_00_ARADDR, AXI_00_ARBURST, AXI_00_ARESET_N, AXI_00_ARID, AXI_00_ARLEN, AXI_00_ARSIZE, AXI_00_ARVALID, AXI_00_AWADDR, AXI_00_AWBURST, AXI_00_AWID, AXI_00_AWLEN, AXI_00_AWSIZE, AXI_00_AWVALID, AXI_00_BREADY, AXI_00_DFI_LP_PWR_X_REQ, AXI_00_RREADY +, AXI_00_WDATA, AXI_00_WDATA_PARITY, AXI_00_WLAST, AXI_00_WSTRB, AXI_00_WVALID, AXI_01_ACLK, AXI_01_ARADDR, AXI_01_ARBURST, AXI_01_ARESET_N, AXI_01_ARID, AXI_01_ARLEN, AXI_01_ARSIZE, AXI_01_ARVALID, AXI_01_AWADDR, AXI_01_AWBURST, AXI_01_AWID, AXI_01_AWLEN, AXI_01_AWSIZE, AXI_01_AWVALID, AXI_01_BREADY, AXI_01_DFI_LP_PWR_X_REQ +, AXI_01_RREADY, AXI_01_WDATA, AXI_01_WDATA_PARITY, AXI_01_WLAST, AXI_01_WSTRB, AXI_01_WVALID, AXI_02_ACLK, AXI_02_ARADDR, AXI_02_ARBURST, AXI_02_ARESET_N, AXI_02_ARID, AXI_02_ARLEN, AXI_02_ARSIZE, AXI_02_ARVALID, AXI_02_AWADDR, AXI_02_AWBURST, AXI_02_AWID, AXI_02_AWLEN, AXI_02_AWSIZE, AXI_02_AWVALID, AXI_02_BREADY +, AXI_02_DFI_LP_PWR_X_REQ, AXI_02_RREADY, AXI_02_WDATA, AXI_02_WDATA_PARITY, AXI_02_WLAST, AXI_02_WSTRB, AXI_02_WVALID, AXI_03_ACLK, AXI_03_ARADDR, AXI_03_ARBURST, AXI_03_ARESET_N, AXI_03_ARID, AXI_03_ARLEN, AXI_03_ARSIZE, AXI_03_ARVALID, AXI_03_AWADDR, AXI_03_AWBURST, AXI_03_AWID, AXI_03_AWLEN, AXI_03_AWSIZE, AXI_03_AWVALID +, AXI_03_BREADY, AXI_03_DFI_LP_PWR_X_REQ, AXI_03_RREADY, AXI_03_WDATA, AXI_03_WDATA_PARITY, AXI_03_WLAST, AXI_03_WSTRB, AXI_03_WVALID, AXI_04_ACLK, AXI_04_ARADDR, AXI_04_ARBURST, AXI_04_ARESET_N, AXI_04_ARID, AXI_04_ARLEN, AXI_04_ARSIZE, AXI_04_ARVALID, AXI_04_AWADDR, AXI_04_AWBURST, AXI_04_AWID, AXI_04_AWLEN, AXI_04_AWSIZE +, AXI_04_AWVALID, AXI_04_BREADY, AXI_04_DFI_LP_PWR_X_REQ, AXI_04_RREADY, AXI_04_WDATA, AXI_04_WDATA_PARITY, AXI_04_WLAST, AXI_04_WSTRB, AXI_04_WVALID, AXI_05_ACLK, AXI_05_ARADDR, AXI_05_ARBURST, AXI_05_ARESET_N, AXI_05_ARID, AXI_05_ARLEN, AXI_05_ARSIZE, AXI_05_ARVALID, AXI_05_AWADDR, AXI_05_AWBURST, AXI_05_AWID, AXI_05_AWLEN +, AXI_05_AWSIZE, AXI_05_AWVALID, AXI_05_BREADY, AXI_05_DFI_LP_PWR_X_REQ, AXI_05_RREADY, AXI_05_WDATA, AXI_05_WDATA_PARITY, AXI_05_WLAST, AXI_05_WSTRB, AXI_05_WVALID, AXI_06_ACLK, AXI_06_ARADDR, AXI_06_ARBURST, AXI_06_ARESET_N, AXI_06_ARID, AXI_06_ARLEN, AXI_06_ARSIZE, AXI_06_ARVALID, AXI_06_AWADDR, AXI_06_AWBURST, AXI_06_AWID +, AXI_06_AWLEN, AXI_06_AWSIZE, AXI_06_AWVALID, AXI_06_BREADY, AXI_06_DFI_LP_PWR_X_REQ, AXI_06_RREADY, AXI_06_WDATA, AXI_06_WDATA_PARITY, AXI_06_WLAST, AXI_06_WSTRB, AXI_06_WVALID, AXI_07_ACLK, AXI_07_ARADDR, AXI_07_ARBURST, AXI_07_ARESET_N, AXI_07_ARID, AXI_07_ARLEN, AXI_07_ARSIZE, AXI_07_ARVALID, AXI_07_AWADDR, AXI_07_AWBURST +, AXI_07_AWID, AXI_07_AWLEN, AXI_07_AWSIZE, AXI_07_AWVALID, AXI_07_BREADY, AXI_07_DFI_LP_PWR_X_REQ, AXI_07_RREADY, AXI_07_WDATA, AXI_07_WDATA_PARITY, AXI_07_WLAST, AXI_07_WSTRB, AXI_07_WVALID, AXI_08_ACLK, AXI_08_ARADDR, AXI_08_ARBURST, AXI_08_ARESET_N, AXI_08_ARID, AXI_08_ARLEN, AXI_08_ARSIZE, AXI_08_ARVALID, AXI_08_AWADDR +, AXI_08_AWBURST, AXI_08_AWID, AXI_08_AWLEN, AXI_08_AWSIZE, AXI_08_AWVALID, AXI_08_BREADY, AXI_08_DFI_LP_PWR_X_REQ, AXI_08_RREADY, AXI_08_WDATA, AXI_08_WDATA_PARITY, AXI_08_WLAST, AXI_08_WSTRB, AXI_08_WVALID, AXI_09_ACLK, AXI_09_ARADDR, AXI_09_ARBURST, AXI_09_ARESET_N, AXI_09_ARID, AXI_09_ARLEN, AXI_09_ARSIZE, AXI_09_ARVALID +, AXI_09_AWADDR, AXI_09_AWBURST, AXI_09_AWID, AXI_09_AWLEN, AXI_09_AWSIZE, AXI_09_AWVALID, AXI_09_BREADY, AXI_09_DFI_LP_PWR_X_REQ, AXI_09_RREADY, AXI_09_WDATA, AXI_09_WDATA_PARITY, AXI_09_WLAST, AXI_09_WSTRB, AXI_09_WVALID, AXI_10_ACLK, AXI_10_ARADDR, AXI_10_ARBURST, AXI_10_ARESET_N, AXI_10_ARID, AXI_10_ARLEN, AXI_10_ARSIZE +, AXI_10_ARVALID, AXI_10_AWADDR, AXI_10_AWBURST, AXI_10_AWID, AXI_10_AWLEN, AXI_10_AWSIZE, AXI_10_AWVALID, AXI_10_BREADY, AXI_10_DFI_LP_PWR_X_REQ, AXI_10_RREADY, AXI_10_WDATA, AXI_10_WDATA_PARITY, AXI_10_WLAST, AXI_10_WSTRB, AXI_10_WVALID, AXI_11_ACLK, AXI_11_ARADDR, AXI_11_ARBURST, AXI_11_ARESET_N, AXI_11_ARID, AXI_11_ARLEN +, AXI_11_ARSIZE, AXI_11_ARVALID, AXI_11_AWADDR, AXI_11_AWBURST, AXI_11_AWID, AXI_11_AWLEN, AXI_11_AWSIZE, AXI_11_AWVALID, AXI_11_BREADY, AXI_11_DFI_LP_PWR_X_REQ, AXI_11_RREADY, AXI_11_WDATA, AXI_11_WDATA_PARITY, AXI_11_WLAST, AXI_11_WSTRB, AXI_11_WVALID, AXI_12_ACLK, AXI_12_ARADDR, AXI_12_ARBURST, AXI_12_ARESET_N, AXI_12_ARID +, AXI_12_ARLEN, AXI_12_ARSIZE, AXI_12_ARVALID, AXI_12_AWADDR, AXI_12_AWBURST, AXI_12_AWID, AXI_12_AWLEN, AXI_12_AWSIZE, AXI_12_AWVALID, AXI_12_BREADY, AXI_12_DFI_LP_PWR_X_REQ, AXI_12_RREADY, AXI_12_WDATA, AXI_12_WDATA_PARITY, AXI_12_WLAST, AXI_12_WSTRB, AXI_12_WVALID, AXI_13_ACLK, AXI_13_ARADDR, AXI_13_ARBURST, AXI_13_ARESET_N +, AXI_13_ARID, AXI_13_ARLEN, AXI_13_ARSIZE, AXI_13_ARVALID, AXI_13_AWADDR, AXI_13_AWBURST, AXI_13_AWID, AXI_13_AWLEN, AXI_13_AWSIZE, AXI_13_AWVALID, AXI_13_BREADY, AXI_13_DFI_LP_PWR_X_REQ, AXI_13_RREADY, AXI_13_WDATA, AXI_13_WDATA_PARITY, AXI_13_WLAST, AXI_13_WSTRB, AXI_13_WVALID, AXI_14_ACLK, AXI_14_ARADDR, AXI_14_ARBURST +, AXI_14_ARESET_N, AXI_14_ARID, AXI_14_ARLEN, AXI_14_ARSIZE, AXI_14_ARVALID, AXI_14_AWADDR, AXI_14_AWBURST, AXI_14_AWID, AXI_14_AWLEN, AXI_14_AWSIZE, AXI_14_AWVALID, AXI_14_BREADY, AXI_14_DFI_LP_PWR_X_REQ, AXI_14_RREADY, AXI_14_WDATA, AXI_14_WDATA_PARITY, AXI_14_WLAST, AXI_14_WSTRB, AXI_14_WVALID, AXI_15_ACLK, AXI_15_ARADDR +, AXI_15_ARBURST, AXI_15_ARESET_N, AXI_15_ARID, AXI_15_ARLEN, AXI_15_ARSIZE, AXI_15_ARVALID, AXI_15_AWADDR, AXI_15_AWBURST, AXI_15_AWID, AXI_15_AWLEN, AXI_15_AWSIZE, AXI_15_AWVALID, AXI_15_BREADY, AXI_15_DFI_LP_PWR_X_REQ, AXI_15_RREADY, AXI_15_WDATA, AXI_15_WDATA_PARITY, AXI_15_WLAST, AXI_15_WSTRB, AXI_15_WVALID, AXI_16_ACLK +, AXI_16_ARADDR, AXI_16_ARBURST, AXI_16_ARESET_N, AXI_16_ARID, AXI_16_ARLEN, AXI_16_ARSIZE, AXI_16_ARVALID, AXI_16_AWADDR, AXI_16_AWBURST, AXI_16_AWID, AXI_16_AWLEN, AXI_16_AWSIZE, AXI_16_AWVALID, AXI_16_BREADY, AXI_16_DFI_LP_PWR_X_REQ, AXI_16_RREADY, AXI_16_WDATA, AXI_16_WDATA_PARITY, AXI_16_WLAST, AXI_16_WSTRB, AXI_16_WVALID +, AXI_17_ACLK, AXI_17_ARADDR, AXI_17_ARBURST, AXI_17_ARESET_N, AXI_17_ARID, AXI_17_ARLEN, AXI_17_ARSIZE, AXI_17_ARVALID, AXI_17_AWADDR, AXI_17_AWBURST, AXI_17_AWID, AXI_17_AWLEN, AXI_17_AWSIZE, AXI_17_AWVALID, AXI_17_BREADY, AXI_17_DFI_LP_PWR_X_REQ, AXI_17_RREADY, AXI_17_WDATA, AXI_17_WDATA_PARITY, AXI_17_WLAST, AXI_17_WSTRB +, AXI_17_WVALID, AXI_18_ACLK, AXI_18_ARADDR, AXI_18_ARBURST, AXI_18_ARESET_N, AXI_18_ARID, AXI_18_ARLEN, AXI_18_ARSIZE, AXI_18_ARVALID, AXI_18_AWADDR, AXI_18_AWBURST, AXI_18_AWID, AXI_18_AWLEN, AXI_18_AWSIZE, AXI_18_AWVALID, AXI_18_BREADY, AXI_18_DFI_LP_PWR_X_REQ, AXI_18_RREADY, AXI_18_WDATA, AXI_18_WDATA_PARITY, AXI_18_WLAST +, AXI_18_WSTRB, AXI_18_WVALID, AXI_19_ACLK, AXI_19_ARADDR, AXI_19_ARBURST, AXI_19_ARESET_N, AXI_19_ARID, AXI_19_ARLEN, AXI_19_ARSIZE, AXI_19_ARVALID, AXI_19_AWADDR, AXI_19_AWBURST, AXI_19_AWID, AXI_19_AWLEN, AXI_19_AWSIZE, AXI_19_AWVALID, AXI_19_BREADY, AXI_19_DFI_LP_PWR_X_REQ, AXI_19_RREADY, AXI_19_WDATA, AXI_19_WDATA_PARITY +, AXI_19_WLAST, AXI_19_WSTRB, AXI_19_WVALID, AXI_20_ACLK, AXI_20_ARADDR, AXI_20_ARBURST, AXI_20_ARESET_N, AXI_20_ARID, AXI_20_ARLEN, AXI_20_ARSIZE, AXI_20_ARVALID, AXI_20_AWADDR, AXI_20_AWBURST, AXI_20_AWID, AXI_20_AWLEN, AXI_20_AWSIZE, AXI_20_AWVALID, AXI_20_BREADY, AXI_20_DFI_LP_PWR_X_REQ, AXI_20_RREADY, AXI_20_WDATA +, AXI_20_WDATA_PARITY, AXI_20_WLAST, AXI_20_WSTRB, AXI_20_WVALID, AXI_21_ACLK, AXI_21_ARADDR, AXI_21_ARBURST, AXI_21_ARESET_N, AXI_21_ARID, AXI_21_ARLEN, AXI_21_ARSIZE, AXI_21_ARVALID, AXI_21_AWADDR, AXI_21_AWBURST, AXI_21_AWID, AXI_21_AWLEN, AXI_21_AWSIZE, AXI_21_AWVALID, AXI_21_BREADY, AXI_21_DFI_LP_PWR_X_REQ, AXI_21_RREADY +, AXI_21_WDATA, AXI_21_WDATA_PARITY, AXI_21_WLAST, AXI_21_WSTRB, AXI_21_WVALID, AXI_22_ACLK, AXI_22_ARADDR, AXI_22_ARBURST, AXI_22_ARESET_N, AXI_22_ARID, AXI_22_ARLEN, AXI_22_ARSIZE, AXI_22_ARVALID, AXI_22_AWADDR, AXI_22_AWBURST, AXI_22_AWID, AXI_22_AWLEN, AXI_22_AWSIZE, AXI_22_AWVALID, AXI_22_BREADY, AXI_22_DFI_LP_PWR_X_REQ +, AXI_22_RREADY, AXI_22_WDATA, AXI_22_WDATA_PARITY, AXI_22_WLAST, AXI_22_WSTRB, AXI_22_WVALID, AXI_23_ACLK, AXI_23_ARADDR, AXI_23_ARBURST, AXI_23_ARESET_N, AXI_23_ARID, AXI_23_ARLEN, AXI_23_ARSIZE, AXI_23_ARVALID, AXI_23_AWADDR, AXI_23_AWBURST, AXI_23_AWID, AXI_23_AWLEN, AXI_23_AWSIZE, AXI_23_AWVALID, AXI_23_BREADY +, AXI_23_DFI_LP_PWR_X_REQ, AXI_23_RREADY, AXI_23_WDATA, AXI_23_WDATA_PARITY, AXI_23_WLAST, AXI_23_WSTRB, AXI_23_WVALID, AXI_24_ACLK, AXI_24_ARADDR, AXI_24_ARBURST, AXI_24_ARESET_N, AXI_24_ARID, AXI_24_ARLEN, AXI_24_ARSIZE, AXI_24_ARVALID, AXI_24_AWADDR, AXI_24_AWBURST, AXI_24_AWID, AXI_24_AWLEN, AXI_24_AWSIZE, AXI_24_AWVALID +, AXI_24_BREADY, AXI_24_DFI_LP_PWR_X_REQ, AXI_24_RREADY, AXI_24_WDATA, AXI_24_WDATA_PARITY, AXI_24_WLAST, AXI_24_WSTRB, AXI_24_WVALID, AXI_25_ACLK, AXI_25_ARADDR, AXI_25_ARBURST, AXI_25_ARESET_N, AXI_25_ARID, AXI_25_ARLEN, AXI_25_ARSIZE, AXI_25_ARVALID, AXI_25_AWADDR, AXI_25_AWBURST, AXI_25_AWID, AXI_25_AWLEN, AXI_25_AWSIZE +, AXI_25_AWVALID, AXI_25_BREADY, AXI_25_DFI_LP_PWR_X_REQ, AXI_25_RREADY, AXI_25_WDATA, AXI_25_WDATA_PARITY, AXI_25_WLAST, AXI_25_WSTRB, AXI_25_WVALID, AXI_26_ACLK, AXI_26_ARADDR, AXI_26_ARBURST, AXI_26_ARESET_N, AXI_26_ARID, AXI_26_ARLEN, AXI_26_ARSIZE, AXI_26_ARVALID, AXI_26_AWADDR, AXI_26_AWBURST, AXI_26_AWID, AXI_26_AWLEN +, AXI_26_AWSIZE, AXI_26_AWVALID, AXI_26_BREADY, AXI_26_DFI_LP_PWR_X_REQ, AXI_26_RREADY, AXI_26_WDATA, AXI_26_WDATA_PARITY, AXI_26_WLAST, AXI_26_WSTRB, AXI_26_WVALID, AXI_27_ACLK, AXI_27_ARADDR, AXI_27_ARBURST, AXI_27_ARESET_N, AXI_27_ARID, AXI_27_ARLEN, AXI_27_ARSIZE, AXI_27_ARVALID, AXI_27_AWADDR, AXI_27_AWBURST, AXI_27_AWID +, AXI_27_AWLEN, AXI_27_AWSIZE, AXI_27_AWVALID, AXI_27_BREADY, AXI_27_DFI_LP_PWR_X_REQ, AXI_27_RREADY, AXI_27_WDATA, AXI_27_WDATA_PARITY, AXI_27_WLAST, AXI_27_WSTRB, AXI_27_WVALID, AXI_28_ACLK, AXI_28_ARADDR, AXI_28_ARBURST, AXI_28_ARESET_N, AXI_28_ARID, AXI_28_ARLEN, AXI_28_ARSIZE, AXI_28_ARVALID, AXI_28_AWADDR, AXI_28_AWBURST +, AXI_28_AWID, AXI_28_AWLEN, AXI_28_AWSIZE, AXI_28_AWVALID, AXI_28_BREADY, AXI_28_DFI_LP_PWR_X_REQ, AXI_28_RREADY, AXI_28_WDATA, AXI_28_WDATA_PARITY, AXI_28_WLAST, AXI_28_WSTRB, AXI_28_WVALID, AXI_29_ACLK, AXI_29_ARADDR, AXI_29_ARBURST, AXI_29_ARESET_N, AXI_29_ARID, AXI_29_ARLEN, AXI_29_ARSIZE, AXI_29_ARVALID, AXI_29_AWADDR +, AXI_29_AWBURST, AXI_29_AWID, AXI_29_AWLEN, AXI_29_AWSIZE, AXI_29_AWVALID, AXI_29_BREADY, AXI_29_DFI_LP_PWR_X_REQ, AXI_29_RREADY, AXI_29_WDATA, AXI_29_WDATA_PARITY, AXI_29_WLAST, AXI_29_WSTRB, AXI_29_WVALID, AXI_30_ACLK, AXI_30_ARADDR, AXI_30_ARBURST, AXI_30_ARESET_N, AXI_30_ARID, AXI_30_ARLEN, AXI_30_ARSIZE, AXI_30_ARVALID +, AXI_30_AWADDR, AXI_30_AWBURST, AXI_30_AWID, AXI_30_AWLEN, AXI_30_AWSIZE, AXI_30_AWVALID, AXI_30_BREADY, AXI_30_DFI_LP_PWR_X_REQ, AXI_30_RREADY, AXI_30_WDATA, AXI_30_WDATA_PARITY, AXI_30_WLAST, AXI_30_WSTRB, AXI_30_WVALID, AXI_31_ACLK, AXI_31_ARADDR, AXI_31_ARBURST, AXI_31_ARESET_N, AXI_31_ARID, AXI_31_ARLEN, AXI_31_ARSIZE +, AXI_31_ARVALID, AXI_31_AWADDR, AXI_31_AWBURST, AXI_31_AWID, AXI_31_AWLEN, AXI_31_AWSIZE, AXI_31_AWVALID, AXI_31_BREADY, AXI_31_DFI_LP_PWR_X_REQ, AXI_31_RREADY, AXI_31_WDATA, AXI_31_WDATA_PARITY, AXI_31_WLAST, AXI_31_WSTRB, AXI_31_WVALID, BSCAN_DRCK_0, BSCAN_DRCK_1, BSCAN_TCK_0, BSCAN_TCK_1, HBM_REF_CLK_0, HBM_REF_CLK_1 +, MBIST_EN_00, MBIST_EN_01, MBIST_EN_02, MBIST_EN_03, MBIST_EN_04, MBIST_EN_05, MBIST_EN_06, MBIST_EN_07, MBIST_EN_08, MBIST_EN_09, MBIST_EN_10, MBIST_EN_11, MBIST_EN_12, MBIST_EN_13, MBIST_EN_14, MBIST_EN_15); parameter CLK_SEL_00 = "FALSE"; parameter CLK_SEL_01 = "FALSE"; parameter CLK_SEL_02 = "FALSE"; @@ -31096,7 +31672,16 @@ module HBM_TWO_STACK_INTF (...); input MBIST_EN_15; endmodule -module PPC405_ADV (...); +module PPC405_ADV(APUFCMDECODED, APUFCMDECUDIVALID, APUFCMENDIAN, APUFCMFLUSH, APUFCMINSTRVALID, APUFCMLOADDVALID, APUFCMOPERANDVALID, APUFCMWRITEBACKOK, APUFCMXERCA, C405CPMCORESLEEPREQ, C405CPMMSRCE, C405CPMMSREE, C405CPMTIMERIRQ, C405CPMTIMERRESETREQ, C405DBGLOADDATAONAPUDBUS, C405DBGMSRWE, C405DBGSTOPACK, C405DBGWBCOMPLETE, C405DBGWBFULL, C405JTGCAPTUREDR, C405JTGEXTEST +, C405JTGPGMOUT, C405JTGSHIFTDR, C405JTGTDO, C405JTGTDOEN, C405JTGUPDATEDR, C405PLBDCUABORT, C405PLBDCUCACHEABLE, C405PLBDCUGUARDED, C405PLBDCUREQUEST, C405PLBDCURNW, C405PLBDCUSIZE2, C405PLBDCUU0ATTR, C405PLBDCUWRITETHRU, C405PLBICUABORT, C405PLBICUCACHEABLE, C405PLBICUREQUEST, C405PLBICUU0ATTR, C405RSTCHIPRESETREQ, C405RSTCORERESETREQ, C405RSTSYSRESETREQ, C405TRCCYCLE +, C405TRCTRIGGEREVENTOUT, C405XXXMACHINECHECK, DCREMACCLK, DCREMACENABLER, DCREMACREAD, DCREMACWRITE, DSOCMBRAMEN, DSOCMBUSY, DSOCMRDADDRVALID, DSOCMWRADDRVALID, EXTDCRREAD, EXTDCRWRITE, ISOCMBRAMEN, ISOCMBRAMEVENWRITEEN, ISOCMBRAMODDWRITEEN, ISOCMDCRBRAMEVENEN, ISOCMDCRBRAMODDEN, ISOCMDCRBRAMRDSELECT, C405TRCTRIGGEREVENTTYPE, C405PLBDCUPRIORITY, C405PLBICUPRIORITY +, C405TRCEVENEXECUTIONSTATUS, C405TRCODDEXECUTIONSTATUS, C405DBGWBIAR, C405PLBICUABUS, APUFCMDECUDI, APUFCMINSTRUCTION, APUFCMLOADDATA, APUFCMRADATA, APUFCMRBDATA, C405PLBDCUABUS, DCREMACDBUS, DSOCMBRAMWRDBUS, EXTDCRDBUSOUT, ISOCMBRAMWRDBUS, APUFCMLOADBYTEEN, C405TRCTRACESTATUS, DSOCMBRAMBYTEWRITE, C405PLBDCUWRDBUS, C405PLBDCUBE, EXTDCRABUS, C405PLBICUSIZE +, ISOCMBRAMRDABUS, ISOCMBRAMWRABUS, DSOCMBRAMABUS, DCREMACABUS, BRAMDSOCMCLK, BRAMISOCMCLK, CPMC405CLOCK, CPMC405CORECLKINACTIVE, CPMC405CPUCLKEN, CPMC405JTAGCLKEN, CPMC405SYNCBYPASS, CPMC405TIMERCLKEN, CPMC405TIMERTICK, CPMDCRCLK, CPMFCMCLK, DBGC405DEBUGHALT, DBGC405EXTBUSHOLDACK, DBGC405UNCONDDEBUGEVENT, DSOCMRWCOMPLETE, EICC405CRITINPUTIRQ, EICC405EXTINPUTIRQ +, EMACDCRACK, EXTDCRACK, FCMAPUDCDCREN, FCMAPUDCDFORCEALIGN, FCMAPUDCDFORCEBESTEERING, FCMAPUDCDFPUOP, FCMAPUDCDGPRWRITE, FCMAPUDCDLDSTBYTE, FCMAPUDCDLDSTDW, FCMAPUDCDLDSTHW, FCMAPUDCDLDSTQW, FCMAPUDCDLDSTWD, FCMAPUDCDLOAD, FCMAPUDCDPRIVOP, FCMAPUDCDRAEN, FCMAPUDCDRBEN, FCMAPUDCDSTORE, FCMAPUDCDTRAPBE, FCMAPUDCDTRAPLE, FCMAPUDCDUPDATE, FCMAPUDCDXERCAEN +, FCMAPUDCDXEROVEN, FCMAPUDECODEBUSY, FCMAPUDONE, FCMAPUEXCEPTION, FCMAPUEXEBLOCKINGMCO, FCMAPUEXENONBLOCKINGMCO, FCMAPUINSTRACK, FCMAPULOADWAIT, FCMAPURESULTVALID, FCMAPUSLEEPNOTREADY, FCMAPUXERCA, FCMAPUXEROV, JTGC405BNDSCANTDO, JTGC405TCK, JTGC405TDI, JTGC405TMS, JTGC405TRSTNEG, MCBCPUCLKEN, MCBJTAGEN, MCBTIMEREN, MCPPCRST +, PLBC405DCUADDRACK, PLBC405DCUBUSY, PLBC405DCUERR, PLBC405DCURDDACK, PLBC405DCUSSIZE1, PLBC405DCUWRDACK, PLBC405ICUADDRACK, PLBC405ICUBUSY, PLBC405ICUERR, PLBC405ICURDDACK, PLBC405ICUSSIZE1, PLBCLK, RSTC405RESETCHIP, RSTC405RESETCORE, RSTC405RESETSYS, TIEC405DETERMINISTICMULT, TIEC405DISOPERANDFWD, TIEC405MMUEN, TIEPVRBIT10, TIEPVRBIT11, TIEPVRBIT28 +, TIEPVRBIT29, TIEPVRBIT30, TIEPVRBIT31, TIEPVRBIT8, TIEPVRBIT9, TRCC405TRACEDISABLE, TRCC405TRIGGEREVENTIN, TIEAPUCONTROL, TIEAPUUDI1, TIEAPUUDI2, TIEAPUUDI3, TIEAPUUDI4, TIEAPUUDI5, TIEAPUUDI6, TIEAPUUDI7, TIEAPUUDI8, FCMAPUEXECRFIELD, BRAMDSOCMRDDBUS, BRAMISOCMDCRRDDBUS, EMACDCRDBUS, EXTDCRDBUSIN +, FCMAPURESULT, FCMAPUCR, TIEDCRADDR, BRAMISOCMRDDBUS, PLBC405DCURDDBUS, PLBC405ICURDDBUS, DSARCVALUE, DSCNTLVALUE, ISARCVALUE, ISCNTLVALUE, PLBC405DCURDWDADDR, PLBC405ICURDWDADDR); parameter in_delay=100; parameter out_delay=100; output APUFCMDECODED; @@ -31302,7 +31887,22 @@ module PPC405_ADV (...); input [1:3] PLBC405ICURDWDADDR; endmodule -module PPC440 (...); +module PPC440(APUFCMDECFPUOP, APUFCMDECLOAD, APUFCMDECNONAUTON, APUFCMDECSTORE, APUFCMDECUDIVALID, APUFCMENDIAN, APUFCMFLUSH, APUFCMINSTRVALID, APUFCMLOADDVALID, APUFCMMSRFE0, APUFCMMSRFE1, APUFCMNEXTINSTRREADY, APUFCMOPERANDVALID, APUFCMWRITEBACKOK, C440CPMCORESLEEPREQ, C440CPMDECIRPTREQ, C440CPMFITIRPTREQ, C440CPMMSRCE, C440CPMMSREE, C440CPMTIMERRESETREQ, C440CPMWDIRPTREQ +, C440JTGTDO, C440JTGTDOEN, C440MACHINECHECK, C440RSTCHIPRESETREQ, C440RSTCORERESETREQ, C440RSTSYSTEMRESETREQ, C440TRCCYCLE, C440TRCTRIGGEREVENTOUT, DMA0LLRSTENGINEACK, DMA0LLRXDSTRDYN, DMA0LLTXEOFN, DMA0LLTXEOPN, DMA0LLTXSOFN, DMA0LLTXSOPN, DMA0LLTXSRCRDYN, DMA0RXIRQ, DMA0TXIRQ, DMA1LLRSTENGINEACK, DMA1LLRXDSTRDYN, DMA1LLTXEOFN, DMA1LLTXEOPN +, DMA1LLTXSOFN, DMA1LLTXSOPN, DMA1LLTXSRCRDYN, DMA1RXIRQ, DMA1TXIRQ, DMA2LLRSTENGINEACK, DMA2LLRXDSTRDYN, DMA2LLTXEOFN, DMA2LLTXEOPN, DMA2LLTXSOFN, DMA2LLTXSOPN, DMA2LLTXSRCRDYN, DMA2RXIRQ, DMA2TXIRQ, DMA3LLRSTENGINEACK, DMA3LLRXDSTRDYN, DMA3LLTXEOFN, DMA3LLTXEOPN, DMA3LLTXSOFN, DMA3LLTXSOPN, DMA3LLTXSRCRDYN +, DMA3RXIRQ, DMA3TXIRQ, MIMCADDRESSVALID, MIMCBANKCONFLICT, MIMCREADNOTWRITE, MIMCROWCONFLICT, MIMCWRITEDATAVALID, PPCCPMINTERCONNECTBUSY, PPCDMDCRREAD, PPCDMDCRWRITE, PPCDSDCRACK, PPCDSDCRTIMEOUTWAIT, PPCEICINTERCONNECTIRQ, PPCMPLBABORT, PPCMPLBBUSLOCK, PPCMPLBLOCKERR, PPCMPLBRDBURST, PPCMPLBREQUEST, PPCMPLBRNW, PPCMPLBWRBURST, PPCS0PLBADDRACK +, PPCS0PLBRDBTERM, PPCS0PLBRDCOMP, PPCS0PLBRDDACK, PPCS0PLBREARBITRATE, PPCS0PLBWAIT, PPCS0PLBWRBTERM, PPCS0PLBWRCOMP, PPCS0PLBWRDACK, PPCS1PLBADDRACK, PPCS1PLBRDBTERM, PPCS1PLBRDCOMP, PPCS1PLBRDDACK, PPCS1PLBREARBITRATE, PPCS1PLBWAIT, PPCS1PLBWRBTERM, PPCS1PLBWRCOMP, PPCS1PLBWRDACK, APUFCMLOADDATA, MIMCWRITEDATA, PPCMPLBWRDBUS, PPCS0PLBRDDBUS +, PPCS1PLBRDDBUS, C440TRCTRIGGEREVENTTYPE, MIMCBYTEENABLE, PPCMPLBBE, PPCMPLBTATTRIBUTE, PPCMPLBPRIORITY, PPCS0PLBSSIZE, PPCS1PLBSSIZE, APUFCMDECLDSTXFERSIZE, C440TRCBRANCHSTATUS, PPCMPLBTYPE, APUFCMINSTRUCTION, APUFCMRADATA, APUFCMRBDATA, DMA0LLTXD, DMA1LLTXD, DMA2LLTXD, DMA3LLTXD, PPCDMDCRDBUSOUT, PPCDSDCRDBUSIN, PPCMPLBABUS +, MIMCADDRESS, APUFCMDECUDI, APUFCMLOADBYTEADDR, DMA0LLTXREM, DMA1LLTXREM, DMA2LLTXREM, DMA3LLTXREM, PPCMPLBSIZE, PPCS0PLBMBUSY, PPCS0PLBMIRQ, PPCS0PLBMRDERR, PPCS0PLBMWRERR, PPCS0PLBRDWDADDR, PPCS1PLBMBUSY, PPCS1PLBMIRQ, PPCS1PLBMRDERR, PPCS1PLBMWRERR, PPCS1PLBRDWDADDR, C440TRCEXECUTIONSTATUS, C440TRCTRACESTATUS, C440DBGSYSTEMCONTROL +, PPCDMDCRABUS, PPCDMDCRUABUS, PPCMPLBUABUS, CPMC440CLK, CPMC440CLKEN, CPMC440CORECLOCKINACTIVE, CPMC440TIMERCLOCK, CPMDCRCLK, CPMDMA0LLCLK, CPMDMA1LLCLK, CPMDMA2LLCLK, CPMDMA3LLCLK, CPMFCMCLK, CPMINTERCONNECTCLK, CPMINTERCONNECTCLKEN, CPMINTERCONNECTCLKNTO1, CPMMCCLK, CPMPPCMPLBCLK, CPMPPCS0PLBCLK, CPMPPCS1PLBCLK, DBGC440DEBUGHALT +, DBGC440UNCONDDEBUGEVENT, DCRPPCDMACK, DCRPPCDMTIMEOUTWAIT, DCRPPCDSREAD, DCRPPCDSWRITE, EICC440CRITIRQ, EICC440EXTIRQ, FCMAPUCONFIRMINSTR, FCMAPUDONE, FCMAPUEXCEPTION, FCMAPUFPSCRFEX, FCMAPURESULTVALID, FCMAPUSLEEPNOTREADY, JTGC440TCK, JTGC440TDI, JTGC440TMS, JTGC440TRSTNEG, LLDMA0RSTENGINEREQ, LLDMA0RXEOFN, LLDMA0RXEOPN, LLDMA0RXSOFN +, LLDMA0RXSOPN, LLDMA0RXSRCRDYN, LLDMA0TXDSTRDYN, LLDMA1RSTENGINEREQ, LLDMA1RXEOFN, LLDMA1RXEOPN, LLDMA1RXSOFN, LLDMA1RXSOPN, LLDMA1RXSRCRDYN, LLDMA1TXDSTRDYN, LLDMA2RSTENGINEREQ, LLDMA2RXEOFN, LLDMA2RXEOPN, LLDMA2RXSOFN, LLDMA2RXSOPN, LLDMA2RXSRCRDYN, LLDMA2TXDSTRDYN, LLDMA3RSTENGINEREQ, LLDMA3RXEOFN, LLDMA3RXEOPN, LLDMA3RXSOFN +, LLDMA3RXSOPN, LLDMA3RXSRCRDYN, LLDMA3TXDSTRDYN, MCMIADDRREADYTOACCEPT, MCMIREADDATAERR, MCMIREADDATAVALID, PLBPPCMADDRACK, PLBPPCMMBUSY, PLBPPCMMIRQ, PLBPPCMMRDERR, PLBPPCMMWRERR, PLBPPCMRDBTERM, PLBPPCMRDDACK, PLBPPCMRDPENDREQ, PLBPPCMREARBITRATE, PLBPPCMTIMEOUT, PLBPPCMWRBTERM, PLBPPCMWRDACK, PLBPPCMWRPENDREQ, PLBPPCS0ABORT, PLBPPCS0BUSLOCK +, PLBPPCS0LOCKERR, PLBPPCS0PAVALID, PLBPPCS0RDBURST, PLBPPCS0RDPENDREQ, PLBPPCS0RDPRIM, PLBPPCS0RNW, PLBPPCS0SAVALID, PLBPPCS0WRBURST, PLBPPCS0WRPENDREQ, PLBPPCS0WRPRIM, PLBPPCS1ABORT, PLBPPCS1BUSLOCK, PLBPPCS1LOCKERR, PLBPPCS1PAVALID, PLBPPCS1RDBURST, PLBPPCS1RDPENDREQ, PLBPPCS1RDPRIM, PLBPPCS1RNW, PLBPPCS1SAVALID, PLBPPCS1WRBURST, PLBPPCS1WRPENDREQ +, PLBPPCS1WRPRIM, RSTC440RESETCHIP, RSTC440RESETCORE, RSTC440RESETSYSTEM, TIEC440ENDIANRESET, TRCC440TRACEDISABLE, TRCC440TRIGGEREVENTIN, FCMAPUSTOREDATA, MCMIREADDATA, PLBPPCMRDDBUS, PLBPPCS0WRDBUS, PLBPPCS1WRDBUS, PLBPPCS0BE, PLBPPCS0TATTRIBUTE, PLBPPCS1BE, PLBPPCS1TATTRIBUTE, PLBPPCMRDPENDPRI, PLBPPCMREQPRI, PLBPPCMSSIZE, PLBPPCMWRPENDPRI, PLBPPCS0MASTERID +, PLBPPCS0MSIZE, PLBPPCS0RDPENDPRI, PLBPPCS0REQPRI, PLBPPCS0WRPENDPRI, PLBPPCS1MASTERID, PLBPPCS1MSIZE, PLBPPCS1RDPENDPRI, PLBPPCS1REQPRI, PLBPPCS1WRPENDPRI, TIEC440DCURDLDCACHEPLBPRIO, TIEC440DCURDNONCACHEPLBPRIO, TIEC440DCURDTOUCHPLBPRIO, TIEC440DCURDURGENTPLBPRIO, TIEC440DCUWRFLUSHPLBPRIO, TIEC440DCUWRSTOREPLBPRIO, TIEC440DCUWRURGENTPLBPRIO, TIEC440ICURDFETCHPLBPRIO, TIEC440ICURDSPECPLBPRIO, TIEC440ICURDTOUCHPLBPRIO, TIEDCRBASEADDR, PLBPPCS0TYPE +, PLBPPCS1TYPE, DCRPPCDMDBUSIN, DCRPPCDSDBUSOUT, FCMAPURESULT, LLDMA0RXD, LLDMA1RXD, LLDMA2RXD, LLDMA3RXD, PLBPPCS0ABUS, PLBPPCS1ABUS, FCMAPUCR, LLDMA0RXREM, LLDMA1RXREM, LLDMA2RXREM, LLDMA3RXREM, PLBPPCMRDWDADDR, PLBPPCS0SIZE, PLBPPCS1SIZE, TIEC440ERPNRESET, TIEC440USERRESET, DBGC440SYSTEMSTATUS +, DCRPPCDSABUS, PLBPPCS0UABUS, PLBPPCS1UABUS, TIEC440PIR, TIEC440PVR); parameter CLOCK_DELAY = "FALSE"; parameter DCR_AUTOLOCK_ENABLE = "TRUE"; parameter PPCDM_ASYNCMODE = "FALSE"; @@ -31692,7 +32292,36 @@ module PPC440 (...); endmodule (* keep *) -module PS7 (...); +module PS7(DMA0DAVALID, DMA0DRREADY, DMA0RSTN, DMA1DAVALID, DMA1DRREADY, DMA1RSTN, DMA2DAVALID, DMA2DRREADY, DMA2RSTN, DMA3DAVALID, DMA3DRREADY, DMA3RSTN, EMIOCAN0PHYTX, EMIOCAN1PHYTX, EMIOENET0GMIITXEN, EMIOENET0GMIITXER, EMIOENET0MDIOMDC, EMIOENET0MDIOO, EMIOENET0MDIOTN, EMIOENET0PTPDELAYREQRX, EMIOENET0PTPDELAYREQTX +, EMIOENET0PTPPDELAYREQRX, EMIOENET0PTPPDELAYREQTX, EMIOENET0PTPPDELAYRESPRX, EMIOENET0PTPPDELAYRESPTX, EMIOENET0PTPSYNCFRAMERX, EMIOENET0PTPSYNCFRAMETX, EMIOENET0SOFRX, EMIOENET0SOFTX, EMIOENET1GMIITXEN, EMIOENET1GMIITXER, EMIOENET1MDIOMDC, EMIOENET1MDIOO, EMIOENET1MDIOTN, EMIOENET1PTPDELAYREQRX, EMIOENET1PTPDELAYREQTX, EMIOENET1PTPPDELAYREQRX, EMIOENET1PTPPDELAYREQTX, EMIOENET1PTPPDELAYRESPRX, EMIOENET1PTPPDELAYRESPTX, EMIOENET1PTPSYNCFRAMERX, EMIOENET1PTPSYNCFRAMETX +, EMIOENET1SOFRX, EMIOENET1SOFTX, EMIOI2C0SCLO, EMIOI2C0SCLTN, EMIOI2C0SDAO, EMIOI2C0SDATN, EMIOI2C1SCLO, EMIOI2C1SCLTN, EMIOI2C1SDAO, EMIOI2C1SDATN, EMIOPJTAGTDO, EMIOPJTAGTDTN, EMIOSDIO0BUSPOW, EMIOSDIO0CLK, EMIOSDIO0CMDO, EMIOSDIO0CMDTN, EMIOSDIO0LED, EMIOSDIO1BUSPOW, EMIOSDIO1CLK, EMIOSDIO1CMDO, EMIOSDIO1CMDTN +, EMIOSDIO1LED, EMIOSPI0MO, EMIOSPI0MOTN, EMIOSPI0SCLKO, EMIOSPI0SCLKTN, EMIOSPI0SO, EMIOSPI0SSNTN, EMIOSPI0STN, EMIOSPI1MO, EMIOSPI1MOTN, EMIOSPI1SCLKO, EMIOSPI1SCLKTN, EMIOSPI1SO, EMIOSPI1SSNTN, EMIOSPI1STN, EMIOTRACECTL, EMIOUART0DTRN, EMIOUART0RTSN, EMIOUART0TX, EMIOUART1DTRN, EMIOUART1RTSN +, EMIOUART1TX, EMIOUSB0VBUSPWRSELECT, EMIOUSB1VBUSPWRSELECT, EMIOWDTRSTO, EVENTEVENTO, MAXIGP0ARESETN, MAXIGP0ARVALID, MAXIGP0AWVALID, MAXIGP0BREADY, MAXIGP0RREADY, MAXIGP0WLAST, MAXIGP0WVALID, MAXIGP1ARESETN, MAXIGP1ARVALID, MAXIGP1AWVALID, MAXIGP1BREADY, MAXIGP1RREADY, MAXIGP1WLAST, MAXIGP1WVALID, SAXIACPARESETN, SAXIACPARREADY +, SAXIACPAWREADY, SAXIACPBVALID, SAXIACPRLAST, SAXIACPRVALID, SAXIACPWREADY, SAXIGP0ARESETN, SAXIGP0ARREADY, SAXIGP0AWREADY, SAXIGP0BVALID, SAXIGP0RLAST, SAXIGP0RVALID, SAXIGP0WREADY, SAXIGP1ARESETN, SAXIGP1ARREADY, SAXIGP1AWREADY, SAXIGP1BVALID, SAXIGP1RLAST, SAXIGP1RVALID, SAXIGP1WREADY, SAXIHP0ARESETN, SAXIHP0ARREADY +, SAXIHP0AWREADY, SAXIHP0BVALID, SAXIHP0RLAST, SAXIHP0RVALID, SAXIHP0WREADY, SAXIHP1ARESETN, SAXIHP1ARREADY, SAXIHP1AWREADY, SAXIHP1BVALID, SAXIHP1RLAST, SAXIHP1RVALID, SAXIHP1WREADY, SAXIHP2ARESETN, SAXIHP2ARREADY, SAXIHP2AWREADY, SAXIHP2BVALID, SAXIHP2RLAST, SAXIHP2RVALID, SAXIHP2WREADY, SAXIHP3ARESETN, SAXIHP3ARREADY +, SAXIHP3AWREADY, SAXIHP3BVALID, SAXIHP3RLAST, SAXIHP3RVALID, SAXIHP3WREADY, MAXIGP0ARID, MAXIGP0AWID, MAXIGP0WID, MAXIGP1ARID, MAXIGP1AWID, MAXIGP1WID, DMA0DATYPE, DMA1DATYPE, DMA2DATYPE, DMA3DATYPE, EMIOUSB0PORTINDCTL, EMIOUSB1PORTINDCTL, EVENTSTANDBYWFE, EVENTSTANDBYWFI, MAXIGP0ARBURST, MAXIGP0ARLOCK +, MAXIGP0ARSIZE, MAXIGP0AWBURST, MAXIGP0AWLOCK, MAXIGP0AWSIZE, MAXIGP1ARBURST, MAXIGP1ARLOCK, MAXIGP1ARSIZE, MAXIGP1AWBURST, MAXIGP1AWLOCK, MAXIGP1AWSIZE, SAXIACPBRESP, SAXIACPRRESP, SAXIGP0BRESP, SAXIGP0RRESP, SAXIGP1BRESP, SAXIGP1RRESP, SAXIHP0BRESP, SAXIHP0RRESP, SAXIHP1BRESP, SAXIHP1RRESP, SAXIHP2BRESP +, SAXIHP2RRESP, SAXIHP3BRESP, SAXIHP3RRESP, IRQP2F, EMIOSDIO0BUSVOLT, EMIOSDIO1BUSVOLT, EMIOSPI0SSON, EMIOSPI1SSON, EMIOTTC0WAVEO, EMIOTTC1WAVEO, MAXIGP0ARPROT, MAXIGP0AWPROT, MAXIGP1ARPROT, MAXIGP1AWPROT, SAXIACPBID, SAXIACPRID, SAXIHP0RACOUNT, SAXIHP1RACOUNT, SAXIHP2RACOUNT, SAXIHP3RACOUNT, EMIOTRACEDATA +, FTMTP2FDEBUG, MAXIGP0ARADDR, MAXIGP0AWADDR, MAXIGP0WDATA, MAXIGP1ARADDR, MAXIGP1AWADDR, MAXIGP1WDATA, SAXIGP0RDATA, SAXIGP1RDATA, EMIOSDIO0DATAO, EMIOSDIO0DATATN, EMIOSDIO1DATAO, EMIOSDIO1DATATN, FCLKCLK, FCLKRESETN, FTMTF2PTRIGACK, FTMTP2FTRIG, MAXIGP0ARCACHE, MAXIGP0ARLEN, MAXIGP0ARQOS, MAXIGP0AWCACHE +, MAXIGP0AWLEN, MAXIGP0AWQOS, MAXIGP0WSTRB, MAXIGP1ARCACHE, MAXIGP1ARLEN, MAXIGP1ARQOS, MAXIGP1AWCACHE, MAXIGP1AWLEN, MAXIGP1AWQOS, MAXIGP1WSTRB, SAXIGP0BID, SAXIGP0RID, SAXIGP1BID, SAXIGP1RID, SAXIHP0BID, SAXIHP0RID, SAXIHP0WACOUNT, SAXIHP1BID, SAXIHP1RID, SAXIHP1WACOUNT, SAXIHP2BID +, SAXIHP2RID, SAXIHP2WACOUNT, SAXIHP3BID, SAXIHP3RID, SAXIHP3WACOUNT, EMIOGPIOO, EMIOGPIOTN, SAXIACPRDATA, SAXIHP0RDATA, SAXIHP1RDATA, SAXIHP2RDATA, SAXIHP3RDATA, EMIOENET0GMIITXD, EMIOENET1GMIITXD, SAXIHP0RCOUNT, SAXIHP0WCOUNT, SAXIHP1RCOUNT, SAXIHP1WCOUNT, SAXIHP2RCOUNT, SAXIHP2WCOUNT, SAXIHP3RCOUNT +, SAXIHP3WCOUNT, DDRCASB, DDRCKE, DDRCKN, DDRCKP, DDRCSB, DDRDRSTB, DDRODT, DDRRASB, DDRVRN, DDRVRP, DDRWEB, PSCLK, PSPORB, PSSRSTB, DDRA, DDRBA, DDRDQ, DDRDM, DDRDQSN, DDRDQSP +, MIO, DMA0ACLK, DMA0DAREADY, DMA0DRLAST, DMA0DRVALID, DMA1ACLK, DMA1DAREADY, DMA1DRLAST, DMA1DRVALID, DMA2ACLK, DMA2DAREADY, DMA2DRLAST, DMA2DRVALID, DMA3ACLK, DMA3DAREADY, DMA3DRLAST, DMA3DRVALID, EMIOCAN0PHYRX, EMIOCAN1PHYRX, EMIOENET0EXTINTIN, EMIOENET0GMIICOL +, EMIOENET0GMIICRS, EMIOENET0GMIIRXCLK, EMIOENET0GMIIRXDV, EMIOENET0GMIIRXER, EMIOENET0GMIITXCLK, EMIOENET0MDIOI, EMIOENET1EXTINTIN, EMIOENET1GMIICOL, EMIOENET1GMIICRS, EMIOENET1GMIIRXCLK, EMIOENET1GMIIRXDV, EMIOENET1GMIIRXER, EMIOENET1GMIITXCLK, EMIOENET1MDIOI, EMIOI2C0SCLI, EMIOI2C0SDAI, EMIOI2C1SCLI, EMIOI2C1SDAI, EMIOPJTAGTCK, EMIOPJTAGTDI, EMIOPJTAGTMS +, EMIOSDIO0CDN, EMIOSDIO0CLKFB, EMIOSDIO0CMDI, EMIOSDIO0WP, EMIOSDIO1CDN, EMIOSDIO1CLKFB, EMIOSDIO1CMDI, EMIOSDIO1WP, EMIOSPI0MI, EMIOSPI0SCLKI, EMIOSPI0SI, EMIOSPI0SSIN, EMIOSPI1MI, EMIOSPI1SCLKI, EMIOSPI1SI, EMIOSPI1SSIN, EMIOSRAMINTIN, EMIOTRACECLK, EMIOUART0CTSN, EMIOUART0DCDN, EMIOUART0DSRN +, EMIOUART0RIN, EMIOUART0RX, EMIOUART1CTSN, EMIOUART1DCDN, EMIOUART1DSRN, EMIOUART1RIN, EMIOUART1RX, EMIOUSB0VBUSPWRFAULT, EMIOUSB1VBUSPWRFAULT, EMIOWDTCLKI, EVENTEVENTI, FPGAIDLEN, FTMDTRACEINCLOCK, FTMDTRACEINVALID, MAXIGP0ACLK, MAXIGP0ARREADY, MAXIGP0AWREADY, MAXIGP0BVALID, MAXIGP0RLAST, MAXIGP0RVALID, MAXIGP0WREADY +, MAXIGP1ACLK, MAXIGP1ARREADY, MAXIGP1AWREADY, MAXIGP1BVALID, MAXIGP1RLAST, MAXIGP1RVALID, MAXIGP1WREADY, SAXIACPACLK, SAXIACPARVALID, SAXIACPAWVALID, SAXIACPBREADY, SAXIACPRREADY, SAXIACPWLAST, SAXIACPWVALID, SAXIGP0ACLK, SAXIGP0ARVALID, SAXIGP0AWVALID, SAXIGP0BREADY, SAXIGP0RREADY, SAXIGP0WLAST, SAXIGP0WVALID +, SAXIGP1ACLK, SAXIGP1ARVALID, SAXIGP1AWVALID, SAXIGP1BREADY, SAXIGP1RREADY, SAXIGP1WLAST, SAXIGP1WVALID, SAXIHP0ACLK, SAXIHP0ARVALID, SAXIHP0AWVALID, SAXIHP0BREADY, SAXIHP0RDISSUECAP1EN, SAXIHP0RREADY, SAXIHP0WLAST, SAXIHP0WRISSUECAP1EN, SAXIHP0WVALID, SAXIHP1ACLK, SAXIHP1ARVALID, SAXIHP1AWVALID, SAXIHP1BREADY, SAXIHP1RDISSUECAP1EN +, SAXIHP1RREADY, SAXIHP1WLAST, SAXIHP1WRISSUECAP1EN, SAXIHP1WVALID, SAXIHP2ACLK, SAXIHP2ARVALID, SAXIHP2AWVALID, SAXIHP2BREADY, SAXIHP2RDISSUECAP1EN, SAXIHP2RREADY, SAXIHP2WLAST, SAXIHP2WRISSUECAP1EN, SAXIHP2WVALID, SAXIHP3ACLK, SAXIHP3ARVALID, SAXIHP3AWVALID, SAXIHP3BREADY, SAXIHP3RDISSUECAP1EN, SAXIHP3RREADY, SAXIHP3WLAST, SAXIHP3WRISSUECAP1EN +, SAXIHP3WVALID, MAXIGP0BID, MAXIGP0RID, MAXIGP1BID, MAXIGP1RID, IRQF2P, DMA0DRTYPE, DMA1DRTYPE, DMA2DRTYPE, DMA3DRTYPE, MAXIGP0BRESP, MAXIGP0RRESP, MAXIGP1BRESP, MAXIGP1RRESP, SAXIACPARBURST, SAXIACPARLOCK, SAXIACPARSIZE, SAXIACPAWBURST, SAXIACPAWLOCK, SAXIACPAWSIZE, SAXIGP0ARBURST +, SAXIGP0ARLOCK, SAXIGP0ARSIZE, SAXIGP0AWBURST, SAXIGP0AWLOCK, SAXIGP0AWSIZE, SAXIGP1ARBURST, SAXIGP1ARLOCK, SAXIGP1ARSIZE, SAXIGP1AWBURST, SAXIGP1AWLOCK, SAXIGP1AWSIZE, SAXIHP0ARBURST, SAXIHP0ARLOCK, SAXIHP0ARSIZE, SAXIHP0AWBURST, SAXIHP0AWLOCK, SAXIHP0AWSIZE, SAXIHP1ARBURST, SAXIHP1ARLOCK, SAXIHP1ARSIZE, SAXIHP1AWBURST +, SAXIHP1AWLOCK, SAXIHP1AWSIZE, SAXIHP2ARBURST, SAXIHP2ARLOCK, SAXIHP2ARSIZE, SAXIHP2AWBURST, SAXIHP2AWLOCK, SAXIHP2AWSIZE, SAXIHP3ARBURST, SAXIHP3ARLOCK, SAXIHP3ARSIZE, SAXIHP3AWBURST, SAXIHP3AWLOCK, SAXIHP3AWSIZE, EMIOTTC0CLKI, EMIOTTC1CLKI, SAXIACPARID, SAXIACPARPROT, SAXIACPAWID, SAXIACPAWPROT, SAXIACPWID +, SAXIGP0ARPROT, SAXIGP0AWPROT, SAXIGP1ARPROT, SAXIGP1AWPROT, SAXIHP0ARPROT, SAXIHP0AWPROT, SAXIHP1ARPROT, SAXIHP1AWPROT, SAXIHP2ARPROT, SAXIHP2AWPROT, SAXIHP3ARPROT, SAXIHP3AWPROT, FTMDTRACEINDATA, FTMTF2PDEBUG, MAXIGP0RDATA, MAXIGP1RDATA, SAXIACPARADDR, SAXIACPAWADDR, SAXIGP0ARADDR, SAXIGP0AWADDR, SAXIGP0WDATA +, SAXIGP1ARADDR, SAXIGP1AWADDR, SAXIGP1WDATA, SAXIHP0ARADDR, SAXIHP0AWADDR, SAXIHP1ARADDR, SAXIHP1AWADDR, SAXIHP2ARADDR, SAXIHP2AWADDR, SAXIHP3ARADDR, SAXIHP3AWADDR, DDRARB, EMIOSDIO0DATAI, EMIOSDIO1DATAI, FCLKCLKTRIGN, FTMDTRACEINATID, FTMTF2PTRIG, FTMTP2FTRIGACK, SAXIACPARCACHE, SAXIACPARLEN, SAXIACPARQOS +, SAXIACPAWCACHE, SAXIACPAWLEN, SAXIACPAWQOS, SAXIGP0ARCACHE, SAXIGP0ARLEN, SAXIGP0ARQOS, SAXIGP0AWCACHE, SAXIGP0AWLEN, SAXIGP0AWQOS, SAXIGP0WSTRB, SAXIGP1ARCACHE, SAXIGP1ARLEN, SAXIGP1ARQOS, SAXIGP1AWCACHE, SAXIGP1AWLEN, SAXIGP1AWQOS, SAXIGP1WSTRB, SAXIHP0ARCACHE, SAXIHP0ARLEN, SAXIHP0ARQOS, SAXIHP0AWCACHE +, SAXIHP0AWLEN, SAXIHP0AWQOS, SAXIHP1ARCACHE, SAXIHP1ARLEN, SAXIHP1ARQOS, SAXIHP1AWCACHE, SAXIHP1AWLEN, SAXIHP1AWQOS, SAXIHP2ARCACHE, SAXIHP2ARLEN, SAXIHP2ARQOS, SAXIHP2AWCACHE, SAXIHP2AWLEN, SAXIHP2AWQOS, SAXIHP3ARCACHE, SAXIHP3ARLEN, SAXIHP3ARQOS, SAXIHP3AWCACHE, SAXIHP3AWLEN, SAXIHP3AWQOS, SAXIACPARUSER +, SAXIACPAWUSER, SAXIGP0ARID, SAXIGP0AWID, SAXIGP0WID, SAXIGP1ARID, SAXIGP1AWID, SAXIGP1WID, SAXIHP0ARID, SAXIHP0AWID, SAXIHP0WID, SAXIHP1ARID, SAXIHP1AWID, SAXIHP1WID, SAXIHP2ARID, SAXIHP2AWID, SAXIHP2WID, SAXIHP3ARID, SAXIHP3AWID, SAXIHP3WID, EMIOGPIOI, SAXIACPWDATA +, SAXIHP0WDATA, SAXIHP1WDATA, SAXIHP2WDATA, SAXIHP3WDATA, EMIOENET0GMIIRXD, EMIOENET1GMIIRXD, SAXIACPWSTRB, SAXIHP0WSTRB, SAXIHP1WSTRB, SAXIHP2WSTRB, SAXIHP3WSTRB); output DMA0DAVALID; output DMA0DRREADY; output DMA0RSTN; @@ -32316,7 +32945,55 @@ module PS7 (...); endmodule (* keep *) -module PS8 (...); +module PS8(ADMA2PLCACK, ADMA2PLTVLD, DPAUDIOREFCLK, DPAUXDATAOEN, DPAUXDATAOUT, DPLIVEVIDEODEOUT, DPMAXISMIXEDAUDIOTDATA, DPMAXISMIXEDAUDIOTID, DPMAXISMIXEDAUDIOTVALID, DPSAXISAUDIOTREADY, DPVIDEOOUTHSYNC, DPVIDEOOUTPIXEL1, DPVIDEOOUTVSYNC, DPVIDEOREFCLK, EMIOCAN0PHYTX, EMIOCAN1PHYTX, EMIOENET0DMABUSWIDTH, EMIOENET0DMATXENDTOG, EMIOENET0GEMTSUTIMERCNT, EMIOENET0GMIITXD, EMIOENET0GMIITXEN +, EMIOENET0GMIITXER, EMIOENET0MDIOMDC, EMIOENET0MDIOO, EMIOENET0MDIOTN, EMIOENET0RXWDATA, EMIOENET0RXWEOP, EMIOENET0RXWERR, EMIOENET0RXWFLUSH, EMIOENET0RXWSOP, EMIOENET0RXWSTATUS, EMIOENET0RXWWR, EMIOENET0SPEEDMODE, EMIOENET0TXRRD, EMIOENET0TXRSTATUS, EMIOENET1DMABUSWIDTH, EMIOENET1DMATXENDTOG, EMIOENET1GMIITXD, EMIOENET1GMIITXEN, EMIOENET1GMIITXER, EMIOENET1MDIOMDC, EMIOENET1MDIOO +, EMIOENET1MDIOTN, EMIOENET1RXWDATA, EMIOENET1RXWEOP, EMIOENET1RXWERR, EMIOENET1RXWFLUSH, EMIOENET1RXWSOP, EMIOENET1RXWSTATUS, EMIOENET1RXWWR, EMIOENET1SPEEDMODE, EMIOENET1TXRRD, EMIOENET1TXRSTATUS, EMIOENET2DMABUSWIDTH, EMIOENET2DMATXENDTOG, EMIOENET2GMIITXD, EMIOENET2GMIITXEN, EMIOENET2GMIITXER, EMIOENET2MDIOMDC, EMIOENET2MDIOO, EMIOENET2MDIOTN, EMIOENET2RXWDATA, EMIOENET2RXWEOP +, EMIOENET2RXWERR, EMIOENET2RXWFLUSH, EMIOENET2RXWSOP, EMIOENET2RXWSTATUS, EMIOENET2RXWWR, EMIOENET2SPEEDMODE, EMIOENET2TXRRD, EMIOENET2TXRSTATUS, EMIOENET3DMABUSWIDTH, EMIOENET3DMATXENDTOG, EMIOENET3GMIITXD, EMIOENET3GMIITXEN, EMIOENET3GMIITXER, EMIOENET3MDIOMDC, EMIOENET3MDIOO, EMIOENET3MDIOTN, EMIOENET3RXWDATA, EMIOENET3RXWEOP, EMIOENET3RXWERR, EMIOENET3RXWFLUSH, EMIOENET3RXWSOP +, EMIOENET3RXWSTATUS, EMIOENET3RXWWR, EMIOENET3SPEEDMODE, EMIOENET3TXRRD, EMIOENET3TXRSTATUS, EMIOGEM0DELAYREQRX, EMIOGEM0DELAYREQTX, EMIOGEM0PDELAYREQRX, EMIOGEM0PDELAYREQTX, EMIOGEM0PDELAYRESPRX, EMIOGEM0PDELAYRESPTX, EMIOGEM0RXSOF, EMIOGEM0SYNCFRAMERX, EMIOGEM0SYNCFRAMETX, EMIOGEM0TSUTIMERCMPVAL, EMIOGEM0TXRFIXEDLAT, EMIOGEM0TXSOF, EMIOGEM1DELAYREQRX, EMIOGEM1DELAYREQTX, EMIOGEM1PDELAYREQRX, EMIOGEM1PDELAYREQTX +, EMIOGEM1PDELAYRESPRX, EMIOGEM1PDELAYRESPTX, EMIOGEM1RXSOF, EMIOGEM1SYNCFRAMERX, EMIOGEM1SYNCFRAMETX, EMIOGEM1TSUTIMERCMPVAL, EMIOGEM1TXRFIXEDLAT, EMIOGEM1TXSOF, EMIOGEM2DELAYREQRX, EMIOGEM2DELAYREQTX, EMIOGEM2PDELAYREQRX, EMIOGEM2PDELAYREQTX, EMIOGEM2PDELAYRESPRX, EMIOGEM2PDELAYRESPTX, EMIOGEM2RXSOF, EMIOGEM2SYNCFRAMERX, EMIOGEM2SYNCFRAMETX, EMIOGEM2TSUTIMERCMPVAL, EMIOGEM2TXRFIXEDLAT, EMIOGEM2TXSOF, EMIOGEM3DELAYREQRX +, EMIOGEM3DELAYREQTX, EMIOGEM3PDELAYREQRX, EMIOGEM3PDELAYREQTX, EMIOGEM3PDELAYRESPRX, EMIOGEM3PDELAYRESPTX, EMIOGEM3RXSOF, EMIOGEM3SYNCFRAMERX, EMIOGEM3SYNCFRAMETX, EMIOGEM3TSUTIMERCMPVAL, EMIOGEM3TXRFIXEDLAT, EMIOGEM3TXSOF, EMIOGPIOO, EMIOGPIOTN, EMIOI2C0SCLO, EMIOI2C0SCLTN, EMIOI2C0SDAO, EMIOI2C0SDATN, EMIOI2C1SCLO, EMIOI2C1SCLTN, EMIOI2C1SDAO, EMIOI2C1SDATN +, EMIOSDIO0BUSPOWER, EMIOSDIO0BUSVOLT, EMIOSDIO0CLKOUT, EMIOSDIO0CMDENA, EMIOSDIO0CMDOUT, EMIOSDIO0DATAENA, EMIOSDIO0DATAOUT, EMIOSDIO0LEDCONTROL, EMIOSDIO1BUSPOWER, EMIOSDIO1BUSVOLT, EMIOSDIO1CLKOUT, EMIOSDIO1CMDENA, EMIOSDIO1CMDOUT, EMIOSDIO1DATAENA, EMIOSDIO1DATAOUT, EMIOSDIO1LEDCONTROL, EMIOSPI0MO, EMIOSPI0MOTN, EMIOSPI0SCLKO, EMIOSPI0SCLKTN, EMIOSPI0SO +, EMIOSPI0SSNTN, EMIOSPI0SSON, EMIOSPI0STN, EMIOSPI1MO, EMIOSPI1MOTN, EMIOSPI1SCLKO, EMIOSPI1SCLKTN, EMIOSPI1SO, EMIOSPI1SSNTN, EMIOSPI1SSON, EMIOSPI1STN, EMIOTTC0WAVEO, EMIOTTC1WAVEO, EMIOTTC2WAVEO, EMIOTTC3WAVEO, EMIOU2DSPORTVBUSCTRLUSB30, EMIOU2DSPORTVBUSCTRLUSB31, EMIOU3DSPORTVBUSCTRLUSB30, EMIOU3DSPORTVBUSCTRLUSB31, EMIOUART0DTRN, EMIOUART0RTSN +, EMIOUART0TX, EMIOUART1DTRN, EMIOUART1RTSN, EMIOUART1TX, EMIOWDT0RSTO, EMIOWDT1RSTO, FMIOGEM0FIFORXCLKTOPLBUFG, FMIOGEM0FIFOTXCLKTOPLBUFG, FMIOGEM1FIFORXCLKTOPLBUFG, FMIOGEM1FIFOTXCLKTOPLBUFG, FMIOGEM2FIFORXCLKTOPLBUFG, FMIOGEM2FIFOTXCLKTOPLBUFG, FMIOGEM3FIFORXCLKTOPLBUFG, FMIOGEM3FIFOTXCLKTOPLBUFG, FMIOGEMTSUCLKTOPLBUFG, FTMGPO, GDMA2PLCACK, GDMA2PLTVLD, MAXIGP0ARADDR, MAXIGP0ARBURST, MAXIGP0ARCACHE +, MAXIGP0ARID, MAXIGP0ARLEN, MAXIGP0ARLOCK, MAXIGP0ARPROT, MAXIGP0ARQOS, MAXIGP0ARSIZE, MAXIGP0ARUSER, MAXIGP0ARVALID, MAXIGP0AWADDR, MAXIGP0AWBURST, MAXIGP0AWCACHE, MAXIGP0AWID, MAXIGP0AWLEN, MAXIGP0AWLOCK, MAXIGP0AWPROT, MAXIGP0AWQOS, MAXIGP0AWSIZE, MAXIGP0AWUSER, MAXIGP0AWVALID, MAXIGP0BREADY, MAXIGP0RREADY +, MAXIGP0WDATA, MAXIGP0WLAST, MAXIGP0WSTRB, MAXIGP0WVALID, MAXIGP1ARADDR, MAXIGP1ARBURST, MAXIGP1ARCACHE, MAXIGP1ARID, MAXIGP1ARLEN, MAXIGP1ARLOCK, MAXIGP1ARPROT, MAXIGP1ARQOS, MAXIGP1ARSIZE, MAXIGP1ARUSER, MAXIGP1ARVALID, MAXIGP1AWADDR, MAXIGP1AWBURST, MAXIGP1AWCACHE, MAXIGP1AWID, MAXIGP1AWLEN, MAXIGP1AWLOCK +, MAXIGP1AWPROT, MAXIGP1AWQOS, MAXIGP1AWSIZE, MAXIGP1AWUSER, MAXIGP1AWVALID, MAXIGP1BREADY, MAXIGP1RREADY, MAXIGP1WDATA, MAXIGP1WLAST, MAXIGP1WSTRB, MAXIGP1WVALID, MAXIGP2ARADDR, MAXIGP2ARBURST, MAXIGP2ARCACHE, MAXIGP2ARID, MAXIGP2ARLEN, MAXIGP2ARLOCK, MAXIGP2ARPROT, MAXIGP2ARQOS, MAXIGP2ARSIZE, MAXIGP2ARUSER +, MAXIGP2ARVALID, MAXIGP2AWADDR, MAXIGP2AWBURST, MAXIGP2AWCACHE, MAXIGP2AWID, MAXIGP2AWLEN, MAXIGP2AWLOCK, MAXIGP2AWPROT, MAXIGP2AWQOS, MAXIGP2AWSIZE, MAXIGP2AWUSER, MAXIGP2AWVALID, MAXIGP2BREADY, MAXIGP2RREADY, MAXIGP2WDATA, MAXIGP2WLAST, MAXIGP2WSTRB, MAXIGP2WVALID, OSCRTCCLK, PLCLK, PMUAIBAFIFMFPDREQ +, PMUAIBAFIFMLPDREQ, PMUERRORTOPL, PMUPLGPO, PSPLEVENTO, PSPLIRQFPD, PSPLIRQLPD, PSPLSTANDBYWFE, PSPLSTANDBYWFI, PSPLTRACECTL, PSPLTRACEDATA, PSPLTRIGACK, PSPLTRIGGER, PSS_ALTO_CORE_PAD_MGTTXN0OUT, PSS_ALTO_CORE_PAD_MGTTXN1OUT, PSS_ALTO_CORE_PAD_MGTTXN2OUT, PSS_ALTO_CORE_PAD_MGTTXN3OUT, PSS_ALTO_CORE_PAD_MGTTXP0OUT, PSS_ALTO_CORE_PAD_MGTTXP1OUT, PSS_ALTO_CORE_PAD_MGTTXP2OUT, PSS_ALTO_CORE_PAD_MGTTXP3OUT, PSS_ALTO_CORE_PAD_PADO +, RPUEVENTO0, RPUEVENTO1, SACEFPDACADDR, SACEFPDACPROT, SACEFPDACSNOOP, SACEFPDACVALID, SACEFPDARREADY, SACEFPDAWREADY, SACEFPDBID, SACEFPDBRESP, SACEFPDBUSER, SACEFPDBVALID, SACEFPDCDREADY, SACEFPDCRREADY, SACEFPDRDATA, SACEFPDRID, SACEFPDRLAST, SACEFPDRRESP, SACEFPDRUSER, SACEFPDRVALID, SACEFPDWREADY +, SAXIACPARREADY, SAXIACPAWREADY, SAXIACPBID, SAXIACPBRESP, SAXIACPBVALID, SAXIACPRDATA, SAXIACPRID, SAXIACPRLAST, SAXIACPRRESP, SAXIACPRVALID, SAXIACPWREADY, SAXIGP0ARREADY, SAXIGP0AWREADY, SAXIGP0BID, SAXIGP0BRESP, SAXIGP0BVALID, SAXIGP0RACOUNT, SAXIGP0RCOUNT, SAXIGP0RDATA, SAXIGP0RID, SAXIGP0RLAST +, SAXIGP0RRESP, SAXIGP0RVALID, SAXIGP0WACOUNT, SAXIGP0WCOUNT, SAXIGP0WREADY, SAXIGP1ARREADY, SAXIGP1AWREADY, SAXIGP1BID, SAXIGP1BRESP, SAXIGP1BVALID, SAXIGP1RACOUNT, SAXIGP1RCOUNT, SAXIGP1RDATA, SAXIGP1RID, SAXIGP1RLAST, SAXIGP1RRESP, SAXIGP1RVALID, SAXIGP1WACOUNT, SAXIGP1WCOUNT, SAXIGP1WREADY, SAXIGP2ARREADY +, SAXIGP2AWREADY, SAXIGP2BID, SAXIGP2BRESP, SAXIGP2BVALID, SAXIGP2RACOUNT, SAXIGP2RCOUNT, SAXIGP2RDATA, SAXIGP2RID, SAXIGP2RLAST, SAXIGP2RRESP, SAXIGP2RVALID, SAXIGP2WACOUNT, SAXIGP2WCOUNT, SAXIGP2WREADY, SAXIGP3ARREADY, SAXIGP3AWREADY, SAXIGP3BID, SAXIGP3BRESP, SAXIGP3BVALID, SAXIGP3RACOUNT, SAXIGP3RCOUNT +, SAXIGP3RDATA, SAXIGP3RID, SAXIGP3RLAST, SAXIGP3RRESP, SAXIGP3RVALID, SAXIGP3WACOUNT, SAXIGP3WCOUNT, SAXIGP3WREADY, SAXIGP4ARREADY, SAXIGP4AWREADY, SAXIGP4BID, SAXIGP4BRESP, SAXIGP4BVALID, SAXIGP4RACOUNT, SAXIGP4RCOUNT, SAXIGP4RDATA, SAXIGP4RID, SAXIGP4RLAST, SAXIGP4RRESP, SAXIGP4RVALID, SAXIGP4WACOUNT +, SAXIGP4WCOUNT, SAXIGP4WREADY, SAXIGP5ARREADY, SAXIGP5AWREADY, SAXIGP5BID, SAXIGP5BRESP, SAXIGP5BVALID, SAXIGP5RACOUNT, SAXIGP5RCOUNT, SAXIGP5RDATA, SAXIGP5RID, SAXIGP5RLAST, SAXIGP5RRESP, SAXIGP5RVALID, SAXIGP5WACOUNT, SAXIGP5WCOUNT, SAXIGP5WREADY, SAXIGP6ARREADY, SAXIGP6AWREADY, SAXIGP6BID, SAXIGP6BRESP +, SAXIGP6BVALID, SAXIGP6RACOUNT, SAXIGP6RCOUNT, SAXIGP6RDATA, SAXIGP6RID, SAXIGP6RLAST, SAXIGP6RRESP, SAXIGP6RVALID, SAXIGP6WACOUNT, SAXIGP6WCOUNT, SAXIGP6WREADY, PSS_ALTO_CORE_PAD_BOOTMODE, PSS_ALTO_CORE_PAD_CLK, PSS_ALTO_CORE_PAD_DONEB, PSS_ALTO_CORE_PAD_DRAMA, PSS_ALTO_CORE_PAD_DRAMACTN, PSS_ALTO_CORE_PAD_DRAMALERTN, PSS_ALTO_CORE_PAD_DRAMBA, PSS_ALTO_CORE_PAD_DRAMBG, PSS_ALTO_CORE_PAD_DRAMCK, PSS_ALTO_CORE_PAD_DRAMCKE +, PSS_ALTO_CORE_PAD_DRAMCKN, PSS_ALTO_CORE_PAD_DRAMCSN, PSS_ALTO_CORE_PAD_DRAMDM, PSS_ALTO_CORE_PAD_DRAMDQ, PSS_ALTO_CORE_PAD_DRAMDQS, PSS_ALTO_CORE_PAD_DRAMDQSN, PSS_ALTO_CORE_PAD_DRAMODT, PSS_ALTO_CORE_PAD_DRAMPARITY, PSS_ALTO_CORE_PAD_DRAMRAMRSTN, PSS_ALTO_CORE_PAD_ERROROUT, PSS_ALTO_CORE_PAD_ERRORSTATUS, PSS_ALTO_CORE_PAD_INITB, PSS_ALTO_CORE_PAD_JTAGTCK, PSS_ALTO_CORE_PAD_JTAGTDI, PSS_ALTO_CORE_PAD_JTAGTDO, PSS_ALTO_CORE_PAD_JTAGTMS, PSS_ALTO_CORE_PAD_MIO, PSS_ALTO_CORE_PAD_PORB, PSS_ALTO_CORE_PAD_PROGB, PSS_ALTO_CORE_PAD_RCALIBINOUT, PSS_ALTO_CORE_PAD_SRSTB +, PSS_ALTO_CORE_PAD_ZQ, ADMAFCICLK, AIBPMUAFIFMFPDACK, AIBPMUAFIFMLPDACK, DDRCEXTREFRESHRANK0REQ, DDRCEXTREFRESHRANK1REQ, DDRCREFRESHPLCLK, DPAUXDATAIN, DPEXTERNALCUSTOMEVENT1, DPEXTERNALCUSTOMEVENT2, DPEXTERNALVSYNCEVENT, DPHOTPLUGDETECT, DPLIVEGFXALPHAIN, DPLIVEGFXPIXEL1IN, DPLIVEVIDEOINDE, DPLIVEVIDEOINHSYNC, DPLIVEVIDEOINPIXEL1, DPLIVEVIDEOINVSYNC, DPMAXISMIXEDAUDIOTREADY, DPSAXISAUDIOCLK, DPSAXISAUDIOTDATA +, DPSAXISAUDIOTID, DPSAXISAUDIOTVALID, DPVIDEOINCLK, EMIOCAN0PHYRX, EMIOCAN1PHYRX, EMIOENET0DMATXSTATUSTOG, EMIOENET0EXTINTIN, EMIOENET0GMIICOL, EMIOENET0GMIICRS, EMIOENET0GMIIRXCLK, EMIOENET0GMIIRXD, EMIOENET0GMIIRXDV, EMIOENET0GMIIRXER, EMIOENET0GMIITXCLK, EMIOENET0MDIOI, EMIOENET0RXWOVERFLOW, EMIOENET0TXRCONTROL, EMIOENET0TXRDATA, EMIOENET0TXRDATARDY, EMIOENET0TXREOP, EMIOENET0TXRERR +, EMIOENET0TXRFLUSHED, EMIOENET0TXRSOP, EMIOENET0TXRUNDERFLOW, EMIOENET0TXRVALID, EMIOENET1DMATXSTATUSTOG, EMIOENET1EXTINTIN, EMIOENET1GMIICOL, EMIOENET1GMIICRS, EMIOENET1GMIIRXCLK, EMIOENET1GMIIRXD, EMIOENET1GMIIRXDV, EMIOENET1GMIIRXER, EMIOENET1GMIITXCLK, EMIOENET1MDIOI, EMIOENET1RXWOVERFLOW, EMIOENET1TXRCONTROL, EMIOENET1TXRDATA, EMIOENET1TXRDATARDY, EMIOENET1TXREOP, EMIOENET1TXRERR, EMIOENET1TXRFLUSHED +, EMIOENET1TXRSOP, EMIOENET1TXRUNDERFLOW, EMIOENET1TXRVALID, EMIOENET2DMATXSTATUSTOG, EMIOENET2EXTINTIN, EMIOENET2GMIICOL, EMIOENET2GMIICRS, EMIOENET2GMIIRXCLK, EMIOENET2GMIIRXD, EMIOENET2GMIIRXDV, EMIOENET2GMIIRXER, EMIOENET2GMIITXCLK, EMIOENET2MDIOI, EMIOENET2RXWOVERFLOW, EMIOENET2TXRCONTROL, EMIOENET2TXRDATA, EMIOENET2TXRDATARDY, EMIOENET2TXREOP, EMIOENET2TXRERR, EMIOENET2TXRFLUSHED, EMIOENET2TXRSOP +, EMIOENET2TXRUNDERFLOW, EMIOENET2TXRVALID, EMIOENET3DMATXSTATUSTOG, EMIOENET3EXTINTIN, EMIOENET3GMIICOL, EMIOENET3GMIICRS, EMIOENET3GMIIRXCLK, EMIOENET3GMIIRXD, EMIOENET3GMIIRXDV, EMIOENET3GMIIRXER, EMIOENET3GMIITXCLK, EMIOENET3MDIOI, EMIOENET3RXWOVERFLOW, EMIOENET3TXRCONTROL, EMIOENET3TXRDATA, EMIOENET3TXRDATARDY, EMIOENET3TXREOP, EMIOENET3TXRERR, EMIOENET3TXRFLUSHED, EMIOENET3TXRSOP, EMIOENET3TXRUNDERFLOW +, EMIOENET3TXRVALID, EMIOENETTSUCLK, EMIOGEM0TSUINCCTRL, EMIOGEM1TSUINCCTRL, EMIOGEM2TSUINCCTRL, EMIOGEM3TSUINCCTRL, EMIOGPIOI, EMIOHUBPORTOVERCRNTUSB20, EMIOHUBPORTOVERCRNTUSB21, EMIOHUBPORTOVERCRNTUSB30, EMIOHUBPORTOVERCRNTUSB31, EMIOI2C0SCLI, EMIOI2C0SDAI, EMIOI2C1SCLI, EMIOI2C1SDAI, EMIOSDIO0CDN, EMIOSDIO0CMDIN, EMIOSDIO0DATAIN, EMIOSDIO0FBCLKIN, EMIOSDIO0WP, EMIOSDIO1CDN +, EMIOSDIO1CMDIN, EMIOSDIO1DATAIN, EMIOSDIO1FBCLKIN, EMIOSDIO1WP, EMIOSPI0MI, EMIOSPI0SCLKI, EMIOSPI0SI, EMIOSPI0SSIN, EMIOSPI1MI, EMIOSPI1SCLKI, EMIOSPI1SI, EMIOSPI1SSIN, EMIOTTC0CLKI, EMIOTTC1CLKI, EMIOTTC2CLKI, EMIOTTC3CLKI, EMIOUART0CTSN, EMIOUART0DCDN, EMIOUART0DSRN, EMIOUART0RIN, EMIOUART0RX +, EMIOUART1CTSN, EMIOUART1DCDN, EMIOUART1DSRN, EMIOUART1RIN, EMIOUART1RX, EMIOWDT0CLKI, EMIOWDT1CLKI, FMIOGEM0FIFORXCLKFROMPL, FMIOGEM0FIFOTXCLKFROMPL, FMIOGEM0SIGNALDETECT, FMIOGEM1FIFORXCLKFROMPL, FMIOGEM1FIFOTXCLKFROMPL, FMIOGEM1SIGNALDETECT, FMIOGEM2FIFORXCLKFROMPL, FMIOGEM2FIFOTXCLKFROMPL, FMIOGEM2SIGNALDETECT, FMIOGEM3FIFORXCLKFROMPL, FMIOGEM3FIFOTXCLKFROMPL, FMIOGEM3SIGNALDETECT, FMIOGEMTSUCLKFROMPL, FTMGPI +, GDMAFCICLK, MAXIGP0ACLK, MAXIGP0ARREADY, MAXIGP0AWREADY, MAXIGP0BID, MAXIGP0BRESP, MAXIGP0BVALID, MAXIGP0RDATA, MAXIGP0RID, MAXIGP0RLAST, MAXIGP0RRESP, MAXIGP0RVALID, MAXIGP0WREADY, MAXIGP1ACLK, MAXIGP1ARREADY, MAXIGP1AWREADY, MAXIGP1BID, MAXIGP1BRESP, MAXIGP1BVALID, MAXIGP1RDATA, MAXIGP1RID +, MAXIGP1RLAST, MAXIGP1RRESP, MAXIGP1RVALID, MAXIGP1WREADY, MAXIGP2ACLK, MAXIGP2ARREADY, MAXIGP2AWREADY, MAXIGP2BID, MAXIGP2BRESP, MAXIGP2BVALID, MAXIGP2RDATA, MAXIGP2RID, MAXIGP2RLAST, MAXIGP2RRESP, MAXIGP2RVALID, MAXIGP2WREADY, NFIQ0LPDRPU, NFIQ1LPDRPU, NIRQ0LPDRPU, NIRQ1LPDRPU, PL2ADMACVLD +, PL2ADMATACK, PL2GDMACVLD, PL2GDMATACK, PLACECLK, PLACPINACT, PLFPGASTOP, PLLAUXREFCLKFPD, PLLAUXREFCLKLPD, PLPMUGPI, PLPSAPUGICFIQ, PLPSAPUGICIRQ, PLPSEVENTI, PLPSIRQ0, PLPSIRQ1, PLPSTRACECLK, PLPSTRIGACK, PLPSTRIGGER, PMUERRORFROMPL, PSS_ALTO_CORE_PAD_MGTRXN0IN, PSS_ALTO_CORE_PAD_MGTRXN1IN, PSS_ALTO_CORE_PAD_MGTRXN2IN +, PSS_ALTO_CORE_PAD_MGTRXN3IN, PSS_ALTO_CORE_PAD_MGTRXP0IN, PSS_ALTO_CORE_PAD_MGTRXP1IN, PSS_ALTO_CORE_PAD_MGTRXP2IN, PSS_ALTO_CORE_PAD_MGTRXP3IN, PSS_ALTO_CORE_PAD_PADI, PSS_ALTO_CORE_PAD_REFN0IN, PSS_ALTO_CORE_PAD_REFN1IN, PSS_ALTO_CORE_PAD_REFN2IN, PSS_ALTO_CORE_PAD_REFN3IN, PSS_ALTO_CORE_PAD_REFP0IN, PSS_ALTO_CORE_PAD_REFP1IN, PSS_ALTO_CORE_PAD_REFP2IN, PSS_ALTO_CORE_PAD_REFP3IN, RPUEVENTI0, RPUEVENTI1, SACEFPDACREADY, SACEFPDARADDR, SACEFPDARBAR, SACEFPDARBURST, SACEFPDARCACHE +, SACEFPDARDOMAIN, SACEFPDARID, SACEFPDARLEN, SACEFPDARLOCK, SACEFPDARPROT, SACEFPDARQOS, SACEFPDARREGION, SACEFPDARSIZE, SACEFPDARSNOOP, SACEFPDARUSER, SACEFPDARVALID, SACEFPDAWADDR, SACEFPDAWBAR, SACEFPDAWBURST, SACEFPDAWCACHE, SACEFPDAWDOMAIN, SACEFPDAWID, SACEFPDAWLEN, SACEFPDAWLOCK, SACEFPDAWPROT, SACEFPDAWQOS +, SACEFPDAWREGION, SACEFPDAWSIZE, SACEFPDAWSNOOP, SACEFPDAWUSER, SACEFPDAWVALID, SACEFPDBREADY, SACEFPDCDDATA, SACEFPDCDLAST, SACEFPDCDVALID, SACEFPDCRRESP, SACEFPDCRVALID, SACEFPDRACK, SACEFPDRREADY, SACEFPDWACK, SACEFPDWDATA, SACEFPDWLAST, SACEFPDWSTRB, SACEFPDWUSER, SACEFPDWVALID, SAXIACPACLK, SAXIACPARADDR +, SAXIACPARBURST, SAXIACPARCACHE, SAXIACPARID, SAXIACPARLEN, SAXIACPARLOCK, SAXIACPARPROT, SAXIACPARQOS, SAXIACPARSIZE, SAXIACPARUSER, SAXIACPARVALID, SAXIACPAWADDR, SAXIACPAWBURST, SAXIACPAWCACHE, SAXIACPAWID, SAXIACPAWLEN, SAXIACPAWLOCK, SAXIACPAWPROT, SAXIACPAWQOS, SAXIACPAWSIZE, SAXIACPAWUSER, SAXIACPAWVALID +, SAXIACPBREADY, SAXIACPRREADY, SAXIACPWDATA, SAXIACPWLAST, SAXIACPWSTRB, SAXIACPWVALID, SAXIGP0ARADDR, SAXIGP0ARBURST, SAXIGP0ARCACHE, SAXIGP0ARID, SAXIGP0ARLEN, SAXIGP0ARLOCK, SAXIGP0ARPROT, SAXIGP0ARQOS, SAXIGP0ARSIZE, SAXIGP0ARUSER, SAXIGP0ARVALID, SAXIGP0AWADDR, SAXIGP0AWBURST, SAXIGP0AWCACHE, SAXIGP0AWID +, SAXIGP0AWLEN, SAXIGP0AWLOCK, SAXIGP0AWPROT, SAXIGP0AWQOS, SAXIGP0AWSIZE, SAXIGP0AWUSER, SAXIGP0AWVALID, SAXIGP0BREADY, SAXIGP0RCLK, SAXIGP0RREADY, SAXIGP0WCLK, SAXIGP0WDATA, SAXIGP0WLAST, SAXIGP0WSTRB, SAXIGP0WVALID, SAXIGP1ARADDR, SAXIGP1ARBURST, SAXIGP1ARCACHE, SAXIGP1ARID, SAXIGP1ARLEN, SAXIGP1ARLOCK +, SAXIGP1ARPROT, SAXIGP1ARQOS, SAXIGP1ARSIZE, SAXIGP1ARUSER, SAXIGP1ARVALID, SAXIGP1AWADDR, SAXIGP1AWBURST, SAXIGP1AWCACHE, SAXIGP1AWID, SAXIGP1AWLEN, SAXIGP1AWLOCK, SAXIGP1AWPROT, SAXIGP1AWQOS, SAXIGP1AWSIZE, SAXIGP1AWUSER, SAXIGP1AWVALID, SAXIGP1BREADY, SAXIGP1RCLK, SAXIGP1RREADY, SAXIGP1WCLK, SAXIGP1WDATA +, SAXIGP1WLAST, SAXIGP1WSTRB, SAXIGP1WVALID, SAXIGP2ARADDR, SAXIGP2ARBURST, SAXIGP2ARCACHE, SAXIGP2ARID, SAXIGP2ARLEN, SAXIGP2ARLOCK, SAXIGP2ARPROT, SAXIGP2ARQOS, SAXIGP2ARSIZE, SAXIGP2ARUSER, SAXIGP2ARVALID, SAXIGP2AWADDR, SAXIGP2AWBURST, SAXIGP2AWCACHE, SAXIGP2AWID, SAXIGP2AWLEN, SAXIGP2AWLOCK, SAXIGP2AWPROT +, SAXIGP2AWQOS, SAXIGP2AWSIZE, SAXIGP2AWUSER, SAXIGP2AWVALID, SAXIGP2BREADY, SAXIGP2RCLK, SAXIGP2RREADY, SAXIGP2WCLK, SAXIGP2WDATA, SAXIGP2WLAST, SAXIGP2WSTRB, SAXIGP2WVALID, SAXIGP3ARADDR, SAXIGP3ARBURST, SAXIGP3ARCACHE, SAXIGP3ARID, SAXIGP3ARLEN, SAXIGP3ARLOCK, SAXIGP3ARPROT, SAXIGP3ARQOS, SAXIGP3ARSIZE +, SAXIGP3ARUSER, SAXIGP3ARVALID, SAXIGP3AWADDR, SAXIGP3AWBURST, SAXIGP3AWCACHE, SAXIGP3AWID, SAXIGP3AWLEN, SAXIGP3AWLOCK, SAXIGP3AWPROT, SAXIGP3AWQOS, SAXIGP3AWSIZE, SAXIGP3AWUSER, SAXIGP3AWVALID, SAXIGP3BREADY, SAXIGP3RCLK, SAXIGP3RREADY, SAXIGP3WCLK, SAXIGP3WDATA, SAXIGP3WLAST, SAXIGP3WSTRB, SAXIGP3WVALID +, SAXIGP4ARADDR, SAXIGP4ARBURST, SAXIGP4ARCACHE, SAXIGP4ARID, SAXIGP4ARLEN, SAXIGP4ARLOCK, SAXIGP4ARPROT, SAXIGP4ARQOS, SAXIGP4ARSIZE, SAXIGP4ARUSER, SAXIGP4ARVALID, SAXIGP4AWADDR, SAXIGP4AWBURST, SAXIGP4AWCACHE, SAXIGP4AWID, SAXIGP4AWLEN, SAXIGP4AWLOCK, SAXIGP4AWPROT, SAXIGP4AWQOS, SAXIGP4AWSIZE, SAXIGP4AWUSER +, SAXIGP4AWVALID, SAXIGP4BREADY, SAXIGP4RCLK, SAXIGP4RREADY, SAXIGP4WCLK, SAXIGP4WDATA, SAXIGP4WLAST, SAXIGP4WSTRB, SAXIGP4WVALID, SAXIGP5ARADDR, SAXIGP5ARBURST, SAXIGP5ARCACHE, SAXIGP5ARID, SAXIGP5ARLEN, SAXIGP5ARLOCK, SAXIGP5ARPROT, SAXIGP5ARQOS, SAXIGP5ARSIZE, SAXIGP5ARUSER, SAXIGP5ARVALID, SAXIGP5AWADDR +, SAXIGP5AWBURST, SAXIGP5AWCACHE, SAXIGP5AWID, SAXIGP5AWLEN, SAXIGP5AWLOCK, SAXIGP5AWPROT, SAXIGP5AWQOS, SAXIGP5AWSIZE, SAXIGP5AWUSER, SAXIGP5AWVALID, SAXIGP5BREADY, SAXIGP5RCLK, SAXIGP5RREADY, SAXIGP5WCLK, SAXIGP5WDATA, SAXIGP5WLAST, SAXIGP5WSTRB, SAXIGP5WVALID, SAXIGP6ARADDR, SAXIGP6ARBURST, SAXIGP6ARCACHE +, SAXIGP6ARID, SAXIGP6ARLEN, SAXIGP6ARLOCK, SAXIGP6ARPROT, SAXIGP6ARQOS, SAXIGP6ARSIZE, SAXIGP6ARUSER, SAXIGP6ARVALID, SAXIGP6AWADDR, SAXIGP6AWBURST, SAXIGP6AWCACHE, SAXIGP6AWID, SAXIGP6AWLEN, SAXIGP6AWLOCK, SAXIGP6AWPROT, SAXIGP6AWQOS, SAXIGP6AWSIZE, SAXIGP6AWUSER, SAXIGP6AWVALID, SAXIGP6BREADY, SAXIGP6RCLK +, SAXIGP6RREADY, SAXIGP6WCLK, SAXIGP6WDATA, SAXIGP6WLAST, SAXIGP6WSTRB, SAXIGP6WVALID, STMEVENT); output [7:0] ADMA2PLCACK; output [7:0] ADMA2PLTVLD; output DPAUDIOREFCLK; @@ -33334,7 +34011,17 @@ module PS8 (...); input [59:0] STMEVENT; endmodule -module ILKN (...); +module ILKN(DRP_DO, DRP_RDY, RX_BYPASS_DATAOUT00, RX_BYPASS_DATAOUT01, RX_BYPASS_DATAOUT02, RX_BYPASS_DATAOUT03, RX_BYPASS_DATAOUT04, RX_BYPASS_DATAOUT05, RX_BYPASS_DATAOUT06, RX_BYPASS_DATAOUT07, RX_BYPASS_DATAOUT08, RX_BYPASS_DATAOUT09, RX_BYPASS_DATAOUT10, RX_BYPASS_DATAOUT11, RX_BYPASS_ENAOUT, RX_BYPASS_IS_AVAILOUT, RX_BYPASS_IS_BADLYFRAMEDOUT, RX_BYPASS_IS_OVERFLOWOUT, RX_BYPASS_IS_SYNCEDOUT, RX_BYPASS_IS_SYNCWORDOUT, RX_CHANOUT0 +, RX_CHANOUT1, RX_CHANOUT2, RX_CHANOUT3, RX_DATAOUT0, RX_DATAOUT1, RX_DATAOUT2, RX_DATAOUT3, RX_ENAOUT0, RX_ENAOUT1, RX_ENAOUT2, RX_ENAOUT3, RX_EOPOUT0, RX_EOPOUT1, RX_EOPOUT2, RX_EOPOUT3, RX_ERROUT0, RX_ERROUT1, RX_ERROUT2, RX_ERROUT3, RX_MTYOUT0, RX_MTYOUT1 +, RX_MTYOUT2, RX_MTYOUT3, RX_OVFOUT, RX_SOPOUT0, RX_SOPOUT1, RX_SOPOUT2, RX_SOPOUT3, STAT_RX_ALIGNED, STAT_RX_ALIGNED_ERR, STAT_RX_BAD_TYPE_ERR, STAT_RX_BURSTMAX_ERR, STAT_RX_BURST_ERR, STAT_RX_CRC24_ERR, STAT_RX_CRC32_ERR, STAT_RX_CRC32_VALID, STAT_RX_DESCRAM_ERR, STAT_RX_DIAGWORD_INTFSTAT, STAT_RX_DIAGWORD_LANESTAT, STAT_RX_FC_STAT, STAT_RX_FRAMING_ERR, STAT_RX_MEOP_ERR +, STAT_RX_MF_ERR, STAT_RX_MF_LEN_ERR, STAT_RX_MF_REPEAT_ERR, STAT_RX_MISALIGNED, STAT_RX_MSOP_ERR, STAT_RX_MUBITS, STAT_RX_MUBITS_UPDATED, STAT_RX_OVERFLOW_ERR, STAT_RX_RETRANS_CRC24_ERR, STAT_RX_RETRANS_DISC, STAT_RX_RETRANS_LATENCY, STAT_RX_RETRANS_REQ, STAT_RX_RETRANS_RETRY_ERR, STAT_RX_RETRANS_SEQ, STAT_RX_RETRANS_SEQ_UPDATED, STAT_RX_RETRANS_STATE, STAT_RX_RETRANS_SUBSEQ, STAT_RX_RETRANS_WDOG_ERR, STAT_RX_RETRANS_WRAP_ERR, STAT_RX_SYNCED, STAT_RX_SYNCED_ERR +, STAT_RX_WORD_SYNC, STAT_TX_BURST_ERR, STAT_TX_ERRINJ_BITERR_DONE, STAT_TX_OVERFLOW_ERR, STAT_TX_RETRANS_BURST_ERR, STAT_TX_RETRANS_BUSY, STAT_TX_RETRANS_RAM_PERROUT, STAT_TX_RETRANS_RAM_RADDR, STAT_TX_RETRANS_RAM_RD_B0, STAT_TX_RETRANS_RAM_RD_B1, STAT_TX_RETRANS_RAM_RD_B2, STAT_TX_RETRANS_RAM_RD_B3, STAT_TX_RETRANS_RAM_RSEL, STAT_TX_RETRANS_RAM_WADDR, STAT_TX_RETRANS_RAM_WDATA, STAT_TX_RETRANS_RAM_WE_B0, STAT_TX_RETRANS_RAM_WE_B1, STAT_TX_RETRANS_RAM_WE_B2, STAT_TX_RETRANS_RAM_WE_B3, STAT_TX_UNDERFLOW_ERR, TX_OVFOUT +, TX_RDYOUT, TX_SERDES_DATA00, TX_SERDES_DATA01, TX_SERDES_DATA02, TX_SERDES_DATA03, TX_SERDES_DATA04, TX_SERDES_DATA05, TX_SERDES_DATA06, TX_SERDES_DATA07, TX_SERDES_DATA08, TX_SERDES_DATA09, TX_SERDES_DATA10, TX_SERDES_DATA11, CORE_CLK, CTL_RX_FORCE_RESYNC, CTL_RX_RETRANS_ACK, CTL_RX_RETRANS_ENABLE, CTL_RX_RETRANS_ERRIN, CTL_RX_RETRANS_FORCE_REQ, CTL_RX_RETRANS_RESET, CTL_RX_RETRANS_RESET_MODE +, CTL_TX_DIAGWORD_INTFSTAT, CTL_TX_DIAGWORD_LANESTAT, CTL_TX_ENABLE, CTL_TX_ERRINJ_BITERR_GO, CTL_TX_ERRINJ_BITERR_LANE, CTL_TX_FC_STAT, CTL_TX_MUBITS, CTL_TX_RETRANS_ENABLE, CTL_TX_RETRANS_RAM_PERRIN, CTL_TX_RETRANS_RAM_RDATA, CTL_TX_RETRANS_REQ, CTL_TX_RETRANS_REQ_VALID, CTL_TX_RLIM_DELTA, CTL_TX_RLIM_ENABLE, CTL_TX_RLIM_INTV, CTL_TX_RLIM_MAX, DRP_ADDR, DRP_CLK, DRP_DI, DRP_EN, DRP_WE +, LBUS_CLK, RX_BYPASS_FORCE_REALIGNIN, RX_BYPASS_RDIN, RX_RESET, RX_SERDES_CLK, RX_SERDES_DATA00, RX_SERDES_DATA01, RX_SERDES_DATA02, RX_SERDES_DATA03, RX_SERDES_DATA04, RX_SERDES_DATA05, RX_SERDES_DATA06, RX_SERDES_DATA07, RX_SERDES_DATA08, RX_SERDES_DATA09, RX_SERDES_DATA10, RX_SERDES_DATA11, RX_SERDES_RESET, TX_BCTLIN0, TX_BCTLIN1, TX_BCTLIN2 +, TX_BCTLIN3, TX_BYPASS_CTRLIN, TX_BYPASS_DATAIN00, TX_BYPASS_DATAIN01, TX_BYPASS_DATAIN02, TX_BYPASS_DATAIN03, TX_BYPASS_DATAIN04, TX_BYPASS_DATAIN05, TX_BYPASS_DATAIN06, TX_BYPASS_DATAIN07, TX_BYPASS_DATAIN08, TX_BYPASS_DATAIN09, TX_BYPASS_DATAIN10, TX_BYPASS_DATAIN11, TX_BYPASS_ENAIN, TX_BYPASS_GEARBOX_SEQIN, TX_BYPASS_MFRAMER_STATEIN, TX_CHANIN0, TX_CHANIN1, TX_CHANIN2, TX_CHANIN3 +, TX_DATAIN0, TX_DATAIN1, TX_DATAIN2, TX_DATAIN3, TX_ENAIN0, TX_ENAIN1, TX_ENAIN2, TX_ENAIN3, TX_EOPIN0, TX_EOPIN1, TX_EOPIN2, TX_EOPIN3, TX_ERRIN0, TX_ERRIN1, TX_ERRIN2, TX_ERRIN3, TX_MTYIN0, TX_MTYIN1, TX_MTYIN2, TX_MTYIN3, TX_RESET +, TX_SERDES_REFCLK, TX_SERDES_REFCLK_RESET, TX_SOPIN0, TX_SOPIN1, TX_SOPIN2, TX_SOPIN3); parameter BYPASS = "FALSE"; parameter [1:0] CTL_RX_BURSTMAX = 2'h3; parameter [1:0] CTL_RX_CHAN_EXT = 2'h0; @@ -33579,7 +34266,17 @@ module ILKN (...); input TX_SOPIN3; endmodule -module ILKNE4 (...); +module ILKNE4(DRP_DO, DRP_RDY, RX_BYPASS_DATAOUT00, RX_BYPASS_DATAOUT01, RX_BYPASS_DATAOUT02, RX_BYPASS_DATAOUT03, RX_BYPASS_DATAOUT04, RX_BYPASS_DATAOUT05, RX_BYPASS_DATAOUT06, RX_BYPASS_DATAOUT07, RX_BYPASS_DATAOUT08, RX_BYPASS_DATAOUT09, RX_BYPASS_DATAOUT10, RX_BYPASS_DATAOUT11, RX_BYPASS_ENAOUT, RX_BYPASS_IS_AVAILOUT, RX_BYPASS_IS_BADLYFRAMEDOUT, RX_BYPASS_IS_OVERFLOWOUT, RX_BYPASS_IS_SYNCEDOUT, RX_BYPASS_IS_SYNCWORDOUT, RX_CHANOUT0 +, RX_CHANOUT1, RX_CHANOUT2, RX_CHANOUT3, RX_DATAOUT0, RX_DATAOUT1, RX_DATAOUT2, RX_DATAOUT3, RX_ENAOUT0, RX_ENAOUT1, RX_ENAOUT2, RX_ENAOUT3, RX_EOPOUT0, RX_EOPOUT1, RX_EOPOUT2, RX_EOPOUT3, RX_ERROUT0, RX_ERROUT1, RX_ERROUT2, RX_ERROUT3, RX_MTYOUT0, RX_MTYOUT1 +, RX_MTYOUT2, RX_MTYOUT3, RX_OVFOUT, RX_SOPOUT0, RX_SOPOUT1, RX_SOPOUT2, RX_SOPOUT3, STAT_RX_ALIGNED, STAT_RX_ALIGNED_ERR, STAT_RX_BAD_TYPE_ERR, STAT_RX_BURSTMAX_ERR, STAT_RX_BURST_ERR, STAT_RX_CRC24_ERR, STAT_RX_CRC32_ERR, STAT_RX_CRC32_VALID, STAT_RX_DESCRAM_ERR, STAT_RX_DIAGWORD_INTFSTAT, STAT_RX_DIAGWORD_LANESTAT, STAT_RX_FC_STAT, STAT_RX_FRAMING_ERR, STAT_RX_MEOP_ERR +, STAT_RX_MF_ERR, STAT_RX_MF_LEN_ERR, STAT_RX_MF_REPEAT_ERR, STAT_RX_MISALIGNED, STAT_RX_MSOP_ERR, STAT_RX_MUBITS, STAT_RX_MUBITS_UPDATED, STAT_RX_OVERFLOW_ERR, STAT_RX_RETRANS_CRC24_ERR, STAT_RX_RETRANS_DISC, STAT_RX_RETRANS_LATENCY, STAT_RX_RETRANS_REQ, STAT_RX_RETRANS_RETRY_ERR, STAT_RX_RETRANS_SEQ, STAT_RX_RETRANS_SEQ_UPDATED, STAT_RX_RETRANS_STATE, STAT_RX_RETRANS_SUBSEQ, STAT_RX_RETRANS_WDOG_ERR, STAT_RX_RETRANS_WRAP_ERR, STAT_RX_SYNCED, STAT_RX_SYNCED_ERR +, STAT_RX_WORD_SYNC, STAT_TX_BURST_ERR, STAT_TX_ERRINJ_BITERR_DONE, STAT_TX_OVERFLOW_ERR, STAT_TX_RETRANS_BURST_ERR, STAT_TX_RETRANS_BUSY, STAT_TX_RETRANS_RAM_PERROUT, STAT_TX_RETRANS_RAM_RADDR, STAT_TX_RETRANS_RAM_RD_B0, STAT_TX_RETRANS_RAM_RD_B1, STAT_TX_RETRANS_RAM_RD_B2, STAT_TX_RETRANS_RAM_RD_B3, STAT_TX_RETRANS_RAM_RSEL, STAT_TX_RETRANS_RAM_WADDR, STAT_TX_RETRANS_RAM_WDATA, STAT_TX_RETRANS_RAM_WE_B0, STAT_TX_RETRANS_RAM_WE_B1, STAT_TX_RETRANS_RAM_WE_B2, STAT_TX_RETRANS_RAM_WE_B3, STAT_TX_UNDERFLOW_ERR, TX_OVFOUT +, TX_RDYOUT, TX_SERDES_DATA00, TX_SERDES_DATA01, TX_SERDES_DATA02, TX_SERDES_DATA03, TX_SERDES_DATA04, TX_SERDES_DATA05, TX_SERDES_DATA06, TX_SERDES_DATA07, TX_SERDES_DATA08, TX_SERDES_DATA09, TX_SERDES_DATA10, TX_SERDES_DATA11, CORE_CLK, CTL_RX_FORCE_RESYNC, CTL_RX_RETRANS_ACK, CTL_RX_RETRANS_ENABLE, CTL_RX_RETRANS_ERRIN, CTL_RX_RETRANS_FORCE_REQ, CTL_RX_RETRANS_RESET, CTL_RX_RETRANS_RESET_MODE +, CTL_TX_DIAGWORD_INTFSTAT, CTL_TX_DIAGWORD_LANESTAT, CTL_TX_ENABLE, CTL_TX_ERRINJ_BITERR_GO, CTL_TX_ERRINJ_BITERR_LANE, CTL_TX_FC_STAT, CTL_TX_MUBITS, CTL_TX_RETRANS_ENABLE, CTL_TX_RETRANS_RAM_PERRIN, CTL_TX_RETRANS_RAM_RDATA, CTL_TX_RETRANS_REQ, CTL_TX_RETRANS_REQ_VALID, CTL_TX_RLIM_DELTA, CTL_TX_RLIM_ENABLE, CTL_TX_RLIM_INTV, CTL_TX_RLIM_MAX, DRP_ADDR, DRP_CLK, DRP_DI, DRP_EN, DRP_WE +, LBUS_CLK, RX_BYPASS_FORCE_REALIGNIN, RX_BYPASS_RDIN, RX_RESET, RX_SERDES_CLK, RX_SERDES_DATA00, RX_SERDES_DATA01, RX_SERDES_DATA02, RX_SERDES_DATA03, RX_SERDES_DATA04, RX_SERDES_DATA05, RX_SERDES_DATA06, RX_SERDES_DATA07, RX_SERDES_DATA08, RX_SERDES_DATA09, RX_SERDES_DATA10, RX_SERDES_DATA11, RX_SERDES_RESET, TX_BCTLIN0, TX_BCTLIN1, TX_BCTLIN2 +, TX_BCTLIN3, TX_BYPASS_CTRLIN, TX_BYPASS_DATAIN00, TX_BYPASS_DATAIN01, TX_BYPASS_DATAIN02, TX_BYPASS_DATAIN03, TX_BYPASS_DATAIN04, TX_BYPASS_DATAIN05, TX_BYPASS_DATAIN06, TX_BYPASS_DATAIN07, TX_BYPASS_DATAIN08, TX_BYPASS_DATAIN09, TX_BYPASS_DATAIN10, TX_BYPASS_DATAIN11, TX_BYPASS_ENAIN, TX_BYPASS_GEARBOX_SEQIN, TX_BYPASS_MFRAMER_STATEIN, TX_CHANIN0, TX_CHANIN1, TX_CHANIN2, TX_CHANIN3 +, TX_DATAIN0, TX_DATAIN1, TX_DATAIN2, TX_DATAIN3, TX_ENAIN0, TX_ENAIN1, TX_ENAIN2, TX_ENAIN3, TX_EOPIN0, TX_EOPIN1, TX_EOPIN2, TX_EOPIN3, TX_ERRIN0, TX_ERRIN1, TX_ERRIN2, TX_ERRIN3, TX_MTYIN0, TX_MTYIN1, TX_MTYIN2, TX_MTYIN3, TX_RESET +, TX_SERDES_REFCLK, TX_SERDES_REFCLK_RESET, TX_SOPIN0, TX_SOPIN1, TX_SOPIN2, TX_SOPIN3); parameter BYPASS = "FALSE"; parameter [1:0] CTL_RX_BURSTMAX = 2'h3; parameter [1:0] CTL_RX_CHAN_EXT = 2'h0; @@ -33825,7 +34522,17 @@ module ILKNE4 (...); endmodule (* keep *) -module VCU (...); +module VCU(VCUPLARREADYAXILITEAPB, VCUPLAWREADYAXILITEAPB, VCUPLBRESPAXILITEAPB, VCUPLBVALIDAXILITEAPB, VCUPLCORESTATUSCLKPLL, VCUPLDECARADDR0, VCUPLDECARADDR1, VCUPLDECARBURST0, VCUPLDECARBURST1, VCUPLDECARCACHE0, VCUPLDECARCACHE1, VCUPLDECARID0, VCUPLDECARID1, VCUPLDECARLEN0, VCUPLDECARLEN1, VCUPLDECARPROT0, VCUPLDECARPROT1, VCUPLDECARQOS0, VCUPLDECARQOS1, VCUPLDECARSIZE0, VCUPLDECARSIZE1 +, VCUPLDECARVALID0, VCUPLDECARVALID1, VCUPLDECAWADDR0, VCUPLDECAWADDR1, VCUPLDECAWBURST0, VCUPLDECAWBURST1, VCUPLDECAWCACHE0, VCUPLDECAWCACHE1, VCUPLDECAWID0, VCUPLDECAWID1, VCUPLDECAWLEN0, VCUPLDECAWLEN1, VCUPLDECAWPROT0, VCUPLDECAWPROT1, VCUPLDECAWQOS0, VCUPLDECAWQOS1, VCUPLDECAWSIZE0, VCUPLDECAWSIZE1, VCUPLDECAWVALID0, VCUPLDECAWVALID1, VCUPLDECBREADY0 +, VCUPLDECBREADY1, VCUPLDECRREADY0, VCUPLDECRREADY1, VCUPLDECWDATA0, VCUPLDECWDATA1, VCUPLDECWLAST0, VCUPLDECWLAST1, VCUPLDECWVALID0, VCUPLDECWVALID1, VCUPLENCALL2CADDR, VCUPLENCALL2CRVALID, VCUPLENCALL2CWDATA, VCUPLENCALL2CWVALID, VCUPLENCARADDR0, VCUPLENCARADDR1, VCUPLENCARBURST0, VCUPLENCARBURST1, VCUPLENCARCACHE0, VCUPLENCARCACHE1, VCUPLENCARID0, VCUPLENCARID1 +, VCUPLENCARLEN0, VCUPLENCARLEN1, VCUPLENCARPROT0, VCUPLENCARPROT1, VCUPLENCARQOS0, VCUPLENCARQOS1, VCUPLENCARSIZE0, VCUPLENCARSIZE1, VCUPLENCARVALID0, VCUPLENCARVALID1, VCUPLENCAWADDR0, VCUPLENCAWADDR1, VCUPLENCAWBURST0, VCUPLENCAWBURST1, VCUPLENCAWCACHE0, VCUPLENCAWCACHE1, VCUPLENCAWID0, VCUPLENCAWID1, VCUPLENCAWLEN0, VCUPLENCAWLEN1, VCUPLENCAWPROT0 +, VCUPLENCAWPROT1, VCUPLENCAWQOS0, VCUPLENCAWQOS1, VCUPLENCAWSIZE0, VCUPLENCAWSIZE1, VCUPLENCAWVALID0, VCUPLENCAWVALID1, VCUPLENCBREADY0, VCUPLENCBREADY1, VCUPLENCRREADY0, VCUPLENCRREADY1, VCUPLENCWDATA0, VCUPLENCWDATA1, VCUPLENCWLAST0, VCUPLENCWLAST1, VCUPLENCWVALID0, VCUPLENCWVALID1, VCUPLMCUMAXIICDCARADDR, VCUPLMCUMAXIICDCARBURST, VCUPLMCUMAXIICDCARCACHE, VCUPLMCUMAXIICDCARID +, VCUPLMCUMAXIICDCARLEN, VCUPLMCUMAXIICDCARLOCK, VCUPLMCUMAXIICDCARPROT, VCUPLMCUMAXIICDCARQOS, VCUPLMCUMAXIICDCARSIZE, VCUPLMCUMAXIICDCARVALID, VCUPLMCUMAXIICDCAWADDR, VCUPLMCUMAXIICDCAWBURST, VCUPLMCUMAXIICDCAWCACHE, VCUPLMCUMAXIICDCAWID, VCUPLMCUMAXIICDCAWLEN, VCUPLMCUMAXIICDCAWLOCK, VCUPLMCUMAXIICDCAWPROT, VCUPLMCUMAXIICDCAWQOS, VCUPLMCUMAXIICDCAWSIZE, VCUPLMCUMAXIICDCAWVALID, VCUPLMCUMAXIICDCBREADY, VCUPLMCUMAXIICDCRREADY, VCUPLMCUMAXIICDCWDATA, VCUPLMCUMAXIICDCWLAST, VCUPLMCUMAXIICDCWSTRB +, VCUPLMCUMAXIICDCWVALID, VCUPLMCUSTATUSCLKPLL, VCUPLPINTREQ, VCUPLPLLSTATUSPLLLOCK, VCUPLPWRSUPPLYSTATUSVCCAUX, VCUPLPWRSUPPLYSTATUSVCUINT, VCUPLRDATAAXILITEAPB, VCUPLRRESPAXILITEAPB, VCUPLRVALIDAXILITEAPB, VCUPLWREADYAXILITEAPB, INITPLVCUGASKETCLAMPCONTROLLVLSHVCCINTD, PLVCUARADDRAXILITEAPB, PLVCUARPROTAXILITEAPB, PLVCUARVALIDAXILITEAPB, PLVCUAWADDRAXILITEAPB, PLVCUAWPROTAXILITEAPB, PLVCUAWVALIDAXILITEAPB, PLVCUAXIDECCLK, PLVCUAXIENCCLK, PLVCUAXILITECLK, PLVCUAXIMCUCLK +, PLVCUBREADYAXILITEAPB, PLVCUCORECLK, PLVCUDECARREADY0, PLVCUDECARREADY1, PLVCUDECAWREADY0, PLVCUDECAWREADY1, PLVCUDECBID0, PLVCUDECBID1, PLVCUDECBRESP0, PLVCUDECBRESP1, PLVCUDECBVALID0, PLVCUDECBVALID1, PLVCUDECRDATA0, PLVCUDECRDATA1, PLVCUDECRID0, PLVCUDECRID1, PLVCUDECRLAST0, PLVCUDECRLAST1, PLVCUDECRRESP0, PLVCUDECRRESP1, PLVCUDECRVALID0 +, PLVCUDECRVALID1, PLVCUDECWREADY0, PLVCUDECWREADY1, PLVCUENCALL2CRDATA, PLVCUENCALL2CRREADY, PLVCUENCARREADY0, PLVCUENCARREADY1, PLVCUENCAWREADY0, PLVCUENCAWREADY1, PLVCUENCBID0, PLVCUENCBID1, PLVCUENCBRESP0, PLVCUENCBRESP1, PLVCUENCBVALID0, PLVCUENCBVALID1, PLVCUENCL2CCLK, PLVCUENCRDATA0, PLVCUENCRDATA1, PLVCUENCRID0, PLVCUENCRID1, PLVCUENCRLAST0 +, PLVCUENCRLAST1, PLVCUENCRRESP0, PLVCUENCRRESP1, PLVCUENCRVALID0, PLVCUENCRVALID1, PLVCUENCWREADY0, PLVCUENCWREADY1, PLVCUMCUCLK, PLVCUMCUMAXIICDCARREADY, PLVCUMCUMAXIICDCAWREADY, PLVCUMCUMAXIICDCBID, PLVCUMCUMAXIICDCBRESP, PLVCUMCUMAXIICDCBVALID, PLVCUMCUMAXIICDCRDATA, PLVCUMCUMAXIICDCRID, PLVCUMCUMAXIICDCRLAST, PLVCUMCUMAXIICDCRRESP, PLVCUMCUMAXIICDCRVALID, PLVCUMCUMAXIICDCWREADY, PLVCUPLLREFCLKPL, PLVCURAWRSTN +, PLVCURREADYAXILITEAPB, PLVCUWDATAAXILITEAPB, PLVCUWSTRBAXILITEAPB, PLVCUWVALIDAXILITEAPB); parameter integer CORECLKREQ = 667; parameter integer DECHORRESOLUTION = 3840; parameter DECODERCHROMAFORMAT = "4_2_2"; @@ -34057,7 +34764,9 @@ module VCU (...); input PLVCUWVALIDAXILITEAPB; endmodule -module FE (...); +module FE(DEBUG_DOUT, DEBUG_PHASE, INTERRUPT, M_AXIS_DOUT_TDATA, M_AXIS_DOUT_TLAST, M_AXIS_DOUT_TVALID, M_AXIS_STATUS_TDATA, M_AXIS_STATUS_TVALID, SPARE_OUT, S_AXIS_CTRL_TREADY, S_AXIS_DIN_TREADY, S_AXIS_DIN_WORDS_TREADY, S_AXIS_DOUT_WORDS_TREADY, S_AXI_ARREADY, S_AXI_AWREADY, S_AXI_BVALID, S_AXI_RDATA, S_AXI_RVALID, S_AXI_WREADY, CORE_CLK, DEBUG_CLK_EN +, DEBUG_EN, DEBUG_SEL_IN, M_AXIS_DOUT_ACLK, M_AXIS_DOUT_TREADY, M_AXIS_STATUS_ACLK, M_AXIS_STATUS_TREADY, RESET_N, SPARE_IN, S_AXIS_CTRL_ACLK, S_AXIS_CTRL_TDATA, S_AXIS_CTRL_TVALID, S_AXIS_DIN_ACLK, S_AXIS_DIN_TDATA, S_AXIS_DIN_TLAST, S_AXIS_DIN_TVALID, S_AXIS_DIN_WORDS_ACLK, S_AXIS_DIN_WORDS_TDATA, S_AXIS_DIN_WORDS_TLAST, S_AXIS_DIN_WORDS_TVALID, S_AXIS_DOUT_WORDS_ACLK, S_AXIS_DOUT_WORDS_TDATA +, S_AXIS_DOUT_WORDS_TLAST, S_AXIS_DOUT_WORDS_TVALID, S_AXI_ACLK, S_AXI_ARADDR, S_AXI_ARVALID, S_AXI_AWADDR, S_AXI_AWVALID, S_AXI_BREADY, S_AXI_RREADY, S_AXI_WDATA, S_AXI_WVALID); parameter MODE = "TURBO_DECODE"; parameter real PHYSICAL_UTILIZATION = 100.00; parameter SIM_DEVICE = "ULTRASCALE_PLUS"; From aaebce7adc453c71c38cd3e3cab305518ff79174 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Wed, 14 Jan 2026 07:39:45 +1300 Subject: [PATCH 108/291] log_help: Don't reformat codeblocks --- kernel/log_help.cc | 42 +++++++++++++++++++++++------------------- 1 file changed, 23 insertions(+), 19 deletions(-) diff --git a/kernel/log_help.cc b/kernel/log_help.cc index 93b91b08b..01c9a93f6 100644 --- a/kernel/log_help.cc +++ b/kernel/log_help.cc @@ -78,7 +78,7 @@ ContentListing* ContentListing::open_option(const string &text, } #define MAX_LINE_LEN 80 -void log_pass_str(const std::string &pass_str, std::string indent_str, bool leading_newline=false) { +void log_body_str(const std::string &pass_str, std::string indent_str, bool leading_newline=false, bool is_formatted=false) { if (pass_str.empty()) return; std::istringstream iss(pass_str); @@ -86,26 +86,30 @@ void log_pass_str(const std::string &pass_str, std::string indent_str, bool lead log("\n"); for (std::string line; std::getline(iss, line);) { log("%s", indent_str); - auto curr_len = indent_str.length(); - std::istringstream lss(line); - for (std::string word; std::getline(lss, word, ' ');) { - while (word[0] == '`' && word.back() == '`') - word = word.substr(1, word.length()-2); - if (curr_len + word.length() >= MAX_LINE_LEN-1) { - curr_len = 0; - log("\n%s", indent_str); - } - if (word.length()) { - log("%s ", word); - curr_len += word.length() + 1; + if (is_formatted) { + log("%s", line); + } else { + auto curr_len = indent_str.length(); + std::istringstream lss(line); + for (std::string word; std::getline(lss, word, ' ');) { + while (word[0] == '`' && word.back() == '`') + word = word.substr(1, word.length()-2); + if (curr_len + word.length() >= MAX_LINE_LEN-1) { + curr_len = 0; + log("\n%s", indent_str); + } + if (word.length()) { + log("%s ", word); + curr_len += word.length() + 1; + } } } log("\n"); } } -void log_pass_str(const std::string &pass_str, int indent=0, bool leading_newline=false) { +void log_body(const ContentListing &content, int indent=0, bool leading_newline=false) { std::string indent_str(indent*4, ' '); - log_pass_str(pass_str, indent_str, leading_newline); + log_body_str(content.body, indent_str, leading_newline, content.type.compare("code") == 0); } PrettyHelp *current_help = nullptr; @@ -134,16 +138,16 @@ void PrettyHelp::log_help() const { for (auto &content : _root_listing) { if (content.type.compare("usage") == 0) { - log_pass_str(content.body, 1, true); + log_body(content, 1, true); log("\n"); } else if (content.type.compare("option") == 0) { - log_pass_str(content.body, 1); + log_body(content, 1); for (auto text : content) { - log_pass_str(text.body, 2); + log_body(text, 2); log("\n"); } } else { - log_pass_str(content.body, 0); + log_body(content, 0); log("\n"); } } From 4031310ebb7b9d5278aa6373692184266dd9b3b6 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Wed, 28 Jan 2026 08:10:31 +1300 Subject: [PATCH 109/291] linux_perf.cc: Use formatted_help Gets the codeblock formatting better. Also fold the on|off into a single usage. --- passes/cmds/linux_perf.cc | 42 +++++++++++++++++++-------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/passes/cmds/linux_perf.cc b/passes/cmds/linux_perf.cc index 5c2c23b6a..fcd529d78 100644 --- a/passes/cmds/linux_perf.cc +++ b/passes/cmds/linux_perf.cc @@ -32,28 +32,28 @@ struct LinuxPerf : public Pass { LinuxPerf() : Pass("linux_perf", "turn linux perf recording off or on") { internal(); } - void help() override + bool formatted_help() override { - log("\n"); - log(" linux_perf [mode]\n"); - log("\n"); - log("This pass turns Linux 'perf' profiling on or off, when it has been configured to use control FIFOs.\n"); - log("\n"); - log("Example shell command line:\n"); - log("mkfifo /tmp/perf.fifo /tmp/perf-ack.fifo\n"); - log("YOSYS_PERF_CTL=/tmp/perf.fifo YOSYS_PERF_ACK=/tmp/perf-ack.fifo \\\n"); - log(" perf record --latency --delay=-1 \\\n"); - log(" --control=fifo:/tmp/perf.fifo,/tmp/perf-ack.fifo --call-graph=dwarf ./yosys -dt -p \\\n"); - log(" \"read_rtlil design.rtlil; linux_perf on; opt_clean; linux_perf off\"\n"); - log("\n"); - log(" linux_perf on\n"); - log("\n"); - log("Start perf recording. YOSYS_PERF_CTL and YOSYS_PERF_ACK must point to Linux perf control FIFOs.\n"); - log("\n"); - log(" linux_perf off\n"); - log("\n"); - log("Stop perf recording.\n"); - log("\n"); + auto *help = PrettyHelp::get_current(); + + auto content_root = help->get_root(); + + content_root->usage("linux_perf [on|off]"); + + content_root->paragraph( + "This pass turns Linux 'perf' profiling on or off, when it has been configured to use control FIFOs." + "YOSYS_PERF_CTL and YOSYS_PERF_ACK must point to Linux perf control FIFOs." + ); + content_root->paragraph("Example shell command line:"); + content_root->codeblock( + "mkfifo /tmp/perf.fifo /tmp/perf-ack.fifo\n" + "YOSYS_PERF_CTL=/tmp/perf.fifo YOSYS_PERF_ACK=/tmp/perf-ack.fifo \\\n" + " perf record --latency --delay=-1 \\\n" + " --control=fifo:/tmp/perf.fifo,/tmp/perf-ack.fifo --call-graph=dwarf ./yosys -dt -p \\\n" + " \"read_rtlil design.rtlil; linux_perf on; opt_clean; linux_perf off\"\n" + ); + + return true; } void execute(std::vector args, RTLIL::Design *) override { From 8ed7ac04d887a68f3787ac37f75fd2cd08392313 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Wed, 28 Jan 2026 08:17:50 +1300 Subject: [PATCH 110/291] linux_perf.cc: Fix overlength codeblock --- passes/cmds/linux_perf.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/cmds/linux_perf.cc b/passes/cmds/linux_perf.cc index fcd529d78..967ccd2f8 100644 --- a/passes/cmds/linux_perf.cc +++ b/passes/cmds/linux_perf.cc @@ -49,8 +49,8 @@ struct LinuxPerf : public Pass { "mkfifo /tmp/perf.fifo /tmp/perf-ack.fifo\n" "YOSYS_PERF_CTL=/tmp/perf.fifo YOSYS_PERF_ACK=/tmp/perf-ack.fifo \\\n" " perf record --latency --delay=-1 \\\n" - " --control=fifo:/tmp/perf.fifo,/tmp/perf-ack.fifo --call-graph=dwarf ./yosys -dt -p \\\n" - " \"read_rtlil design.rtlil; linux_perf on; opt_clean; linux_perf off\"\n" + " --control=fifo:/tmp/perf.fifo,/tmp/perf-ack.fifo --call-graph=dwarf ./yosys \\\n" + " -dt -p \"read_rtlil design.rtlil; linux_perf on; opt_clean; linux_perf off\"\n" ); return true; From fdff3dac2bd60306494c593ec20f17ceff35b965 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 28 Jan 2026 09:38:33 +0100 Subject: [PATCH 111/291] Update ABC as per 2026-01-28 --- abc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/abc b/abc index 01ad37aad..9dcae29da 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit 01ad37aada7566964219c993818af75234f93ce0 +Subproject commit 9dcae29da366ba9b7b518a8426545811be1ea61e From fc2b7c317f64e7b75f2e0082fe2e0483bde55bf2 Mon Sep 17 00:00:00 2001 From: Natalia Date: Wed, 28 Jan 2026 03:14:20 -0800 Subject: [PATCH 112/291] linux_perf: include unistd for POSIX I/O --- passes/cmds/linux_perf.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/passes/cmds/linux_perf.cc b/passes/cmds/linux_perf.cc index 967ccd2f8..40cae3d91 100644 --- a/passes/cmds/linux_perf.cc +++ b/passes/cmds/linux_perf.cc @@ -23,6 +23,7 @@ #include #include +#include USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN From 188082551abce31bbb5d7d911320d011147545f8 Mon Sep 17 00:00:00 2001 From: Natalia Date: Wed, 28 Jan 2026 03:37:08 -0800 Subject: [PATCH 113/291] verific: only use MFCU when VHDL present --- frontends/verific/verific.cc | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 67e70d5e7..4012708c2 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3746,20 +3746,34 @@ struct VerificPass : public Pass { #ifdef VERIFIC_VHDL_SUPPORT int i; + Array *file_names_sv = new Array(POINTER_HASH); + bool has_vhdl = false; FOREACH_ARRAY_ITEM(file_names, i, filename) { std::string filename_str = filename; if ((filename_str.substr(filename_str.find_last_of(".") + 1) == "vhd") || (filename_str.substr(filename_str.find_last_of(".") + 1) == "vhdl")) { + has_vhdl = true; vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2019").c_str()); if (!vhdl_file::Analyze(filename, work.c_str(), vhdl_file::VHDL_2019)) { verific_error_msg.clear(); log_cmd_error("Reading VHDL sources failed.\n"); } - } else if (!veri_file::Analyze(filename, analysis_mode, work.c_str())) { - verific_error_msg.clear(); - log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); + } else { + file_names_sv->Insert(strdup(filename)); } } + if (has_vhdl) { + FOREACH_ARRAY_ITEM(file_names_sv, i, filename) { + if (!veri_file::Analyze(filename, analysis_mode, work.c_str())) { + verific_error_msg.clear(); + log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); + } + } + } else if (!veri_file::AnalyzeMultipleFiles(file_names_sv, analysis_mode, work.c_str(), veri_file::MFCU)) { + verific_error_msg.clear(); + log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); + } + delete file_names_sv; #else if (!veri_file::AnalyzeMultipleFiles(file_names, analysis_mode, work.c_str(), veri_file::MFCU)) { verific_error_msg.clear(); From 6a6e5f0f54900d0c60d4095bb62bb61e56935703 Mon Sep 17 00:00:00 2001 From: Natalia Date: Wed, 28 Jan 2026 03:44:33 -0800 Subject: [PATCH 114/291] linux_perf: only include unistd on Linux --- passes/cmds/linux_perf.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/cmds/linux_perf.cc b/passes/cmds/linux_perf.cc index 40cae3d91..2b75a3a79 100644 --- a/passes/cmds/linux_perf.cc +++ b/passes/cmds/linux_perf.cc @@ -23,12 +23,12 @@ #include #include -#include USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN #ifdef __linux__ +#include struct LinuxPerf : public Pass { LinuxPerf() : Pass("linux_perf", "turn linux perf recording off or on") { internal(); From 74c601db0fbd5573620f1344c55e9c61f5e6ccdc Mon Sep 17 00:00:00 2001 From: Natalia Date: Wed, 28 Jan 2026 03:55:42 -0800 Subject: [PATCH 115/291] tests/verific: add mixed -f list case --- tests/verific/mixed_flist.flist | 2 ++ tests/verific/mixed_flist.sv | 3 +++ tests/verific/mixed_flist.vhd | 14 ++++++++++++++ tests/verific/mixed_flist.ys | 5 +++++ 4 files changed, 24 insertions(+) create mode 100644 tests/verific/mixed_flist.flist create mode 100644 tests/verific/mixed_flist.sv create mode 100644 tests/verific/mixed_flist.vhd create mode 100644 tests/verific/mixed_flist.ys diff --git a/tests/verific/mixed_flist.flist b/tests/verific/mixed_flist.flist new file mode 100644 index 000000000..d4edb8532 --- /dev/null +++ b/tests/verific/mixed_flist.flist @@ -0,0 +1,2 @@ +mixed_flist.sv +mixed_flist.vhd diff --git a/tests/verific/mixed_flist.sv b/tests/verific/mixed_flist.sv new file mode 100644 index 000000000..83c04054f --- /dev/null +++ b/tests/verific/mixed_flist.sv @@ -0,0 +1,3 @@ +module sv_top(input logic a, output logic y); + assign y = a; +endmodule diff --git a/tests/verific/mixed_flist.vhd b/tests/verific/mixed_flist.vhd new file mode 100644 index 000000000..25a10f963 --- /dev/null +++ b/tests/verific/mixed_flist.vhd @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity vhdl_mod is + port ( + a : in std_logic; + y : out std_logic + ); +end entity vhdl_mod; + +architecture rtl of vhdl_mod is +begin + y <= a; +end architecture rtl; diff --git a/tests/verific/mixed_flist.ys b/tests/verific/mixed_flist.ys new file mode 100644 index 000000000..4cbdb1e59 --- /dev/null +++ b/tests/verific/mixed_flist.ys @@ -0,0 +1,5 @@ +verific -f -sv mixed_flist.flist +verific -import sv_top +verific -import vhdl_mod +select -assert-mod-count 1 sv_top +select -assert-mod-count 1 vhdl_mod From 8c2ef89732c0e6755b17be949ec8296ad503b509 Mon Sep 17 00:00:00 2001 From: Natalia Date: Wed, 28 Jan 2026 04:13:04 -0800 Subject: [PATCH 116/291] tests/verific: import mixed -f list with -all --- tests/verific/mixed_flist.ys | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/tests/verific/mixed_flist.ys b/tests/verific/mixed_flist.ys index 4cbdb1e59..2a0af80db 100644 --- a/tests/verific/mixed_flist.ys +++ b/tests/verific/mixed_flist.ys @@ -1,5 +1,4 @@ verific -f -sv mixed_flist.flist -verific -import sv_top -verific -import vhdl_mod +verific -import -all select -assert-mod-count 1 sv_top -select -assert-mod-count 1 vhdl_mod +select -assert-mod-count 2 From 5a64fe2d9161f24dd4fc3d67c09316c415005ff8 Mon Sep 17 00:00:00 2001 From: Natalia Date: Wed, 28 Jan 2026 04:21:13 -0800 Subject: [PATCH 117/291] tests/verific: assert module count explicitly --- tests/verific/mixed_flist.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/verific/mixed_flist.ys b/tests/verific/mixed_flist.ys index 2a0af80db..59849a5e5 100644 --- a/tests/verific/mixed_flist.ys +++ b/tests/verific/mixed_flist.ys @@ -1,4 +1,4 @@ verific -f -sv mixed_flist.flist verific -import -all select -assert-mod-count 1 sv_top -select -assert-mod-count 2 +select -assert-mod-count 2 =* From 139c38ecfa43b2b97b05376b0eccef71045b9d04 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Wed, 28 Jan 2026 18:22:12 +0000 Subject: [PATCH 118/291] Dump module details when design_equal fails --- passes/cmds/design_equal.cc | 49 ++++++++++++++++++++++++------------- 1 file changed, 32 insertions(+), 17 deletions(-) diff --git a/passes/cmds/design_equal.cc b/passes/cmds/design_equal.cc index a949db9ff..d5f0d617a 100644 --- a/passes/cmds/design_equal.cc +++ b/passes/cmds/design_equal.cc @@ -30,6 +30,21 @@ class ModuleComparator public: ModuleComparator(RTLIL::Module *mod_a, RTLIL::Module *mod_b) : mod_a(mod_a), mod_b(mod_b) {} + template + [[noreturn]] void error(FmtString...> fmt, const Args &... args) + { + formatted_error(fmt.format(args...)); + } + [[noreturn]] + void formatted_error(std::string err) + { + log("Module A: %s\n", log_id(mod_a->name)); + log_module(mod_a, " "); + log("Module B: %s\n", log_id(mod_b->name)); + log_module(mod_b, " "); + log_cmd_error("Designs are different: %s\n", err); + } + bool compare_sigbit(const RTLIL::SigBit &a, const RTLIL::SigBit &b) { if (a.wire == nullptr && b.wire == nullptr) @@ -90,13 +105,13 @@ public: { for (const auto &it : mod_a->wires_) { if (mod_b->wires_.count(it.first) == 0) - log_error("Module %s missing wire %s in second design.\n", log_id(mod_a->name), log_id(it.first)); + error("Module %s missing wire %s in second design.\n", log_id(mod_a->name), log_id(it.first)); if (std::string mismatch = compare_wires(it.second, mod_b->wires_.at(it.first)); !mismatch.empty()) - log_error("Module %s wire %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch); + error("Module %s wire %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch); } for (const auto &it : mod_b->wires_) if (mod_a->wires_.count(it.first) == 0) - log_error("Module %s missing wire %s in first design.\n", log_id(mod_b->name), log_id(it.first)); + error("Module %s missing wire %s in first design.\n", log_id(mod_b->name), log_id(it.first)); } std::string compare_memories(const RTLIL::Memory *a, const RTLIL::Memory *b) @@ -150,26 +165,26 @@ public: { for (const auto &it : mod_a->cells_) { if (mod_b->cells_.count(it.first) == 0) - log_error("Module %s missing cell %s in second design.\n", log_id(mod_a->name), log_id(it.first)); + error("Module %s missing cell %s in second design.\n", log_id(mod_a->name), log_id(it.first)); if (std::string mismatch = compare_cells(it.second, mod_b->cells_.at(it.first)); !mismatch.empty()) - log_error("Module %s cell %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch); + error("Module %s cell %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch); } for (const auto &it : mod_b->cells_) if (mod_a->cells_.count(it.first) == 0) - log_error("Module %s missing cell %s in first design.\n", log_id(mod_b->name), log_id(it.first)); + error("Module %s missing cell %s in first design.\n", log_id(mod_b->name), log_id(it.first)); } void check_memories() { for (const auto &it : mod_a->memories) { if (mod_b->memories.count(it.first) == 0) - log_error("Module %s missing memory %s in second design.\n", log_id(mod_a->name), log_id(it.first)); + error("Module %s missing memory %s in second design.\n", log_id(mod_a->name), log_id(it.first)); if (std::string mismatch = compare_memories(it.second, mod_b->memories.at(it.first)); !mismatch.empty()) - log_error("Module %s memory %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch); + error("Module %s memory %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch); } for (const auto &it : mod_b->memories) if (mod_a->memories.count(it.first) == 0) - log_error("Module %s missing memory %s in first design.\n", log_id(mod_b->name), log_id(it.first)); + error("Module %s missing memory %s in first design.\n", log_id(mod_b->name), log_id(it.first)); } std::string compare_case_rules(const RTLIL::CaseRule *a, const RTLIL::CaseRule *b) @@ -270,13 +285,13 @@ public: { for (auto &it : mod_a->processes) { if (mod_b->processes.count(it.first) == 0) - log_error("Module %s missing process %s in second design.\n", log_id(mod_a->name), log_id(it.first)); + error("Module %s missing process %s in second design.\n", log_id(mod_a->name), log_id(it.first)); if (std::string mismatch = compare_processes(it.second, mod_b->processes.at(it.first)); !mismatch.empty()) - log_error("Module %s process %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch.c_str()); + error("Module %s process %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch.c_str()); } for (auto &it : mod_b->processes) if (mod_a->processes.count(it.first) == 0) - log_error("Module %s missing process %s in first design.\n", log_id(mod_b->name), log_id(it.first)); + error("Module %s missing process %s in first design.\n", log_id(mod_b->name), log_id(it.first)); } void check_connections() @@ -284,13 +299,13 @@ public: const auto &conns_a = mod_a->connections(); const auto &conns_b = mod_b->connections(); if (conns_a.size() != conns_b.size()) { - log_error("Module %s connection count differs: %zu != %zu\n", log_id(mod_a->name), conns_a.size(), conns_b.size()); + error("Module %s connection count differs: %zu != %zu\n", log_id(mod_a->name), conns_a.size(), conns_b.size()); } else { for (size_t i = 0; i < conns_a.size(); i++) { if (!compare_sigspec(conns_a[i].first, conns_b[i].first)) - log_error("Module %s connection %zu LHS %s != %s.\n", log_id(mod_a->name), i, log_signal(conns_a[i].first), log_signal(conns_b[i].first)); + error("Module %s connection %zu LHS %s != %s.\n", log_id(mod_a->name), i, log_signal(conns_a[i].first), log_signal(conns_b[i].first)); if (!compare_sigspec(conns_a[i].second, conns_b[i].second)) - log_error("Module %s connection %zu RHS %s != %s.\n", log_id(mod_a->name), i, log_signal(conns_a[i].second), log_signal(conns_b[i].second)); + error("Module %s connection %zu RHS %s != %s.\n", log_id(mod_a->name), i, log_signal(conns_a[i].second), log_signal(conns_b[i].second)); } } } @@ -298,9 +313,9 @@ public: void check() { if (mod_a->name != mod_b->name) - log_error("Modules have different names: %s != %s\n", log_id(mod_a->name), log_id(mod_b->name)); + error("Modules have different names: %s != %s\n", log_id(mod_a->name), log_id(mod_b->name)); if (std::string mismatch = compare_attributes(mod_a, mod_b); !mismatch.empty()) - log_error("Module %s %s.\n", log_id(mod_a->name), mismatch); + error("Module %s %s.\n", log_id(mod_a->name), mismatch); check_wires(); check_cells(); check_memories(); From 1f6a13dac780673fb340322024ea32f24f297561 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Thu, 29 Jan 2026 00:31:03 +0000 Subject: [PATCH 119/291] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 03a2ad64a..54826ee03 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.61+80 +YOSYS_VER := 0.61+97 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From b6c148f84a5f08f73e23c187148261cff9301e4f Mon Sep 17 00:00:00 2001 From: Natalia Date: Wed, 28 Jan 2026 22:46:10 -0800 Subject: [PATCH 120/291] tests/verific: ensure mixed -f requires VHDL unit --- tests/verific/mixed_flist.sv | 3 ++- tests/verific/mixed_flist.ys | 3 +-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/verific/mixed_flist.sv b/tests/verific/mixed_flist.sv index 83c04054f..28e073891 100644 --- a/tests/verific/mixed_flist.sv +++ b/tests/verific/mixed_flist.sv @@ -1,3 +1,4 @@ module sv_top(input logic a, output logic y); - assign y = a; + // Instantiates VHDL entity to ensure mixed -f list is required + vhdl_mod u_vhdl(.a(a), .y(y)); endmodule diff --git a/tests/verific/mixed_flist.ys b/tests/verific/mixed_flist.ys index 59849a5e5..9f5fe607a 100644 --- a/tests/verific/mixed_flist.ys +++ b/tests/verific/mixed_flist.ys @@ -1,4 +1,3 @@ verific -f -sv mixed_flist.flist -verific -import -all +verific -import sv_top select -assert-mod-count 1 sv_top -select -assert-mod-count 2 =* From 8d504ecb48c2338d9f6991ee4e9c0222761ed36a Mon Sep 17 00:00:00 2001 From: Natalia Date: Thu, 29 Jan 2026 00:03:28 -0800 Subject: [PATCH 121/291] verific: use MFCU for SV file list --- frontends/verific/verific.cc | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 4012708c2..299b38d16 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3747,12 +3747,10 @@ struct VerificPass : public Pass { #ifdef VERIFIC_VHDL_SUPPORT int i; Array *file_names_sv = new Array(POINTER_HASH); - bool has_vhdl = false; FOREACH_ARRAY_ITEM(file_names, i, filename) { std::string filename_str = filename; if ((filename_str.substr(filename_str.find_last_of(".") + 1) == "vhd") || (filename_str.substr(filename_str.find_last_of(".") + 1) == "vhdl")) { - has_vhdl = true; vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2019").c_str()); if (!vhdl_file::Analyze(filename, work.c_str(), vhdl_file::VHDL_2019)) { verific_error_msg.clear(); @@ -3762,14 +3760,7 @@ struct VerificPass : public Pass { file_names_sv->Insert(strdup(filename)); } } - if (has_vhdl) { - FOREACH_ARRAY_ITEM(file_names_sv, i, filename) { - if (!veri_file::Analyze(filename, analysis_mode, work.c_str())) { - verific_error_msg.clear(); - log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); - } - } - } else if (!veri_file::AnalyzeMultipleFiles(file_names_sv, analysis_mode, work.c_str(), veri_file::MFCU)) { + if (!veri_file::AnalyzeMultipleFiles(file_names_sv, analysis_mode, work.c_str(), veri_file::MFCU)) { verific_error_msg.clear(); log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); } From 6007b68e9ce705f851970596d0555a5e3ac1c5b6 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 29 Jan 2026 09:30:12 +0100 Subject: [PATCH 122/291] ABC update (MINGW fix) --- abc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/abc b/abc index 9dcae29da..79010216c 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit 9dcae29da366ba9b7b518a8426545811be1ea61e +Subproject commit 79010216cb87427dd7a0c8d38f156494221be006 From b70f527c67d24526c3f26e89439d046572829a2a Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 29 Jan 2026 10:32:30 +0100 Subject: [PATCH 123/291] verific: fixed -sv2017 option and added ability to set VHDL standard if applicable --- frontends/verific/verific.cc | 41 +++++++++++++++++++++++++++++++++--- 1 file changed, 38 insertions(+), 3 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 299b38d16..9f13eee23 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3163,6 +3163,9 @@ struct VerificPass : public Pass { #endif #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT log(" verific {-f|-F} [-vlog95|-vlog2k|-sv2005|-sv2009|\n"); +#ifdef VERIFIC_VHDL_SUPPORT + log(" -vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl2019|-vhdl|\n"); +#endif log(" -sv2012|-sv2017|-sv|-formal] \n"); log("\n"); log("Load and execute the specified command file.\n"); @@ -3698,6 +3701,7 @@ struct VerificPass : public Pass { if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F")) { unsigned verilog_mode = veri_file::UNDEFINED; + unsigned vhdl_mode = vhdl_file::UNDEFINED; bool is_formal = false; const char* filename = nullptr; @@ -3716,10 +3720,38 @@ struct VerificPass : public Pass { } else if (args[argidx] == "-sv2009") { verilog_mode = veri_file::SYSTEM_VERILOG_2009; continue; - } else if (args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal") { + } else if (args[argidx] == "-sv2012") { + verilog_mode = veri_file::SYSTEM_VERILOG_2012; + continue; + } else if (args[argidx] == "-sv2017") { + verilog_mode = veri_file::SYSTEM_VERILOG_2017; + continue; + } else if (args[argidx] == "-sv" || args[argidx] == "-formal") { verilog_mode = veri_file::SYSTEM_VERILOG; if (args[argidx] == "-formal") is_formal = true; continue; +#ifdef VERIFIC_VHDL_SUPPORT + } else if (args[argidx] == "-vhdl87") { + vhdl_mode = vhdl_file::VHDL_87; + vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str()); + continue; + } else if (args[argidx] == "-vhdl93") { + vhdl_mode = vhdl_file::VHDL_93; + vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str()); + continue; + } else if (args[argidx] == "-vhdl2k") { + vhdl_mode = vhdl_file::VHDL_2K; + vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str()); + continue; + } else if (args[argidx] == "-vhdl2019") { + vhdl_mode = vhdl_file::VHDL_2019; + vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2019").c_str()); + continue; + } else if (args[argidx] == "-vhdl2008" || args[argidx] == "-vhdl") { + vhdl_mode = vhdl_file::VHDL_2008; + vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str()); + continue; +#endif } else if (args[argidx].compare(0, 1, "-") == 0) { cmd_error(args, argidx, "unknown option"); goto check_error; @@ -3745,14 +3777,17 @@ struct VerificPass : public Pass { veri_file::DefineMacro(is_formal ? "FORMAL" : "SYNTHESIS"); #ifdef VERIFIC_VHDL_SUPPORT + if (vhdl_mode == vhdl_file::UNDEFINED) { + vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str()); + vhdl_mode = vhdl_file::VHDL_2008; + } int i; Array *file_names_sv = new Array(POINTER_HASH); FOREACH_ARRAY_ITEM(file_names, i, filename) { std::string filename_str = filename; if ((filename_str.substr(filename_str.find_last_of(".") + 1) == "vhd") || (filename_str.substr(filename_str.find_last_of(".") + 1) == "vhdl")) { - vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2019").c_str()); - if (!vhdl_file::Analyze(filename, work.c_str(), vhdl_file::VHDL_2019)) { + if (!vhdl_file::Analyze(filename, work.c_str(), vhdl_mode)) { verific_error_msg.clear(); log_cmd_error("Reading VHDL sources failed.\n"); } From 7439d2489e4e5bfedd987d0a7a306955cf451bf7 Mon Sep 17 00:00:00 2001 From: Natalia Date: Thu, 29 Jan 2026 02:20:50 -0800 Subject: [PATCH 124/291] add assertion to run_pass test --- tests/pyosys/test_design_run_pass.py | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/tests/pyosys/test_design_run_pass.py b/tests/pyosys/test_design_run_pass.py index c9656fd7a..59316f269 100644 --- a/tests/pyosys/test_design_run_pass.py +++ b/tests/pyosys/test_design_run_pass.py @@ -3,10 +3,11 @@ from pathlib import Path from pyosys import libyosys as ys __file_dir__ = Path(__file__).absolute().parent +src = __file_dir__.parent / "simple" / "fiedler-cooley.v" design = ys.Design() -design.run_pass( - ["read_verilog", str(__file_dir__.parent / "simple" / "fiedler-cooley.v")] -) -design.run_pass("prep") -design.run_pass(["opt", "-full"]) +design.run_pass(["read_verilog", str(src)]) +design.run_pass("hierarchy -top up3down5") +design.run_pass(["proc"]) +design.run_pass("opt -full") +design.run_pass("select -assert-mod-count 1 up3down5") From 61b1c3c75a56343dc494bfc514321615dad351d5 Mon Sep 17 00:00:00 2001 From: Natalia Date: Thu, 29 Jan 2026 02:42:23 -0800 Subject: [PATCH 125/291] use run_pass in ecp5 add/sub test --- tests/pyosys/test_design_run_pass.py | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/tests/pyosys/test_design_run_pass.py b/tests/pyosys/test_design_run_pass.py index 59316f269..f0013577d 100644 --- a/tests/pyosys/test_design_run_pass.py +++ b/tests/pyosys/test_design_run_pass.py @@ -1,13 +1,20 @@ -from pathlib import Path - +from pathlib import Path from pyosys import libyosys as ys __file_dir__ = Path(__file__).absolute().parent -src = __file_dir__.parent / "simple" / "fiedler-cooley.v" +add_sub = __file_dir__.parent / "arch" / "common" / "add_sub.v" -design = ys.Design() -design.run_pass(["read_verilog", str(src)]) -design.run_pass("hierarchy -top up3down5") -design.run_pass(["proc"]) -design.run_pass("opt -full") -design.run_pass("select -assert-mod-count 1 up3down5") +base = ys.Design() +base.run_pass(["read_verilog", str(add_sub)]) +base.run_pass("hierarchy -top top") +base.run_pass(["proc"]) +base.run_pass("equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5") + +postopt = ys.Design() +postopt.run_pass("design -load postopt") +postopt.run_pass(["cd", "top"]) +postopt.run_pass("select -assert-min 25 t:LUT4") +postopt.run_pass("select -assert-max 26 t:LUT4") +postopt.run_pass(["select", "-assert-count", "10", "t:PFUMX"]) +postopt.run_pass(["select", "-assert-count", "6", "t:L6MUX21"]) +postopt.run_pass("select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D") From 106f289e318caa45f53c5b6185e29df54f8d8685 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Fri, 30 Jan 2026 00:30:58 +0000 Subject: [PATCH 126/291] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 54826ee03..e4ebf9887 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.61+97 +YOSYS_VER := 0.61+112 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 6af1b5b19c279c09319f3fa8c094df89c06e9f7e Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 29 Jan 2026 18:47:12 +0000 Subject: [PATCH 127/291] Don't treat ABC 'Error:' output as indicating a fatal error, since these messages aren't necessarily fatal --- passes/techmap/abc.cc | 58 +++++++++++++++++++++++++++++++++---------- 1 file changed, 45 insertions(+), 13 deletions(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index e73be611a..ae0f3e053 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1127,9 +1127,34 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module handle_loops(assign_map, module); } +static bool is_abc_prompt(const std::string &line, std::string &rest) { + size_t pos = 0; + while (true) { + // The prompt may not start at the start of the line, because + // ABC can output progress and maybe other data that isn't + // newline-terminated. + size_t start = line.find("abc ", pos); + if (start == std::string::npos) + return false; + pos = start + 4; + + size_t digits = 0; + while (pos + digits < line.size() && line[pos + digits] >= '0' && line[pos + digits] <= '9') + ++digits; + if (digits < 2) + return false; + if (line.substr(pos + digits, 2) == "> ") { + rest = line.substr(pos + digits + 2); + return true; + } + } +} + bool read_until_abc_done(abc_output_filter &filt, int fd, DeferredLogs &logs) { std::string line; char buf[1024]; + bool seen_source_cmd = false; + bool seen_yosys_abc_done = false; while (true) { int ret = read(fd, buf, sizeof(buf) - 1); if (ret < 0) { @@ -1144,23 +1169,30 @@ bool read_until_abc_done(abc_output_filter &filt, int fd, DeferredLogs &logs) { char *end = buf + ret; while (start < end) { char *p = static_cast(memchr(start, '\n', end - start)); - if (p == nullptr) { - break; + char *upto = p == nullptr ? end : p + 1; + line.append(start, upto - start); + start = upto; + + std::string rest; + bool is_prompt = is_abc_prompt(line, rest); + if (is_prompt && seen_source_cmd) { + // This is the first prompt after we sourced the script. + // We are done here. + // We won't have seen a newline yet since ABC is waiting at the prompt. + if (!seen_yosys_abc_done) + logs.log_error("ABC script did not complete successfully\n"); + return seen_yosys_abc_done; } - line.append(start, p + 1 - start); - if (line.substr(0, 14) == "YOSYS_ABC_DONE") { - // Ignore any leftover output, there should only be a prompt perhaps - return true; - } - // If ABC aborted the sourced script, it returns to the prompt and will - // never print YOSYS_ABC_DONE. Treat this as a failed run, not a hang. - if (line.substr(0, 7) == "Error: ") { - logs.log_error("ABC: %s", line.c_str()); - return false; + if (line.empty() || line[line.size() - 1] != '\n') { + // No newline yet, wait for more text + continue; } filt.next_line(line); + if (is_prompt && rest.substr(0, 7) == "source ") + seen_source_cmd = true; + if (line.substr(0, 14) == "YOSYS_ABC_DONE") + seen_yosys_abc_done = true; line.clear(); - start = p + 1; } line.append(start, end - start); } From 9c56c93632f0aca1a7ded76582ce41dea08d906a Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 29 Jan 2026 18:47:42 +0000 Subject: [PATCH 128/291] Add missing newlines to some 'log_error's --- passes/techmap/abc.cc | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index ae0f3e053..e9d02b85c 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -188,10 +188,10 @@ struct AbcProcess int status; int ret = waitpid(pid, &status, 0); if (ret != pid) { - log_error("waitpid(%d) failed", pid); + log_error("waitpid(%d) failed\n", pid); } if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) { - log_error("ABC failed with status %X", status); + log_error("ABC failed with status %X\n", status); } if (from_child_pipe >= 0) close(from_child_pipe); @@ -203,12 +203,12 @@ std::optional spawn_abc(const char* abc_exe, DeferredLogs &logs) { // fork()s. int to_child_pipe[2]; if (pipe2(to_child_pipe, O_CLOEXEC) != 0) { - logs.log_error("pipe failed"); + logs.log_error("pipe failed\n"); return std::nullopt; } int from_child_pipe[2]; if (pipe2(from_child_pipe, O_CLOEXEC) != 0) { - logs.log_error("pipe failed"); + logs.log_error("pipe failed\n"); return std::nullopt; } @@ -221,39 +221,39 @@ std::optional spawn_abc(const char* abc_exe, DeferredLogs &logs) { posix_spawn_file_actions_t file_actions; if (posix_spawn_file_actions_init(&file_actions) != 0) { - logs.log_error("posix_spawn_file_actions_init failed"); + logs.log_error("posix_spawn_file_actions_init failed\n"); return std::nullopt; } if (posix_spawn_file_actions_addclose(&file_actions, to_child_pipe[1]) != 0) { - logs.log_error("posix_spawn_file_actions_addclose failed"); + logs.log_error("posix_spawn_file_actions_addclose failed\n"); return std::nullopt; } if (posix_spawn_file_actions_addclose(&file_actions, from_child_pipe[0]) != 0) { - logs.log_error("posix_spawn_file_actions_addclose failed"); + logs.log_error("posix_spawn_file_actions_addclose failed\n"); return std::nullopt; } if (posix_spawn_file_actions_adddup2(&file_actions, to_child_pipe[0], STDIN_FILENO) != 0) { - logs.log_error("posix_spawn_file_actions_adddup2 failed"); + logs.log_error("posix_spawn_file_actions_adddup2 failed\n"); return std::nullopt; } if (posix_spawn_file_actions_adddup2(&file_actions, from_child_pipe[1], STDOUT_FILENO) != 0) { - logs.log_error("posix_spawn_file_actions_adddup2 failed"); + logs.log_error("posix_spawn_file_actions_adddup2 failed\n"); return std::nullopt; } if (posix_spawn_file_actions_addclose(&file_actions, to_child_pipe[0]) != 0) { - logs.log_error("posix_spawn_file_actions_addclose failed"); + logs.log_error("posix_spawn_file_actions_addclose failed\n"); return std::nullopt; } if (posix_spawn_file_actions_addclose(&file_actions, from_child_pipe[1]) != 0) { - logs.log_error("posix_spawn_file_actions_addclose failed"); + logs.log_error("posix_spawn_file_actions_addclose failed\n"); return std::nullopt; } char arg1[] = "-s"; char* argv[] = { strdup(abc_exe), arg1, nullptr }; if (0 != posix_spawnp(&result.pid, abc_exe, &file_actions, nullptr, argv, environ)) { - logs.log_error("posix_spawnp %s failed (errno=%s)", abc_exe, strerror(errno)); + logs.log_error("posix_spawnp %s failed (errno=%s)\n", abc_exe, strerror(errno)); return std::nullopt; } free(argv[0]); @@ -1158,11 +1158,11 @@ bool read_until_abc_done(abc_output_filter &filt, int fd, DeferredLogs &logs) { while (true) { int ret = read(fd, buf, sizeof(buf) - 1); if (ret < 0) { - logs.log_error("Failed to read from ABC, errno=%d", errno); + logs.log_error("Failed to read from ABC, errno=%d\n", errno); return false; } if (ret == 0) { - logs.log_error("ABC exited prematurely"); + logs.log_error("ABC exited prematurely\n"); return false; } char *start = buf; From b88d6588bc23fff3dd30a112b2646be288505c68 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 2 Feb 2026 11:25:57 +0100 Subject: [PATCH 129/291] Update ABC as per 2026-02-02 --- abc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/abc b/abc index 79010216c..734f64d5b 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit 79010216cb87427dd7a0c8d38f156494221be006 +Subproject commit 734f64d5b907158dc4337ee82b3b74566d74ba08 From 224549fb88fd4d2301d643aa1fb60958d631b93c Mon Sep 17 00:00:00 2001 From: Sean Luchen Date: Mon, 2 Feb 2026 15:26:03 -0800 Subject: [PATCH 130/291] Guard vhdl_file::UNDEFINED behind VERIFIC_VHDL_SUPPORT. Signed-off-by: Sean Luchen --- frontends/verific/verific.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 9f13eee23..6a1c81aa4 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3701,7 +3701,9 @@ struct VerificPass : public Pass { if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F")) { unsigned verilog_mode = veri_file::UNDEFINED; +#ifdef VERIFIC_VHDL_SUPPORT unsigned vhdl_mode = vhdl_file::UNDEFINED; +#endif bool is_formal = false; const char* filename = nullptr; From 153ddc0c84ce8de4896a7b11918199b8fc1022ac Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 3 Feb 2026 00:33:37 +0000 Subject: [PATCH 131/291] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index e4ebf9887..92a854819 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.61+112 +YOSYS_VER := 0.61+129 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 3bfeaee8ca216f17c11a6ab13ddaa877e2eb7ad0 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 2 Feb 2026 19:09:30 +0100 Subject: [PATCH 132/291] opt_expr: fix const lhs of $pow to $shl --- passes/opt/opt_expr.cc | 7 ++++-- tests/opt/opt_expr.ys | 56 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+), 2 deletions(-) diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index ffe678d2f..7131053c9 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -1667,7 +1667,11 @@ skip_identity: int bit_idx; const auto onehot = sig_a.is_onehot(&bit_idx); - if (onehot) { + // Power of two + // A is unsigned or positive + if (onehot && (!cell->parameters[ID::A_SIGNED].as_bool() || bit_idx < sig_a.size() - 1)) { + cell->parameters[ID::A_SIGNED] = 0; + // 2^B = 1<name.c_str(), module->name.c_str()); @@ -1679,7 +1683,6 @@ skip_identity: log_debug("Replacing pow cell `%s' in module `%s' with multiply and left-shift\n", cell->name.c_str(), module->name.c_str()); cell->type = ID($mul); - cell->parameters[ID::A_SIGNED] = 0; cell->setPort(ID::A, Const(bit_idx, cell->parameters[ID::A_WIDTH].as_int())); SigSpec y_wire = module->addWire(NEW_ID, y_size); diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index 7c446afd1..61b54a92f 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -319,3 +319,59 @@ check equiv_opt -assert opt_expr -keepdc design -load postopt select -assert-count 1 t:$mul r:A_WIDTH=4 %i r:B_WIDTH=4 %i r:Y_WIDTH=8 %i + +########### + +design -reset +read_rtlil < Date: Tue, 3 Feb 2026 12:09:24 +0100 Subject: [PATCH 133/291] Release version 0.62 --- CHANGELOG | 20 +++++++++++++++++++- Makefile | 4 ++-- docs/source/conf.py | 2 +- 3 files changed, 22 insertions(+), 4 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 73c1606da..6e2bca32c 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,8 +2,26 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.61 .. Yosys 0.62-dev +Yosys 0.61 .. Yosys 0.62 -------------------------- + * Various + - verific: Added "-sv2017" flag option to support System + Verilog 2017. + - verific: Added VHDL related flags to "-f" and "-F" and + support reading VHDL file from file lists. + - Updated cell libs with proper module declaration where + non standard (...) style was used. + + * New commands and options + - Added "-word" option to "lut2mux" pass to enable emitting + word level cells. + - Added experimental "opt_balance_tree" pass to convert + cascaded cells into tree of cells to improve timing. + - Added "-gatesi" option to "write_blif" pass to init gates + under gates_mode in BLIF format. + - Added "-on" and "-off" options to "debug" pass for + persistent debug logging. + - Added "linux_perf" pass to control performance recording. Yosys 0.60 .. Yosys 0.61 -------------------------- diff --git a/Makefile b/Makefile index 92a854819..28608f573 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.61+129 +YOSYS_VER := 0.62 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) @@ -186,7 +186,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: - sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 5ae48ee.. | wc -l`/;" Makefile +# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 5ae48ee.. | wc -l`/;" Makefile ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q) diff --git a/docs/source/conf.py b/docs/source/conf.py index 34f8be029..a7da22d97 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -6,7 +6,7 @@ import os project = 'YosysHQ Yosys' author = 'YosysHQ GmbH' copyright ='2026 YosysHQ GmbH' -yosys_ver = "0.61" +yosys_ver = "0.62" # select HTML theme html_theme = 'furo-ys' From 44afd4bbdd2094144fa178f3bbfb4f92c135850c Mon Sep 17 00:00:00 2001 From: Jeppe Johansen Date: Wed, 24 Aug 2022 18:31:45 +0200 Subject: [PATCH 134/291] Add support for subtraction in preadder --- techlibs/xilinx/xilinx_dsp.cc | 20 +++++++++++++------- techlibs/xilinx/xilinx_dsp.pmg | 32 +++++++++++++++++++++++++++++++- 2 files changed, 44 insertions(+), 8 deletions(-) diff --git a/techlibs/xilinx/xilinx_dsp.cc b/techlibs/xilinx/xilinx_dsp.cc index 22e6bce5b..194b9ac10 100644 --- a/techlibs/xilinx/xilinx_dsp.cc +++ b/techlibs/xilinx/xilinx_dsp.cc @@ -263,6 +263,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) log("Analysing %s.%s for Xilinx DSP packing.\n", log_id(pm.module), log_id(st.dsp)); log_debug("preAdd: %s\n", log_id(st.preAdd, "--")); + log_debug("preSub: %s\n", log_id(st.preSub, "--")); log_debug("ffAD: %s\n", log_id(st.ffAD, "--")); log_debug("ffA2: %s\n", log_id(st.ffA2, "--")); log_debug("ffA1: %s\n", log_id(st.ffA1, "--")); @@ -278,17 +279,22 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) Cell *cell = st.dsp; - if (st.preAdd) { - log(" preadder %s (%s)\n", log_id(st.preAdd), log_id(st.preAdd->type)); - bool A_SIGNED = st.preAdd->getParam(ID::A_SIGNED).as_bool(); - bool D_SIGNED = st.preAdd->getParam(ID::B_SIGNED).as_bool(); - if (st.sigA == st.preAdd->getPort(ID::B)) + if (st.preAdd || st.preSub) { + Cell* preAdder = st.preAdd ? st.preAdd : st.preSub; + + log(" preadder %s (%s)\n", log_id(preAdder), log_id(preAdder->type)); + bool A_SIGNED = preAdder->getParam(ID::A_SIGNED).as_bool(); + bool D_SIGNED = preAdder->getParam(ID::B_SIGNED).as_bool(); + if (st.sigA == preAdder->getPort(ID::B)) std::swap(A_SIGNED, D_SIGNED); st.sigA.extend_u0(30, A_SIGNED); st.sigD.extend_u0(25, D_SIGNED); cell->setPort(ID::A, st.sigA); cell->setPort(ID::D, st.sigD); - cell->setPort(ID(INMODE), Const::from_string("00100")); + if (preAdder->type == ID($add)) + cell->setPort(ID(INMODE), Const::from_string("00100")); + else + cell->setPort(ID(INMODE), Const::from_string("01100")); if (st.ffAD) { if (st.ffAD->type.in(ID($dffe), ID($sdffe))) { @@ -303,7 +309,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) cell->setParam(ID(USE_DPORT), Const("TRUE")); - pm.autoremove(st.preAdd); + pm.autoremove(preAdder); } if (st.postAdd) { log(" postadder %s (%s)\n", log_id(st.postAdd), log_id(st.postAdd->type)); diff --git a/techlibs/xilinx/xilinx_dsp.pmg b/techlibs/xilinx/xilinx_dsp.pmg index ef0157621..6ec891290 100644 --- a/techlibs/xilinx/xilinx_dsp.pmg +++ b/techlibs/xilinx/xilinx_dsp.pmg @@ -6,6 +6,8 @@ // If ADREG matched, treat 'A' input as input of ADREG // ( 3) Match the driver of the 'A' and 'D' inputs for a possible $add cell // (pre-adder) +// (3.1) Match the driver of the 'A' and 'D' inputs for a possible $sub cell +// (pre-adder) // ( 4) If pre-adder was present, find match 'A' input for A2REG // If pre-adder was not present, move ADREG to A2REG // If A2REG, then match 'A' input for A1REG @@ -152,13 +154,41 @@ code sigA sigD } endcode +// (3.1) Match the driver of the 'A' and 'D' inputs for a possible $sub cell +// (pre-adder) +match preSub + if sigD.empty() || sigD.is_fully_zero() + // Ensure that preAdder not already used + if param(dsp, \USE_DPORT).decode_string() == "FALSE" + if port(dsp, \INMODE, Const(0, 5)).is_fully_zero() + + select preSub->type.in($sub) + // Output has to be 25 bits or less + select GetSize(port(preSub, \Y)) <= 25 + select nusers(port(preSub, \Y)) == 2 + // D port has to be 25 bits or less + select GetSize(port(preSub, \A)) <= 25 + // A port has to be 30 bits or less + select GetSize(port(preSub, \B)) <= 30 + index port(preSub, \Y) === sigA + + optional +endmatch + +code sigA sigD + if (preSub) { + sigD = port(preSub, \A); + sigA = port(preSub, \B); + } +endcode + // (4) If pre-adder was present, find match 'A' input for A2REG // If pre-adder was not present, move ADREG to A2REG // Then match 'A' input for A1REG code argQ ffAD sigA clock ffA2 ffA1 // Only search for ffA2 if there was a pre-adder // (otherwise ffA2 would have been matched as ffAD) - if (preAdd) { + if (preAdd || preSub) { if (param(dsp, \AREG).as_int() == 0) { argQ = sigA; subpattern(in_dffe); From 000be270ca3272dd660dcd82b8a142b9fd593411 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 3 Feb 2026 17:54:46 +0100 Subject: [PATCH 135/291] equiv_simple, equiv_induct: refactor --- passes/equiv/equiv.h | 73 ++++++++++++++++++++++ passes/equiv/equiv_induct.cc | 66 +++++--------------- passes/equiv/equiv_simple.cc | 118 ++++++++++++++--------------------- 3 files changed, 136 insertions(+), 121 deletions(-) create mode 100644 passes/equiv/equiv.h diff --git a/passes/equiv/equiv.h b/passes/equiv/equiv.h new file mode 100644 index 000000000..b255042ba --- /dev/null +++ b/passes/equiv/equiv.h @@ -0,0 +1,73 @@ +#ifndef EQUIV_H +#define EQUIV_H + +#include "kernel/log.h" +#include "kernel/yosys_common.h" +#include "kernel/sigtools.h" +#include "kernel/satgen.h" + +YOSYS_NAMESPACE_BEGIN + +static void report_missing_model(bool warn_only, RTLIL::Cell* cell) +{ + std::string s; + if (cell->is_builtin_ff()) + s = stringf("No SAT model available for async FF cell %s (%s). Consider running `async2sync` or `clk2fflogic` first.\n", log_id(cell), log_id(cell->type)); + else + s = stringf("No SAT model available for cell %s (%s).\n", log_id(cell), log_id(cell->type)); + + if (warn_only) { + log_formatted_warning_noprefix(s); + } else { + log_formatted_error(s); + } +} + +struct EquivWorker { + RTLIL::Module *module; + + ezSatPtr ez; + SatGen satgen; + + struct Config { + bool model_undef = false; + int max_seq = 1; + bool set_assumes = false; + + bool parse(const std::vector& args, size_t& idx) { + if (args[idx] == "-undef") { + model_undef = true; + return true; + } + if (args[idx] == "-seq" && idx+1 < args.size()) { + max_seq = atoi(args[++idx].c_str()); + return true; + } + if (args[idx] == "-set-assumes") { + set_assumes = true; + return true; + } + return false; + } + static std::string help(const char* default_seq) { + return stringf( + " -undef\n" + " enable modelling of undef states\n" + "\n" + " -seq \n" + " the max. number of time steps to be considered (default = %s)\n" + "\n" + " -set-assumes\n" + " set all assumptions provided via $assume cells\n" + , default_seq); + } + }; + Config cfg; + + EquivWorker(RTLIL::Module *module, const SigMap *sigmap, Config cfg) : module(module), satgen(ez.get(), sigmap), cfg(cfg) { + satgen.model_undef = cfg.model_undef; + } +}; + +YOSYS_NAMESPACE_END +#endif // EQUIV_H diff --git a/passes/equiv/equiv_induct.cc b/passes/equiv/equiv_induct.cc index e1a3a7990..c91501719 100644 --- a/passes/equiv/equiv_induct.cc +++ b/passes/equiv/equiv_induct.cc @@ -18,49 +18,34 @@ */ #include "kernel/yosys.h" -#include "kernel/satgen.h" -#include "kernel/sigtools.h" +#include "passes/equiv/equiv.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -struct EquivInductWorker +struct EquivInductWorker : public EquivWorker { - Module *module; SigMap sigmap; vector cells; pool workset; - ezSatPtr ez; - SatGen satgen; - - int max_seq; int success_counter; - bool set_assumes; dict ez_step_is_consistent; - pool cell_warn_cache; SigPool undriven_signals; - EquivInductWorker(Module *module, const pool &unproven_equiv_cells, bool model_undef, int max_seq, bool set_assumes) : module(module), sigmap(module), + EquivInductWorker(Module *module, const pool &unproven_equiv_cells, Config cfg) : EquivWorker(module, &sigmap, cfg), sigmap(module), cells(module->selected_cells()), workset(unproven_equiv_cells), - satgen(ez.get(), &sigmap), max_seq(max_seq), success_counter(0), set_assumes(set_assumes) - { - satgen.model_undef = model_undef; - } + success_counter(0) {} void create_timestep(int step) { vector ez_equal_terms; for (auto cell : cells) { - if (!satgen.importCell(cell, step) && !cell_warn_cache.count(cell)) { - if (cell->is_builtin_ff()) - log_warning("No SAT model available for async FF cell %s (%s). Consider running `async2sync` or `clk2fflogic` first.\n", log_id(cell), log_id(cell->type)); - else - log_warning("No SAT model available for cell %s (%s).\n", log_id(cell), log_id(cell->type)); - cell_warn_cache.insert(cell); + if (!satgen.importCell(cell, step)) { + report_missing_model(true, cell); } if (cell->type == ID($equiv)) { SigBit bit_a = sigmap(cell->getPort(ID::A)).as_bit(); @@ -78,7 +63,7 @@ struct EquivInductWorker } } - if (set_assumes) { + if (cfg.set_assumes) { if (step == 1) { RTLIL::SigSpec assumes_a, assumes_en; satgen.getAssumes(assumes_a, assumes_en, step); @@ -123,7 +108,7 @@ struct EquivInductWorker GetSize(satgen.initial_state), GetSize(undriven_signals)); } - for (int step = 1; step <= max_seq; step++) + for (int step = 1; step <= cfg.max_seq; step++) { ez->assume(ez_step_is_consistent[step]); @@ -146,7 +131,7 @@ struct EquivInductWorker return; } - log(" Proof for induction step failed. %s\n", step != max_seq ? "Extending to next time step." : "Trying to prove individual $equiv from workset."); + log(" Proof for induction step failed. %s\n", step != cfg.max_seq ? "Extending to next time step." : "Trying to prove individual $equiv from workset."); } workset.sort(); @@ -158,12 +143,12 @@ struct EquivInductWorker log(" Trying to prove $equiv for %s:", log_signal(sigmap(cell->getPort(ID::Y)))); - int ez_a = satgen.importSigBit(bit_a, max_seq+1); - int ez_b = satgen.importSigBit(bit_b, max_seq+1); + int ez_a = satgen.importSigBit(bit_a, cfg.max_seq+1); + int ez_b = satgen.importSigBit(bit_b, cfg.max_seq+1); int cond = ez->XOR(ez_a, ez_b); if (satgen.model_undef) - cond = ez->AND(cond, ez->NOT(satgen.importUndefSigBit(bit_a, max_seq+1))); + cond = ez->AND(cond, ez->NOT(satgen.importUndefSigBit(bit_a, cfg.max_seq+1))); if (!ez->solve(cond)) { log(" success!\n"); @@ -189,14 +174,7 @@ struct EquivInductPass : public Pass { log("Only selected $equiv cells are proven and only selected cells are used to\n"); log("perform the proof.\n"); log("\n"); - log(" -undef\n"); - log(" enable modelling of undef states\n"); - log("\n"); - log(" -seq \n"); - log(" the max. number of time steps to be considered (default = 4)\n"); - log("\n"); - log(" -set-assumes\n"); - log(" set all assumptions provided via $assume cells\n"); + EquivWorker::Config::help("4"); log("\n"); log("This command is very effective in proving complex sequential circuits, when\n"); log("the internal state of the circuit quickly propagates to $equiv cells.\n"); @@ -214,25 +192,15 @@ struct EquivInductPass : public Pass { void execute(std::vector args, Design *design) override { int success_counter = 0; - bool model_undef = false, set_assumes = false; - int max_seq = 4; + EquivWorker::Config cfg; + cfg.max_seq = 4; log_header(design, "Executing EQUIV_INDUCT pass.\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-undef") { - model_undef = true; + if (cfg.parse(args, argidx)) continue; - } - if (args[argidx] == "-seq" && argidx+1 < args.size()) { - max_seq = atoi(args[++argidx].c_str()); - continue; - } - if (args[argidx] == "-set-assumes") { - set_assumes = true; - continue; - } break; } extra_args(args, argidx, design); @@ -253,7 +221,7 @@ struct EquivInductPass : public Pass { continue; } - EquivInductWorker worker(module, unproven_equiv_cells, model_undef, max_seq, set_assumes); + EquivInductWorker worker(module, unproven_equiv_cells, cfg); worker.run(); success_counter += worker.success_counter; } diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc index 97f95ac63..0749d18aa 100644 --- a/passes/equiv/equiv_simple.cc +++ b/passes/equiv/equiv_simple.cc @@ -17,15 +17,52 @@ * */ +#include "kernel/log.h" #include "kernel/yosys.h" -#include "kernel/satgen.h" +#include "passes/equiv/equiv.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -struct EquivSimpleWorker +struct EquivSimpleWorker : public EquivWorker { - Module *module; + struct Config : EquivWorker::Config { + bool verbose = false; + bool short_cones = false; + bool group = true; + bool parse(const std::vector& args, size_t& idx) { + if (EquivWorker::Config::parse(args, idx)) + return true; + if (args[idx] == "-v") { + verbose = true; + return true; + } + if (args[idx] == "-short") { + short_cones = true; + return true; + } + if (args[idx] == "-nogroup") { + group = false; + return true; + } + return false; + } + static std::string help(const char* default_seq) { + return EquivWorker::Config::help(default_seq) + + " -v\n" + " verbose output\n" + "\n" + " -short\n" + " create shorter input cones that stop at shared nodes. This yields\n" + " simpler SAT problems but sometimes fails to prove equivalence.\n" + "\n" + " -nogroup\n" + " disabling grouping of $equiv cells by output wire\n" + "\n"; + } + }; + Config cfg; + const vector &equiv_cells; const vector &assume_cells; struct Cone { @@ -43,27 +80,11 @@ struct EquivSimpleWorker }; DesignModel model; - ezSatPtr ez; - SatGen satgen; - - struct Config { - bool verbose = false; - bool short_cones = false; - bool model_undef = false; - bool nogroup = false; - bool set_assumes = false; - int max_seq = 1; - }; - Config cfg; - pool> imported_cells_cache; EquivSimpleWorker(const vector &equiv_cells, const vector &assume_cells, DesignModel model, Config cfg) : - module(equiv_cells.front()->module), equiv_cells(equiv_cells), assume_cells(assume_cells), - model(model), satgen(ez.get(), &model.sigmap), cfg(cfg) - { - satgen.model_undef = cfg.model_undef; - } + EquivWorker(equiv_cells.front()->module, &model.sigmap, cfg), equiv_cells(equiv_cells), assume_cells(assume_cells), + model(model) {} struct ConeFinder { DesignModel model; @@ -229,14 +250,6 @@ struct EquivSimpleWorker return extra_problem_cells; } - static void report_missing_model(Cell* cell) - { - if (cell->is_builtin_ff()) - log_cmd_error("No SAT model available for async FF cell %s (%s). Consider running `async2sync` or `clk2fflogic` first.\n", log_id(cell), log_id(cell->type)); - else - log_cmd_error("No SAT model available for cell %s (%s).\n", log_id(cell), log_id(cell->type)); - } - void prepare_ezsat(int ez_context, SigBit bit_a, SigBit bit_b) { if (satgen.model_undef) @@ -323,7 +336,7 @@ struct EquivSimpleWorker for (auto cell : problem_cells) { auto key = pair(cell, step+1); if (!imported_cells_cache.count(key) && !satgen.importCell(cell, step+1)) { - report_missing_model(cell); + report_missing_model(true, cell); } imported_cells_cache.insert(key); } @@ -414,24 +427,7 @@ struct EquivSimplePass : public Pass { log("\n"); log("This command tries to prove $equiv cells using a simple direct SAT approach.\n"); log("\n"); - log(" -v\n"); - log(" verbose output\n"); - log("\n"); - log(" -undef\n"); - log(" enable modelling of undef states\n"); - log("\n"); - log(" -short\n"); - log(" create shorter input cones that stop at shared nodes. This yields\n"); - log(" simpler SAT problems but sometimes fails to prove equivalence.\n"); - log("\n"); - log(" -nogroup\n"); - log(" disabling grouping of $equiv cells by output wire\n"); - log("\n"); - log(" -seq \n"); - log(" the max. number of time steps to be considered (default = 1)\n"); - log("\n"); - log(" -set-assumes\n"); - log(" set all assumptions provided via $assume cells\n"); + EquivSimpleWorker::Config::help("1"); log("\n"); } void execute(std::vector args, Design *design) override @@ -443,30 +439,8 @@ struct EquivSimplePass : public Pass { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-v") { - cfg.verbose = true; + if (cfg.parse(args, argidx)) continue; - } - if (args[argidx] == "-short") { - cfg.short_cones = true; - continue; - } - if (args[argidx] == "-undef") { - cfg.model_undef = true; - continue; - } - if (args[argidx] == "-nogroup") { - cfg.nogroup = true; - continue; - } - if (args[argidx] == "-seq" && argidx+1 < args.size()) { - cfg.max_seq = atoi(args[++argidx].c_str()); - continue; - } - if (args[argidx] == "-set-assumes") { - cfg.set_assumes = true; - continue; - } break; } extra_args(args, argidx, design); @@ -489,7 +463,7 @@ struct EquivSimplePass : public Pass { if (cell->type == ID($equiv) && cell->getPort(ID::A) != cell->getPort(ID::B)) { auto bit = sigmap(cell->getPort(ID::Y).as_bit()); auto bit_group = bit; - if (!cfg.nogroup && bit_group.wire) + if (cfg.group && bit_group.wire) bit_group.offset = 0; unproven_equiv_cells[bit_group][bit] = cell; unproven_cells_counter++; From 8e73e2a306809369c2f71d6037f1671e36e69d4e Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 3 Feb 2026 17:56:10 +0100 Subject: [PATCH 136/291] sat: add -ignore-unknown-cells instead of -ignore_unknown_cells for consistency --- passes/sat/sat.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 90b85d709..ffebdd01c 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -961,10 +961,10 @@ struct SatPass : public Pass { log(" -show-regs, -show-public, -show-all\n"); log(" show all registers, show signals with 'public' names, show all signals\n"); log("\n"); - log(" -ignore_div_by_zero\n"); + log(" -ignore-div-by-zero\n"); log(" ignore all solutions that involve a division by zero\n"); log("\n"); - log(" -ignore_unknown_cells\n"); + log(" -ignore-unknown-cells\n"); log(" ignore all cells that can not be matched to a SAT model\n"); log("\n"); log("The following options can be used to set up a sequential problem:\n"); @@ -1141,7 +1141,7 @@ struct SatPass : public Pass { stepsize = max(1, atoi(args[++argidx].c_str())); continue; } - if (args[argidx] == "-ignore_div_by_zero") { + if (args[argidx] == "-ignore-div-by-zero" || args[argidx] == "-ignore_div_by_zero") { ignore_div_by_zero = true; continue; } @@ -1316,7 +1316,7 @@ struct SatPass : public Pass { show_all = true; continue; } - if (args[argidx] == "-ignore_unknown_cells") { + if (args[argidx] == "-ignore-unknown-cells" || args[argidx] == "-ignore_unknown_cells") { ignore_unknown_cells = true; continue; } From 8d1c1faf82ec085c9756a31010ed9d50d06334d3 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 3 Feb 2026 17:59:31 +0100 Subject: [PATCH 137/291] equiv_simple, equiv_induct: error by default on missing model, add -ignore-unknown-cells --- passes/equiv/equiv.h | 8 ++++++++ passes/equiv/equiv_induct.cc | 2 +- passes/equiv/equiv_simple.cc | 2 +- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/passes/equiv/equiv.h b/passes/equiv/equiv.h index b255042ba..8a24b2fcd 100644 --- a/passes/equiv/equiv.h +++ b/passes/equiv/equiv.h @@ -33,6 +33,7 @@ struct EquivWorker { bool model_undef = false; int max_seq = 1; bool set_assumes = false; + bool ignore_unknown_cells = false; bool parse(const std::vector& args, size_t& idx) { if (args[idx] == "-undef") { @@ -47,6 +48,10 @@ struct EquivWorker { set_assumes = true; return true; } + if (args[idx] == "-ignore-unknown-cells") { + ignore_unknown_cells = true; + return true; + } return false; } static std::string help(const char* default_seq) { @@ -59,6 +64,9 @@ struct EquivWorker { "\n" " -set-assumes\n" " set all assumptions provided via $assume cells\n" + "\n" + " -ignore-unknown-cells\n" + " ignore all cells that can not be matched to a SAT model\n" , default_seq); } }; diff --git a/passes/equiv/equiv_induct.cc b/passes/equiv/equiv_induct.cc index c91501719..f7ceb78a3 100644 --- a/passes/equiv/equiv_induct.cc +++ b/passes/equiv/equiv_induct.cc @@ -45,7 +45,7 @@ struct EquivInductWorker : public EquivWorker for (auto cell : cells) { if (!satgen.importCell(cell, step)) { - report_missing_model(true, cell); + report_missing_model(cfg.ignore_unknown_cells, cell); } if (cell->type == ID($equiv)) { SigBit bit_a = sigmap(cell->getPort(ID::A)).as_bit(); diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc index 0749d18aa..f345e9794 100644 --- a/passes/equiv/equiv_simple.cc +++ b/passes/equiv/equiv_simple.cc @@ -336,7 +336,7 @@ struct EquivSimpleWorker : public EquivWorker for (auto cell : problem_cells) { auto key = pair(cell, step+1); if (!imported_cells_cache.count(key) && !satgen.importCell(cell, step+1)) { - report_missing_model(true, cell); + report_missing_model(cfg.ignore_unknown_cells, cell); } imported_cells_cache.insert(key); } From d199195785fb058eb1c92502787e79be3ea56943 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 3 Feb 2026 18:00:45 +0100 Subject: [PATCH 138/291] satgen: cover $input_port --- kernel/satgen.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/satgen.cc b/kernel/satgen.cc index f2c1e00c2..b8b850bb3 100644 --- a/kernel/satgen.cc +++ b/kernel/satgen.cc @@ -1378,7 +1378,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) return true; } - if (cell->type == ID($scopeinfo)) + if (cell->type == ID($scopeinfo) || cell->type == ID($input_port)) { return true; } From 2efd0247a10192fb1240c0c7a6778b2979b3377d Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 3 Feb 2026 18:09:51 +0100 Subject: [PATCH 139/291] opt_hier: fix test --- tests/opt/opt_hier.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/opt/opt_hier.tcl b/tests/opt/opt_hier.tcl index 65d8f9809..d006759f5 100644 --- a/tests/opt/opt_hier.tcl +++ b/tests/opt/opt_hier.tcl @@ -27,7 +27,7 @@ foreach fn [glob opt_hier_*.v] { design -copy-from gate -as gate A:top yosys rename -hide equiv_make gold gate equiv - equiv_induct equiv + equiv_induct -ignore-unknown-cells equiv equiv_status -assert equiv log -pop From c768e55983f2077da5d0a7d1798f73a35055af8b Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 3 Feb 2026 18:10:02 +0100 Subject: [PATCH 140/291] ice40: fix dsp_const test --- tests/arch/ice40/ice40_dsp_const.ys | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/arch/ice40/ice40_dsp_const.ys b/tests/arch/ice40/ice40_dsp_const.ys index c9c76a1ac..735f945a1 100644 --- a/tests/arch/ice40/ice40_dsp_const.ys +++ b/tests/arch/ice40/ice40_dsp_const.ys @@ -74,6 +74,7 @@ EOT techmap -wb -D EQUIV -autoproc -map +/ice40/cells_sim.v +async2sync equiv_make top ref equiv select -assert-any -module equiv t:$equiv equiv_induct From ed53ff2f4988c6fc49cefafa85b6a82ef2ca1871 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 3 Feb 2026 18:37:39 +0100 Subject: [PATCH 141/291] equiv_simple, equiv_induct: fix config --- passes/equiv/equiv.h | 89 ++++++++++++++++++------------------ passes/equiv/equiv_induct.cc | 8 ++-- passes/equiv/equiv_simple.cc | 81 ++++++++++++++++---------------- 3 files changed, 90 insertions(+), 88 deletions(-) diff --git a/passes/equiv/equiv.h b/passes/equiv/equiv.h index 8a24b2fcd..9641e65a7 100644 --- a/passes/equiv/equiv.h +++ b/passes/equiv/equiv.h @@ -23,54 +23,55 @@ static void report_missing_model(bool warn_only, RTLIL::Cell* cell) } } +struct EquivBasicConfig { + bool model_undef = false; + int max_seq = 1; + bool set_assumes = false; + bool ignore_unknown_cells = false; + + bool parse(const std::vector& args, size_t& idx) { + if (args[idx] == "-undef") { + model_undef = true; + return true; + } + if (args[idx] == "-seq" && idx+1 < args.size()) { + max_seq = atoi(args[++idx].c_str()); + return true; + } + if (args[idx] == "-set-assumes") { + set_assumes = true; + return true; + } + if (args[idx] == "-ignore-unknown-cells") { + ignore_unknown_cells = true; + return true; + } + return false; + } + static std::string help(const char* default_seq) { + return stringf( + " -undef\n" + " enable modelling of undef states\n" + "\n" + " -seq \n" + " the max. number of time steps to be considered (default = %s)\n" + "\n" + " -set-assumes\n" + " set all assumptions provided via $assume cells\n" + "\n" + " -ignore-unknown-cells\n" + " ignore all cells that can not be matched to a SAT model\n" + , default_seq); + } +}; + +template struct EquivWorker { RTLIL::Module *module; - ezSatPtr ez; + ezSatPtr ez; SatGen satgen; - - struct Config { - bool model_undef = false; - int max_seq = 1; - bool set_assumes = false; - bool ignore_unknown_cells = false; - - bool parse(const std::vector& args, size_t& idx) { - if (args[idx] == "-undef") { - model_undef = true; - return true; - } - if (args[idx] == "-seq" && idx+1 < args.size()) { - max_seq = atoi(args[++idx].c_str()); - return true; - } - if (args[idx] == "-set-assumes") { - set_assumes = true; - return true; - } - if (args[idx] == "-ignore-unknown-cells") { - ignore_unknown_cells = true; - return true; - } - return false; - } - static std::string help(const char* default_seq) { - return stringf( - " -undef\n" - " enable modelling of undef states\n" - "\n" - " -seq \n" - " the max. number of time steps to be considered (default = %s)\n" - "\n" - " -set-assumes\n" - " set all assumptions provided via $assume cells\n" - "\n" - " -ignore-unknown-cells\n" - " ignore all cells that can not be matched to a SAT model\n" - , default_seq); - } - }; - Config cfg; + Config cfg; EquivWorker(RTLIL::Module *module, const SigMap *sigmap, Config cfg) : module(module), satgen(ez.get(), sigmap), cfg(cfg) { satgen.model_undef = cfg.model_undef; diff --git a/passes/equiv/equiv_induct.cc b/passes/equiv/equiv_induct.cc index f7ceb78a3..d843fef67 100644 --- a/passes/equiv/equiv_induct.cc +++ b/passes/equiv/equiv_induct.cc @@ -23,7 +23,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -struct EquivInductWorker : public EquivWorker +struct EquivInductWorker : public EquivWorker<> { SigMap sigmap; @@ -35,7 +35,7 @@ struct EquivInductWorker : public EquivWorker dict ez_step_is_consistent; SigPool undriven_signals; - EquivInductWorker(Module *module, const pool &unproven_equiv_cells, Config cfg) : EquivWorker(module, &sigmap, cfg), sigmap(module), + EquivInductWorker(Module *module, const pool &unproven_equiv_cells, EquivBasicConfig cfg) : EquivWorker<>(module, &sigmap, cfg), sigmap(module), cells(module->selected_cells()), workset(unproven_equiv_cells), success_counter(0) {} @@ -174,7 +174,7 @@ struct EquivInductPass : public Pass { log("Only selected $equiv cells are proven and only selected cells are used to\n"); log("perform the proof.\n"); log("\n"); - EquivWorker::Config::help("4"); + EquivBasicConfig::help("4"); log("\n"); log("This command is very effective in proving complex sequential circuits, when\n"); log("the internal state of the circuit quickly propagates to $equiv cells.\n"); @@ -192,7 +192,7 @@ struct EquivInductPass : public Pass { void execute(std::vector args, Design *design) override { int success_counter = 0; - EquivWorker::Config cfg; + EquivBasicConfig cfg {}; cfg.max_seq = 4; log_header(design, "Executing EQUIV_INDUCT pass.\n"); diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc index f345e9794..ff6df295c 100644 --- a/passes/equiv/equiv_simple.cc +++ b/passes/equiv/equiv_simple.cc @@ -24,45 +24,44 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -struct EquivSimpleWorker : public EquivWorker -{ - struct Config : EquivWorker::Config { - bool verbose = false; - bool short_cones = false; - bool group = true; - bool parse(const std::vector& args, size_t& idx) { - if (EquivWorker::Config::parse(args, idx)) - return true; - if (args[idx] == "-v") { - verbose = true; - return true; - } - if (args[idx] == "-short") { - short_cones = true; - return true; - } - if (args[idx] == "-nogroup") { - group = false; - return true; - } - return false; +struct EquivSimpleConfig : EquivBasicConfig { + bool verbose = false; + bool short_cones = false; + bool group = true; + bool parse(const std::vector& args, size_t& idx) { + if (EquivBasicConfig::parse(args, idx)) + return true; + if (args[idx] == "-v") { + verbose = true; + return true; } - static std::string help(const char* default_seq) { - return EquivWorker::Config::help(default_seq) + - " -v\n" - " verbose output\n" - "\n" - " -short\n" - " create shorter input cones that stop at shared nodes. This yields\n" - " simpler SAT problems but sometimes fails to prove equivalence.\n" - "\n" - " -nogroup\n" - " disabling grouping of $equiv cells by output wire\n" - "\n"; + if (args[idx] == "-short") { + short_cones = true; + return true; } - }; - Config cfg; + if (args[idx] == "-nogroup") { + group = false; + return true; + } + return false; + } + static std::string help(const char* default_seq) { + return EquivBasicConfig::help(default_seq) + + " -v\n" + " verbose output\n" + "\n" + " -short\n" + " create shorter input cones that stop at shared nodes. This yields\n" + " simpler SAT problems but sometimes fails to prove equivalence.\n" + "\n" + " -nogroup\n" + " disabling grouping of $equiv cells by output wire\n" + "\n"; + } +}; +struct EquivSimpleWorker : public EquivWorker +{ const vector &equiv_cells; const vector &assume_cells; struct Cone { @@ -82,8 +81,8 @@ struct EquivSimpleWorker : public EquivWorker pool> imported_cells_cache; - EquivSimpleWorker(const vector &equiv_cells, const vector &assume_cells, DesignModel model, Config cfg) : - EquivWorker(equiv_cells.front()->module, &model.sigmap, cfg), equiv_cells(equiv_cells), assume_cells(assume_cells), + EquivSimpleWorker(const vector &equiv_cells, const vector &assume_cells, DesignModel model, EquivSimpleConfig cfg) : + EquivWorker(equiv_cells.front()->module, &model.sigmap, cfg), equiv_cells(equiv_cells), assume_cells(assume_cells), model(model) {} struct ConeFinder { @@ -270,7 +269,9 @@ struct EquivSimpleWorker : public EquivWorker } void construct_ezsat(const pool& input_bits, int step) { + log("ezsat\n"); if (cfg.set_assumes) { + log("yep assume\n"); if (cfg.verbose && step == cfg.max_seq) { RTLIL::SigSpec assumes_a, assumes_en; satgen.getAssumes(assumes_a, assumes_en, step+1); @@ -427,12 +428,12 @@ struct EquivSimplePass : public Pass { log("\n"); log("This command tries to prove $equiv cells using a simple direct SAT approach.\n"); log("\n"); - EquivSimpleWorker::Config::help("1"); + EquivSimpleConfig::help("1"); log("\n"); } void execute(std::vector args, Design *design) override { - EquivSimpleWorker::Config cfg = {}; + EquivSimpleConfig cfg {}; int success_counter = 0; log_header(design, "Executing EQUIV_SIMPLE pass.\n"); From 91b226b4d40815109f0ac1223bc2fafdf0aa0d03 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 3 Feb 2026 18:40:32 +0100 Subject: [PATCH 142/291] specify: fix test --- tests/various/specify.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/various/specify.ys b/tests/various/specify.ys index d7260d524..86471de5e 100644 --- a/tests/various/specify.ys +++ b/tests/various/specify.ys @@ -43,7 +43,7 @@ select n:C_* -assert-count 2 equiv_make gold gate equiv hierarchy -top equiv equiv_struct -equiv_induct -seq 5 +equiv_induct -ignore-unknown-cells -seq 5 equiv_status -assert design -reset @@ -57,7 +57,7 @@ select n:B_* -assert-count 2 equiv_make gold gate equiv hierarchy -top equiv equiv_struct -equiv_induct -seq 5 +equiv_induct -ignore-unknown-cells -seq 5 equiv_status -assert design -reset From 3f01d7a33ae27df8f1d120dce082b02e526e8a0c Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Tue, 3 Feb 2026 14:41:08 -0800 Subject: [PATCH 143/291] Add test --- tests/arch/xilinx/dsp_preadder_sub.ys | 41 +++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 tests/arch/xilinx/dsp_preadder_sub.ys diff --git a/tests/arch/xilinx/dsp_preadder_sub.ys b/tests/arch/xilinx/dsp_preadder_sub.ys new file mode 100644 index 000000000..04e5e9da0 --- /dev/null +++ b/tests/arch/xilinx/dsp_preadder_sub.ys @@ -0,0 +1,41 @@ +read_verilog < Date: Tue, 3 Feb 2026 22:47:20 +0000 Subject: [PATCH 144/291] Only reuse ABC processes if we're using yosys-abc and it was built with ENABLE_READLINE (cherry picked from commit 5054fd17d7b70f2df97360bb0f0cc1c92a6ffe72) --- passes/techmap/abc.cc | 99 +++++++++++++++++++++++++++---------------- 1 file changed, 63 insertions(+), 36 deletions(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index e9d02b85c..f7fa095a0 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -143,6 +143,14 @@ struct AbcConfig bool markgroups = false; pool enabled_gates; bool cmos_cost = false; + + bool is_yosys_abc() const { +#ifdef ABCEXTERNAL + return false; +#else + return exe_file == yosys_abc_executable; +#endif + } }; struct AbcSigVal { @@ -155,7 +163,12 @@ struct AbcSigVal { } }; -#if defined(__linux__) && !defined(YOSYS_DISABLE_SPAWN) +// REUSE_YOSYS_ABC_PROCESSES only works when ABC is built with ENABLE_READLINE. +#if defined(__linux__) && !defined(YOSYS_DISABLE_SPAWN) && defined(YOSYS_ENABLE_READLINE) +#define REUSE_YOSYS_ABC_PROCESSES +#endif + +#ifdef REUSE_YOSYS_ABC_PROCESSES struct AbcProcess { pid_t pid; @@ -1063,8 +1076,9 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module abc_script += stringf("; dress \"%s/input.blif\"", run_abc.tempdir_name); abc_script += stringf("; write_blif %s/output.blif", run_abc.tempdir_name); abc_script = add_echos_to_abc_cmd(abc_script); -#if defined(__linux__) && !defined(YOSYS_DISABLE_SPAWN) - abc_script += "; echo; echo \"YOSYS_ABC_DONE\"\n"; +#if defined(REUSE_YOSYS_ABC_PROCESSES) + if (config.is_yosys_abc()) + abc_script += "; echo; echo \"YOSYS_ABC_DONE\"\n"; #endif for (size_t i = 0; i+1 < abc_script.size(); i++) @@ -1127,6 +1141,7 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module handle_loops(assign_map, module); } +#if defined(REUSE_YOSYS_ABC_PROCESSES) static bool is_abc_prompt(const std::string &line, std::string &rest) { size_t pos = 0; while (true) { @@ -1197,8 +1212,13 @@ bool read_until_abc_done(abc_output_filter &filt, int fd, DeferredLogs &logs) { line.append(start, end - start); } } +#endif +#if defined(REUSE_YOSYS_ABC_PROCESSES) void RunAbcState::run(ConcurrentStack &process_pool) +#else +void RunAbcState::run(ConcurrentStack &) +#endif { std::string buffer = stringf("%s/input.blif", tempdir_name); FILE *f = fopen(buffer.c_str(), "wt"); @@ -1323,9 +1343,13 @@ void RunAbcState::run(ConcurrentStack &process_pool) logs.log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n", count_gates, GetSize(signal_list), count_input, count_output); - if (count_output > 0) - { - std::string tmp_script_name = stringf("%s/abc.script", tempdir_name); + if (count_output == 0) { + log("Don't call ABC as there is nothing to map.\n"); + return; + } + int ret; + std::string tmp_script_name = stringf("%s/abc.script", tempdir_name); + do { logs.log("Running ABC script: %s\n", replace_tempdir(tmp_script_name, tempdir_name, config.show_tempdir)); errno = 0; @@ -1356,7 +1380,7 @@ void RunAbcState::run(ConcurrentStack &process_pool) abc_argv[2] = strdup("-f"); abc_argv[3] = strdup(tmp_script_name.c_str()); abc_argv[4] = 0; - int ret = abc::Abc_RealMain(4, abc_argv); + ret = abc::Abc_RealMain(4, abc_argv); free(abc_argv[0]); free(abc_argv[1]); free(abc_argv[2]); @@ -1371,39 +1395,42 @@ void RunAbcState::run(ConcurrentStack &process_pool) for (std::string line; std::getline(temp_stdouterr_r, line); ) filt.next_line(line + "\n"); temp_stdouterr_r.close(); -#elif defined(__linux__) && !defined(YOSYS_DISABLE_SPAWN) - AbcProcess process; - if (std::optional process_opt = process_pool.try_pop_back()) { - process = std::move(process_opt.value()); - } else if (std::optional process_opt = spawn_abc(config.exe_file.c_str(), logs)) { - process = std::move(process_opt.value()); - } else { - return; - } - std::string cmd = stringf( - "empty\n" - "source %s\n", tmp_script_name); - int ret = write(process.to_child_pipe, cmd.c_str(), cmd.size()); - if (ret != static_cast(cmd.size())) { - logs.log_error("write failed"); - return; - } - ret = read_until_abc_done(filt, process.from_child_pipe, logs) ? 0 : 1; - if (ret == 0) { - process_pool.push_back(std::move(process)); - } + break; #else - std::string cmd = stringf("\"%s\" -s -f %s/abc.script 2>&1", config.exe_file.c_str(), tempdir_name.c_str()); - int ret = run_command(cmd, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1)); -#endif - if (ret != 0) { - logs.log_error("ABC: execution of script \"%s\" failed: return code %d (errno=%d).\n", tmp_script_name, ret, errno); - return; +#if defined(REUSE_YOSYS_ABC_PROCESSES) + if (config.is_yosys_abc()) { + AbcProcess process; + if (std::optional process_opt = process_pool.try_pop_back()) { + process = std::move(process_opt.value()); + } else if (std::optional process_opt = spawn_abc(config.exe_file.c_str(), logs)) { + process = std::move(process_opt.value()); + } else { + return; + } + std::string cmd = stringf( + "empty\n" + "source %s\n", tmp_script_name); + ret = write(process.to_child_pipe, cmd.c_str(), cmd.size()); + if (ret != static_cast(cmd.size())) { + logs.log_error("write failed"); + return; + } + ret = read_until_abc_done(filt, process.from_child_pipe, logs) ? 0 : 1; + if (ret == 0) { + process_pool.push_back(std::move(process)); + } + break; } - did_run = true; +#endif + std::string cmd = stringf("\"%s\" -s -f %s 2>&1", config.exe_file, tmp_script_name); + ret = run_command(cmd, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1)); +#endif + } while (false); + if (ret != 0) { + logs.log_error("ABC: execution of script \"%s\" failed: return code %d (errno=%d).\n", tmp_script_name, ret, errno); return; } - log("Don't call ABC as there is nothing to map.\n"); + did_run = true; } void emit_global_input_files(const AbcConfig &config) From ddfa34d7439381a73203702f76c71fbe199c8cd1 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 4 Feb 2026 08:54:38 +0100 Subject: [PATCH 145/291] Next dev cycle --- CHANGELOG | 3 +++ Makefile | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 6e2bca32c..e345a8514 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ List of major changes and improvements between releases ======================================================= +Yosys 0.62 .. Yosys 0.63-dev +-------------------------- + Yosys 0.61 .. Yosys 0.62 -------------------------- * Various diff --git a/Makefile b/Makefile index 28608f573..364e1ce8d 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.62 +YOSYS_VER := 0.62+0 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) @@ -186,7 +186,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: -# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 5ae48ee.. | wc -l`/;" Makefile + sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 7326bb7.. | wc -l`/;" Makefile ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q) From 0640a5904b400f981df771a6f7789cd7b8c5e139 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Thu, 5 Feb 2026 00:33:25 +0000 Subject: [PATCH 146/291] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 364e1ce8d..81f9e0652 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.62+0 +YOSYS_VER := 0.62+9 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 34f8582725b5d286a705b17df1fe546df6eaab34 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Sat, 7 Feb 2026 12:12:13 +1300 Subject: [PATCH 147/291] Sanitize ABC global and per-run temporary directory names in logs --- passes/techmap/abc.cc | 56 ++++++++++++---------- tests/techmap/abc_temp_dir_sanitization.ys | 13 +++++ 2 files changed, 45 insertions(+), 24 deletions(-) create mode 100644 tests/techmap/abc_temp_dir_sanitization.ys diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index f7fa095a0..6e5b1fba8 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -285,7 +285,7 @@ using AbcSigMap = SigValMap; struct RunAbcState { const AbcConfig &config; - std::string tempdir_name; + std::string per_run_tempdir_name; std::vector signal_list; bool did_run = false; bool err = false; @@ -836,16 +836,23 @@ std::string fold_abc_cmd(std::string str) return new_str; } -std::string replace_tempdir(std::string text, std::string tempdir_name, bool show_tempdir) +std::string replace_tempdir(std::string text, std::string_view global_tempdir_name, std::string_view per_run_tempdir_name, bool show_tempdir) { if (show_tempdir) return text; while (1) { - size_t pos = text.find(tempdir_name); + size_t pos = text.find(global_tempdir_name); if (pos == std::string::npos) break; - text = text.substr(0, pos) + "" + text.substr(pos + GetSize(tempdir_name)); + text = text.substr(0, pos) + "" + text.substr(pos + GetSize(global_tempdir_name)); + } + + while (1) { + size_t pos = text.find(per_run_tempdir_name); + if (pos == std::string::npos) + break; + text = text.substr(0, pos) + "" + text.substr(pos + GetSize(per_run_tempdir_name)); } std::string selfdir_name = proc_self_dirname(); @@ -867,11 +874,12 @@ struct abc_output_filter bool got_cr; int escape_seq_state; std::string linebuf; - std::string tempdir_name; + std::string global_tempdir_name; + std::string per_run_tempdir_name; bool show_tempdir; - abc_output_filter(RunAbcState& state, std::string tempdir_name, bool show_tempdir) - : state(state), tempdir_name(tempdir_name), show_tempdir(show_tempdir) + abc_output_filter(RunAbcState& state, std::string global_tempdir_name, std::string per_run_tempdir_name, bool show_tempdir) + : state(state), global_tempdir_name(global_tempdir_name), per_run_tempdir_name(per_run_tempdir_name), show_tempdir(show_tempdir) { got_cr = false; escape_seq_state = 0; @@ -898,7 +906,7 @@ struct abc_output_filter return; } if (ch == '\n') { - state.logs.log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir)); + state.logs.log("ABC: %s\n", replace_tempdir(linebuf, global_tempdir_name, per_run_tempdir_name, show_tempdir)); got_cr = false, linebuf.clear(); return; } @@ -999,15 +1007,15 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module const AbcConfig &config = run_abc.config; if (config.cleanup) - run_abc.tempdir_name = get_base_tmpdir() + "/"; + run_abc.per_run_tempdir_name = get_base_tmpdir() + "/"; else - run_abc.tempdir_name = "_tmp_"; - run_abc.tempdir_name += proc_program_prefix() + "yosys-abc-XXXXXX"; - run_abc.tempdir_name = make_temp_dir(run_abc.tempdir_name); + run_abc.per_run_tempdir_name = "_tmp_"; + run_abc.per_run_tempdir_name += proc_program_prefix() + "yosys-abc-XXXXXX"; + run_abc.per_run_tempdir_name = make_temp_dir(run_abc.per_run_tempdir_name); log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n", - module->name.c_str(), replace_tempdir(run_abc.tempdir_name, run_abc.tempdir_name, config.show_tempdir).c_str()); + module->name.c_str(), replace_tempdir(run_abc.per_run_tempdir_name, config.global_tempdir_name, run_abc.per_run_tempdir_name, config.show_tempdir).c_str()); - std::string abc_script = stringf("read_blif \"%s/input.blif\"; ", run_abc.tempdir_name); + std::string abc_script = stringf("read_blif \"%s/input.blif\"; ", run_abc.per_run_tempdir_name); if (!config.liberty_files.empty() || !config.genlib_files.empty()) { std::string dont_use_args; @@ -1073,8 +1081,8 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos)) abc_script = abc_script.substr(0, pos) + config.lutin_shared + abc_script.substr(pos+3); if (config.abc_dress) - abc_script += stringf("; dress \"%s/input.blif\"", run_abc.tempdir_name); - abc_script += stringf("; write_blif %s/output.blif", run_abc.tempdir_name); + abc_script += stringf("; dress \"%s/input.blif\"", run_abc.per_run_tempdir_name); + abc_script += stringf("; write_blif %s/output.blif", run_abc.per_run_tempdir_name); abc_script = add_echos_to_abc_cmd(abc_script); #if defined(REUSE_YOSYS_ABC_PROCESSES) if (config.is_yosys_abc()) @@ -1085,7 +1093,7 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module if (abc_script[i] == ';' && abc_script[i+1] == ' ') abc_script[i+1] = '\n'; - std::string buffer = stringf("%s/abc.script", run_abc.tempdir_name); + std::string buffer = stringf("%s/abc.script", run_abc.per_run_tempdir_name); FILE *f = fopen(buffer.c_str(), "wt"); if (f == nullptr) log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno)); @@ -1220,7 +1228,7 @@ void RunAbcState::run(ConcurrentStack &process_pool) void RunAbcState::run(ConcurrentStack &) #endif { - std::string buffer = stringf("%s/input.blif", tempdir_name); + std::string buffer = stringf("%s/input.blif", per_run_tempdir_name); FILE *f = fopen(buffer.c_str(), "wt"); if (f == nullptr) { logs.log("Opening %s for writing failed: %s\n", buffer, strerror(errno)); @@ -1348,14 +1356,14 @@ void RunAbcState::run(ConcurrentStack &) return; } int ret; - std::string tmp_script_name = stringf("%s/abc.script", tempdir_name); + std::string tmp_script_name = stringf("%s/abc.script", per_run_tempdir_name); do { - logs.log("Running ABC script: %s\n", replace_tempdir(tmp_script_name, tempdir_name, config.show_tempdir)); + logs.log("Running ABC script: %s\n", replace_tempdir(tmp_script_name, config.global_tempdir_name, per_run_tempdir_name, config.show_tempdir)); errno = 0; - abc_output_filter filt(*this, tempdir_name, config.show_tempdir); + abc_output_filter filt(*this, config.global_tempdir_name, per_run_tempdir_name, config.show_tempdir); #ifdef YOSYS_LINK_ABC - string temp_stdouterr_name = stringf("%s/stdouterr.txt", tempdir_name); + string temp_stdouterr_name = stringf("%s/stdouterr.txt", per_run_tempdir_name); FILE *temp_stdouterr_w = fopen(temp_stdouterr_name.c_str(), "w"); if (temp_stdouterr_w == NULL) log_error("ABC: cannot open a temporary file for output redirection"); @@ -1502,7 +1510,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL return; } - std::string buffer = stringf("%s/%s", run_abc.tempdir_name, "output.blif"); + std::string buffer = stringf("%s/%s", run_abc.per_run_tempdir_name, "output.blif"); std::ifstream ifs; ifs.open(buffer); if (ifs.fail()) @@ -1789,7 +1797,7 @@ void AbcModuleState::finish() if (run_abc.config.cleanup) { log("Removing temp directory.\n"); - remove_directory(run_abc.tempdir_name); + remove_directory(run_abc.per_run_tempdir_name); } log_pop(); } diff --git a/tests/techmap/abc_temp_dir_sanitization.ys b/tests/techmap/abc_temp_dir_sanitization.ys new file mode 100644 index 000000000..ed87ff980 --- /dev/null +++ b/tests/techmap/abc_temp_dir_sanitization.ys @@ -0,0 +1,13 @@ +read_verilog < Date: Fri, 6 Feb 2026 17:26:08 -0800 Subject: [PATCH 148/291] Typo --- libs/ezsat/ezcmdline.cc | 2 +- libs/ezsat/ezminisat.cc | 4 ++-- libs/ezsat/ezsat.cc | 2 +- libs/ezsat/ezsat.h | 6 +++--- passes/sat/sat.cc | 4 ++-- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/libs/ezsat/ezcmdline.cc b/libs/ezsat/ezcmdline.cc index dddec1067..2eef1b06d 100644 --- a/libs/ezsat/ezcmdline.cc +++ b/libs/ezsat/ezcmdline.cc @@ -67,7 +67,7 @@ bool ezCmdlineSAT::solver(const std::vector &modelExpressions, std::vector< modelValues.resize(modelIdx.size()); if (!status_sat && !status_unsat) { - solverTimoutStatus = true; + solverTimeoutStatus = true; } if (!status_sat) { return false; diff --git a/libs/ezsat/ezminisat.cc b/libs/ezsat/ezminisat.cc index 30df625cb..1f4b8855f 100644 --- a/libs/ezsat/ezminisat.cc +++ b/libs/ezsat/ezminisat.cc @@ -103,7 +103,7 @@ bool ezMiniSAT::solver(const std::vector &modelExpressions, std::vector 0) { if (alarmHandlerTimeout == 0) - solverTimoutStatus = true; + solverTimeoutStatus = true; alarm(0); sigaction(SIGALRM, &old_sig_action, NULL); alarm(old_alarm_timeout); diff --git a/libs/ezsat/ezsat.cc b/libs/ezsat/ezsat.cc index fbdfc20f6..3e63d3e84 100644 --- a/libs/ezsat/ezsat.cc +++ b/libs/ezsat/ezsat.cc @@ -54,7 +54,7 @@ ezSAT::ezSAT() cnfClausesCount = 0; solverTimeout = 0; - solverTimoutStatus = false; + solverTimeoutStatus = false; literal("CONST_TRUE"); literal("CONST_FALSE"); diff --git a/libs/ezsat/ezsat.h b/libs/ezsat/ezsat.h index 507708cb2..445c8edba 100644 --- a/libs/ezsat/ezsat.h +++ b/libs/ezsat/ezsat.h @@ -78,7 +78,7 @@ protected: public: int solverTimeout; - bool solverTimoutStatus; + bool solverTimeoutStatus; ezSAT(); virtual ~ezSAT(); @@ -153,8 +153,8 @@ public: solverTimeout = newTimeoutSeconds; } - bool getSolverTimoutStatus() { - return solverTimoutStatus; + bool getSolverTimeoutStatus() { + return solverTimeoutStatus; } // manage CNF (usually only accessed by SAT solvers) diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 90b85d709..bb7b9ee29 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -441,7 +441,7 @@ struct SatHelper log_assert(gotTimeout == false); ez->setSolverTimeout(timeout); bool success = ez->solve(modelExpressions, modelValues, assumptions); - if (ez->getSolverTimoutStatus()) + if (ez->getSolverTimeoutStatus()) gotTimeout = true; return success; } @@ -451,7 +451,7 @@ struct SatHelper log_assert(gotTimeout == false); ez->setSolverTimeout(timeout); bool success = ez->solve(modelExpressions, modelValues, a, b, c, d, e, f); - if (ez->getSolverTimoutStatus()) + if (ez->getSolverTimeoutStatus()) gotTimeout = true; return success; } From 2bb352a86171ac2bb36d3baa9ac3fb3046a521f5 Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Fri, 6 Feb 2026 17:45:00 -0800 Subject: [PATCH 149/291] Missing newline --- libs/ezsat/ezsat.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/ezsat/ezsat.cc b/libs/ezsat/ezsat.cc index 3e63d3e84..69a59c8cd 100644 --- a/libs/ezsat/ezsat.cc +++ b/libs/ezsat/ezsat.cc @@ -1225,7 +1225,7 @@ ezSATvec ezSAT::vec(const std::vector &vec) void ezSAT::printDIMACS(FILE *f, bool verbose, const std::vector> &extraClauses) const { if (cnfConsumed) { - fprintf(stderr, "Usage error: printDIMACS() must not be called after cnfConsumed()!"); + fprintf(stderr, "Usage error: printDIMACS() must not be called after cnfConsumed()!\n"); abort(); } From b2f9ac4fb5d5a79515b9f905bf76a493b301fad3 Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Fri, 6 Feb 2026 18:18:03 -0800 Subject: [PATCH 150/291] Check for dimacs nullptr on file creation+fn call --- libs/ezsat/ezcmdline.cc | 3 +++ libs/ezsat/ezsat.cc | 5 +++++ 2 files changed, 8 insertions(+) diff --git a/libs/ezsat/ezcmdline.cc b/libs/ezsat/ezcmdline.cc index 2eef1b06d..57800591c 100644 --- a/libs/ezsat/ezcmdline.cc +++ b/libs/ezsat/ezcmdline.cc @@ -14,6 +14,9 @@ bool ezCmdlineSAT::solver(const std::vector &modelExpressions, std::vector< const std::string cnf_filename = Yosys::stringf("%s/problem.cnf", tempdir_name.c_str()); const std::string sat_command = Yosys::stringf("%s %s", command.c_str(), cnf_filename.c_str()); FILE *dimacs = fopen(cnf_filename.c_str(), "w"); + if (dimacs == nullptr) { + Yosys::log_cmd_error("Failed to create CNF file `%s`.\n", cnf_filename.c_str()); + } std::vector modelIdx; for (auto id : modelExpressions) diff --git a/libs/ezsat/ezsat.cc b/libs/ezsat/ezsat.cc index 69a59c8cd..8e3114705 100644 --- a/libs/ezsat/ezsat.cc +++ b/libs/ezsat/ezsat.cc @@ -1224,6 +1224,11 @@ ezSATvec ezSAT::vec(const std::vector &vec) void ezSAT::printDIMACS(FILE *f, bool verbose, const std::vector> &extraClauses) const { + if (f == nullptr) { + fprintf(stderr, "Usage error: printDIMACS() must not be called with a null FILE pointer\n"); + abort(); + } + if (cnfConsumed) { fprintf(stderr, "Usage error: printDIMACS() must not be called after cnfConsumed()!\n"); abort(); From 1502e233715854c8835563b3f0d26fb7c84f49d3 Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Fri, 6 Feb 2026 19:26:32 -0800 Subject: [PATCH 151/291] Set solver from scratchpad or command line --- kernel/satgen.h | 1 + passes/sat/sat.cc | 46 +++++++++++++++++++++++++++++++++++++++++----- 2 files changed, 42 insertions(+), 5 deletions(-) diff --git a/kernel/satgen.h b/kernel/satgen.h index 7815847b3..c53d20fe0 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -59,6 +59,7 @@ struct SatSolver struct ezSatPtr : public std::unique_ptr { ezSatPtr() : unique_ptr(yosys_satsolver->create()) { } + explicit ezSatPtr(SatSolver *solver) : unique_ptr((solver ? solver : yosys_satsolver)->create()) { } }; struct SatGen diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index bb7b9ee29..8a0a45dcf 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -31,6 +31,22 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN +static SatSolver *find_satsolver(const std::string &name) +{ + for (auto solver = yosys_satsolver_list; solver != nullptr; solver = solver->next) + if (solver->name == name) + return solver; + return nullptr; +} + +static std::string list_satsolvers() +{ + std::string result; + for (auto solver = yosys_satsolver_list; solver != nullptr; solver = solver->next) + result += result.empty() ? solver->name : ", " + solver->name; + return result; +} + struct SatHelper { RTLIL::Design *design; @@ -60,8 +76,8 @@ struct SatHelper int max_timestep, timeout; bool gotTimeout; - SatHelper(RTLIL::Design *design, RTLIL::Module *module, bool enable_undef, bool set_def_formal) : - design(design), module(module), sigmap(module), ct(design), satgen(ez.get(), &sigmap) + SatHelper(RTLIL::Design *design, RTLIL::Module *module, SatSolver *solver, bool enable_undef, bool set_def_formal) : + design(design), module(module), sigmap(module), ct(design), ez(solver), satgen(ez.get(), &sigmap) { this->enable_undef = enable_undef; satgen.model_undef = enable_undef; @@ -1066,6 +1082,10 @@ struct SatPass : public Pass { log(" -timeout \n"); log(" Maximum number of seconds a single SAT instance may take.\n"); log("\n"); + log(" -select-solver \n"); + log(" Select SAT solver implementation for this invocation.\n"); + log(" If not given, uses scratchpad key 'sat.solver' if set, otherwise default.\n"); + log("\n"); log(" -verify\n"); log(" Return an error and stop the synthesis script if the proof fails.\n"); log("\n"); @@ -1097,8 +1117,14 @@ struct SatPass : public Pass { log_header(design, "Executing SAT pass (solving SAT problems in the circuit).\n"); + std::string solver_name = design->scratchpad_get_string("sat.solver", ""); + size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-select-solver" && argidx+1 < args.size()) { + solver_name = args[++argidx]; + continue; + } if (args[argidx] == "-all") { loopcount = -1; continue; @@ -1336,6 +1362,14 @@ struct SatPass : public Pass { } extra_args(args, argidx, design); + SatSolver *solver = yosys_satsolver; + if (!solver_name.empty()) { + solver = find_satsolver(solver_name); + if (solver == nullptr) + log_cmd_error("Unknown SAT solver '%s'. Available solvers: %s\n", + solver_name, list_satsolvers()); + } + RTLIL::Module *module = NULL; for (auto mod : design->selected_modules()) { if (module) @@ -1398,13 +1432,15 @@ struct SatPass : public Pass { shows.push_back(wire->name.str()); } + log("Using SAT solver `%s`.\n", solver->name.c_str()); + if (tempinduct) { if (loopcount > 0 || max_undef) log_cmd_error("The options -max, -all, and -max_undef are not supported for temporal induction proofs!\n"); - SatHelper basecase(design, module, enable_undef, set_def_formal); - SatHelper inductstep(design, module, enable_undef, set_def_formal); + SatHelper basecase(design, module, solver, enable_undef, set_def_formal); + SatHelper inductstep(design, module, solver, enable_undef, set_def_formal); basecase.sets = sets; basecase.set_assumes = set_assumes; @@ -1593,7 +1629,7 @@ struct SatPass : public Pass { if (maxsteps > 0) log_cmd_error("The options -maxsteps is only supported for temporal induction proofs!\n"); - SatHelper sathelper(design, module, enable_undef, set_def_formal); + SatHelper sathelper(design, module, solver, enable_undef, set_def_formal); sathelper.sets = sets; sathelper.set_assumes = set_assumes; From b8ee50d77f92da71420186a9ab2918918b32b809 Mon Sep 17 00:00:00 2001 From: Rowan Goemans Date: Mon, 9 Feb 2026 14:13:40 +0100 Subject: [PATCH 152/291] kernel/celledges: cover more cell types --- kernel/celledges.cc | 144 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 136 insertions(+), 8 deletions(-) diff --git a/kernel/celledges.cc b/kernel/celledges.cc index c39ced95a..195d4b15b 100644 --- a/kernel/celledges.cc +++ b/kernel/celledges.cc @@ -112,6 +112,41 @@ void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) db->add_edge(cell, ID::A, i, ID::Y, 0, -1); } +void logic_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) +{ + int a_width = GetSize(cell->getPort(ID::A)); + int b_width = GetSize(cell->getPort(ID::B)); + + for (int i = 0; i < a_width; i++) + db->add_edge(cell, ID::A, i, ID::Y, 0, -1); + for (int i = 0; i < b_width; i++) + db->add_edge(cell, ID::B, i, ID::Y, 0, -1); +} + +void concat_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) +{ + int a_width = GetSize(cell->getPort(ID::A)); + int b_width = GetSize(cell->getPort(ID::B)); + + for (int i = 0; i < a_width; i++) + db->add_edge(cell, ID::A, i, ID::Y, i, -1); + for (int i = 0; i < b_width; i++) + db->add_edge(cell, ID::B, i, ID::Y, a_width + i, -1); +} + +void slice_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) +{ + int offset = cell->getParam(ID::OFFSET).as_int(); + int a_width = GetSize(cell->getPort(ID::A)); + int y_width = GetSize(cell->getPort(ID::Y)); + + for (int i = 0; i < y_width; i++) { + int a_bit = offset + i; + if (a_bit >= 0 && a_bit < a_width) + db->add_edge(cell, ID::A, a_bit, ID::Y, i, -1); + } +} + void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { int a_width = GetSize(cell->getPort(ID::A)); @@ -254,7 +289,7 @@ void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) int skip = 1 << (k + 1); int base = skip -1; if (i % skip != base && i - a_width + 2 < 1 << b_width_capped) - db->add_edge(cell, ID::B, k, ID::Y, i, -1); + db->add_edge(cell, ID::B, k, ID::Y, i, -1); } else if (is_signed) { if (i - a_width + 2 < 1 << b_width_capped) db->add_edge(cell, ID::B, k, ID::Y, i, -1); @@ -388,6 +423,64 @@ void ff_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) db->add_edge(cell, ID::ARST, 0, ID::Q, k, -1); } +void full_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) +{ + std::vector input_ports; + std::vector output_ports; + + for (auto &conn : cell->connections()) + { + RTLIL::IdString port = conn.first; + RTLIL::PortDir dir = cell->port_dir(port); + if (cell->input(port) || dir == RTLIL::PortDir::PD_INOUT) + input_ports.push_back(port); + if (cell->output(port) || dir == RTLIL::PortDir::PD_INOUT) + output_ports.push_back(port); + } + + for (auto out_port : output_ports) + { + int out_width = GetSize(cell->getPort(out_port)); + for (int out_bit = 0; out_bit < out_width; out_bit++) + { + for (auto in_port : input_ports) + { + int in_width = GetSize(cell->getPort(in_port)); + for (int in_bit = 0; in_bit < in_width; in_bit++) + db->add_edge(cell, in_port, in_bit, out_port, out_bit, -1); + } + } + } +} + +void bweqx_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) +{ + int width = GetSize(cell->getPort(ID::Y)); + int a_width = GetSize(cell->getPort(ID::A)); + int b_width = GetSize(cell->getPort(ID::B)); + int max_width = std::min(width, std::min(a_width, b_width)); + + for (int i = 0; i < max_width; i++) { + db->add_edge(cell, ID::A, i, ID::Y, i, -1); + db->add_edge(cell, ID::B, i, ID::Y, i, -1); + } +} + +void bwmux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) +{ + int width = GetSize(cell->getPort(ID::Y)); + int a_width = GetSize(cell->getPort(ID::A)); + int b_width = GetSize(cell->getPort(ID::B)); + int s_width = GetSize(cell->getPort(ID::S)); + int max_width = std::min(width, std::min(a_width, std::min(b_width, s_width))); + + for (int i = 0; i < max_width; i++) { + db->add_edge(cell, ID::A, i, ID::Y, i, -1); + db->add_edge(cell, ID::B, i, ID::Y, i, -1); + db->add_edge(cell, ID::S, i, ID::Y, i, -1); + } +} + PRIVATE_NAMESPACE_END bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL::Cell *cell) @@ -417,6 +510,21 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL return true; } + if (cell->type.in(ID($logic_and), ID($logic_or))) { + logic_op(this, cell); + return true; + } + + if (cell->type == ID($slice)) { + slice_op(this, cell); + return true; + } + + if (cell->type == ID($concat)) { + concat_op(this, cell); + return true; + } + if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) { shift_op(this, cell); return true; @@ -442,6 +550,16 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL return true; } + if (cell->type == ID($bweqx)) { + bweqx_op(this, cell); + return true; + } + + if (cell->type == ID($bwmux)) { + bwmux_op(this, cell); + return true; + } + if (cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2), ID($meminit))) { mem_op(this, cell); return true; @@ -452,13 +570,24 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL return true; } - // FIXME: $mul $div $mod $divfloor $modfloor $slice $concat - // FIXME: $lut $sop $alu $lcu $macc $macc_v2 $fa - // FIXME: $mul $div $mod $divfloor $modfloor $pow $slice $concat $bweqx - // FIXME: $lut $sop $alu $lcu $macc $fa $logic_and $logic_or $bwmux + if (cell->type.in(ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow))) { + full_op(this, cell); + return true; + } - // FIXME: $_BUF_ $_NOT_ $_AND_ $_NAND_ $_OR_ $_NOR_ $_XOR_ $_XNOR_ $_ANDNOT_ $_ORNOT_ - // FIXME: $_MUX_ $_NMUX_ $_MUX4_ $_MUX8_ $_MUX16_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_ + if (cell->type.in(ID($lut), ID($sop), ID($alu), ID($lcu), ID($macc), ID($macc_v2))) { + full_op(this, cell); + return true; + } + + if (cell->type.in( + ID($_BUF_), ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), + ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_), + ID($_MUX4_), ID($_MUX8_), ID($_MUX16_), ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), + ID($_OAI4_), ID($_TBUF_))) { + full_op(this, cell); + return true; + } // FIXME: $specify2 $specify3 $specrule ??? // FIXME: $equiv $set_tag $get_tag $overwrite_tag $original_tag @@ -468,4 +597,3 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL return false; } - From 6f6fa49d3cac7f2d379a162b0dc6dc3ea49faa54 Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Mon, 9 Feb 2026 09:05:56 -0800 Subject: [PATCH 153/291] Typo --- passes/cmds/scratchpad.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/cmds/scratchpad.cc b/passes/cmds/scratchpad.cc index f64ce943c..24ab5cfd8 100644 --- a/passes/cmds/scratchpad.cc +++ b/passes/cmds/scratchpad.cc @@ -37,7 +37,7 @@ struct ScratchpadPass : public Pass { log("\n"); log(" scratchpad [options]\n"); log("\n"); - log("This pass allows to read and modify values from the scratchpad of the current\n"); + log("This pass allows reading and modifying values from the scratchpad of the current\n"); log("design. Options:\n"); log("\n"); log(" -get \n"); From b04948a8cdd2f13838f2472b7af4afa1ad516f6f Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Mon, 9 Feb 2026 09:38:45 -0800 Subject: [PATCH 154/291] Simplify test --- tests/arch/xilinx/dsp_preadder_sub.ys | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/tests/arch/xilinx/dsp_preadder_sub.ys b/tests/arch/xilinx/dsp_preadder_sub.ys index 04e5e9da0..0e23ac373 100644 --- a/tests/arch/xilinx/dsp_preadder_sub.ys +++ b/tests/arch/xilinx/dsp_preadder_sub.ys @@ -1,23 +1,11 @@ read_verilog < Date: Mon, 9 Feb 2026 23:16:47 +0100 Subject: [PATCH 155/291] Makefile: test target requires unit-test, add vanilla-test for old test target --- .github/workflows/test-sanitizers.yml | 4 +- .github/workflows/test-verific.yml | 4 +- Makefile | 6 +- README.md | 4 +- .../extending_yosys/test_suites.rst | 55 +++++++++++++------ 5 files changed, 47 insertions(+), 26 deletions(-) diff --git a/.github/workflows/test-sanitizers.yml b/.github/workflows/test-sanitizers.yml index 11a339cd3..c6b3d8db0 100644 --- a/.github/workflows/test-sanitizers.yml +++ b/.github/workflows/test-sanitizers.yml @@ -65,7 +65,7 @@ jobs: - name: Run tests shell: bash run: | - make -j$procs test TARGETS= EXTRA_TARGETS= + make -j$procs vanilla-test TARGETS= EXTRA_TARGETS= - name: Report errors if: ${{ failure() }} @@ -76,4 +76,4 @@ jobs: - name: Run unit tests shell: bash run: | - make -j$procs unit-test ENABLE_LIBYOSYS=1 + make -j$procs unit-test diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml index adc6f59d8..feba3c0f9 100644 --- a/.github/workflows/test-verific.yml +++ b/.github/workflows/test-verific.yml @@ -68,7 +68,7 @@ jobs: - name: Run Yosys tests run: | - make -j$procs test + make -j$procs vanilla-test - name: Run Verific specific Yosys tests run: | @@ -83,7 +83,7 @@ jobs: - name: Run unit tests shell: bash run: | - make -j$procs unit-test ENABLE_LTO=1 ENABLE_LIBYOSYS=1 + make -j$procs unit-test ENABLE_LTO=1 test-pyosys: needs: pre-job diff --git a/Makefile b/Makefile index 364e1ce8d..7ce3153df 100644 --- a/Makefile +++ b/Makefile @@ -977,9 +977,11 @@ makefile-tests/%: %/run-test.mk $(TARGETS) $(EXTRA_TARGETS) $(MAKE) -C $* -f run-test.mk +@echo "...passed tests in $*" -test: makefile-tests abcopt-tests seed-tests +test: vanilla-test unit-test + +vanilla-test: makefile-tests abcopt-tests seed-tests @echo "" - @echo " Passed \"make test\"." + @echo " Passed \"make vanilla-test\"." ifeq ($(ENABLE_VERIFIC),1) ifeq ($(YOSYS_NOVERIFIC),1) @echo " Ran tests without verific support due to YOSYS_NOVERIFIC=1." diff --git a/README.md b/README.md index 3b2f41768..df65a6a10 100644 --- a/README.md +++ b/README.md @@ -114,8 +114,8 @@ To build Yosys simply type 'make' in this directory. $ sudo make install Tests are located in the tests subdirectory and can be executed using the test -target. Note that you need gawk as well as a recent version of iverilog (i.e. -build from git). Then, execute tests via: +target. Note that you need gawk, a recent version of iverilog, and gtest. +Execute tests via: $ make test diff --git a/docs/source/yosys_internals/extending_yosys/test_suites.rst b/docs/source/yosys_internals/extending_yosys/test_suites.rst index 81a79e77f..c43dc3a84 100644 --- a/docs/source/yosys_internals/extending_yosys/test_suites.rst +++ b/docs/source/yosys_internals/extending_yosys/test_suites.rst @@ -8,7 +8,43 @@ Running the included test suite The Yosys source comes with a test suite to avoid regressions and keep everything working as expected. Tests can be run by calling ``make test`` from -the root Yosys directory. +the root Yosys directory. By default, this runs vanilla and unit tests. + +Vanilla tests +~~~~~~~~~~~~~ + +These make up the majority of our testing coverage. +They can be run with ``make vanilla-test`` and are based on calls to +make subcommands (``make makefile-tests``) and shell scripts +(``make seed-tests`` and ``make abcopt-tests``). Both use ``run-test.sh`` +files, but make-based tests only call ``tests/gen-tests-makefile.sh`` +to generate a makefile appropriate for the given directory, so only +afterwards when make is invoked do the tests actually run. + +Usually their structure looks something like this: +you write a .ys file that gets automatically run, +which runs a frontend like ``read_verilog`` or ``read_rtlil`` with +a relative path or a heredoc, then runs some commands including the command +under test, and then uses :doc:`/using_yosys/more_scripting/selections` +with ``-assert-count``. Usually it's unnecessary to "register" the test anywhere +as if it's similar to other tests it will be run together with the rest. + +Unit tests +~~~~~~~~~~ + +Running the unit tests requires the following additional packages: + +.. tab:: Ubuntu + + .. code:: console + + sudo apt-get install libgtest-dev + +.. tab:: macOS + + No additional requirements. + +Unit tests can be run with ``make unit-test``. Functional tests ~~~~~~~~~~~~~~~~ @@ -41,23 +77,6 @@ instructions `_. Then, set the :makevar:`ENABLE_FUNCTIONAL_TESTS` make variable when calling ``make test`` and the functional tests will be run as well. -Unit tests -~~~~~~~~~~ - -Running the unit tests requires the following additional packages: - -.. tab:: Ubuntu - - .. code:: console - - sudo apt-get install libgtest-dev - -.. tab:: macOS - - No additional requirements. - -Unit tests can be run with ``make unit-test``. - Docs tests ~~~~~~~~~~ From a6e33d99161d9fe0be662b51de376bfa3227e311 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 10 Feb 2026 00:38:43 +0000 Subject: [PATCH 156/291] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 81f9e0652..d0ca321e3 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.62+9 +YOSYS_VER := 0.62+14 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 030e495c8b617ba59b4cd01393f85448450c373a Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 10 Feb 2026 15:05:17 +1300 Subject: [PATCH 157/291] test-build: Build and cache libyosys.so --- .github/workflows/test-build.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index ab6eb3148..6cb60f1fd 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -71,7 +71,7 @@ jobs: mkdir build cd build make -f ../Makefile config-$CC - make -f ../Makefile -j$procs + make -f ../Makefile -j$procs ENABLE_LIBYOSYS=1 - name: Log yosys-config output run: | @@ -81,7 +81,7 @@ jobs: shell: bash run: | cd build - tar -cvf ../build.tar share/ yosys yosys-* + tar -cvf ../build.tar share/ yosys yosys-* libyosys.so - name: Store build artifact uses: actions/upload-artifact@v4 From 9f30f0e7d668f9caba7a53953152e4d981eadab8 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 10 Feb 2026 15:34:47 +1300 Subject: [PATCH 158/291] test-build: Don't rebuild OBJS --- .github/workflows/test-build.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index 6cb60f1fd..a14234925 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -131,7 +131,7 @@ jobs: - name: Run tests shell: bash run: | - make -j$procs test TARGETS= EXTRA_TARGETS= CONFIG=$CC + make -j$procs test OBJS= TARGETS= EXTRA_TARGETS= CONFIG=$CC - name: Report errors if: ${{ failure() }} From dfbef2fe24715bb1f8d74a0d10941afad3de3327 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 11 Feb 2026 00:55:36 +0100 Subject: [PATCH 159/291] .github: run unit tests in build jobs, not test jobs --- .github/workflows/test-build.yml | 5 +++-- .github/workflows/test-sanitizers.yml | 4 ---- .github/workflows/test-verific.yml | 5 ----- 3 files changed, 3 insertions(+), 11 deletions(-) diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index a14234925..06eb8187c 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -71,7 +71,8 @@ jobs: mkdir build cd build make -f ../Makefile config-$CC - make -f ../Makefile -j$procs ENABLE_LIBYOSYS=1 + make -f ../Makefile -j$procs + make -f ../Makefile unit-test -j$procs - name: Log yosys-config output run: | @@ -219,7 +220,7 @@ jobs: - name: Run tests shell: bash run: | - make -C docs test -j$procs + make -C docs vanilla-test -j$procs test-docs-build: name: Try build docs diff --git a/.github/workflows/test-sanitizers.yml b/.github/workflows/test-sanitizers.yml index c6b3d8db0..7650470c3 100644 --- a/.github/workflows/test-sanitizers.yml +++ b/.github/workflows/test-sanitizers.yml @@ -73,7 +73,3 @@ jobs: run: | find tests/**/*.err -print -exec cat {} \; - - name: Run unit tests - shell: bash - run: | - make -j$procs unit-test diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml index feba3c0f9..cd2545cc8 100644 --- a/.github/workflows/test-verific.yml +++ b/.github/workflows/test-verific.yml @@ -80,11 +80,6 @@ jobs: run: | make -C sby run_ci - - name: Run unit tests - shell: bash - run: | - make -j$procs unit-test ENABLE_LTO=1 - test-pyosys: needs: pre-job if: ${{ needs.pre-job.outputs.should_skip != 'true' && github.repository == 'YosysHQ/Yosys' }} From 98c3f03497938dc1f314aa6fd8768e3a71eb4eb9 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 11 Feb 2026 00:58:29 +0100 Subject: [PATCH 160/291] docs: clarify vanilla test run-test.sh --- docs/source/yosys_internals/extending_yosys/test_suites.rst | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/docs/source/yosys_internals/extending_yosys/test_suites.rst b/docs/source/yosys_internals/extending_yosys/test_suites.rst index c43dc3a84..d3422b23a 100644 --- a/docs/source/yosys_internals/extending_yosys/test_suites.rst +++ b/docs/source/yosys_internals/extending_yosys/test_suites.rst @@ -27,7 +27,8 @@ which runs a frontend like ``read_verilog`` or ``read_rtlil`` with a relative path or a heredoc, then runs some commands including the command under test, and then uses :doc:`/using_yosys/more_scripting/selections` with ``-assert-count``. Usually it's unnecessary to "register" the test anywhere -as if it's similar to other tests it will be run together with the rest. +as if it's being added to an existing directory, depending +on how the ``run-test.sh`` in that directory works. Unit tests ~~~~~~~~~~ From a6a07fb39c0f3e79aea7b543ffb2e36a04e887b3 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 11 Feb 2026 00:59:12 +0100 Subject: [PATCH 161/291] Dockerfile: remove --- Dockerfile | 58 ------------------------------------------------------ 1 file changed, 58 deletions(-) delete mode 100644 Dockerfile diff --git a/Dockerfile b/Dockerfile deleted file mode 100644 index 9806696e0..000000000 --- a/Dockerfile +++ /dev/null @@ -1,58 +0,0 @@ -ARG IMAGE="python:3-slim-buster" - -#--- - -FROM $IMAGE AS base - -RUN apt-get update -qq \ - && DEBIAN_FRONTEND=noninteractive apt-get -y install --no-install-recommends \ - ca-certificates \ - clang \ - lld \ - curl \ - libffi-dev \ - libreadline-dev \ - tcl-dev \ - graphviz \ - xdot \ - && apt-get autoclean && apt-get clean && apt-get -y autoremove \ - && update-ca-certificates \ - && rm -rf /var/lib/apt/lists - -#--- - -FROM base AS build - -RUN apt-get update -qq \ - && DEBIAN_FRONTEND=noninteractive apt-get -y install --no-install-recommends \ - bison \ - flex \ - gawk \ - gcc \ - git \ - iverilog \ - pkg-config \ - && apt-get autoclean && apt-get clean && apt-get -y autoremove \ - && rm -rf /var/lib/apt/lists - -COPY . /yosys - -ENV PREFIX /opt/yosys - -RUN cd /yosys \ - && make \ - && make install \ - && make test - -#--- - -FROM base - -COPY --from=build /opt/yosys /opt/yosys - -ENV PATH /opt/yosys/bin:$PATH - -RUN useradd -m yosys -USER yosys - -CMD ["yosys"] From 5a46106a46a739fb4a4a164353349e6fb3077221 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 11 Feb 2026 01:04:50 +0100 Subject: [PATCH 162/291] abc9: remove -liberty --- passes/techmap/abc9.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 8b61a9299..138fa0aee 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -221,7 +221,7 @@ struct Abc9Pass : public ScriptPass if ((arg == "-exe" || arg == "-script" || arg == "-D" || /*arg == "-S" ||*/ arg == "-lut" || arg == "-luts" || /*arg == "-box" ||*/ arg == "-W" || arg == "-genlib" || - arg == "-constr" || arg == "-dont_use" || arg == "-liberty") && + arg == "-constr" || arg == "-dont_use") && argidx+1 < args.size()) { if (arg == "-lut" || arg == "-luts") lut_mode = true; From fe613f29b90337e1251ed2e038b78a4c299f967d Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 11 Feb 2026 11:33:27 +0100 Subject: [PATCH 163/291] .github: move gtest to build dependencies --- .github/actions/setup-build-env/action.yml | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/.github/actions/setup-build-env/action.yml b/.github/actions/setup-build-env/action.yml index 60fe481e7..3c5465a9b 100644 --- a/.github/actions/setup-build-env/action.yml +++ b/.github/actions/setup-build-env/action.yml @@ -42,7 +42,7 @@ runs: if: runner.os == 'Linux' && inputs.get-build-deps == 'true' uses: awalsh128/cache-apt-pkgs-action@v1.6.0 with: - packages: bison clang flex libffi-dev libfl-dev libreadline-dev pkg-config tcl-dev zlib1g-dev + packages: bison clang flex libffi-dev libfl-dev libreadline-dev pkg-config tcl-dev zlib1g-dev libgtest-dev version: ${{ inputs.runs-on }}-buildys - name: Linux docs dependencies @@ -54,12 +54,12 @@ runs: # if updating test dependencies, make sure to update # docs/source/yosys_internals/extending_yosys/test_suites.rst to match. - - name: Linux test dependencies - if: runner.os == 'Linux' && inputs.get-test-deps == 'true' - uses: awalsh128/cache-apt-pkgs-action@v1.6.0 - with: - packages: libgtest-dev - version: ${{ inputs.runs-on }}-testys + # - name: Linux test dependencies + # if: runner.os == 'Linux' && inputs.get-test-deps == 'true' + # uses: awalsh128/cache-apt-pkgs-action@v1.6.0 + # with: + # packages: + # version: ${{ inputs.runs-on }}-testys - name: Install macOS Dependencies if: runner.os == 'macOS' From c4094e457b5013d64c60342444c7cd204382c3c7 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 11 Feb 2026 11:34:54 +0100 Subject: [PATCH 164/291] abc9: remove -genlib, -constr --- passes/techmap/abc9.cc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 138fa0aee..7ed94617e 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -219,9 +219,8 @@ struct Abc9Pass : public ScriptPass for (argidx = 1; argidx < args.size(); argidx++) { std::string arg = args[argidx]; if ((arg == "-exe" || arg == "-script" || arg == "-D" || - /*arg == "-S" ||*/ arg == "-lut" || arg == "-luts" || - /*arg == "-box" ||*/ arg == "-W" || arg == "-genlib" || - arg == "-constr" || arg == "-dont_use") && + arg == "-lut" || arg == "-luts" || + arg == "-W" || arg == "-dont_use") && argidx+1 < args.size()) { if (arg == "-lut" || arg == "-luts") lut_mode = true; From 915912cc761cb5b059bcb823df1646424cf3b42a Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 11 Feb 2026 11:39:09 +0100 Subject: [PATCH 165/291] abc9: remove -dont_use --- passes/techmap/abc9.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 7ed94617e..16df82bb6 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -219,8 +219,7 @@ struct Abc9Pass : public ScriptPass for (argidx = 1; argidx < args.size(); argidx++) { std::string arg = args[argidx]; if ((arg == "-exe" || arg == "-script" || arg == "-D" || - arg == "-lut" || arg == "-luts" || - arg == "-W" || arg == "-dont_use") && + arg == "-lut" || arg == "-luts" || arg == "-W") && argidx+1 < args.size()) { if (arg == "-lut" || arg == "-luts") lut_mode = true; From 3f1fbfdaee9049c0c274e73032e09266d6a36525 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 11 Feb 2026 12:16:02 +0100 Subject: [PATCH 166/291] blifparse: add bounds check --- frontends/blif/blifparse.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index 30512d324..350d7cafe 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -629,6 +629,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool goto try_next_value; } } + log_assert(i < lutptr->size()); lutptr->set(i, !strcmp(output, "0") ? RTLIL::State::S0 : RTLIL::State::S1); try_next_value:; } From 43a15113ff41f5a7ae40a70ca66a93e8b864f9f3 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 11 Feb 2026 12:07:41 +0100 Subject: [PATCH 167/291] aigerparse: add some bounds checks --- frontends/aiger/aigerparse.cc | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 4df37c0cd..a27a23e79 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -286,10 +286,15 @@ end_of_header: RTLIL::IdString escaped_s = stringf("\\%s", s); RTLIL::Wire* wire; - if (c == 'i') wire = inputs[l1]; - else if (c == 'l') wire = latches[l1]; - else if (c == 'o') { + if (c == 'i') { + log_assert(l1 < inputs.size()); + wire = inputs[l1]; + } else if (c == 'l') { + log_assert(l1 < latches.size()); + wire = latches[l1]; + } else if (c == 'o') { wire = module->wire(escaped_s); + log_assert(l1 < outputs.size()); if (wire) { // Could have been renamed by a latch module->swap_names(wire, outputs[l1]); @@ -297,9 +302,9 @@ end_of_header: goto next; } wire = outputs[l1]; - } - else if (c == 'b') wire = bad_properties[l1]; - else log_abort(); + } else if (c == 'b') { + wire = bad_properties[l1]; + } else log_abort(); module->rename(wire, escaped_s); } From 2e03ee143478533968716478886634f610219f3a Mon Sep 17 00:00:00 2001 From: Lofty Date: Wed, 11 Feb 2026 11:46:17 +0000 Subject: [PATCH 168/291] aigerparse: sanity-check AIGER header --- frontends/aiger/aigerparse.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index a27a23e79..e55349aa7 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -657,6 +657,9 @@ void AigerReader::parse_aiger_binary() unsigned l1, l2, l3; std::string line; + if (M != I + L + A) + log_error("Binary AIGER input is malformed: maximum variable index M is %u, but number of inputs, latches and AND gates adds up to %u.\n", M, I + L + A); + // Parse inputs int digits = decimal_digits(I); for (unsigned i = 1; i <= I; ++i) { From 12ace45b89035e128ba41b10938ed2665ae30c2a Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Wed, 22 Jun 2022 10:57:46 -0700 Subject: [PATCH 169/291] Support param. default values in JSON FE and SV BE --- abc | 2 +- backends/verilog/verilog_backend.cc | 11 +++++++++++ frontends/json/jsonparse.cc | 3 +++ 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/abc b/abc index 734f64d5b..799ba6322 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit 734f64d5b907158dc4337ee82b3b74566d74ba08 +Subproject commit 799ba632239b2a4db2bacda81de4e6efdc486b0c diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 3d451117c..b3029b051 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -421,6 +421,14 @@ void dump_attributes(std::ostream &f, std::string indent, dictattributes, "\n", /*modattr=*/false, /*regattr=*/reg_wires.count(wire->name)); @@ -2438,6 +2446,9 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) f << indent + " " << "reg " << id(initial_id) << " = 0;\n"; } + for (auto p : module->parameter_default_values) + dump_parameter(f, indent + " ", p.first, p.second); + // first dump input / output according to their order in module->ports for (auto port : module->ports) dump_wire(f, indent + " ", module->wire(port)); diff --git a/frontends/json/jsonparse.cc b/frontends/json/jsonparse.cc index 743ac5d9e..803931f32 100644 --- a/frontends/json/jsonparse.cc +++ b/frontends/json/jsonparse.cc @@ -302,6 +302,9 @@ void json_import(Design *design, string &modname, JsonNode *node) if (node->data_dict.count("attributes")) json_parse_attr_param(module->attributes, node->data_dict.at("attributes")); + if (node->data_dict.count("parameter_default_values")) + json_parse_attr_param(module->parameter_default_values, node->data_dict.at("parameter_default_values")); + dict signal_bits; if (node->data_dict.count("ports")) From 9ad7aed4a53e3467a89808544a2ac8701c6a5c9f Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Tue, 6 Jan 2026 09:37:13 -0800 Subject: [PATCH 170/291] Update backends/verilog/verilog_backend.cc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Marcelina Kościelnicka <236399+mwkmwkmwk@users.noreply.github.com> --- backends/verilog/verilog_backend.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index b3029b051..6284cdf33 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -426,7 +426,7 @@ void dump_parameter(std::ostream &f, std::string indent, RTLIL::IdString id_stri f << stringf("%sparameter %s", indent.c_str(), id(id_string).c_str()); f << stringf(" = "); dump_const(f, parameter); - f << stringf(";\n"); + f << ";\n"; } void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire) From 1ede98797f7eee220cba4fad695e41cdec05684e Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Tue, 6 Jan 2026 09:37:21 -0800 Subject: [PATCH 171/291] Update backends/verilog/verilog_backend.cc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Marcelina Kościelnicka <236399+mwkmwkmwk@users.noreply.github.com> --- backends/verilog/verilog_backend.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 6284cdf33..13f6acec4 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -423,8 +423,7 @@ void dump_attributes(std::ostream &f, std::string indent, dict Date: Tue, 6 Jan 2026 10:38:03 -0800 Subject: [PATCH 172/291] Add tests --- tests/various/json_param_defaults.v | 10 ++++++++++ tests/various/json_param_defaults.ys | 8 ++++++++ 2 files changed, 18 insertions(+) create mode 100644 tests/various/json_param_defaults.v create mode 100644 tests/various/json_param_defaults.ys diff --git a/tests/various/json_param_defaults.v b/tests/various/json_param_defaults.v new file mode 100644 index 000000000..7d3b94a68 --- /dev/null +++ b/tests/various/json_param_defaults.v @@ -0,0 +1,10 @@ +module json_param_defaults #( + parameter WIDTH = 8, + parameter SIGNED = 1 +) ( + input [WIDTH-1:0] a, + output [WIDTH-1:0] y +); + wire [WIDTH-1:0] y_int = a << SIGNED; + assign y = y_int; +endmodule diff --git a/tests/various/json_param_defaults.ys b/tests/various/json_param_defaults.ys new file mode 100644 index 000000000..2624ab884 --- /dev/null +++ b/tests/various/json_param_defaults.ys @@ -0,0 +1,8 @@ +! mkdir -p temp +read_verilog -sv json_param_defaults.v +write_json temp/json_param_defaults.json +design -reset +read_json temp/json_param_defaults.json +write_verilog -noattr temp/json_param_defaults.v +! grep -qF "parameter WIDTH = 32'd8" temp/json_param_defaults.v +! grep -qF "parameter SIGNED = 32'd1" temp/json_param_defaults.v From be9c857e7252751b77bc1548fdbde0f11906a1e8 Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Wed, 11 Feb 2026 08:12:38 -0800 Subject: [PATCH 173/291] Fix ABC after merge --- abc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/abc b/abc index 799ba6322..734f64d5b 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit 799ba632239b2a4db2bacda81de4e6efdc486b0c +Subproject commit 734f64d5b907158dc4337ee82b3b74566d74ba08 From a13b5c421108fd1dfe6cd1aff0070777a31c2ec5 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 11 Feb 2026 17:30:08 +0100 Subject: [PATCH 174/291] Update ABC as per 2026-02-11 --- abc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/abc b/abc index 734f64d5b..c18b835ef 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit 734f64d5b907158dc4337ee82b3b74566d74ba08 +Subproject commit c18b835ef140217c84a26ba510f98f69d54dd48e From 7a0774c3bb200d8b5d3278c7c69f9e5d893af43c Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Wed, 11 Feb 2026 08:33:39 -0800 Subject: [PATCH 175/291] Don't dump params by default --- backends/verilog/verilog_backend.cc | 17 ++++++++++++++--- tests/various/json_param_defaults.ys | 2 +- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 13f6acec4..73ffcbf3e 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -95,7 +95,8 @@ bool VERILOG_BACKEND::id_is_verilog_escaped(const std::string &str) { PRIVATE_NAMESPACE_BEGIN -bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, extmem, defparam, decimal, siminit, systemverilog, simple_lhs, noparallelcase; +bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, extmem, defparam, decimal, siminit, systemverilog, simple_lhs, + noparallelcase, default_params; int auto_name_counter, auto_name_offset, auto_name_digits, extmem_counter; dict auto_name_map; std::set reg_wires; @@ -2445,8 +2446,9 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) f << indent + " " << "reg " << id(initial_id) << " = 0;\n"; } - for (auto p : module->parameter_default_values) - dump_parameter(f, indent + " ", p.first, p.second); + if (default_params) + for (auto p : module->parameter_default_values) + dump_parameter(f, indent + " ", p.first, p.second); // first dump input / output according to their order in module->ports for (auto port : module->ports) @@ -2555,6 +2557,10 @@ struct VerilogBackend : public Backend { log(" use 'defparam' statements instead of the Verilog-2001 syntax for\n"); log(" cell parameters.\n"); log("\n"); + log(" -default_params\n"); + log(" emit module parameter declarations from\n"); + log(" parameter_default_values.\n"); + log("\n"); log(" -blackboxes\n"); log(" usually modules with the 'blackbox' attribute are ignored. with\n"); log(" this option set only the modules with the 'blackbox' attribute\n"); @@ -2592,6 +2598,7 @@ struct VerilogBackend : public Backend { siminit = false; simple_lhs = false; noparallelcase = false; + default_params = false; auto_prefix = ""; bool blackboxes = false; @@ -2652,6 +2659,10 @@ struct VerilogBackend : public Backend { defparam = true; continue; } + if (arg == "-defaultparams") { + default_params = true; + continue; + } if (arg == "-decimal") { decimal = true; continue; diff --git a/tests/various/json_param_defaults.ys b/tests/various/json_param_defaults.ys index 2624ab884..45e312de2 100644 --- a/tests/various/json_param_defaults.ys +++ b/tests/various/json_param_defaults.ys @@ -3,6 +3,6 @@ read_verilog -sv json_param_defaults.v write_json temp/json_param_defaults.json design -reset read_json temp/json_param_defaults.json -write_verilog -noattr temp/json_param_defaults.v +write_verilog -noattr -defaultparams temp/json_param_defaults.v ! grep -qF "parameter WIDTH = 32'd8" temp/json_param_defaults.v ! grep -qF "parameter SIGNED = 32'd1" temp/json_param_defaults.v From 1319112913c48983b8bbfb000f43b2715e148b7d Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Thu, 12 Feb 2026 00:32:36 +0000 Subject: [PATCH 176/291] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 5bf66c1a9..02fe61004 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.62+14 +YOSYS_VER := 0.62+39 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 5ea073d45e3988d6115616f56a82547b5befea7d Mon Sep 17 00:00:00 2001 From: Maxim Kudinov Date: Tue, 3 Feb 2026 19:04:31 +0300 Subject: [PATCH 177/291] gowin: format MULT instances --- techlibs/gowin/dsp_map.v | 76 ++++++++++++++++++++-------------------- 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/techlibs/gowin/dsp_map.v b/techlibs/gowin/dsp_map.v index dfde0b6a1..f03bcdff0 100644 --- a/techlibs/gowin/dsp_map.v +++ b/techlibs/gowin/dsp_map.v @@ -6,20 +6,20 @@ module \$__MUL9X9 (input [8:0] A, input [8:0] B, output [17:0] Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; - MULT9X9 __TECHMAP_REPLACE__ ( - .CLK(1'b0), - .CE(1'b0), - .RESET(1'b0), - .A(A), - .SIA({A_WIDTH{1'b0}}), - .ASEL(1'b0), - .ASIGN(A_SIGNED ? 1'b1 : 1'b0), - .B(B), - .SIB({B_WIDTH{1'b0}}), - .BSEL(1'b0), - .BSIGN(B_SIGNED ? 1'b1 : 1'b0), - .DOUT(Y) - ); + MULT9X9 __TECHMAP_REPLACE__ ( + .CLK(1'b0), + .CE(1'b0), + .RESET(1'b0), + .A(A), + .SIA({A_WIDTH{1'b0}}), + .ASEL(1'b0), + .ASIGN(A_SIGNED ? 1'b1 : 1'b0), + .B(B), + .SIB({B_WIDTH{1'b0}}), + .BSEL(1'b0), + .BSIGN(B_SIGNED ? 1'b1 : 1'b0), + .DOUT(Y) + ); endmodule @@ -31,20 +31,20 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; - MULT18X18 __TECHMAP_REPLACE__ ( - .CLK(1'b0), - .CE(1'b0), - .RESET(1'b0), - .A(A), - .SIA({A_WIDTH{1'b0}}), - .ASEL(1'b0), - .ASIGN(A_SIGNED ? 1'b1 : 1'b0), - .B(B), - .SIB({B_WIDTH{1'b0}}), - .BSEL(1'b0), - .BSIGN(B_SIGNED ? 1'b1 : 1'b0), - .DOUT(Y) - ); + MULT18X18 __TECHMAP_REPLACE__ ( + .CLK(1'b0), + .CE(1'b0), + .RESET(1'b0), + .A(A), + .SIA({A_WIDTH{1'b0}}), + .ASEL(1'b0), + .ASIGN(A_SIGNED ? 1'b1 : 1'b0), + .B(B), + .SIB({B_WIDTH{1'b0}}), + .BSEL(1'b0), + .BSIGN(B_SIGNED ? 1'b1 : 1'b0), + .DOUT(Y) + ); endmodule @@ -56,15 +56,15 @@ module \$__MUL36X36 (input [35:0] A, input [35:0] B, output [71:0] Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; - MULT36X36 __TECHMAP_REPLACE__ ( - .CLK(1'b0), - .RESET(1'b0), - .CE(1'b0), - .A(A), - .ASIGN(A_SIGNED ? 1'b1 : 1'b0), - .B(B), - .BSIGN(B_SIGNED ? 1'b1 : 1'b0), - .DOUT(Y) - ); + MULT36X36 __TECHMAP_REPLACE__ ( + .CLK(1'b0), + .RESET(1'b0), + .CE(1'b0), + .A(A), + .ASIGN(A_SIGNED ? 1'b1 : 1'b0), + .B(B), + .BSIGN(B_SIGNED ? 1'b1 : 1'b0), + .DOUT(Y) + ); endmodule From 542b29fa6a1fe52631d15b7c29632d7532f0acd9 Mon Sep 17 00:00:00 2001 From: Maxim Kudinov Date: Tue, 3 Feb 2026 19:55:47 +0300 Subject: [PATCH 178/291] gowin: synth_gowin: Merge flatten label with coarse --- techlibs/gowin/synth_gowin.cc | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 9cc213945..2bf21cbc9 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -254,17 +254,13 @@ struct SynthGowinPass : public ScriptPass run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt)); } - if (flatten && check_label("flatten", "(unless -noflatten)")) - { - run("proc"); - run("flatten"); - run("tribuf -logic"); - run("deminout"); - } - if (check_label("coarse")) { run("proc"); + if (flatten || help_mode) + run("flatten", "(unless -noflatten)"); + run("tribuf -logic"); + run("deminout"); run("opt_expr"); run("opt_clean"); run("check"); From 5b94a97fb37787aa34a4808abd3df9de0842583b Mon Sep 17 00:00:00 2001 From: Maxim Kudinov Date: Thu, 12 Feb 2026 13:57:34 +0300 Subject: [PATCH 179/291] gowin: synth_gowin: Add -nodsp option --- techlibs/gowin/synth_gowin.cc | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 2bf21cbc9..cdc7d20f0 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -112,13 +112,16 @@ struct SynthGowinPass : public ScriptPass log(" -setundef\n"); log(" set undriven wires and parameters to zero\n"); log("\n"); + log(" -nodsp\n"); + log(" do not infer DSP multipliers\n"); + log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } string top_opt, vout_file, json_file, family; - bool retime, nobram, nolutram, flatten, nodffe, strict_gw5a_dffs, nowidelut, abc9, noiopads, noalu, no_rw_check, setundef; + bool retime, nobram, nolutram, flatten, nodffe, strict_gw5a_dffs, nowidelut, abc9, noiopads, noalu, no_rw_check, setundef, nodsp; void clear_flags() override { @@ -138,6 +141,7 @@ struct SynthGowinPass : public ScriptPass noalu = false; no_rw_check = false; setundef = false; + nodsp = false; } void execute(std::vector args, RTLIL::Design *design) override @@ -224,6 +228,10 @@ struct SynthGowinPass : public ScriptPass setundef = true; continue; } + if (args[argidx] == "-nodsp") { + nodsp = true; + continue; + } break; } extra_args(args, argidx, design); @@ -273,9 +281,9 @@ struct SynthGowinPass : public ScriptPass run("share"); if (help_mode) { - run("techmap -map +/mul2dsp.v [...]", "(if -family gw1n or gw2a)"); - run("techmap -map +/gowin/dsp_map.v", "(if -family gw1n or gw2a)"); - } else if (family == "gw1n" || family == "gw2a") { + run("techmap -map +/mul2dsp.v [...]", "(unless -nodsp and if -family gw1n or gw2a)"); + run("techmap -map +/gowin/dsp_map.v", "(unless -nodsp and if -family gw1n or gw2a)"); + } else if (!nodsp && (family == "gw1n" || family == "gw2a")) { for (const auto &rule : dsp_rules) { run(stringf("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=%d -D DSP_B_MAXWIDTH=%d -D DSP_A_MINWIDTH=%d -D DSP_B_MINWIDTH=%d -D DSP_NAME=%s", rule.a_maxwidth, rule.b_maxwidth, rule.a_minwidth, rule.b_minwidth, rule.prim)); From b055ea05fd314a6a928f0c2e3f777d6e8bf5f7d8 Mon Sep 17 00:00:00 2001 From: Maxim Kudinov Date: Thu, 12 Feb 2026 14:12:32 +0300 Subject: [PATCH 180/291] gowin: dsp: Add mult inference tests --- tests/arch/gowin/mul_gw1n.ys | 53 ++++++++++++++++++++++++++++++++++++ tests/arch/gowin/mul_gw2a.ys | 53 ++++++++++++++++++++++++++++++++++++ 2 files changed, 106 insertions(+) create mode 100644 tests/arch/gowin/mul_gw1n.ys create mode 100644 tests/arch/gowin/mul_gw2a.ys diff --git a/tests/arch/gowin/mul_gw1n.ys b/tests/arch/gowin/mul_gw1n.ys new file mode 100644 index 000000000..9b1748255 --- /dev/null +++ b/tests/arch/gowin/mul_gw1n.ys @@ -0,0 +1,53 @@ +read_verilog ../common/mul.v +chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16 +hierarchy -top top +proc +# equivalence checking is somewhat slow (and missing simulation models) +synth_gowin -family gw1n +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT9X9 + + +# Make sure that DSPs are not inferred with -nodsp option +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16 +hierarchy -top top +proc +synth_gowin -family gw1n -nodsp +cd top # Constrain all select calls below inside the top module +select -assert-none t:MULT9X9 + + +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 16 -set Y_WIDTH 16 -set A_WIDTH 32 +hierarchy -top top +proc +synth_gowin -family gw1n +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT18X18 + + +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 32 -set Y_WIDTH 32 -set A_WIDTH 64 +hierarchy -top top +proc +# equivalence checking is too slow here +synth_gowin +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT36X36 + + +# We end up with two 18x18 multipliers +# 36x36 min width is 22 +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 32 -set Y_WIDTH 16 -set A_WIDTH 48 +hierarchy -top top +proc +# equivalence checking is too slow here +synth_gowin +cd top # Constrain all select calls below inside the top module +select -assert-count 2 t:MULT18X18 diff --git a/tests/arch/gowin/mul_gw2a.ys b/tests/arch/gowin/mul_gw2a.ys new file mode 100644 index 000000000..895c580b7 --- /dev/null +++ b/tests/arch/gowin/mul_gw2a.ys @@ -0,0 +1,53 @@ +read_verilog ../common/mul.v +chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16 +hierarchy -top top +proc +# equivalence checking is somewhat slow (and missing simulation models) +synth_gowin -family gw2a +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT9X9 + + +# Make sure that DSPs are not inferred with -nodsp option +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16 +hierarchy -top top +proc +synth_gowin -family gw2a -nodsp +cd top # Constrain all select calls below inside the top module +select -assert-none t:MULT9X9 + + +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 16 -set Y_WIDTH 16 -set A_WIDTH 32 +hierarchy -top top +proc +synth_gowin -family gw2a +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT18X18 + + +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 32 -set Y_WIDTH 32 -set A_WIDTH 64 +hierarchy -top top +proc +# equivalence checking is too slow here +synth_gowin -family gw2a +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT36X36 + + +# We end up with two 18x18 multipliers +# 36x36 min width is 22 +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 32 -set Y_WIDTH 16 -set A_WIDTH 48 +hierarchy -top top +proc +# equivalence checking is too slow here +synth_gowin -family gw2a +cd top # Constrain all select calls below inside the top module +select -assert-count 2 t:MULT18X18 From cc79c6a76173622aa75d1d8c1f2c206b601e24c2 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 12 Feb 2026 12:17:07 +0100 Subject: [PATCH 181/291] Support building out of tree, but keep always in tests/unit --- Makefile | 4 ++-- tests/unit/Makefile | 9 +++++---- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/Makefile b/Makefile index 7ce3153df..f20e63078 100644 --- a/Makefile +++ b/Makefile @@ -1013,11 +1013,11 @@ ystests: $(TARGETS) $(EXTRA_TARGETS) # Unit test unit-test: libyosys.so - @$(MAKE) -C $(UNITESTPATH) CXX="$(CXX)" CC="$(CC)" CPPFLAGS="$(CPPFLAGS)" \ + @$(MAKE) -f $(UNITESTPATH)/Makefile CXX="$(CXX)" CC="$(CC)" CPPFLAGS="$(CPPFLAGS)" \ CXXFLAGS="$(CXXFLAGS)" LINKFLAGS="$(LINKFLAGS)" LIBS="$(LIBS)" ROOTPATH="$(CURDIR)" clean-unit-test: - @$(MAKE) -C $(UNITESTPATH) clean + @$(MAKE) -f $(UNITESTPATH)/Makefile clean install-dev: $(PROGRAM_PREFIX)yosys-config share $(INSTALL_SUDO) mkdir -p $(DESTDIR)$(BINDIR) diff --git a/tests/unit/Makefile b/tests/unit/Makefile index b275d7f41..e8f76cba9 100644 --- a/tests/unit/Makefile +++ b/tests/unit/Makefile @@ -18,10 +18,11 @@ endif EXTRAFLAGS := -lyosys -pthread -OBJTEST := objtest -BINTEST := bintest +MAKEFILE_DIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST)))) +OBJTEST := $(MAKEFILE_DIR)objtest +BINTEST := $(MAKEFILE_DIR)bintest -ALLTESTFILE := $(shell find . -name '*Test.cc' | sed 's|^\./||' | tr '\n' ' ') +ALLTESTFILE := $(shell cd $(MAKEFILE_DIR) && find . -name '*Test.cc' | sed 's|^\./||' | tr '\n' ' ') TESTDIRS := $(sort $(dir $(ALLTESTFILE))) TESTS := $(addprefix $(BINTEST)/, $(basename $(ALLTESTFILE:%Test.cc=%Test.o))) @@ -34,7 +35,7 @@ $(BINTEST)/%: $(OBJTEST)/%.o | prepare $(CXX) -L$(ROOTPATH) $(RPATH) $(LINKFLAGS) -o $@ $^ $(LIBS) \ $(GTEST_LDFLAGS) $(EXTRAFLAGS) -$(OBJTEST)/%.o: $(basename $(subst $(OBJTEST),.,%)).cc | prepare +$(OBJTEST)/%.o: $(MAKEFILE_DIR)/%.cc | prepare $(CXX) -o $@ -c -I$(ROOTPATH) $(CPPFLAGS) $(CXXFLAGS) $(GTEST_CXXFLAGS) $^ .PHONY: prepare run-tests clean From c6e48f4bea903c08a99b4f5f6b91f30652155786 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 12 Feb 2026 14:06:08 +0100 Subject: [PATCH 182/291] These are tests from other Makefile --- .github/workflows/test-build.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index 06eb8187c..2a870cd29 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -220,7 +220,7 @@ jobs: - name: Run tests shell: bash run: | - make -C docs vanilla-test -j$procs + make -C docs test -j$procs test-docs-build: name: Try build docs From e5b3e9fc1f43c3c3e09ae0d4b143528a213cb1c9 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 12 Feb 2026 14:08:49 +0100 Subject: [PATCH 183/291] This one should run only vanilla-tests --- .github/workflows/test-build.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index 2a870cd29..4f14e149c 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -132,7 +132,7 @@ jobs: - name: Run tests shell: bash run: | - make -j$procs test OBJS= TARGETS= EXTRA_TARGETS= CONFIG=$CC + make -j$procs vanilla-test OBJS= TARGETS= EXTRA_TARGETS= CONFIG=$CC - name: Report errors if: ${{ failure() }} From bb7aa7d208921fd8c1f438335822d661fe8e01ad Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 12 Feb 2026 14:56:45 +0100 Subject: [PATCH 184/291] Cleanup of yml files --- .github/actions/setup-build-env/action.yml | 9 --------- .github/workflows/test-build.yml | 2 +- 2 files changed, 1 insertion(+), 10 deletions(-) diff --git a/.github/actions/setup-build-env/action.yml b/.github/actions/setup-build-env/action.yml index 3c5465a9b..c9dc5fc22 100644 --- a/.github/actions/setup-build-env/action.yml +++ b/.github/actions/setup-build-env/action.yml @@ -52,15 +52,6 @@ runs: packages: graphviz xdot version: ${{ inputs.runs-on }}-docsys - # if updating test dependencies, make sure to update - # docs/source/yosys_internals/extending_yosys/test_suites.rst to match. - # - name: Linux test dependencies - # if: runner.os == 'Linux' && inputs.get-test-deps == 'true' - # uses: awalsh128/cache-apt-pkgs-action@v1.6.0 - # with: - # packages: - # version: ${{ inputs.runs-on }}-testys - - name: Install macOS Dependencies if: runner.os == 'macOS' shell: bash diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index 4f14e149c..ebdeb15d8 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -132,7 +132,7 @@ jobs: - name: Run tests shell: bash run: | - make -j$procs vanilla-test OBJS= TARGETS= EXTRA_TARGETS= CONFIG=$CC + make -j$procs vanilla-test TARGETS= EXTRA_TARGETS= CONFIG=$CC - name: Report errors if: ${{ failure() }} From e2f0c4d9a04dcc2b2e5667471635073db6102517 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Fri, 13 Feb 2026 00:35:27 +0000 Subject: [PATCH 185/291] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 02fe61004..0f76cdbef 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.62+39 +YOSYS_VER := 0.62+55 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 1e852cef16f98692a8a284194ffe52bec06c7166 Mon Sep 17 00:00:00 2001 From: Chris Hathhorn Date: Thu, 12 Feb 2026 21:51:38 -0600 Subject: [PATCH 186/291] Fix segfault from shift with 0-width signed arg. Fixes #5684. --- kernel/calc.cc | 2 +- tests/various/const_shift_empty_arg.ys | 49 ++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 1 deletion(-) create mode 100644 tests/various/const_shift_empty_arg.ys diff --git a/kernel/calc.cc b/kernel/calc.cc index 9b0885db9..84ac100ab 100644 --- a/kernel/calc.cc +++ b/kernel/calc.cc @@ -291,7 +291,7 @@ static RTLIL::Const const_shift_worker(const RTLIL::Const &arg1, const RTLIL::Co if (pos < 0) result.set(i, vacant_bits); else if (pos >= BigInteger(GetSize(arg1))) - result.set(i, sign_ext ? arg1.back() : vacant_bits); + result.set(i, sign_ext && !arg1.empty() ? arg1.back() : vacant_bits); else result.set(i, arg1[pos.toInt()]); } diff --git a/tests/various/const_shift_empty_arg.ys b/tests/various/const_shift_empty_arg.ys new file mode 100644 index 000000000..4073e198d --- /dev/null +++ b/tests/various/const_shift_empty_arg.ys @@ -0,0 +1,49 @@ +# Regression test for #5684: const_shift_worker must not crash when arg1 is +# empty. + +read_json << EOF +{ + "modules": { + "sshl": { + "cells": { + "sshlCell": { + "connections": { + "A": [], + "B": [3], + "Y": [1] + }, + "parameters": { + "A_SIGNED": "1", + "A_WIDTH": "0", + "B_SIGNED": "0", + "B_WIDTH": "1", + "Y_WIDTH": "1" + }, + "port_directions": { + "A": "input", + "B": "input", + "Y": "output" + }, + "type": "$sshl" + } + }, + "ports": { + "A": { + "bits": [], + "direction": "input" + }, + "B": { + "bits": [3], + "direction": "input" + }, + "Y": { + "bits": [1], + "direction": "output" + } + } + } + } +} +EOF + +eval -set B 0 -show Y sshl From c7d88ded9424501d9196f84913a6dd31762ecab7 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 13 Feb 2026 14:21:41 +0100 Subject: [PATCH 187/291] Make version bump automatic --- Makefile | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 0f76cdbef..4c37bfb8d 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,17 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.62+55 +YOSYS_VER := 0.62 + +ifneq (, $(shell command -v git 2>/dev/null)) +ifneq (, $(shell git rev-parse --git-dir 2>/dev/null)) + GIT_COMMIT_COUNT := $(shell git rev-list --count $(shell git describe --tags --abbrev=0)..HEAD 2>/dev/null) + ifneq ($(GIT_COMMIT_COUNT),0) + YOSYS_VER := $(YOSYS_VER)+$(GIT_COMMIT_COUNT) + endif +endif +endif + YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) @@ -185,9 +195,6 @@ endif OBJS = kernel/version_$(GIT_REV).o -bumpversion: - sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 7326bb7.. | wc -l`/;" Makefile - ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q) # set ABCEXTERNAL = to use an external ABC instance From adf8b6b0d88aff391255888a48501d8a9a696031 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 13 Feb 2026 14:22:10 +0100 Subject: [PATCH 188/291] Add +post to version if from tarbal --- Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Makefile b/Makefile index 4c37bfb8d..78066b2e0 100644 --- a/Makefile +++ b/Makefile @@ -169,6 +169,8 @@ ifneq (, $(shell git rev-parse --git-dir 2>/dev/null)) ifneq ($(GIT_COMMIT_COUNT),0) YOSYS_VER := $(YOSYS_VER)+$(GIT_COMMIT_COUNT) endif +else + YOSYS_VER := $(YOSYS_VER)+post endif endif From 0090aa96b658de655e10258f7e8b39bae54746fe Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 13 Feb 2026 14:22:33 +0100 Subject: [PATCH 189/291] Remove version bump action --- .github/workflows/version.yml | 34 ---------------------------------- 1 file changed, 34 deletions(-) delete mode 100644 .github/workflows/version.yml diff --git a/.github/workflows/version.yml b/.github/workflows/version.yml deleted file mode 100644 index 78d34db46..000000000 --- a/.github/workflows/version.yml +++ /dev/null @@ -1,34 +0,0 @@ -name: Bump version - -on: - workflow_dispatch: - schedule: - - cron: '0 0 * * *' - -jobs: - bump-version: - if: github.repository == 'YosysHQ/Yosys' - runs-on: ubuntu-latest - steps: - - name: Checkout - uses: actions/checkout@v4 - with: - fetch-depth: 0 - submodules: true - persist-credentials: false - - name: Take last commit - id: log - run: echo "message=$(git log --no-merges -1 --oneline)" >> $GITHUB_OUTPUT - - name: Bump version - if: ${{ !contains(steps.log.outputs.message, 'Bump version') }} - run: | - make bumpversion - git config --local user.email "41898282+github-actions[bot]@users.noreply.github.com" - git config --local user.name "github-actions[bot]" - git add Makefile - git commit -m "Bump version" - - name: Push changes # push the output folder to your repo - if: ${{ !contains(steps.log.outputs.message, 'Bump version') }} - uses: ad-m/github-push-action@master - with: - github_token: ${{ secrets.GITHUB_TOKEN }} From e6e57b33e36256f86697950ba6af803225c8b7e3 Mon Sep 17 00:00:00 2001 From: nella Date: Sun, 15 Feb 2026 09:00:04 +0100 Subject: [PATCH 190/291] document abc --keep-going pdr [sc-220]. --- backends/aiger/aiger.cc | 5 +++ .../more_scripting/model_checking.rst | 36 +++++++++++++++++-- passes/cmds/rename.cc | 11 ++++-- 3 files changed, 46 insertions(+), 6 deletions(-) diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index 95f4c19e2..62c79f60b 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -931,6 +931,11 @@ struct AigerBackend : public Backend { log("\n"); log(" -ywmap \n"); log(" write a map file for conversion to and from yosys witness traces.\n"); + log(" The generated JSON map includes \"asserts\" and \"assumes\" arrays\n"); + log(" containing the hierarchical witness paths of the corresponding\n"); + log(" $assert and $assume cells. This enables downstream tools to map\n"); + log(" AIGER bad-state properties and invariant constraints back to\n"); + log(" individual formal properties by name.\n"); log("\n"); log(" -I, -O, -B, -L\n"); log(" If the design contains no input/output/assert/flip-flop then create one\n"); diff --git a/docs/source/using_yosys/more_scripting/model_checking.rst b/docs/source/using_yosys/more_scripting/model_checking.rst index 799c99b6f..da9193a6f 100644 --- a/docs/source/using_yosys/more_scripting/model_checking.rst +++ b/docs/source/using_yosys/more_scripting/model_checking.rst @@ -3,9 +3,9 @@ Symbolic model checking .. todo:: check text context -.. note:: - - While it is possible to perform model checking directly in Yosys, it +.. note:: + + While it is possible to perform model checking directly in Yosys, it is highly recommended to use SBY or EQY for formal hardware verification. Symbolic Model Checking (SMC) is used to formally prove that a circuit has (or @@ -117,3 +117,33 @@ Result with fixed :file:`axis_master.v`: Solving problem with 159144 variables and 441626 clauses.. SAT proof finished - no model found: SUCCESS! + +Witness framework and per-property tracking +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +When using AIGER-based formal verification flows (such as the ``abc`` engine in +SymbiYosys), Yosys provides infrastructure for tracking individual formal +properties through the verification pipeline. + +The ``rename -witness`` pass (run automatically by ``prep``) assigns public +names to all cells that participate in the witness framework: + +- Witness signal cells: ``$anyconst``, ``$anyseq``, ``$anyinit``, + ``$allconst``, ``$allseq`` +- Formal property cells: ``$assert``, ``$assume``, ``$cover``, ``$live``, + ``$fair``, ``$check`` + +These public names allow downstream tools to refer to individual properties by +their hierarchical path rather than by anonymous internal identifiers. + +The ``write_aiger -ywmap`` option generates a JSON map file that includes, among +other things, ``"asserts"`` and ``"assumes"`` arrays. Each entry contains the +hierarchical witness path of the corresponding ``$assert`` or ``$assume`` cell. +This lets tools such as SymbiYosys map AIGER bad-state properties and invariant +constraints back to individual formal properties, enabling features like +per-property pass/fail reporting (e.g. ``abc pdr`` with ``--keep-going`` mode). + +The ``write_smt2`` backend similarly uses the public witness names when emitting +``yosys-smt2-assert`` and ``yosys-smt2-assume`` comments. Cells whose +``hdlname`` attribute contains the ``_witness_`` marker are treated as having +private names for comment purposes, keeping solver output clean. diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index 078ffb769..f87396743 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -263,9 +263,14 @@ struct RenamePass : public Pass { log(" rename -witness\n"); log("\n"); log("Assigns auto-generated names to all $any*/$all* output wires and containing\n"); - log("cells that do not have a public name. This ensures that, during formal\n"); - log("verification, a solver-found trace can be fully specified using a public\n"); - log("hierarchical names.\n"); + log("cells that do not have a public name. Also renames formal property cells\n"); + log("($assert, $assume, $cover, $live, $fair, $check) that have private names,\n"); + log("giving them public witness-trackable names.\n"); + log("\n"); + log("This ensures that, during formal verification, a solver-found trace can be\n"); + log("fully specified using public hierarchical names, and that individual property\n"); + log("results can be tracked by name in flows that support per-property reporting\n"); + log("(e.g. SBY with abc pdr in --keep-going mode).\n"); log("\n"); log("\n"); log(" rename -hide [selection]\n"); From 63068f9b8f1084d859ab35d454eaa3e74fb3e227 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 16 Feb 2026 16:44:33 +0100 Subject: [PATCH 191/291] count relative to version tag, and ignore non existing --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 78066b2e0..9451e1a6c 100644 --- a/Makefile +++ b/Makefile @@ -165,7 +165,7 @@ YOSYS_VER := 0.62 ifneq (, $(shell command -v git 2>/dev/null)) ifneq (, $(shell git rev-parse --git-dir 2>/dev/null)) - GIT_COMMIT_COUNT := $(shell git rev-list --count $(shell git describe --tags --abbrev=0)..HEAD 2>/dev/null) + GIT_COMMIT_COUNT := $(or $(shell git rev-list --count v$(YOSYS_VER)..HEAD 2>/dev/null),0) ifneq ($(GIT_COMMIT_COUNT),0) YOSYS_VER := $(YOSYS_VER)+$(GIT_COMMIT_COUNT) endif From 81ea922512a5ce7e6fdba1f4ff0c23ce4c3b743a Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 16 Feb 2026 16:54:26 +0100 Subject: [PATCH 192/291] sat: use the same cell import warnings as equiv --- passes/sat/sat.cc | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index ffebdd01c..c143e938e 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -27,6 +27,7 @@ #include "kernel/satgen.h" #include "kernel/yosys.h" #include "kernel/log_help.h" +#include "passes/equiv/equiv.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -227,16 +228,12 @@ struct SatHelper int import_cell_counter = 0; for (auto cell : module->cells()) if (design->selected(module, cell)) { - // log("Import cell: %s\n", RTLIL::id2cstr(cell->name)); if (satgen.importCell(cell, timestep)) { for (auto &p : cell->connections()) if (ct.cell_output(cell->type, p.first)) show_drivers.insert(sigmap(p.second), cell); import_cell_counter++; - } else if (ignore_unknown_cells) - log_warning("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); - else - log_error("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); + } else report_missing_model(ignore_unknown_cells, cell); } log("Imported %d cells to SAT database.\n", import_cell_counter); From 77f64de9979e957452be2a4f2f428f0607791b63 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 16 Feb 2026 17:01:09 +0100 Subject: [PATCH 193/291] satgen: move report_missing_model here from equiv.h --- kernel/satgen.cc | 20 ++++++++++++++++++++ kernel/satgen.h | 2 ++ passes/equiv/equiv.h | 15 --------------- passes/sat/sat.cc | 1 - 4 files changed, 22 insertions(+), 16 deletions(-) diff --git a/kernel/satgen.cc b/kernel/satgen.cc index b8b850bb3..7fbcba1b2 100644 --- a/kernel/satgen.cc +++ b/kernel/satgen.cc @@ -19,6 +19,7 @@ #include "kernel/satgen.h" #include "kernel/ff.h" +#include "kernel/yosys_common.h" USING_YOSYS_NAMESPACE @@ -1387,3 +1388,22 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) // .. and all sequential cells with asynchronous inputs return false; } + +namespace Yosys { + +void report_missing_model(bool warn_only, RTLIL::Cell* cell) +{ + std::string s; + if (cell->is_builtin_ff()) + s = stringf("No SAT model available for async FF cell %s (%s). Consider running `async2sync` or `clk2fflogic` first.\n", log_id(cell), log_id(cell->type)); + else + s = stringf("No SAT model available for cell %s (%s).\n", log_id(cell), log_id(cell->type)); + + if (warn_only) { + log_formatted_warning_noprefix(s); + } else { + log_formatted_error(s); + } +} + +} diff --git a/kernel/satgen.h b/kernel/satgen.h index 7815847b3..9ad940585 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -292,6 +292,8 @@ struct SatGen bool importCell(RTLIL::Cell *cell, int timestep = -1); }; +void report_missing_model(bool warn_only, RTLIL::Cell* cell); + YOSYS_NAMESPACE_END #endif diff --git a/passes/equiv/equiv.h b/passes/equiv/equiv.h index 9641e65a7..95d4b25e9 100644 --- a/passes/equiv/equiv.h +++ b/passes/equiv/equiv.h @@ -8,21 +8,6 @@ YOSYS_NAMESPACE_BEGIN -static void report_missing_model(bool warn_only, RTLIL::Cell* cell) -{ - std::string s; - if (cell->is_builtin_ff()) - s = stringf("No SAT model available for async FF cell %s (%s). Consider running `async2sync` or `clk2fflogic` first.\n", log_id(cell), log_id(cell->type)); - else - s = stringf("No SAT model available for cell %s (%s).\n", log_id(cell), log_id(cell->type)); - - if (warn_only) { - log_formatted_warning_noprefix(s); - } else { - log_formatted_error(s); - } -} - struct EquivBasicConfig { bool model_undef = false; int max_seq = 1; diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index c143e938e..203147172 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -27,7 +27,6 @@ #include "kernel/satgen.h" #include "kernel/yosys.h" #include "kernel/log_help.h" -#include "passes/equiv/equiv.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN From 2b4f481850d7ddc160e34d68e201917e508e25c7 Mon Sep 17 00:00:00 2001 From: nella Date: Wed, 18 Feb 2026 09:24:41 +0100 Subject: [PATCH 194/291] Cleanup docs. --- backends/aiger/aiger.cc | 9 +++---- .../more_scripting/model_checking.rst | 24 +++++++++---------- passes/cmds/rename.cc | 13 ++++------ 3 files changed, 19 insertions(+), 27 deletions(-) diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index 62c79f60b..0c49e84b8 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -930,12 +930,9 @@ struct AigerBackend : public Backend { log(" make indexes zero based, enable using map files with smt solvers.\n"); log("\n"); log(" -ywmap \n"); - log(" write a map file for conversion to and from yosys witness traces.\n"); - log(" The generated JSON map includes \"asserts\" and \"assumes\" arrays\n"); - log(" containing the hierarchical witness paths of the corresponding\n"); - log(" $assert and $assume cells. This enables downstream tools to map\n"); - log(" AIGER bad-state properties and invariant constraints back to\n"); - log(" individual formal properties by name.\n"); + log(" write a map file for conversion to and from yosys witness traces,\n"); + log(" also allows for mapping AIGER bad-state properties and invariant\n"); + log(" constraints back to individual formal properties by name.\n"); log("\n"); log(" -I, -O, -B, -L\n"); log(" If the design contains no input/output/assert/flip-flop then create one\n"); diff --git a/docs/source/using_yosys/more_scripting/model_checking.rst b/docs/source/using_yosys/more_scripting/model_checking.rst index da9193a6f..b418f6aff 100644 --- a/docs/source/using_yosys/more_scripting/model_checking.rst +++ b/docs/source/using_yosys/more_scripting/model_checking.rst @@ -121,29 +121,29 @@ Result with fixed :file:`axis_master.v`: Witness framework and per-property tracking ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -When using AIGER-based formal verification flows (such as the ``abc`` engine in -SymbiYosys), Yosys provides infrastructure for tracking individual formal +When using AIGER-based formal verification flows (such as the `abc` engine in +SBY), Yosys provides infrastructure for tracking individual formal properties through the verification pipeline. -The ``rename -witness`` pass (run automatically by ``prep``) assigns public +The `rename -witness` pass (run automatically by `prep`) assigns public names to all cells that participate in the witness framework: -- Witness signal cells: ``$anyconst``, ``$anyseq``, ``$anyinit``, - ``$allconst``, ``$allseq`` -- Formal property cells: ``$assert``, ``$assume``, ``$cover``, ``$live``, - ``$fair``, ``$check`` +- Witness signal cells: `$anyconst`, `$anyseq`, `$anyinit`, + `$allconst`, `$allseq` +- Formal property cells: `$assert`, `$assume`, `$cover`, `$live`, + `$fair`, `$check` These public names allow downstream tools to refer to individual properties by their hierarchical path rather than by anonymous internal identifiers. -The ``write_aiger -ywmap`` option generates a JSON map file that includes, among +The `write_aiger -ywmap` option generates a JSON map file that includes, among other things, ``"asserts"`` and ``"assumes"`` arrays. Each entry contains the -hierarchical witness path of the corresponding ``$assert`` or ``$assume`` cell. -This lets tools such as SymbiYosys map AIGER bad-state properties and invariant +hierarchical witness path of the corresponding `$assert` or `$assume` cell. +This lets tools such as SBY map AIGER bad-state properties and invariant constraints back to individual formal properties, enabling features like -per-property pass/fail reporting (e.g. ``abc pdr`` with ``--keep-going`` mode). +per-property pass/fail reporting (e.g. `abc pdr` with ``--keep-going`` mode). -The ``write_smt2`` backend similarly uses the public witness names when emitting +The `write_smt2` backend similarly uses the public witness names when emitting ``yosys-smt2-assert`` and ``yosys-smt2-assume`` comments. Cells whose ``hdlname`` attribute contains the ``_witness_`` marker are treated as having private names for comment purposes, keeping solver output clean. diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index f87396743..836dfe5b1 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -262,15 +262,10 @@ struct RenamePass : public Pass { log("\n"); log(" rename -witness\n"); log("\n"); - log("Assigns auto-generated names to all $any*/$all* output wires and containing\n"); - log("cells that do not have a public name. Also renames formal property cells\n"); - log("($assert, $assume, $cover, $live, $fair, $check) that have private names,\n"); - log("giving them public witness-trackable names.\n"); - log("\n"); - log("This ensures that, during formal verification, a solver-found trace can be\n"); - log("fully specified using public hierarchical names, and that individual property\n"); - log("results can be tracked by name in flows that support per-property reporting\n"); - log("(e.g. SBY with abc pdr in --keep-going mode).\n"); + log("Assigns auto-generated names to objects used in formal verification\n"); + log("that do not have a public name. This applies to all formal property\n"); + log("cells ($assert, $assume, $cover, $live, $fair, $check), $any*/$all*\n"); + log("output wires, and their containing cells.\n"); log("\n"); log("\n"); log(" rename -hide [selection]\n"); From 01e89a8f9e8ea16d2bab74f725c19d6348fc5f46 Mon Sep 17 00:00:00 2001 From: nella Date: Wed, 18 Feb 2026 09:29:35 +0100 Subject: [PATCH 195/291] Remove cell mentions. --- .../more_scripting/model_checking.rst | 17 ++++++++--------- passes/cmds/rename.cc | 7 +++---- 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/docs/source/using_yosys/more_scripting/model_checking.rst b/docs/source/using_yosys/more_scripting/model_checking.rst index b418f6aff..02400d5d8 100644 --- a/docs/source/using_yosys/more_scripting/model_checking.rst +++ b/docs/source/using_yosys/more_scripting/model_checking.rst @@ -136,14 +136,13 @@ names to all cells that participate in the witness framework: These public names allow downstream tools to refer to individual properties by their hierarchical path rather than by anonymous internal identifiers. -The `write_aiger -ywmap` option generates a JSON map file that includes, among -other things, ``"asserts"`` and ``"assumes"`` arrays. Each entry contains the -hierarchical witness path of the corresponding `$assert` or `$assume` cell. -This lets tools such as SBY map AIGER bad-state properties and invariant -constraints back to individual formal properties, enabling features like -per-property pass/fail reporting (e.g. `abc pdr` with ``--keep-going`` mode). +The `write_aiger -ywmap` option generates a map file for conversion to and from +Yosys witness traces, and also allows for mapping AIGER bad-state properties and +invariant constraints back to individual formal properties by name. This enables +features like per-property pass/fail reporting (e.g. `abc pdr` with +``--keep-going`` mode). The `write_smt2` backend similarly uses the public witness names when emitting -``yosys-smt2-assert`` and ``yosys-smt2-assume`` comments. Cells whose -``hdlname`` attribute contains the ``_witness_`` marker are treated as having -private names for comment purposes, keeping solver output clean. +SMT2 comments. Cells whose ``hdlname`` attribute contains the ``_witness_`` +marker are treated as having private names for comment purposes, keeping solver +output clean. diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index 836dfe5b1..a07d588c4 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -254,10 +254,9 @@ struct RenamePass : public Pass { log("\n"); log(" rename -enumerate [-pattern ] [selection]\n"); log("\n"); - log("Assign short auto-generated names to all selected wires and cells with private\n"); - log("names. The -pattern option can be used to set the pattern for the new names.\n"); - log("The character %% in the pattern is replaced with a integer number. The default\n"); - log("pattern is '_%%_'.\n"); + log("Assigns auto-generated names to objects used in formal verification\n"); + log("that do not have a public name. This applies to all formal property\n"); + log("cells, $any*/$all* output wires, and their containing cells.\n"); log("\n"); log("\n"); log(" rename -witness\n"); From 62f19cb3a96a3884e83184b994ff3be51eff7221 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 18 Feb 2026 12:20:36 +0100 Subject: [PATCH 196/291] modtools: fix port_del db erase --- kernel/modtools.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/kernel/modtools.h b/kernel/modtools.h index a081c7556..6dd7600e9 100644 --- a/kernel/modtools.h +++ b/kernel/modtools.h @@ -94,8 +94,11 @@ struct ModIndex : public RTLIL::Monitor { for (int i = 0; i < GetSize(sig); i++) { RTLIL::SigBit bit = sigmap(sig[i]); - if (bit.wire) + if (bit.wire) { database[bit].ports.erase(PortInfo(cell, port, i)); + if (!database[bit].is_input && !database[bit].is_output && database[bit].ports.empty()) + database.erase(bit); + } } } From 5bb31485b75587dd6b751f910a899775391cf144 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 18 Feb 2026 13:34:36 +0100 Subject: [PATCH 197/291] Display repo and branch when applicable --- Makefile | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/Makefile b/Makefile index 9451e1a6c..588606e2f 100644 --- a/Makefile +++ b/Makefile @@ -802,9 +802,30 @@ endif $(Q) mkdir -p $(dir $@) $(P) $(CXX) -o $@ -c $(CPPFLAGS) $(CXXFLAGS) $< +YOSYS_REPO := +ifneq (, $(shell command -v git 2>/dev/null)) +ifneq (, $(shell git rev-parse --git-dir 2>/dev/null)) + GIT_REMOTE := $(strip $(shell git config --get remote.origin.url 2>/dev/null | $(AWK) '{print tolower($$0)}')) + ifneq ($(strip $(GIT_REMOTE)),) + YOSYS_REPO := $(strip $(shell echo $(GIT_REMOTE) | $(AWK) -F '[:/]' '{gsub(/\.git$$/, "", $$NF); printf "%s/%s", $$(NF-1), $$NF}')) + endif + ifeq ($(strip $(YOSYS_REPO)),yosyshq/yosys) + YOSYS_REPO := + endif + GIT_BRANCH := $(shell git rev-parse --abbrev-ref HEAD 2>/dev/null) + ifeq ($(filter main HEAD release/v%,$(GIT_BRANCH)),) + YOSYS_REPO := $(YOSYS_REPO) at $(GIT_BRANCH) + endif + YOSYS_REPO := $(strip $(YOSYS_REPO)) +endif +endif + YOSYS_GIT_STR := $(GIT_REV)$(GIT_DIRTY) YOSYS_COMPILER := $(notdir $(CXX)) $(shell $(CXX) --version | tr ' ()' '\n' | grep '^[0-9]' | head -n1) $(filter -f% -m% -O% -DNDEBUG,$(CXXFLAGS)) YOSYS_VER_STR := Yosys $(YOSYS_VER) (git sha1 $(YOSYS_GIT_STR), $(YOSYS_COMPILER)) +ifneq ($(strip $(YOSYS_REPO)),) + YOSYS_VER_STR := $(YOSYS_VER_STR) [$(YOSYS_REPO)] +endif kernel/version_$(GIT_REV).cc: $(YOSYS_SRC)/Makefile $(P) rm -f kernel/version_*.o kernel/version_*.d kernel/version_*.cc From c75d80905a8e8e358e9604cf9823299d103d5dca Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 18 Feb 2026 21:20:13 +0100 Subject: [PATCH 198/291] modtools: fix database sanity on wire name swap --- kernel/modtools.h | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/kernel/modtools.h b/kernel/modtools.h index 6dd7600e9..cf68693bc 100644 --- a/kernel/modtools.h +++ b/kernel/modtools.h @@ -28,6 +28,22 @@ YOSYS_NAMESPACE_BEGIN struct ModIndex : public RTLIL::Monitor { + struct PointerOrderedSigBit : public RTLIL::SigBit { + PointerOrderedSigBit(SigBit s) { + wire = s.wire; + if (wire) + offset = s.offset; + else + data = s.data; + } + inline bool operator<(const RTLIL::SigBit &other) const { + if (wire == other.wire) + return wire ? (offset < other.offset) : (data < other.data); + if (wire != nullptr && other.wire != nullptr) + return wire < other.wire; // look here + return (wire != nullptr) < (other.wire != nullptr); + } + }; struct PortInfo { RTLIL::Cell* cell; RTLIL::IdString port; @@ -77,7 +93,7 @@ struct ModIndex : public RTLIL::Monitor SigMap sigmap; RTLIL::Module *module; - std::map database; + std::map database; int auto_reload_counter; bool auto_reload_module; From abc7563a35cf4f9927d19cd0f430ff6f6c606f94 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 18 Feb 2026 22:15:44 +0100 Subject: [PATCH 199/291] modtools: add ModIndex unit test --- kernel/modtools.h | 12 ++++++-- tests/unit/kernel/modindexTest.cc | 47 +++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+), 3 deletions(-) create mode 100644 tests/unit/kernel/modindexTest.cc diff --git a/kernel/modtools.h b/kernel/modtools.h index cf68693bc..5cd8e3cb2 100644 --- a/kernel/modtools.h +++ b/kernel/modtools.h @@ -151,11 +151,11 @@ struct ModIndex : public RTLIL::Monitor } } - void check() + bool ok() { #ifndef NDEBUG if (auto_reload_module) - return; + return true; for (auto it : database) log_assert(it.first == sigmap(it.first)); @@ -175,11 +175,17 @@ struct ModIndex : public RTLIL::Monitor else if (!(it.second == database_bak.at(it.first))) log("ModuleIndex::check(): Different content for database[%s].\n", log_signal(it.first)); - log_assert(database == database_bak); + return false; } + return true; #endif } + void check() + { + log_assert(ok()); + } + void notify_connect(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override { log_assert(module == cell->module); diff --git a/tests/unit/kernel/modindexTest.cc b/tests/unit/kernel/modindexTest.cc new file mode 100644 index 000000000..1921c9a93 --- /dev/null +++ b/tests/unit/kernel/modindexTest.cc @@ -0,0 +1,47 @@ +#include + +#include "kernel/modtools.h" +#include "kernel/rtlil.h" + +YOSYS_NAMESPACE_BEGIN + +TEST(ModIndexSwapTest, has) +{ + Design* d = new Design; + Module* m = d->addModule("$m"); + Wire* o = m->addWire("$o", 2); + o->port_input = true; + Wire* i = m->addWire("$i", 2); + i->port_input = true; + m->fixup_ports(); + m->addNot("$not", i, o); + auto mi = ModIndex(m); + mi.reload_module(); + for (auto [sb, info] : mi.database) { + EXPECT_TRUE(mi.database.find(sb) != mi.database.end()); + } + m->swap_names(i, o); + for (auto [sb, info] : mi.database) { + EXPECT_TRUE(mi.database.find(sb) != mi.database.end()); + } +} + +TEST(ModIndexDeleteTest, has) +{ + if (log_files.empty()) log_files.emplace_back(stdout); + Design* d = new Design; + Module* m = d->addModule("$m"); + Wire* w = m->addWire("$w"); + Wire* o = m->addWire("$o"); + o->port_output = true; + m->fixup_ports(); + Cell* not_ = m->addNotGate("$not", w, o); + auto mi = ModIndex(m); + mi.reload_module(); + mi.dump_db(); + Wire* a = m->addWire("\\a"); + not_->setPort(ID::A, a); + EXPECT_TRUE(mi.ok()); +} + +YOSYS_NAMESPACE_END From 094481739fa862669f1bb36e1c7bdbd255e4523c Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Sat, 18 Oct 2025 12:58:25 +1300 Subject: [PATCH 200/291] memory_libmap: Add -force-params Reduce complexity for adi brams by unconditionally providing the WIDTH and ABITS parameters. --- passes/memory/memory_libmap.cc | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/passes/memory/memory_libmap.cc b/passes/memory/memory_libmap.cc index c3c10363b..87adaa26d 100644 --- a/passes/memory/memory_libmap.cc +++ b/passes/memory/memory_libmap.cc @@ -39,6 +39,7 @@ struct PassOptions { bool no_auto_distributed; bool no_auto_block; bool no_auto_huge; + bool force_params; double logic_cost_rom; double logic_cost_ram; }; @@ -1859,7 +1860,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector &cells, cons cell->setParam(stringf("\\PORT_%s_WR_BE_WIDTH", name), GetSize(hw_wren)); } else { cell->setPort(stringf("\\PORT_%s_WR_EN", name), hw_wren); - if (cfg.def->byte != 0 && cfg.def->width_mode != WidthMode::Single) + if (cfg.def->byte != 0 && (cfg.def->width_mode != WidthMode::Single || opts.force_params)) cell->setParam(stringf("\\PORT_%s_WR_EN_WIDTH", name), GetSize(hw_wren)); } } @@ -2068,8 +2069,10 @@ void MemMapping::emit(const MemConfig &cfg) { std::vector cells; for (int rd = 0; rd < cfg.repl_d; rd++) { Cell *cell = mem.module->addCell(stringf("%s.%d.%d", mem.memid, rp, rd), cfg.def->id); - if (cfg.def->width_mode == WidthMode::Global) + if (cfg.def->width_mode == WidthMode::Global || opts.force_params) cell->setParam(ID::WIDTH, cfg.def->dbits[cfg.base_width_log2]); + if (opts.force_params) + cell->setParam(ID::ABITS, cfg.def->abits); if (cfg.def->widthscale) { std::vector val; for (auto &bit: init_swz.bits[rd]) @@ -2179,6 +2182,9 @@ struct MemoryLibMapPass : public Pass { log(" Disables automatic mapping of given kind of RAMs. Manual mapping\n"); log(" (using ram_style or other attributes) is still supported.\n"); log("\n"); + log(" -force-params\n"); + log(" Always generate memories with WIDTH and ABITS parameters.\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) override { @@ -2188,6 +2194,7 @@ struct MemoryLibMapPass : public Pass { opts.no_auto_distributed = false; opts.no_auto_block = false; opts.no_auto_huge = false; + opts.force_params = false; opts.logic_cost_ram = 1.0; opts.logic_cost_rom = 1.0/16.0; log_header(design, "Executing MEMORY_LIBMAP pass (mapping memories to cells).\n"); @@ -2214,6 +2221,10 @@ struct MemoryLibMapPass : public Pass { opts.no_auto_huge = true; continue; } + if (args[argidx] == "-force-params") { + opts.force_params = true; + continue; + } if (args[argidx] == "-logic-cost-rom" && argidx+1 < args.size()) { opts.logic_cost_rom = strtod(args[++argidx].c_str(), nullptr); continue; From 68e47ebcfeff498bba742c6eb3c9bbd6ed41589a Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 20 Feb 2026 15:23:45 +0100 Subject: [PATCH 201/291] CI: WASI - Applying YoWASP changes to script --- .github/workflows/extra-builds.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml index 5d0ac72d4..8af99def8 100644 --- a/.github/workflows/extra-builds.yml +++ b/.github/workflows/extra-builds.yml @@ -103,6 +103,7 @@ jobs: ENABLE_ZLIB := 0 CXXFLAGS += -I$(pwd)/flex-prefix/include + LINKFLAGS += -Wl,-z,stack-size=8388608 -Wl,--stack-first -Wl,--strip-all END make -C build -f ../Makefile CXX=clang -j$(nproc) From 2386923b8fe9563f318c2c4d47ef6caaca5e9dc0 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 20 Feb 2026 12:34:41 +1300 Subject: [PATCH 202/291] gowin: Fix bram ADA byte enables --- techlibs/gowin/brams_map.v | 2 +- techlibs/gowin/brams_map_gw5a.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/gowin/brams_map.v b/techlibs/gowin/brams_map.v index 774896e79..6187eadac 100644 --- a/techlibs/gowin/brams_map.v +++ b/techlibs/gowin/brams_map.v @@ -205,7 +205,7 @@ output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA; wire RSTA = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST; wire RSTB = OPTION_RESET_MODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST; -wire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_B_WR_BE); +wire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE); wire [13:0] ADB = `addrbe(PORT_B_WIDTH, PORT_B_ADDR, PORT_B_WR_BE); generate diff --git a/techlibs/gowin/brams_map_gw5a.v b/techlibs/gowin/brams_map_gw5a.v index 547b0d1d1..8bc77bf4f 100644 --- a/techlibs/gowin/brams_map_gw5a.v +++ b/techlibs/gowin/brams_map_gw5a.v @@ -205,7 +205,7 @@ output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA; wire RSTA = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST; wire RSTB = OPTION_RESET_MODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST; -wire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_B_WR_BE); +wire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE); wire [13:0] ADB = `addrbe(PORT_B_WIDTH, PORT_B_ADDR, PORT_B_WR_BE); generate From fd311c55019b5f96b54b8c72aa0294863b7e9eb4 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 20 Feb 2026 12:42:55 +1300 Subject: [PATCH 203/291] tests/arch/gowin: Add wr_en test --- tests/arch/gowin/bug5688.ys | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 tests/arch/gowin/bug5688.ys diff --git a/tests/arch/gowin/bug5688.ys b/tests/arch/gowin/bug5688.ys new file mode 100644 index 000000000..39019c4d6 --- /dev/null +++ b/tests/arch/gowin/bug5688.ys @@ -0,0 +1,31 @@ +read_verilog << EOT +`default_nettype none + +module top ( + input wire clk, + input wire [9:0] rd_addr, + output reg [15:0] rd_data, + input wire [9:0] wr_addr, + input wire [15:0] wr_data, + input wire wr_en +); + + (* ram_style = "block" *) reg [15:0] mem [0:1023]; + + // Read port — separate always block + always @(posedge clk) begin + rd_data <= mem[rd_addr]; + end + + // Write port — separate always block + always @(posedge clk) begin + if (wr_en) + mem[wr_addr] <= wr_data; + end + +endmodule + +EOT +synth_gowin -top top +splitnets +select -assert-any top/mem.0.0 %ci*:+DPX9B[ADA]:+DFF:+IBUF i:wr_en %i From b51110a50b484212fc04f46f95bd8678ac0364dc Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 23 Feb 2026 09:01:55 +0100 Subject: [PATCH 204/291] Build various Verific configurations --- .github/workflows/test-verific-cfg.yml | 109 +++++++++++++++++++++++++ 1 file changed, 109 insertions(+) create mode 100644 .github/workflows/test-verific-cfg.yml diff --git a/.github/workflows/test-verific-cfg.yml b/.github/workflows/test-verific-cfg.yml new file mode 100644 index 000000000..232ca6bd7 --- /dev/null +++ b/.github/workflows/test-verific-cfg.yml @@ -0,0 +1,109 @@ +name: Build various Verific configurations + +on: + workflow_dispatch: + +jobs: + test-verific-cfg: + if: github.repository_owner == 'YosysHQ' + runs-on: [self-hosted, linux, x64, fast] + steps: + - name: Checkout Yosys + uses: actions/checkout@v4 + with: + persist-credentials: false + submodules: true + - name: Runtime environment + run: | + echo "procs=$(nproc)" >> $GITHUB_ENV + + - name: verific [SV] + run: | + make config-clang + echo "ENABLE_VERIFIC := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_SYSTEMVERILOG := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_VHDL := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_HIER_TREE := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_EDIF := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_LIBERTY := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 0" >> Makefile.conf + echo "ENABLE_CCACHE := 1" >> Makefile.conf + make -j$procs + + - name: verific [VHDL] + run: | + make config-clang + echo "ENABLE_VERIFIC := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_SYSTEMVERILOG := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_VHDL := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_HIER_TREE := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_EDIF := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_LIBERTY := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 0" >> Makefile.conf + echo "ENABLE_CCACHE := 1" >> Makefile.conf + make -j$procs + + - name: verific [SV + VHDL] + run: | + make config-clang + echo "ENABLE_VERIFIC := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_SYSTEMVERILOG := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_VHDL := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_HIER_TREE := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_EDIF := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_LIBERTY := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 0" >> Makefile.conf + echo "ENABLE_CCACHE := 1" >> Makefile.conf + make -j$procs + + - name: verific [SV + HIER] + run: | + make config-clang + echo "ENABLE_VERIFIC := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_SYSTEMVERILOG := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_VHDL := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_HIER_TREE := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_EDIF := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_LIBERTY := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 0" >> Makefile.conf + echo "ENABLE_CCACHE := 1" >> Makefile.conf + make -j$procs + + - name: verific [VHDL + HIER] + run: | + make config-clang + echo "ENABLE_VERIFIC := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_SYSTEMVERILOG := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_VHDL := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_HIER_TREE := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_EDIF := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_LIBERTY := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 0" >> Makefile.conf + echo "ENABLE_CCACHE := 1" >> Makefile.conf + make -j$procs + + - name: verific [SV + VHDL + HIER] + run: | + make config-clang + echo "ENABLE_VERIFIC := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_SYSTEMVERILOG := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_VHDL := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_HIER_TREE := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_EDIF := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_LIBERTY := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 0" >> Makefile.conf + echo "ENABLE_CCACHE := 1" >> Makefile.conf + make -j$procs + + - name: verific [SV + VHDL + HIER + EDIF + LIBERTY] + run: | + make config-clang + echo "ENABLE_VERIFIC := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_SYSTEMVERILOG := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_VHDL := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_HIER_TREE := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_EDIF := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_LIBERTY := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 0" >> Makefile.conf + echo "ENABLE_CCACHE := 1" >> Makefile.conf + make -j$procs From 31f7d0d92d6463748672c3b43c55153ee2c14984 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 25 Feb 2026 10:36:46 +0100 Subject: [PATCH 205/291] Remove already disabled CI job --- .github/workflows/update-flake-lock.yml | 25 ------------------------- 1 file changed, 25 deletions(-) delete mode 100644 .github/workflows/update-flake-lock.yml diff --git a/.github/workflows/update-flake-lock.yml b/.github/workflows/update-flake-lock.yml deleted file mode 100644 index b32498baf..000000000 --- a/.github/workflows/update-flake-lock.yml +++ /dev/null @@ -1,25 +0,0 @@ -name: update-flake-lock -on: - workflow_dispatch: # allows manual triggering - schedule: - - cron: '0 0 * * 0' # runs weekly on Sunday at 00:00 - -jobs: - lockfile: - if: github.repository == 'YosysHQ/Yosys' - runs-on: ubuntu-latest - steps: - - name: Checkout repository - uses: actions/checkout@v4 - with: - persist-credentials: false - - name: Install Nix - uses: DeterminateSystems/nix-installer-action@main - - name: Update flake.lock - uses: DeterminateSystems/update-flake-lock@main - with: - token: ${{CI_CREATE_PR_TOKEN}} - pr-title: "Update flake.lock" # Title of PR to be created - pr-labels: | # Labels to be set on the PR - dependencies - automated From 2c52546e2a9b1ac94c1ddfdd88ef80238c412c7e Mon Sep 17 00:00:00 2001 From: nella Date: Wed, 25 Feb 2026 16:42:05 +0100 Subject: [PATCH 206/291] Fix docs. --- docs/source/using_yosys/more_scripting/model_checking.rst | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/source/using_yosys/more_scripting/model_checking.rst b/docs/source/using_yosys/more_scripting/model_checking.rst index 02400d5d8..cbf5dc7b0 100644 --- a/docs/source/using_yosys/more_scripting/model_checking.rst +++ b/docs/source/using_yosys/more_scripting/model_checking.rst @@ -121,12 +121,12 @@ Result with fixed :file:`axis_master.v`: Witness framework and per-property tracking ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -When using AIGER-based formal verification flows (such as the `abc` engine in +When using AIGER-based formal verification flows (such as the ``abc`` engine in SBY), Yosys provides infrastructure for tracking individual formal properties through the verification pipeline. -The `rename -witness` pass (run automatically by `prep`) assigns public -names to all cells that participate in the witness framework: +The `rename -witness` pass assigns public names to all cells that participate in +the witness framework: - Witness signal cells: `$anyconst`, `$anyseq`, `$anyinit`, `$allconst`, `$allseq` @@ -139,7 +139,7 @@ their hierarchical path rather than by anonymous internal identifiers. The `write_aiger -ywmap` option generates a map file for conversion to and from Yosys witness traces, and also allows for mapping AIGER bad-state properties and invariant constraints back to individual formal properties by name. This enables -features like per-property pass/fail reporting (e.g. `abc pdr` with +features like per-property pass/fail reporting (e.g. ``abc pdr`` with ``--keep-going`` mode). The `write_smt2` backend similarly uses the public witness names when emitting From 5970be33fb0dc99e9ca98ca5a6bc65b22c6ee3ce Mon Sep 17 00:00:00 2001 From: Andrew Pullin Date: Tue, 24 Feb 2026 09:55:11 -0800 Subject: [PATCH 207/291] abc9: preserve topological-loop asserts with targeted SCC fallback A real-world ABC9 flow hit residual combinational loops after SCC breaking, tripping the prep_xaiger loop assertion. Keep the existing topological assertions in place (prep_xaiger and reintegrate still assert no_loops). To handle residual non-box loops, add a targeted fallback in prep_xaiger: when loops remain after normal SCC breaking, insert additional $__ABC9_SCC_BREAKER cuts on non-box loop cells, rebuild toposort, and then re-check the existing assertion. Also keep pre-ABC9 SCC tagging on all cell types (scc -all_cell_types) and add a regression test (tests/techmap/abc9-nonbox-loop-with-box.ys). --- passes/techmap/abc9_ops.cc | 113 ++++++++++++++++----- tests/arch/ice40/fsm.ys | 2 +- tests/techmap/abc9-nonbox-loop-with-box.ys | 19 ++++ 3 files changed, 107 insertions(+), 27 deletions(-) create mode 100644 tests/techmap/abc9-nonbox-loop-with-box.ys diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 8d3869ece..7471ec700 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -23,6 +23,7 @@ #include "kernel/utils.h" #include "kernel/celltypes.h" #include "kernel/timinginfo.h" +#include USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -587,6 +588,7 @@ void break_scc(RTLIL::Module *module) auto id = it->second; auto r = ids_seen.insert(id); cell->attributes.erase(it); + // Cut exactly one representative cell per SCC id. if (!r.second) continue; for (auto &c : cell->connections_) { @@ -710,8 +712,6 @@ void prep_xaiger(RTLIL::Module *module, bool dff) SigMap sigmap(module); - dict> bit_drivers, bit_users; - TopoSort toposort; dict> box_ports; for (auto cell : module->cells()) { @@ -750,39 +750,100 @@ void prep_xaiger(RTLIL::Module *module, bool dff) } } } - else if (!yosys_celltypes.cell_known(cell->type)) - continue; - - // TODO: Speed up toposort -- we care about box ordering only - for (auto conn : cell->connections()) { - if (cell->input(conn.first)) - for (auto bit : sigmap(conn.second)) - bit_users[bit].insert(cell->name); - - if (cell->output(conn.first) && !abc9_flop) - for (auto bit : sigmap(conn.second)) - bit_drivers[bit].insert(cell->name); - } - toposort.node(cell->name); } if (box_ports.empty()) return; - for (auto &it : bit_users) - if (bit_drivers.count(it.first)) - for (auto driver_cell : bit_drivers.at(it.first)) - for (auto user_cell : it.second) - toposort.edge(driver_cell, user_cell); + // Build the same topo graph for the initial pass and the optional retry. + auto build_toposort = [&](TopoSort &toposort) { + dict> bit_drivers, bit_users; - if (ys_debug(1)) - toposort.analyze_loops = true; + for (auto cell : module->cells()) { + if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) + continue; + if (cell->has_keep_attr()) + continue; - bool no_loops = toposort.sort(); + auto inst_module = design->module(cell->type); + bool abc9_flop = inst_module && inst_module->get_bool_attribute(ID::abc9_flop); + if (abc9_flop && !dff) + continue; + if (!(inst_module && inst_module->get_bool_attribute(ID::abc9_box)) && !yosys_celltypes.cell_known(cell->type)) + continue; + + // TODO: Speed up toposort -- we care about box ordering only + for (auto conn : cell->connections()) { + if (cell->input(conn.first)) + for (auto bit : sigmap(conn.second)) + bit_users[bit].insert(cell->name); + + if (cell->output(conn.first) && !abc9_flop) + for (auto bit : sigmap(conn.second)) + bit_drivers[bit].insert(cell->name); + } + toposort.node(cell->name); + } + + // Build producer -> consumer edges on sigmapped nets. + for (auto &it : bit_users) + if (bit_drivers.count(it.first)) + for (auto driver_cell : bit_drivers.at(it.first)) + for (auto user_cell : it.second) + toposort.edge(driver_cell, user_cell); + if (ys_debug(1)) + toposort.analyze_loops = true; + return toposort.sort(); + }; + + // Build TopoSort in a container, as we may need to conditionally rebuild it on retry. + std::optional> toposort; + toposort.emplace(); + bool no_loops = build_toposort(toposort.value()); + + // Fallback for residual loops after SCC cutting: insert additional + // breakers on non-box loop cells, then re-run toposort checks. + if (!no_loops) { + SigSpec I, O; + pool broken_cells; + + for (auto &loop : toposort.value().loops) + for (auto cell_name : loop) { + // Loop reports can overlap; cut each cell at most once. + if (!broken_cells.insert(cell_name).second) + continue; + auto cell = module->cell(cell_name); + log_assert(cell); + auto inst_module = design->module(cell->type); + if (inst_module && inst_module->get_bool_attribute(ID::abc9_box)) + continue; + for (auto &c : cell->connections_) { + if (c.second.is_fully_const()) continue; + if (cell->output(c.first)) { + Wire *w = module->addWire(NEW_ID, GetSize(c.second)); + I.append(w); + O.append(c.second); + c.second = w; + } + } + } + + if (!I.empty()) { + auto cell = module->addCell(NEW_ID, ID($__ABC9_SCC_BREAKER)); + log_assert(GetSize(I) == GetSize(O)); + cell->setParam(ID::WIDTH, GetSize(I)); + cell->setPort(ID::I, std::move(I)); + cell->setPort(ID::O, std::move(O)); + + // Rebuild topo ordering after inserting the additional breakers. + toposort.emplace(); + no_loops = build_toposort(toposort.value()); + } + } if (ys_debug(1)) { unsigned i = 0; - for (auto &it : toposort.loops) { + for (auto &it : toposort.value().loops) { log(" loop %d\n", i++); for (auto cell_name : it) { auto cell = module->cell(cell_name); @@ -806,7 +867,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff) TimingInfo timing; int port_id = 1, box_count = 0; - for (auto cell_name : toposort.sorted) { + for (auto cell_name : toposort.value().sorted) { RTLIL::Cell *cell = module->cell(cell_name); log_assert(cell); diff --git a/tests/arch/ice40/fsm.ys b/tests/arch/ice40/fsm.ys index e3b746202..b01d34bba 100644 --- a/tests/arch/ice40/fsm.ys +++ b/tests/arch/ice40/fsm.ys @@ -12,5 +12,5 @@ cd fsm # Constrain all select calls below inside the top module select -assert-count 4 t:SB_DFF select -assert-count 2 t:SB_DFFESR -select -assert-max 15 t:SB_LUT4 +select -assert-max 16 t:SB_LUT4 select -assert-none t:SB_DFFESR t:SB_DFF t:SB_LUT4 %% t:* %D diff --git a/tests/techmap/abc9-nonbox-loop-with-box.ys b/tests/techmap/abc9-nonbox-loop-with-box.ys new file mode 100644 index 000000000..2b7a551bc --- /dev/null +++ b/tests/techmap/abc9-nonbox-loop-with-box.ys @@ -0,0 +1,19 @@ +read_verilog -icells -specify < o) = 1; +endspecify +endmodule + +module top(input i, output o); + wire a, b, c, z; + $_AND_ a0(.A(b), .B(i), .Y(a)); + $_AND_ b0(.A(a), .B(c), .Y(b)); + $_AND_ c0(.A(b), .B(i), .Y(c)); + box1 u_box(.i(i), .o(z)); + assign o = c ^ z; +endmodule +EOT + +abc9 -lut 4 From b3caec1a93baf847559422bb30df8b1168296292 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 27 Feb 2026 07:55:34 +0100 Subject: [PATCH 208/291] Update ABC as per 2026-02-27 --- abc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/abc b/abc index c18b835ef..8e401543d 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit c18b835ef140217c84a26ba510f98f69d54dd48e +Subproject commit 8e401543d3ecf65e3a3631c7a271793a4d356cb0 From 7f1f247c5629863902e36bb2d7b51f9aec2feb59 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 27 Feb 2026 13:12:32 +0100 Subject: [PATCH 209/291] gowin: remove spurious warning --- techlibs/gowin/synth_gowin.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 3d1414e9e..9fd4dca86 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -309,7 +309,7 @@ struct SynthGowinPass : public ScriptPass if (nolutram) args += " -no-auto-distributed"; } - run(stringf("memory_libmap -lib +/gowin/lutrams.txt -lib +/gowin/brams.txt -D %s", family) + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)"); + run(stringf("memory_libmap -lib +/gowin/lutrams.txt -lib +/gowin/brams.txt%s", family == "gw5a" ? " -D gw5a" : "") + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)"); run(stringf("techmap -map +/gowin/lutrams_map.v -map +/gowin/brams_map%s.v", family == "gw5a" ? "_gw5a" : "")); } From e9442194f27140e3e80cb3bf407c3259d562c449 Mon Sep 17 00:00:00 2001 From: likeamahoney Date: Fri, 27 Feb 2026 20:42:40 +0300 Subject: [PATCH 210/291] support automatic lifetime qualifier on procedural variables --- frontends/ast/genrtlil.cc | 12 ++++ frontends/verilog/verilog_parser.y | 18 +++-- tests/verilog/automatic_lifetime.ys | 104 ++++++++++++++++++++++++++++ 3 files changed, 129 insertions(+), 5 deletions(-) create mode 100644 tests/verilog/automatic_lifetime.ys diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index d9eb51a9c..65af26132 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -403,6 +403,18 @@ struct AST_INTERNAL::ProcessGenerator if (GetSize(syncrule->signal) != 1) always->input_error("Found posedge/negedge event on a signal that is not 1 bit wide!\n"); addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true); + // Automatic (nosync) variables must not become flip-flops: remove + // them from clocked sync rules so that proc_dff does not infer + // an unnecessary register for a purely combinational temporary. + syncrule->actions.erase( + std::remove_if(syncrule->actions.begin(), syncrule->actions.end(), + [](const RTLIL::SigSig &ss) { + for (auto &chunk : ss.first.chunks()) + if (chunk.wire && chunk.wire->get_bool_attribute(ID::nosync)) + return true; + return false; + }), + syncrule->actions.end()); proc->syncs.push_back(syncrule); } if (proc->syncs.empty()) { diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 684727d5b..148a6cc63 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -84,7 +84,7 @@ int current_function_or_task_port_id; std::vector case_type_stack; bool do_not_require_port_stubs; - bool current_wire_rand, current_wire_const; + bool current_wire_rand, current_wire_const, current_wire_automatic; bool current_modport_input, current_modport_output; bool default_nettype_wire = true; std::istream* lexin; @@ -958,14 +958,18 @@ delay: non_opt_delay | %empty; io_wire_type: - { extra->astbuf3 = std::make_unique(@$, AST_WIRE); extra->current_wire_rand = false; extra->current_wire_const = false; } + { extra->astbuf3 = std::make_unique(@$, AST_WIRE); extra->current_wire_rand = false; extra->current_wire_const = false; extra->current_wire_automatic = false; } wire_type_token_io wire_type_const_rand opt_wire_type_token wire_type_signedness { $$ = std::move(extra->astbuf3); SET_RULE_LOC(@$, @2, @$); }; non_io_wire_type: - { extra->astbuf3 = std::make_unique(@$, AST_WIRE); extra->current_wire_rand = false; extra->current_wire_const = false; } - wire_type_const_rand wire_type_token wire_type_signedness - { $$ = std::move(extra->astbuf3); SET_RULE_LOC(@$, @2, @$); }; + { extra->astbuf3 = std::make_unique(@$, AST_WIRE); extra->current_wire_rand = false; extra->current_wire_const = false; extra->current_wire_automatic = false; } + opt_lifetime wire_type_const_rand wire_type_token wire_type_signedness + { + if (extra->current_wire_automatic) + extra->astbuf3->set_attribute(ID::nosync, AstNode::mkconst_int(extra->astbuf3->location, 1, false)); + $$ = std::move(extra->astbuf3); SET_RULE_LOC(@$, @2, @$); + }; wire_type: io_wire_type { $$ = std::move($1); } | @@ -1253,6 +1257,10 @@ opt_automatic: TOK_AUTOMATIC | %empty; +opt_lifetime: + TOK_AUTOMATIC { extra->current_wire_automatic = true; } | + %empty; + task_func_args_opt: TOK_LPAREN TOK_RPAREN | %empty | TOK_LPAREN { extra->albuf = nullptr; diff --git a/tests/verilog/automatic_lifetime.ys b/tests/verilog/automatic_lifetime.ys new file mode 100644 index 000000000..84e21e088 --- /dev/null +++ b/tests/verilog/automatic_lifetime.ys @@ -0,0 +1,104 @@ +# Automatic reg as intermediate value in always @(*) +# The result must be provably equivalent to the direct expression. +# No latch or DFF must be created for tmp. +design -reset +read_verilog -sv <> 4) & 1'b1)); +endmodule +EOF +proc +async2sync +select -assert-none t:$dff t:$dlatch %% +sat -verify -prove-asserts -show-all + +# automatic in a clocked block — only the explicitly registered +# output (result) must get a DFF; the automatic temp must not. +design -reset +read_verilog -sv < Date: Wed, 4 Mar 2026 07:46:40 +0100 Subject: [PATCH 211/291] Fix help message for equiv passes --- passes/equiv/equiv_induct.cc | 2 +- passes/equiv/equiv_simple.cc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/equiv/equiv_induct.cc b/passes/equiv/equiv_induct.cc index d843fef67..e4480c893 100644 --- a/passes/equiv/equiv_induct.cc +++ b/passes/equiv/equiv_induct.cc @@ -174,7 +174,7 @@ struct EquivInductPass : public Pass { log("Only selected $equiv cells are proven and only selected cells are used to\n"); log("perform the proof.\n"); log("\n"); - EquivBasicConfig::help("4"); + log("%s", EquivBasicConfig::help("4")); log("\n"); log("This command is very effective in proving complex sequential circuits, when\n"); log("the internal state of the circuit quickly propagates to $equiv cells.\n"); diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc index ff6df295c..e498928c3 100644 --- a/passes/equiv/equiv_simple.cc +++ b/passes/equiv/equiv_simple.cc @@ -428,7 +428,7 @@ struct EquivSimplePass : public Pass { log("\n"); log("This command tries to prove $equiv cells using a simple direct SAT approach.\n"); log("\n"); - EquivSimpleConfig::help("1"); + log("%s", EquivSimpleConfig::help("1")); log("\n"); } void execute(std::vector args, Design *design) override From 70a11c6bf0e8dd669f56c7da3587f78b405138e2 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 4 Mar 2026 07:46:57 +0100 Subject: [PATCH 212/291] Release version 0.63 --- CHANGELOG | 14 +++++++++++++- Makefile | 4 ++-- docs/source/conf.py | 2 +- 3 files changed, 16 insertions(+), 4 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index e345a8514..4904d9639 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,8 +2,20 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.62 .. Yosys 0.63-dev +Yosys 0.62 .. Yosys 0.63 -------------------------- + * Various + - Added DSP inference for Gowin GW1N and GW2A. + - Added support for subtract in preadder for Xilinx arch. + - Added infrastructure to run a sat solver as a command. + + * New commands and options + - Added "-ignore-unknown-cells" option to "equiv_induct" + and "equiv_simple" pass. + - Added "-force-params" option to "memory_libmap" pass. + - Added "-select-solver" option to "sat" pass. + - Added "-default_params" option to "write_verilog" pass. + - Added "-nodsp" option to "synth_gowin" pass. Yosys 0.61 .. Yosys 0.62 -------------------------- diff --git a/Makefile b/Makefile index 0a15c2b23..5a2cb66f5 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.62 +YOSYS_VER := 0.63 ifneq (, $(shell command -v git 2>/dev/null)) ifneq (, $(shell git rev-parse --git-dir 2>/dev/null)) @@ -170,7 +170,7 @@ ifneq (, $(shell git rev-parse --git-dir 2>/dev/null)) YOSYS_VER := $(YOSYS_VER)+$(GIT_COMMIT_COUNT) endif else - YOSYS_VER := $(YOSYS_VER)+post +# YOSYS_VER := $(YOSYS_VER)+post endif endif diff --git a/docs/source/conf.py b/docs/source/conf.py index a7da22d97..458040db0 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -6,7 +6,7 @@ import os project = 'YosysHQ Yosys' author = 'YosysHQ GmbH' copyright ='2026 YosysHQ GmbH' -yosys_ver = "0.62" +yosys_ver = "0.63" # select HTML theme html_theme = 'furo-ys' From 228052bfb3e4a733e4bdb3fe57cdc7692a47e220 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 4 Mar 2026 08:45:13 +0100 Subject: [PATCH 213/291] Next dev cycle --- CHANGELOG | 3 +++ Makefile | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/CHANGELOG b/CHANGELOG index 4904d9639..372a59d58 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ List of major changes and improvements between releases ======================================================= +Yosys 0.63 .. Yosys 0.64-dev +-------------------------- + Yosys 0.62 .. Yosys 0.63 -------------------------- * Various diff --git a/Makefile b/Makefile index 5a2cb66f5..507c74a63 100644 --- a/Makefile +++ b/Makefile @@ -170,7 +170,7 @@ ifneq (, $(shell git rev-parse --git-dir 2>/dev/null)) YOSYS_VER := $(YOSYS_VER)+$(GIT_COMMIT_COUNT) endif else -# YOSYS_VER := $(YOSYS_VER)+post + YOSYS_VER := $(YOSYS_VER)+post endif endif From cf4d4ff23dfa831db43d4fa4e772a4afffdd125f Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 4 Mar 2026 11:35:16 +0100 Subject: [PATCH 214/291] CI: add support for merge queue --- .github/workflows/extra-builds.yml | 39 ++++++++++++++++------- .github/workflows/prepare-docs.yml | 23 +++++++++++--- .github/workflows/source-vendor.yml | 7 ++++- .github/workflows/test-build.yml | 45 +++++++++++++++++++++------ .github/workflows/test-compile.yml | 31 ++++++++++++------ .github/workflows/test-sanitizers.yml | 32 ++++++++++++++----- .github/workflows/test-verific.yml | 42 ++++++++++++++++--------- 7 files changed, 161 insertions(+), 58 deletions(-) diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml index 8af99def8..d301ea882 100644 --- a/.github/workflows/extra-builds.yml +++ b/.github/workflows/extra-builds.yml @@ -1,23 +1,20 @@ name: Test extra build flows on: - # always test main - push: - branches: - - main - merge_group: - # test PRs pull_request: - # allow triggering tests, ignores skip check + merge_group: + #push: + # branches: [ main ] workflow_dispatch: jobs: pre_job: runs-on: ubuntu-latest outputs: - should_skip: ${{ steps.skip_check.outputs.should_skip }} + should_skip: ${{ steps.set_output.outputs.should_skip }} steps: - id: skip_check + if: ${{ github.event_name != 'merge_group' }} uses: fkirc/skip-duplicate-actions@v5 with: # don't run on documentation changes @@ -26,11 +23,19 @@ jobs: # but never cancel main cancel_others: ${{ github.ref != 'refs/heads/main' }} + - id: set_output + run: | + if [ "${{ github.event_name }}" = "merge_group" ]; then + echo "should_skip=false" >> $GITHUB_OUTPUT + else + echo "should_skip=${{ steps.skip_check.outputs.should_skip }}" >> $GITHUB_OUTPUT + fi + vs-prep: name: Prepare Visual Studio build runs-on: ubuntu-latest needs: [pre_job] - if: needs.pre_job.outputs.should_skip != 'true' + if: (github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true' steps: - uses: actions/checkout@v4 with: @@ -48,7 +53,7 @@ jobs: name: Visual Studio build runs-on: windows-latest needs: [vs-prep, pre_job] - if: needs.pre_job.outputs.should_skip != 'true' + if: (github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true' steps: - uses: actions/download-artifact@v4 with: @@ -65,7 +70,7 @@ jobs: wasi-build: name: WASI build needs: pre_job - if: needs.pre_job.outputs.should_skip != 'true' + if: (github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true' runs-on: ubuntu-latest steps: - uses: actions/checkout@v4 @@ -111,7 +116,7 @@ jobs: nix-build: name: "Build nix flake" needs: pre_job - if: needs.pre_job.outputs.should_skip != 'true' + if: (github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true' runs-on: ${{ matrix.os }} strategy: matrix: @@ -126,3 +131,13 @@ jobs: with: install_url: https://releases.nixos.org/nix/nix-2.30.0/install - run: nix build .?submodules=1 -L + + extra-builds-result: + runs-on: ubuntu-latest + needs: + - vs-build + - wasi-build + - nix-build + if: always() && !contains(join(needs.*.result, ','), 'failure') && !contains(join(needs.*.result, ','), 'cancelled') + steps: + - run: echo "All good" \ No newline at end of file diff --git a/.github/workflows/prepare-docs.yml b/.github/workflows/prepare-docs.yml index e3d917942..e2ebe9e69 100644 --- a/.github/workflows/prepare-docs.yml +++ b/.github/workflows/prepare-docs.yml @@ -1,17 +1,24 @@ name: Build docs artifact with Verific -on: [push, pull_request, merge_group] +on: + pull_request: + merge_group: + push: + branches: [ main, "docs-preview/**", "docs-preview*" ] + tags: [ "*" ] + workflow_dispatch: jobs: check_docs_rebuild: runs-on: ubuntu-latest outputs: - skip_check: ${{ steps.skip_check.outputs.should_skip }} + should_skip: ${{ steps.set_output.outputs.should_skip }} docs_export: ${{ steps.docs_var.outputs.docs_export }} env: docs_export: ${{ github.ref == 'refs/heads/main' || startsWith(github.ref, 'refs/heads/docs-preview') || startsWith(github.ref, 'refs/tags/') }} steps: - id: skip_check + if: ${{ github.event_name != 'merge_group' }} uses: fkirc/skip-duplicate-actions@v5 with: paths_ignore: '["**/README.md"]' @@ -22,11 +29,19 @@ jobs: - id: docs_var run: echo "docs_export=${docs_export}" >> $GITHUB_OUTPUT + - id: set_output + run: | + if [ "${{ github.event_name }}" = "merge_group" ]; then + echo "should_skip=false" >> $GITHUB_OUTPUT + else + echo "should_skip=${{ steps.skip_check.outputs.should_skip }}" >> $GITHUB_OUTPUT + fi + prepare-docs: # docs builds are needed for anything on main, any tagged versions, and any tag # or branch starting with docs-preview needs: check_docs_rebuild - if: ${{ needs.check_docs_rebuild.outputs.should_skip != 'true' && github.repository == 'YosysHQ/Yosys' }} + if: ${{ needs.check_docs_rebuild.outputs.should_skip != 'true' && github.repository_owner == 'YosysHQ' }} runs-on: [self-hosted, linux, x64, fast] steps: - name: Checkout Yosys @@ -75,7 +90,7 @@ jobs: make -C docs html -j$procs TARGETS= EXTRA_TARGETS= - name: Trigger RTDs build - if: ${{ needs.check_docs_rebuild.outputs.docs_export == 'true' }} + if: ${{ needs.check_docs_rebuild.outputs.docs_export == 'true' && github.repository == 'YosysHQ/Yosys' }} uses: dfm/rtds-action@v1.1.0 with: webhook_url: ${{ secrets.RTDS_WEBHOOK_URL }} diff --git a/.github/workflows/source-vendor.yml b/.github/workflows/source-vendor.yml index dc9480ef6..bf8a63c99 100644 --- a/.github/workflows/source-vendor.yml +++ b/.github/workflows/source-vendor.yml @@ -1,6 +1,11 @@ name: Create source archive with vendored dependencies -on: [push, workflow_dispatch] +on: + pull_request: + merge_group: + push: + branches: [ main ] + workflow_dispatch: jobs: vendor-sources: diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index ebdeb15d8..ac5591b5c 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -1,23 +1,20 @@ name: Build and run tests on: - # always test main - push: - branches: - - main - merge_group: - # test PRs pull_request: - # allow triggering tests, ignores skip check + merge_group: + #push: + # branches: [ main ] workflow_dispatch: jobs: pre_job: runs-on: ubuntu-latest outputs: - should_skip: ${{ steps.skip_check.outputs.should_skip }} + should_skip: ${{ steps.set_output.outputs.should_skip }} steps: - id: skip_check + if: ${{ github.event_name != 'merge_group' }} uses: fkirc/skip-duplicate-actions@v5 with: # don't run on documentation changes @@ -26,12 +23,21 @@ jobs: # but never cancel main cancel_others: ${{ github.ref != 'refs/heads/main' }} + - id: set_output + run: | + if [ "${{ github.event_name }}" = "merge_group" ]; then + echo "should_skip=false" >> $GITHUB_OUTPUT + else + echo "should_skip=${{ steps.skip_check.outputs.should_skip }}" >> $GITHUB_OUTPUT + fi + pre_docs_job: runs-on: ubuntu-latest outputs: - should_skip: ${{ steps.skip_check.outputs.should_skip }} + should_skip: ${{ steps.set_output.outputs.should_skip }} steps: - id: skip_check + if: ${{ github.event_name != 'merge_group' }} uses: fkirc/skip-duplicate-actions@v5 with: # don't run on readme changes @@ -40,6 +46,14 @@ jobs: # but never cancel main cancel_others: ${{ github.ref != 'refs/heads/main' }} + - id: set_output + run: | + if [ "${{ github.event_name }}" = "merge_group" ]; then + echo "should_skip=false" >> $GITHUB_OUTPUT + else + echo "should_skip=${{ steps.skip_check.outputs.should_skip }}" >> $GITHUB_OUTPUT + fi + build-yosys: name: Reusable build runs-on: ${{ matrix.os }} @@ -226,7 +240,7 @@ jobs: name: Try build docs runs-on: [self-hosted, linux, x64, fast] needs: [pre_docs_job] - if: ${{ needs.pre_docs_job.outputs.should_skip != 'true' && github.repository == 'YosysHQ/Yosys' }} + if: ${{ needs.pre_docs_job.outputs.should_skip != 'true' && github.repository_owner == 'YosysHQ' }} strategy: matrix: docs-target: [html, latexpdf] @@ -265,3 +279,14 @@ jobs: name: docs-build-${{ matrix.docs-target }} path: docs/build/ retention-days: 7 + + test-build-result: + runs-on: ubuntu-latest + needs: + - test-yosys + - test-cells + - test-docs + - test-docs-build + if: always() && !contains(join(needs.*.result, ','), 'failure') && !contains(join(needs.*.result, ','), 'cancelled') + steps: + - run: echo "All good" \ No newline at end of file diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml index 000d1c400..7536ecebe 100644 --- a/.github/workflows/test-compile.yml +++ b/.github/workflows/test-compile.yml @@ -1,23 +1,20 @@ name: Compiler testing on: - # always test main - push: - branches: - - main - merge_group: - # test PRs pull_request: - # allow triggering tests, ignores skip check + merge_group: + #push: + # branches: [ main ] workflow_dispatch: jobs: pre_job: runs-on: ubuntu-latest outputs: - should_skip: ${{ steps.skip_check.outputs.should_skip }} + should_skip: ${{ steps.set_output.outputs.should_skip }} steps: - id: skip_check + if: ${{ github.event_name != 'merge_group' }} uses: fkirc/skip-duplicate-actions@v5 with: # don't run on documentation changes @@ -26,10 +23,18 @@ jobs: # but never cancel main cancel_others: ${{ github.ref != 'refs/heads/main' }} + - id: set_output + run: | + if [ "${{ github.event_name }}" = "merge_group" ]; then + echo "should_skip=false" >> $GITHUB_OUTPUT + else + echo "should_skip=${{ steps.skip_check.outputs.should_skip }}" >> $GITHUB_OUTPUT + fi + test-compile: runs-on: ${{ matrix.os }} needs: pre_job - if: needs.pre_job.outputs.should_skip != 'true' + if: (github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true' env: CXXFLAGS: ${{ startsWith(matrix.compiler, 'gcc') && '-Wp,-D_GLIBCXX_ASSERTIONS' || ''}} CC_SHORT: ${{ startsWith(matrix.compiler, 'gcc') && 'gcc' || 'clang' }} @@ -90,3 +95,11 @@ jobs: run: | make config-$CC_SHORT make -j$procs CXXSTD=c++20 compile-only + + test-compile-result: + runs-on: ubuntu-latest + needs: + - test-compile + if: always() && !contains(join(needs.*.result, ','), 'failure') && !contains(join(needs.*.result, ','), 'cancelled') + steps: + - run: echo "All good" diff --git a/.github/workflows/test-sanitizers.yml b/.github/workflows/test-sanitizers.yml index 7650470c3..85417f746 100644 --- a/.github/workflows/test-sanitizers.yml +++ b/.github/workflows/test-sanitizers.yml @@ -1,32 +1,41 @@ name: Check clang sanitizers on: - # always test main - push: - branches: - - main + pull_request: merge_group: - # ignore PRs due to time needed - # allow triggering tests, ignores skip check + #push: + # branches: [ main ] workflow_dispatch: jobs: pre_job: runs-on: ubuntu-latest outputs: - should_skip: ${{ steps.skip_check.outputs.should_skip }} + should_skip: ${{ steps.set_output.outputs.should_skip }} steps: - id: skip_check + if: ${{ github.event_name != 'merge_group' }} uses: fkirc/skip-duplicate-actions@v5 with: # don't run on documentation changes paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]' + # cancel previous builds if a new commit is pushed + # but never cancel main + cancel_others: ${{ github.ref != 'refs/heads/main' }} + + - id: set_output + run: | + if [ "${{ github.event_name }}" = "merge_group" ]; then + echo "should_skip=false" >> $GITHUB_OUTPUT + else + echo "should_skip=${{ steps.skip_check.outputs.should_skip }}" >> $GITHUB_OUTPUT + fi run_san: name: Build and run tests runs-on: ${{ matrix.os }} needs: pre_job - if: needs.pre_job.outputs.should_skip != 'true' + if: (github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true' env: CC: clang ASAN_OPTIONS: halt_on_error=1 @@ -73,3 +82,10 @@ jobs: run: | find tests/**/*.err -print -exec cat {} \; + test-sanitizers-result: + runs-on: ubuntu-latest + needs: + - run_san + if: always() && !contains(join(needs.*.result, ','), 'failure') && !contains(join(needs.*.result, ','), 'cancelled') + steps: + - run: echo "All good" diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml index cd2545cc8..cd88f547e 100644 --- a/.github/workflows/test-verific.yml +++ b/.github/workflows/test-verific.yml @@ -1,23 +1,20 @@ name: Build and run tests with Verific (Linux) on: - # always test main - push: - branches: - - main - merge_group: - # test PRs pull_request: - # allow triggering tests, ignores skip check + merge_group: + #push: + # branches: [ main ] workflow_dispatch: jobs: - pre-job: + pre_job: runs-on: ubuntu-latest outputs: - should_skip: ${{ steps.skip_check.outputs.should_skip }} + should_skip: ${{ steps.set_output.outputs.should_skip }} steps: - id: skip_check + if: ${{ github.event_name != 'merge_group' }} uses: fkirc/skip-duplicate-actions@v5 with: # don't run on documentation changes @@ -26,9 +23,17 @@ jobs: # but never cancel main cancel_others: ${{ github.ref != 'refs/heads/main' }} + - id: set_output + run: | + if [ "${{ github.event_name }}" = "merge_group" ]; then + echo "should_skip=false" >> $GITHUB_OUTPUT + else + echo "should_skip=${{ steps.skip_check.outputs.should_skip }}" >> $GITHUB_OUTPUT + fi + test-verific: - needs: pre-job - if: ${{ needs.pre-job.outputs.should_skip != 'true' && github.repository == 'YosysHQ/Yosys' }} + needs: pre_job + if: ${{ needs.pre_job.outputs.should_skip != 'true' && github.repository_owner == 'YosysHQ' }} runs-on: [self-hosted, linux, x64, fast] steps: - name: Checkout Yosys @@ -76,13 +81,13 @@ jobs: cd tests/svtypes && bash run-test.sh - name: Run SBY tests - if: ${{ github.ref == 'refs/heads/main' }} + if: ${{ github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch' }} run: | make -C sby run_ci test-pyosys: - needs: pre-job - if: ${{ needs.pre-job.outputs.should_skip != 'true' && github.repository == 'YosysHQ/Yosys' }} + needs: pre_job + if: ${{ needs.pre_job.outputs.should_skip != 'true' && github.repository_owner == 'YosysHQ' }} runs-on: [self-hosted, linux, x64, fast] steps: - name: Checkout Yosys @@ -118,3 +123,12 @@ jobs: run: | export PYTHONPATH=${GITHUB_WORKSPACE}/.local/usr/lib/python3/site-packages:$PYTHONPATH python3 tests/pyosys/run_tests.py + + test-verific-result: + runs-on: ubuntu-latest + needs: + - test-verific + - test-pyosys + if: always() && !contains(join(needs.*.result, ','), 'failure') && !contains(join(needs.*.result, ','), 'cancelled') + steps: + - run: echo "All good" From a61455645d524df256661ee1278f8f9f40270253 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 25 Nov 2025 15:06:36 +0100 Subject: [PATCH 215/291] newcelltypes: init --- Makefile | 1 + kernel/newcelltypes.h | 435 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 436 insertions(+) create mode 100644 kernel/newcelltypes.h diff --git a/Makefile b/Makefile index 0a15c2b23..f6c37d613 100644 --- a/Makefile +++ b/Makefile @@ -613,6 +613,7 @@ $(eval $(call add_include_file,kernel/bitpattern.h)) $(eval $(call add_include_file,kernel/cellaigs.h)) $(eval $(call add_include_file,kernel/celledges.h)) $(eval $(call add_include_file,kernel/celltypes.h)) +$(eval $(call add_include_file,kernel/newcelltypes.h)) $(eval $(call add_include_file,kernel/consteval.h)) $(eval $(call add_include_file,kernel/constids.inc)) $(eval $(call add_include_file,kernel/cost.h)) diff --git a/kernel/newcelltypes.h b/kernel/newcelltypes.h new file mode 100644 index 000000000..1c0a2c2db --- /dev/null +++ b/kernel/newcelltypes.h @@ -0,0 +1,435 @@ +#ifndef NEWCELLTYPES_H +#define NEWCELLTYPES_H + +#include "kernel/yosys.h" + +YOSYS_NAMESPACE_BEGIN + +namespace TurboCellTypes { + +constexpr int MAX_CELLS = 300; +constexpr int MAX_PORTS = 10; +template +struct CellTableBuilder { + struct PortList { + std::array ports{}; + size_t count = 0; + constexpr PortList() = default; + constexpr PortList(std::initializer_list init) { + for (auto p : init) { + ports[count++] = p; + } + } + constexpr auto begin() const { return ports.begin(); } + constexpr auto end() const { return ports.begin() + count; } + constexpr size_t size() const { return count; } + }; + struct Features { + bool is_evaluable = false; + bool is_combinatorial = false; + bool is_synthesizable = false; + bool is_stdcell = false; + bool is_ff = false; + bool is_mem_noff = false; + bool is_anyinit = false; + bool is_tristate = false; + }; + struct CellInfo { + RTLIL::IdString type; + PortList inputs, outputs; + Features features; + }; + std::array cells{}; + size_t count = 0; + + constexpr void setup_type(RTLIL::IdString type, std::initializer_list inputs, std::initializer_list outputs, const Features& features) { + cells[count++] = {type, PortList(inputs), PortList(outputs), features}; + } + constexpr void setup_internals_eval() + { + Features features { + .is_evaluable = true, + }; + std::initializer_list unary_ops = { + ID($not), ID($pos), ID($buf), ID($neg), + ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), + ID($logic_not), ID($slice), ID($lut), ID($sop) + }; + + std::initializer_list binary_ops = { + ID($and), ID($or), ID($xor), ID($xnor), + ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx), + ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt), + ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow), + ID($logic_and), ID($logic_or), ID($concat), ID($macc), + ID($bweqx) + }; + + for (auto type : unary_ops) + setup_type(type, {ID::A}, {ID::Y}, features); + + for (auto type : binary_ops) + setup_type(type, {ID::A, ID::B}, {ID::Y}, features); + + for (auto type : {ID($mux), ID($pmux), ID($bwmux)}) + setup_type(type, {ID::A, ID::B, ID::S}, {ID::Y}, features); + + for (auto type : {ID($bmux), ID($demux)}) + setup_type(type, {ID::A, ID::S}, {ID::Y}, features); + + setup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, features); + setup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, features); + setup_type(ID($macc_v2), {ID::A, ID::B, ID::C}, {ID::Y}, features); + setup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, features); + } + constexpr void setup_internals_ff() + { + Features features { + .is_ff = true, + }; + setup_type(ID($sr), {ID::SET, ID::CLR}, {ID::Q}, features); + setup_type(ID($ff), {ID::D}, {ID::Q}, features); + setup_type(ID($dff), {ID::CLK, ID::D}, {ID::Q}, features); + setup_type(ID($dffe), {ID::CLK, ID::EN, ID::D}, {ID::Q}, features); + setup_type(ID($dffsr), {ID::CLK, ID::SET, ID::CLR, ID::D}, {ID::Q}, features); + setup_type(ID($dffsre), {ID::CLK, ID::SET, ID::CLR, ID::D, ID::EN}, {ID::Q}, features); + setup_type(ID($adff), {ID::CLK, ID::ARST, ID::D}, {ID::Q}, features); + setup_type(ID($adffe), {ID::CLK, ID::ARST, ID::D, ID::EN}, {ID::Q}, features); + setup_type(ID($aldff), {ID::CLK, ID::ALOAD, ID::AD, ID::D}, {ID::Q}, features); + setup_type(ID($aldffe), {ID::CLK, ID::ALOAD, ID::AD, ID::D, ID::EN}, {ID::Q}, features); + setup_type(ID($sdff), {ID::CLK, ID::SRST, ID::D}, {ID::Q}, features); + setup_type(ID($sdffe), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q}, features); + setup_type(ID($sdffce), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q}, features); + setup_type(ID($dlatch), {ID::EN, ID::D}, {ID::Q}, features); + setup_type(ID($adlatch), {ID::EN, ID::D, ID::ARST}, {ID::Q}, features); + setup_type(ID($dlatchsr), {ID::EN, ID::SET, ID::CLR, ID::D}, {ID::Q}, features); + } + constexpr void setup_internals_anyinit() + { + Features features { + .is_anyinit = true, + }; + setup_type(ID($anyinit), {ID::D}, {ID::Q}, features); + } + constexpr void setup_internals_mem_noff() + { + Features features { + .is_mem_noff = true, + }; + // NOT setup_internals_ff() + + setup_type(ID($memrd), {ID::CLK, ID::EN, ID::ADDR}, {ID::DATA}, features); + setup_type(ID($memrd_v2), {ID::CLK, ID::EN, ID::ARST, ID::SRST, ID::ADDR}, {ID::DATA}, features); + setup_type(ID($memwr), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, {}, features); + setup_type(ID($memwr_v2), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, {}, features); + setup_type(ID($meminit), {ID::ADDR, ID::DATA}, {}, features); + setup_type(ID($meminit_v2), {ID::ADDR, ID::DATA, ID::EN}, {}, features); + setup_type(ID($mem), {ID::RD_CLK, ID::RD_EN, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA}, features); + setup_type(ID($mem_v2), {ID::RD_CLK, ID::RD_EN, ID::RD_ARST, ID::RD_SRST, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA}, features); + + // What? + setup_type(ID($fsm), {ID::CLK, ID::ARST, ID::CTRL_IN}, {ID::CTRL_OUT}, features); + } + constexpr void setup_stdcells_tristate() + { + Features features { + .is_stdcell = true, + .is_tristate = true, + }; + setup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y}, features); + } + // TODO check correctness in unit test + constexpr void setup_stdcells_ff() { + Features features { + .is_stdcell = true, + .is_ff = true, + }; + + // for (auto c1 : list_np) + // for (auto c2 : list_np) + // setup_type(std::string("$_SR_") + c1 + c2 + "_", {ID::S, ID::R}, {ID::Q}, features); + setup_type(ID::$_SR_NN_, {ID::S, ID::R}, {ID::Q}, features); + setup_type(ID::$_SR_NP_, {ID::S, ID::R}, {ID::Q}, features); + setup_type(ID::$_SR_PN_, {ID::S, ID::R}, {ID::Q}, features); + setup_type(ID::$_SR_PP_, {ID::S, ID::R}, {ID::Q}, features); + + setup_type(ID($_FF_), {ID::D}, {ID::Q}, features); + + // for (auto c1 : list_np) + // setup_type(std::string("$_DFF_") + c1 + "_", {ID::C, ID::D}, {ID::Q}, features); + setup_type(ID::$_DFF_N_, {ID::C, ID::D}, {ID::Q}, features); + setup_type(ID::$_DFF_P_, {ID::C, ID::D}, {ID::Q}, features); + + // for (auto c1 : list_np) + // for (auto c2 : list_np) + // setup_type(std::string("$_DFFE_") + c1 + c2 + "_", {ID::C, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFE_NN_, {ID::C, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFE_NP_, {ID::C, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFE_PN_, {ID::C, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFE_PP_, {ID::C, ID::D, ID::E}, {ID::Q}, features); + // for (auto c1 : list_np) + // for (auto c2 : list_np) + // for (auto c3 : list_01) + // setup_type(std::string("$_DFF_") + c1 + c2 + c3 + "_", {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DFF_NN0_, {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DFF_NN1_, {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DFF_NP0_, {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DFF_NP1_, {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DFF_PN0_, {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DFF_PN1_, {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DFF_PP0_, {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DFF_PP1_, {ID::C, ID::R, ID::D}, {ID::Q}, features); + // for (auto c1 : list_np) + // for (auto c2 : list_np) + // for (auto c3 : list_01) + // for (auto c4 : list_np) + // setup_type(std::string("$_DFFE_") + c1 + c2 + c3 + c4 + "_", {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFE_NN0N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFE_NN0P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFE_NN1N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFE_NN1P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFE_NP0N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFE_NP0P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFE_NP1N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFE_NP1P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFE_PN0N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFE_PN0P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFE_PN1N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFE_PN1P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFE_PP0N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFE_PP0P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFE_PP1N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFE_PP1P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + // for (auto c1 : list_np) + // for (auto c2 : list_np) + // setup_type(std::string("$_ALDFF_") + c1 + c2 + "_", {ID::C, ID::L, ID::AD, ID::D}, {ID::Q}, features); + setup_type(ID::$_ALDFF_NN_, {ID::C, ID::L, ID::AD, ID::D}, {ID::Q}, features); + setup_type(ID::$_ALDFF_NP_, {ID::C, ID::L, ID::AD, ID::D}, {ID::Q}, features); + setup_type(ID::$_ALDFF_PN_, {ID::C, ID::L, ID::AD, ID::D}, {ID::Q}, features); + setup_type(ID::$_ALDFF_PP_, {ID::C, ID::L, ID::AD, ID::D}, {ID::Q}, features); + // for (auto c1 : list_np) + // for (auto c2 : list_np) + // for (auto c3 : list_np) + // setup_type(std::string("$_ALDFFE_") + c1 + c2 + c3 + "_", {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_ALDFFE_NNN_, {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_ALDFFE_NNP_, {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_ALDFFE_NPN_, {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_ALDFFE_NPP_, {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_ALDFFE_PNN_, {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_ALDFFE_PNP_, {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_ALDFFE_PPN_, {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_ALDFFE_PPP_, {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); + // for (auto c1 : list_np) + // for (auto c2 : list_np) + // for (auto c3 : list_np) + // setup_type(std::string("$_DFFSR_") + c1 + c2 + c3 + "_", {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DFFSR_NNN_, {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DFFSR_NNP_, {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DFFSR_NPN_, {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DFFSR_NPP_, {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DFFSR_PNN_, {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DFFSR_PNP_, {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DFFSR_PPN_, {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DFFSR_PPP_, {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); + // for (auto c1 : list_np) + // for (auto c2 : list_np) + // for (auto c3 : list_np) + // for (auto c4 : list_np) + // setup_type(std::string("$_DFFSRE_") + c1 + c2 + c3 + c4 + "_", {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFSRE_NNNN_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFSRE_NNNP_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFSRE_NNPN_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFSRE_NNPP_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFSRE_NPNN_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFSRE_NPNP_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFSRE_NPPN_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFSRE_NPPP_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFSRE_PNNN_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFSRE_PNNP_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFSRE_PNPN_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFSRE_PNPP_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFSRE_PPNN_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFSRE_PPNP_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFSRE_PPPN_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_DFFSRE_PPPP_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + // for (auto c1 : list_np) + // for (auto c2 : list_np) + // for (auto c3 : list_01) + // setup_type(std::string("$_SDFF_") + c1 + c2 + c3 + "_", {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_SDFF_NN0_, {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_SDFF_NN1_, {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_SDFF_NP0_, {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_SDFF_NP1_, {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_SDFF_PN0_, {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_SDFF_PN1_, {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_SDFF_PP0_, {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_SDFF_PP1_, {ID::C, ID::R, ID::D}, {ID::Q}, features); + // for (auto c1 : list_np) + // for (auto c2 : list_np) + // for (auto c3 : list_01) + // for (auto c4 : list_np) + // setup_type(std::string("$_SDFFE_") + c1 + c2 + c3 + c4 + "_", {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFE_NN0N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFE_NN0P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFE_NN1N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFE_NN1P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFE_NP0N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFE_NP0P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFE_NP1N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFE_NP1P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFE_PN0N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFE_PN0P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFE_PN1N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFE_PN1P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFE_PP0N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFE_PP0P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFE_PP1N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFE_PP1P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + // for (auto c1 : list_np) + // for (auto c2 : list_np) + // for (auto c3 : list_01) + // for (auto c4 : list_np) + // setup_type(std::string("$_SDFFCE_") + c1 + c2 + c3 + c4 + "_", {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFCE_NN0N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFCE_NN0P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFCE_NN1N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFCE_NN1P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFCE_NP0N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFCE_NP0P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFCE_NP1N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFCE_NP1P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFCE_PN0N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFCE_PN0P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFCE_PN1N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFCE_PN1P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFCE_PP0N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFCE_PP0P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFCE_PP1N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID::$_SDFFCE_PP1P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + // for (auto c1 : list_np) + // setup_type(std::string("$_DLATCH_") + c1 + "_", {ID::E, ID::D}, {ID::Q}, features); + setup_type(ID::$_DLATCH_N_, {ID::E, ID::D}, {ID::Q}, features); + setup_type(ID::$_DLATCH_P_, {ID::E, ID::D}, {ID::Q}, features); + + // for (auto c1 : list_np) + // for (auto c2 : list_np) + // for (auto c3 : list_01) + // setup_type(std::string("$_DLATCH_") + c1 + c2 + c3 + "_", {ID::E, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DLATCH_NN0_, {ID::E, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DLATCH_NN1_, {ID::E, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DLATCH_NP0_, {ID::E, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DLATCH_NP1_, {ID::E, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DLATCH_PN0_, {ID::E, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DLATCH_PN1_, {ID::E, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DLATCH_PP0_, {ID::E, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DLATCH_PP1_, {ID::E, ID::R, ID::D}, {ID::Q}, features); + // for (auto c1 : list_np) + // for (auto c2 : list_np) + // for (auto c3 : list_np) + // setup_type(std::string("$_DLATCHSR_") + c1 + c2 + c3 + "_", {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DLATCHSR_NNN_, {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DLATCHSR_NNP_, {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DLATCHSR_NPN_, {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DLATCHSR_NPP_, {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DLATCHSR_PNN_, {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DLATCHSR_PNP_, {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DLATCHSR_PPN_, {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID::$_DLATCHSR_PPP_, {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); + } + constexpr CellTableBuilder() { + setup_internals_eval(); + setup_internals_ff(); + setup_internals_anyinit(); + setup_internals_mem_noff(); + setup_stdcells_tristate(); + setup_stdcells_ff(); + // TODO + } + +}; + + +constexpr CellTableBuilder turbo_builder{}; + +struct Categories { + struct Category { + std::array data{}; + constexpr bool operator()(IdString type) const { + return data[type.index_]; + } + constexpr bool& operator[](size_t idx) { + return data[idx]; + } + // Optional: Helper to expose size + constexpr size_t size() const { return data.size(); } + }; + Category is_evaluable {}; + Category is_combinatorial {}; + Category is_synthesizable {}; + Category is_stdcell {}; + Category is_ff {}; + Category is_mem_noff {}; + Category is_anyinit {}; + Category is_tristate {}; + constexpr Categories() { + for (size_t i = 0; i < turbo_builder.count; ++i) { + auto& c = turbo_builder.cells[i]; + size_t idx = c.type.index_; + is_evaluable[idx] = c.features.is_evaluable; + is_combinatorial[idx] = c.features.is_combinatorial; + is_synthesizable[idx] = c.features.is_synthesizable; + is_stdcell[idx] = c.features.is_stdcell; + is_ff[idx] = c.features.is_ff; + is_mem_noff[idx] = c.features.is_mem_noff; + is_anyinit[idx] = c.features.is_anyinit; + is_tristate[idx] = c.features.is_tristate; + } + } + constexpr static Category join(Category left, Category right) { + Category c {}; + for (size_t i = 0; i < MAX_CELLS; ++i) { + c[i] = left[i] || right[i]; + } + return c; + } + constexpr static Category meet(Category left, Category right) { + Category c {}; + for (size_t i = 0; i < MAX_CELLS; ++i) { + c[i] = left[i] && right[i]; + } + return c; + } + constexpr static Category complement(Category old) { + Category c {}; + for (size_t i = 0; i < MAX_CELLS; ++i) { + c[i] = !old[i]; + } + return c; + } +}; + +// Pure +static constexpr Categories categories; + +// Legacy +namespace Compat { + static constexpr auto internals_all = Categories::complement(categories.is_stdcell); + static constexpr auto internals_mem_ff = Categories::meet(categories.is_ff, categories.is_mem_noff); + // auto stdcells_mem = Categories::meet(internals_all, categories.is_mem_noff); +}; + +namespace { + static_assert(categories.is_evaluable(ID($and))); + static_assert(!categories.is_ff(ID($and))); + static_assert(Categories::join(categories.is_evaluable, categories.is_ff)(ID($and))); + static_assert(Categories::join(categories.is_evaluable, categories.is_ff)(ID($dffsr))); + static_assert(!Categories::join(categories.is_evaluable, categories.is_ff)(ID($anyinit))); + +} + + + +}; +YOSYS_NAMESPACE_END + +#endif From 3671d577a0c9e2fc01c0eae53112c05eb0ef9093 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 25 Nov 2025 15:07:17 +0100 Subject: [PATCH 216/291] opt_clean: use newcelltypes --- passes/opt/opt_clean.cc | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index f1d21435c..bea514878 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -21,6 +21,7 @@ #include "kernel/sigtools.h" #include "kernel/log.h" #include "kernel/celltypes.h" +#include "kernel/newcelltypes.h" #include "kernel/ffinit.h" #include #include @@ -101,7 +102,10 @@ struct keep_cache_t }; keep_cache_t keep_cache; -CellTypes ct_reg, ct_all; +static constexpr auto ct_reg = TurboCellTypes::Categories::join( + TurboCellTypes::Compat::internals_mem_ff, + TurboCellTypes::categories.is_anyinit); +CellTypes ct_all; int count_rm_cells, count_rm_wires; void rmunused_module_cells(Module *module, bool verbose) @@ -310,10 +314,10 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos if (!purge_mode) for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; - if (ct_reg.cell_known(cell->type)) { + if (ct_reg(cell->type)) { bool clk2fflogic = cell->get_bool_attribute(ID(clk2fflogic)); for (auto &it2 : cell->connections()) - if (clk2fflogic ? it2.first == ID::D : ct_reg.cell_output(cell->type, it2.first)) + if (clk2fflogic ? it2.first == ID::D : ct_all.cell_output(cell->type, it2.first)) register_signals.add(it2.second); } for (auto &it2 : cell->connections()) @@ -517,14 +521,12 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos bool rmunused_module_init(RTLIL::Module *module, bool verbose) { bool did_something = false; - CellTypes fftypes; - fftypes.setup_internals_mem(); SigMap sigmap(module); dict qbits; for (auto cell : module->cells()) - if (fftypes.cell_known(cell->type) && cell->hasPort(ID::Q)) + if (TurboCellTypes::Compat::internals_mem_ff(cell->type) && cell->hasPort(ID::Q)) { SigSpec sig = cell->getPort(ID::Q); @@ -697,10 +699,6 @@ struct OptCleanPass : public Pass { keep_cache.reset(design, purge_mode); - ct_reg.setup_internals_mem(); - ct_reg.setup_internals_anyinit(); - ct_reg.setup_stdcells_mem(); - ct_all.setup(design); count_rm_cells = 0; @@ -719,7 +717,6 @@ struct OptCleanPass : public Pass { design->check(); keep_cache.reset(); - ct_reg.clear(); ct_all.clear(); log_pop(); @@ -760,10 +757,6 @@ struct CleanPass : public Pass { keep_cache.reset(design); - ct_reg.setup_internals_mem(); - ct_reg.setup_internals_anyinit(); - ct_reg.setup_stdcells_mem(); - ct_all.setup(design); count_rm_cells = 0; @@ -783,7 +776,6 @@ struct CleanPass : public Pass { design->check(); keep_cache.reset(); - ct_reg.clear(); ct_all.clear(); request_garbage_collection(); From 6adc08b0e5a48358de5a2577924da4f7872fa12f Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 25 Nov 2025 15:15:16 +0100 Subject: [PATCH 217/291] opt_expr: use newcelltypes --- kernel/newcelltypes.h | 2 +- passes/opt/opt_expr.cc | 10 ++++------ 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/kernel/newcelltypes.h b/kernel/newcelltypes.h index 1c0a2c2db..df1c13960 100644 --- a/kernel/newcelltypes.h +++ b/kernel/newcelltypes.h @@ -415,7 +415,7 @@ static constexpr Categories categories; namespace Compat { static constexpr auto internals_all = Categories::complement(categories.is_stdcell); static constexpr auto internals_mem_ff = Categories::meet(categories.is_ff, categories.is_mem_noff); - // auto stdcells_mem = Categories::meet(internals_all, categories.is_mem_noff); + static constexpr auto stdcells_mem = Categories::meet(categories.is_stdcell, categories.is_mem_noff); }; namespace { diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 7131053c9..f7e43beca 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -20,6 +20,7 @@ #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/celltypes.h" +#include "kernel/newcelltypes.h" #include "kernel/utils.h" #include "kernel/log.h" #include @@ -31,7 +32,7 @@ PRIVATE_NAMESPACE_BEGIN bool did_something; -void replace_undriven(RTLIL::Module *module, const CellTypes &ct) +void replace_undriven(RTLIL::Module *module, const NewCellTypes &ct) { SigMap sigmap(module); SigPool driven_signals; @@ -407,9 +408,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } - CellTypes ct_memcells; - ct_memcells.setup_stdcells_mem(); - if (!noclkinv) for (auto cell : module->cells()) if (design->selected(module, cell)) { @@ -433,7 +431,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (cell->type.in(ID($dffe), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce), ID($dffsre), ID($dlatch), ID($adlatch), ID($dlatchsr))) handle_polarity_inv(cell, ID::EN, ID::EN_POLARITY, assign_map, invert_map); - if (!ct_memcells.cell_known(cell->type)) + if (!TurboCellTypes::Compat::stdcells_mem(cell->type)) continue; handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", ID::S, assign_map, invert_map); @@ -2294,7 +2292,7 @@ struct OptExprPass : public Pass { } extra_args(args, argidx, design); - CellTypes ct(design); + NewCellTypes ct(design); for (auto module : design->selected_modules()) { log("Optimizing module %s.\n", log_id(module)); From 35ccaa60d710c1ccdb442386bcbc85a221017bab Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 25 Nov 2025 16:11:05 +0100 Subject: [PATCH 218/291] newcelltypes: TurboCellTypes -> StaticCellTypes --- kernel/newcelltypes.h | 2 +- passes/opt/opt_clean.cc | 8 ++++---- passes/opt/opt_expr.cc | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/kernel/newcelltypes.h b/kernel/newcelltypes.h index df1c13960..92c947439 100644 --- a/kernel/newcelltypes.h +++ b/kernel/newcelltypes.h @@ -5,7 +5,7 @@ YOSYS_NAMESPACE_BEGIN -namespace TurboCellTypes { +namespace StaticCellTypes { constexpr int MAX_CELLS = 300; constexpr int MAX_PORTS = 10; diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index bea514878..3afb77512 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -102,9 +102,9 @@ struct keep_cache_t }; keep_cache_t keep_cache; -static constexpr auto ct_reg = TurboCellTypes::Categories::join( - TurboCellTypes::Compat::internals_mem_ff, - TurboCellTypes::categories.is_anyinit); +static constexpr auto ct_reg = StaticCellTypes::Categories::join( + StaticCellTypes::Compat::mem_ff, + StaticCellTypes::categories.is_anyinit); CellTypes ct_all; int count_rm_cells, count_rm_wires; @@ -526,7 +526,7 @@ bool rmunused_module_init(RTLIL::Module *module, bool verbose) dict qbits; for (auto cell : module->cells()) - if (TurboCellTypes::Compat::internals_mem_ff(cell->type) && cell->hasPort(ID::Q)) + if (StaticCellTypes::Compat::internals_mem_ff(cell->type) && cell->hasPort(ID::Q)) { SigSpec sig = cell->getPort(ID::Q); diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index f7e43beca..2c040b09d 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -431,7 +431,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (cell->type.in(ID($dffe), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce), ID($dffsre), ID($dlatch), ID($adlatch), ID($dlatchsr))) handle_polarity_inv(cell, ID::EN, ID::EN_POLARITY, assign_map, invert_map); - if (!TurboCellTypes::Compat::stdcells_mem(cell->type)) + if (!StaticCellTypes::Compat::stdcells_mem(cell->type)) continue; handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", ID::S, assign_map, invert_map); From 9e59f05c258fbe95a8342dda4716124b775a32d9 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 25 Nov 2025 18:41:26 +0100 Subject: [PATCH 219/291] newcelltypes: wrap design celltypes support --- kernel/newcelltypes.h | 184 ++++++++++++++++++++++++++++++++++++---- passes/opt/opt_clean.cc | 2 +- 2 files changed, 168 insertions(+), 18 deletions(-) diff --git a/kernel/newcelltypes.h b/kernel/newcelltypes.h index 92c947439..0379eda05 100644 --- a/kernel/newcelltypes.h +++ b/kernel/newcelltypes.h @@ -1,6 +1,7 @@ #ifndef NEWCELLTYPES_H #define NEWCELLTYPES_H +#include "kernel/rtlil.h" #include "kernel/yosys.h" YOSYS_NAMESPACE_BEGIN @@ -9,7 +10,6 @@ namespace StaticCellTypes { constexpr int MAX_CELLS = 300; constexpr int MAX_PORTS = 10; -template struct CellTableBuilder { struct PortList { std::array ports{}; @@ -22,6 +22,14 @@ struct CellTableBuilder { } constexpr auto begin() const { return ports.begin(); } constexpr auto end() const { return ports.begin() + count; } + constexpr bool contains(RTLIL::IdString port) const { + for (size_t i = 0; i < count; i++) { + if (port == ports[i]) + return true; + } + + return false; + } constexpr size_t size() const { return count; } }; struct Features { @@ -349,7 +357,54 @@ struct CellTableBuilder { }; -constexpr CellTableBuilder turbo_builder{}; +constexpr CellTableBuilder turbo_builder{}; + +// template +// struct Worlds { +// struct World { +// std::array data{}; +// constexpr T operator()(IdString type) const { +// return data[type.index_]; +// } +// constexpr T& operator[](size_t idx) { +// return data[idx]; +// } +// constexpr size_t size() const { return data.size(); } +// }; +// World is_known {}; +// World is_evaluable {}; +// World is_combinatorial {}; +// World is_synthesizable {}; +// World is_stdcell {}; +// World is_ff {}; +// World is_mem_noff {}; +// World is_anyinit {}; +// World is_tristate {}; +// virtual constexpr Categories(); +// }; + +struct PortInfo { + struct PortLists { + std::array data{}; + constexpr CellTableBuilder::PortList operator()(IdString type) const { + return data[type.index_]; + } + constexpr CellTableBuilder::PortList& operator[](size_t idx) { + return data[idx]; + } + constexpr size_t size() const { return data.size(); } + }; + PortLists inputs {}; + PortLists outputs {}; + constexpr PortInfo() { + for (size_t i = 0; i < turbo_builder.count; ++i) { + auto& cell = turbo_builder.cells[i]; + size_t idx = cell.type.index_; + inputs[idx] = cell.inputs; + outputs[idx] = cell.outputs; + } + } +}; struct Categories { struct Category { @@ -360,9 +415,10 @@ struct Categories { constexpr bool& operator[](size_t idx) { return data[idx]; } - // Optional: Helper to expose size constexpr size_t size() const { return data.size(); } }; + Category empty {}; + Category is_known {}; Category is_evaluable {}; Category is_combinatorial {}; Category is_synthesizable {}; @@ -373,16 +429,17 @@ struct Categories { Category is_tristate {}; constexpr Categories() { for (size_t i = 0; i < turbo_builder.count; ++i) { - auto& c = turbo_builder.cells[i]; - size_t idx = c.type.index_; - is_evaluable[idx] = c.features.is_evaluable; - is_combinatorial[idx] = c.features.is_combinatorial; - is_synthesizable[idx] = c.features.is_synthesizable; - is_stdcell[idx] = c.features.is_stdcell; - is_ff[idx] = c.features.is_ff; - is_mem_noff[idx] = c.features.is_mem_noff; - is_anyinit[idx] = c.features.is_anyinit; - is_tristate[idx] = c.features.is_tristate; + auto& cell = turbo_builder.cells[i]; + size_t idx = cell.type.index_; + is_known[idx] = true; + is_evaluable[idx] = cell.features.is_evaluable; + is_combinatorial[idx] = cell.features.is_combinatorial; + is_synthesizable[idx] = cell.features.is_synthesizable; + is_stdcell[idx] = cell.features.is_stdcell; + is_ff[idx] = cell.features.is_ff; + is_mem_noff[idx] = cell.features.is_mem_noff; + is_anyinit[idx] = cell.features.is_anyinit; + is_tristate[idx] = cell.features.is_tristate; } } constexpr static Category join(Category left, Category right) { @@ -409,12 +466,13 @@ struct Categories { }; // Pure +static constexpr PortInfo port_info; static constexpr Categories categories; // Legacy namespace Compat { static constexpr auto internals_all = Categories::complement(categories.is_stdcell); - static constexpr auto internals_mem_ff = Categories::meet(categories.is_ff, categories.is_mem_noff); + static constexpr auto internals_mem_ff = Categories::join(categories.is_ff, categories.is_mem_noff); static constexpr auto stdcells_mem = Categories::meet(categories.is_stdcell, categories.is_mem_noff); }; @@ -424,12 +482,104 @@ namespace { static_assert(Categories::join(categories.is_evaluable, categories.is_ff)(ID($and))); static_assert(Categories::join(categories.is_evaluable, categories.is_ff)(ID($dffsr))); static_assert(!Categories::join(categories.is_evaluable, categories.is_ff)(ID($anyinit))); - } - - }; + +struct NewCellType { + RTLIL::IdString type; + pool inputs, outputs; + bool is_evaluable; + bool is_combinatorial; + bool is_synthesizable; +}; + +struct NewCellTypes { + StaticCellTypes::Categories::Category static_cell_types = StaticCellTypes::categories.empty; + dict custom_cell_types; + + NewCellTypes() { + } + + NewCellTypes(RTLIL::Design *design) { + setup(design); + } + void setup(RTLIL::Design *design = NULL) { + if (design) + setup_design(design); + + } + void setup_design(RTLIL::Design *design) { + for (auto module : design->modules()) + setup_module(module); + static_cell_types = StaticCellTypes::categories.is_known; + } + + void setup_module(RTLIL::Module *module) { + pool inputs, outputs; + for (RTLIL::IdString wire_name : module->ports) { + RTLIL::Wire *wire = module->wire(wire_name); + if (wire->port_input) + inputs.insert(wire->name); + if (wire->port_output) + outputs.insert(wire->name); + } + setup_type(module->name, inputs, outputs); + } + + void setup_type(RTLIL::IdString type, const pool &inputs, const pool &outputs, bool is_evaluable = false, bool is_combinatorial = false, bool is_synthesizable = false) { + NewCellType ct = {type, inputs, outputs, is_evaluable, is_combinatorial, is_synthesizable}; + custom_cell_types[ct.type] = ct; + } + + void clear() { + custom_cell_types.clear(); + static_cell_types = StaticCellTypes::categories.empty; + } + + bool cell_known(const RTLIL::IdString &type) const { + return static_cell_types(type) || custom_cell_types.count(type) != 0; + } + + bool cell_output(const RTLIL::IdString &type, const RTLIL::IdString &port) const + { + if (static_cell_types(type) && StaticCellTypes::port_info.outputs(type).contains(port)) { + return true; + } + auto it = custom_cell_types.find(type); + return it != custom_cell_types.end() && it->second.outputs.count(port) != 0; + } + + bool cell_input(const RTLIL::IdString &type, const RTLIL::IdString &port) const + { + if (static_cell_types(type) && StaticCellTypes::port_info.inputs(type).contains(port)) { + return true; + } + auto it = custom_cell_types.find(type); + return it != custom_cell_types.end() && it->second.inputs.count(port) != 0; + } + + RTLIL::PortDir cell_port_dir(RTLIL::IdString type, RTLIL::IdString port) const + { + bool is_input, is_output; + if (static_cell_types(type)) { + is_input = StaticCellTypes::port_info.inputs(type).contains(port); + is_output = StaticCellTypes::port_info.outputs(type).contains(port); + } else { + auto it = custom_cell_types.find(type); + if (it == custom_cell_types.end()) + return RTLIL::PD_UNKNOWN; + is_input = it->second.inputs.count(port); + is_output = it->second.outputs.count(port); + } + return RTLIL::PortDir(is_input + is_output * 2); + } + bool cell_evaluable(const RTLIL::IdString &type) const + { + return static_cell_types(type) && StaticCellTypes::categories.is_evaluable(type); + } +}; + YOSYS_NAMESPACE_END #endif diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 3afb77512..72d22ddd3 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -105,7 +105,7 @@ keep_cache_t keep_cache; static constexpr auto ct_reg = StaticCellTypes::Categories::join( StaticCellTypes::Compat::mem_ff, StaticCellTypes::categories.is_anyinit); -CellTypes ct_all; +NewCellTypes ct_all; int count_rm_cells, count_rm_wires; void rmunused_module_cells(Module *module, bool verbose) From 7e9e88c2ec49fbdd91e12a625c01476336ed3b57 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 25 Nov 2025 19:06:46 +0100 Subject: [PATCH 220/291] newcelltypes: bounds check --- kernel/newcelltypes.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/kernel/newcelltypes.h b/kernel/newcelltypes.h index 0379eda05..b25a690ca 100644 --- a/kernel/newcelltypes.h +++ b/kernel/newcelltypes.h @@ -410,7 +410,10 @@ struct Categories { struct Category { std::array data{}; constexpr bool operator()(IdString type) const { - return data[type.index_]; + size_t idx = type.index_; + if (idx >= MAX_CELLS) + return false; + return data[idx]; } constexpr bool& operator[](size_t idx) { return data[idx]; @@ -496,12 +499,14 @@ struct NewCellType { struct NewCellTypes { StaticCellTypes::Categories::Category static_cell_types = StaticCellTypes::categories.empty; - dict custom_cell_types; + dict custom_cell_types = {}; NewCellTypes() { + static_cell_types = StaticCellTypes::categories.empty; } NewCellTypes(RTLIL::Design *design) { + static_cell_types = StaticCellTypes::categories.empty; setup(design); } void setup(RTLIL::Design *design = NULL) { From 2d7d6ca10b3d47797e4bff017d37aaec9853f02c Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 25 Nov 2025 20:08:26 +0100 Subject: [PATCH 221/291] newcelltypes: unit test --- tests/unit/kernel/cellTypesTest.cc | 37 ++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 tests/unit/kernel/cellTypesTest.cc diff --git a/tests/unit/kernel/cellTypesTest.cc b/tests/unit/kernel/cellTypesTest.cc new file mode 100644 index 000000000..1743ef7a0 --- /dev/null +++ b/tests/unit/kernel/cellTypesTest.cc @@ -0,0 +1,37 @@ +#include +#include "kernel/yosys.h" +#include "kernel/yosys_common.h" +#include "kernel/celltypes.h" +#include "kernel/newcelltypes.h" + +#include + +YOSYS_NAMESPACE_BEGIN + +TEST(CellTypesTest, basic) +{ + yosys_setup(); + log_files.push_back(stdout); + CellTypes older; + NewCellTypes newer; + log("setup nullptr\n"); + older.setup(nullptr); + newer.setup(nullptr); + log("setup type bleh\n"); + older.setup_type(ID(bleh), {ID::G}, {ID::H, ID::I}, false, true); + newer.setup_type(ID(bleh), {ID::G}, {ID::H, ID::I}, false, true); + + EXPECT_EQ(older.cell_known(ID(aaaaa)), newer.cell_known(ID(aaaaa))); + EXPECT_EQ(older.cell_known(ID($and)), newer.cell_known(ID($and))); + for (size_t i = 0; i < 1000; i++) { + IdString type; + type.index_ = i; + if (older.cell_known(type) != newer.cell_known(type)) + std::cout << i << " " << type.str() << "\n"; + EXPECT_EQ(older.cell_known(type), newer.cell_known(type)); + + } + yosys_shutdown(); +} + +YOSYS_NAMESPACE_END From 3212dfaf1f98d92111ccd5b58bfe752f412b209b Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 25 Nov 2025 20:08:41 +0100 Subject: [PATCH 222/291] newcelltypes: fix unit test --- kernel/newcelltypes.h | 316 +++++++++++++++++++++++++----------------- kernel/rtlil.cc | 1 + 2 files changed, 190 insertions(+), 127 deletions(-) diff --git a/kernel/newcelltypes.h b/kernel/newcelltypes.h index b25a690ca..b537139e7 100644 --- a/kernel/newcelltypes.h +++ b/kernel/newcelltypes.h @@ -8,8 +8,10 @@ YOSYS_NAMESPACE_BEGIN namespace StaticCellTypes { +// Given by last internal cell type IdString constids.inc, compilation error if too low constexpr int MAX_CELLS = 300; -constexpr int MAX_PORTS = 10; +// Currently given by _MUX16_, compilation error if too low +constexpr int MAX_PORTS = 20; struct CellTableBuilder { struct PortList { std::array ports{}; @@ -53,6 +55,39 @@ struct CellTableBuilder { constexpr void setup_type(RTLIL::IdString type, std::initializer_list inputs, std::initializer_list outputs, const Features& features) { cells[count++] = {type, PortList(inputs), PortList(outputs), features}; } + constexpr void setup_internals_other() + { + Features features { + .is_tristate = true, + }; + setup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y}, features); + + features = {}; + setup_type(ID($assert), {ID::A, ID::EN}, {}, features); + setup_type(ID($assume), {ID::A, ID::EN}, {}, features); + setup_type(ID($live), {ID::A, ID::EN}, {}, features); + setup_type(ID($fair), {ID::A, ID::EN}, {}, features); + setup_type(ID($cover), {ID::A, ID::EN}, {}, features); + setup_type(ID($initstate), {}, {ID::Y}, features); + setup_type(ID($anyconst), {}, {ID::Y}, features); + setup_type(ID($anyseq), {}, {ID::Y}, features); + setup_type(ID($allconst), {}, {ID::Y}, features); + setup_type(ID($allseq), {}, {ID::Y}, features); + setup_type(ID($equiv), {ID::A, ID::B}, {ID::Y}, features); + setup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, {}, features); + setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, {}, features); + setup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, {}, features); + setup_type(ID($print), {ID::EN, ID::ARGS, ID::TRG}, {}, features); + setup_type(ID($check), {ID::A, ID::EN, ID::ARGS, ID::TRG}, {}, features); + setup_type(ID($set_tag), {ID::A, ID::SET, ID::CLR}, {ID::Y}, features); + setup_type(ID($get_tag), {ID::A}, {ID::Y}, features); + setup_type(ID($overwrite_tag), {ID::A, ID::SET, ID::CLR}, {}, features); + setup_type(ID($original_tag), {ID::A}, {ID::Y}, features); + setup_type(ID($future_ff), {ID::A}, {ID::Y}, features); + setup_type(ID($scopeinfo), {}, {}, features); + setup_type(ID($input_port), {}, {ID::Y}, features); + setup_type(ID($connect), {ID::A, ID::B}, {}, features); + } constexpr void setup_internals_eval() { Features features { @@ -146,7 +181,34 @@ struct CellTableBuilder { }; setup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y}, features); } - // TODO check correctness in unit test + + constexpr void setup_stdcells_eval() + { + Features features { + .is_evaluable = true, + .is_stdcell = true, + }; + setup_type(ID($_BUF_), {ID::A}, {ID::Y}, features); + setup_type(ID($_NOT_), {ID::A}, {ID::Y}, features); + setup_type(ID($_AND_), {ID::A, ID::B}, {ID::Y}, features); + setup_type(ID($_NAND_), {ID::A, ID::B}, {ID::Y}, features); + setup_type(ID($_OR_), {ID::A, ID::B}, {ID::Y}, features); + setup_type(ID($_NOR_), {ID::A, ID::B}, {ID::Y}, features); + setup_type(ID($_XOR_), {ID::A, ID::B}, {ID::Y}, features); + setup_type(ID($_XNOR_), {ID::A, ID::B}, {ID::Y}, features); + setup_type(ID($_ANDNOT_), {ID::A, ID::B}, {ID::Y}, features); + setup_type(ID($_ORNOT_), {ID::A, ID::B}, {ID::Y}, features); + setup_type(ID($_MUX_), {ID::A, ID::B, ID::S}, {ID::Y}, features); + setup_type(ID($_NMUX_), {ID::A, ID::B, ID::S}, {ID::Y}, features); + setup_type(ID($_MUX4_), {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T}, {ID::Y}, features); + setup_type(ID($_MUX8_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U}, {ID::Y}, features); + setup_type(ID($_MUX16_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K, ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V}, {ID::Y}, features); + setup_type(ID($_AOI3_), {ID::A, ID::B, ID::C}, {ID::Y}, features); + setup_type(ID($_OAI3_), {ID::A, ID::B, ID::C}, {ID::Y}, features); + setup_type(ID($_AOI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, features); + setup_type(ID($_OAI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, features); + } + constexpr void setup_stdcells_ff() { Features features { .is_stdcell = true, @@ -156,10 +218,10 @@ struct CellTableBuilder { // for (auto c1 : list_np) // for (auto c2 : list_np) // setup_type(std::string("$_SR_") + c1 + c2 + "_", {ID::S, ID::R}, {ID::Q}, features); - setup_type(ID::$_SR_NN_, {ID::S, ID::R}, {ID::Q}, features); - setup_type(ID::$_SR_NP_, {ID::S, ID::R}, {ID::Q}, features); - setup_type(ID::$_SR_PN_, {ID::S, ID::R}, {ID::Q}, features); - setup_type(ID::$_SR_PP_, {ID::S, ID::R}, {ID::Q}, features); + setup_type(ID($_SR_NN_), {ID::S, ID::R}, {ID::Q}, features); + setup_type(ID($_SR_NP_), {ID::S, ID::R}, {ID::Q}, features); + setup_type(ID($_SR_PN_), {ID::S, ID::R}, {ID::Q}, features); + setup_type(ID($_SR_PP_), {ID::S, ID::R}, {ID::Q}, features); setup_type(ID($_FF_), {ID::D}, {ID::Q}, features); @@ -179,179 +241,180 @@ struct CellTableBuilder { // for (auto c2 : list_np) // for (auto c3 : list_01) // setup_type(std::string("$_DFF_") + c1 + c2 + c3 + "_", {ID::C, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DFF_NN0_, {ID::C, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DFF_NN1_, {ID::C, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DFF_NP0_, {ID::C, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DFF_NP1_, {ID::C, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DFF_PN0_, {ID::C, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DFF_PN1_, {ID::C, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DFF_PP0_, {ID::C, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DFF_PP1_, {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DFF_NN0_), {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DFF_NN1_), {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DFF_NP0_), {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DFF_NP1_), {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DFF_PN0_), {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DFF_PN1_), {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DFF_PP0_), {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DFF_PP1_), {ID::C, ID::R, ID::D}, {ID::Q}, features); // for (auto c1 : list_np) // for (auto c2 : list_np) // for (auto c3 : list_01) // for (auto c4 : list_np) // setup_type(std::string("$_DFFE_") + c1 + c2 + c3 + c4 + "_", {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFE_NN0N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFE_NN0P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFE_NN1N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFE_NN1P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFE_NP0N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFE_NP0P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFE_NP1N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFE_NP1P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFE_PN0N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFE_PN0P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFE_PN1N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFE_PN1P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFE_PP0N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFE_PP0P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFE_PP1N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFE_PP1P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFE_NN0N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFE_NN0P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFE_NN1N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFE_NN1P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFE_NP0N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFE_NP0P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFE_NP1N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFE_NP1P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFE_PN0N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFE_PN0P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFE_PN1N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFE_PN1P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFE_PP0N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFE_PP0P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFE_PP1N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFE_PP1P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); // for (auto c1 : list_np) // for (auto c2 : list_np) // setup_type(std::string("$_ALDFF_") + c1 + c2 + "_", {ID::C, ID::L, ID::AD, ID::D}, {ID::Q}, features); - setup_type(ID::$_ALDFF_NN_, {ID::C, ID::L, ID::AD, ID::D}, {ID::Q}, features); - setup_type(ID::$_ALDFF_NP_, {ID::C, ID::L, ID::AD, ID::D}, {ID::Q}, features); - setup_type(ID::$_ALDFF_PN_, {ID::C, ID::L, ID::AD, ID::D}, {ID::Q}, features); - setup_type(ID::$_ALDFF_PP_, {ID::C, ID::L, ID::AD, ID::D}, {ID::Q}, features); + setup_type(ID($_ALDFF_NN_), {ID::C, ID::L, ID::AD, ID::D}, {ID::Q}, features); + setup_type(ID($_ALDFF_NP_), {ID::C, ID::L, ID::AD, ID::D}, {ID::Q}, features); + setup_type(ID($_ALDFF_PN_), {ID::C, ID::L, ID::AD, ID::D}, {ID::Q}, features); + setup_type(ID($_ALDFF_PP_), {ID::C, ID::L, ID::AD, ID::D}, {ID::Q}, features); // for (auto c1 : list_np) // for (auto c2 : list_np) // for (auto c3 : list_np) // setup_type(std::string("$_ALDFFE_") + c1 + c2 + c3 + "_", {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_ALDFFE_NNN_, {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_ALDFFE_NNP_, {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_ALDFFE_NPN_, {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_ALDFFE_NPP_, {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_ALDFFE_PNN_, {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_ALDFFE_PNP_, {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_ALDFFE_PPN_, {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_ALDFFE_PPP_, {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_ALDFFE_NNN_), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_ALDFFE_NNP_), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_ALDFFE_NPN_), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_ALDFFE_NPP_), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_ALDFFE_PNN_), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_ALDFFE_PNP_), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_ALDFFE_PPN_), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_ALDFFE_PPP_), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features); // for (auto c1 : list_np) // for (auto c2 : list_np) // for (auto c3 : list_np) // setup_type(std::string("$_DFFSR_") + c1 + c2 + c3 + "_", {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DFFSR_NNN_, {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DFFSR_NNP_, {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DFFSR_NPN_, {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DFFSR_NPP_, {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DFFSR_PNN_, {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DFFSR_PNP_, {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DFFSR_PPN_, {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DFFSR_PPP_, {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DFFSR_NNN_), {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DFFSR_NNP_), {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DFFSR_NPN_), {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DFFSR_NPP_), {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DFFSR_PNN_), {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DFFSR_PNP_), {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DFFSR_PPN_), {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DFFSR_PPP_), {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features); // for (auto c1 : list_np) // for (auto c2 : list_np) // for (auto c3 : list_np) // for (auto c4 : list_np) // setup_type(std::string("$_DFFSRE_") + c1 + c2 + c3 + c4 + "_", {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFSRE_NNNN_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFSRE_NNNP_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFSRE_NNPN_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFSRE_NNPP_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFSRE_NPNN_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFSRE_NPNP_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFSRE_NPPN_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFSRE_NPPP_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFSRE_PNNN_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFSRE_PNNP_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFSRE_PNPN_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFSRE_PNPP_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFSRE_PPNN_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFSRE_PPNP_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFSRE_PPPN_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_DFFSRE_PPPP_, {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFSRE_NNNN_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFSRE_NNNP_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFSRE_NNPN_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFSRE_NNPP_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFSRE_NPNN_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFSRE_NPNP_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFSRE_NPPN_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFSRE_NPPP_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFSRE_PNNN_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFSRE_PNNP_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFSRE_PNPN_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFSRE_PNPP_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFSRE_PPNN_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFSRE_PPNP_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFSRE_PPPN_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_DFFSRE_PPPP_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features); // for (auto c1 : list_np) // for (auto c2 : list_np) // for (auto c3 : list_01) // setup_type(std::string("$_SDFF_") + c1 + c2 + c3 + "_", {ID::C, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_SDFF_NN0_, {ID::C, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_SDFF_NN1_, {ID::C, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_SDFF_NP0_, {ID::C, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_SDFF_NP1_, {ID::C, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_SDFF_PN0_, {ID::C, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_SDFF_PN1_, {ID::C, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_SDFF_PP0_, {ID::C, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_SDFF_PP1_, {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_SDFF_NN0_), {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_SDFF_NN1_), {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_SDFF_NP0_), {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_SDFF_NP1_), {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_SDFF_PN0_), {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_SDFF_PN1_), {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_SDFF_PP0_), {ID::C, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_SDFF_PP1_), {ID::C, ID::R, ID::D}, {ID::Q}, features); // for (auto c1 : list_np) // for (auto c2 : list_np) // for (auto c3 : list_01) // for (auto c4 : list_np) // setup_type(std::string("$_SDFFE_") + c1 + c2 + c3 + c4 + "_", {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFE_NN0N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFE_NN0P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFE_NN1N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFE_NN1P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFE_NP0N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFE_NP0P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFE_NP1N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFE_NP1P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFE_PN0N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFE_PN0P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFE_PN1N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFE_PN1P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFE_PP0N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFE_PP0P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFE_PP1N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFE_PP1P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFE_NN0N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFE_NN0P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFE_NN1N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFE_NN1P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFE_NP0N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFE_NP0P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFE_NP1N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFE_NP1P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFE_PN0N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFE_PN0P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFE_PN1N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFE_PN1P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFE_PP0N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFE_PP0P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFE_PP1N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFE_PP1P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); // for (auto c1 : list_np) // for (auto c2 : list_np) // for (auto c3 : list_01) // for (auto c4 : list_np) // setup_type(std::string("$_SDFFCE_") + c1 + c2 + c3 + c4 + "_", {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFCE_NN0N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFCE_NN0P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFCE_NN1N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFCE_NN1P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFCE_NP0N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFCE_NP0P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFCE_NP1N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFCE_NP1P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFCE_PN0N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFCE_PN0P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFCE_PN1N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFCE_PN1P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFCE_PP0N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFCE_PP0P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFCE_PP1N_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); - setup_type(ID::$_SDFFCE_PP1P_, {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFCE_NN0N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFCE_NN0P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFCE_NN1N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFCE_NN1P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFCE_NP0N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFCE_NP0P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFCE_NP1N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFCE_NP1P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFCE_PN0N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFCE_PN0P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFCE_PN1N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFCE_PN1P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFCE_PP0N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFCE_PP0P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFCE_PP1N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); + setup_type(ID($_SDFFCE_PP1P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features); // for (auto c1 : list_np) // setup_type(std::string("$_DLATCH_") + c1 + "_", {ID::E, ID::D}, {ID::Q}, features); - setup_type(ID::$_DLATCH_N_, {ID::E, ID::D}, {ID::Q}, features); - setup_type(ID::$_DLATCH_P_, {ID::E, ID::D}, {ID::Q}, features); + setup_type(ID($_DLATCH_N_), {ID::E, ID::D}, {ID::Q}, features); + setup_type(ID($_DLATCH_P_), {ID::E, ID::D}, {ID::Q}, features); // for (auto c1 : list_np) // for (auto c2 : list_np) // for (auto c3 : list_01) // setup_type(std::string("$_DLATCH_") + c1 + c2 + c3 + "_", {ID::E, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DLATCH_NN0_, {ID::E, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DLATCH_NN1_, {ID::E, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DLATCH_NP0_, {ID::E, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DLATCH_NP1_, {ID::E, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DLATCH_PN0_, {ID::E, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DLATCH_PN1_, {ID::E, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DLATCH_PP0_, {ID::E, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DLATCH_PP1_, {ID::E, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DLATCH_NN0_), {ID::E, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DLATCH_NN1_), {ID::E, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DLATCH_NP0_), {ID::E, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DLATCH_NP1_), {ID::E, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DLATCH_PN0_), {ID::E, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DLATCH_PN1_), {ID::E, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DLATCH_PP0_), {ID::E, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DLATCH_PP1_), {ID::E, ID::R, ID::D}, {ID::Q}, features); // for (auto c1 : list_np) // for (auto c2 : list_np) // for (auto c3 : list_np) // setup_type(std::string("$_DLATCHSR_") + c1 + c2 + c3 + "_", {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DLATCHSR_NNN_, {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DLATCHSR_NNP_, {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DLATCHSR_NPN_, {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DLATCHSR_NPP_, {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DLATCHSR_PNN_, {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DLATCHSR_PNP_, {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DLATCHSR_PPN_, {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); - setup_type(ID::$_DLATCHSR_PPP_, {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DLATCHSR_NNN_), {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DLATCHSR_NNP_), {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DLATCHSR_NPN_), {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DLATCHSR_NPP_), {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DLATCHSR_PNN_), {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DLATCHSR_PNP_), {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DLATCHSR_PPN_), {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); + setup_type(ID($_DLATCHSR_PPP_), {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features); } constexpr CellTableBuilder() { + setup_internals_other(); setup_internals_eval(); setup_internals_ff(); setup_internals_anyinit(); setup_internals_mem_noff(); setup_stdcells_tristate(); + setup_stdcells_eval(); setup_stdcells_ff(); - // TODO } }; @@ -512,12 +575,11 @@ struct NewCellTypes { void setup(RTLIL::Design *design = NULL) { if (design) setup_design(design); - + static_cell_types = StaticCellTypes::categories.is_known; } void setup_design(RTLIL::Design *design) { for (auto module : design->modules()) setup_module(module); - static_cell_types = StaticCellTypes::categories.is_known; } void setup_module(RTLIL::Module *module) { diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index eef1c319d..c59c0b1f7 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -288,6 +288,7 @@ void RTLIL::OwningIdString::collect_garbage() dict RTLIL::constpad; +// TODO take a look static const pool &builtin_ff_cell_types_internal() { static const pool res = { ID($sr), From 07ec8708e41d0b6ca42f6948cac7ae24387a6726 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 25 Nov 2025 20:17:27 +0100 Subject: [PATCH 223/291] share: use newcelltypes --- kernel/newcelltypes.h | 9 ++++ passes/opt/share.cc | 114 ++++++++++++++++++------------------------ 2 files changed, 59 insertions(+), 64 deletions(-) diff --git a/kernel/newcelltypes.h b/kernel/newcelltypes.h index b537139e7..6f520d891 100644 --- a/kernel/newcelltypes.h +++ b/kernel/newcelltypes.h @@ -481,6 +481,15 @@ struct Categories { constexpr bool& operator[](size_t idx) { return data[idx]; } + constexpr void set_id(IdString type, bool val = true) { + size_t idx = type.index_; + if (idx >= MAX_CELLS) + return; // TODO should be an assert but then it's not constexpr + data[idx] = val; + } + constexpr void set(size_t idx, bool val = true) { + data[idx] = val; + } constexpr size_t size() const { return data.size(); } }; Category empty {}; diff --git a/passes/opt/share.cc b/passes/opt/share.cc index 307cd299b..f7843cc08 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -23,6 +23,7 @@ #include "kernel/modtools.h" #include "kernel/utils.h" #include "kernel/macc.h" +#include "kernel/newcelltypes.h" #include USING_YOSYS_NAMESPACE @@ -38,19 +39,18 @@ struct ShareWorkerConfig bool opt_force; bool opt_aggressive; bool opt_fast; - pool generic_uni_ops, generic_bin_ops, generic_cbin_ops, generic_other_ops; + StaticCellTypes::Categories::Category generic_uni_ops, generic_bin_ops, generic_cbin_ops, generic_other_ops; }; struct ShareWorker { const ShareWorkerConfig config; int limit; - pool generic_ops; + StaticCellTypes::Categories::Category generic_ops; RTLIL::Design *design; RTLIL::Module *module; - CellTypes fwd_ct, cone_ct; ModWalker modwalker; pool cells_to_remove; @@ -75,7 +75,7 @@ struct ShareWorker queue_bits.insert(modwalker.signal_outputs.begin(), modwalker.signal_outputs.end()); for (auto &it : module->cells_) - if (!fwd_ct.cell_known(it.second->type)) { + if (!StaticCellTypes::Compat::internals_nomem_noff(it.second->type)) { pool &bits = modwalker.cell_inputs[it.second]; queue_bits.insert(bits.begin(), bits.end()); } @@ -95,7 +95,7 @@ struct ShareWorker queue_bits.insert(bits.begin(), bits.end()); visited_cells.insert(pbit.cell); } - if (fwd_ct.cell_known(pbit.cell->type) && visited_cells.count(pbit.cell) == 0) { + if (StaticCellTypes::Compat::internals_nomem_noff(pbit.cell->type) && visited_cells.count(pbit.cell) == 0) { pool &bits = modwalker.cell_inputs[pbit.cell]; terminal_bits.insert(bits.begin(), bits.end()); queue_bits.insert(bits.begin(), bits.end()); @@ -388,7 +388,7 @@ struct ShareWorker continue; } - if (generic_ops.count(cell->type)) { + if (generic_ops(cell->type)) { if (config.opt_aggressive) shareable_cells.insert(cell); continue; @@ -412,7 +412,7 @@ struct ShareWorker return true; } - if (config.generic_uni_ops.count(c1->type)) + if (config.generic_uni_ops(c1->type)) { if (!config.opt_aggressive) { @@ -429,7 +429,7 @@ struct ShareWorker return true; } - if (config.generic_bin_ops.count(c1->type) || c1->type == ID($alu)) + if (config.generic_bin_ops(c1->type) || c1->type == ID($alu)) { if (!config.opt_aggressive) { @@ -449,7 +449,7 @@ struct ShareWorker return true; } - if (config.generic_cbin_ops.count(c1->type)) + if (config.generic_cbin_ops(c1->type)) { if (!config.opt_aggressive) { @@ -511,7 +511,7 @@ struct ShareWorker { log_assert(c1->type == c2->type); - if (config.generic_uni_ops.count(c1->type)) + if (config.generic_uni_ops(c1->type)) { if (c1->parameters.at(ID::A_SIGNED).as_bool() != c2->parameters.at(ID::A_SIGNED).as_bool()) { @@ -560,11 +560,11 @@ struct ShareWorker return supercell; } - if (config.generic_bin_ops.count(c1->type) || config.generic_cbin_ops.count(c1->type) || c1->type == ID($alu)) + if (config.generic_bin_ops(c1->type) || config.generic_cbin_ops(c1->type) || c1->type == ID($alu)) { bool modified_src_cells = false; - if (config.generic_cbin_ops.count(c1->type)) + if (config.generic_cbin_ops(c1->type)) { int score_unflipped = max(c1->parameters.at(ID::A_WIDTH).as_int(), c2->parameters.at(ID::A_WIDTH).as_int()) + max(c1->parameters.at(ID::B_WIDTH).as_int(), c2->parameters.at(ID::B_WIDTH).as_int()); @@ -758,7 +758,7 @@ struct ShareWorker recursion_state.insert(cell); for (auto c : consumer_cells) - if (fwd_ct.cell_known(c->type)) { + if (StaticCellTypes::Compat::internals_nomem_noff(c->type)) { const pool &bits = find_forbidden_controls(c); forbidden_controls_cache[cell].insert(bits.begin(), bits.end()); } @@ -897,7 +897,7 @@ struct ShareWorker return activation_patterns_cache.at(cell); } for (auto &pbit : modwalker.signal_consumers[bit]) { - log_assert(fwd_ct.cell_known(pbit.cell->type)); + log_assert(StaticCellTypes::Compat::internals_nomem_noff(pbit.cell->type)); if ((pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) && (pbit.port == ID::A || pbit.port == ID::B)) driven_data_muxes.insert(pbit.cell); else @@ -1214,24 +1214,10 @@ struct ShareWorker ShareWorker(ShareWorkerConfig config, RTLIL::Design* design) : config(config), design(design), modwalker(design) { - generic_ops.insert(config.generic_uni_ops.begin(), config.generic_uni_ops.end()); - generic_ops.insert(config.generic_bin_ops.begin(), config.generic_bin_ops.end()); - generic_ops.insert(config.generic_cbin_ops.begin(), config.generic_cbin_ops.end()); - generic_ops.insert(config.generic_other_ops.begin(), config.generic_other_ops.end()); - - fwd_ct.setup_internals(); - - cone_ct.setup_internals(); - cone_ct.cell_types.erase(ID($mul)); - cone_ct.cell_types.erase(ID($mod)); - cone_ct.cell_types.erase(ID($div)); - cone_ct.cell_types.erase(ID($modfloor)); - cone_ct.cell_types.erase(ID($divfloor)); - cone_ct.cell_types.erase(ID($pow)); - cone_ct.cell_types.erase(ID($shl)); - cone_ct.cell_types.erase(ID($shr)); - cone_ct.cell_types.erase(ID($sshl)); - cone_ct.cell_types.erase(ID($sshr)); + generic_ops = StaticCellTypes::Categories::join(generic_ops, config.generic_uni_ops); + generic_ops = StaticCellTypes::Categories::join(generic_ops, config.generic_bin_ops); + generic_ops = StaticCellTypes::Categories::join(generic_ops, config.generic_cbin_ops); + generic_ops = StaticCellTypes::Categories::join(generic_ops, config.generic_other_ops); } void operator()(RTLIL::Module *module) { @@ -1561,45 +1547,45 @@ struct SharePass : public Pass { config.opt_aggressive = false; config.opt_fast = false; - config.generic_uni_ops.insert(ID($not)); - // config.generic_uni_ops.insert(ID($pos)); - config.generic_uni_ops.insert(ID($neg)); + config.generic_uni_ops.set_id(ID($not)); + // config.generic_uni_ops.set_id(ID($pos)); + config.generic_uni_ops.set_id(ID($neg)); - config.generic_cbin_ops.insert(ID($and)); - config.generic_cbin_ops.insert(ID($or)); - config.generic_cbin_ops.insert(ID($xor)); - config.generic_cbin_ops.insert(ID($xnor)); + config.generic_cbin_ops.set_id(ID($and)); + config.generic_cbin_ops.set_id(ID($or)); + config.generic_cbin_ops.set_id(ID($xor)); + config.generic_cbin_ops.set_id(ID($xnor)); - config.generic_bin_ops.insert(ID($shl)); - config.generic_bin_ops.insert(ID($shr)); - config.generic_bin_ops.insert(ID($sshl)); - config.generic_bin_ops.insert(ID($sshr)); + config.generic_bin_ops.set_id(ID($shl)); + config.generic_bin_ops.set_id(ID($shr)); + config.generic_bin_ops.set_id(ID($sshl)); + config.generic_bin_ops.set_id(ID($sshr)); - config.generic_bin_ops.insert(ID($lt)); - config.generic_bin_ops.insert(ID($le)); - config.generic_bin_ops.insert(ID($eq)); - config.generic_bin_ops.insert(ID($ne)); - config.generic_bin_ops.insert(ID($eqx)); - config.generic_bin_ops.insert(ID($nex)); - config.generic_bin_ops.insert(ID($ge)); - config.generic_bin_ops.insert(ID($gt)); + config.generic_bin_ops.set_id(ID($lt)); + config.generic_bin_ops.set_id(ID($le)); + config.generic_bin_ops.set_id(ID($eq)); + config.generic_bin_ops.set_id(ID($ne)); + config.generic_bin_ops.set_id(ID($eqx)); + config.generic_bin_ops.set_id(ID($nex)); + config.generic_bin_ops.set_id(ID($ge)); + config.generic_bin_ops.set_id(ID($gt)); - config.generic_cbin_ops.insert(ID($add)); - config.generic_cbin_ops.insert(ID($mul)); + config.generic_cbin_ops.set_id(ID($add)); + config.generic_cbin_ops.set_id(ID($mul)); - config.generic_bin_ops.insert(ID($sub)); - config.generic_bin_ops.insert(ID($div)); - config.generic_bin_ops.insert(ID($mod)); - config.generic_bin_ops.insert(ID($divfloor)); - config.generic_bin_ops.insert(ID($modfloor)); - // config.generic_bin_ops.insert(ID($pow)); + config.generic_bin_ops.set_id(ID($sub)); + config.generic_bin_ops.set_id(ID($div)); + config.generic_bin_ops.set_id(ID($mod)); + config.generic_bin_ops.set_id(ID($divfloor)); + config.generic_bin_ops.set_id(ID($modfloor)); + // config.generic_bin_ops.set_id(ID($pow)); - config.generic_uni_ops.insert(ID($logic_not)); - config.generic_cbin_ops.insert(ID($logic_and)); - config.generic_cbin_ops.insert(ID($logic_or)); + config.generic_uni_ops.set_id(ID($logic_not)); + config.generic_cbin_ops.set_id(ID($logic_and)); + config.generic_cbin_ops.set_id(ID($logic_or)); - config.generic_other_ops.insert(ID($alu)); - config.generic_other_ops.insert(ID($macc)); + config.generic_other_ops.set_id(ID($alu)); + config.generic_other_ops.set_id(ID($macc)); log_header(design, "Executing SHARE pass (SAT-based resource sharing).\n"); From e3f9911e33766b261d1be523986350e67bcf519e Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 25 Nov 2025 20:21:33 +0100 Subject: [PATCH 224/291] newcelltypes: refactor --- kernel/newcelltypes.h | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/kernel/newcelltypes.h b/kernel/newcelltypes.h index 6f520d891..e5c1bc76a 100644 --- a/kernel/newcelltypes.h +++ b/kernel/newcelltypes.h @@ -478,7 +478,7 @@ struct Categories { return false; return data[idx]; } - constexpr bool& operator[](size_t idx) { + constexpr bool operator[](size_t idx) { return data[idx]; } constexpr void set_id(IdString type, bool val = true) { @@ -506,35 +506,35 @@ struct Categories { for (size_t i = 0; i < turbo_builder.count; ++i) { auto& cell = turbo_builder.cells[i]; size_t idx = cell.type.index_; - is_known[idx] = true; - is_evaluable[idx] = cell.features.is_evaluable; - is_combinatorial[idx] = cell.features.is_combinatorial; - is_synthesizable[idx] = cell.features.is_synthesizable; - is_stdcell[idx] = cell.features.is_stdcell; - is_ff[idx] = cell.features.is_ff; - is_mem_noff[idx] = cell.features.is_mem_noff; - is_anyinit[idx] = cell.features.is_anyinit; - is_tristate[idx] = cell.features.is_tristate; + is_known.set(idx); + is_evaluable.set(idx, cell.features.is_evaluable); + is_combinatorial.set(idx, cell.features.is_combinatorial); + is_synthesizable.set(idx, cell.features.is_synthesizable); + is_stdcell.set(idx, cell.features.is_stdcell); + is_ff.set(idx, cell.features.is_ff); + is_mem_noff.set(idx, cell.features.is_mem_noff); + is_anyinit.set(idx, cell.features.is_anyinit); + is_tristate.set(idx, cell.features.is_tristate); } } constexpr static Category join(Category left, Category right) { Category c {}; for (size_t i = 0; i < MAX_CELLS; ++i) { - c[i] = left[i] || right[i]; + c.set(i, left[i] || right[i]); } return c; } constexpr static Category meet(Category left, Category right) { Category c {}; for (size_t i = 0; i < MAX_CELLS; ++i) { - c[i] = left[i] && right[i]; + c.set(i, left[i] && right[i]); } return c; } - constexpr static Category complement(Category old) { + constexpr static Category complement(Category arg) { Category c {}; for (size_t i = 0; i < MAX_CELLS; ++i) { - c[i] = !old[i]; + c.set(i, !arg[i]); } return c; } From a9463d1aee122b2ebd04545a044aec4756a8e636 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 25 Nov 2025 22:41:12 +0100 Subject: [PATCH 225/291] newcelltypes: fix non-cells --- kernel/newcelltypes.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/kernel/newcelltypes.h b/kernel/newcelltypes.h index e5c1bc76a..005b4c117 100644 --- a/kernel/newcelltypes.h +++ b/kernel/newcelltypes.h @@ -531,6 +531,8 @@ struct Categories { } return c; } + // Sketchy! Make sure to always meet with only the known universe. + // In other words, no modus tollens allowed constexpr static Category complement(Category arg) { Category c {}; for (size_t i = 0; i < MAX_CELLS; ++i) { @@ -546,8 +548,12 @@ static constexpr Categories categories; // Legacy namespace Compat { - static constexpr auto internals_all = Categories::complement(categories.is_stdcell); - static constexpr auto internals_mem_ff = Categories::join(categories.is_ff, categories.is_mem_noff); + static constexpr auto internals_all = Categories::meet(categories.is_known, Categories::complement(categories.is_stdcell)); + static constexpr auto mem_ff = Categories::join(categories.is_ff, categories.is_mem_noff); + static constexpr auto nomem_noff = Categories::meet(categories.is_known, Categories::complement(mem_ff)); + static constexpr auto internals_mem_ff = Categories::meet(internals_all, mem_ff); + // old setup_internals + static constexpr auto internals_nomem_noff = Categories::meet(internals_all, nomem_noff); static constexpr auto stdcells_mem = Categories::meet(categories.is_stdcell, categories.is_mem_noff); }; From a0f87dc2d1d18e751aa83566211c130713e1365c Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 25 Nov 2025 23:36:40 +0100 Subject: [PATCH 226/291] modtools: use newcelltypes --- kernel/modtools.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/kernel/modtools.h b/kernel/modtools.h index 5cd8e3cb2..193269687 100644 --- a/kernel/modtools.h +++ b/kernel/modtools.h @@ -23,6 +23,7 @@ #include "kernel/yosys.h" #include "kernel/sigtools.h" #include "kernel/celltypes.h" +#include "kernel/newcelltypes.h" YOSYS_NAMESPACE_BEGIN @@ -357,7 +358,7 @@ struct ModWalker RTLIL::Design *design; RTLIL::Module *module; - CellTypes ct; + NewCellTypes ct; SigMap sigmap; dict> signal_drivers; From 8e17fb02661a7ae91c9a6b4d171973aa9c3b88fa Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 25 Nov 2025 23:47:56 +0100 Subject: [PATCH 227/291] consteval: use newcelltypes --- kernel/consteval.h | 6 +++--- kernel/newcelltypes.h | 2 ++ 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/kernel/consteval.h b/kernel/consteval.h index ca04d722f..d00ae8f33 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -24,6 +24,7 @@ #include "kernel/sigtools.h" #include "kernel/celltypes.h" #include "kernel/macc.h" +#include "kernel/newcelltypes.h" YOSYS_NAMESPACE_BEGIN @@ -44,9 +45,8 @@ struct ConstEval ConstEval(RTLIL::Module *module, RTLIL::State defaultval = RTLIL::State::Sm) : module(module), assign_map(module), defaultval(defaultval) { - CellTypes ct; - ct.setup_internals(); - ct.setup_stdcells(); + auto ct = NewCellTypes(); + ct.static_cell_types = StaticCellTypes::Compat::nomem_noff; for (auto &it : module->cells_) { if (!ct.cell_known(it.second->type)) diff --git a/kernel/newcelltypes.h b/kernel/newcelltypes.h index 005b4c117..28584b1f1 100644 --- a/kernel/newcelltypes.h +++ b/kernel/newcelltypes.h @@ -554,6 +554,8 @@ namespace Compat { static constexpr auto internals_mem_ff = Categories::meet(internals_all, mem_ff); // old setup_internals static constexpr auto internals_nomem_noff = Categories::meet(internals_all, nomem_noff); + // old setup_stdcells + static constexpr auto stdcells_nomem_noff = Categories::meet(categories.is_stdcell, nomem_noff); static constexpr auto stdcells_mem = Categories::meet(categories.is_stdcell, categories.is_mem_noff); }; From 31b86ebc2ea3b177b3aefdb256f5b308ea096de6 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 25 Nov 2025 23:52:30 +0100 Subject: [PATCH 228/291] newcelltypes: comment --- kernel/newcelltypes.h | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/newcelltypes.h b/kernel/newcelltypes.h index 28584b1f1..be661fc4f 100644 --- a/kernel/newcelltypes.h +++ b/kernel/newcelltypes.h @@ -550,6 +550,7 @@ static constexpr Categories categories; namespace Compat { static constexpr auto internals_all = Categories::meet(categories.is_known, Categories::complement(categories.is_stdcell)); static constexpr auto mem_ff = Categories::join(categories.is_ff, categories.is_mem_noff); + // old setup_internals + setup_stdcells static constexpr auto nomem_noff = Categories::meet(categories.is_known, Categories::complement(mem_ff)); static constexpr auto internals_mem_ff = Categories::meet(internals_all, mem_ff); // old setup_internals From d91e1c8607038132df0767e1107084653fe239a1 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 26 Nov 2025 00:03:43 +0100 Subject: [PATCH 229/291] newcelltypes: test against builtin_ff_cell_types --- tests/unit/kernel/cellTypesTest.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/unit/kernel/cellTypesTest.cc b/tests/unit/kernel/cellTypesTest.cc index 1743ef7a0..0383d831d 100644 --- a/tests/unit/kernel/cellTypesTest.cc +++ b/tests/unit/kernel/cellTypesTest.cc @@ -30,6 +30,9 @@ TEST(CellTypesTest, basic) std::cout << i << " " << type.str() << "\n"; EXPECT_EQ(older.cell_known(type), newer.cell_known(type)); + if (RTLIL::builtin_ff_cell_types().count(type) != StaticCellTypes::categories.is_ff(type)) + std::cout << i << " " << type.str() << "\n"; + EXPECT_EQ(RTLIL::builtin_ff_cell_types().count(type), StaticCellTypes::categories.is_ff(type)); } yosys_shutdown(); } From 4ab22cbb9724cbb3f213329ed1ba53eb4fb9eb2f Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 26 Nov 2025 00:03:53 +0100 Subject: [PATCH 230/291] abc: use newcelltypes --- passes/techmap/abc.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 6e5b1fba8..a072bf022 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -43,7 +43,7 @@ #include "kernel/register.h" #include "kernel/sigtools.h" -#include "kernel/celltypes.h" +#include "kernel/newcelltypes.h" #include "kernel/ffinit.h" #include "kernel/ff.h" #include "kernel/cost.h" @@ -2455,7 +2455,7 @@ struct AbcPass : public Pass { continue; } - CellTypes ct(design); + NewCellTypes ct(design); std::vector all_cells = mod->selected_cells(); pool unassigned_cells(all_cells.begin(), all_cells.end()); From 665b6eeb4a1325f242882d173a3b31a12dc62c51 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 26 Nov 2025 00:14:12 +0100 Subject: [PATCH 231/291] aiger2: add TODO --- backends/aiger2/aiger.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index babc29826..5f7e71a3a 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -45,6 +45,8 @@ PRIVATE_NAMESPACE_BEGIN // TODO //#define ARITH_OPS ID($add), ID($sub), ID($neg) +// TODO convert to newcelltypes + #define KNOWN_OPS BITWISE_OPS, REDUCE_OPS, LOGIC_OPS, GATE_OPS, ID($pos), CMP_OPS, \ ID($pmux), ID($bmux) /*, ARITH_OPS*/ From c3ed884bc4ce5d8b9a135a1d14a58de057fb7466 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 26 Nov 2025 00:16:07 +0100 Subject: [PATCH 232/291] drivertools: use newcelltypes --- kernel/drivertools.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/kernel/drivertools.h b/kernel/drivertools.h index ba7b2aa84..28d3be91e 100644 --- a/kernel/drivertools.h +++ b/kernel/drivertools.h @@ -25,7 +25,7 @@ #include "kernel/rtlil.h" #include "kernel/sigtools.h" -#include "kernel/celltypes.h" +#include "kernel/newcelltypes.h" YOSYS_NAMESPACE_BEGIN @@ -1093,10 +1093,10 @@ private: struct DriverMap { - CellTypes celltypes; + NewCellTypes celltypes; DriverMap() { celltypes.setup(); } - DriverMap(Design *design) { celltypes.setup(); celltypes.setup_design(design); } + DriverMap(Design *design) { celltypes.setup(design); } private: From 7a5c303ccd0dde31fe121b130e295a97aeb12eea Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 26 Nov 2025 00:32:11 +0100 Subject: [PATCH 233/291] backends: use newcelltypes --- backends/blif/blif.cc | 4 ++-- backends/edif/edif.cc | 4 ++-- backends/intersynth/intersynth.cc | 4 ++-- backends/smt2/smt2.cc | 4 ++-- backends/smv/smv.cc | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index 85db8679e..cc339bcbc 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -24,7 +24,7 @@ #include "kernel/rtlil.h" #include "kernel/register.h" #include "kernel/sigtools.h" -#include "kernel/celltypes.h" +#include "kernel/newcelltypes.h" #include "kernel/log.h" #include @@ -61,7 +61,7 @@ struct BlifDumper RTLIL::Module *module; RTLIL::Design *design; BlifDumperConfig *config; - CellTypes ct; + NewCellTypes ct; SigMap sigmap; dict init_bits; diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 61d6ee254..145477b6b 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -23,7 +23,7 @@ #include "kernel/rtlil.h" #include "kernel/register.h" #include "kernel/sigtools.h" -#include "kernel/celltypes.h" +#include "kernel/newcelltypes.h" #include "kernel/log.h" #include @@ -138,7 +138,7 @@ struct EdifBackend : public Backend { bool lsbidx = false; std::map> lib_cell_ports; bool nogndvcc = false, gndvccy = false, keepmode = false; - CellTypes ct(design); + NewCellTypes ct(design); EdifNames edif_names; size_t argidx; diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 78eab17da..ad16d50ab 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -20,7 +20,7 @@ #include "kernel/rtlil.h" #include "kernel/register.h" #include "kernel/sigtools.h" -#include "kernel/celltypes.h" +#include "kernel/newcelltypes.h" #include "kernel/log.h" #include @@ -117,7 +117,7 @@ struct IntersynthBackend : public Backend { std::set conntypes_code, celltypes_code; std::string netlists_code; - CellTypes ct(design); + NewCellTypes ct(design); for (auto lib : libs) ct.setup_design(lib); diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index d80622029..9d0ebc2aa 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -20,7 +20,7 @@ #include "kernel/rtlil.h" #include "kernel/register.h" #include "kernel/sigtools.h" -#include "kernel/celltypes.h" +#include "kernel/newcelltypes.h" #include "kernel/log.h" #include "kernel/mem.h" #include "libs/json11/json11.hpp" @@ -32,7 +32,7 @@ PRIVATE_NAMESPACE_BEGIN struct Smt2Worker { - CellTypes ct; + NewCellTypes ct; SigMap sigmap; RTLIL::Module *module; bool bvmode, memmode, wiresmode, verbose, statebv, statedt, forallmode; diff --git a/backends/smv/smv.cc b/backends/smv/smv.cc index a6ccbf27f..acefad060 100644 --- a/backends/smv/smv.cc +++ b/backends/smv/smv.cc @@ -20,7 +20,7 @@ #include "kernel/rtlil.h" #include "kernel/register.h" #include "kernel/sigtools.h" -#include "kernel/celltypes.h" +#include "kernel/newcelltypes.h" #include "kernel/log.h" #include @@ -29,7 +29,7 @@ PRIVATE_NAMESPACE_BEGIN struct SmvWorker { - CellTypes ct; + NewCellTypes ct; SigMap sigmap; RTLIL::Module *module; std::ostream &f; From 5216d32d1b70d095a776c3bd2cb2ac187e4b4bba Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 26 Nov 2025 00:47:30 +0100 Subject: [PATCH 234/291] yosys: use newcelltypes for yosys_celltypes --- kernel/celltypes.h | 3 --- kernel/newcelltypes.h | 39 +++++++++------------------------------ kernel/yosys.cc | 8 +++----- 3 files changed, 12 insertions(+), 38 deletions(-) diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 34b013dd9..91e0e7070 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -548,9 +548,6 @@ struct CellTypes } }; -// initialized by yosys_setup() -extern CellTypes yosys_celltypes; - YOSYS_NAMESPACE_END #endif diff --git a/kernel/newcelltypes.h b/kernel/newcelltypes.h index be661fc4f..868b54c8f 100644 --- a/kernel/newcelltypes.h +++ b/kernel/newcelltypes.h @@ -419,32 +419,7 @@ struct CellTableBuilder { }; - -constexpr CellTableBuilder turbo_builder{}; - -// template -// struct Worlds { -// struct World { -// std::array data{}; -// constexpr T operator()(IdString type) const { -// return data[type.index_]; -// } -// constexpr T& operator[](size_t idx) { -// return data[idx]; -// } -// constexpr size_t size() const { return data.size(); } -// }; -// World is_known {}; -// World is_evaluable {}; -// World is_combinatorial {}; -// World is_synthesizable {}; -// World is_stdcell {}; -// World is_ff {}; -// World is_mem_noff {}; -// World is_anyinit {}; -// World is_tristate {}; -// virtual constexpr Categories(); -// }; +constexpr CellTableBuilder builder{}; struct PortInfo { struct PortLists { @@ -460,8 +435,8 @@ struct PortInfo { PortLists inputs {}; PortLists outputs {}; constexpr PortInfo() { - for (size_t i = 0; i < turbo_builder.count; ++i) { - auto& cell = turbo_builder.cells[i]; + for (size_t i = 0; i < builder.count; ++i) { + auto& cell = builder.cells[i]; size_t idx = cell.type.index_; inputs[idx] = cell.inputs; outputs[idx] = cell.outputs; @@ -503,8 +478,8 @@ struct Categories { Category is_anyinit {}; Category is_tristate {}; constexpr Categories() { - for (size_t i = 0; i < turbo_builder.count; ++i) { - auto& cell = turbo_builder.cells[i]; + for (size_t i = 0; i < builder.count; ++i) { + auto& cell = builder.cells[i]; size_t idx = cell.type.index_; is_known.set(idx); is_evaluable.set(idx, cell.features.is_evaluable); @@ -558,6 +533,8 @@ namespace Compat { // old setup_stdcells static constexpr auto stdcells_nomem_noff = Categories::meet(categories.is_stdcell, nomem_noff); static constexpr auto stdcells_mem = Categories::meet(categories.is_stdcell, categories.is_mem_noff); + // old setup_internals_eval + // static constexpr auto internals_eval = Categories::meet(internals_all, categories.is_evaluable); }; namespace { @@ -665,6 +642,8 @@ struct NewCellTypes { } }; +extern NewCellTypes yosys_celltypes; + YOSYS_NAMESPACE_END #endif diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 4264cb772..29fcd48d8 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -18,8 +18,8 @@ */ #include "kernel/yosys.h" -#include "kernel/celltypes.h" #include "kernel/log.h" +#include "kernel/newcelltypes.h" #ifdef YOSYS_ENABLE_READLINE # include @@ -92,7 +92,7 @@ const char* yosys_maybe_version() { } RTLIL::Design *yosys_design = NULL; -CellTypes yosys_celltypes; +NewCellTypes yosys_celltypes; #ifdef YOSYS_ENABLE_TCL Tcl_Interp *yosys_tcl_interp = NULL; @@ -262,7 +262,7 @@ void yosys_setup() Pass::init_register(); yosys_design = new RTLIL::Design; - yosys_celltypes.setup(); + yosys_celltypes.static_cell_types = StaticCellTypes::categories.is_known; log_push(); } @@ -291,8 +291,6 @@ void yosys_shutdown() log_errfile = NULL; log_files.clear(); - yosys_celltypes.clear(); - #ifdef YOSYS_ENABLE_TCL if (yosys_tcl_interp != NULL) { if (!Tcl_InterpDeleted(yosys_tcl_interp)) { From ecb8b20f6231bf27b7500728a07b710ae812d48a Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 26 Nov 2025 00:50:41 +0100 Subject: [PATCH 235/291] yosys: use newcelltypes for yosys_celltypes users --- frontends/aiger/aigerparse.cc | 2 +- kernel/rtlil.cc | 2 +- passes/cmds/check.cc | 2 +- passes/cmds/select.cc | 6 +++--- passes/cmds/torder.cc | 2 +- passes/equiv/equiv.h | 1 + passes/sat/sim.cc | 1 + passes/techmap/abc9_ops.cc | 2 +- 8 files changed, 10 insertions(+), 8 deletions(-) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index e55349aa7..9931ef78f 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -37,7 +37,7 @@ #include "kernel/yosys.h" #include "kernel/sigtools.h" -#include "kernel/celltypes.h" +#include "kernel/newcelltypes.h" #include "aigerparse.h" YOSYS_NAMESPACE_BEGIN diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index c59c0b1f7..61dac3313 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -19,7 +19,7 @@ #include "kernel/yosys.h" #include "kernel/macc.h" -#include "kernel/celltypes.h" +#include "kernel/newcelltypes.h" #include "kernel/binding.h" #include "kernel/sigtools.h" #include "frontends/verilog/verilog_frontend.h" diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index b7a5feb57..1019c2955 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -20,7 +20,7 @@ #include "kernel/yosys.h" #include "kernel/sigtools.h" #include "kernel/celledges.h" -#include "kernel/celltypes.h" +#include "kernel/newcelltypes.h" #include "kernel/utils.h" #include "kernel/log_help.h" diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 0df47664f..2359efe03 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -18,7 +18,7 @@ */ #include "kernel/yosys.h" -#include "kernel/celltypes.h" +#include "kernel/newcelltypes.h" #include "kernel/sigtools.h" #include "kernel/log_help.h" @@ -488,7 +488,7 @@ static int parse_comma_list(std::set &tokens, const std::string } } -static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::vector &rules, std::set &limits, int max_objects, char mode, CellTypes &ct, bool eval_only) +static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::vector &rules, std::set &limits, int max_objects, char mode, NewCellTypes &ct, bool eval_only) { int sel_objects = 0; bool is_input, is_output; @@ -564,7 +564,7 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char std::vector rules; std::set limits; - CellTypes ct; + NewCellTypes ct; if (mode != 'x') ct.setup(design); diff --git a/passes/cmds/torder.cc b/passes/cmds/torder.cc index 537b6793d..52c00072f 100644 --- a/passes/cmds/torder.cc +++ b/passes/cmds/torder.cc @@ -18,7 +18,7 @@ */ #include "kernel/yosys.h" -#include "kernel/celltypes.h" +#include "kernel/newcelltypes.h" #include "kernel/sigtools.h" #include "kernel/utils.h" #include "kernel/log_help.h" diff --git a/passes/equiv/equiv.h b/passes/equiv/equiv.h index 95d4b25e9..055dc440b 100644 --- a/passes/equiv/equiv.h +++ b/passes/equiv/equiv.h @@ -5,6 +5,7 @@ #include "kernel/yosys_common.h" #include "kernel/sigtools.h" #include "kernel/satgen.h" +#include "kernel/newcelltypes.h" YOSYS_NAMESPACE_BEGIN diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 27d6d12c1..d78da892f 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -20,6 +20,7 @@ #include "kernel/yosys.h" #include "kernel/sigtools.h" #include "kernel/celltypes.h" +#include "kernel/newcelltypes.h" #include "kernel/mem.h" #include "kernel/fstdata.h" #include "kernel/ff.h" diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 8d3869ece..75efd230a 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -21,7 +21,7 @@ #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/utils.h" -#include "kernel/celltypes.h" +#include "kernel/newcelltypes.h" #include "kernel/timinginfo.h" USING_YOSYS_NAMESPACE From 12412d1fa59d9bcd3f7d62131968b4200b1c9a36 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 26 Nov 2025 00:53:01 +0100 Subject: [PATCH 236/291] register: use newcelltypes --- kernel/register.cc | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/kernel/register.cc b/kernel/register.cc index abde8f47e..cba6d5f99 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -22,6 +22,7 @@ #include "kernel/json.h" #include "kernel/gzip.h" #include "kernel/log_help.h" +#include "kernel/newcelltypes.h" #include #include @@ -975,16 +976,18 @@ struct HelpPass : public Pass { json.entry("generator", yosys_maybe_version()); dict> groups; - dict> cells; + dict> cells; // iterate over cells bool raise_error = false; - for (auto &it : yosys_celltypes.cell_types) { - auto name = it.first.str(); + for (auto it : StaticCellTypes::builder.cells) { + if (!StaticCellTypes::categories.is_known(it.type)) + continue; + auto name = it.type.str(); if (cell_help_messages.contains(name)) { auto cell_help = cell_help_messages.get(name); groups[cell_help.group].emplace_back(name); - auto cell_pair = pair(cell_help, it.second); + auto cell_pair = pair(cell_help, it); cells.emplace(name, cell_pair); } else { log("ERROR: Missing cell help for cell '%s'.\n", name); @@ -1025,9 +1028,9 @@ struct HelpPass : public Pass { json.name("outputs"); json.value(outputs); vector properties; // CellType properties - if (ct.is_evaluable) properties.push_back("is_evaluable"); - if (ct.is_combinatorial) properties.push_back("is_combinatorial"); - if (ct.is_synthesizable) properties.push_back("is_synthesizable"); + if (ct.features.is_evaluable) properties.push_back("is_evaluable"); + if (ct.features.is_combinatorial) properties.push_back("is_combinatorial"); + if (ct.features.is_synthesizable) properties.push_back("is_synthesizable"); // SimHelper properties size_t last = 0; size_t next = 0; while ((next = ch.tags.find(", ", last)) != string::npos) { From f594014befd4aa0611603b7613e13f3c18e3a1db Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 26 Nov 2025 13:15:02 +0100 Subject: [PATCH 237/291] newcelltypes: proper bounds for unit test --- tests/unit/kernel/cellTypesTest.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/unit/kernel/cellTypesTest.cc b/tests/unit/kernel/cellTypesTest.cc index 0383d831d..1df8ba3ad 100644 --- a/tests/unit/kernel/cellTypesTest.cc +++ b/tests/unit/kernel/cellTypesTest.cc @@ -23,7 +23,7 @@ TEST(CellTypesTest, basic) EXPECT_EQ(older.cell_known(ID(aaaaa)), newer.cell_known(ID(aaaaa))); EXPECT_EQ(older.cell_known(ID($and)), newer.cell_known(ID($and))); - for (size_t i = 0; i < 1000; i++) { + for (size_t i = 0; i < static_cast(RTLIL::StaticId::STATIC_ID_END); i++) { IdString type; type.index_ = i; if (older.cell_known(type) != newer.cell_known(type)) From 661fcb24cb62b0eb4146268f679ce117b87a2f2a Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 26 Nov 2025 13:17:24 +0100 Subject: [PATCH 238/291] newcelltypes: fix MSVC build --- kernel/newcelltypes.h | 46 ++++++++++++++++++------------------------- 1 file changed, 19 insertions(+), 27 deletions(-) diff --git a/kernel/newcelltypes.h b/kernel/newcelltypes.h index 868b54c8f..e26de0569 100644 --- a/kernel/newcelltypes.h +++ b/kernel/newcelltypes.h @@ -57,9 +57,8 @@ struct CellTableBuilder { } constexpr void setup_internals_other() { - Features features { - .is_tristate = true, - }; + Features features {}; + features.is_tristate = true; setup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y}, features); features = {}; @@ -90,9 +89,8 @@ struct CellTableBuilder { } constexpr void setup_internals_eval() { - Features features { - .is_evaluable = true, - }; + Features features {}; + features.is_evaluable = true; std::initializer_list unary_ops = { ID($not), ID($pos), ID($buf), ID($neg), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), @@ -127,9 +125,8 @@ struct CellTableBuilder { } constexpr void setup_internals_ff() { - Features features { - .is_ff = true, - }; + Features features {}; + features.is_ff = true; setup_type(ID($sr), {ID::SET, ID::CLR}, {ID::Q}, features); setup_type(ID($ff), {ID::D}, {ID::Q}, features); setup_type(ID($dff), {ID::CLK, ID::D}, {ID::Q}, features); @@ -149,16 +146,14 @@ struct CellTableBuilder { } constexpr void setup_internals_anyinit() { - Features features { - .is_anyinit = true, - }; + Features features {}; + features.is_anyinit = true; setup_type(ID($anyinit), {ID::D}, {ID::Q}, features); } constexpr void setup_internals_mem_noff() { - Features features { - .is_mem_noff = true, - }; + Features features {}; + features.is_mem_noff = true; // NOT setup_internals_ff() setup_type(ID($memrd), {ID::CLK, ID::EN, ID::ADDR}, {ID::DATA}, features); @@ -175,19 +170,17 @@ struct CellTableBuilder { } constexpr void setup_stdcells_tristate() { - Features features { - .is_stdcell = true, - .is_tristate = true, - }; + Features features {}; + features.is_stdcell = true; + features.is_tristate = true; setup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y}, features); } constexpr void setup_stdcells_eval() { - Features features { - .is_evaluable = true, - .is_stdcell = true, - }; + Features features {}; + features.is_stdcell = true; + features.is_evaluable = true; setup_type(ID($_BUF_), {ID::A}, {ID::Y}, features); setup_type(ID($_NOT_), {ID::A}, {ID::Y}, features); setup_type(ID($_AND_), {ID::A, ID::B}, {ID::Y}, features); @@ -210,10 +203,9 @@ struct CellTableBuilder { } constexpr void setup_stdcells_ff() { - Features features { - .is_stdcell = true, - .is_ff = true, - }; + Features features {}; + features.is_stdcell = true; + features.is_ff = true; // for (auto c1 : list_np) // for (auto c2 : list_np) From ae10e9e9551689e4a76215118eacecca1579e8fe Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 27 Nov 2025 01:58:06 +0100 Subject: [PATCH 239/291] pyosys: disable test --- tests/pyosys/test_dict.py | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/tests/pyosys/test_dict.py b/tests/pyosys/test_dict.py index 717fed8ea..57d4dc82f 100644 --- a/tests/pyosys/test_dict.py +++ b/tests/pyosys/test_dict.py @@ -35,10 +35,4 @@ print(repr_test.popitem()) assert before - 1 == len(repr_test) # test noncomparable -## if ys.CellType ever gets an == operator just disable this section -uncomparable_value = ys.Globals.yosys_celltypes.cell_types[ys.IdString("$not")] - -x = ys.IdstringToCelltypeDict({ ys.IdString("\\a"): uncomparable_value}) -y = ys.IdstringToCelltypeDict({ ys.IdString("\\a"): uncomparable_value}) - -assert x != y # not comparable +# TODO newcelltypes? From 793a3513c60dea5c7c323d353701a8da36b96479 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 27 Nov 2025 02:53:29 +0100 Subject: [PATCH 240/291] newcelltypes: use unordered_map --- kernel/newcelltypes.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/kernel/newcelltypes.h b/kernel/newcelltypes.h index e26de0569..c4a4ea329 100644 --- a/kernel/newcelltypes.h +++ b/kernel/newcelltypes.h @@ -548,8 +548,13 @@ struct NewCellType { }; struct NewCellTypes { + struct IdStringHash { + std::size_t operator()(const IdString id) const { + return static_cast(id.hash_top().yield()); + } + }; StaticCellTypes::Categories::Category static_cell_types = StaticCellTypes::categories.empty; - dict custom_cell_types = {}; + std::unordered_map custom_cell_types {}; NewCellTypes() { static_cell_types = StaticCellTypes::categories.empty; From 0284595e9ca79392fa406671acb0823a253a1aae Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 27 Nov 2025 03:32:31 +0100 Subject: [PATCH 241/291] celltypes: fix absurd eval declarations --- kernel/celltypes.h | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 91e0e7070..c03cbdcc3 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -87,22 +87,22 @@ struct CellTypes { setup_internals_eval(); - setup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y}, true); + setup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y}); - setup_type(ID($assert), {ID::A, ID::EN}, pool(), true); - setup_type(ID($assume), {ID::A, ID::EN}, pool(), true); - setup_type(ID($live), {ID::A, ID::EN}, pool(), true); - setup_type(ID($fair), {ID::A, ID::EN}, pool(), true); - setup_type(ID($cover), {ID::A, ID::EN}, pool(), true); - setup_type(ID($initstate), pool(), {ID::Y}, true); - setup_type(ID($anyconst), pool(), {ID::Y}, true); - setup_type(ID($anyseq), pool(), {ID::Y}, true); - setup_type(ID($allconst), pool(), {ID::Y}, true); - setup_type(ID($allseq), pool(), {ID::Y}, true); - setup_type(ID($equiv), {ID::A, ID::B}, {ID::Y}, true); - setup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool(), true); - setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool(), true); - setup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool(), true); + setup_type(ID($assert), {ID::A, ID::EN}, pool()); + setup_type(ID($assume), {ID::A, ID::EN}, pool()); + setup_type(ID($live), {ID::A, ID::EN}, pool()); + setup_type(ID($fair), {ID::A, ID::EN}, pool()); + setup_type(ID($cover), {ID::A, ID::EN}, pool()); + setup_type(ID($initstate), pool(), {ID::Y}); + setup_type(ID($anyconst), pool(), {ID::Y}); + setup_type(ID($anyseq), pool(), {ID::Y}); + setup_type(ID($allconst), pool(), {ID::Y}); + setup_type(ID($allseq), pool(), {ID::Y}); + setup_type(ID($equiv), {ID::A, ID::B}, {ID::Y}); + setup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool()); + setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool()); + setup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool()); setup_type(ID($print), {ID::EN, ID::ARGS, ID::TRG}, pool()); setup_type(ID($check), {ID::A, ID::EN, ID::ARGS, ID::TRG}, pool()); setup_type(ID($set_tag), {ID::A, ID::SET, ID::CLR}, {ID::Y}); @@ -195,7 +195,7 @@ struct CellTypes { setup_stdcells_eval(); - setup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y}, true); + setup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y}); } void setup_stdcells_eval() From 6d4736269b2611a4f4d6fa4c53a5180af58d28ad Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 27 Nov 2025 03:32:41 +0100 Subject: [PATCH 242/291] newcelltypes: extend testing --- tests/unit/kernel/cellTypesTest.cc | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/tests/unit/kernel/cellTypesTest.cc b/tests/unit/kernel/cellTypesTest.cc index 1df8ba3ad..aec8b05fc 100644 --- a/tests/unit/kernel/cellTypesTest.cc +++ b/tests/unit/kernel/cellTypesTest.cc @@ -14,24 +14,30 @@ TEST(CellTypesTest, basic) log_files.push_back(stdout); CellTypes older; NewCellTypes newer; - log("setup nullptr\n"); older.setup(nullptr); newer.setup(nullptr); - log("setup type bleh\n"); older.setup_type(ID(bleh), {ID::G}, {ID::H, ID::I}, false, true); newer.setup_type(ID(bleh), {ID::G}, {ID::H, ID::I}, false, true); EXPECT_EQ(older.cell_known(ID(aaaaa)), newer.cell_known(ID(aaaaa))); EXPECT_EQ(older.cell_known(ID($and)), newer.cell_known(ID($and))); + auto check_port = [&](auto type, auto port) { + EXPECT_EQ(older.cell_port_dir(type, port), newer.cell_port_dir(type, port)); + EXPECT_EQ(older.cell_input(type, port), newer.cell_input(type, port)); + EXPECT_EQ(older.cell_output(type, port), newer.cell_output(type, port)); + }; for (size_t i = 0; i < static_cast(RTLIL::StaticId::STATIC_ID_END); i++) { IdString type; type.index_ = i; - if (older.cell_known(type) != newer.cell_known(type)) - std::cout << i << " " << type.str() << "\n"; EXPECT_EQ(older.cell_known(type), newer.cell_known(type)); + if (older.cell_evaluable(type) != newer.cell_evaluable(type)) + std::cout << type.str() << "\n"; + EXPECT_EQ(older.cell_evaluable(type), newer.cell_evaluable(type)); + for (auto port : StaticCellTypes::builder.cells.data()->inputs.ports) + check_port(type, port); + for (auto port : StaticCellTypes::builder.cells.data()->outputs.ports) + check_port(type, port); - if (RTLIL::builtin_ff_cell_types().count(type) != StaticCellTypes::categories.is_ff(type)) - std::cout << i << " " << type.str() << "\n"; EXPECT_EQ(RTLIL::builtin_ff_cell_types().count(type), StaticCellTypes::categories.is_ff(type)); } yosys_shutdown(); From cae54a4c7bd8fcade1242cb0a7a6384c1de1697d Mon Sep 17 00:00:00 2001 From: nella Date: Sat, 28 Feb 2026 18:09:34 +0100 Subject: [PATCH 243/291] Aiger use newcelltypes. --- backends/aiger2/aiger.cc | 129 ++++++++++++++++++++++++--------------- 1 file changed, 79 insertions(+), 50 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 5f7e71a3a..1831fdb03 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -23,7 +23,7 @@ // - zero-width operands #include "kernel/register.h" -#include "kernel/celltypes.h" +#include "kernel/newcelltypes.h" #include "kernel/rtlil.h" USING_YOSYS_NAMESPACE @@ -45,10 +45,30 @@ PRIVATE_NAMESPACE_BEGIN // TODO //#define ARITH_OPS ID($add), ID($sub), ID($neg) -// TODO convert to newcelltypes - -#define KNOWN_OPS BITWISE_OPS, REDUCE_OPS, LOGIC_OPS, GATE_OPS, ID($pos), CMP_OPS, \ - ID($pmux), ID($bmux) /*, ARITH_OPS*/ +static constexpr auto known_ops = []() constexpr { + StaticCellTypes::Categories::Category c{}; + // bitwise + for (auto id : {ID($buf), ID($not), ID($mux), ID($and), ID($or), ID($xor), ID($xnor), ID($fa), ID($bwmux)}) + c.set_id(id); + // reduce + for (auto id : {ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool)}) + c.set_id(id); + // logic + for (auto id : {ID($logic_and), ID($logic_or), ID($logic_not)}) + c.set_id(id); + // gates + for (auto id : {ID($_BUF_), ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), + ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_), + ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_)}) + c.set_id(id); + // compare + for (auto id : {ID($eq), ID($ne), ID($lt), ID($le), ID($ge), ID($gt)}) + c.set_id(id); + // other + for (auto id : {ID($pos), ID($pmux), ID($bmux)}) + c.set_id(id); + return c; +}(); template struct Index { @@ -94,7 +114,7 @@ struct Index { int pos = index_wires(info, m); for (auto cell : m->cells()) { - if (cell->type.in(KNOWN_OPS) || cell->type.in(ID($scopeinfo), ID($specify2), ID($specify3), ID($input_port))) + if (known_ops(cell->type) || cell->type.in(ID($scopeinfo), ID($specify2), ID($specify3), ID($input_port))) continue; Module *submodule = m->design->module(cell->type); @@ -106,7 +126,7 @@ struct Index { pos += index_module(submodule); } else { if (allow_blackboxes) { - info.found_blackboxes.insert(cell); + info.found_blackboxes.insert(cell); } else { // Even if we don't allow blackboxes these might still be // present outside of any traversed input cones, so we @@ -271,7 +291,7 @@ struct Index { } else if (cell->type.in(ID($lt), ID($le), ID($gt), ID($ge))) { if (cell->type.in(ID($gt), ID($ge))) std::swap(aport, bport); - int carry = cell->type.in(ID($le), ID($ge)) ? CFALSE : CTRUE; + int carry = cell->type.in(ID($le), ID($ge)) ? CFALSE : CTRUE; Lit a = Writer::EMPTY_LIT; Lit b = Writer::EMPTY_LIT; // TODO: this might not be the most economic structure; revisit at a later date @@ -581,7 +601,7 @@ struct Index { // an output of a cell Cell *driver = bit.wire->driverCell(); - if (driver->type.in(KNOWN_OPS)) { + if (known_ops(driver->type)) { ret = impl_op(cursor, driver, bit.wire->driverPort(), bit.offset); } else { Module *def = cursor.enter(*this, driver); @@ -918,15 +938,15 @@ struct XAigerWriter : AigerWriter { std::vector pos; std::vector pis; - // * The aiger output port sequence is COs (inputs to modeled boxes), - // inputs to opaque boxes, then module outputs. COs going first is - // required by abc. - // * proper_pos_counter counts ports which follow after COs - // * The mapping file `pseudopo` and `po` statements use indexing relative - // to the first port following COs. - // * If a module output is directly driven by an opaque box, the emission - // of the po statement in the mapping file is skipped. This is done to - // aid re-integration of the mapped result. + // * The aiger output port sequence is COs (inputs to modeled boxes), + // inputs to opaque boxes, then module outputs. COs going first is + // required by abc. + // * proper_pos_counter counts ports which follow after COs + // * The mapping file `pseudopo` and `po` statements use indexing relative + // to the first port following COs. + // * If a module output is directly driven by an opaque box, the emission + // of the po statement in the mapping file is skipped. This is done to + // aid re-integration of the mapped result. int proper_pos_counter = 0; pool driven_by_opaque_box; @@ -1333,41 +1353,50 @@ struct Aiger2Backend : Backend { log(" perform structural hashing while writing\n"); log("\n"); log(" -flatten\n"); - log(" allow descending into submodules and write a flattened view of the design\n"); - log(" hierarchy starting at the selected top\n"); - log("\n"); + log(" allow descending into submodules and write a flattened view of the design\n"); + log(" hierarchy starting at the selected top\n"); + log("\n"); log("This command is able to ingest all combinational cells except for:\n"); log("\n"); - pool supported = {KNOWN_OPS}; - CellTypes ct; - ct.setup_internals_eval(); log(" "); int col = 0; - for (auto pair : ct.cell_types) - if (!supported.count(pair.first)) { - if (col + pair.first.size() + 2 > 72) { + for (size_t i = 0; i < StaticCellTypes::builder.count; i++) { + auto &cell = StaticCellTypes::builder.cells[i]; + if (!cell.features.is_evaluable) + continue; + if (cell.features.is_stdcell) + continue; + if (known_ops(cell.type)) + continue; + std::string name = log_id(cell.type); + if (col + name.size() + 2 > 72) { log("\n "); col = 0; } - col += pair.first.size() + 2; - log("%s, ", log_id(pair.first)); + col += name.size() + 2; + log("%s, ", name.c_str()); } log("\n"); log("\n"); log("And all combinational gates except for:\n"); log("\n"); - CellTypes ct2; - ct2.setup_stdcells(); log(" "); col = 0; - for (auto pair : ct2.cell_types) - if (!supported.count(pair.first)) { - if (col + pair.first.size() + 2 > 72) { + for (size_t i = 0; i < StaticCellTypes::builder.count; i++) { + auto &cell = StaticCellTypes::builder.cells[i]; + if (!cell.features.is_evaluable) + continue; + if (!cell.features.is_stdcell) + continue; + if (known_ops(cell.type)) + continue; + std::string name = log_id(cell.type); + if (col + name.size() + 2 > 72) { log("\n "); col = 0; } - col += pair.first.size() + 2; - log("%s, ", log_id(pair.first)); + col += name.size() + 2; + log("%s, ", name.c_str()); } log("\n"); } @@ -1425,20 +1454,20 @@ struct XAiger2Backend : Backend { log(" perform structural hashing while writing\n"); log("\n"); log(" -flatten\n"); - log(" allow descending into submodules and write a flattened view of the design\n"); - log(" hierarchy starting at the selected top\n"); - log("\n"); - log(" -mapping_prep\n"); - log(" after the file is written, prepare the module for reintegration of\n"); - log(" a mapping in a subsequent command. all cells which are not blackboxed nor\n"); - log(" whiteboxed are removed from the design as well as all wires which only\n"); - log(" connect to removed cells\n"); - log(" (conflicts with -flatten)\n"); - log("\n"); - log(" -map2 \n"); - log(" write a map2 file which 'read_xaiger2 -sc_mapping' can read to\n"); - log(" reintegrate a mapping\n"); - log(" (conflicts with -flatten)\n"); + log(" allow descending into submodules and write a flattened view of the design\n"); + log(" hierarchy starting at the selected top\n"); + log("\n"); + log(" -mapping_prep\n"); + log(" after the file is written, prepare the module for reintegration of\n"); + log(" a mapping in a subsequent command. all cells which are not blackboxed nor\n"); + log(" whiteboxed are removed from the design as well as all wires which only\n"); + log(" connect to removed cells\n"); + log(" (conflicts with -flatten)\n"); + log("\n"); + log(" -map2 \n"); + log(" write a map2 file which 'read_xaiger2 -sc_mapping' can read to\n"); + log(" reintegrate a mapping\n"); + log(" (conflicts with -flatten)\n"); log("\n"); } From 66bd4716cf31423dcd0174229aed2065de44dad7 Mon Sep 17 00:00:00 2001 From: nella Date: Sat, 28 Feb 2026 18:30:37 +0100 Subject: [PATCH 244/291] rtlil use newcelltypes. --- kernel/rtlil.cc | 158 +---------------------------- kernel/rtlil.h | 2 - passes/cmds/icell_liberty.cc | 3 +- tests/unit/kernel/cellTypesTest.cc | 47 ++++++++- 4 files changed, 47 insertions(+), 163 deletions(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 61dac3313..339450c6a 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -288,162 +288,6 @@ void RTLIL::OwningIdString::collect_garbage() dict RTLIL::constpad; -// TODO take a look -static const pool &builtin_ff_cell_types_internal() { - static const pool res = { - ID($sr), - ID($ff), - ID($dff), - ID($dffe), - ID($dffsr), - ID($dffsre), - ID($adff), - ID($adffe), - ID($aldff), - ID($aldffe), - ID($sdff), - ID($sdffe), - ID($sdffce), - ID($dlatch), - ID($adlatch), - ID($dlatchsr), - ID($_DFFE_NN_), - ID($_DFFE_NP_), - ID($_DFFE_PN_), - ID($_DFFE_PP_), - ID($_DFFSR_NNN_), - ID($_DFFSR_NNP_), - ID($_DFFSR_NPN_), - ID($_DFFSR_NPP_), - ID($_DFFSR_PNN_), - ID($_DFFSR_PNP_), - ID($_DFFSR_PPN_), - ID($_DFFSR_PPP_), - ID($_DFFSRE_NNNN_), - ID($_DFFSRE_NNNP_), - ID($_DFFSRE_NNPN_), - ID($_DFFSRE_NNPP_), - ID($_DFFSRE_NPNN_), - ID($_DFFSRE_NPNP_), - ID($_DFFSRE_NPPN_), - ID($_DFFSRE_NPPP_), - ID($_DFFSRE_PNNN_), - ID($_DFFSRE_PNNP_), - ID($_DFFSRE_PNPN_), - ID($_DFFSRE_PNPP_), - ID($_DFFSRE_PPNN_), - ID($_DFFSRE_PPNP_), - ID($_DFFSRE_PPPN_), - ID($_DFFSRE_PPPP_), - ID($_DFF_N_), - ID($_DFF_P_), - ID($_DFF_NN0_), - ID($_DFF_NN1_), - ID($_DFF_NP0_), - ID($_DFF_NP1_), - ID($_DFF_PN0_), - ID($_DFF_PN1_), - ID($_DFF_PP0_), - ID($_DFF_PP1_), - ID($_DFFE_NN0N_), - ID($_DFFE_NN0P_), - ID($_DFFE_NN1N_), - ID($_DFFE_NN1P_), - ID($_DFFE_NP0N_), - ID($_DFFE_NP0P_), - ID($_DFFE_NP1N_), - ID($_DFFE_NP1P_), - ID($_DFFE_PN0N_), - ID($_DFFE_PN0P_), - ID($_DFFE_PN1N_), - ID($_DFFE_PN1P_), - ID($_DFFE_PP0N_), - ID($_DFFE_PP0P_), - ID($_DFFE_PP1N_), - ID($_DFFE_PP1P_), - ID($_ALDFF_NN_), - ID($_ALDFF_NP_), - ID($_ALDFF_PN_), - ID($_ALDFF_PP_), - ID($_ALDFFE_NNN_), - ID($_ALDFFE_NNP_), - ID($_ALDFFE_NPN_), - ID($_ALDFFE_NPP_), - ID($_ALDFFE_PNN_), - ID($_ALDFFE_PNP_), - ID($_ALDFFE_PPN_), - ID($_ALDFFE_PPP_), - ID($_SDFF_NN0_), - ID($_SDFF_NN1_), - ID($_SDFF_NP0_), - ID($_SDFF_NP1_), - ID($_SDFF_PN0_), - ID($_SDFF_PN1_), - ID($_SDFF_PP0_), - ID($_SDFF_PP1_), - ID($_SDFFE_NN0N_), - ID($_SDFFE_NN0P_), - ID($_SDFFE_NN1N_), - ID($_SDFFE_NN1P_), - ID($_SDFFE_NP0N_), - ID($_SDFFE_NP0P_), - ID($_SDFFE_NP1N_), - ID($_SDFFE_NP1P_), - ID($_SDFFE_PN0N_), - ID($_SDFFE_PN0P_), - ID($_SDFFE_PN1N_), - ID($_SDFFE_PN1P_), - ID($_SDFFE_PP0N_), - ID($_SDFFE_PP0P_), - ID($_SDFFE_PP1N_), - ID($_SDFFE_PP1P_), - ID($_SDFFCE_NN0N_), - ID($_SDFFCE_NN0P_), - ID($_SDFFCE_NN1N_), - ID($_SDFFCE_NN1P_), - ID($_SDFFCE_NP0N_), - ID($_SDFFCE_NP0P_), - ID($_SDFFCE_NP1N_), - ID($_SDFFCE_NP1P_), - ID($_SDFFCE_PN0N_), - ID($_SDFFCE_PN0P_), - ID($_SDFFCE_PN1N_), - ID($_SDFFCE_PN1P_), - ID($_SDFFCE_PP0N_), - ID($_SDFFCE_PP0P_), - ID($_SDFFCE_PP1N_), - ID($_SDFFCE_PP1P_), - ID($_SR_NN_), - ID($_SR_NP_), - ID($_SR_PN_), - ID($_SR_PP_), - ID($_DLATCH_N_), - ID($_DLATCH_P_), - ID($_DLATCH_NN0_), - ID($_DLATCH_NN1_), - ID($_DLATCH_NP0_), - ID($_DLATCH_NP1_), - ID($_DLATCH_PN0_), - ID($_DLATCH_PN1_), - ID($_DLATCH_PP0_), - ID($_DLATCH_PP1_), - ID($_DLATCHSR_NNN_), - ID($_DLATCHSR_NNP_), - ID($_DLATCHSR_NPN_), - ID($_DLATCHSR_NPP_), - ID($_DLATCHSR_PNN_), - ID($_DLATCHSR_PNP_), - ID($_DLATCHSR_PPN_), - ID($_DLATCHSR_PPP_), - ID($_FF_), - }; - return res; -} - -const pool &RTLIL::builtin_ff_cell_types() { - return builtin_ff_cell_types_internal(); -} - #define check(condition) log_assert(condition && "malformed Const union") const Const::bitvectype& Const::get_bits() const { @@ -4611,7 +4455,7 @@ bool RTLIL::Cell::is_mem_cell() const } bool RTLIL::Cell::is_builtin_ff() const { - return builtin_ff_cell_types_internal().count(type) > 0; + return StaticCellTypes::categories.is_ff(type); } RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index fea53081e..18bac5e6a 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -737,8 +737,6 @@ template <> struct IDMacroHelper<-1> { namespace RTLIL { extern dict constpad; - const pool &builtin_ff_cell_types(); - static inline std::string escape_id(const std::string &str) { if (str.size() > 0 && str[0] != '\\' && str[0] != '$') return "\\" + str; diff --git a/passes/cmds/icell_liberty.cc b/passes/cmds/icell_liberty.cc index a928e5d58..1d3628f1f 100644 --- a/passes/cmds/icell_liberty.cc +++ b/passes/cmds/icell_liberty.cc @@ -1,5 +1,6 @@ #include "kernel/yosys.h" #include "kernel/celltypes.h" +#include "kernel/newcelltypes.h" #include "kernel/ff.h" USING_YOSYS_NAMESPACE @@ -123,7 +124,7 @@ struct LibertyStubber { return; } - if (RTLIL::builtin_ff_cell_types().count(base_name)) + if (StaticCellTypes::categories.is_ff(base_name)) return liberty_flop(base, derived, f); auto& base_type = ct.cell_types[base_name]; diff --git a/tests/unit/kernel/cellTypesTest.cc b/tests/unit/kernel/cellTypesTest.cc index aec8b05fc..f2c044df4 100644 --- a/tests/unit/kernel/cellTypesTest.cc +++ b/tests/unit/kernel/cellTypesTest.cc @@ -18,7 +18,6 @@ TEST(CellTypesTest, basic) newer.setup(nullptr); older.setup_type(ID(bleh), {ID::G}, {ID::H, ID::I}, false, true); newer.setup_type(ID(bleh), {ID::G}, {ID::H, ID::I}, false, true); - EXPECT_EQ(older.cell_known(ID(aaaaa)), newer.cell_known(ID(aaaaa))); EXPECT_EQ(older.cell_known(ID($and)), newer.cell_known(ID($and))); auto check_port = [&](auto type, auto port) { @@ -26,6 +25,49 @@ TEST(CellTypesTest, basic) EXPECT_EQ(older.cell_input(type, port), newer.cell_input(type, port)); EXPECT_EQ(older.cell_output(type, port), newer.cell_output(type, port)); }; + + // ground truth + const pool expected_ff_types = { + ID($sr), ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre), + ID($adff), ID($adffe), ID($aldff), ID($aldffe), + ID($sdff), ID($sdffe), ID($sdffce), + ID($dlatch), ID($adlatch), ID($dlatchsr), + ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), + ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_), + ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_), + ID($_DFFSRE_NNNN_), ID($_DFFSRE_NNNP_), ID($_DFFSRE_NNPN_), ID($_DFFSRE_NNPP_), + ID($_DFFSRE_NPNN_), ID($_DFFSRE_NPNP_), ID($_DFFSRE_NPPN_), ID($_DFFSRE_NPPP_), + ID($_DFFSRE_PNNN_), ID($_DFFSRE_PNNP_), ID($_DFFSRE_PNPN_), ID($_DFFSRE_PNPP_), + ID($_DFFSRE_PPNN_), ID($_DFFSRE_PPNP_), ID($_DFFSRE_PPPN_), ID($_DFFSRE_PPPP_), + ID($_DFF_N_), ID($_DFF_P_), + ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_), + ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_), + ID($_DFFE_NN0N_), ID($_DFFE_NN0P_), ID($_DFFE_NN1N_), ID($_DFFE_NN1P_), + ID($_DFFE_NP0N_), ID($_DFFE_NP0P_), ID($_DFFE_NP1N_), ID($_DFFE_NP1P_), + ID($_DFFE_PN0N_), ID($_DFFE_PN0P_), ID($_DFFE_PN1N_), ID($_DFFE_PN1P_), + ID($_DFFE_PP0N_), ID($_DFFE_PP0P_), ID($_DFFE_PP1N_), ID($_DFFE_PP1P_), + ID($_ALDFF_NN_), ID($_ALDFF_NP_), ID($_ALDFF_PN_), ID($_ALDFF_PP_), + ID($_ALDFFE_NNN_), ID($_ALDFFE_NNP_), ID($_ALDFFE_NPN_), ID($_ALDFFE_NPP_), + ID($_ALDFFE_PNN_), ID($_ALDFFE_PNP_), ID($_ALDFFE_PPN_), ID($_ALDFFE_PPP_), + ID($_SDFF_NN0_), ID($_SDFF_NN1_), ID($_SDFF_NP0_), ID($_SDFF_NP1_), + ID($_SDFF_PN0_), ID($_SDFF_PN1_), ID($_SDFF_PP0_), ID($_SDFF_PP1_), + ID($_SDFFE_NN0N_), ID($_SDFFE_NN0P_), ID($_SDFFE_NN1N_), ID($_SDFFE_NN1P_), + ID($_SDFFE_NP0N_), ID($_SDFFE_NP0P_), ID($_SDFFE_NP1N_), ID($_SDFFE_NP1P_), + ID($_SDFFE_PN0N_), ID($_SDFFE_PN0P_), ID($_SDFFE_PN1N_), ID($_SDFFE_PN1P_), + ID($_SDFFE_PP0N_), ID($_SDFFE_PP0P_), ID($_SDFFE_PP1N_), ID($_SDFFE_PP1P_), + ID($_SDFFCE_NN0N_), ID($_SDFFCE_NN0P_), ID($_SDFFCE_NN1N_), ID($_SDFFCE_NN1P_), + ID($_SDFFCE_NP0N_), ID($_SDFFCE_NP0P_), ID($_SDFFCE_NP1N_), ID($_SDFFCE_NP1P_), + ID($_SDFFCE_PN0N_), ID($_SDFFCE_PN0P_), ID($_SDFFCE_PN1N_), ID($_SDFFCE_PN1P_), + ID($_SDFFCE_PP0N_), ID($_SDFFCE_PP0P_), ID($_SDFFCE_PP1N_), ID($_SDFFCE_PP1P_), + ID($_SR_NN_), ID($_SR_NP_), ID($_SR_PN_), ID($_SR_PP_), + ID($_DLATCH_N_), ID($_DLATCH_P_), + ID($_DLATCH_NN0_), ID($_DLATCH_NN1_), ID($_DLATCH_NP0_), ID($_DLATCH_NP1_), + ID($_DLATCH_PN0_), ID($_DLATCH_PN1_), ID($_DLATCH_PP0_), ID($_DLATCH_PP1_), + ID($_DLATCHSR_NNN_), ID($_DLATCHSR_NNP_), ID($_DLATCHSR_NPN_), ID($_DLATCHSR_NPP_), + ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_), + ID($_FF_), + }; + for (size_t i = 0; i < static_cast(RTLIL::StaticId::STATIC_ID_END); i++) { IdString type; type.index_ = i; @@ -37,8 +79,7 @@ TEST(CellTypesTest, basic) check_port(type, port); for (auto port : StaticCellTypes::builder.cells.data()->outputs.ports) check_port(type, port); - - EXPECT_EQ(RTLIL::builtin_ff_cell_types().count(type), StaticCellTypes::categories.is_ff(type)); + EXPECT_EQ(expected_ff_types.count(type) > 0, StaticCellTypes::categories.is_ff(type)); } yosys_shutdown(); } From b8ee0803abd9deab49e067f0586fcd97dbef13cb Mon Sep 17 00:00:00 2001 From: nella Date: Sat, 28 Feb 2026 18:39:16 +0100 Subject: [PATCH 245/291] Remove todo. --- tests/pyosys/test_dict.py | 3 --- 1 file changed, 3 deletions(-) diff --git a/tests/pyosys/test_dict.py b/tests/pyosys/test_dict.py index 57d4dc82f..59342391c 100644 --- a/tests/pyosys/test_dict.py +++ b/tests/pyosys/test_dict.py @@ -33,6 +33,3 @@ assert repr_test == {'tomato': 'tomato', 'first': 'second', 'key': 'value', 'im before = len(repr_test) print(repr_test.popitem()) assert before - 1 == len(repr_test) - -# test noncomparable -# TODO newcelltypes? From 04822c66600eef91f5b495233350abd15454348b Mon Sep 17 00:00:00 2001 From: nella Date: Mon, 2 Mar 2026 12:11:25 +0100 Subject: [PATCH 246/291] Readd builtin_ff_cell_types for plugin parity. --- kernel/rtlil.cc | 13 +++++++++++++ kernel/rtlil.h | 3 +++ 2 files changed, 16 insertions(+) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 339450c6a..66bf3b9f7 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -288,6 +288,19 @@ void RTLIL::OwningIdString::collect_garbage() dict RTLIL::constpad; +const pool &RTLIL::builtin_ff_cell_types() { + static const pool res = []() { + pool r; + for (size_t i = 0; i < StaticCellTypes::builder.count; i++) { + auto &cell = StaticCellTypes::builder.cells[i]; + if (cell.features.is_ff) + r.insert(cell.type); + } + return r; + }(); + return res; +} + #define check(condition) log_assert(condition && "malformed Const union") const Const::bitvectype& Const::get_bits() const { diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 18bac5e6a..6f26d0d39 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -737,6 +737,9 @@ template <> struct IDMacroHelper<-1> { namespace RTLIL { extern dict constpad; + [[deprecated("use StaticCellTypes::categories.is_ff() instead")]] + const pool &builtin_ff_cell_types(); + static inline std::string escape_id(const std::string &str) { if (str.size() > 0 && str[0] != '\\' && str[0] != '$') return "\\" + str; From 16b1a914f1f131337726440415221e0ed424c228 Mon Sep 17 00:00:00 2001 From: nella Date: Mon, 2 Mar 2026 12:24:41 +0100 Subject: [PATCH 247/291] Aiger use defines for known ops. --- backends/aiger2/aiger.cc | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 1831fdb03..6f32d05de 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -47,24 +47,16 @@ PRIVATE_NAMESPACE_BEGIN static constexpr auto known_ops = []() constexpr { StaticCellTypes::Categories::Category c{}; - // bitwise - for (auto id : {ID($buf), ID($not), ID($mux), ID($and), ID($or), ID($xor), ID($xnor), ID($fa), ID($bwmux)}) + for (auto id : {BITWISE_OPS}) c.set_id(id); - // reduce - for (auto id : {ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool)}) + for (auto id : {REDUCE_OPS}) c.set_id(id); - // logic - for (auto id : {ID($logic_and), ID($logic_or), ID($logic_not)}) + for (auto id : {LOGIC_OPS}) c.set_id(id); - // gates - for (auto id : {ID($_BUF_), ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), - ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_), - ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_)}) + for (auto id : {GATE_OPS}) c.set_id(id); - // compare - for (auto id : {ID($eq), ID($ne), ID($lt), ID($le), ID($ge), ID($gt)}) + for (auto id : {CMP_OPS}) c.set_id(id); - // other for (auto id : {ID($pos), ID($pmux), ID($bmux)}) c.set_id(id); return c; From 6485a13809df455a7a6c658147f8542d6907d7d8 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 4 Mar 2026 15:17:26 +0100 Subject: [PATCH 248/291] newcelltypes: mark header unstable --- kernel/newcelltypes.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/kernel/newcelltypes.h b/kernel/newcelltypes.h index c4a4ea329..bb14293a3 100644 --- a/kernel/newcelltypes.h +++ b/kernel/newcelltypes.h @@ -6,6 +6,11 @@ YOSYS_NAMESPACE_BEGIN +/** + * This API is unstable. + * It may change or be removed in future versions and break dependent code. + */ + namespace StaticCellTypes { // Given by last internal cell type IdString constids.inc, compilation error if too low From 26dc01102ef87980fef394fb9aa37c4709e04ae0 Mon Sep 17 00:00:00 2001 From: YRabbit Date: Thu, 5 Mar 2026 09:17:37 +1000 Subject: [PATCH 249/291] GOWIN. Disable read-before-write mode. According to the latest documentation from GOWIN - "UG285-1.4E Gowin BSRAM & SSRAM User Guide" The dual port BSRAM of all 55nm devices (including GW1N, GW2A and GW1A series) does not support the read-before-write mode (WRITE_MODE = 2) Signed-off-by: YRabbit --- techlibs/gowin/brams.txt | 5 ----- 1 file changed, 5 deletions(-) diff --git a/techlibs/gowin/brams.txt b/techlibs/gowin/brams.txt index 6898c9bd9..1507d2781 100644 --- a/techlibs/gowin/brams.txt +++ b/techlibs/gowin/brams.txt @@ -51,11 +51,6 @@ ram block $__GOWIN_DP_ { portoption "WRITE_MODE" 1 { rdwr new; } - ifndef gw5a { - portoption "WRITE_MODE" 2 { - rdwr old; - } - } wrbe_separate; } } From 6ac8c8cb05675641af5d7b645b8767d114f0e1f5 Mon Sep 17 00:00:00 2001 From: Andrew Pullin Date: Fri, 23 Jan 2026 06:46:21 -0800 Subject: [PATCH 250/291] ast: Add support for array-to-array assignment This commit adds support for SystemVerilog array-to-array assignment operations that were previously unsupported: 1. Direct array assignment: `b = a;` 2. Array ternary expressions: `out = sel ? a : b;` Both single-dimensional and multi-dimensional unpacked arrays are supported. The implementation expands these array operations during AST simplification into element-wise assignments. Example of now-supported syntax: ```systemverilog wire [7:0] state_regs[8]; wire [7:0] r[8]; wire [7:0] sel[8]; assign sel = condition ? state_regs : r; ``` Co-Authored-By: Claude Opus 4.5 --- frontends/ast/simplify.cc | 194 ++++++++++++++++++++++++++++++++++ tests/svtypes/array_assign.sv | 87 +++++++++++++++ 2 files changed, 281 insertions(+) create mode 100644 tests/svtypes/array_assign.sv diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index a5b8c77ac..f314ff3d5 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -269,6 +269,83 @@ static int add_dimension(AstNode *node, AstNode *rnode) node->input_error("Unpacked array in packed struct/union member %s\n", node->str); } +// Check if node is an unexpanded array reference (AST_IDENTIFIER -> AST_MEMORY without indexing) +static bool is_unexpanded_array_ref(AstNode *node) +{ + if (node->type != AST_IDENTIFIER) + return false; + if (node->id2ast == nullptr || node->id2ast->type != AST_MEMORY) + return false; + // No indexing children = whole array reference + return node->children.empty(); +} + +// Check if two memories have compatible unpacked dimensions for array assignment +static bool arrays_have_compatible_dims(AstNode *mem_a, AstNode *mem_b) +{ + if (mem_a->unpacked_dimensions != mem_b->unpacked_dimensions) + return false; + for (int i = 0; i < mem_a->unpacked_dimensions; i++) { + if (mem_a->dimensions[i].range_width != mem_b->dimensions[i].range_width) + return false; + } + // Also check packed dimensions (element width) + int a_width, a_size, a_bits; + int b_width, b_size, b_bits; + mem_a->meminfo(a_width, a_size, a_bits); + mem_b->meminfo(b_width, b_size, b_bits); + return a_width == b_width; +} + +// Convert per-dimension element positions to declared index values. +// Position 0 is the first declared element for each unpacked dimension. +static std::vector array_indices_from_position(AstNode *mem, const std::vector &position) +{ + int num_dims = mem->unpacked_dimensions; + log_assert(GetSize(position) == num_dims); + + std::vector indices(num_dims); + for (int d = 0; d < num_dims; d++) { + int low = mem->dimensions[d].range_right; + int high = low + mem->dimensions[d].range_width - 1; + indices[d] = mem->dimensions[d].range_swapped ? (low + position[d]) : (high - position[d]); + } + return indices; +} + +// Generate all element positions for a multi-dimensional unpacked array and +// call callback once for each combination. +static void foreach_array_position(AstNode *mem, std::function&)> callback) +{ + int num_dims = mem->unpacked_dimensions; + if (num_dims == 0) { + callback({}); + return; + } + + std::vector position(num_dims, 0); + std::vector sizes(num_dims); + + for (int d = 0; d < num_dims; d++) + sizes[d] = mem->dimensions[d].range_width; + + // Iterate through all position combinations (rightmost dimension fastest). + while (true) { + callback(position); + + int d = num_dims - 1; + while (d >= 0) { + position[d]++; + if (position[d] < sizes[d]) + break; + position[d] = 0; + d--; + } + if (d < 0) + break; + } +} + static int size_packed_struct(AstNode *snode, int base_offset) { // Struct members will be laid out in the structure contiguously from left to right. @@ -3200,6 +3277,123 @@ skip_dynamic_range_lvalue_expansion:; } } + // Expand array assignment: arr_out = arr_in OR arr_out = cond ? arr_a : arr_b + // Supports multi-dimensional unpacked arrays + if ((type == AST_ASSIGN_EQ || type == AST_ASSIGN_LE || type == AST_ASSIGN) && + is_unexpanded_array_ref(children[0].get())) + { + AstNode *lhs = children[0].get(); + AstNode *rhs = children[1].get(); + AstNode *lhs_mem = lhs->id2ast; + + // Case 1: Direct array assignment (b = a) + bool is_direct_assign = is_unexpanded_array_ref(rhs); + + // Case 2: Ternary array assignment (out = sel ? a : b) + bool is_ternary_assign = (rhs->type == AST_TERNARY && + is_unexpanded_array_ref(rhs->children[1].get()) && + is_unexpanded_array_ref(rhs->children[2].get())); + + if (is_direct_assign || is_ternary_assign) + { + AstNode *direct_rhs_mem = nullptr; + AstNode *true_mem = nullptr; + AstNode *false_mem = nullptr; + + // Validate array compatibility + if (is_direct_assign) { + direct_rhs_mem = rhs->id2ast; + if (!arrays_have_compatible_dims(lhs_mem, direct_rhs_mem)) + input_error("Array dimension mismatch in assignment\n"); + } else { + true_mem = rhs->children[1]->id2ast; + false_mem = rhs->children[2]->id2ast; + if (!arrays_have_compatible_dims(lhs_mem, true_mem) || + !arrays_have_compatible_dims(lhs_mem, false_mem)) + input_error("Array dimension mismatch in ternary expression\n"); + } + + int num_dims = lhs_mem->unpacked_dimensions; + + // Helper to add index to an identifier clone + auto add_indices_to_id = [&](std::unique_ptr id, const std::vector& indices) { + if (num_dims == 1) { + // Single dimension: use AST_RANGE + id->children.push_back(std::make_unique(location, AST_RANGE, + mkconst_int(location, indices[0], true))); + } else { + // Multiple dimensions: use AST_MULTIRANGE + auto multirange = std::make_unique(location, AST_MULTIRANGE); + for (int idx : indices) { + multirange->children.push_back(std::make_unique(location, AST_RANGE, + mkconst_int(location, idx, true))); + } + id->children.push_back(std::move(multirange)); + } + id->integer = num_dims; + // Reset basic_prep so multirange gets resolved during subsequent simplify passes + id->basic_prep = false; + return id; + }; + + // Calculate total number of elements and warn if large + int total_elements = 1; + for (int d = 0; d < num_dims; d++) + total_elements *= lhs_mem->dimensions[d].range_width; + if (total_elements > 10000) + log_warning("Expanding array assignment with %d elements at %s, this may be slow.\n", + total_elements, location.to_string().c_str()); + + // Collect all assignments + std::vector> assignments; + + foreach_array_position(lhs_mem, [&](const std::vector& position) { + auto lhs_indices = array_indices_from_position(lhs_mem, position); + auto lhs_idx = add_indices_to_id(lhs->clone(), lhs_indices); + + std::unique_ptr rhs_expr; + if (is_direct_assign) { + auto rhs_indices = array_indices_from_position(direct_rhs_mem, position); + rhs_expr = add_indices_to_id(rhs->clone(), rhs_indices); + } else { + // Ternary case + AstNode *cond = rhs->children[0].get(); + AstNode *true_val = rhs->children[1].get(); + AstNode *false_val = rhs->children[2].get(); + + auto true_indices = array_indices_from_position(true_mem, position); + auto false_indices = array_indices_from_position(false_mem, position); + auto true_idx = add_indices_to_id(true_val->clone(), true_indices); + auto false_idx = add_indices_to_id(false_val->clone(), false_indices); + + rhs_expr = std::make_unique(location, AST_TERNARY, + cond->clone(), std::move(true_idx), std::move(false_idx)); + } + + auto assign = std::make_unique(location, type, + std::move(lhs_idx), std::move(rhs_expr)); + assign->was_checked = true; + assignments.push_back(std::move(assign)); + }); + + // For continuous assignments, add to module; for procedural, use block + if (type == AST_ASSIGN) { + // Add all but last to module + for (size_t i = 0; i + 1 < assignments.size(); i++) + current_ast_mod->children.push_back(std::move(assignments[i])); + // Last one replaces current node + newNode = std::move(assignments.back()); + } else { + // Wrap in AST_BLOCK for procedural + newNode = std::make_unique(location, AST_BLOCK); + for (auto& assign : assignments) + newNode->children.push_back(std::move(assign)); + } + + goto apply_newNode; + } + } + // assignment with memory in left-hand side expression -> replace with memory write port if (stage > 1 && (type == AST_ASSIGN_EQ || type == AST_ASSIGN_LE) && children[0]->type == AST_IDENTIFIER && children[0]->id2ast && children[0]->id2ast->type == AST_MEMORY && children[0]->id2ast->children.size() >= 2 && diff --git a/tests/svtypes/array_assign.sv b/tests/svtypes/array_assign.sv new file mode 100644 index 000000000..a5ca6363c --- /dev/null +++ b/tests/svtypes/array_assign.sv @@ -0,0 +1,87 @@ +// Test for array-to-array assignment and ternary expressions + +`define STRINGIFY(x) `"x`" +`define STATIC_ASSERT(x) if(!(x)) $error({"assert failed: ", `STRINGIFY(x)}) + +module top; + // Test 1: Basic array ternary with continuous assignment + reg [7:0] a1[4]; + reg [7:0] b1[4]; + wire [7:0] out1[4]; + wire sel1; + assign out1 = sel1 ? a1 : b1; + `STATIC_ASSERT($bits(out1) == 32); + + // Test 2: Non-zero base index + reg [7:0] a2[3:6]; + reg [7:0] b2[3:6]; + wire [7:0] out2[3:6]; + wire sel2; + assign out2 = sel2 ? a2 : b2; + `STATIC_ASSERT($bits(out2) == 32); + + // Test 3: Single-bit elements + reg a3[8]; + reg b3[8]; + wire out3[8]; + wire sel3; + assign out3 = sel3 ? a3 : b3; + `STATIC_ASSERT($bits(out3) == 8); + + // Test 4: Multi-dimensional array ternary + reg [7:0] a4[2][3]; + reg [7:0] b4[2][3]; + wire [7:0] out4[2][3]; + wire sel4; + assign out4 = sel4 ? a4 : b4; + `STATIC_ASSERT($bits(out4) == 48); + + // Test 5: Direct array assignment (continuous) + reg [7:0] a5[4]; + wire [7:0] b5[4]; + assign b5 = a5; + `STATIC_ASSERT($bits(b5) == 32); + + // Test 6: Multi-dimensional direct assignment (continuous) + reg [7:0] a6[2][3]; + wire [7:0] b6[2][3]; + assign b6 = a6; + `STATIC_ASSERT($bits(b6) == 48); + + // Test 7: Procedural direct assignment with different unpacked index ranges + // Covers the AST_BLOCK expansion path for AST_ASSIGN_EQ. + logic pa [1:0][1:0]; + logic pb [1:0][0:1]; + always_comb begin + pa[0][0] = 1'b0; + pa[0][1] = 1'b1; + pa[1][0] = 1'b1; + pa[1][1] = 1'b1; + + pb = pa; + + assert(pb[0][1] == 1'b0); + assert(pb[0][0] == 1'b1); + assert(pb[1][1] == 1'b1); + assert(pb[1][0] == 1'b1); + end + + // Test 8: Procedural ternary assignment on arrays + // Covers the AST_BLOCK expansion path for ternary RHS. + logic pt_a [1:0]; + logic pt_b [1:0]; + logic pt_o [1:0]; + logic pt_sel; + always_comb begin + pt_a[0] = 1'b0; + pt_a[1] = 1'b1; + pt_b[0] = 1'b1; + pt_b[1] = 1'b0; + pt_sel = 1'b1; + + pt_o = pt_sel ? pt_a : pt_b; + + assert(pt_o[0] == 1'b0); + assert(pt_o[1] == 1'b1); + end +endmodule From d5ea7f70167291655a3e1110fe18978b7c1e6876 Mon Sep 17 00:00:00 2001 From: Lofty Date: Tue, 23 Sep 2025 11:08:17 +0100 Subject: [PATCH 251/291] Create synth_analogdevices --- techlibs/analogdevices/Makefile.inc | 22 + techlibs/analogdevices/abc9_model.v | 39 + techlibs/analogdevices/arith_map.v | 157 + techlibs/analogdevices/brams.txt | 165 + techlibs/analogdevices/brams_defs.vh | 561 + techlibs/analogdevices/brams_map.v | 284 + techlibs/analogdevices/cells_map.v | 364 + techlibs/analogdevices/cells_sim.v | 4377 ++ techlibs/analogdevices/cells_xtra.py | 730 + techlibs/analogdevices/cells_xtra.v | 34120 ++++++++++++++++ techlibs/analogdevices/dsp_map.v | 50 + techlibs/analogdevices/ff_map.v | 120 + techlibs/analogdevices/lut_map.v | 83 + techlibs/analogdevices/lutrams.txt | 78 + techlibs/analogdevices/lutrams_map.v | 459 + techlibs/analogdevices/mux_map.v | 74 + techlibs/analogdevices/synth_analogdevices.cc | 504 + 17 files changed, 42187 insertions(+) create mode 100644 techlibs/analogdevices/Makefile.inc create mode 100644 techlibs/analogdevices/abc9_model.v create mode 100644 techlibs/analogdevices/arith_map.v create mode 100644 techlibs/analogdevices/brams.txt create mode 100644 techlibs/analogdevices/brams_defs.vh create mode 100644 techlibs/analogdevices/brams_map.v create mode 100644 techlibs/analogdevices/cells_map.v create mode 100644 techlibs/analogdevices/cells_sim.v create mode 100644 techlibs/analogdevices/cells_xtra.py create mode 100644 techlibs/analogdevices/cells_xtra.v create mode 100644 techlibs/analogdevices/dsp_map.v create mode 100644 techlibs/analogdevices/ff_map.v create mode 100644 techlibs/analogdevices/lut_map.v create mode 100644 techlibs/analogdevices/lutrams.txt create mode 100644 techlibs/analogdevices/lutrams_map.v create mode 100644 techlibs/analogdevices/mux_map.v create mode 100644 techlibs/analogdevices/synth_analogdevices.cc diff --git a/techlibs/analogdevices/Makefile.inc b/techlibs/analogdevices/Makefile.inc new file mode 100644 index 000000000..52a48f8b4 --- /dev/null +++ b/techlibs/analogdevices/Makefile.inc @@ -0,0 +1,22 @@ + +OBJS += techlibs/analogdevices/synth_analogdevices.o + +$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/cells_map.v)) +$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/cells_sim.v)) +$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/cells_xtra.v)) + +$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/lutrams.txt)) +$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/lutrams_map.v)) + +$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/brams_defs.vh)) + +$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/brams.txt)) +$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/brams_map.v)) + +$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/arith_map.v)) +$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/ff_map.v)) +$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/lut_map.v)) +$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/mux_map.v)) +$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/dsp_map.v)) + +$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/abc9_model.v)) diff --git a/techlibs/analogdevices/abc9_model.v b/techlibs/analogdevices/abc9_model.v new file mode 100644 index 000000000..3958a2bf0 --- /dev/null +++ b/techlibs/analogdevices/abc9_model.v @@ -0,0 +1,39 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * 2019 Eddie Hung + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +// ============================================================================ + +// Box containing MUXF7.[AB] + MUXF8, +// Necessary to make these an atomic unit so that +// ABC cannot optimise just one of the MUXF7 away +// and expect to save on its delay +(* abc9_box, lib_whitebox *) +module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1); + assign O = S1 ? (S0 ? I3 : I2) + : (S0 ? I1 : I0); + specify + (I0 => O) = 294; + (I1 => O) = 297; + (I2 => O) = 311; + (I3 => O) = 317; + (S0 => O) = 390; + (S1 => O) = 273; + endspecify +endmodule diff --git a/techlibs/analogdevices/arith_map.v b/techlibs/analogdevices/arith_map.v new file mode 100644 index 000000000..288e1eccf --- /dev/null +++ b/techlibs/analogdevices/arith_map.v @@ -0,0 +1,157 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +// ============================================================================ +// LCU + +(* techmap_celltype = "$lcu" *) +module _80_analogdevices_lcu (P, G, CI, CO); + parameter WIDTH = 2; + + (* force_downto *) + input [WIDTH-1:0] P, G; + input CI; + + (* force_downto *) + output [WIDTH-1:0] CO; + + wire _TECHMAP_FAIL_ = WIDTH <= 2; + + genvar i; + +generate + localparam CARRY4_COUNT = (WIDTH + 3) / 4; + localparam MAX_WIDTH = CARRY4_COUNT * 4; + localparam PAD_WIDTH = MAX_WIDTH - WIDTH; + + (* force_downto *) + wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, P & ~G}; + (* force_downto *) + wire [MAX_WIDTH-1:0] GG = {{PAD_WIDTH{1'b0}}, G}; + (* force_downto *) + wire [MAX_WIDTH-1:0] C; + assign CO = C; + + generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice + if (i == 0) begin + CRY4 carry4 + ( + .CYINIT(CI), + .CI (1'd0), + .DI (GG[i*4 +: 4]), + .S (S [i*4 +: 4]), + .CO (C [i*4 +: 4]), + ); + end else begin + CRY4 carry4 + ( + .CYINIT(1'd0), + .CI (C [i*4 - 1]), + .DI (GG[i*4 +: 4]), + .S (S [i*4 +: 4]), + .CO (C [i*4 +: 4]), + ); + end + end endgenerate +endgenerate + +endmodule + + +// ============================================================================ +// ALU + +(* techmap_celltype = "$alu" *) +module _80_analogdevices_alu (A, B, CI, BI, X, Y, CO); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + parameter _TECHMAP_CONSTVAL_CI_ = 0; + parameter _TECHMAP_CONSTMSK_CI_ = 0; + + (* force_downto *) + input [A_WIDTH-1:0] A; + (* force_downto *) + input [B_WIDTH-1:0] B; + (* force_downto *) + output [Y_WIDTH-1:0] X, Y; + + input CI, BI; + (* force_downto *) + output [Y_WIDTH-1:0] CO; + + wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; + + (* force_downto *) + wire [Y_WIDTH-1:0] A_buf, B_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + + (* force_downto *) + wire [Y_WIDTH-1:0] AA = A_buf; + (* force_downto *) + wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; + + genvar i; + + localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4; + localparam MAX_WIDTH = CARRY4_COUNT * 4; + localparam PAD_WIDTH = MAX_WIDTH - Y_WIDTH; + + (* force_downto *) + wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, AA ^ BB}; + (* force_downto *) + wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA}; + + (* force_downto *) + wire [MAX_WIDTH-1:0] O; + (* force_downto *) + wire [MAX_WIDTH-1:0] C; + assign Y = O, CO = C; + + genvar i; + generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice + if (i == 0) begin + CRY4 carry4 + ( + .CYINIT(CI), + .CI (1'd0), + .DI (DI[i*4 +: 4]), + .S (S [i*4 +: 4]), + .O (O [i*4 +: 4]), + .CO (C [i*4 +: 4]) + ); + end else begin + CRY4 carry4 + ( + .CYINIT(1'd0), + .CI (C [i*4 - 1]), + .DI (DI[i*4 +: 4]), + .S (S [i*4 +: 4]), + .O (O [i*4 +: 4]), + .CO (C [i*4 +: 4]) + ); + end + end endgenerate + + assign X = S; +endmodule + diff --git a/techlibs/analogdevices/brams.txt b/techlibs/analogdevices/brams.txt new file mode 100644 index 000000000..7bcbeb0a8 --- /dev/null +++ b/techlibs/analogdevices/brams.txt @@ -0,0 +1,165 @@ +# Block RAMs for Virtex 4+. +# The corresponding mapping files are: +# - brams_xc6v_map.v: Virtex 6, Series 7 + +ram block $__ANALOGDEVICES_BLOCKRAM_TDP_ { + byte 9; + ifdef HAS_SIZE_36 { + option "MODE" "HALF" { + abits 14; + widths 1 2 4 9 18 per_port; + cost 129; + } + option "MODE" "FULL" { + abits 15; + widths 1 2 4 9 18 36 per_port; + cost 257; + } + ifdef HAS_CASCADE { + option "MODE" "CASCADE" { + abits 16; + # hack to enforce same INIT layout as in the other modes + widths 1 2 4 9 per_port; + cost 513; + } + } + } else { + option "MODE" "FULL" { + abits 14; + widths 1 2 4 9 18 36 per_port; + cost 129; + } + ifdef HAS_CASCADE { + option "MODE" "CASCADE" { + abits 15; + widths 1 2 4 9 per_port; + cost 257; + } + } + } + init any; + port srsw "A" "B" { + option "MODE" "HALF" { + width mix; + } + option "MODE" "FULL" { + width mix; + } + option "MODE" "CASCADE" { + width mix 1; + } + ifdef HAS_ADDRCE { + # TODO + # addrce; + } + # Spartan 6 and Virtex 6 have a bug where READ_FIRST is not usable with asynchronous clocks. + ifdef HAS_CONFLICT_BUG { + option "HAS_RDFIRST" 1 { + clock posedge "C"; + } + option "HAS_RDFIRST" 0 { + clock posedge; + } + } else { + clock posedge; + } + clken; + rdsrst any gated_clken; + rdinit any; + portoption "WRITE_MODE" "NO_CHANGE" { + rdwr no_change; + option "MODE" "CASCADE" { + forbid; + } + } + portoption "WRITE_MODE" "WRITE_FIRST" { + ifdef HAS_SIZE_36 { + rdwr new; + } else { + rdwr new_only; + } + } + ifdef HAS_CONFLICT_BUG { + option "HAS_RDFIRST" 1 { + portoption "WRITE_MODE" "READ_FIRST" { + rdwr old; + wrtrans all old; + } + } + } else { + portoption "WRITE_MODE" "READ_FIRST" { + rdwr old; + wrtrans all old; + } + } + optional_rw; + } +} + +ifdef HAS_SIZE_36 { + ram block $__ANALOGDEVICES_BLOCKRAM_SDP_ { + byte 9; + option "MODE" "HALF" { + abits 14; + widths 1 2 4 9 18 36 per_port; + cost 129; + } + option "MODE" "FULL" { + abits 15; + widths 1 2 4 9 18 36 72 per_port; + cost 257; + } + init any; + port sw "W" { + ifndef HAS_MIXWIDTH_SDP { + option "MODE" "HALF" width 36; + option "MODE" "FULL" width 72; + } + ifdef HAS_ADDRCE { + # TODO + # addrce; + } + # Spartan 6 and Virtex 6 have a bug where READ_FIRST is not usable with asynchronous clocks. + ifdef HAS_CONFLICT_BUG { + option "WRITE_MODE" "READ_FIRST" { + clock posedge "C"; + } + option "WRITE_MODE" "WRITE_FIRST" { + clock posedge; + } + } else { + clock posedge; + } + clken; + option "WRITE_MODE" "READ_FIRST" { + wrtrans all old; + } + optional; + } + port sr "R" { + ifndef HAS_MIXWIDTH_SDP { + option "MODE" "HALF" width 36; + option "MODE" "FULL" width 72; + } + ifdef HAS_ADDRCE { + # TODO + # addrce; + } + # Spartan 6 and Virtex 6 have a bug where READ_FIRST is not usable with asynchronous clocks. + ifdef HAS_CONFLICT_BUG { + option "WRITE_MODE" "READ_FIRST" { + clock posedge "C"; + } + option "WRITE_MODE" "WRITE_FIRST" { + clock posedge; + } + } else { + clock posedge; + } + clken; + rdsrst any gated_clken; + rdinit any; + optional; + } + } +} diff --git a/techlibs/analogdevices/brams_defs.vh b/techlibs/analogdevices/brams_defs.vh new file mode 100644 index 000000000..69fe5d716 --- /dev/null +++ b/techlibs/analogdevices/brams_defs.vh @@ -0,0 +1,561 @@ +`define PARAMS_INIT_9 \ + .INIT_00(slice_init('h00)), \ + .INIT_01(slice_init('h01)), \ + .INIT_02(slice_init('h02)), \ + .INIT_03(slice_init('h03)), \ + .INIT_04(slice_init('h04)), \ + .INIT_05(slice_init('h05)), \ + .INIT_06(slice_init('h06)), \ + .INIT_07(slice_init('h07)), \ + .INIT_08(slice_init('h08)), \ + .INIT_09(slice_init('h09)), \ + .INIT_0A(slice_init('h0a)), \ + .INIT_0B(slice_init('h0b)), \ + .INIT_0C(slice_init('h0c)), \ + .INIT_0D(slice_init('h0d)), \ + .INIT_0E(slice_init('h0e)), \ + .INIT_0F(slice_init('h0f)), \ + .INIT_10(slice_init('h10)), \ + .INIT_11(slice_init('h11)), \ + .INIT_12(slice_init('h12)), \ + .INIT_13(slice_init('h13)), \ + .INIT_14(slice_init('h14)), \ + .INIT_15(slice_init('h15)), \ + .INIT_16(slice_init('h16)), \ + .INIT_17(slice_init('h17)), \ + .INIT_18(slice_init('h18)), \ + .INIT_19(slice_init('h19)), \ + .INIT_1A(slice_init('h1a)), \ + .INIT_1B(slice_init('h1b)), \ + .INIT_1C(slice_init('h1c)), \ + .INIT_1D(slice_init('h1d)), \ + .INIT_1E(slice_init('h1e)), \ + .INIT_1F(slice_init('h1f)), + +`define PARAMS_INITP_9 \ + .INITP_00(slice_initp('h00)), \ + .INITP_01(slice_initp('h01)), \ + .INITP_02(slice_initp('h02)), \ + .INITP_03(slice_initp('h03)), + +`define PARAMS_INIT_18 \ + .INIT_00(slice_init('h00)), \ + .INIT_01(slice_init('h01)), \ + .INIT_02(slice_init('h02)), \ + .INIT_03(slice_init('h03)), \ + .INIT_04(slice_init('h04)), \ + .INIT_05(slice_init('h05)), \ + .INIT_06(slice_init('h06)), \ + .INIT_07(slice_init('h07)), \ + .INIT_08(slice_init('h08)), \ + .INIT_09(slice_init('h09)), \ + .INIT_0A(slice_init('h0a)), \ + .INIT_0B(slice_init('h0b)), \ + .INIT_0C(slice_init('h0c)), \ + .INIT_0D(slice_init('h0d)), \ + .INIT_0E(slice_init('h0e)), \ + .INIT_0F(slice_init('h0f)), \ + .INIT_10(slice_init('h10)), \ + .INIT_11(slice_init('h11)), \ + .INIT_12(slice_init('h12)), \ + .INIT_13(slice_init('h13)), \ + .INIT_14(slice_init('h14)), \ + .INIT_15(slice_init('h15)), \ + .INIT_16(slice_init('h16)), \ + .INIT_17(slice_init('h17)), \ + .INIT_18(slice_init('h18)), \ + .INIT_19(slice_init('h19)), \ + .INIT_1A(slice_init('h1a)), \ + .INIT_1B(slice_init('h1b)), \ + .INIT_1C(slice_init('h1c)), \ + .INIT_1D(slice_init('h1d)), \ + .INIT_1E(slice_init('h1e)), \ + .INIT_1F(slice_init('h1f)), \ + .INIT_20(slice_init('h20)), \ + .INIT_21(slice_init('h21)), \ + .INIT_22(slice_init('h22)), \ + .INIT_23(slice_init('h23)), \ + .INIT_24(slice_init('h24)), \ + .INIT_25(slice_init('h25)), \ + .INIT_26(slice_init('h26)), \ + .INIT_27(slice_init('h27)), \ + .INIT_28(slice_init('h28)), \ + .INIT_29(slice_init('h29)), \ + .INIT_2A(slice_init('h2a)), \ + .INIT_2B(slice_init('h2b)), \ + .INIT_2C(slice_init('h2c)), \ + .INIT_2D(slice_init('h2d)), \ + .INIT_2E(slice_init('h2e)), \ + .INIT_2F(slice_init('h2f)), \ + .INIT_30(slice_init('h30)), \ + .INIT_31(slice_init('h31)), \ + .INIT_32(slice_init('h32)), \ + .INIT_33(slice_init('h33)), \ + .INIT_34(slice_init('h34)), \ + .INIT_35(slice_init('h35)), \ + .INIT_36(slice_init('h36)), \ + .INIT_37(slice_init('h37)), \ + .INIT_38(slice_init('h38)), \ + .INIT_39(slice_init('h39)), \ + .INIT_3A(slice_init('h3a)), \ + .INIT_3B(slice_init('h3b)), \ + .INIT_3C(slice_init('h3c)), \ + .INIT_3D(slice_init('h3d)), \ + .INIT_3E(slice_init('h3e)), \ + .INIT_3F(slice_init('h3f)), + +`define PARAMS_INIT_18_U \ + .INIT_00(slice_init('h40)), \ + .INIT_01(slice_init('h41)), \ + .INIT_02(slice_init('h42)), \ + .INIT_03(slice_init('h43)), \ + .INIT_04(slice_init('h44)), \ + .INIT_05(slice_init('h45)), \ + .INIT_06(slice_init('h46)), \ + .INIT_07(slice_init('h47)), \ + .INIT_08(slice_init('h48)), \ + .INIT_09(slice_init('h49)), \ + .INIT_0A(slice_init('h4a)), \ + .INIT_0B(slice_init('h4b)), \ + .INIT_0C(slice_init('h4c)), \ + .INIT_0D(slice_init('h4d)), \ + .INIT_0E(slice_init('h4e)), \ + .INIT_0F(slice_init('h4f)), \ + .INIT_10(slice_init('h50)), \ + .INIT_11(slice_init('h51)), \ + .INIT_12(slice_init('h52)), \ + .INIT_13(slice_init('h53)), \ + .INIT_14(slice_init('h54)), \ + .INIT_15(slice_init('h55)), \ + .INIT_16(slice_init('h56)), \ + .INIT_17(slice_init('h57)), \ + .INIT_18(slice_init('h58)), \ + .INIT_19(slice_init('h59)), \ + .INIT_1A(slice_init('h5a)), \ + .INIT_1B(slice_init('h5b)), \ + .INIT_1C(slice_init('h5c)), \ + .INIT_1D(slice_init('h5d)), \ + .INIT_1E(slice_init('h5e)), \ + .INIT_1F(slice_init('h5f)), \ + .INIT_20(slice_init('h60)), \ + .INIT_21(slice_init('h61)), \ + .INIT_22(slice_init('h62)), \ + .INIT_23(slice_init('h63)), \ + .INIT_24(slice_init('h64)), \ + .INIT_25(slice_init('h65)), \ + .INIT_26(slice_init('h66)), \ + .INIT_27(slice_init('h67)), \ + .INIT_28(slice_init('h68)), \ + .INIT_29(slice_init('h69)), \ + .INIT_2A(slice_init('h6a)), \ + .INIT_2B(slice_init('h6b)), \ + .INIT_2C(slice_init('h6c)), \ + .INIT_2D(slice_init('h6d)), \ + .INIT_2E(slice_init('h6e)), \ + .INIT_2F(slice_init('h6f)), \ + .INIT_30(slice_init('h70)), \ + .INIT_31(slice_init('h71)), \ + .INIT_32(slice_init('h72)), \ + .INIT_33(slice_init('h73)), \ + .INIT_34(slice_init('h74)), \ + .INIT_35(slice_init('h75)), \ + .INIT_36(slice_init('h76)), \ + .INIT_37(slice_init('h77)), \ + .INIT_38(slice_init('h78)), \ + .INIT_39(slice_init('h79)), \ + .INIT_3A(slice_init('h7a)), \ + .INIT_3B(slice_init('h7b)), \ + .INIT_3C(slice_init('h7c)), \ + .INIT_3D(slice_init('h7d)), \ + .INIT_3E(slice_init('h7e)), \ + .INIT_3F(slice_init('h7f)), + +`define PARAMS_INITP_18 \ + .INITP_00(slice_initp('h00)), \ + .INITP_01(slice_initp('h01)), \ + .INITP_02(slice_initp('h02)), \ + .INITP_03(slice_initp('h03)), \ + .INITP_04(slice_initp('h04)), \ + .INITP_05(slice_initp('h05)), \ + .INITP_06(slice_initp('h06)), \ + .INITP_07(slice_initp('h07)), + +`define PARAMS_INIT_36 \ + .INIT_00(slice_init('h00)), \ + .INIT_01(slice_init('h01)), \ + .INIT_02(slice_init('h02)), \ + .INIT_03(slice_init('h03)), \ + .INIT_04(slice_init('h04)), \ + .INIT_05(slice_init('h05)), \ + .INIT_06(slice_init('h06)), \ + .INIT_07(slice_init('h07)), \ + .INIT_08(slice_init('h08)), \ + .INIT_09(slice_init('h09)), \ + .INIT_0A(slice_init('h0a)), \ + .INIT_0B(slice_init('h0b)), \ + .INIT_0C(slice_init('h0c)), \ + .INIT_0D(slice_init('h0d)), \ + .INIT_0E(slice_init('h0e)), \ + .INIT_0F(slice_init('h0f)), \ + .INIT_10(slice_init('h10)), \ + .INIT_11(slice_init('h11)), \ + .INIT_12(slice_init('h12)), \ + .INIT_13(slice_init('h13)), \ + .INIT_14(slice_init('h14)), \ + .INIT_15(slice_init('h15)), \ + .INIT_16(slice_init('h16)), \ + .INIT_17(slice_init('h17)), \ + .INIT_18(slice_init('h18)), \ + .INIT_19(slice_init('h19)), \ + .INIT_1A(slice_init('h1a)), \ + .INIT_1B(slice_init('h1b)), \ + .INIT_1C(slice_init('h1c)), \ + .INIT_1D(slice_init('h1d)), \ + .INIT_1E(slice_init('h1e)), \ + .INIT_1F(slice_init('h1f)), \ + .INIT_20(slice_init('h20)), \ + .INIT_21(slice_init('h21)), \ + .INIT_22(slice_init('h22)), \ + .INIT_23(slice_init('h23)), \ + .INIT_24(slice_init('h24)), \ + .INIT_25(slice_init('h25)), \ + .INIT_26(slice_init('h26)), \ + .INIT_27(slice_init('h27)), \ + .INIT_28(slice_init('h28)), \ + .INIT_29(slice_init('h29)), \ + .INIT_2A(slice_init('h2a)), \ + .INIT_2B(slice_init('h2b)), \ + .INIT_2C(slice_init('h2c)), \ + .INIT_2D(slice_init('h2d)), \ + .INIT_2E(slice_init('h2e)), \ + .INIT_2F(slice_init('h2f)), \ + .INIT_30(slice_init('h30)), \ + .INIT_31(slice_init('h31)), \ + .INIT_32(slice_init('h32)), \ + .INIT_33(slice_init('h33)), \ + .INIT_34(slice_init('h34)), \ + .INIT_35(slice_init('h35)), \ + .INIT_36(slice_init('h36)), \ + .INIT_37(slice_init('h37)), \ + .INIT_38(slice_init('h38)), \ + .INIT_39(slice_init('h39)), \ + .INIT_3A(slice_init('h3a)), \ + .INIT_3B(slice_init('h3b)), \ + .INIT_3C(slice_init('h3c)), \ + .INIT_3D(slice_init('h3d)), \ + .INIT_3E(slice_init('h3e)), \ + .INIT_3F(slice_init('h3f)), \ + .INIT_40(slice_init('h40)), \ + .INIT_41(slice_init('h41)), \ + .INIT_42(slice_init('h42)), \ + .INIT_43(slice_init('h43)), \ + .INIT_44(slice_init('h44)), \ + .INIT_45(slice_init('h45)), \ + .INIT_46(slice_init('h46)), \ + .INIT_47(slice_init('h47)), \ + .INIT_48(slice_init('h48)), \ + .INIT_49(slice_init('h49)), \ + .INIT_4A(slice_init('h4a)), \ + .INIT_4B(slice_init('h4b)), \ + .INIT_4C(slice_init('h4c)), \ + .INIT_4D(slice_init('h4d)), \ + .INIT_4E(slice_init('h4e)), \ + .INIT_4F(slice_init('h4f)), \ + .INIT_50(slice_init('h50)), \ + .INIT_51(slice_init('h51)), \ + .INIT_52(slice_init('h52)), \ + .INIT_53(slice_init('h53)), \ + .INIT_54(slice_init('h54)), \ + .INIT_55(slice_init('h55)), \ + .INIT_56(slice_init('h56)), \ + .INIT_57(slice_init('h57)), \ + .INIT_58(slice_init('h58)), \ + .INIT_59(slice_init('h59)), \ + .INIT_5A(slice_init('h5a)), \ + .INIT_5B(slice_init('h5b)), \ + .INIT_5C(slice_init('h5c)), \ + .INIT_5D(slice_init('h5d)), \ + .INIT_5E(slice_init('h5e)), \ + .INIT_5F(slice_init('h5f)), \ + .INIT_60(slice_init('h60)), \ + .INIT_61(slice_init('h61)), \ + .INIT_62(slice_init('h62)), \ + .INIT_63(slice_init('h63)), \ + .INIT_64(slice_init('h64)), \ + .INIT_65(slice_init('h65)), \ + .INIT_66(slice_init('h66)), \ + .INIT_67(slice_init('h67)), \ + .INIT_68(slice_init('h68)), \ + .INIT_69(slice_init('h69)), \ + .INIT_6A(slice_init('h6a)), \ + .INIT_6B(slice_init('h6b)), \ + .INIT_6C(slice_init('h6c)), \ + .INIT_6D(slice_init('h6d)), \ + .INIT_6E(slice_init('h6e)), \ + .INIT_6F(slice_init('h6f)), \ + .INIT_70(slice_init('h70)), \ + .INIT_71(slice_init('h71)), \ + .INIT_72(slice_init('h72)), \ + .INIT_73(slice_init('h73)), \ + .INIT_74(slice_init('h74)), \ + .INIT_75(slice_init('h75)), \ + .INIT_76(slice_init('h76)), \ + .INIT_77(slice_init('h77)), \ + .INIT_78(slice_init('h78)), \ + .INIT_79(slice_init('h79)), \ + .INIT_7A(slice_init('h7a)), \ + .INIT_7B(slice_init('h7b)), \ + .INIT_7C(slice_init('h7c)), \ + .INIT_7D(slice_init('h7d)), \ + .INIT_7E(slice_init('h7e)), \ + .INIT_7F(slice_init('h7f)), + +`define PARAMS_INIT_36_U \ + .INIT_00(slice_init('h80)), \ + .INIT_01(slice_init('h81)), \ + .INIT_02(slice_init('h82)), \ + .INIT_03(slice_init('h83)), \ + .INIT_04(slice_init('h84)), \ + .INIT_05(slice_init('h85)), \ + .INIT_06(slice_init('h86)), \ + .INIT_07(slice_init('h87)), \ + .INIT_08(slice_init('h88)), \ + .INIT_09(slice_init('h89)), \ + .INIT_0A(slice_init('h8a)), \ + .INIT_0B(slice_init('h8b)), \ + .INIT_0C(slice_init('h8c)), \ + .INIT_0D(slice_init('h8d)), \ + .INIT_0E(slice_init('h8e)), \ + .INIT_0F(slice_init('h8f)), \ + .INIT_10(slice_init('h90)), \ + .INIT_11(slice_init('h91)), \ + .INIT_12(slice_init('h92)), \ + .INIT_13(slice_init('h93)), \ + .INIT_14(slice_init('h94)), \ + .INIT_15(slice_init('h95)), \ + .INIT_16(slice_init('h96)), \ + .INIT_17(slice_init('h97)), \ + .INIT_18(slice_init('h98)), \ + .INIT_19(slice_init('h99)), \ + .INIT_1A(slice_init('h9a)), \ + .INIT_1B(slice_init('h9b)), \ + .INIT_1C(slice_init('h9c)), \ + .INIT_1D(slice_init('h9d)), \ + .INIT_1E(slice_init('h9e)), \ + .INIT_1F(slice_init('h9f)), \ + .INIT_20(slice_init('ha0)), \ + .INIT_21(slice_init('ha1)), \ + .INIT_22(slice_init('ha2)), \ + .INIT_23(slice_init('ha3)), \ + .INIT_24(slice_init('ha4)), \ + .INIT_25(slice_init('ha5)), \ + .INIT_26(slice_init('ha6)), \ + .INIT_27(slice_init('ha7)), \ + .INIT_28(slice_init('ha8)), \ + .INIT_29(slice_init('ha9)), \ + .INIT_2A(slice_init('haa)), \ + .INIT_2B(slice_init('hab)), \ + .INIT_2C(slice_init('hac)), \ + .INIT_2D(slice_init('had)), \ + .INIT_2E(slice_init('hae)), \ + .INIT_2F(slice_init('haf)), \ + .INIT_30(slice_init('hb0)), \ + .INIT_31(slice_init('hb1)), \ + .INIT_32(slice_init('hb2)), \ + .INIT_33(slice_init('hb3)), \ + .INIT_34(slice_init('hb4)), \ + .INIT_35(slice_init('hb5)), \ + .INIT_36(slice_init('hb6)), \ + .INIT_37(slice_init('hb7)), \ + .INIT_38(slice_init('hb8)), \ + .INIT_39(slice_init('hb9)), \ + .INIT_3A(slice_init('hba)), \ + .INIT_3B(slice_init('hbb)), \ + .INIT_3C(slice_init('hbc)), \ + .INIT_3D(slice_init('hbd)), \ + .INIT_3E(slice_init('hbe)), \ + .INIT_3F(slice_init('hbf)), \ + .INIT_40(slice_init('hc0)), \ + .INIT_41(slice_init('hc1)), \ + .INIT_42(slice_init('hc2)), \ + .INIT_43(slice_init('hc3)), \ + .INIT_44(slice_init('hc4)), \ + .INIT_45(slice_init('hc5)), \ + .INIT_46(slice_init('hc6)), \ + .INIT_47(slice_init('hc7)), \ + .INIT_48(slice_init('hc8)), \ + .INIT_49(slice_init('hc9)), \ + .INIT_4A(slice_init('hca)), \ + .INIT_4B(slice_init('hcb)), \ + .INIT_4C(slice_init('hcc)), \ + .INIT_4D(slice_init('hcd)), \ + .INIT_4E(slice_init('hce)), \ + .INIT_4F(slice_init('hcf)), \ + .INIT_50(slice_init('hd0)), \ + .INIT_51(slice_init('hd1)), \ + .INIT_52(slice_init('hd2)), \ + .INIT_53(slice_init('hd3)), \ + .INIT_54(slice_init('hd4)), \ + .INIT_55(slice_init('hd5)), \ + .INIT_56(slice_init('hd6)), \ + .INIT_57(slice_init('hd7)), \ + .INIT_58(slice_init('hd8)), \ + .INIT_59(slice_init('hd9)), \ + .INIT_5A(slice_init('hda)), \ + .INIT_5B(slice_init('hdb)), \ + .INIT_5C(slice_init('hdc)), \ + .INIT_5D(slice_init('hdd)), \ + .INIT_5E(slice_init('hde)), \ + .INIT_5F(slice_init('hdf)), \ + .INIT_60(slice_init('he0)), \ + .INIT_61(slice_init('he1)), \ + .INIT_62(slice_init('he2)), \ + .INIT_63(slice_init('he3)), \ + .INIT_64(slice_init('he4)), \ + .INIT_65(slice_init('he5)), \ + .INIT_66(slice_init('he6)), \ + .INIT_67(slice_init('he7)), \ + .INIT_68(slice_init('he8)), \ + .INIT_69(slice_init('he9)), \ + .INIT_6A(slice_init('hea)), \ + .INIT_6B(slice_init('heb)), \ + .INIT_6C(slice_init('hec)), \ + .INIT_6D(slice_init('hed)), \ + .INIT_6E(slice_init('hee)), \ + .INIT_6F(slice_init('hef)), \ + .INIT_70(slice_init('hf0)), \ + .INIT_71(slice_init('hf1)), \ + .INIT_72(slice_init('hf2)), \ + .INIT_73(slice_init('hf3)), \ + .INIT_74(slice_init('hf4)), \ + .INIT_75(slice_init('hf5)), \ + .INIT_76(slice_init('hf6)), \ + .INIT_77(slice_init('hf7)), \ + .INIT_78(slice_init('hf8)), \ + .INIT_79(slice_init('hf9)), \ + .INIT_7A(slice_init('hfa)), \ + .INIT_7B(slice_init('hfb)), \ + .INIT_7C(slice_init('hfc)), \ + .INIT_7D(slice_init('hfd)), \ + .INIT_7E(slice_init('hfe)), \ + .INIT_7F(slice_init('hff)), + +`define PARAMS_INITP_36 \ + .INITP_00(slice_initp('h00)), \ + .INITP_01(slice_initp('h01)), \ + .INITP_02(slice_initp('h02)), \ + .INITP_03(slice_initp('h03)), \ + .INITP_04(slice_initp('h04)), \ + .INITP_05(slice_initp('h05)), \ + .INITP_06(slice_initp('h06)), \ + .INITP_07(slice_initp('h07)), \ + .INITP_08(slice_initp('h08)), \ + .INITP_09(slice_initp('h09)), \ + .INITP_0A(slice_initp('h0a)), \ + .INITP_0B(slice_initp('h0b)), \ + .INITP_0C(slice_initp('h0c)), \ + .INITP_0D(slice_initp('h0d)), \ + .INITP_0E(slice_initp('h0e)), \ + .INITP_0F(slice_initp('h0f)), + +`define MAKE_DO(do, dop, rdata) \ + wire [63:0] do; \ + wire [7:0] dop; \ + assign rdata = { \ + dop[7], \ + do[63:56], \ + dop[6], \ + do[55:48], \ + dop[5], \ + do[47:40], \ + dop[4], \ + do[39:32], \ + dop[3], \ + do[31:24], \ + dop[2], \ + do[23:16], \ + dop[1], \ + do[15:8], \ + dop[0], \ + do[7:0] \ + }; + +`define MAKE_DI(di, dip, wdata) \ + wire [63:0] di; \ + wire [7:0] dip; \ + assign { \ + dip[7], \ + di[63:56], \ + dip[6], \ + di[55:48], \ + dip[5], \ + di[47:40], \ + dip[4], \ + di[39:32], \ + dip[3], \ + di[31:24], \ + dip[2], \ + di[23:16], \ + dip[1], \ + di[15:8], \ + dip[0], \ + di[7:0] \ + } = wdata; + +function [71:0] ival; + input integer width; + input [71:0] val; + if (width == 72) + ival = { + val[71], + val[62], + val[53], + val[44], + val[35], + val[26], + val[17], + val[8], + val[70:63], + val[61:54], + val[52:45], + val[43:36], + val[34:27], + val[25:18], + val[16:9], + val[7:0] + }; + else if (width == 36) + ival = { + val[35], + val[26], + val[17], + val[8], + val[34:27], + val[25:18], + val[16:9], + val[7:0] + }; + else if (width == 18) + ival = { + val[17], + val[8], + val[16:9], + val[7:0] + }; + else + ival = val; +endfunction + +function [255:0] slice_init; + input integer idx; + integer i; + for (i = 0; i < 32; i = i + 1) + slice_init[i*8+:8] = INIT[(idx * 32 + i)*9+:8]; +endfunction + +function [255:0] slice_initp; + input integer idx; + integer i; + for (i = 0; i < 256; i = i + 1) + slice_initp[i] = INIT[(idx * 256 + i)*9+8]; +endfunction diff --git a/techlibs/analogdevices/brams_map.v b/techlibs/analogdevices/brams_map.v new file mode 100644 index 000000000..f4655a220 --- /dev/null +++ b/techlibs/analogdevices/brams_map.v @@ -0,0 +1,284 @@ +module $__ANALOGDEVICES_BLOCKRAM_TDP_ (...); + +parameter INIT = 0; +parameter OPTION_MODE = "FULL"; +parameter OPTION_HAS_RDFIRST = 0; + +parameter PORT_A_RD_WIDTH = 1; +parameter PORT_A_WR_WIDTH = 1; +parameter PORT_A_WR_EN_WIDTH = 1; +parameter PORT_A_RD_USED = 1; +parameter PORT_A_WR_USED = 1; +parameter PORT_A_OPTION_WRITE_MODE = "NO_CHANGE"; +parameter PORT_A_RD_INIT_VALUE = 0; +parameter PORT_A_RD_SRST_VALUE = 1; + +parameter PORT_B_RD_WIDTH = 1; +parameter PORT_B_WR_WIDTH = 1; +parameter PORT_B_WR_EN_WIDTH = 1; +parameter PORT_B_RD_USED = 0; +parameter PORT_B_WR_USED = 0; +parameter PORT_B_OPTION_WRITE_MODE = "NO_CHANGE"; +parameter PORT_B_RD_INIT_VALUE = 0; +parameter PORT_B_RD_SRST_VALUE = 0; + +input CLK_C; + +input PORT_A_CLK; +input PORT_A_CLK_EN; +input [15:0] PORT_A_ADDR; +input [PORT_A_WR_WIDTH-1:0] PORT_A_WR_DATA; +input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN; +output [PORT_A_RD_WIDTH-1:0] PORT_A_RD_DATA; +input PORT_A_RD_SRST; + +input PORT_B_CLK; +input PORT_B_CLK_EN; +input [15:0] PORT_B_ADDR; +input [PORT_B_WR_WIDTH-1:0] PORT_B_WR_DATA; +input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN; +output [PORT_B_RD_WIDTH-1:0] PORT_B_RD_DATA; +input PORT_B_RD_SRST; + +`include "brams_defs.vh" + +`define PARAMS_COMMON \ + .WRITE_MODE_A(PORT_A_OPTION_WRITE_MODE), \ + .WRITE_MODE_B(PORT_B_OPTION_WRITE_MODE), \ + .READ_WIDTH_A(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0), \ + .READ_WIDTH_B(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0), \ + .WRITE_WIDTH_A(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0), \ + .WRITE_WIDTH_B(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0), \ + .DOA_REG(0), \ + .DOB_REG(0), \ + .INIT_A(ival(PORT_A_RD_WIDTH, PORT_A_RD_INIT_VALUE)), \ + .INIT_B(ival(PORT_B_RD_WIDTH, PORT_B_RD_INIT_VALUE)), \ + .SRVAL_A(ival(PORT_A_RD_WIDTH, PORT_A_RD_SRST_VALUE)), \ + .SRVAL_B(ival(PORT_B_RD_WIDTH, PORT_B_RD_SRST_VALUE)), \ + .RAM_MODE("TDP"), + +`define PORTS_COMMON \ + .DOADO(DO_A), \ + .DOPADOP(DOP_A), \ + .DIADI(DI_A), \ + .DIPADIP(DIP_A), \ + .DOBDO(DO_B), \ + .DOPBDOP(DOP_B), \ + .DIBDI(DI_B), \ + .DIPBDIP(DIP_B), \ + .CLKARDCLK(PORT_A_CLK), \ + .CLKBWRCLK(PORT_B_CLK), \ + .ENARDEN(PORT_A_CLK_EN), \ + .ENBWREN(PORT_B_CLK_EN), \ + .REGCEAREGCE(1'b0), \ + .REGCEB(1'b0), \ + .RSTRAMARSTRAM(PORT_A_RD_SRST), \ + .RSTRAMB(PORT_B_RD_SRST), \ + .RSTREGARSTREG(1'b0), \ + .RSTREGB(1'b0), \ + .WEA(WE_A), \ + .WEBWE(WE_B), + +`MAKE_DI(DI_A, DIP_A, PORT_A_WR_DATA) +`MAKE_DI(DI_B, DIP_B, PORT_B_WR_DATA) +`MAKE_DO(DO_A, DOP_A, PORT_A_RD_DATA) +`MAKE_DO(DO_B, DOP_B, PORT_B_RD_DATA) + +wire [3:0] WE_A = {4{PORT_A_WR_EN}}; +wire [3:0] WE_B = {4{PORT_B_WR_EN}}; + +generate + +if (OPTION_MODE == "HALF") begin + RAMB18E1 #( + `PARAMS_INIT_18 + `PARAMS_INITP_18 + `PARAMS_COMMON + ) _TECHMAP_REPLACE_ ( + `PORTS_COMMON + .ADDRARDADDR(PORT_A_ADDR[13:0]), + .ADDRBWRADDR(PORT_B_ADDR[13:0]), + ); +end else if (OPTION_MODE == "FULL") begin + RAMB36E1 #( + `PARAMS_INIT_36 + `PARAMS_INITP_36 + `PARAMS_COMMON + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + ) _TECHMAP_REPLACE_ ( + `PORTS_COMMON + .ADDRARDADDR({1'b1, PORT_A_ADDR[14:0]}), + .ADDRBWRADDR({1'b1, PORT_B_ADDR[14:0]}), + ); +end else begin + wire CAS_A, CAS_B; + RAMB36E1 #( + `PARAMS_INIT_36 + `PARAMS_COMMON + .RAM_EXTENSION_A("LOWER"), + .RAM_EXTENSION_B("LOWER"), + ) lower ( + .DIADI(DI_A), + .DIBDI(DI_B), + .CLKARDCLK(PORT_A_CLK), + .CLKBWRCLK(PORT_B_CLK), + .ENARDEN(PORT_A_CLK_EN), + .ENBWREN(PORT_B_CLK_EN), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(PORT_A_RD_SRST), + .RSTRAMB(PORT_B_RD_SRST), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .WEA(WE_A), + .WEBWE(WE_B), + .ADDRARDADDR(PORT_A_ADDR), + .ADDRBWRADDR(PORT_B_ADDR), + .CASCADEOUTA(CAS_A), + .CASCADEOUTB(CAS_B), + ); + RAMB36E1 #( + `PARAMS_INIT_36_U + `PARAMS_COMMON + .RAM_EXTENSION_A("UPPER"), + .RAM_EXTENSION_B("UPPER"), + ) upper ( + .DOADO(DO_A), + .DIADI(DI_A), + .DOBDO(DO_B), + .DIBDI(DI_B), + .CLKARDCLK(PORT_A_CLK), + .CLKBWRCLK(PORT_B_CLK), + .ENARDEN(PORT_A_CLK_EN), + .ENBWREN(PORT_B_CLK_EN), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(PORT_A_RD_SRST), + .RSTRAMB(PORT_B_RD_SRST), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .WEA(WE_A), + .WEBWE(WE_B), + .ADDRARDADDR(PORT_A_ADDR), + .ADDRBWRADDR(PORT_B_ADDR), + .CASCADEINA(CAS_A), + .CASCADEINB(CAS_B), + ); +end + +endgenerate + +endmodule + + +module $__ANALOGDEVICES_BLOCKRAM_SDP_ (...); + +parameter INIT = 0; +parameter OPTION_MODE = "FULL"; +parameter OPTION_WRITE_MODE = "READ_FIRST"; + +parameter PORT_W_WIDTH = 1; +parameter PORT_W_WR_EN_WIDTH = 1; +parameter PORT_W_USED = 1; + +parameter PORT_R_WIDTH = 1; +parameter PORT_R_USED = 0; +parameter PORT_R_RD_INIT_VALUE = 0; +parameter PORT_R_RD_SRST_VALUE = 0; + +input CLK_C; + +input PORT_W_CLK; +input PORT_W_CLK_EN; +input [15:0] PORT_W_ADDR; +input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA; +input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN; + +input PORT_R_CLK; +input PORT_R_CLK_EN; +input [15:0] PORT_R_ADDR; +output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA; +input PORT_R_RD_SRST; + +`include "brams_defs.vh" + +`define PARAMS_COMMON \ + .WRITE_MODE_A(OPTION_WRITE_MODE), \ + .WRITE_MODE_B(OPTION_WRITE_MODE), \ + .READ_WIDTH_A(PORT_R_USED ? PORT_R_WIDTH : 0), \ + .READ_WIDTH_B(0), \ + .WRITE_WIDTH_A(0), \ + .WRITE_WIDTH_B(PORT_W_USED ? PORT_W_WIDTH : 0), \ + .DOA_REG(0), \ + .DOB_REG(0), \ + .RAM_MODE("SDP"), + +`define PORTS_COMMON \ + .CLKBWRCLK(PORT_W_CLK), \ + .CLKARDCLK(PORT_R_CLK), \ + .ENBWREN(PORT_W_CLK_EN), \ + .ENARDEN(PORT_R_CLK_EN), \ + .REGCEAREGCE(1'b0), \ + .REGCEB(1'b0), \ + .RSTRAMARSTRAM(PORT_R_RD_SRST), \ + .RSTRAMB(1'b0), \ + .RSTREGARSTREG(1'b0), \ + .RSTREGB(1'b0), \ + .WEA(0), \ + .WEBWE(PORT_W_WR_EN), + +`MAKE_DI(DI, DIP, PORT_W_WR_DATA) +`MAKE_DO(DO, DOP, PORT_R_RD_DATA) + +generate + +if (OPTION_MODE == "HALF") begin + RAMB18E1 #( + `PARAMS_INIT_18 + `PARAMS_INITP_18 + `PARAMS_COMMON + .INIT_A(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_INIT_VALUE[17:0]) : ival(PORT_R_WIDTH, PORT_R_RD_INIT_VALUE)), + .INIT_B(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_INIT_VALUE[35:18]) : 0), + .SRVAL_A(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_SRST_VALUE[17:0]) : ival(PORT_R_WIDTH, PORT_R_RD_SRST_VALUE)), + .SRVAL_B(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_SRST_VALUE[35:18]) : 0), + ) _TECHMAP_REPLACE_ ( + `PORTS_COMMON + .ADDRARDADDR(PORT_R_ADDR[13:0]), + .ADDRBWRADDR(PORT_W_ADDR[13:0]), + .DOADO(DO[15:0]), + .DOBDO(DO[31:16]), + .DOPADOP(DOP[1:0]), + .DOPBDOP(DOP[3:2]), + .DIADI(DI[15:0]), + .DIBDI(PORT_W_WIDTH == 36 ? DI[31:16] : DI[15:0]), + .DIPADIP(DIP[1:0]), + .DIPBDIP(PORT_W_WIDTH == 36 ? DIP[3:2] : DIP[1:0]), + ); +end else if (OPTION_MODE == "FULL") begin + RAMB36E1 #( + `PARAMS_INIT_36 + `PARAMS_INITP_36 + `PARAMS_COMMON + .INIT_A(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_INIT_VALUE[35:0]) : ival(PORT_R_WIDTH, PORT_R_RD_INIT_VALUE)), + .INIT_B(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_INIT_VALUE[71:36]) : 0), + .SRVAL_A(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_SRST_VALUE[35:0]) : ival(PORT_R_WIDTH, PORT_R_RD_SRST_VALUE)), + .SRVAL_B(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_SRST_VALUE[71:36]) : 0), + ) _TECHMAP_REPLACE_ ( + `PORTS_COMMON + .ADDRARDADDR({1'b1, PORT_R_ADDR}), + .ADDRBWRADDR({1'b1, PORT_W_ADDR}), + .DOADO(DO[31:0]), + .DOBDO(DO[63:32]), + .DOPADOP(DOP[3:0]), + .DOPBDOP(DOP[7:4]), + .DIADI(DI[31:0]), + .DIBDI(PORT_W_WIDTH == 72 ? DI[63:32] : DI[31:0]), + .DIPADIP(DIP[3:0]), + .DIPBDIP(PORT_W_WIDTH == 71 ? DIP[7:4] : DIP[3:0]), + ); +end + +endgenerate + +endmodule diff --git a/techlibs/analogdevices/cells_map.v b/techlibs/analogdevices/cells_map.v new file mode 100644 index 000000000..eb28e6e4b --- /dev/null +++ b/techlibs/analogdevices/cells_map.v @@ -0,0 +1,364 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * 2019 Eddie Hung + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +module \$__SHREG_ (input C, input D, input E, output Q); + parameter DEPTH = 0; + parameter [DEPTH-1:0] INIT = 0; + parameter CLKPOL = 1; + parameter ENPOL = 2; + + \$__ANALOGDEVICES_SHREG_ #(.DEPTH(DEPTH), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(DEPTH-1), .E(E), .Q(Q)); +endmodule + +module \$__ANALOGDEVICES_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO); + parameter DEPTH = 0; + parameter [DEPTH-1:0] INIT = 0; + parameter CLKPOL = 1; + parameter ENPOL = 2; + + // shregmap's INIT parameter shifts out LSB first; + // however Analog Devices expects MSB first + function [DEPTH-1:0] brev; + input [DEPTH-1:0] din; + integer i; + begin + for (i = 0; i < DEPTH; i=i+1) + brev[i] = din[DEPTH-1-i]; + end + endfunction + localparam [DEPTH-1:0] INIT_R = brev(INIT); + + parameter _TECHMAP_CONSTMSK_L_ = 0; + + wire CE; + generate + if (ENPOL == 0) + assign CE = ~E; + else if (ENPOL == 1) + assign CE = E; + else + assign CE = 1'b1; + if (DEPTH == 1) begin + if (CLKPOL) + FDRE #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0)); + else + FDRE_1 #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0)); + end else + if (DEPTH <= 16) begin + SRL16E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A0(L[0]), .A1(L[1]), .A2(L[2]), .A3(L[3]), .CE(CE), .CLK(C), .D(D), .Q(Q)); + end else + if (DEPTH > 17 && DEPTH <= 32) begin + SRLC32E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(Q)); + end else + if (DEPTH > 33 && DEPTH <= 64) begin + wire T0, T1, T2; + SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1)); + \$__ANALOGDEVICES_SHREG_ #(.DEPTH(DEPTH-32), .INIT(INIT[DEPTH-32-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L), .E(E), .Q(T2)); + if (&_TECHMAP_CONSTMSK_L_) + assign Q = T2; + else + LUTMUX7 fpga_mux_0 (.O(Q), .I0(T0), .I1(T2), .S(L[5])); + end else + if (DEPTH > 65 && DEPTH <= 96) begin + wire T0, T1, T2, T3, T4, T5, T6; + SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1)); + SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3)); + \$__ANALOGDEVICES_SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4)); + if (&_TECHMAP_CONSTMSK_L_) + assign Q = T4; + else + \$__ANALOGDEVICES_LUTMUX78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(1'bx), .S0(L[5]), .S1(L[6]), .O(Q)); + end else + if (DEPTH > 97 && DEPTH < 128) begin + wire T0, T1, T2, T3, T4, T5, T6, T7, T8; + SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1)); + SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3)); + SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5)); + \$__ANALOGDEVICES_SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6)); + if (&_TECHMAP_CONSTMSK_L_) + assign Q = T6; + else + \$__ANALOGDEVICES_LUTMUX78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S0(L[5]), .S1(L[6]), .O(Q)); + end + else if (DEPTH == 128) begin + wire T0, T1, T2, T3, T4, T5, T6; + SRLC32E #(.INIT(INIT_R[ 32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1)); + SRLC32E #(.INIT(INIT_R[ 64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3)); + SRLC32E #(.INIT(INIT_R[ 96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5)); + SRLC32E #(.INIT(INIT_R[128-1:96]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_3 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T5), .Q(T6), .Q31(SO)); + if (&_TECHMAP_CONSTMSK_L_) + assign Q = T6; + else + \$__ANALOGDEVICES_LUTMUX78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S0(L[5]), .S1(L[6]), .O(Q)); + end + // For fixed length, if just 1 over a convenient value, decompose + else if (DEPTH <= 129 && &_TECHMAP_CONSTMSK_L_) begin + wire T; + \$__ANALOGDEVICES_SHREG_ #(.DEPTH(DEPTH-1), .INIT(INIT[DEPTH-1:1]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl (.C(C), .D(D), .L({32{1'b1}}), .E(E), .Q(T)); + \$__ANALOGDEVICES_SHREG_ #(.DEPTH(1), .INIT(INIT[0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_last (.C(C), .D(T), .L(L), .E(E), .Q(Q)); + end + // For variable length, if just 1 over a convenient value, then bump up one more + else if (DEPTH < 129 && ~&_TECHMAP_CONSTMSK_L_) + \$__ANALOGDEVICES_SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q)); + else begin + localparam depth0 = 128; + localparam num_srl128 = DEPTH / depth0; + localparam depthN = DEPTH % depth0; + wire [num_srl128 + (depthN > 0 ? 1 : 0) - 1:0] T; + wire [num_srl128 + (depthN > 0 ? 1 : 0) :0] S; + assign S[0] = D; + genvar i; + for (i = 0; i < num_srl128; i++) + \$__ANALOGDEVICES_SHREG_ #(.DEPTH(depth0), .INIT(INIT[DEPTH-1-i*depth0-:depth0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl (.C(C), .D(S[i]), .L(L[$clog2(depth0)-1:0]), .E(E), .Q(T[i]), .SO(S[i+1])); + + if (depthN > 0) + \$__ANALOGDEVICES_SHREG_ #(.DEPTH(depthN), .INIT(INIT[depthN-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_last (.C(C), .D(S[num_srl128]), .L(L[$clog2(depth0)-1:0]), .E(E), .Q(T[num_srl128])); + + if (&_TECHMAP_CONSTMSK_L_) + assign Q = T[num_srl128 + (depthN > 0 ? 1 : 0) - 1]; + else + assign Q = T[L[DEPTH-1:$clog2(depth0)]]; + end + endgenerate +endmodule + +`ifdef MIN_MUX_INPUTS +module \$__ANALOGDEVICES_SHIFTX (A, B, Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + (* force_downto *) + input [A_WIDTH-1:0] A; + (* force_downto *) + input [B_WIDTH-1:0] B; + (* force_downto *) + output [Y_WIDTH-1:0] Y; + + parameter [A_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0; + parameter [A_WIDTH-1:0] _TECHMAP_CONSTVAL_A_ = 0; + parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0; + parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0; + + function integer A_WIDTH_trimmed; + input integer start; + begin + A_WIDTH_trimmed = start; + while (A_WIDTH_trimmed > 0 && _TECHMAP_CONSTMSK_A_[A_WIDTH_trimmed-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH_trimmed-1] === 1'bx) + A_WIDTH_trimmed = A_WIDTH_trimmed - 1; + end + endfunction + + generate + genvar i, j; + // Bit-blast + if (Y_WIDTH > 1) begin + for (i = 0; i < Y_WIDTH; i++) + \$__ANALOGDEVICES_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i])); + end + // If the LSB of B is constant zero (and Y_WIDTH is 1) then + // we can optimise by removing every other entry from A + // and popping the constant zero from B + else if (_TECHMAP_CONSTMSK_B_[0] && !_TECHMAP_CONSTVAL_B_[0]) begin + wire [(A_WIDTH+1)/2-1:0] A_i; + for (i = 0; i < (A_WIDTH+1)/2; i++) + assign A_i[i] = A[i*2]; + \$__ANALOGDEVICES_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y)); + end + // Trim off any leading 1'bx -es in A + else if (_TECHMAP_CONSTMSK_A_[A_WIDTH-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH-1] === 1'bx) begin + localparam A_WIDTH_new = A_WIDTH_trimmed(A_WIDTH-1); + if (A_WIDTH_new == 0) + assign Y = 1'bx; + else + \$__ANALOGDEVICES_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B), .Y(Y)); + end + else if (A_WIDTH < `MIN_MUX_INPUTS) begin + wire _TECHMAP_FAIL_ = 1; + end + else if (A_WIDTH == 2) begin + LUTMUX7 fpga_hard_mux (.I0(A[0]), .I1(A[1]), .S(B[0]), .O(Y)); + end + else if (A_WIDTH <= 4) begin + wire [4-1:0] Ax; + if (A_WIDTH == 4) + assign Ax = A; + else + // Rather than extend with 1'bx which gets flattened to 1'b0 + // causing the "don't care" status to get lost, extend with + // the same driver of F7B.I0 so that we can optimise F7B away + // later + assign Ax = {A[1], A}; + \$__ANALOGDEVICES_LUTMUX78 fpga_hard_mux (.I0(Ax[0]), .I1(Ax[2]), .I2(Ax[1]), .I3(Ax[3]), .S0(B[1]), .S1(B[0]), .O(Y)); + end + // Note that the following decompositions are 'backwards' in that + // the LSBs are placed on the hard resources, and the soft resources + // are used for MSBs. + // This has the effect of more effectively utilising the hard mux; + // take for example a 5:1 multiplexer, currently this would map as: + // + // A[0] \___ __ A[0] \__ __ + // A[4] / \| \ whereas the more A[1] / \| \ + // A[1] _____| | obvious mapping A[2] \___| | + // A[2] _____| |-- of MSBs to hard A[3] / | |__ + // A[3]______| | resources would A[4] ____| | + // |__/ lead to: 1'bx ____| | + // || |__/ + // || || + // B[1:0] B[1:2] + // + // Expectation would be that the 'forward' mapping (right) is more + // area efficient (consider a 9:1 multiplexer using 2x4:1 multiplexers + // on its I0 and I1 inputs, and A[8] and 1'bx on its I2 and I3 inputs) + // but that the 'backwards' mapping (left) is more delay efficient + // since smaller LUTs are faster than wider ones. + else if (A_WIDTH <= 8) begin + wire [8-1:0] Ax = {{{8-A_WIDTH}{1'bx}}, A}; + wire T0 = B[2] ? Ax[4] : Ax[0]; + wire T1 = B[2] ? Ax[5] : Ax[1]; + wire T2 = B[2] ? Ax[6] : Ax[2]; + wire T3 = B[2] ? Ax[7] : Ax[3]; + \$__ANALOGDEVICES_LUTMUX78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T1), .I3(T3), .S0(B[1]), .S1(B[0]), .O(Y)); + end + else if (A_WIDTH <= 16) begin + wire [16-1:0] Ax = {{{16-A_WIDTH}{1'bx}}, A}; + wire T0 = B[2] ? B[3] ? Ax[12] : Ax[4] + : B[3] ? Ax[ 8] : Ax[0]; + wire T1 = B[2] ? B[3] ? Ax[13] : Ax[5] + : B[3] ? Ax[ 9] : Ax[1]; + wire T2 = B[2] ? B[3] ? Ax[14] : Ax[6] + : B[3] ? Ax[10] : Ax[2]; + wire T3 = B[2] ? B[3] ? Ax[15] : Ax[7] + : B[3] ? Ax[11] : Ax[3]; + \$__ANALOGDEVICES_LUTMUX78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T1), .I3(T3), .S0(B[1]), .S1(B[0]), .O(Y)); + end + else begin + localparam num_mux16 = (A_WIDTH+15) / 16; + localparam clog2_num_mux16 = $clog2(num_mux16); + wire [num_mux16-1:0] T; + wire [num_mux16*16-1:0] Ax = {{(num_mux16*16-A_WIDTH){1'bx}}, A}; + for (i = 0; i < num_mux16; i++) + \$__ANALOGDEVICES_SHIFTX #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(16), + .B_WIDTH(4), + .Y_WIDTH(Y_WIDTH) + ) fpga_mux ( + .A(Ax[i*16+:16]), + .B(B[3:0]), + .Y(T[i]) + ); + \$__ANALOGDEVICES_SHIFTX #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(num_mux16), + .B_WIDTH(clog2_num_mux16), + .Y_WIDTH(Y_WIDTH) + ) _TECHMAP_REPLACE_ ( + .A(T), + .B(B[B_WIDTH-1-:clog2_num_mux16]), + .Y(Y)); + end + endgenerate +endmodule + +(* techmap_celltype = "$__ANALOGDEVICES_SHIFTX" *) +module _90__ANALOGDEVICES_SHIFTX (A, B, Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + (* force_downto *) + input [A_WIDTH-1:0] A; + (* force_downto *) + input [B_WIDTH-1:0] B; + (* force_downto *) + output [Y_WIDTH-1:0] Y; + + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y)); +endmodule + +module \$_MUX_ (A, B, S, Y); + input A, B, S; + output Y; + generate + if (`MIN_MUX_INPUTS == 2) + \$__ANALOGDEVICES_SHIFTX #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(2), .B_WIDTH(1), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({B,A}), .B(S), .Y(Y)); + else + wire _TECHMAP_FAIL_ = 1; + endgenerate +endmodule + +module \$_MUX4_ (A, B, C, D, S, T, Y); + input A, B, C, D, S, T; + output Y; + \$__ANALOGDEVICES_SHIFTX #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({D,C,B,A}), .B({T,S}), .Y(Y)); +endmodule + +module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y); + input A, B, C, D, E, F, G, H, S, T, U; + output Y; + \$__ANALOGDEVICES_SHIFTX #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({H,G,F,E,D,C,B,A}), .B({U,T,S}), .Y(Y)); +endmodule + +module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y); + input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V; + output Y; + \$__ANALOGDEVICES_SHIFTX #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y)); +endmodule +`endif + +module \$__ANALOGDEVICES_LUTMUX78 (O, I0, I1, I2, I3, S0, S1); + output O; + input I0, I1, I2, I3, S0, S1; + wire T0, T1; + parameter _TECHMAP_BITS_CONNMAP_ = 0; + parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I0_ = 0; + parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I1_ = 0; + parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I2_ = 0; + parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I3_ = 0; + parameter _TECHMAP_CONSTMSK_S0_ = 0; + parameter _TECHMAP_CONSTVAL_S0_ = 0; + parameter _TECHMAP_CONSTMSK_S1_ = 0; + parameter _TECHMAP_CONSTVAL_S1_ = 0; + if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1) + assign T0 = I1; + else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_) + assign T0 = I0; + else + LUTMUX7 mux7a (.I0(I0), .I1(I1), .S(S0), .O(T0)); + if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1) + assign T1 = I3; + else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_) + assign T1 = I2; + else + LUTMUX7 mux7b (.I0(I2), .I1(I3), .S(S0), .O(T1)); + if (_TECHMAP_CONSTMSK_S1_ && _TECHMAP_CONSTVAL_S1_ === 1'b1) + assign O = T1; + else if (_TECHMAP_CONSTMSK_S1_ || (_TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_ && _TECHMAP_CONNMAP_I1_ === _TECHMAP_CONNMAP_I2_ && _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)) + assign O = T0; + else + LUTMUX8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O)); +endmodule diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v new file mode 100644 index 000000000..05a320986 --- /dev/null +++ b/techlibs/analogdevices/cells_sim.v @@ -0,0 +1,4377 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +// See Analog Devices UG953 and UG474 for a description of the cell types below. +// http://www.analogdevices.com/support/documentation/user_guides/ug474_7Series_CLB.pdf +// http://www.analogdevices.com/support/documentation/sw_manuals/analogdevices2014_4/ug953-vivado-7series-libraries.pdf + +module VDD(output P); + assign P = 1; +endmodule + +module GND(output G); + assign G = 0; +endmodule + +module INBUF( + output O, + (* iopad_external_pin *) + input I); + parameter CCIO_EN = "TRUE"; + parameter CAPACITANCE = "DONT_CARE"; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IFD_DELAY_VALUE = "AUTO"; + parameter IOSTANDARD = "DEFAULT"; + assign O = I; + specify + (I => O) = 0; + endspecify +endmodule + +module IBUFG( + output O, + (* iopad_external_pin *) + input I); + parameter CAPACITANCE = "DONT_CARE"; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + assign O = I; +endmodule + +module OUTBUF( + (* iopad_external_pin *) + output O, + input I); + parameter CAPACITANCE = "DONT_CARE"; + parameter IOSTANDARD = "DEFAULT"; + parameter DRIVE = 12; + parameter SLEW = "SLOW"; + assign O = I; + specify + (I => O) = 0; + endspecify +endmodule + +module IOBUF ( + (* iopad_external_pin *) + inout IO, + output O, + input I, + input T +); + parameter integer DRIVE = 12; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + assign IO = T ? 1'bz : I; + assign O = IO; + specify + (I => IO) = 0; + (IO => O) = 0; + endspecify +endmodule + +module OBUFT ( + (* iopad_external_pin *) + output O, + input I, + input T +); + parameter CAPACITANCE = "DONT_CARE"; + parameter integer DRIVE = 12; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + assign O = T ? 1'bz : I; + specify + (I => O) = 0; + endspecify +endmodule + +module BUFG( + (* clkbuf_driver *) + output O, + input I); + assign O = I; + specify + // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/CLK_BUFG_TOP_R.sdf#L11 + (I => O) = 96; + endspecify +endmodule + +module BUFGCTRL( + (* clkbuf_driver *) + output O, + input I0, input I1, + (* invertible_pin = "IS_S0_INVERTED" *) + input S0, + (* invertible_pin = "IS_S1_INVERTED" *) + input S1, + (* invertible_pin = "IS_CE0_INVERTED" *) + input CE0, + (* invertible_pin = "IS_CE1_INVERTED" *) + input CE1, + (* invertible_pin = "IS_IGNORE0_INVERTED" *) + input IGNORE0, + (* invertible_pin = "IS_IGNORE1_INVERTED" *) + input IGNORE1); + +parameter [0:0] INIT_OUT = 1'b0; +parameter PRESELECT_I0 = "FALSE"; +parameter PRESELECT_I1 = "FALSE"; +parameter [0:0] IS_CE0_INVERTED = 1'b0; +parameter [0:0] IS_CE1_INVERTED = 1'b0; +parameter [0:0] IS_S0_INVERTED = 1'b0; +parameter [0:0] IS_S1_INVERTED = 1'b0; +parameter [0:0] IS_IGNORE0_INVERTED = 1'b0; +parameter [0:0] IS_IGNORE1_INVERTED = 1'b0; + +wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT); +wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT); +wire S0_true = (S0 ^ IS_S0_INVERTED); +wire S1_true = (S1 ^ IS_S1_INVERTED); + +assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT); + +endmodule + +module BUFHCE( + (* clkbuf_driver *) + output O, + input I, + (* invertible_pin = "IS_CE_INVERTED" *) + input CE); + +parameter [0:0] INIT_OUT = 1'b0; +parameter CE_TYPE = "SYNC"; +parameter [0:0] IS_CE_INVERTED = 1'b0; + +assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT); + +endmodule + +// module OBUFT(output O, input I, T); +// assign O = T ? 1'bz : I; +// endmodule + +// module IOBUF(inout IO, output O, input I, T); +// assign O = IO, IO = T ? 1'bz : I; +// endmodule + +module INV( + (* clkbuf_inv = "I" *) + output O, + input I +); + assign O = !I; + specify + (I => O) = 127; + endspecify +endmodule + +(* abc9_lut=1 *) +module LUT1(output O, input I0); + parameter [1:0] INIT = 0; + assign O = I0 ? INIT[1] : INIT[0]; + specify + (I0 => O) = 127; + endspecify +endmodule + +(* abc9_lut=2 *) +module LUT2(output O, input I0, I1); + parameter [3:0] INIT = 0; + wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 238; + (I1 => O) = 127; + endspecify +endmodule + +(* abc9_lut=3 *) +module LUT3(output O, input I0, I1, I2); + parameter [7:0] INIT = 0; + wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 407; + (I1 => O) = 238; + (I2 => O) = 127; + endspecify +endmodule + +(* abc9_lut=3 *) +module LUT4(output O, input I0, I1, I2, I3); + parameter [15:0] INIT = 0; + wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 472; + (I1 => O) = 407; + (I2 => O) = 238; + (I3 => O) = 127; + endspecify +endmodule + +(* abc9_lut=3 *) +module LUT5(output O, input I0, I1, I2, I3, I4); + parameter [31:0] INIT = 0; + wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0]; + wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 631; + (I1 => O) = 472; + (I2 => O) = 407; + (I3 => O) = 238; + (I4 => O) = 127; + endspecify +endmodule + +// This is a placeholder for ABC9 to extract the area/delay +// cost of 3-input LUTs and is not intended to be instantiated + +(* abc9_lut=5 *) +module LUT6(output O, input I0, I1, I2, I3, I4, I5); + parameter [63:0] INIT = 0; + wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0]; + wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0]; + wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 642; + (I1 => O) = 631; + (I2 => O) = 472; + (I3 => O) = 407; + (I4 => O) = 238; + (I5 => O) = 127; + endspecify +endmodule + +module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5); + parameter [63:0] INIT = 0; + wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0]; + wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0]; + wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O6 = I0 ? s1[1] : s1[0]; + + wire [15: 0] s5_4 = I4 ? INIT[31:16] : INIT[15: 0]; + wire [ 7: 0] s5_3 = I3 ? s5_4[15: 8] : s5_4[ 7: 0]; + wire [ 3: 0] s5_2 = I2 ? s5_3[ 7: 4] : s5_3[ 3: 0]; + wire [ 1: 0] s5_1 = I1 ? s5_2[ 3: 2] : s5_2[ 1: 0]; + assign O5 = I0 ? s5_1[1] : s5_1[0]; +endmodule + +// This is a placeholder for ABC9 to extract the area/delay +// cost of 3-input LUTs and is not intended to be instantiated +(* abc9_lut=10 *) +module \$__ABC9_LUT7 (output O, input I0, I1, I2, I3, I4, I5, I6); +`ifndef __ICARUS__ + specify + // https://github.com/SymbiFlow/prjxray-db/blob/1c85daf1b115da4d27ca83c6b89f53a94de39748/artix7/timings/slicel.sdf#L867 + (I0 => O) = 642 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; + (I1 => O) = 631 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; + (I2 => O) = 472 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; + (I3 => O) = 407 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; + (I4 => O) = 238 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; + (I5 => O) = 127 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; + (I6 => O) = 0 + 296 /* to select F7BMUX */ + 174 /* CMUX */; + endspecify +`endif +endmodule + +// This is a placeholder for ABC9 to extract the area/delay +// cost of 3-input LUTs and is not intended to be instantiated +(* abc9_lut=20 *) +module \$__ABC9_LUT8 (output O, input I0, I1, I2, I3, I4, I5, I6, I7); +`ifndef __ICARUS__ + specify + // https://github.com/SymbiFlow/prjxray-db/blob/1c85daf1b115da4d27ca83c6b89f53a94de39748/artix7/timings/slicel.sdf#L716 + (I0 => O) = 642 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */; + (I1 => O) = 631 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */; + (I2 => O) = 472 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */; + (I3 => O) = 407 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */; + (I4 => O) = 238 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */; + (I5 => O) = 127 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */; + (I6 => O) = 0 + 296 /* to select F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */; + (I7 => O) = 0 + 0 + 273 /* to select F8MUX */ + 192 /* BMUX */; + endspecify +`endif +endmodule + +(* abc9_box, lib_whitebox *) +module LUTMUX7(output O, input I0, I1, S); + assign O = S ? I1 : I0; + specify + // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L451-L453 + (I0 => O) = 217; + (I1 => O) = 223; + (S => O) = 296; + endspecify +endmodule + +(* abc9_box, lib_whitebox *) +module LUTMUX8(output O, input I0, I1, S); + assign O = S ? I1 : I0; + specify + // Max delays from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L462-L464 + (I0 => O) = 104; + (I1 => O) = 94; + (S => O) = 273; + endspecify +endmodule + +(* abc9_box, lib_whitebox *) +module CRY4( + (* abc9_carry *) + output [3:0] CO, + output [3:0] O, + (* abc9_carry *) + input CI, + input CYINIT, + input [3:0] DI, S +); + assign O = S ^ {CO[2:0], CI | CYINIT}; + assign CO[0] = S[0] ? CI | CYINIT : DI[0]; + assign CO[1] = S[1] ? CO[0] : DI[1]; + assign CO[2] = S[2] ? CO[1] : DI[2]; + assign CO[3] = S[3] ? CO[2] : DI[3]; + specify + // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L11-L46 + (CYINIT => O[0]) = 482; + (S[0] => O[0]) = 223; + (CI => O[0]) = 222; + (CYINIT => O[1]) = 598; + (DI[0] => O[1]) = 407; + (S[0] => O[1]) = 400; + (S[1] => O[1]) = 205; + (CI => O[1]) = 334; + (CYINIT => O[2]) = 584; + (DI[0] => O[2]) = 556; + (DI[1] => O[2]) = 537; + (S[0] => O[2]) = 523; + (S[1] => O[2]) = 558; + (S[2] => O[2]) = 226; + (CI => O[2]) = 239; + (CYINIT => O[3]) = 642; + (DI[0] => O[3]) = 615; + (DI[1] => O[3]) = 596; + (DI[2] => O[3]) = 438; + (S[0] => O[3]) = 582; + (S[1] => O[3]) = 618; + (S[2] => O[3]) = 330; + (S[3] => O[3]) = 227; + (CI => O[3]) = 313; + (CYINIT => CO[0]) = 536; + (DI[0] => CO[0]) = 379; + (S[0] => CO[0]) = 340; + (CI => CO[0]) = 271; + (CYINIT => CO[1]) = 494; + (DI[0] => CO[1]) = 465; + (DI[1] => CO[1]) = 445; + (S[0] => CO[1]) = 433; + (S[1] => CO[1]) = 469; + (CI => CO[1]) = 157; + (CYINIT => CO[2]) = 592; + (DI[0] => CO[2]) = 540; + (DI[1] => CO[2]) = 520; + (DI[2] => CO[2]) = 356; + (S[0] => CO[2]) = 512; + (S[1] => CO[2]) = 548; + (S[2] => CO[2]) = 292; + (CI => CO[2]) = 228; + (CYINIT => CO[3]) = 580; + (DI[0] => CO[3]) = 526; + (DI[1] => CO[3]) = 507; + (DI[2] => CO[3]) = 398; + (DI[3] => CO[3]) = 385; + (S[0] => CO[3]) = 508; + (S[1] => CO[3]) = 528; + (S[2] => CO[3]) = 378; + (S[3] => CO[3]) = 380; + (CI => CO[3]) = 114; + endspecify +endmodule + +module CARRY8( + output [7:0] CO, + output [7:0] O, + input CI, + input CI_TOP, + input [7:0] DI, S +); + parameter CARRY_TYPE = "SINGLE_CY8"; + wire CI4 = (CARRY_TYPE == "DUAL_CY4" ? CI_TOP : CO[3]); + assign O = S ^ {CO[6:4], CI4, CO[2:0], CI}; + assign CO[0] = S[0] ? CI : DI[0]; + assign CO[1] = S[1] ? CO[0] : DI[1]; + assign CO[2] = S[2] ? CO[1] : DI[2]; + assign CO[3] = S[3] ? CO[2] : DI[3]; + assign CO[4] = S[4] ? CI4 : DI[4]; + assign CO[5] = S[5] ? CO[4] : DI[5]; + assign CO[6] = S[6] ? CO[5] : DI[6]; + assign CO[7] = S[7] ? CO[6] : DI[7]; +endmodule + +module ORCY (output O, input CI, I); + assign O = CI | I; +endmodule + +module MULT_AND (output LO, input I0, I1); + assign LO = I0 & I1; +endmodule + +// Flip-flops and latches. + +// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250 + +(* abc9_flop, lib_whitebox *) +module FDRE ( + output reg Q, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C, + input CE, + (* invertible_pin = "IS_D_INVERTED" *) + input D, + (* invertible_pin = "IS_R_INVERTED" *) + input R +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_R_INVERTED = 1'b0; + initial Q <= INIT; + generate + case (|IS_C_INVERTED) + 1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; + 1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; + endcase + endgenerate + specify + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 + $setup(D , posedge C &&& CE && !IS_C_INVERTED , /*-46*/ 0); // Negative times not currently supported + $setup(D , negedge C &&& CE && IS_C_INVERTED , /*-46*/ 0); // Negative times not currently supported + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 + $setup(CE, posedge C &&& !IS_C_INVERTED, 109); + $setup(CE, negedge C &&& IS_C_INVERTED, 109); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 + $setup(R , posedge C &&& !IS_C_INVERTED, 404); + $setup(R , negedge C &&& IS_C_INVERTED, 404); + // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243 + if (!IS_C_INVERTED && R != IS_R_INVERTED) (posedge C => (Q : 1'b0)) = 303; + if ( IS_C_INVERTED && R != IS_R_INVERTED) (negedge C => (Q : 1'b0)) = 303; + if (!IS_C_INVERTED && R == IS_R_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303; + if ( IS_C_INVERTED && R == IS_R_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303; + endspecify +endmodule + +(* abc9_flop, lib_whitebox *) +module FDRE_1 ( + output reg Q, + (* clkbuf_sink *) + input C, + input CE, + input D, + input R +); + parameter [0:0] INIT = 1'b0; + initial Q <= INIT; + always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D; + specify + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 + $setup(D , negedge C &&& CE, /*-46*/ 0); // Negative times not currently supported + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 + $setup(CE, negedge C, 109); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 + $setup(R , negedge C, 404); // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243 + if (R) (negedge C => (Q : 1'b0)) = 303; + if (!R && CE) (negedge C => (Q : D)) = 303; + endspecify +endmodule + +(* abc9_flop, lib_whitebox *) +module FDSE ( + output reg Q, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C, + input CE, + (* invertible_pin = "IS_D_INVERTED" *) + input D, + (* invertible_pin = "IS_S_INVERTED" *) + input S +); + parameter [0:0] INIT = 1'b1; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_S_INVERTED = 1'b0; + initial Q <= INIT; + generate + case (|IS_C_INVERTED) + 1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; + 1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; + endcase + endgenerate + specify + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 + $setup(D , posedge C &&& !IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported + $setup(D , negedge C &&& IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 + $setup(CE, posedge C &&& !IS_C_INVERTED, 109); + $setup(CE, negedge C &&& IS_C_INVERTED, 109); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 + $setup(S , posedge C &&& !IS_C_INVERTED, 404); + $setup(S , negedge C &&& IS_C_INVERTED, 404); + // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243 + if (!IS_C_INVERTED && S != IS_S_INVERTED) (posedge C => (Q : 1'b1)) = 303; + if ( IS_C_INVERTED && S != IS_S_INVERTED) (negedge C => (Q : 1'b1)) = 303; + if (!IS_C_INVERTED && S == IS_S_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303; + if ( IS_C_INVERTED && S == IS_S_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303; + endspecify +endmodule + +(* abc9_flop, lib_whitebox *) +module FDSE_1 ( + output reg Q, + (* clkbuf_sink *) + input C, + input CE, + input D, + input S +); + parameter [0:0] INIT = 1'b1; + initial Q <= INIT; + always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D; + specify + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 + $setup(D , negedge C &&& CE, /*-46*/ 0); // Negative times not currently supported + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 + $setup(CE, negedge C, 109); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 + $setup(S , negedge C, 404); + // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243 + if (S) (negedge C => (Q : 1'b1)) = 303; + if (!S && CE) (negedge C => (Q : D)) = 303; + endspecify +endmodule + +module FDRSE ( + output reg Q, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C, + (* invertible_pin = "IS_CE_INVERTED" *) + input CE, + (* invertible_pin = "IS_D_INVERTED" *) + input D, + (* invertible_pin = "IS_R_INVERTED" *) + input R, + (* invertible_pin = "IS_S_INVERTED" *) + input S +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_CE_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_R_INVERTED = 1'b0; + parameter [0:0] IS_S_INVERTED = 1'b0; + initial Q <= INIT; + wire c = C ^ IS_C_INVERTED; + wire ce = CE ^ IS_CE_INVERTED; + wire d = D ^ IS_D_INVERTED; + wire r = R ^ IS_R_INVERTED; + wire s = S ^ IS_S_INVERTED; + always @(posedge c) + if (r) + Q <= 0; + else if (s) + Q <= 1; + else if (ce) + Q <= d; +endmodule + +module FDRSE_1 ( + output reg Q, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C, + (* invertible_pin = "IS_CE_INVERTED" *) + input CE, + (* invertible_pin = "IS_D_INVERTED" *) + input D, + (* invertible_pin = "IS_R_INVERTED" *) + input R, + (* invertible_pin = "IS_S_INVERTED" *) + input S +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_CE_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_R_INVERTED = 1'b0; + parameter [0:0] IS_S_INVERTED = 1'b0; + initial Q <= INIT; + wire c = C ^ IS_C_INVERTED; + wire ce = CE ^ IS_CE_INVERTED; + wire d = D ^ IS_D_INVERTED; + wire r = R ^ IS_R_INVERTED; + wire s = S ^ IS_S_INVERTED; + always @(negedge c) + if (r) + Q <= 0; + else if (s) + Q <= 1; + else if (ce) + Q <= d; +endmodule + +(* abc9_box, lib_whitebox *) +module FDCE ( + output reg Q, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C, + input CE, + (* invertible_pin = "IS_CLR_INVERTED" *) + input CLR, + (* invertible_pin = "IS_D_INVERTED" *) + input D +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_CLR_INVERTED = 1'b0; + initial Q <= INIT; + generate + case ({|IS_C_INVERTED, |IS_CLR_INVERTED}) + 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; + 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; + 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; + 2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; + endcase + endgenerate + specify + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 + $setup(D , posedge C &&& !IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported + $setup(D , negedge C &&& IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 + $setup(CE , posedge C &&& !IS_C_INVERTED, 109); + $setup(CE , negedge C &&& IS_C_INVERTED, 109); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 + $setup(CLR, posedge C &&& !IS_C_INVERTED, 404); + $setup(CLR, negedge C &&& IS_C_INVERTED, 404); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270 +`ifndef YOSYS + if (!IS_CLR_INVERTED) (posedge CLR => (Q : 1'b0)) = 764; + if ( IS_CLR_INVERTED) (negedge CLR => (Q : 1'b0)) = 764; +`else + if (IS_CLR_INVERTED != CLR) (CLR => Q) = 764; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif + if (!IS_C_INVERTED && CLR == IS_CLR_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303; + if ( IS_C_INVERTED && CLR == IS_CLR_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303; + endspecify +endmodule + +(* abc9_box, lib_whitebox *) +module FDCE_1 ( + output reg Q, + (* clkbuf_sink *) + input C, + input CE, + input CLR, + input D +); + parameter [0:0] INIT = 1'b0; + initial Q <= INIT; + always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D; + specify + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 + $setup(D , negedge C &&& CE, /*-46*/ 0); // Negative times not currently supported + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 + $setup(CE , negedge C, 109); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 + $setup(CLR, negedge C, 404); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270 +`ifndef YOSYS + (posedge CLR => (Q : 1'b0)) = 764; +`else + if (CLR) (CLR => Q) = 764; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif + if (!CLR && CE) (negedge C => (Q : D)) = 303; + endspecify +endmodule + +(* abc9_box, lib_whitebox *) +module FDPE ( + output reg Q, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C, + input CE, + (* invertible_pin = "IS_D_INVERTED" *) + input D, + (* invertible_pin = "IS_PRE_INVERTED" *) + input PRE +); + parameter [0:0] INIT = 1'b1; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_PRE_INVERTED = 1'b0; + initial Q <= INIT; + generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED}) + 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; + 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; + 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; + 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; + endcase + endgenerate + specify + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 + $setup(D , posedge C &&& !IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported + $setup(D , negedge C &&& IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 + $setup(CE , posedge C &&& !IS_C_INVERTED, 109); + $setup(CE , negedge C &&& IS_C_INVERTED, 109); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 + $setup(PRE, posedge C &&& !IS_C_INVERTED, 404); + $setup(PRE, negedge C &&& IS_C_INVERTED, 404); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270 +`ifndef YOSYS + if (!IS_PRE_INVERTED) (posedge PRE => (Q : 1'b1)) = 764; + if ( IS_PRE_INVERTED) (negedge PRE => (Q : 1'b1)) = 764; +`else + if (IS_PRE_INVERTED != PRE) (PRE => Q) = 764; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif + if (!IS_C_INVERTED && PRE == IS_PRE_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303; + if ( IS_C_INVERTED && PRE == IS_PRE_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303; + endspecify +endmodule + +(* abc9_box, lib_whitebox *) +module FDPE_1 ( + output reg Q, + (* clkbuf_sink *) + input C, + input CE, + input D, + input PRE +); + parameter [0:0] INIT = 1'b1; + initial Q <= INIT; + always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; + specify + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 + $setup(D , negedge C &&& CE, /*-46*/ 0); // Negative times not currently supported + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 + $setup(CE , negedge C, 109); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 + $setup(PRE, negedge C, 404); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270 +`ifndef YOSYS + (posedge PRE => (Q : 1'b1)) = 764; +`else + if (PRE) (PRE => Q) = 764; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif + if (!PRE && CE) (negedge C => (Q : D)) = 303; + endspecify +endmodule + +module FDCPE ( + output wire Q, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C, + input CE, + (* invertible_pin = "IS_CLR_INVERTED" *) + input CLR, + input D, + (* invertible_pin = "IS_PRE_INVERTED" *) + input PRE +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_CLR_INVERTED = 1'b0; + parameter [0:0] IS_PRE_INVERTED = 1'b0; + wire c = C ^ IS_C_INVERTED; + wire clr = CLR ^ IS_CLR_INVERTED; + wire pre = PRE ^ IS_PRE_INVERTED; + // Hacky model to avoid simulation-synthesis mismatches. + reg qc, qp, qs; + initial qc = INIT; + initial qp = INIT; + initial qs = 0; + always @(posedge c, posedge clr) begin + if (clr) + qc <= 0; + else if (CE) + qc <= D; + end + always @(posedge c, posedge pre) begin + if (pre) + qp <= 1; + else if (CE) + qp <= D; + end + always @* begin + if (clr) + qs <= 0; + else if (pre) + qs <= 1; + end + assign Q = qs ? qp : qc; +endmodule + +module FDCPE_1 ( + output wire Q, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C, + input CE, + (* invertible_pin = "IS_CLR_INVERTED" *) + input CLR, + input D, + (* invertible_pin = "IS_PRE_INVERTED" *) + input PRE +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_CLR_INVERTED = 1'b0; + parameter [0:0] IS_PRE_INVERTED = 1'b0; + wire c = C ^ IS_C_INVERTED; + wire clr = CLR ^ IS_CLR_INVERTED; + wire pre = PRE ^ IS_PRE_INVERTED; + // Hacky model to avoid simulation-synthesis mismatches. + reg qc, qp, qs; + initial qc = INIT; + initial qp = INIT; + initial qs = 0; + always @(negedge c, posedge clr) begin + if (clr) + qc <= 0; + else if (CE) + qc <= D; + end + always @(negedge c, posedge pre) begin + if (pre) + qp <= 1; + else if (CE) + qp <= D; + end + always @* begin + if (clr) + qs <= 0; + else if (pre) + qs <= 1; + end + assign Q = qs ? qp : qc; +endmodule + +module LDCE ( + output reg Q, + (* invertible_pin = "IS_CLR_INVERTED" *) + input CLR, + input D, + (* invertible_pin = "IS_G_INVERTED" *) + input G, + input GE +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_CLR_INVERTED = 1'b0; + parameter [0:0] IS_G_INVERTED = 1'b0; + parameter MSGON = "TRUE"; + parameter XON = "TRUE"; + initial Q = INIT; + wire clr = CLR ^ IS_CLR_INVERTED; + wire g = G ^ IS_G_INVERTED; + always @* + if (clr) Q <= 1'b0; + else if (GE && g) Q <= D; +endmodule + +module LDPE ( + output reg Q, + input D, + (* invertible_pin = "IS_G_INVERTED" *) + input G, + input GE, + (* invertible_pin = "IS_PRE_INVERTED" *) + input PRE +); + parameter [0:0] INIT = 1'b1; + parameter [0:0] IS_G_INVERTED = 1'b0; + parameter [0:0] IS_PRE_INVERTED = 1'b0; + parameter MSGON = "TRUE"; + parameter XON = "TRUE"; + initial Q = INIT; + wire g = G ^ IS_G_INVERTED; + wire pre = PRE ^ IS_PRE_INVERTED; + always @* + if (pre) Q <= 1'b1; + else if (GE && g) Q <= D; +endmodule + +module LDCPE ( + output reg Q, + (* invertible_pin = "IS_CLR_INVERTED" *) + input CLR, + (* invertible_pin = "IS_D_INVERTED" *) + input D, + (* invertible_pin = "IS_G_INVERTED" *) + input G, + (* invertible_pin = "IS_GE_INVERTED" *) + input GE, + (* invertible_pin = "IS_PRE_INVERTED" *) + input PRE +); + parameter [0:0] INIT = 1'b1; + parameter [0:0] IS_CLR_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_G_INVERTED = 1'b0; + parameter [0:0] IS_GE_INVERTED = 1'b0; + parameter [0:0] IS_PRE_INVERTED = 1'b0; + initial Q = INIT; + wire d = D ^ IS_D_INVERTED; + wire g = G ^ IS_G_INVERTED; + wire ge = GE ^ IS_GE_INVERTED; + wire clr = CLR ^ IS_CLR_INVERTED; + wire pre = PRE ^ IS_PRE_INVERTED; + always @* + if (clr) Q <= 1'b0; + else if (pre) Q <= 1'b1; + else if (ge && g) Q <= d; +endmodule + +module AND2B1L ( + output O, + input DI, + (* invertible_pin = "IS_SRI_INVERTED" *) + input SRI +); + parameter [0:0] IS_SRI_INVERTED = 1'b0; + assign O = DI & ~(SRI ^ IS_SRI_INVERTED); +endmodule + +module OR2L ( + output O, + input DI, + (* invertible_pin = "IS_SRI_INVERTED" *) + input SRI +); + parameter [0:0] IS_SRI_INVERTED = 1'b0; + assign O = DI | (SRI ^ IS_SRI_INVERTED); +endmodule + +// LUTRAM. + +// Single port. + +module RAM16X1S ( + output O, + input A0, A1, A2, A3, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [15:0] INIT = 16'h0000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [3:0] a = {A3, A2, A1, A0}; + reg [15:0] mem = INIT; + assign O = mem[a]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) if (WE) mem[a] <= D; +endmodule + +module RAM16X1S_1 ( + output O, + input A0, A1, A2, A3, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [15:0] INIT = 16'h0000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [3:0] a = {A3, A2, A1, A0}; + reg [15:0] mem = INIT; + assign O = mem[a]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(negedge clk) if (WE) mem[a] <= D; +endmodule + +module RAM32X1S ( + output O, + input A0, A1, A2, A3, A4, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [31:0] INIT = 32'h00000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [4:0] a = {A4, A3, A2, A1, A0}; + reg [31:0] mem = INIT; + assign O = mem[a]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) if (WE) mem[a] <= D; +endmodule + +module RAM32X1S_1 ( + output O, + input A0, A1, A2, A3, A4, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [31:0] INIT = 32'h00000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [4:0] a = {A4, A3, A2, A1, A0}; + reg [31:0] mem = INIT; + assign O = mem[a]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(negedge clk) if (WE) mem[a] <= D; +endmodule + +module RAM64X1S ( + output O, + input A0, A1, A2, A3, A4, A5, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [63:0] INIT = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [5:0] a = {A5, A4, A3, A2, A1, A0}; + reg [63:0] mem = INIT; + assign O = mem[a]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) if (WE) mem[a] <= D; +endmodule + +module RAM64X1S_1 ( + output O, + input A0, A1, A2, A3, A4, A5, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [63:0] INIT = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [5:0] a = {A5, A4, A3, A2, A1, A0}; + reg [63:0] mem = INIT; + assign O = mem[a]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(negedge clk) if (WE) mem[a] <= D; +endmodule + +module RAM128X1S ( + output O, + input A0, A1, A2, A3, A4, A5, A6, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [127:0] INIT = 128'h00000000000000000000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [6:0] a = {A6, A5, A4, A3, A2, A1, A0}; + reg [127:0] mem = INIT; + assign O = mem[a]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) if (WE) mem[a] <= D; +endmodule + +module RAM128X1S_1 ( + output O, + input A0, A1, A2, A3, A4, A5, A6, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [127:0] INIT = 128'h00000000000000000000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [6:0] a = {A6, A5, A4, A3, A2, A1, A0}; + reg [127:0] mem = INIT; + assign O = mem[a]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(negedge clk) if (WE) mem[a] <= D; +endmodule + +module RAM256X1S ( + output O, + input [7:0] A, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [255:0] INIT = 256'h0; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + reg [255:0] mem = INIT; + assign O = mem[A]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) if (WE) mem[A] <= D; +endmodule + +module RAM512X1S ( + output O, + input [8:0] A, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [511:0] INIT = 512'h0; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + reg [511:0] mem = INIT; + assign O = mem[A]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) if (WE) mem[A] <= D; +endmodule + +// Single port, wide. + +module RAM16X2S ( + output O0, O1, + input A0, A1, A2, A3, + input D0, D1, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [15:0] INIT_00 = 16'h0000; + parameter [15:0] INIT_01 = 16'h0000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [3:0] a = {A3, A2, A1, A0}; + wire clk = WCLK ^ IS_WCLK_INVERTED; + reg [15:0] mem0 = INIT_00; + reg [15:0] mem1 = INIT_01; + assign O0 = mem0[a]; + assign O1 = mem1[a]; + always @(posedge clk) + if (WE) begin + mem0[a] <= D0; + mem1[a] <= D1; + end +endmodule + +module RAM32X2S ( + output O0, O1, + input A0, A1, A2, A3, A4, + input D0, D1, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [31:0] INIT_00 = 32'h00000000; + parameter [31:0] INIT_01 = 32'h00000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [4:0] a = {A4, A3, A2, A1, A0}; + wire clk = WCLK ^ IS_WCLK_INVERTED; + reg [31:0] mem0 = INIT_00; + reg [31:0] mem1 = INIT_01; + assign O0 = mem0[a]; + assign O1 = mem1[a]; + always @(posedge clk) + if (WE) begin + mem0[a] <= D0; + mem1[a] <= D1; + end +endmodule + +module RAM64X2S ( + output O0, O1, + input A0, A1, A2, A3, A4, A5, + input D0, D1, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [63:0] INIT_00 = 64'h0000000000000000; + parameter [63:0] INIT_01 = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [5:0] a = {A5, A3, A2, A1, A0}; + wire clk = WCLK ^ IS_WCLK_INVERTED; + reg [63:0] mem0 = INIT_00; + reg [63:0] mem1 = INIT_01; + assign O0 = mem0[a]; + assign O1 = mem1[a]; + always @(posedge clk) + if (WE) begin + mem0[a] <= D0; + mem1[a] <= D1; + end +endmodule + +module RAM16X4S ( + output O0, O1, O2, O3, + input A0, A1, A2, A3, + input D0, D1, D2, D3, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [15:0] INIT_00 = 16'h0000; + parameter [15:0] INIT_01 = 16'h0000; + parameter [15:0] INIT_02 = 16'h0000; + parameter [15:0] INIT_03 = 16'h0000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [3:0] a = {A3, A2, A1, A0}; + wire clk = WCLK ^ IS_WCLK_INVERTED; + reg [15:0] mem0 = INIT_00; + reg [15:0] mem1 = INIT_01; + reg [15:0] mem2 = INIT_02; + reg [15:0] mem3 = INIT_03; + assign O0 = mem0[a]; + assign O1 = mem1[a]; + assign O2 = mem2[a]; + assign O3 = mem3[a]; + always @(posedge clk) + if (WE) begin + mem0[a] <= D0; + mem1[a] <= D1; + mem2[a] <= D2; + mem3[a] <= D3; + end +endmodule + +module RAM32X4S ( + output O0, O1, O2, O3, + input A0, A1, A2, A3, A4, + input D0, D1, D2, D3, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [31:0] INIT_00 = 32'h00000000; + parameter [31:0] INIT_01 = 32'h00000000; + parameter [31:0] INIT_02 = 32'h00000000; + parameter [31:0] INIT_03 = 32'h00000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [4:0] a = {A4, A3, A2, A1, A0}; + wire clk = WCLK ^ IS_WCLK_INVERTED; + reg [31:0] mem0 = INIT_00; + reg [31:0] mem1 = INIT_01; + reg [31:0] mem2 = INIT_02; + reg [31:0] mem3 = INIT_03; + assign O0 = mem0[a]; + assign O1 = mem1[a]; + assign O2 = mem2[a]; + assign O3 = mem3[a]; + always @(posedge clk) + if (WE) begin + mem0[a] <= D0; + mem1[a] <= D1; + mem2[a] <= D2; + mem3[a] <= D3; + end +endmodule + +module RAM16X8S ( + output [7:0] O, + input A0, A1, A2, A3, + input [7:0] D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [15:0] INIT_00 = 16'h0000; + parameter [15:0] INIT_01 = 16'h0000; + parameter [15:0] INIT_02 = 16'h0000; + parameter [15:0] INIT_03 = 16'h0000; + parameter [15:0] INIT_04 = 16'h0000; + parameter [15:0] INIT_05 = 16'h0000; + parameter [15:0] INIT_06 = 16'h0000; + parameter [15:0] INIT_07 = 16'h0000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [3:0] a = {A3, A2, A1, A0}; + wire clk = WCLK ^ IS_WCLK_INVERTED; + reg [15:0] mem0 = INIT_00; + reg [15:0] mem1 = INIT_01; + reg [15:0] mem2 = INIT_02; + reg [15:0] mem3 = INIT_03; + reg [15:0] mem4 = INIT_04; + reg [15:0] mem5 = INIT_05; + reg [15:0] mem6 = INIT_06; + reg [15:0] mem7 = INIT_07; + assign O[0] = mem0[a]; + assign O[1] = mem1[a]; + assign O[2] = mem2[a]; + assign O[3] = mem3[a]; + assign O[4] = mem4[a]; + assign O[5] = mem5[a]; + assign O[6] = mem6[a]; + assign O[7] = mem7[a]; + always @(posedge clk) + if (WE) begin + mem0[a] <= D[0]; + mem1[a] <= D[1]; + mem2[a] <= D[2]; + mem3[a] <= D[3]; + mem4[a] <= D[4]; + mem5[a] <= D[5]; + mem6[a] <= D[6]; + mem7[a] <= D[7]; + end +endmodule + +module RAM32X8S ( + output [7:0] O, + input A0, A1, A2, A3, A4, + input [7:0] D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [31:0] INIT_00 = 32'h00000000; + parameter [31:0] INIT_01 = 32'h00000000; + parameter [31:0] INIT_02 = 32'h00000000; + parameter [31:0] INIT_03 = 32'h00000000; + parameter [31:0] INIT_04 = 32'h00000000; + parameter [31:0] INIT_05 = 32'h00000000; + parameter [31:0] INIT_06 = 32'h00000000; + parameter [31:0] INIT_07 = 32'h00000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [4:0] a = {A4, A3, A2, A1, A0}; + wire clk = WCLK ^ IS_WCLK_INVERTED; + reg [31:0] mem0 = INIT_00; + reg [31:0] mem1 = INIT_01; + reg [31:0] mem2 = INIT_02; + reg [31:0] mem3 = INIT_03; + reg [31:0] mem4 = INIT_04; + reg [31:0] mem5 = INIT_05; + reg [31:0] mem6 = INIT_06; + reg [31:0] mem7 = INIT_07; + assign O[0] = mem0[a]; + assign O[1] = mem1[a]; + assign O[2] = mem2[a]; + assign O[3] = mem3[a]; + assign O[4] = mem4[a]; + assign O[5] = mem5[a]; + assign O[6] = mem6[a]; + assign O[7] = mem7[a]; + always @(posedge clk) + if (WE) begin + mem0[a] <= D[0]; + mem1[a] <= D[1]; + mem2[a] <= D[2]; + mem3[a] <= D[3]; + mem4[a] <= D[4]; + mem5[a] <= D[5]; + mem6[a] <= D[6]; + mem7[a] <= D[7]; + end +endmodule + +// Dual port. + +module RAM16X1D ( + output DPO, SPO, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE, + input A0, A1, A2, A3, + input DPRA0, DPRA1, DPRA2, DPRA3 +); + parameter INIT = 16'h0; + parameter IS_WCLK_INVERTED = 1'b0; + wire [3:0] a = {A3, A2, A1, A0}; + wire [3:0] dpra = {DPRA3, DPRA2, DPRA1, DPRA0}; + reg [15:0] mem = INIT; + assign SPO = mem[a]; + assign DPO = mem[dpra]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) if (WE) mem[a] <= D; +endmodule + +module RAM16X1D_1 ( + output DPO, SPO, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE, + input A0, A1, A2, A3, + input DPRA0, DPRA1, DPRA2, DPRA3 +); + parameter INIT = 16'h0; + parameter IS_WCLK_INVERTED = 1'b0; + wire [3:0] a = {A3, A2, A1, A0}; + wire [3:0] dpra = {DPRA3, DPRA2, DPRA1, DPRA0}; + reg [15:0] mem = INIT; + assign SPO = mem[a]; + assign DPO = mem[dpra]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(negedge clk) if (WE) mem[a] <= D; +endmodule + +(* abc9_box, lib_whitebox *) +module RAM32X1D ( + output DPO, SPO, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE, + input A0, A1, A2, A3, A4, + input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4 +); + parameter INIT = 32'h0; + parameter IS_WCLK_INVERTED = 1'b0; + wire [4:0] a = {A4, A3, A2, A1, A0}; + wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}; + reg [31:0] mem = INIT; + assign SPO = mem[a]; + assign DPO = mem[dpra]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) if (WE) mem[a] <= D; + specify + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986 + $setup(D , posedge WCLK &&& !IS_WCLK_INVERTED && WE, 453); + $setup(D , negedge WCLK &&& IS_WCLK_INVERTED && WE, 453); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834 + $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED, 654); + $setup(WE, negedge WCLK &&& IS_WCLK_INVERTED, 654); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800 + $setup(A0, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245); + $setup(A0, negedge WCLK &&& IS_WCLK_INVERTED && WE, 245); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798 + $setup(A1, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208); + $setup(A1, negedge WCLK &&& IS_WCLK_INVERTED && WE, 208); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796 + $setup(A2, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147); + $setup(A2, negedge WCLK &&& IS_WCLK_INVERTED && WE, 147); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794 + $setup(A3, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68); + $setup(A3, negedge WCLK &&& IS_WCLK_INVERTED && WE, 68); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792 + $setup(A4, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66); + $setup(A4, posedge WCLK &&& IS_WCLK_INVERTED && WE, 66); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981 + if (!IS_WCLK_INVERTED) (posedge WCLK => (SPO : D)) = 1153; + if (!IS_WCLK_INVERTED) (posedge WCLK => (DPO : 1'bx)) = 1153; + if ( IS_WCLK_INVERTED) (posedge WCLK => (SPO : D)) = 1153; + if ( IS_WCLK_INVERTED) (negedge WCLK => (DPO : 1'bx)) = 1153; + (A0 => SPO) = 642; (DPRA0 => DPO) = 642; + (A1 => SPO) = 632; (DPRA1 => DPO) = 631; + (A2 => SPO) = 472; (DPRA2 => DPO) = 472; + (A3 => SPO) = 407; (DPRA3 => DPO) = 407; + (A4 => SPO) = 238; (DPRA4 => DPO) = 238; + endspecify +endmodule + +(* abc9_box, lib_whitebox *) +module RAM32X1D_1 ( + output DPO, SPO, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE, + input A0, + input A1, + input A2, + input A3, + input A4, + input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4 +); + parameter INIT = 32'h0; + parameter IS_WCLK_INVERTED = 1'b0; + wire [4:0] a = {A4, A3, A2, A1, A0}; + wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}; + reg [31:0] mem = INIT; + assign SPO = mem[a]; + assign DPO = mem[dpra]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(negedge clk) if (WE) mem[a] <= D; + specify + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986 + $setup(D , negedge WCLK &&& WE, 453); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834 + $setup(WE, negedge WCLK, 654); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800 + $setup(A0, negedge WCLK &&& WE, 245); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798 + $setup(A1, negedge WCLK &&& WE, 208); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796 + $setup(A2, negedge WCLK &&& WE, 147); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794 + $setup(A3, negedge WCLK &&& WE, 68); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792 + $setup(A4, negedge WCLK &&& WE, 66); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981 + if (WE) (negedge WCLK => (SPO : D)) = 1153; + if (WE) (negedge WCLK => (DPO : 1'bx)) = 1153; + (A0 => SPO) = 642; (DPRA0 => DPO) = 642; + (A1 => SPO) = 632; (DPRA1 => DPO) = 631; + (A2 => SPO) = 472; (DPRA2 => DPO) = 472; + (A3 => SPO) = 407; (DPRA3 => DPO) = 407; + (A4 => SPO) = 238; (DPRA4 => DPO) = 238; + endspecify +endmodule + +(* abc9_box, lib_whitebox *) +module RAM64X1D ( + output DPO, SPO, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE, + input A0, A1, A2, A3, A4, A5, + input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 +); + parameter INIT = 64'h0; + parameter IS_WCLK_INVERTED = 1'b0; + wire [5:0] a = {A5, A4, A3, A2, A1, A0}; + wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}; + reg [63:0] mem = INIT; + assign SPO = mem[a]; + assign DPO = mem[dpra]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) if (WE) mem[a] <= D; + specify + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986 + $setup(D , posedge WCLK &&& !IS_WCLK_INVERTED && WE, 453); + $setup(D , negedge WCLK &&& IS_WCLK_INVERTED && WE, 453); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834 + $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED, 654); + $setup(WE, negedge WCLK &&& IS_WCLK_INVERTED, 654); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828 + $setup(A0, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 362); + $setup(A0, negedge WCLK &&& IS_WCLK_INVERTED && WE, 362); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826 + $setup(A1, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245); + $setup(A1, negedge WCLK &&& IS_WCLK_INVERTED && WE, 245); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824 + $setup(A2, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208); + $setup(A2, negedge WCLK &&& IS_WCLK_INVERTED && WE, 208); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822 + $setup(A3, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147); + $setup(A3, negedge WCLK &&& IS_WCLK_INVERTED && WE, 147); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820 + $setup(A4, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68); + $setup(A4, negedge WCLK &&& IS_WCLK_INVERTED && WE, 68); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818 + $setup(A5, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66); + $setup(A5, negedge WCLK &&& IS_WCLK_INVERTED && WE, 66); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981 + if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (SPO : D)) = 1153; + if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DPO : 1'bx)) = 1153; + if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (SPO : D)) = 1153; + if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DPO : 1'bx)) = 1153; + (A0 => SPO) = 642; (DPRA0 => DPO) = 642; + (A1 => SPO) = 632; (DPRA1 => DPO) = 631; + (A2 => SPO) = 472; (DPRA2 => DPO) = 472; + (A3 => SPO) = 407; (DPRA3 => DPO) = 407; + (A4 => SPO) = 238; (DPRA4 => DPO) = 238; + (A5 => SPO) = 127; (DPRA5 => DPO) = 127; + endspecify +endmodule + +module RAM64X1D_1 ( + output DPO, SPO, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE, + input A0, A1, A2, A3, A4, A5, + input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 +); + parameter INIT = 64'h0; + parameter IS_WCLK_INVERTED = 1'b0; + wire [5:0] a = {A5, A4, A3, A2, A1, A0}; + wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}; + reg [63:0] mem = INIT; + assign SPO = mem[a]; + assign DPO = mem[dpra]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(negedge clk) if (WE) mem[a] <= D; + specify + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986 + $setup(D , negedge WCLK &&& WE, 453); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834 + $setup(WE, negedge WCLK, 654); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828 + $setup(A0, negedge WCLK &&& WE, 362); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826 + $setup(A1, negedge WCLK &&& WE, 245); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824 + $setup(A2, negedge WCLK &&& WE, 208); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822 + $setup(A3, negedge WCLK &&& WE, 147); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820 + $setup(A4, negedge WCLK &&& WE, 68); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818 + $setup(A5, negedge WCLK &&& WE, 66); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981 + if (WE) (negedge WCLK => (SPO : D)) = 1153; + if (WE) (negedge WCLK => (DPO : 1'bx)) = 1153; + (A0 => SPO) = 642; (DPRA0 => DPO) = 642; + (A1 => SPO) = 632; (DPRA1 => DPO) = 631; + (A2 => SPO) = 472; (DPRA2 => DPO) = 472; + (A3 => SPO) = 407; (DPRA3 => DPO) = 407; + (A4 => SPO) = 238; (DPRA4 => DPO) = 238; + (A5 => SPO) = 127; (DPRA5 => DPO) = 127; + endspecify +endmodule + +(* abc9_box, lib_whitebox *) +module RAM128X1D ( + output DPO, SPO, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE, + input [6:0] A, + input [6:0] DPRA +); + parameter INIT = 128'h0; + parameter IS_WCLK_INVERTED = 1'b0; + reg [127:0] mem = INIT; + assign SPO = mem[A]; + assign DPO = mem[DPRA]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) if (WE) mem[A] <= D; + specify + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986 + $setup(D , posedge WCLK &&& !IS_WCLK_INVERTED && WE, 453); + $setup(D , negedge WCLK &&& IS_WCLK_INVERTED && WE, 453); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834 + $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED, 654); + $setup(WE, negedge WCLK &&& IS_WCLK_INVERTED, 654); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-830 + $setup(A[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 616); + $setup(A[0], negedge WCLK &&& IS_WCLK_INVERTED && WE, 616); + $setup(A[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 362); + $setup(A[1], negedge WCLK &&& IS_WCLK_INVERTED && WE, 362); + $setup(A[2], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245); + $setup(A[2], negedge WCLK &&& IS_WCLK_INVERTED && WE, 245); + $setup(A[3], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208); + $setup(A[3], negedge WCLK &&& IS_WCLK_INVERTED && WE, 208); + $setup(A[4], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147); + $setup(A[4], negedge WCLK &&& IS_WCLK_INVERTED && WE, 147); + $setup(A[5], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68); + $setup(A[5], negedge WCLK &&& IS_WCLK_INVERTED && WE, 68); + $setup(A[6], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66); + $setup(A[6], negedge WCLK &&& IS_WCLK_INVERTED && WE, 66); +`ifndef __ICARUS__ + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981 + if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (SPO : D)) = 1153 + 217 /* to cross F7AMUX */ + 175 /* AMUX */; + if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DPO : 1'bx)) = 1153 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; + (A[0] => SPO) = 642 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; + (A[1] => SPO) = 631 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; + (A[2] => SPO) = 472 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; + (A[3] => SPO) = 407 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; + (A[4] => SPO) = 238 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; + (A[5] => SPO) = 127 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; + (A[6] => SPO) = 0 + 276 /* to select F7AMUX */ + 175 /* AMUX */; + (DPRA[0] => DPO) = 642 + 223 /* to cross LUTMUX7 */ + 174 /* CMUX */; + (DPRA[1] => DPO) = 631 + 223 /* to cross LUTMUX7 */ + 174 /* CMUX */; + (DPRA[2] => DPO) = 472 + 223 /* to cross LUTMUX7 */ + 174 /* CMUX */; + (DPRA[3] => DPO) = 407 + 223 /* to cross LUTMUX7 */ + 174 /* CMUX */; + (DPRA[4] => DPO) = 238 + 223 /* to cross LUTMUX7 */ + 174 /* CMUX */; + (DPRA[5] => DPO) = 127 + 223 /* to cross LUTMUX7 */ + 174 /* CMUX */; + (DPRA[6] => DPO) = 0 + 296 /* to select LUTMUX7 */ + 174 /* CMUX */; +`endif + endspecify +endmodule + +module RAM256X1D ( + output DPO, SPO, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE, + input [7:0] A, DPRA +); + parameter INIT = 256'h0; + parameter IS_WCLK_INVERTED = 1'b0; + reg [255:0] mem = INIT; + assign SPO = mem[A]; + assign DPO = mem[DPRA]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) if (WE) mem[A] <= D; +endmodule + +// Multi port. + +(* abc9_box, lib_whitebox *) +module RAM32M ( + output [1:0] DOA, + output [1:0] DOB, + output [1:0] DOC, + output [1:0] DOD, + input [4:0] ADDRA, ADDRB, ADDRC, + input [4:0] ADDRD, + input [1:0] DIA, + input [1:0] DIB, + input [1:0] DIC, + input [1:0] DID, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [63:0] INIT_A = 64'h0000000000000000; + parameter [63:0] INIT_B = 64'h0000000000000000; + parameter [63:0] INIT_C = 64'h0000000000000000; + parameter [63:0] INIT_D = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + reg [63:0] mem_a = INIT_A; + reg [63:0] mem_b = INIT_B; + reg [63:0] mem_c = INIT_C; + reg [63:0] mem_d = INIT_D; + assign DOA = mem_a[2*ADDRA+:2]; + assign DOB = mem_b[2*ADDRB+:2]; + assign DOC = mem_c[2*ADDRC+:2]; + assign DOD = mem_d[2*ADDRD+:2]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) + if (WE) begin + mem_a[2*ADDRD+:2] <= DIA; + mem_b[2*ADDRD+:2] <= DIB; + mem_c[2*ADDRD+:2] <= DIC; + mem_d[2*ADDRD+:2] <= DID; + end + specify + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986 + $setup(ADDRD[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245); + $setup(ADDRD[0], negedge WCLK &&& IS_WCLK_INVERTED && WE, 245); + $setup(ADDRD[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208); + $setup(ADDRD[1], negedge WCLK &&& IS_WCLK_INVERTED && WE, 208); + $setup(ADDRD[2], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147); + $setup(ADDRD[2], negedge WCLK &&& IS_WCLK_INVERTED && WE, 147); + $setup(ADDRD[3], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68); + $setup(ADDRD[3], negedge WCLK &&& IS_WCLK_INVERTED && WE, 68); + $setup(ADDRD[4], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66); + $setup(ADDRD[4], negedge WCLK &&& IS_WCLK_INVERTED && WE, 66); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988 + $setup(DIA[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 453); + $setup(DIA[0], negedge WCLK &&& IS_WCLK_INVERTED && WE, 453); + $setup(DIA[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 384); + $setup(DIA[1], negedge WCLK &&& IS_WCLK_INVERTED && WE, 384); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056 + $setup(DIB[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 461); + $setup(DIB[0], negedge WCLK &&& IS_WCLK_INVERTED && WE, 461); + $setup(DIB[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 354); + $setup(DIB[1], negedge WCLK &&& IS_WCLK_INVERTED && WE, 354); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124 + $setup(DIC[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 457); + $setup(DIC[0], negedge WCLK &&& IS_WCLK_INVERTED && WE, 457); + $setup(DIC[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 375); + $setup(DIC[1], negedge WCLK &&& IS_WCLK_INVERTED && WE, 375); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192 + $setup(DID[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 310); + $setup(DID[0], negedge WCLK &&& IS_WCLK_INVERTED && WE, 310); + $setup(DID[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 334); + $setup(DID[1], negedge WCLK &&& IS_WCLK_INVERTED && WE, 334); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834 + $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED, 654); + $setup(WE, negedge WCLK &&& IS_WCLK_INVERTED, 654); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889 + if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOA[0] : DIA[0])) = 1153; + if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOA[0] : DIA[0])) = 1153; + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857 + if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOA[1] : DIA[1])) = 1188; + if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOA[1] : DIA[1])) = 1188; + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 + if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOB[0] : DIB[0])) = 1161; + if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOB[0] : DIB[0])) = 1161; + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L925 + if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOB[1] : DIB[1])) = 1187; + if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOB[1] : DIB[1])) = 1187; + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L993 + if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOC[0] : DIC[0])) = 1158; + if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOC[0] : DIC[0])) = 1158; + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025 + if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOC[1] : DIC[1])) = 1180; + if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOC[1] : DIC[1])) = 1180; + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093 + if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD[0] : DID[0])) = 1163; + if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD[0] : DID[0])) = 1163; + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061 + if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD[1] : DID[1])) = 1190; + if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD[1] : DID[1])) = 1190; + (ADDRA[0] *> DOA) = 642; (ADDRB[0] *> DOB) = 642; (ADDRC[0] *> DOC) = 642; (ADDRD[0] *> DOD) = 642; + (ADDRA[1] *> DOA) = 631; (ADDRB[1] *> DOB) = 631; (ADDRC[1] *> DOC) = 631; (ADDRD[1] *> DOD) = 631; + (ADDRA[2] *> DOA) = 472; (ADDRB[2] *> DOB) = 472; (ADDRC[2] *> DOC) = 472; (ADDRD[2] *> DOD) = 472; + (ADDRA[3] *> DOA) = 407; (ADDRB[3] *> DOB) = 407; (ADDRC[3] *> DOC) = 407; (ADDRD[3] *> DOD) = 407; + (ADDRA[4] *> DOA) = 238; (ADDRB[4] *> DOB) = 238; (ADDRC[4] *> DOC) = 238; (ADDRD[4] *> DOD) = 238; + endspecify +endmodule + +module RAM32M16 ( + output [1:0] DOA, + output [1:0] DOB, + output [1:0] DOC, + output [1:0] DOD, + output [1:0] DOE, + output [1:0] DOF, + output [1:0] DOG, + output [1:0] DOH, + input [4:0] ADDRA, + input [4:0] ADDRB, + input [4:0] ADDRC, + input [4:0] ADDRD, + input [4:0] ADDRE, + input [4:0] ADDRF, + input [4:0] ADDRG, + input [4:0] ADDRH, + input [1:0] DIA, + input [1:0] DIB, + input [1:0] DIC, + input [1:0] DID, + input [1:0] DIE, + input [1:0] DIF, + input [1:0] DIG, + input [1:0] DIH, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [63:0] INIT_A = 64'h0000000000000000; + parameter [63:0] INIT_B = 64'h0000000000000000; + parameter [63:0] INIT_C = 64'h0000000000000000; + parameter [63:0] INIT_D = 64'h0000000000000000; + parameter [63:0] INIT_E = 64'h0000000000000000; + parameter [63:0] INIT_F = 64'h0000000000000000; + parameter [63:0] INIT_G = 64'h0000000000000000; + parameter [63:0] INIT_H = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + reg [63:0] mem_a = INIT_A; + reg [63:0] mem_b = INIT_B; + reg [63:0] mem_c = INIT_C; + reg [63:0] mem_d = INIT_D; + reg [63:0] mem_e = INIT_E; + reg [63:0] mem_f = INIT_F; + reg [63:0] mem_g = INIT_G; + reg [63:0] mem_h = INIT_H; + assign DOA = mem_a[2*ADDRA+:2]; + assign DOB = mem_b[2*ADDRB+:2]; + assign DOC = mem_c[2*ADDRC+:2]; + assign DOD = mem_d[2*ADDRD+:2]; + assign DOE = mem_e[2*ADDRE+:2]; + assign DOF = mem_f[2*ADDRF+:2]; + assign DOG = mem_g[2*ADDRG+:2]; + assign DOH = mem_h[2*ADDRH+:2]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) + if (WE) begin + mem_a[2*ADDRH+:2] <= DIA; + mem_b[2*ADDRH+:2] <= DIB; + mem_c[2*ADDRH+:2] <= DIC; + mem_d[2*ADDRH+:2] <= DID; + mem_e[2*ADDRH+:2] <= DIE; + mem_f[2*ADDRH+:2] <= DIF; + mem_g[2*ADDRH+:2] <= DIG; + mem_h[2*ADDRH+:2] <= DIH; + end +endmodule + +(* abc9_box, lib_whitebox *) +module RAM64M ( + output DOA, + output DOB, + output DOC, + output DOD, + input [5:0] ADDRA, ADDRB, ADDRC, + input [5:0] ADDRD, + input DIA, + input DIB, + input DIC, + input DID, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [63:0] INIT_A = 64'h0000000000000000; + parameter [63:0] INIT_B = 64'h0000000000000000; + parameter [63:0] INIT_C = 64'h0000000000000000; + parameter [63:0] INIT_D = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + reg [63:0] mem_a = INIT_A; + reg [63:0] mem_b = INIT_B; + reg [63:0] mem_c = INIT_C; + reg [63:0] mem_d = INIT_D; + assign DOA = mem_a[ADDRA]; + assign DOB = mem_b[ADDRB]; + assign DOC = mem_c[ADDRC]; + assign DOD = mem_d[ADDRD]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) + if (WE) begin + mem_a[ADDRD] <= DIA; + mem_b[ADDRD] <= DIB; + mem_c[ADDRD] <= DIC; + mem_d[ADDRD] <= DID; + end + specify + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-L830 + $setup(ADDRD[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 362); + $setup(ADDRD[0], negedge WCLK &&& IS_WCLK_INVERTED && WE, 362); + $setup(ADDRD[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245); + $setup(ADDRD[1], negedge WCLK &&& IS_WCLK_INVERTED && WE, 245); + $setup(ADDRD[2], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208); + $setup(ADDRD[2], negedge WCLK &&& IS_WCLK_INVERTED && WE, 208); + $setup(ADDRD[3], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147); + $setup(ADDRD[3], negedge WCLK &&& IS_WCLK_INVERTED && WE, 147); + $setup(ADDRD[4], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68); + $setup(ADDRD[4], negedge WCLK &&& IS_WCLK_INVERTED && WE, 68); + $setup(ADDRD[5], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66); + $setup(ADDRD[5], negedge WCLK &&& IS_WCLK_INVERTED && WE, 66); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988 + $setup(DIA, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 384); + $setup(DIA, negedge WCLK &&& IS_WCLK_INVERTED && WE, 384); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056 + $setup(DIB, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 354); + $setup(DIB, negedge WCLK &&& IS_WCLK_INVERTED && WE, 354); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124 + $setup(DIC, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 375); + $setup(DIC, negedge WCLK &&& IS_WCLK_INVERTED && WE, 375); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192 + $setup(DID, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 310); + $setup(DID, negedge WCLK &&& IS_WCLK_INVERTED && WE, 310); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834 + $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 654); + $setup(WE, negedge WCLK &&& IS_WCLK_INVERTED && WE, 654); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889 + if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOA : DIA)) = 1153; + if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOA : DIA)) = 1153; + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 + if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOB : DIB)) = 1161; + if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOB : DIB)) = 1161; + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025 + if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOC : DIC)) = 1158; + if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOC : DIC)) = 1158; + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093 + if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD : DID)) = 1163; + if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD : DID)) = 1163; + (ADDRA[0] => DOA) = 642; (ADDRB[0] => DOB) = 642; (ADDRC[0] => DOC) = 642; (ADDRD[0] => DOD) = 642; + (ADDRA[1] => DOA) = 631; (ADDRB[1] => DOB) = 631; (ADDRC[1] => DOC) = 631; (ADDRD[1] => DOD) = 631; + (ADDRA[2] => DOA) = 472; (ADDRB[2] => DOB) = 472; (ADDRC[2] => DOC) = 472; (ADDRD[2] => DOD) = 472; + (ADDRA[3] => DOA) = 407; (ADDRB[3] => DOB) = 407; (ADDRC[3] => DOC) = 407; (ADDRD[3] => DOD) = 407; + (ADDRA[4] => DOA) = 238; (ADDRB[4] => DOB) = 238; (ADDRC[4] => DOC) = 238; (ADDRD[4] => DOD) = 238; + endspecify +endmodule + +module RAM64M8 ( + output DOA, + output DOB, + output DOC, + output DOD, + output DOE, + output DOF, + output DOG, + output DOH, + input [5:0] ADDRA, + input [5:0] ADDRB, + input [5:0] ADDRC, + input [5:0] ADDRD, + input [5:0] ADDRE, + input [5:0] ADDRF, + input [5:0] ADDRG, + input [5:0] ADDRH, + input DIA, + input DIB, + input DIC, + input DID, + input DIE, + input DIF, + input DIG, + input DIH, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [63:0] INIT_A = 64'h0000000000000000; + parameter [63:0] INIT_B = 64'h0000000000000000; + parameter [63:0] INIT_C = 64'h0000000000000000; + parameter [63:0] INIT_D = 64'h0000000000000000; + parameter [63:0] INIT_E = 64'h0000000000000000; + parameter [63:0] INIT_F = 64'h0000000000000000; + parameter [63:0] INIT_G = 64'h0000000000000000; + parameter [63:0] INIT_H = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + reg [63:0] mem_a = INIT_A; + reg [63:0] mem_b = INIT_B; + reg [63:0] mem_c = INIT_C; + reg [63:0] mem_d = INIT_D; + reg [63:0] mem_e = INIT_E; + reg [63:0] mem_f = INIT_F; + reg [63:0] mem_g = INIT_G; + reg [63:0] mem_h = INIT_H; + assign DOA = mem_a[ADDRA]; + assign DOB = mem_b[ADDRB]; + assign DOC = mem_c[ADDRC]; + assign DOD = mem_d[ADDRD]; + assign DOE = mem_e[ADDRE]; + assign DOF = mem_f[ADDRF]; + assign DOG = mem_g[ADDRG]; + assign DOH = mem_h[ADDRH]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) + if (WE) begin + mem_a[ADDRH] <= DIA; + mem_b[ADDRH] <= DIB; + mem_c[ADDRH] <= DIC; + mem_d[ADDRH] <= DID; + mem_e[ADDRH] <= DIE; + mem_f[ADDRH] <= DIF; + mem_g[ADDRH] <= DIG; + mem_h[ADDRH] <= DIH; + end +endmodule + +module RAM32X16DR8 ( + output DOA, + output DOB, + output DOC, + output DOD, + output DOE, + output DOF, + output DOG, + output [1:0] DOH, + input [5:0] ADDRA, ADDRB, ADDRC, ADDRD, ADDRE, ADDRF, ADDRG, + input [4:0] ADDRH, + input [1:0] DIA, + input [1:0] DIB, + input [1:0] DIC, + input [1:0] DID, + input [1:0] DIE, + input [1:0] DIF, + input [1:0] DIG, + input [1:0] DIH, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + reg [63:0] mem_a, mem_b, mem_c, mem_d, mem_e, mem_f, mem_g, mem_h; + assign DOA = mem_a[ADDRA]; + assign DOB = mem_b[ADDRB]; + assign DOC = mem_c[ADDRC]; + assign DOD = mem_d[ADDRD]; + assign DOE = mem_e[ADDRE]; + assign DOF = mem_f[ADDRF]; + assign DOG = mem_g[ADDRG]; + assign DOH = mem_h[2*ADDRH+:2]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) + if (WE) begin + mem_a[2*ADDRH+:2] <= DIA; + mem_b[2*ADDRH+:2] <= DIB; + mem_c[2*ADDRH+:2] <= DIC; + mem_d[2*ADDRH+:2] <= DID; + mem_e[2*ADDRH+:2] <= DIE; + mem_f[2*ADDRH+:2] <= DIF; + mem_g[2*ADDRH+:2] <= DIG; + mem_h[2*ADDRH+:2] <= DIH; + end +endmodule + +module RAM64X8SW ( + output [7:0] O, + input [5:0] A, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE, + input [2:0] WSEL +); + parameter [63:0] INIT_A = 64'h0000000000000000; + parameter [63:0] INIT_B = 64'h0000000000000000; + parameter [63:0] INIT_C = 64'h0000000000000000; + parameter [63:0] INIT_D = 64'h0000000000000000; + parameter [63:0] INIT_E = 64'h0000000000000000; + parameter [63:0] INIT_F = 64'h0000000000000000; + parameter [63:0] INIT_G = 64'h0000000000000000; + parameter [63:0] INIT_H = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + reg [63:0] mem_a = INIT_A; + reg [63:0] mem_b = INIT_B; + reg [63:0] mem_c = INIT_C; + reg [63:0] mem_d = INIT_D; + reg [63:0] mem_e = INIT_E; + reg [63:0] mem_f = INIT_F; + reg [63:0] mem_g = INIT_G; + reg [63:0] mem_h = INIT_H; + assign O[7] = mem_a[A]; + assign O[6] = mem_b[A]; + assign O[5] = mem_c[A]; + assign O[4] = mem_d[A]; + assign O[3] = mem_e[A]; + assign O[2] = mem_f[A]; + assign O[1] = mem_g[A]; + assign O[0] = mem_h[A]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) + if (WE) begin + case (WSEL) + 3'b111: mem_a[A] <= D; + 3'b110: mem_b[A] <= D; + 3'b101: mem_c[A] <= D; + 3'b100: mem_d[A] <= D; + 3'b011: mem_e[A] <= D; + 3'b010: mem_f[A] <= D; + 3'b001: mem_g[A] <= D; + 3'b000: mem_h[A] <= D; + endcase + end +endmodule + +// ROM. + +module ROM16X1 ( + output O, + input A0, A1, A2, A3 +); + parameter [15:0] INIT = 16'h0; + assign O = INIT[{A3, A2, A1, A0}]; +endmodule + +module ROM32X1 ( + output O, + input A0, A1, A2, A3, A4 +); + parameter [31:0] INIT = 32'h0; + assign O = INIT[{A4, A3, A2, A1, A0}]; +endmodule + +module ROM64X1 ( + output O, + input A0, A1, A2, A3, A4, A5 +); + parameter [63:0] INIT = 64'h0; + assign O = INIT[{A5, A4, A3, A2, A1, A0}]; +endmodule + +module ROM128X1 ( + output O, + input A0, A1, A2, A3, A4, A5, A6 +); + parameter [127:0] INIT = 128'h0; + assign O = INIT[{A6, A5, A4, A3, A2, A1, A0}]; +endmodule + +module ROM256X1 ( + output O, + input A0, A1, A2, A3, A4, A5, A6, A7 +); + parameter [255:0] INIT = 256'h0; + assign O = INIT[{A7, A6, A5, A4, A3, A2, A1, A0}]; +endmodule + +// Shift registers. + +(* abc9_box, lib_whitebox *) +module SRL16 ( + output Q, + input A0, A1, A2, A3, + (* clkbuf_sink *) + input CLK, + input D +); + parameter [15:0] INIT = 16'h0000; + + reg [15:0] r = INIT; + assign Q = r[{A3,A2,A1,A0}]; + always @(posedge CLK) r <= { r[14:0], D }; + + specify + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905 + (posedge CLK => (Q : 1'bx)) = 1472; + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912 + $setup(D , posedge CLK, 173); + (A0 => Q) = 631; + (A1 => Q) = 472; + (A2 => Q) = 407; + (A3 => Q) = 238; + endspecify +endmodule + +(* abc9_box, lib_whitebox *) +module SRL16E ( + output Q, + input A0, A1, A2, A3, CE, + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK, + input D +); + parameter [15:0] INIT = 16'h0000; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + + reg [15:0] r = INIT; + assign Q = r[{A3,A2,A1,A0}]; + generate + if (IS_CLK_INVERTED) begin + always @(negedge CLK) if (CE) r <= { r[14:0], D }; + end + else + always @(posedge CLK) if (CE) r <= { r[14:0], D }; + endgenerate + specify + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912 + $setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173); + $setup(D , negedge CLK &&& IS_CLK_INVERTED, 173); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905 + if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : D)) = 1472; + if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : D)) = 1472; + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905 + if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : 1'bx)) = 1472; + if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : 1'bx)) = 1472; + (A0 => Q) = 631; + (A1 => Q) = 472; + (A2 => Q) = 407; + (A3 => Q) = 238; + endspecify +endmodule + +(* abc9_box, lib_whitebox *) +module SRLC16 ( + output Q, + output Q15, + input A0, A1, A2, A3, + (* clkbuf_sink *) + input CLK, + input D +); + parameter [15:0] INIT = 16'h0000; + + reg [15:0] r = INIT; + assign Q15 = r[15]; + assign Q = r[{A3,A2,A1,A0}]; + always @(posedge CLK) r <= { r[14:0], D }; + + specify + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912 + $setup(D , posedge CLK, 173); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905 + (posedge CLK => (Q : 1'bx)) = 1472; + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904 + (posedge CLK => (Q15 : 1'bx)) = 1114; + (A0 => Q) = 631; + (A1 => Q) = 472; + (A2 => Q) = 407; + (A3 => Q) = 238; + endspecify +endmodule + +(* abc9_box, lib_whitebox *) +module SRLC16E ( + output Q, + output Q15, + input A0, A1, A2, A3, CE, + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK, + input D +); + parameter [15:0] INIT = 16'h0000; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + + reg [15:0] r = INIT; + assign Q15 = r[15]; + assign Q = r[{A3,A2,A1,A0}]; + generate + if (IS_CLK_INVERTED) begin + always @(negedge CLK) if (CE) r <= { r[14:0], D }; + end + else + always @(posedge CLK) if (CE) r <= { r[14:0], D }; + endgenerate + specify + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912 + $setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173); + $setup(D , negedge CLK &&& IS_CLK_INVERTED, 173); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 + $setup(CE, posedge CLK &&& !IS_CLK_INVERTED, 109); + $setup(CE, negedge CLK &&& IS_CLK_INVERTED, 109); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905 + if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : D)) = 1472; + if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : D)) = 1472; + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904 + if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q15 : 1'bx)) = 1114; + if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q15 : 1'bx)) = 1114; + (A0 => Q) = 631; + (A1 => Q) = 472; + (A2 => Q) = 407; + (A3 => Q) = 238; + endspecify +endmodule + +(* abc9_box, lib_whitebox *) +module SRLC32E ( + output Q, + output Q31, + input [4:0] A, + input CE, + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK, + input D +); + parameter [31:0] INIT = 32'h00000000; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + + reg [31:0] r = INIT; + assign Q31 = r[31]; + assign Q = r[A]; + generate + if (IS_CLK_INVERTED) begin + always @(negedge CLK) if (CE) r <= { r[30:0], D }; + end + else + always @(posedge CLK) if (CE) r <= { r[30:0], D }; + endgenerate + specify + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912 + $setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173); + $setup(D , negedge CLK &&& IS_CLK_INVERTED, 173); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 + $setup(CE, posedge CLK &&& !IS_CLK_INVERTED, 109); + $setup(CE, negedge CLK &&& IS_CLK_INVERTED, 109); + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905 + if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : 1'bx)) = 1472; + if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : 1'bx)) = 1472; + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904 + if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q31 : 1'bx)) = 1114; + if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q31 : 1'bx)) = 1114; + (A[0] => Q) = 642; + (A[1] => Q) = 631; + (A[2] => Q) = 472; + (A[3] => Q) = 407; + (A[4] => Q) = 238; + endspecify +endmodule + +module CFGLUT5 ( + output CDO, + output O5, + output O6, + input I4, + input I3, + input I2, + input I1, + input I0, + input CDI, + input CE, + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK +); + parameter [31:0] INIT = 32'h00000000; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + wire clk = CLK ^ IS_CLK_INVERTED; + reg [31:0] r = INIT; + assign CDO = r[31]; + assign O5 = r[{1'b0, I3, I2, I1, I0}]; + assign O6 = r[{I4, I3, I2, I1, I0}]; + always @(posedge clk) if (CE) r <= {r[30:0], CDI}; +endmodule + +// DSP + +// Virtex 2, Virtex 2 Pro, Spartan 3. + +// Asynchronous mode. + +module MULT18X18 ( + input signed [17:0] A, + input signed [17:0] B, + output signed [35:0] P +); + +assign P = A * B; + +endmodule + +// Synchronous mode. + +module MULT18X18S ( + input signed [17:0] A, + input signed [17:0] B, + output reg signed [35:0] P, + (* clkbuf_sink *) + input C, + input CE, + input R +); + +always @(posedge C) + if (R) + P <= 0; + else if (CE) + P <= A * B; + +endmodule + +// Spartan 3E, Spartan 3A. + +module MULT18X18SIO ( + input signed [17:0] A, + input signed [17:0] B, + output signed [35:0] P, + (* clkbuf_sink *) + input CLK, + input CEA, + input CEB, + input CEP, + input RSTA, + input RSTB, + input RSTP, + input signed [17:0] BCIN, + output signed [17:0] BCOUT +); + +parameter integer AREG = 1; +parameter integer BREG = 1; +parameter B_INPUT = "DIRECT"; +parameter integer PREG = 1; + +// The multiplier. +wire signed [35:0] P_MULT; +wire signed [17:0] A_MULT; +wire signed [17:0] B_MULT; +assign P_MULT = A_MULT * B_MULT; + +// The cascade output. +assign BCOUT = B_MULT; + +// The B input multiplexer. +wire signed [17:0] B_MUX; +assign B_MUX = (B_INPUT == "DIRECT") ? B : BCIN; + +// The registers. +reg signed [17:0] A_REG; +reg signed [17:0] B_REG; +reg signed [35:0] P_REG; + +initial begin + A_REG = 0; + B_REG = 0; + P_REG = 0; +end + +always @(posedge CLK) begin + if (RSTA) + A_REG <= 0; + else if (CEA) + A_REG <= A; + + if (RSTB) + B_REG <= 0; + else if (CEB) + B_REG <= B_MUX; + + if (RSTP) + P_REG <= 0; + else if (CEP) + P_REG <= P_MULT; +end + +// The register enables. +assign A_MULT = (AREG == 1) ? A_REG : A; +assign B_MULT = (BREG == 1) ? B_REG : B_MUX; +assign P = (PREG == 1) ? P_REG : P_MULT; + +endmodule + +// Spartan 3A DSP. + +module DSP48A ( + input signed [17:0] A, + input signed [17:0] B, + input signed [47:0] C, + input signed [17:0] D, + input signed [47:0] PCIN, + input CARRYIN, + input [7:0] OPMODE, + output signed [47:0] P, + output signed [17:0] BCOUT, + output signed [47:0] PCOUT, + output CARRYOUT, + (* clkbuf_sink *) + input CLK, + input CEA, + input CEB, + input CEC, + input CED, + input CEM, + input CECARRYIN, + input CEOPMODE, + input CEP, + input RSTA, + input RSTB, + input RSTC, + input RSTD, + input RSTM, + input RSTCARRYIN, + input RSTOPMODE, + input RSTP +); + +parameter integer A0REG = 0; +parameter integer A1REG = 1; +parameter integer B0REG = 0; +parameter integer B1REG = 1; +parameter integer CREG = 1; +parameter integer DREG = 1; +parameter integer MREG = 1; +parameter integer CARRYINREG = 1; +parameter integer OPMODEREG = 1; +parameter integer PREG = 1; +parameter CARRYINSEL = "CARRYIN"; +parameter RSTTYPE = "SYNC"; + +// This is a strict subset of Spartan 6 -- reuse its model. + +/* verilator lint_off PINMISSING */ +DSP48A1 #( + .A0REG(A0REG), + .A1REG(A1REG), + .B0REG(B0REG), + .B1REG(B1REG), + .CREG(CREG), + .DREG(DREG), + .MREG(MREG), + .CARRYINREG(CARRYINREG), + .CARRYOUTREG(0), + .OPMODEREG(OPMODEREG), + .PREG(PREG), + .CARRYINSEL(CARRYINSEL), + .RSTTYPE(RSTTYPE) +) upgrade ( + .A(A), + .B(B), + .C(C), + .D(D), + .PCIN(PCIN), + .CARRYIN(CARRYIN), + .OPMODE(OPMODE), + // M unconnected + .P(P), + .BCOUT(BCOUT), + .PCOUT(PCOUT), + .CARRYOUT(CARRYOUT), + // CARRYOUTF unconnected + .CLK(CLK), + .CEA(CEA), + .CEB(CEB), + .CEC(CEC), + .CED(CED), + .CEM(CEM), + .CECARRYIN(CECARRYIN), + .CEOPMODE(CEOPMODE), + .CEP(CEP), + .RSTA(RSTA), + .RSTB(RSTB), + .RSTC(RSTC), + .RSTD(RSTD), + .RSTM(RSTM), + .RSTCARRYIN(RSTCARRYIN), + .RSTOPMODE(RSTOPMODE), + .RSTP(RSTP) +); +/* verilator lint_on PINMISSING */ + +endmodule + +// Spartan 6. + +module DSP48A1 ( + input signed [17:0] A, + input signed [17:0] B, + input signed [47:0] C, + input signed [17:0] D, + input signed [47:0] PCIN, + input CARRYIN, + input [7:0] OPMODE, + output signed [35:0] M, + output signed [47:0] P, + output signed [17:0] BCOUT, + output signed [47:0] PCOUT, + output CARRYOUT, + output CARRYOUTF, + (* clkbuf_sink *) + input CLK, + input CEA, + input CEB, + input CEC, + input CED, + input CEM, + input CECARRYIN, + input CEOPMODE, + input CEP, + input RSTA, + input RSTB, + input RSTC, + input RSTD, + input RSTM, + input RSTCARRYIN, + input RSTOPMODE, + input RSTP +); + +parameter integer A0REG = 0; +parameter integer A1REG = 1; +parameter integer B0REG = 0; +parameter integer B1REG = 1; +parameter integer CREG = 1; +parameter integer DREG = 1; +parameter integer MREG = 1; +parameter integer CARRYINREG = 1; +parameter integer CARRYOUTREG = 1; +parameter integer OPMODEREG = 1; +parameter integer PREG = 1; +parameter CARRYINSEL = "OPMODE5"; +parameter RSTTYPE = "SYNC"; + +wire signed [35:0] M_MULT; +wire signed [47:0] P_IN; +wire signed [17:0] A0_OUT; +wire signed [17:0] B0_OUT; +wire signed [17:0] A1_OUT; +wire signed [17:0] B1_OUT; +wire signed [17:0] B1_IN; +wire signed [47:0] C_OUT; +wire signed [17:0] D_OUT; +wire signed [7:0] OPMODE_OUT; +wire CARRYIN_OUT; +wire CARRYOUT_IN; +wire CARRYIN_IN; +reg signed [47:0] XMUX; +reg signed [47:0] ZMUX; + +// The registers. +reg signed [17:0] A0_REG; +reg signed [17:0] A1_REG; +reg signed [17:0] B0_REG; +reg signed [17:0] B1_REG; +reg signed [47:0] C_REG; +reg signed [17:0] D_REG; +reg signed [35:0] M_REG; +reg signed [47:0] P_REG; +reg [7:0] OPMODE_REG; +reg CARRYIN_REG; +reg CARRYOUT_REG; + +initial begin + A0_REG = 0; + A1_REG = 0; + B0_REG = 0; + B1_REG = 0; + C_REG = 0; + D_REG = 0; + M_REG = 0; + P_REG = 0; + OPMODE_REG = 0; + CARRYIN_REG = 0; + CARRYOUT_REG = 0; +end + +generate + +if (RSTTYPE == "SYNC") begin + always @(posedge CLK) begin + if (RSTA) begin + A0_REG <= 0; + A1_REG <= 0; + end else if (CEA) begin + A0_REG <= A; + A1_REG <= A0_OUT; + end + end + + always @(posedge CLK) begin + if (RSTB) begin + B0_REG <= 0; + B1_REG <= 0; + end else if (CEB) begin + B0_REG <= B; + B1_REG <= B1_IN; + end + end + + always @(posedge CLK) begin + if (RSTC) begin + C_REG <= 0; + end else if (CEC) begin + C_REG <= C; + end + end + + always @(posedge CLK) begin + if (RSTD) begin + D_REG <= 0; + end else if (CED) begin + D_REG <= D; + end + end + + always @(posedge CLK) begin + if (RSTM) begin + M_REG <= 0; + end else if (CEM) begin + M_REG <= M_MULT; + end + end + + always @(posedge CLK) begin + if (RSTP) begin + P_REG <= 0; + end else if (CEP) begin + P_REG <= P_IN; + end + end + + always @(posedge CLK) begin + if (RSTOPMODE) begin + OPMODE_REG <= 0; + end else if (CEOPMODE) begin + OPMODE_REG <= OPMODE; + end + end + + always @(posedge CLK) begin + if (RSTCARRYIN) begin + CARRYIN_REG <= 0; + CARRYOUT_REG <= 0; + end else if (CECARRYIN) begin + CARRYIN_REG <= CARRYIN_IN; + CARRYOUT_REG <= CARRYOUT_IN; + end + end +end else begin + always @(posedge CLK, posedge RSTA) begin + if (RSTA) begin + A0_REG <= 0; + A1_REG <= 0; + end else if (CEA) begin + A0_REG <= A; + A1_REG <= A0_OUT; + end + end + + always @(posedge CLK, posedge RSTB) begin + if (RSTB) begin + B0_REG <= 0; + B1_REG <= 0; + end else if (CEB) begin + B0_REG <= B; + B1_REG <= B1_IN; + end + end + + always @(posedge CLK, posedge RSTC) begin + if (RSTC) begin + C_REG <= 0; + end else if (CEC) begin + C_REG <= C; + end + end + + always @(posedge CLK, posedge RSTD) begin + if (RSTD) begin + D_REG <= 0; + end else if (CED) begin + D_REG <= D; + end + end + + always @(posedge CLK, posedge RSTM) begin + if (RSTM) begin + M_REG <= 0; + end else if (CEM) begin + M_REG <= M_MULT; + end + end + + always @(posedge CLK, posedge RSTP) begin + if (RSTP) begin + P_REG <= 0; + end else if (CEP) begin + P_REG <= P_IN; + end + end + + always @(posedge CLK, posedge RSTOPMODE) begin + if (RSTOPMODE) begin + OPMODE_REG <= 0; + end else if (CEOPMODE) begin + OPMODE_REG <= OPMODE; + end + end + + always @(posedge CLK, posedge RSTCARRYIN) begin + if (RSTCARRYIN) begin + CARRYIN_REG <= 0; + CARRYOUT_REG <= 0; + end else if (CECARRYIN) begin + CARRYIN_REG <= CARRYIN_IN; + CARRYOUT_REG <= CARRYOUT_IN; + end + end +end + +endgenerate + +// The register enables. +assign A0_OUT = (A0REG == 1) ? A0_REG : A; +assign A1_OUT = (A1REG == 1) ? A1_REG : A0_OUT; +assign B0_OUT = (B0REG == 1) ? B0_REG : B; +assign B1_OUT = (B1REG == 1) ? B1_REG : B1_IN; +assign C_OUT = (CREG == 1) ? C_REG : C; +assign D_OUT = (DREG == 1) ? D_REG : D; +assign M = (MREG == 1) ? M_REG : M_MULT; +assign P = (PREG == 1) ? P_REG : P_IN; +assign OPMODE_OUT = (OPMODEREG == 1) ? OPMODE_REG : OPMODE; +assign CARRYIN_OUT = (CARRYINREG == 1) ? CARRYIN_REG : CARRYIN_IN; +assign CARRYOUT = (CARRYOUTREG == 1) ? CARRYOUT_REG : CARRYOUT_IN; +assign CARRYOUTF = CARRYOUT; + +// The pre-adder. +wire signed [17:0] PREADDER; +assign B1_IN = OPMODE_OUT[4] ? PREADDER : B0_OUT; +assign PREADDER = OPMODE_OUT[6] ? D_OUT - B0_OUT : D_OUT + B0_OUT; + +// The multiplier. +assign M_MULT = A1_OUT * B1_OUT; + +// The carry in selection. +assign CARRYIN_IN = (CARRYINSEL == "OPMODE5") ? OPMODE_OUT[5] : CARRYIN; + +// The post-adder inputs. +always @* begin + case (OPMODE_OUT[1:0]) + 2'b00: XMUX <= 0; + 2'b01: XMUX <= M; + 2'b10: XMUX <= P; + 2'b11: XMUX <= {D_OUT[11:0], A1_OUT, B1_OUT}; + default: XMUX <= 48'hxxxxxxxxxxxx; + endcase +end + +always @* begin + case (OPMODE_OUT[3:2]) + 2'b00: ZMUX <= 0; + 2'b01: ZMUX <= PCIN; + 2'b10: ZMUX <= P; + 2'b11: ZMUX <= C_OUT; + default: ZMUX <= 48'hxxxxxxxxxxxx; + endcase +end + +// The post-adder. +wire signed [48:0] X_EXT; +wire signed [48:0] Z_EXT; +assign X_EXT = {1'b0, XMUX}; +assign Z_EXT = {1'b0, ZMUX}; +assign {CARRYOUT_IN, P_IN} = OPMODE_OUT[7] ? (Z_EXT - (X_EXT + CARRYIN_OUT)) : (Z_EXT + X_EXT + CARRYIN_OUT); + +// Cascade outputs. +assign BCOUT = B1_OUT; +assign PCOUT = P; + +endmodule + +module DSP48 ( + input signed [17:0] A, + input signed [17:0] B, + input signed [47:0] C, + input signed [17:0] BCIN, + input signed [47:0] PCIN, + input CARRYIN, + input [6:0] OPMODE, + input SUBTRACT, + input [1:0] CARRYINSEL, + output signed [47:0] P, + output signed [17:0] BCOUT, + output signed [47:0] PCOUT, + (* clkbuf_sink *) + input CLK, + input CEA, + input CEB, + input CEC, + input CEM, + input CECARRYIN, + input CECINSUB, + input CECTRL, + input CEP, + input RSTA, + input RSTB, + input RSTC, + input RSTM, + input RSTCARRYIN, + input RSTCTRL, + input RSTP +); + +parameter integer AREG = 1; +parameter integer BREG = 1; +parameter integer CREG = 1; +parameter integer MREG = 1; +parameter integer PREG = 1; +parameter integer CARRYINREG = 1; +parameter integer CARRYINSELREG = 1; +parameter integer OPMODEREG = 1; +parameter integer SUBTRACTREG = 1; +parameter B_INPUT = "DIRECT"; +parameter LEGACY_MODE = "MULT18X18S"; + +wire signed [17:0] A_OUT; +wire signed [17:0] B_OUT; +wire signed [47:0] C_OUT; +wire signed [35:0] M_MULT; +wire signed [35:0] M_OUT; +wire signed [47:0] P_IN; +wire [6:0] OPMODE_OUT; +wire [1:0] CARRYINSEL_OUT; +wire CARRYIN_OUT; +wire SUBTRACT_OUT; +reg INT_CARRYIN_XY; +reg INT_CARRYIN_Z; +reg signed [47:0] XMUX; +reg signed [47:0] YMUX; +wire signed [47:0] XYMUX; +reg signed [47:0] ZMUX; +reg CIN; + +// The B input multiplexer. +wire signed [17:0] B_MUX; +assign B_MUX = (B_INPUT == "DIRECT") ? B : BCIN; + +// The cascade output. +assign BCOUT = B_OUT; +assign PCOUT = P; + +// The registers. +reg signed [17:0] A0_REG; +reg signed [17:0] A1_REG; +reg signed [17:0] B0_REG; +reg signed [17:0] B1_REG; +reg signed [47:0] C_REG; +reg signed [35:0] M_REG; +reg signed [47:0] P_REG; +reg [6:0] OPMODE_REG; +reg [1:0] CARRYINSEL_REG; +reg SUBTRACT_REG; +reg CARRYIN_REG; +reg INT_CARRYIN_XY_REG; + +initial begin + A0_REG = 0; + A1_REG = 0; + B0_REG = 0; + B1_REG = 0; + C_REG = 0; + M_REG = 0; + P_REG = 0; + OPMODE_REG = 0; + CARRYINSEL_REG = 0; + SUBTRACT_REG = 0; + CARRYIN_REG = 0; + INT_CARRYIN_XY_REG = 0; +end + +always @(posedge CLK) begin + if (RSTA) begin + A0_REG <= 0; + A1_REG <= 0; + end else if (CEA) begin + A0_REG <= A; + A1_REG <= A0_REG; + end + if (RSTB) begin + B0_REG <= 0; + B1_REG <= 0; + end else if (CEB) begin + B0_REG <= B_MUX; + B1_REG <= B0_REG; + end + if (RSTC) begin + C_REG <= 0; + end else if (CEC) begin + C_REG <= C; + end + if (RSTM) begin + M_REG <= 0; + end else if (CEM) begin + M_REG <= M_MULT; + end + if (RSTP) begin + P_REG <= 0; + end else if (CEP) begin + P_REG <= P_IN; + end + if (RSTCTRL) begin + OPMODE_REG <= 0; + CARRYINSEL_REG <= 0; + SUBTRACT_REG <= 0; + end else begin + if (CECTRL) begin + OPMODE_REG <= OPMODE; + CARRYINSEL_REG <= CARRYINSEL; + end + if (CECINSUB) + SUBTRACT_REG <= SUBTRACT; + end + if (RSTCARRYIN) begin + CARRYIN_REG <= 0; + INT_CARRYIN_XY_REG <= 0; + end else begin + if (CECINSUB) + CARRYIN_REG <= CARRYIN; + if (CECARRYIN) + INT_CARRYIN_XY_REG <= INT_CARRYIN_XY; + end +end + +// The register enables. +assign A_OUT = (AREG == 2) ? A1_REG : (AREG == 1) ? A0_REG : A; +assign B_OUT = (BREG == 2) ? B1_REG : (BREG == 1) ? B0_REG : B_MUX; +assign C_OUT = (CREG == 1) ? C_REG : C; +assign M_OUT = (MREG == 1) ? M_REG : M_MULT; +assign P = (PREG == 1) ? P_REG : P_IN; +assign OPMODE_OUT = (OPMODEREG == 1) ? OPMODE_REG : OPMODE; +assign SUBTRACT_OUT = (SUBTRACTREG == 1) ? SUBTRACT_REG : SUBTRACT; +assign CARRYINSEL_OUT = (CARRYINSELREG == 1) ? CARRYINSEL_REG : CARRYINSEL; +assign CARRYIN_OUT = (CARRYINREG == 1) ? CARRYIN_REG : CARRYIN; + +// The multiplier. +assign M_MULT = A_OUT * B_OUT; + +// The post-adder inputs. +always @* begin + case (OPMODE_OUT[1:0]) + 2'b00: XMUX <= 0; + 2'b10: XMUX <= P; + 2'b11: XMUX <= {{12{A_OUT[17]}}, A_OUT, B_OUT}; + default: XMUX <= 48'hxxxxxxxxxxxx; + endcase + case (OPMODE_OUT[1:0]) + 2'b01: INT_CARRYIN_XY <= A_OUT[17] ~^ B_OUT[17]; + 2'b11: INT_CARRYIN_XY <= ~A_OUT[17]; + // TODO: not tested in hardware. + default: INT_CARRYIN_XY <= A_OUT[17] ~^ B_OUT[17]; + endcase +end + +always @* begin + case (OPMODE_OUT[3:2]) + 2'b00: YMUX <= 0; + 2'b11: YMUX <= C_OUT; + default: YMUX <= 48'hxxxxxxxxxxxx; + endcase +end + +assign XYMUX = (OPMODE_OUT[3:0] == 4'b0101) ? M_OUT : (XMUX + YMUX); + +always @* begin + case (OPMODE_OUT[6:4]) + 3'b000: ZMUX <= 0; + 3'b001: ZMUX <= PCIN; + 3'b010: ZMUX <= P; + 3'b011: ZMUX <= C_OUT; + 3'b101: ZMUX <= {{17{PCIN[47]}}, PCIN[47:17]}; + 3'b110: ZMUX <= {{17{P[47]}}, P[47:17]}; + default: ZMUX <= 48'hxxxxxxxxxxxx; + endcase + // TODO: check how all this works on actual hw. + if (OPMODE_OUT[1:0] == 2'b10) + INT_CARRYIN_Z <= ~P[47]; + else + case (OPMODE_OUT[6:4]) + 3'b001: INT_CARRYIN_Z <= ~PCIN[47]; + 3'b010: INT_CARRYIN_Z <= ~P[47]; + 3'b101: INT_CARRYIN_Z <= ~PCIN[47]; + 3'b110: INT_CARRYIN_Z <= ~P[47]; + default: INT_CARRYIN_Z <= 1'bx; + endcase +end + +always @* begin + case (CARRYINSEL_OUT) + 2'b00: CIN <= CARRYIN_OUT; + 2'b01: CIN <= INT_CARRYIN_Z; + 2'b10: CIN <= INT_CARRYIN_XY; + 2'b11: CIN <= INT_CARRYIN_XY_REG; + default: CIN <= 1'bx; + endcase +end + +// The post-adder. +assign P_IN = SUBTRACT_OUT ? (ZMUX - (XYMUX + CIN)) : (ZMUX + XYMUX + CIN); + +endmodule + +// TODO: DSP48E (Virtex 5). + +// Virtex 6, Series 7. + +`ifdef YOSYS +(* abc9_box=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG) +`ifdef ALLOW_WHITEBOX_DSP48E1 + // Do not make DSP48E1 a whitebox for ABC9 even if fully combinatorial, since it is a big complex block + , lib_whitebox=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG || INMODEREG || OPMODEREG || ALUMODEREG || CARRYINREG || CARRYINSELREG) +`endif +*) +`endif +module DSP48E1 ( + output [29:0] ACOUT, + output [17:0] BCOUT, + output reg CARRYCASCOUT, + output reg [3:0] CARRYOUT, + output reg MULTSIGNOUT, + output OVERFLOW, + output reg signed [47:0] P, + output reg PATTERNBDETECT, + output reg PATTERNDETECT, + output [47:0] PCOUT, + output UNDERFLOW, + input signed [29:0] A, + input [29:0] ACIN, + input [3:0] ALUMODE, + input signed [17:0] B, + input [17:0] BCIN, + input [47:0] C, + input CARRYCASCIN, + input CARRYIN, + input [2:0] CARRYINSEL, + input CEA1, + input CEA2, + input CEAD, + input CEALUMODE, + input CEB1, + input CEB2, + input CEC, + input CECARRYIN, + input CECTRL, + input CED, + input CEINMODE, + input CEM, + input CEP, + (* clkbuf_sink *) input CLK, + input [24:0] D, + input [4:0] INMODE, + input MULTSIGNIN, + input [6:0] OPMODE, + input [47:0] PCIN, + input RSTA, + input RSTALLCARRYIN, + input RSTALUMODE, + input RSTB, + input RSTC, + input RSTCTRL, + input RSTD, + input RSTINMODE, + input RSTM, + input RSTP +); + parameter integer ACASCREG = 1; + parameter integer ADREG = 1; + parameter integer ALUMODEREG = 1; + parameter integer AREG = 1; + parameter AUTORESET_PATDET = "NO_RESET"; + parameter A_INPUT = "DIRECT"; + parameter integer BCASCREG = 1; + parameter integer BREG = 1; + parameter B_INPUT = "DIRECT"; + parameter integer CARRYINREG = 1; + parameter integer CARRYINSELREG = 1; + parameter integer CREG = 1; + parameter integer DREG = 1; + parameter integer INMODEREG = 1; + parameter integer MREG = 1; + parameter integer OPMODEREG = 1; + parameter integer PREG = 1; + parameter SEL_MASK = "MASK"; + parameter SEL_PATTERN = "PATTERN"; + parameter USE_DPORT = "FALSE"; + parameter USE_MULT = "MULTIPLY"; + parameter USE_PATTERN_DETECT = "NO_PATDET"; + parameter USE_SIMD = "ONE48"; + parameter [47:0] MASK = 48'h3FFFFFFFFFFF; + parameter [47:0] PATTERN = 48'h000000000000; + parameter [3:0] IS_ALUMODE_INVERTED = 4'b0; + parameter [0:0] IS_CARRYIN_INVERTED = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [4:0] IS_INMODE_INVERTED = 5'b0; + parameter [6:0] IS_OPMODE_INVERTED = 7'b0; + +`ifdef YOSYS + function integer \A.required ; + begin + if (AREG != 0) \A.required = 254; + else if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin + if (MREG != 0) \A.required = 1416; + else if (PREG != 0) \A.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 3030 : 2739) ; + end + else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin + // Worst-case from ADREG and MREG + if (MREG != 0) \A.required = 2400; + else if (ADREG != 0) \A.required = 1283; + else if (PREG != 0) \A.required = 3723; + else if (PREG != 0) \A.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 4014 : 3723) ; + end + else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin + if (PREG != 0) \A.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1730 : 1441) ; + end + end + endfunction + function integer \B.required ; + begin + if (BREG != 0) \B.required = 324; + else if (MREG != 0) \B.required = 1285; + else if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin + if (PREG != 0) \B.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 2898 : 2608) ; + end + else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin + if (PREG != 0) \B.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 2898 : 2608) ; + end + else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin + if (PREG != 0) \B.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1718 : 1428) ; + end + end + endfunction + function integer \C.required ; + begin + if (CREG != 0) \C.required = 168; + else if (PREG != 0) \C.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1534 : 1244) ; + end + endfunction + function integer \D.required ; + begin + if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin + end + else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin + if (DREG != 0) \D.required = 248; + else if (ADREG != 0) \D.required = 1195; + else if (MREG != 0) \D.required = 2310; + else if (PREG != 0) \D.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 3925 : 3635) ; + end + else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin + end + end + endfunction + function integer \P.arrival ; + begin + if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin + if (PREG != 0) \P.arrival = 329; + // Worst-case from CREG and MREG + else if (CREG != 0) \P.arrival = 1687; + else if (MREG != 0) \P.arrival = 1671; + // Worst-case from AREG and BREG + else if (AREG != 0) \P.arrival = 2952; + else if (BREG != 0) \P.arrival = 2813; + end + else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin + if (PREG != 0) \P.arrival = 329; + // Worst-case from CREG and MREG + else if (CREG != 0) \P.arrival = 1687; + else if (MREG != 0) \P.arrival = 1671; + // Worst-case from AREG, ADREG, BREG, DREG + else if (AREG != 0) \P.arrival = 3935; + else if (DREG != 0) \P.arrival = 3908; + else if (ADREG != 0) \P.arrival = 2958; + else if (BREG != 0) \P.arrival = 2813; + end + else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin + if (PREG != 0) \P.arrival = 329; + // Worst-case from AREG, BREG, CREG + else if (CREG != 0) \P.arrival = 1687; + else if (AREG != 0) \P.arrival = 1632; + else if (BREG != 0) \P.arrival = 1616; + end + end + endfunction + function integer \PCOUT.arrival ; + begin + if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin + if (PREG != 0) \PCOUT.arrival = 435; + // Worst-case from CREG and MREG + else if (CREG != 0) \PCOUT.arrival = 1835; + else if (MREG != 0) \PCOUT.arrival = 1819; + // Worst-case from AREG and BREG + else if (AREG != 0) \PCOUT.arrival = 3098; + else if (BREG != 0) \PCOUT.arrival = 2960; + end + else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin + if (PREG != 0) \PCOUT.arrival = 435; + // Worst-case from CREG and MREG + else if (CREG != 0) \PCOUT.arrival = 1835; + else if (MREG != 0) \PCOUT.arrival = 1819; + // Worst-case from AREG, ADREG, BREG, DREG + else if (AREG != 0) \PCOUT.arrival = 4083; + else if (DREG != 0) \PCOUT.arrival = 4056; + else if (BREG != 0) \PCOUT.arrival = 2960; + else if (ADREG != 0) \PCOUT.arrival = 2859; + end + else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin + if (PREG != 0) \PCOUT.arrival = 435; + // Worst-case from AREG, BREG, CREG + else if (CREG != 0) \PCOUT.arrival = 1835; + else if (AREG != 0) \PCOUT.arrival = 1780; + else if (BREG != 0) \PCOUT.arrival = 1765; + end + end + endfunction + function integer \A.P.comb ; + begin + if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \A.P.comb = 2823; + else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.P.comb = 3806; + else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \A.P.comb = 1523; + end + endfunction + function integer \A.PCOUT.comb ; + begin + if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \A.PCOUT.comb = 2970; + else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.PCOUT.comb = 3954; + else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \A.PCOUT.comb = 1671; + end + endfunction + function integer \B.P.comb ; + begin + if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \B.P.comb = 2690; + else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.P.comb = 2690; + else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \B.P.comb = 1509; + end + endfunction + function integer \B.PCOUT.comb ; + begin + if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \B.PCOUT.comb = 2838; + else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.PCOUT.comb = 2838; + else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \B.PCOUT.comb = 1658; + end + endfunction + function integer \C.P.comb ; + begin + if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \C.P.comb = 1325; + else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.P.comb = 1325; + else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \C.P.comb = 1325; + end + endfunction + function integer \C.PCOUT.comb ; + begin + if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \C.PCOUT.comb = 1474; + else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.PCOUT.comb = 1474; + else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \C.PCOUT.comb = 1474; + end + endfunction + function integer \D.P.comb ; + begin + if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \D.P.comb = 3717; + end + endfunction + function integer \D.PCOUT.comb ; + begin + if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \D.PCOUT.comb = 3700; + end + endfunction + + generate + if (PREG == 0 && MREG == 0 && AREG == 0 && ADREG == 0) + specify + (A *> P) = \A.P.comb (); + (A *> PCOUT) = \A.PCOUT.comb (); + endspecify + else + specify + $setup(A, posedge CLK &&& !IS_CLK_INVERTED, \A.required () ); + $setup(A, negedge CLK &&& IS_CLK_INVERTED, \A.required () ); + endspecify + + if (PREG == 0 && MREG == 0 && BREG == 0) + specify + (B *> P) = \B.P.comb (); + (B *> PCOUT) = \B.PCOUT.comb (); + endspecify + else + specify + $setup(B, posedge CLK &&& !IS_CLK_INVERTED, \B.required () ); + $setup(B, negedge CLK &&& IS_CLK_INVERTED, \B.required () ); + endspecify + + if (PREG == 0 && CREG == 0) + specify + (C *> P) = \C.P.comb (); + (C *> PCOUT) = \C.PCOUT.comb (); + endspecify + else + specify + $setup(C, posedge CLK &&& !IS_CLK_INVERTED, \C.required () ); + $setup(C, negedge CLK &&& IS_CLK_INVERTED, \C.required () ); + endspecify + + if (PREG == 0 && MREG == 0 && ADREG == 0 && DREG == 0) + specify + (D *> P) = \D.P.comb (); + (D *> PCOUT) = \D.PCOUT.comb (); + endspecify + else + specify + $setup(D, posedge CLK &&& !IS_CLK_INVERTED, \D.required () ); + $setup(D, negedge CLK &&& IS_CLK_INVERTED, \D.required () ); + endspecify + + if (PREG == 0) + specify + (PCIN *> P) = 1107; + (PCIN *> PCOUT) = 1255; + endspecify + else + specify + $setup(PCIN, posedge CLK &&& !IS_CLK_INVERTED, USE_PATTERN_DETECT != "NO_PATDET" ? 1315 : 1025); + $setup(PCIN, negedge CLK &&& IS_CLK_INVERTED, USE_PATTERN_DETECT != "NO_PATDET" ? 1315 : 1025); + endspecify + + if (PREG || AREG || ADREG || BREG || CREG || DREG || MREG) + specify + if (!IS_CLK_INVERTED && CEP) (posedge CLK => (P : 48'bx)) = \P.arrival () ; + if ( IS_CLK_INVERTED && CEP) (negedge CLK => (P : 48'bx)) = \P.arrival () ; + if (!IS_CLK_INVERTED && CEP) (posedge CLK => (PCOUT : 48'bx)) = \PCOUT.arrival () ; + if ( IS_CLK_INVERTED && CEP) (negedge CLK => (PCOUT : 48'bx)) = \PCOUT.arrival () ; + endspecify + endgenerate +`endif + + initial begin +`ifndef YOSYS + if (AUTORESET_PATDET != "NO_RESET") $fatal(1, "Unsupported AUTORESET_PATDET value"); + if (SEL_MASK != "MASK") $fatal(1, "Unsupported SEL_MASK value"); + if (SEL_PATTERN != "PATTERN") $fatal(1, "Unsupported SEL_PATTERN value"); + if (USE_SIMD != "ONE48" && USE_SIMD != "TWO24" && USE_SIMD != "FOUR12") $fatal(1, "Unsupported USE_SIMD value"); + if (IS_ALUMODE_INVERTED != 4'b0) $fatal(1, "Unsupported IS_ALUMODE_INVERTED value"); + if (IS_CARRYIN_INVERTED != 1'b0) $fatal(1, "Unsupported IS_CARRYIN_INVERTED value"); + if (IS_CLK_INVERTED != 1'b0) $fatal(1, "Unsupported IS_CLK_INVERTED value"); + if (IS_INMODE_INVERTED != 5'b0) $fatal(1, "Unsupported IS_INMODE_INVERTED value"); + if (IS_OPMODE_INVERTED != 7'b0) $fatal(1, "Unsupported IS_OPMODE_INVERTED value"); +`endif + end + + wire signed [29:0] A_muxed; + wire signed [17:0] B_muxed; + + generate + if (A_INPUT == "CASCADE") assign A_muxed = ACIN; + else assign A_muxed = A; + + if (B_INPUT == "CASCADE") assign B_muxed = BCIN; + else assign B_muxed = B; + endgenerate + + reg signed [29:0] Ar1, Ar2; + reg signed [24:0] Dr; + reg signed [17:0] Br1, Br2; + reg signed [47:0] Cr; + reg [4:0] INMODEr; + reg [6:0] OPMODEr; + reg [3:0] ALUMODEr; + reg [2:0] CARRYINSELr; + + generate + // Configurable A register + if (AREG == 2) begin + initial Ar1 = 30'b0; + initial Ar2 = 30'b0; + always @(posedge CLK) + if (RSTA) begin + Ar1 <= 30'b0; + Ar2 <= 30'b0; + end else begin + if (CEA1) Ar1 <= A_muxed; + if (CEA2) Ar2 <= Ar1; + end + end else if (AREG == 1) begin + //initial Ar1 = 30'b0; + initial Ar2 = 30'b0; + always @(posedge CLK) + if (RSTA) begin + Ar1 <= 30'b0; + Ar2 <= 30'b0; + end else begin + if (CEA1) Ar1 <= A_muxed; + if (CEA2) Ar2 <= A_muxed; + end + end else begin + always @* Ar1 <= A_muxed; + always @* Ar2 <= A_muxed; + end + + // Configurable B register + if (BREG == 2) begin + initial Br1 = 25'b0; + initial Br2 = 25'b0; + always @(posedge CLK) + if (RSTB) begin + Br1 <= 18'b0; + Br2 <= 18'b0; + end else begin + if (CEB1) Br1 <= B_muxed; + if (CEB2) Br2 <= Br1; + end + end else if (BREG == 1) begin + //initial Br1 = 18'b0; + initial Br2 = 18'b0; + always @(posedge CLK) + if (RSTB) begin + Br1 <= 18'b0; + Br2 <= 18'b0; + end else begin + if (CEB1) Br1 <= B_muxed; + if (CEB2) Br2 <= B_muxed; + end + end else begin + always @* Br1 <= B_muxed; + always @* Br2 <= B_muxed; + end + + // C and D registers + if (CREG == 1) initial Cr = 48'b0; + if (CREG == 1) begin always @(posedge CLK) if (RSTC) Cr <= 48'b0; else if (CEC) Cr <= C; end + else always @* Cr <= C; + + if (DREG == 1) initial Dr = 25'b0; + if (DREG == 1) begin always @(posedge CLK) if (RSTD) Dr <= 25'b0; else if (CED) Dr <= D; end + else always @* Dr <= D; + + // Control registers + if (INMODEREG == 1) initial INMODEr = 5'b0; + if (INMODEREG == 1) begin always @(posedge CLK) if (RSTINMODE) INMODEr <= 5'b0; else if (CEINMODE) INMODEr <= INMODE; end + else always @* INMODEr <= INMODE; + if (OPMODEREG == 1) initial OPMODEr = 7'b0; + if (OPMODEREG == 1) begin always @(posedge CLK) if (RSTCTRL) OPMODEr <= 7'b0; else if (CECTRL) OPMODEr <= OPMODE; end + else always @* OPMODEr <= OPMODE; + if (ALUMODEREG == 1) initial ALUMODEr = 4'b0; + if (ALUMODEREG == 1) begin always @(posedge CLK) if (RSTALUMODE) ALUMODEr <= 4'b0; else if (CEALUMODE) ALUMODEr <= ALUMODE; end + else always @* ALUMODEr <= ALUMODE; + if (CARRYINSELREG == 1) initial CARRYINSELr = 3'b0; + if (CARRYINSELREG == 1) begin always @(posedge CLK) if (RSTCTRL) CARRYINSELr <= 3'b0; else if (CECTRL) CARRYINSELr <= CARRYINSEL; end + else always @* CARRYINSELr <= CARRYINSEL; + endgenerate + + // A and B cascade + generate + if (ACASCREG == 1 && AREG == 2) assign ACOUT = Ar1; + else assign ACOUT = Ar2; + if (BCASCREG == 1 && BREG == 2) assign BCOUT = Br1; + else assign BCOUT = Br2; + endgenerate + + // A/D input selection and pre-adder + wire signed [24:0] Ar12_muxed = INMODEr[0] ? Ar1 : Ar2; + wire signed [24:0] Ar12_gated = INMODEr[1] ? 25'b0 : Ar12_muxed; + wire signed [24:0] Dr_gated = INMODEr[2] ? Dr : 25'b0; + wire signed [24:0] AD_result = INMODEr[3] ? (Dr_gated - Ar12_gated) : (Dr_gated + Ar12_gated); + reg signed [24:0] ADr; + + generate + if (ADREG == 1) initial ADr = 25'b0; + if (ADREG == 1) begin always @(posedge CLK) if (RSTD) ADr <= 25'b0; else if (CEAD) ADr <= AD_result; end + else always @* ADr <= AD_result; + endgenerate + + // 25x18 multiplier + wire signed [24:0] A_MULT; + wire signed [17:0] B_MULT = INMODEr[4] ? Br1 : Br2; + generate + if (USE_DPORT == "TRUE") assign A_MULT = ADr; + else assign A_MULT = Ar12_gated; + endgenerate + + wire signed [42:0] M = A_MULT * B_MULT; + wire signed [42:0] Mx = (CARRYINSEL == 3'b010) ? 43'bx : M; + reg signed [42:0] Mr = 43'b0; + + // Multiplier result register + generate + if (MREG == 1) begin always @(posedge CLK) if (RSTM) Mr <= 43'b0; else if (CEM) Mr <= Mx; end + else always @* Mr <= Mx; + endgenerate + + wire signed [42:0] Mrx = (CARRYINSELr == 3'b010) ? 43'bx : Mr; + + // X, Y and Z ALU inputs + reg signed [47:0] X, Y, Z; + + always @* begin + // X multiplexer + case (OPMODEr[1:0]) + 2'b00: X = 48'b0; + 2'b01: begin X = $signed(Mrx); +`ifndef YOSYS + if (OPMODEr[3:2] != 2'b01) $fatal(1, "OPMODEr[3:2] must be 2'b01 when OPMODEr[1:0] is 2'b01"); +`endif + end + 2'b10: + if (PREG == 1) + X = P; + else begin + X = 48'bx; +`ifndef YOSYS + $fatal(1, "PREG must be 1 when OPMODEr[1:0] is 2'b10"); +`endif + end + 2'b11: X = $signed({Ar2, Br2}); + default: X = 48'bx; + endcase + + // Y multiplexer + case (OPMODEr[3:2]) + 2'b00: Y = 48'b0; + 2'b01: begin Y = 48'b0; // FIXME: more accurate partial product modelling? +`ifndef YOSYS + if (OPMODEr[1:0] != 2'b01) $fatal(1, "OPMODEr[1:0] must be 2'b01 when OPMODEr[3:2] is 2'b01"); +`endif + end + 2'b10: Y = {48{1'b1}}; + 2'b11: Y = Cr; + default: Y = 48'bx; + endcase + + // Z multiplexer + case (OPMODEr[6:4]) + 3'b000: Z = 48'b0; + 3'b001: Z = PCIN; + 3'b010: + if (PREG == 1) + Z = P; + else begin + Z = 48'bx; +`ifndef YOSYS + $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b010"); +`endif + end + 3'b011: Z = Cr; + 3'b100: + if (PREG == 1 && OPMODEr[3:0] === 4'b1000) + Z = P; + else begin + Z = 48'bx; +`ifndef YOSYS + if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b100"); + if (OPMODEr[3:0] != 4'b1000) $fatal(1, "OPMODEr[3:0] must be 4'b1000 when OPMODEr[6:4] i0s 3'b100"); +`endif + end + 3'b101: Z = $signed(PCIN[47:17]); + 3'b110: + if (PREG == 1) + Z = $signed(P[47:17]); + else begin + Z = 48'bx; +`ifndef YOSYS + $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b110"); +`endif + end + default: Z = 48'bx; + endcase + end + + // Carry in + wire A24_xnor_B17d = A_MULT[24] ~^ B_MULT[17]; + reg CARRYINr, A24_xnor_B17; + generate + if (CARRYINREG == 1) initial CARRYINr = 1'b0; + if (CARRYINREG == 1) begin always @(posedge CLK) if (RSTALLCARRYIN) CARRYINr <= 1'b0; else if (CECARRYIN) CARRYINr <= CARRYIN; end + else always @* CARRYINr = CARRYIN; + + if (MREG == 1) initial A24_xnor_B17 = 1'b0; + if (MREG == 1) begin always @(posedge CLK) if (RSTALLCARRYIN) A24_xnor_B17 <= 1'b0; else if (CEM) A24_xnor_B17 <= A24_xnor_B17d; end + else always @* A24_xnor_B17 = A24_xnor_B17d; + endgenerate + + reg cin_muxed; + + always @(*) begin + case (CARRYINSELr) + 3'b000: cin_muxed = CARRYINr; + 3'b001: cin_muxed = ~PCIN[47]; + 3'b010: cin_muxed = CARRYCASCIN; + 3'b011: cin_muxed = PCIN[47]; + 3'b100: + if (PREG == 1) + cin_muxed = CARRYCASCOUT; + else begin + cin_muxed = 1'bx; +`ifndef YOSYS + $fatal(1, "PREG must be 1 when CARRYINSEL is 3'b100"); +`endif + end + 3'b101: + if (PREG == 1) + cin_muxed = ~P[47]; + else begin + cin_muxed = 1'bx; +`ifndef YOSYS + $fatal(1, "PREG must be 1 when CARRYINSEL is 3'b101"); +`endif + end + 3'b110: cin_muxed = A24_xnor_B17; + 3'b111: + if (PREG == 1) + cin_muxed = P[47]; + else begin + cin_muxed = 1'bx; +`ifndef YOSYS + $fatal(1, "PREG must be 1 when CARRYINSEL is 3'b111"); +`endif + end + default: cin_muxed = 1'bx; + endcase + end + + wire alu_cin = (ALUMODEr[3] || ALUMODEr[2]) ? 1'b0 : cin_muxed; + + // ALU core + wire [47:0] Z_muxinv = ALUMODEr[0] ? ~Z : Z; + wire [47:0] xor_xyz = X ^ Y ^ Z_muxinv; + wire [47:0] maj_xyz = (X & Y) | (X & Z_muxinv) | (Y & Z_muxinv); + + wire [47:0] xor_xyz_muxed = ALUMODEr[3] ? maj_xyz : xor_xyz; + wire [47:0] maj_xyz_gated = ALUMODEr[2] ? 48'b0 : maj_xyz; + + wire [48:0] maj_xyz_simd_gated; + wire [3:0] int_carry_in, int_carry_out, ext_carry_out; + wire [47:0] alu_sum; + assign int_carry_in[0] = 1'b0; + wire [3:0] carryout_reset; + + generate + if (USE_SIMD == "FOUR12") begin + assign maj_xyz_simd_gated = { + maj_xyz_gated[47:36], + 1'b0, maj_xyz_gated[34:24], + 1'b0, maj_xyz_gated[22:12], + 1'b0, maj_xyz_gated[10:0], + alu_cin + }; + assign int_carry_in[3:1] = 3'b000; + assign ext_carry_out = { + int_carry_out[3], + maj_xyz_gated[35] ^ int_carry_out[2], + maj_xyz_gated[23] ^ int_carry_out[1], + maj_xyz_gated[11] ^ int_carry_out[0] + }; + assign carryout_reset = 4'b0000; + end else if (USE_SIMD == "TWO24") begin + assign maj_xyz_simd_gated = { + maj_xyz_gated[47:24], + 1'b0, maj_xyz_gated[22:0], + alu_cin + }; + assign int_carry_in[3:1] = {int_carry_out[2], 1'b0, int_carry_out[0]}; + assign ext_carry_out = { + int_carry_out[3], + 1'bx, + maj_xyz_gated[23] ^ int_carry_out[1], + 1'bx + }; + assign carryout_reset = 4'b0x0x; + end else begin + assign maj_xyz_simd_gated = {maj_xyz_gated, alu_cin}; + assign int_carry_in[3:1] = int_carry_out[2:0]; + assign ext_carry_out = { + int_carry_out[3], + 3'bxxx + }; + assign carryout_reset = 4'b0xxx; + end + + genvar i; + for (i = 0; i < 4; i = i + 1) + assign {int_carry_out[i], alu_sum[i*12 +: 12]} = {1'b0, maj_xyz_simd_gated[i*12 +: ((i == 3) ? 13 : 12)]} + + xor_xyz_muxed[i*12 +: 12] + int_carry_in[i]; + endgenerate + + wire signed [47:0] Pd = ALUMODEr[1] ? ~alu_sum : alu_sum; + wire [3:0] CARRYOUTd = (OPMODEr[3:0] == 4'b0101 || ALUMODEr[3:2] != 2'b00) ? 4'bxxxx : + ((ALUMODEr[0] & ALUMODEr[1]) ? ~ext_carry_out : ext_carry_out); + wire CARRYCASCOUTd = ext_carry_out[3]; + wire MULTSIGNOUTd = Mrx[42]; + + generate + if (PREG == 1) begin + initial P = 48'b0; + initial CARRYOUT = carryout_reset; + initial CARRYCASCOUT = 1'b0; + initial MULTSIGNOUT = 1'b0; + always @(posedge CLK) + if (RSTP) begin + P <= 48'b0; + CARRYOUT <= carryout_reset; + CARRYCASCOUT <= 1'b0; + MULTSIGNOUT <= 1'b0; + end else if (CEP) begin + P <= Pd; + CARRYOUT <= CARRYOUTd; + CARRYCASCOUT <= CARRYCASCOUTd; + MULTSIGNOUT <= MULTSIGNOUTd; + end + end else begin + always @* begin + P = Pd; + CARRYOUT = CARRYOUTd; + CARRYCASCOUT = CARRYCASCOUTd; + MULTSIGNOUT = MULTSIGNOUTd; + end + end + endgenerate + + assign PCOUT = P; + + generate + wire PATTERNDETECTd, PATTERNBDETECTd; + + if (USE_PATTERN_DETECT == "PATDET") begin + // TODO: Support SEL_PATTERN != "PATTERN" and SEL_MASK != "MASK + assign PATTERNDETECTd = &(~(Pd ^ PATTERN) | MASK); + assign PATTERNBDETECTd = &((Pd ^ PATTERN) | MASK); + end else begin + assign PATTERNDETECTd = 1'b1; + assign PATTERNBDETECTd = 1'b1; + end + + if (PREG == 1) begin + reg PATTERNDETECTPAST, PATTERNBDETECTPAST; + initial PATTERNDETECT = 1'b0; + initial PATTERNBDETECT = 1'b0; + initial PATTERNDETECTPAST = 1'b0; + initial PATTERNBDETECTPAST = 1'b0; + always @(posedge CLK) + if (RSTP) begin + PATTERNDETECT <= 1'b0; + PATTERNBDETECT <= 1'b0; + PATTERNDETECTPAST <= 1'b0; + PATTERNBDETECTPAST <= 1'b0; + end else if (CEP) begin + PATTERNDETECT <= PATTERNDETECTd; + PATTERNBDETECT <= PATTERNBDETECTd; + PATTERNDETECTPAST <= PATTERNDETECT; + PATTERNBDETECTPAST <= PATTERNBDETECT; + end + assign OVERFLOW = &{PATTERNDETECTPAST, ~PATTERNBDETECT, ~PATTERNDETECT}; + assign UNDERFLOW = &{PATTERNBDETECTPAST, ~PATTERNBDETECT, ~PATTERNDETECT}; + end else begin + always @* begin + PATTERNDETECT = PATTERNDETECTd; + PATTERNBDETECT = PATTERNBDETECTd; + end + assign OVERFLOW = 1'bx, UNDERFLOW = 1'bx; + end + endgenerate + +endmodule + +// TODO: DSP48E2 (Ultrascale). + +// Block RAM + +module RAMB18E1 ( + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) + input CLKARDCLK, + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) + input CLKBWRCLK, + (* invertible_pin = "IS_ENARDEN_INVERTED" *) + input ENARDEN, + (* invertible_pin = "IS_ENBWREN_INVERTED" *) + input ENBWREN, + input REGCEAREGCE, + input REGCEB, + (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) + input RSTRAMARSTRAM, + (* invertible_pin = "IS_RSTRAMB_INVERTED" *) + input RSTRAMB, + (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) + input RSTREGARSTREG, + (* invertible_pin = "IS_RSTREGB_INVERTED" *) + input RSTREGB, + input [13:0] ADDRARDADDR, + input [13:0] ADDRBWRADDR, + input [15:0] DIADI, + input [15:0] DIBDI, + input [1:0] DIPADIP, + input [1:0] DIPBDIP, + input [1:0] WEA, + input [3:0] WEBWE, + output [15:0] DOADO, + output [15:0] DOBDO, + output [1:0] DOPADOP, + output [1:0] DOPBDOP +); + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_A = 18'h0; + parameter INIT_B = 18'h0; + parameter INIT_FILE = "NONE"; + parameter RAM_MODE = "TDP"; + parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE"; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter RSTREG_PRIORITY_A = "RSTREG"; + parameter RSTREG_PRIORITY_B = "RSTREG"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SIM_DEVICE = "VIRTEX6"; + parameter SRVAL_A = 18'h0; + parameter SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + parameter IS_CLKARDCLK_INVERTED = 1'b0; + parameter IS_CLKBWRCLK_INVERTED = 1'b0; + parameter IS_ENARDEN_INVERTED = 1'b0; + parameter IS_ENBWREN_INVERTED = 1'b0; + parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0; + parameter IS_RSTRAMB_INVERTED = 1'b0; + parameter IS_RSTREGARSTREG_INVERTED = 1'b0; + parameter IS_RSTREGB_INVERTED = 1'b0; + + specify + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L13 + $setup(ADDRARDADDR, posedge CLKARDCLK, 566); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L17 + $setup(ADDRBWRADDR, posedge CLKBWRCLK, 566); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L19 + $setup(WEA, posedge CLKARDCLK, 532); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L21 + $setup(WEBWE, posedge CLKBWRCLK, 532); + // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L29 + $setup(REGCEAREGCE, posedge CLKARDCLK, 360); + // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L31 + $setup(RSTREGARSTREG, posedge CLKARDCLK, 342); + // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L49 + $setup(REGCEB, posedge CLKBWRCLK, 360); + // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L59 + $setup(RSTREGB, posedge CLKBWRCLK, 342); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L123 + $setup(DIADI, posedge CLKARDCLK, 737); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L133 + $setup(DIBDI, posedge CLKBWRCLK, 737); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L125 + $setup(DIPADIP, posedge CLKARDCLK, 737); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L135 + $setup(DIPBDIP, posedge CLKBWRCLK, 737); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L143 + if (&DOA_REG) (posedge CLKARDCLK => (DOADO : 16'bx)) = 2454; + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L144 + if (&DOA_REG) (posedge CLKARDCLK => (DOPADOP : 2'bx)) = 2454; + // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L153 + if (|DOA_REG) (posedge CLKARDCLK => (DOADO : 16'bx)) = 882; + // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L154 + if (|DOA_REG) (posedge CLKARDCLK => (DOPADOP : 2'bx)) = 882; + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L163 + if (&DOB_REG) (posedge CLKBWRCLK => (DOBDO : 16'bx)) = 2454; + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L164 + if (&DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 2'bx)) = 2454; + // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L173 + if (|DOB_REG) (posedge CLKBWRCLK => (DOBDO : 16'bx)) = 882; + // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L174 + if (|DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 2'bx)) = 882; + endspecify +endmodule + +module RAMB36E1 ( + output CASCADEOUTA, + output CASCADEOUTB, + output [31:0] DOADO, + output [31:0] DOBDO, + output [3:0] DOPADOP, + output [3:0] DOPBDOP, + output [7:0] ECCPARITY, + output [8:0] RDADDRECC, + output SBITERR, + output DBITERR, + (* invertible_pin = "IS_ENARDEN_INVERTED" *) + input ENARDEN, + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) + input CLKARDCLK, + (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) + input RSTRAMARSTRAM, + (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) + input RSTREGARSTREG, + input CASCADEINA, + input REGCEAREGCE, + (* invertible_pin = "IS_ENBWREN_INVERTED" *) + input ENBWREN, + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) + input CLKBWRCLK, + (* invertible_pin = "IS_RSTRAMB_INVERTED" *) + input RSTRAMB, + (* invertible_pin = "IS_RSTREGB_INVERTED" *) + input RSTREGB, + input CASCADEINB, + input REGCEB, + input INJECTDBITERR, + input INJECTSBITERR, + input [15:0] ADDRARDADDR, + input [15:0] ADDRBWRADDR, + input [31:0] DIADI, + input [31:0] DIBDI, + input [3:0] DIPADIP, + input [3:0] DIPBDIP, + input [3:0] WEA, + input [7:0] WEBWE +); + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter EN_ECC_READ = "FALSE"; + parameter EN_ECC_WRITE = "FALSE"; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_A = 36'h0; + parameter INIT_B = 36'h0; + parameter INIT_FILE = "NONE"; + parameter RAM_EXTENSION_A = "NONE"; + parameter RAM_EXTENSION_B = "NONE"; + parameter RAM_MODE = "TDP"; + parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE"; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter RSTREG_PRIORITY_A = "RSTREG"; + parameter RSTREG_PRIORITY_B = "RSTREG"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SIM_DEVICE = "VIRTEX6"; + parameter SRVAL_A = 36'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + parameter IS_CLKARDCLK_INVERTED = 1'b0; + parameter IS_CLKBWRCLK_INVERTED = 1'b0; + parameter IS_ENARDEN_INVERTED = 1'b0; + parameter IS_ENBWREN_INVERTED = 1'b0; + parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0; + parameter IS_RSTRAMB_INVERTED = 1'b0; + parameter IS_RSTREGARSTREG_INVERTED = 1'b0; + parameter IS_RSTREGB_INVERTED = 1'b0; + + specify + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L13 + $setup(ADDRARDADDR, posedge CLKARDCLK, 566); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L17 + $setup(ADDRBWRADDR, posedge CLKBWRCLK, 566); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L19 + $setup(WEA, posedge CLKARDCLK, 532); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L21 + $setup(WEBWE, posedge CLKBWRCLK, 532); + // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L29 + $setup(REGCEAREGCE, posedge CLKARDCLK, 360); + // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L31 + $setup(RSTREGARSTREG, posedge CLKARDCLK, 342); + // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L49 + $setup(REGCEB, posedge CLKBWRCLK, 360); + // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L59 + $setup(RSTREGB, posedge CLKBWRCLK, 342); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L123 + $setup(DIADI, posedge CLKARDCLK, 737); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L133 + $setup(DIBDI, posedge CLKBWRCLK, 737); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L125 + $setup(DIPADIP, posedge CLKARDCLK, 737); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L135 + $setup(DIPBDIP, posedge CLKBWRCLK, 737); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L143 + if (&DOA_REG) (posedge CLKARDCLK => (DOADO : 32'bx)) = 2454; + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L144 + if (&DOA_REG) (posedge CLKARDCLK => (DOPADOP : 4'bx)) = 2454; + // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L153 + if (|DOA_REG) (posedge CLKARDCLK => (DOADO : 32'bx)) = 882; + // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L154 + if (|DOA_REG) (posedge CLKARDCLK => (DOPADOP : 4'bx)) = 882; + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L163 + if (&DOB_REG) (posedge CLKBWRCLK => (DOBDO : 32'bx)) = 2454; + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L164 + if (&DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 4'bx)) = 2454; + // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L173 + if (|DOB_REG) (posedge CLKBWRCLK => (DOBDO : 32'bx)) = 882; + // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L174 + if (|DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 4'bx)) = 882; + endspecify +endmodule diff --git a/techlibs/analogdevices/cells_xtra.py b/techlibs/analogdevices/cells_xtra.py new file mode 100644 index 000000000..645f1497d --- /dev/null +++ b/techlibs/analogdevices/cells_xtra.py @@ -0,0 +1,730 @@ +#!/usr/bin/env python3 + +from argparse import ArgumentParser +from io import StringIO +from enum import Enum, auto +import os.path +import sys +import re + + +class Cell: + def __init__(self, name, keep=False, port_attrs={}): + self.name = name + self.keep = keep + self.port_attrs = port_attrs + + +CELLS = [ + # Design element types listed in: + # - UG607 (Spartan 3) + # - UG613 (Spartan 3A) + # - UG617 (Spartan 3E) + # - UG615 (Spartan 6) + # - UG619 (Virtex 4) + # - UG621 (Virtex 5) + # - UG623 (Virtex 6) + # - UG953 (Series 7) + # - UG974 (Ultrascale) + + # CLB -- RAM/ROM. + # Cell('RAM16X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM16X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM128X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM512X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM16X2S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM16X4S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32X4S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM16X8S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32X8S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM16X1D', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM16X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM64X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM256X1D', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32M16', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM64M8', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32X16DR8', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM64X8SW', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('ROM16X1'), + # Cell('ROM32X1'), + # Cell('ROM64X1'), + # Cell('ROM128X1'), + # Cell('ROM256X1'), + + # CLB -- registers/latches. + # Virtex 1/2/4/5, Spartan 3. + # Cell('FDCPE', port_attrs={'C': ['clkbuf_sink']}), + # Cell('FDRSE', port_attrs={'C': ['clkbuf_sink']}), + # Cell('LDCPE', port_attrs={'C': ['clkbuf_sink']}), + # Virtex 6, Spartan 6, Series 7, Ultrascale. + # Cell('FDCE'), + # Cell('FDPE'), + # Cell('FDRE'), + # Cell('FDSE'), + # Cell('LDCE'), + # Cell('LDPE'), + # Cell('AND2B1L'), + # Cell('OR2L'), + + # CLB -- other. + # Cell('LUT1'), + # Cell('LUT2'), + # Cell('LUT3'), + # Cell('LUT4'), + # Cell('LUT5'), + # Cell('LUT6'), + # Cell('LUT6_2'), + # Cell('MUXF5'), + # Cell('MUXF6'), + # Cell('MUXF7'), + # Cell('MUXF8'), + # Cell('MUXF9'), + # Cell('CARRY4'), + # Cell('CARRY8'), + # Cell('MUXCY'), + # Cell('XORCY'), + # Cell('ORCY'), + # Cell('MULT_AND'), + # Cell('SRL16', port_attrs={'CLK': ['clkbuf_sink']}), + # Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}), + # Cell('SRLC16', port_attrs={'CLK': ['clkbuf_sink']}), + # Cell('SRLC16E', port_attrs={'CLK': ['clkbuf_sink']}), + # Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}), + # Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}), + + # Block RAM. + # Virtex. + Cell('RAMB4_S1', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('RAMB4_S2', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('RAMB4_S4', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('RAMB4_S8', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('RAMB4_S16', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('RAMB4_S1_S1', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB4_S1_S2', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB4_S1_S4', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB4_S1_S8', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB4_S1_S16', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB4_S2_S2', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB4_S2_S4', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB4_S2_S8', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB4_S2_S16', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB4_S4_S4', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB4_S4_S8', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB4_S4_S16', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB4_S8_S8', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB4_S8_S16', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB4_S16_S16', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + # Virtex 2, Spartan 3. + Cell('RAMB16_S1', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('RAMB16_S2', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('RAMB16_S4', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('RAMB16_S9', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('RAMB16_S18', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('RAMB16_S36', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('RAMB16_S1_S1', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S1_S2', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S1_S4', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S1_S9', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S1_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S1_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S2_S2', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S2_S4', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S2_S9', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S2_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S2_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S4_S4', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S4_S9', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S4_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S4_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S9_S9', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S9_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S9_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S18_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S18_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S36_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + # Spartan 3A (in addition to above). + Cell('RAMB16BWE_S18', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('RAMB16BWE_S36', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('RAMB16BWE_S18_S9', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16BWE_S18_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16BWE_S36_S9', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16BWE_S36_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16BWE_S36_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + # Spartan 3A DSP. + Cell('RAMB16BWER', port_attrs={ 'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + # Spartan 6 (in addition to above). + Cell('RAMB8BWER', port_attrs={ 'CLKAWRCLK': ['clkbuf_sink'], 'CLKBRDCLK': ['clkbuf_sink']}), + # Virtex 4. + Cell('FIFO16', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('RAMB16', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB32_S64_ECC', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + # Virtex 5. + Cell('FIFO18', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('FIFO18_36', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('FIFO36', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('FIFO36_72', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('RAMB18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB18SDP', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('RAMB36SDP', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + # Virtex 6 / Series 7. + Cell('FIFO18E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('FIFO36E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + #Cell('RAMB18E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']]}), + #Cell('RAMB36E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']]}), + # Ultrascale. + Cell('FIFO18E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('FIFO36E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('RAMB18E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}), + Cell('RAMB36E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}), + + # Ultra RAM. + Cell('URAM288', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('URAM288_BASE', port_attrs={'CLK': ['clkbuf_sink']}), + + # Multipliers and DSP. + # Cell('MULT18X18'), # Virtex 2, Spartan 3 + # Cell('MULT18X18S', port_attrs={'C': ['clkbuf_sink']}), # Spartan 3 + # Cell('MULT18X18SIO', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3E + # Cell('DSP48A', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3A DSP + # Cell('DSP48A1', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 6 + # Cell('DSP48', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 4 + Cell('DSP48E', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 5 + #Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 6 / Series 7 + Cell('DSP48E2', port_attrs={'CLK': ['clkbuf_sink']}), # Ultrascale + + # I/O logic. + # Virtex 2, Spartan 3. + # Note: these two are not officially listed in the HDL library guide, but + # they are more fundamental than OFDDR* and are necessary to construct + # differential DDR outputs (OFDDR* can only do single-ended). + Cell('FDDRCPE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}), + Cell('FDDRRSE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}), + Cell('IFDDRCPE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'D': ['iopad_external_pin']}), + Cell('IFDDRRSE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'D': ['iopad_external_pin']}), + Cell('OFDDRCPE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'Q': ['iopad_external_pin']}), + Cell('OFDDRRSE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'Q': ['iopad_external_pin']}), + Cell('OFDDRTCPE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'O': ['iopad_external_pin']}), + Cell('OFDDRTRSE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'O': ['iopad_external_pin']}), + # Spartan 3E. + Cell('IDDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}), + Cell('ODDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}), + # Virtex 4. + Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}), + Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}), + Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}), + Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}), + Cell('IDELAY', port_attrs={'C': ['clkbuf_sink']}), + Cell('ISERDES', port_attrs={ + 'CLK': ['clkbuf_sink'], + 'OCLK': ['clkbuf_sink'], + 'CLKDIV': ['clkbuf_sink'], + }), + Cell('OSERDES', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}), + # Virtex 5. + Cell('IODELAY', port_attrs={'C': ['clkbuf_sink']}), + Cell('ISERDES_NODELAY', port_attrs={ + 'CLK': ['clkbuf_sink'], + 'CLKB': ['clkbuf_sink'], + 'OCLK': ['clkbuf_sink'], + 'CLKDIV': ['clkbuf_sink'], + }), + # Virtex 6. + Cell('IODELAYE1', port_attrs={'C': ['clkbuf_sink']}), + Cell('ISERDESE1', port_attrs={ + 'CLK': ['clkbuf_sink'], + 'CLKB': ['clkbuf_sink'], + 'OCLK': ['clkbuf_sink'], + 'CLKDIV': ['clkbuf_sink'], + }), + Cell('OSERDESE1', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}), + # Series 7. + Cell('IDELAYE2', port_attrs={'C': ['clkbuf_sink']}), + Cell('ODELAYE2', port_attrs={'C': ['clkbuf_sink']}), + Cell('ISERDESE2', port_attrs={ + 'CLK': ['clkbuf_sink'], + 'CLKB': ['clkbuf_sink'], + 'OCLK': ['clkbuf_sink'], + 'OCLKB': ['clkbuf_sink'], + 'CLKDIV': ['clkbuf_sink'], + 'CLKDIVP': ['clkbuf_sink'], + }), + Cell('OSERDESE2', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}), + Cell('PHASER_IN', keep=True), + Cell('PHASER_IN_PHY', keep=True), + Cell('PHASER_OUT', keep=True), + Cell('PHASER_OUT_PHY', keep=True), + Cell('PHASER_REF', keep=True), + Cell('PHY_CONTROL', keep=True), + # Ultrascale. + Cell('IDDRE1', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}), + Cell('ODDRE1', port_attrs={'C': ['clkbuf_sink']}), + Cell('IDELAYE3', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('ODELAYE3', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('ISERDESE3', port_attrs={ + 'CLK': ['clkbuf_sink'], + 'CLK_B': ['clkbuf_sink'], + 'FIFO_RD_CLK': ['clkbuf_sink'], + 'CLKDIV': ['clkbuf_sink'], + }), + Cell('OSERDESE3', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}), + Cell('BITSLICE_CONTROL', keep=True), + Cell('RIU_OR', keep=True), + Cell('RX_BITSLICE'), + Cell('RXTX_BITSLICE'), + Cell('TX_BITSLICE'), + Cell('TX_BITSLICE_TRI'), + # Spartan 6. + Cell('IODELAY2', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}), + Cell('IODRP2', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}), + Cell('IODRP2_MCB', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}), + Cell('ISERDES2', port_attrs={ + 'CLK0': ['clkbuf_sink'], + 'CLK1': ['clkbuf_sink'], + 'CLKDIV': ['clkbuf_sink'], + }), + Cell('OSERDES2', port_attrs={ + 'CLK0': ['clkbuf_sink'], + 'CLK1': ['clkbuf_sink'], + 'CLKDIV': ['clkbuf_sink'], + }), + + # I/O buffers. + # Input. + # Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}), + Cell('IBUF_DLY_ADJ', port_attrs={'I': ['iopad_external_pin']}), + Cell('IBUF_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin']}), + Cell('IBUF_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin']}), + Cell('IBUF_ANALOG', port_attrs={'I': ['iopad_external_pin']}), + Cell('IBUFE3', port_attrs={'I': ['iopad_external_pin']}), + Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('IBUFDS_DLY_ADJ', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('IBUFDS_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('IBUFDS_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('IBUFDS_DIFF_OUT_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('IBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('IBUFDSE3', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('IBUFDS_DPHY', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + # Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}), + Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + # I/O. + # Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}), + Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}), + Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}), + Cell('IOBUFE3', port_attrs={'IO': ['iopad_external_pin']}), + Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), + Cell('IOBUFDS_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), + Cell('IOBUFDS_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), + Cell('IOBUFDS_DIFF_OUT', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), + Cell('IOBUFDS_DIFF_OUT_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), + Cell('IOBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), + Cell('IOBUFDSE3', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), + # Output. + # Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}), + Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), + Cell('OBUFDS_DPHY', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), + # Output + tristate. + # Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}), + Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), + # Pulls. + Cell('KEEPER'), + Cell('PULLDOWN'), + Cell('PULLUP'), + # Misc. + Cell('DCIRESET', keep=True), + Cell('HPIO_VREF', keep=True), # Ultrascale + + # Clock buffers (global). + # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}), + #Cell('BUFGCTRL', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFGMUX_CTRL', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFGMUX_VIRTEX4', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFG_GT', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFG_GT_SYNC'), + Cell('BUFG_PS', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFGCE_DIV', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFH', port_attrs={'O': ['clkbuf_driver']}), + #Cell('BUFHCE', port_attrs={'O': ['clkbuf_driver']}), + + # Clock buffers (IO) -- Spartan 6. + Cell('BUFIO2', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}), + Cell('BUFIO2_2CLK', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}), + Cell('BUFIO2FB', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFPLL', port_attrs={'IOCLK': ['clkbuf_driver']}), + Cell('BUFPLL_MCB', port_attrs={'IOCLK0': ['clkbuf_driver'], 'IOCLK1': ['clkbuf_driver']}), + + # Clock buffers (IO and regional) -- Virtex. + Cell('BUFIO', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFIODQS', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFR', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFMR', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFMRCE', port_attrs={'O': ['clkbuf_driver']}), + + # Clock components. + # VIrtex. + # TODO: CLKDLL + # TODO: CLKDLLE + # TODO: CLKDLLHF + # Virtex 2, Spartan 3. + Cell('DCM'), + # Spartan 3E. + Cell('DCM_SP'), + # Spartan 6 (also uses DCM_SP and PLL_BASE). + Cell('DCM_CLKGEN'), + # Virtex 4/5. + Cell('DCM_ADV'), + Cell('DCM_BASE'), + Cell('DCM_PS'), + # Virtex 4. + Cell('PMCD'), + # Virtex 5. + Cell('PLL_ADV'), + Cell('PLL_BASE'), + # Virtex 6. + Cell('MMCM_ADV'), + Cell('MMCM_BASE'), + # Series 7. + Cell('MMCME2_ADV'), + Cell('MMCME2_BASE'), + Cell('PLLE2_ADV'), + Cell('PLLE2_BASE'), + # Ultrascale. + Cell('MMCME3_ADV'), + Cell('MMCME3_BASE'), + Cell('PLLE3_ADV'), + Cell('PLLE3_BASE'), + # Ultrascale+. + Cell('MMCME4_ADV'), + Cell('MMCME4_BASE'), + Cell('PLLE4_ADV'), + Cell('PLLE4_BASE'), + + # Misc stuff. + Cell('BUFT'), + # Series 7 I/O FIFOs. + Cell('IN_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('OUT_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + # Ultrascale special synchronizer register. + Cell('HARD_SYNC', port_attrs={'CLK': ['clkbuf_sink']}), + + # Singletons. + # Startup. + # TODO: STARTUP_VIRTEX + # TODO: STARTUP_VIRTEX2 + Cell('STARTUP_SPARTAN3', keep=True), + Cell('STARTUP_SPARTAN3E', keep=True), + Cell('STARTUP_SPARTAN3A', keep=True), + Cell('STARTUP_SPARTAN6', keep=True), + Cell('STARTUP_VIRTEX4', keep=True), + Cell('STARTUP_VIRTEX5', keep=True), + Cell('STARTUP_VIRTEX6', keep=True), + Cell('STARTUPE2', keep=True), # Series 7 + Cell('STARTUPE3', keep=True), # Ultrascale + # Capture trigger. + # TODO: CAPTURE_VIRTEX + # TODO: CAPTURE_VIRTEX2 + Cell('CAPTURE_SPARTAN3', keep=True), + Cell('CAPTURE_SPARTAN3A', keep=True), + Cell('CAPTURE_VIRTEX4', keep=True), + Cell('CAPTURE_VIRTEX5', keep=True), + Cell('CAPTURE_VIRTEX6', keep=True), + Cell('CAPTUREE2', keep=True), # Series 7 + # Internal Configuration Access Port. + # TODO: ICAP_VIRTEX2 + Cell('ICAP_SPARTAN3A', keep=True), + Cell('ICAP_SPARTAN6', keep=True), + Cell('ICAP_VIRTEX4', keep=True), + Cell('ICAP_VIRTEX5', keep=True), + Cell('ICAP_VIRTEX6', keep=True), + Cell('ICAPE2', keep=True), # Series 7 + Cell('ICAPE3', keep=True), # Ultrascale + # JTAG. + # TODO: BSCAN_VIRTEX + # TODO: BSCAN_VIRTEX2 + Cell('BSCAN_SPARTAN3', keep=True), + Cell('BSCAN_SPARTAN3A', keep=True), + Cell('BSCAN_SPARTAN6', keep=True), + Cell('BSCAN_VIRTEX4', keep=True), + Cell('BSCAN_VIRTEX5', keep=True), + Cell('BSCAN_VIRTEX6', keep=True), + Cell('BSCANE2', keep=True), # Series 7, Ultrascale + # DNA port. + Cell('DNA_PORT'), # Virtex 5/6, Series 7, Spartan 3A/6 + Cell('DNA_PORTE2'), # Ultrascale + # Frame ECC. + Cell('FRAME_ECC_VIRTEX4'), + Cell('FRAME_ECC_VIRTEX5'), + Cell('FRAME_ECC_VIRTEX6'), + Cell('FRAME_ECCE2'), # Series 7 + Cell('FRAME_ECCE3'), # Ultrascale + Cell('FRAME_ECCE4'), # Ultrascale+ + # AXSS command access. + Cell('USR_ACCESS_VIRTEX4'), + Cell('USR_ACCESS_VIRTEX5'), + Cell('USR_ACCESS_VIRTEX6'), + Cell('USR_ACCESSE2'), # Series 7, Ultrascale + # Misc. + Cell('POST_CRC_INTERNAL'), # Spartan 6 + Cell('SUSPEND_SYNC', keep=True), # Spartan 6 + Cell('KEY_CLEAR', keep=True), # Virtex 5 + Cell('MASTER_JTAG', keep=True), # Ultrascale + Cell('SPI_ACCESS', keep=True), # Spartan 3AN + Cell('EFUSE_USR'), + + # ADC. + Cell('SYSMON', keep=True), # Virtex 5/6 + Cell('XADC', keep=True), # Series 7 + Cell('SYSMONE1', keep=True), # Ultrascale + Cell('SYSMONE4', keep=True), # Ultrascale+ + + # Gigabit transceivers. + # Spartan 6. + Cell('GTPA1_DUAL'), + # Virtex 2 Pro. + # TODO: GT_* + # TODO: GT10_* + # Virtex 4. + Cell('GT11_CUSTOM'), + Cell('GT11_DUAL'), + Cell('GT11CLK'), + Cell('GT11CLK_MGT'), + # Virtex 5. + Cell('GTP_DUAL'), + Cell('GTX_DUAL'), + Cell('CRC32', port_attrs={'CRCCLK': ['clkbuf_sink']}), + Cell('CRC64', port_attrs={'CRCCLK': ['clkbuf_sink']}), + # Virtex 6. + Cell('GTHE1_QUAD'), + Cell('GTXE1'), + Cell('IBUFDS_GTXE1', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('IBUFDS_GTHE1', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + # Series 7. + Cell('GTHE2_CHANNEL'), + Cell('GTHE2_COMMON'), + Cell('GTPE2_CHANNEL'), + Cell('GTPE2_COMMON'), + Cell('GTXE2_CHANNEL'), + Cell('GTXE2_COMMON'), + Cell('IBUFDS_GTE2', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + # Ultrascale. + Cell('GTHE3_CHANNEL'), + Cell('GTHE3_COMMON'), + Cell('GTYE3_CHANNEL'), + Cell('GTYE3_COMMON'), + Cell('IBUFDS_GTE3', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('OBUFDS_GTE3', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), + Cell('OBUFDS_GTE3_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), + # Ultrascale+. + Cell('GTHE4_CHANNEL'), + Cell('GTHE4_COMMON'), + Cell('GTYE4_CHANNEL'), + Cell('GTYE4_COMMON'), + Cell('IBUFDS_GTE4', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('OBUFDS_GTE4', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), + Cell('OBUFDS_GTE4_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), + # Ultrascale+ GTM. + Cell('GTM_DUAL'), # not in the libraries guide + Cell('IBUFDS_GTM', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('OBUFDS_GTM', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), + Cell('OBUFDS_GTM_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), + + # High-speed ADC/DAC. + Cell('HSDAC'), # not in libraries guide + Cell('HSADC'), # not in libraries guide + Cell('RFDAC'), # not in libraries guide + Cell('RFADC'), # not in libraries guide + + # PCIE IP. + Cell('PCIE_A1'), # Spartan 6 + Cell('PCIE_EP'), # Virtex 5 + Cell('PCIE_2_0'), # Virtex 6 + Cell('PCIE_2_1'), # Series 7 + Cell('PCIE_3_0'), # Series 7 + Cell('PCIE_3_1'), # Ultrascale + Cell('PCIE40E4'), # Ultrascale+ + Cell('PCIE4CE4'), # Ultrascale+ v2 (not in the libraries guide) + + # Ethernet IP. + Cell('EMAC'), # Virtex 4 + Cell('TEMAC'), # Virtex 5 + Cell('TEMAC_SINGLE'), # Virtex 6 + Cell('CMAC'), # Ultrascale + Cell('CMACE4'), # Ultrsacale+ + + # Hard memory controllers. + Cell('MCB'), # Spartan 6 Memory Controller Block + Cell('HBM_REF_CLK', keep=True), # not in liraries guide + # not sure how the following relate to the hw + Cell('HBM_SNGLBLI_INTF_APB', keep=True), # not in liraries guide + Cell('HBM_SNGLBLI_INTF_AXI', keep=True), # not in liraries guide + Cell('HBM_ONE_STACK_INTF', keep=True), # not in liraries guide + Cell('HBM_TWO_STACK_INTF', keep=True), # not in liraries guide + + # PowerPC. + # TODO PPC405 (Virtex 2) + Cell('PPC405_ADV'), # Virtex 4 + Cell('PPC440'), # Virtex 5 + + # ARM. + Cell('PS7', keep=True), # The Zynq 7000 ARM Processor System (not in libraries guide). + Cell('PS8', keep=True), # The Zynq Ultrascale+ ARM Processor System (not in libraries guide). + + # Misc hard IP. + Cell('ILKN'), # Ultrascale Interlaken + Cell('ILKNE4'), # Ultrascale+ Interlaken + Cell('VCU', keep=True), # Zynq MPSoC Video Codec Unit (not in libraries guide). + Cell('FE'), # Zynq RFSoC Forward Error Correction (not in libraries guide). +] + + +class State(Enum): + OUTSIDE = auto() + IN_MODULE = auto() + IN_OTHER_MODULE = auto() + IN_FUNCTION = auto() + IN_TASK = auto() + +def xtract_cell_decl(cell, dirs, outf): + for dir in dirs: + for ext in ['.v', '.sv']: + fname = os.path.join(dir, cell.name + ext) + try: + with open(fname) as f: + state = State.OUTSIDE + found = False + # Probably the most horrible Verilog "parser" ever written. + module_ports = [] + invertible_ports = set() + for l in f: + l = l.partition('//')[0] + l = l.strip() + if l == 'module {}'.format(cell.name) or l.startswith('module {} '.format(cell.name)): + if found: + print('Multiple modules in {}.'.format(fname)) + sys.exit(1) + elif state != State.OUTSIDE: + print('Nested modules in {}.'.format(fname)) + sys.exit(1) + found = True + state = State.IN_MODULE + if cell.keep: + outf.write('(* keep *)\n') + outf.write('module {} (...);\n'.format(cell.name)) + elif l.startswith('module '): + if state != State.OUTSIDE: + print('Nested modules in {}.'.format(fname)) + sys.exit(1) + state = State.IN_OTHER_MODULE + elif l.startswith('task '): + if state == State.IN_MODULE: + state = State.IN_TASK + elif l.startswith('function '): + if state == State.IN_MODULE: + state = State.IN_FUNCTION + elif l == 'endtask': + if state == State.IN_TASK: + state = State.IN_MODULE + elif l == 'endfunction': + if state == State.IN_FUNCTION: + state = State.IN_MODULE + elif l == 'endmodule': + if state == State.IN_MODULE: + for kind, rng, port in module_ports: + for attr in cell.port_attrs.get(port, []): + outf.write(' (* {} *)\n'.format(attr)) + if port in invertible_ports: + outf.write(' (* invertible_pin = "IS_{}_INVERTED" *)\n'.format(port)) + if rng is None: + outf.write(' {} {};\n'.format(kind, port)) + else: + outf.write(' {} {} {};\n'.format(kind, rng, port)) + outf.write(l + '\n') + outf.write('\n') + elif state != State.IN_OTHER_MODULE: + print('endmodule in weird place in {}.'.format(cell.name, fname)) + sys.exit(1) + state = State.OUTSIDE + elif l.startswith(('input ', 'output ', 'inout ')) and state == State.IN_MODULE: + if l.endswith((';', ',')): + l = l[:-1] + if ';' in l: + print('Weird port line in {} [{}].'.format(fname, l)) + sys.exit(1) + kind, _, ports = l.partition(' ') + for port in ports.split(','): + port = port.strip() + if port.startswith('['): + rng, port = port.split() + else: + rng = None + module_ports.append((kind, rng, port)) + elif l.startswith('parameter ') and state == State.IN_MODULE: + if 'UNPLACED' in l: + continue + if l.endswith((';', ',')): + l = l[:-1] + while ' ' in l: + l = l.replace(' ', ' ') + if ';' in l: + print('Weird parameter line in {} [{}].'.format(fname, l)) + sys.exit(1) + outf.write(' {};\n'.format(l)) + match = re.search('IS_([a-zA-Z0-9_]+)_INVERTED', l) + if match: + invertible_ports.add(match[1]) + if state != State.OUTSIDE: + print('endmodule not found in {}.'.format(fname)) + sys.exit(1) + if not found: + print('Cannot find module {} in {}.'.format(cell.name, fname)) + sys.exit(1) + return + except FileNotFoundError: + continue + print('Cannot find {}.'.format(cell.name)) + sys.exit(1) + +if __name__ == '__main__': + parser = ArgumentParser(description='Extract Analog Devices blackbox cell definitions from ISE and Vivado.') + parser.add_argument('vivado_dir', nargs='?', default='/opt/Analog Devices/Vivado/2022.2') + parser.add_argument('ise_dir', nargs='?', default='/opt/Analog Devices/ISE/14.7') + args = parser.parse_args() + + dirs = [ + os.path.join(args.vivado_dir, 'data/verilog/src/xeclib'), + os.path.join(args.vivado_dir, 'data/verilog/src/unisims'), + os.path.join(args.vivado_dir, 'data/verilog/src/retarget'), + os.path.join(args.ise_dir, 'ISE_DS/ISE/verilog/xeclib/unisims'), + ] + for dir in dirs: + if not os.path.isdir(dir): + print('{} is not a directory'.format(dir)) + + out = StringIO() + for cell in CELLS: + xtract_cell_decl(cell, dirs, out) + + with open('cells_xtra.v', 'w') as f: + f.write('// Created by cells_xtra.py from Analog Devices models\n') + f.write('\n') + f.write(out.getvalue()) diff --git a/techlibs/analogdevices/cells_xtra.v b/techlibs/analogdevices/cells_xtra.v new file mode 100644 index 000000000..d12546aa7 --- /dev/null +++ b/techlibs/analogdevices/cells_xtra.v @@ -0,0 +1,34120 @@ +// Created by cells_xtra.py from Analog Devices models + +module RAMB4_S1 (...); + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [0:0] DO; + input [11:0] ADDR; + input [0:0] DI; + input EN; + (* clkbuf_sink *) + input CLK; + input WE; + input RST; +endmodule + +module RAMB4_S2 (...); + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [1:0] DO; + input [10:0] ADDR; + input [1:0] DI; + input EN; + (* clkbuf_sink *) + input CLK; + input WE; + input RST; +endmodule + +module RAMB4_S4 (...); + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [3:0] DO; + input [9:0] ADDR; + input [3:0] DI; + input EN; + (* clkbuf_sink *) + input CLK; + input WE; + input RST; +endmodule + +module RAMB4_S8 (...); + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [7:0] DO; + input [8:0] ADDR; + input [7:0] DI; + input EN; + (* clkbuf_sink *) + input CLK; + input WE; + input RST; +endmodule + +module RAMB4_S16 (...); + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [15:0] DO; + input [7:0] ADDR; + input [15:0] DI; + input EN; + (* clkbuf_sink *) + input CLK; + input WE; + input RST; +endmodule + +module RAMB4_S1_S1 (...); + parameter SIM_COLLISION_CHECK = "ALL"; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [0:0] DOA; + input [11:0] ADDRA; + input [0:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input RSTA; + output [0:0] DOB; + input [11:0] ADDRB; + input [0:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input RSTB; +endmodule + +module RAMB4_S1_S2 (...); + parameter SIM_COLLISION_CHECK = "ALL"; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [0:0] DOA; + input [11:0] ADDRA; + input [0:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input RSTA; + output [1:0] DOB; + input [10:0] ADDRB; + input [1:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input RSTB; +endmodule + +module RAMB4_S1_S4 (...); + parameter SIM_COLLISION_CHECK = "ALL"; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [0:0] DOA; + input [11:0] ADDRA; + input [0:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input RSTA; + output [3:0] DOB; + input [9:0] ADDRB; + input [3:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input RSTB; +endmodule + +module RAMB4_S1_S8 (...); + parameter SIM_COLLISION_CHECK = "ALL"; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [0:0] DOA; + input [11:0] ADDRA; + input [0:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input RSTA; + output [7:0] DOB; + input [8:0] ADDRB; + input [7:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input RSTB; +endmodule + +module RAMB4_S1_S16 (...); + parameter SIM_COLLISION_CHECK = "ALL"; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [0:0] DOA; + input [11:0] ADDRA; + input [0:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input RSTA; + output [15:0] DOB; + input [7:0] ADDRB; + input [15:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input RSTB; +endmodule + +module RAMB4_S2_S2 (...); + parameter SIM_COLLISION_CHECK = "ALL"; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [1:0] DOA; + input [10:0] ADDRA; + input [1:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input RSTA; + output [1:0] DOB; + input [10:0] ADDRB; + input [1:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input RSTB; +endmodule + +module RAMB4_S2_S4 (...); + parameter SIM_COLLISION_CHECK = "ALL"; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [1:0] DOA; + input [10:0] ADDRA; + input [1:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input RSTA; + output [3:0] DOB; + input [9:0] ADDRB; + input [3:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input RSTB; +endmodule + +module RAMB4_S2_S8 (...); + parameter SIM_COLLISION_CHECK = "ALL"; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [1:0] DOA; + input [10:0] ADDRA; + input [1:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input RSTA; + output [7:0] DOB; + input [8:0] ADDRB; + input [7:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input RSTB; +endmodule + +module RAMB4_S2_S16 (...); + parameter SIM_COLLISION_CHECK = "ALL"; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [1:0] DOA; + input [10:0] ADDRA; + input [1:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input RSTA; + output [15:0] DOB; + input [7:0] ADDRB; + input [15:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input RSTB; +endmodule + +module RAMB4_S4_S4 (...); + parameter SIM_COLLISION_CHECK = "ALL"; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [3:0] DOA; + input [9:0] ADDRA; + input [3:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input RSTA; + output [3:0] DOB; + input [9:0] ADDRB; + input [3:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input RSTB; +endmodule + +module RAMB4_S4_S8 (...); + parameter SIM_COLLISION_CHECK = "ALL"; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [3:0] DOA; + input [9:0] ADDRA; + input [3:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input RSTA; + output [7:0] DOB; + input [8:0] ADDRB; + input [7:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input RSTB; +endmodule + +module RAMB4_S4_S16 (...); + parameter SIM_COLLISION_CHECK = "ALL"; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [3:0] DOA; + input [9:0] ADDRA; + input [3:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input RSTA; + output [15:0] DOB; + input [7:0] ADDRB; + input [15:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input RSTB; +endmodule + +module RAMB4_S8_S8 (...); + parameter SIM_COLLISION_CHECK = "ALL"; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [7:0] DOA; + input [8:0] ADDRA; + input [7:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input RSTA; + output [7:0] DOB; + input [8:0] ADDRB; + input [7:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input RSTB; +endmodule + +module RAMB4_S8_S16 (...); + parameter SIM_COLLISION_CHECK = "ALL"; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [7:0] DOA; + input [8:0] ADDRA; + input [7:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input RSTA; + output [15:0] DOB; + input [7:0] ADDRB; + input [15:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input RSTB; +endmodule + +module RAMB4_S16_S16 (...); + parameter SIM_COLLISION_CHECK = "ALL"; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [15:0] DOA; + input [7:0] ADDRA; + input [15:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input RSTA; + output [15:0] DOB; + input [7:0] ADDRB; + input [15:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input RSTB; +endmodule + +module RAMB16_S1 (...); + parameter [0:0] INIT = 1'h0; + parameter [0:0] SRVAL = 1'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [0:0] DO; + input [13:0] ADDR; + input [0:0] DI; + input EN; + (* clkbuf_sink *) + input CLK; + input WE; + input SSR; +endmodule + +module RAMB16_S2 (...); + parameter [1:0] INIT = 2'h0; + parameter [1:0] SRVAL = 2'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [1:0] DO; + input [12:0] ADDR; + input [1:0] DI; + input EN; + (* clkbuf_sink *) + input CLK; + input WE; + input SSR; +endmodule + +module RAMB16_S4 (...); + parameter [3:0] INIT = 4'h0; + parameter [3:0] SRVAL = 4'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [3:0] DO; + input [11:0] ADDR; + input [3:0] DI; + input EN; + (* clkbuf_sink *) + input CLK; + input WE; + input SSR; +endmodule + +module RAMB16_S9 (...); + parameter [8:0] INIT = 9'h0; + parameter [8:0] SRVAL = 9'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [7:0] DO; + output [0:0] DOP; + input [10:0] ADDR; + input [7:0] DI; + input [0:0] DIP; + input EN; + (* clkbuf_sink *) + input CLK; + input WE; + input SSR; +endmodule + +module RAMB16_S18 (...); + parameter [17:0] INIT = 18'h0; + parameter [17:0] SRVAL = 18'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [15:0] DO; + output [1:0] DOP; + input [9:0] ADDR; + input [15:0] DI; + input [1:0] DIP; + input EN; + (* clkbuf_sink *) + input CLK; + input WE; + input SSR; +endmodule + +module RAMB16_S36 (...); + parameter [35:0] INIT = 36'h0; + parameter [35:0] SRVAL = 36'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [31:0] DO; + output [3:0] DOP; + input [8:0] ADDR; + input [31:0] DI; + input [3:0] DIP; + input EN; + (* clkbuf_sink *) + input CLK; + input WE; + input SSR; +endmodule + +module RAMB16_S1_S1 (...); + parameter [0:0] INIT_A = 1'h0; + parameter [0:0] INIT_B = 1'h0; + parameter [0:0] SRVAL_A = 1'h0; + parameter [0:0] SRVAL_B = 1'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [0:0] DOA; + input [13:0] ADDRA; + input [0:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [0:0] DOB; + input [13:0] ADDRB; + input [0:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S1_S2 (...); + parameter [0:0] INIT_A = 1'h0; + parameter [1:0] INIT_B = 2'h0; + parameter [0:0] SRVAL_A = 1'h0; + parameter [1:0] SRVAL_B = 2'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [0:0] DOA; + input [13:0] ADDRA; + input [0:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [1:0] DOB; + input [12:0] ADDRB; + input [1:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S1_S4 (...); + parameter [0:0] INIT_A = 1'h0; + parameter [3:0] INIT_B = 4'h0; + parameter [0:0] SRVAL_A = 1'h0; + parameter [3:0] SRVAL_B = 4'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [0:0] DOA; + input [13:0] ADDRA; + input [0:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [3:0] DOB; + input [11:0] ADDRB; + input [3:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S1_S9 (...); + parameter [0:0] INIT_A = 1'h0; + parameter [8:0] INIT_B = 9'h0; + parameter [0:0] SRVAL_A = 1'h0; + parameter [8:0] SRVAL_B = 9'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [0:0] DOA; + input [13:0] ADDRA; + input [0:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [7:0] DOB; + output [0:0] DOPB; + input [10:0] ADDRB; + input [7:0] DIB; + input [0:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S1_S18 (...); + parameter [0:0] INIT_A = 1'h0; + parameter [17:0] INIT_B = 18'h0; + parameter [0:0] SRVAL_A = 1'h0; + parameter [17:0] SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [0:0] DOA; + input [13:0] ADDRA; + input [0:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [15:0] DOB; + output [1:0] DOPB; + input [9:0] ADDRB; + input [15:0] DIB; + input [1:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S1_S36 (...); + parameter [0:0] INIT_A = 1'h0; + parameter [35:0] INIT_B = 36'h0; + parameter [0:0] SRVAL_A = 1'h0; + parameter [35:0] SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [0:0] DOA; + input [13:0] ADDRA; + input [0:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [31:0] DOB; + output [3:0] DOPB; + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S2_S2 (...); + parameter [1:0] INIT_A = 2'h0; + parameter [1:0] INIT_B = 2'h0; + parameter [1:0] SRVAL_A = 2'h0; + parameter [1:0] SRVAL_B = 2'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [1:0] DOA; + input [12:0] ADDRA; + input [1:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [1:0] DOB; + input [12:0] ADDRB; + input [1:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S2_S4 (...); + parameter [1:0] INIT_A = 2'h0; + parameter [3:0] INIT_B = 4'h0; + parameter [1:0] SRVAL_A = 2'h0; + parameter [3:0] SRVAL_B = 4'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [1:0] DOA; + input [12:0] ADDRA; + input [1:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [3:0] DOB; + input [11:0] ADDRB; + input [3:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S2_S9 (...); + parameter [1:0] INIT_A = 2'h0; + parameter [8:0] INIT_B = 9'h0; + parameter [1:0] SRVAL_A = 2'h0; + parameter [8:0] SRVAL_B = 9'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [1:0] DOA; + input [12:0] ADDRA; + input [1:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [7:0] DOB; + output [0:0] DOPB; + input [10:0] ADDRB; + input [7:0] DIB; + input [0:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S2_S18 (...); + parameter [1:0] INIT_A = 2'h0; + parameter [17:0] INIT_B = 18'h0; + parameter [1:0] SRVAL_A = 2'h0; + parameter [17:0] SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [1:0] DOA; + input [12:0] ADDRA; + input [1:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [15:0] DOB; + output [1:0] DOPB; + input [9:0] ADDRB; + input [15:0] DIB; + input [1:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S2_S36 (...); + parameter [1:0] INIT_A = 2'h0; + parameter [35:0] INIT_B = 36'h0; + parameter [1:0] SRVAL_A = 2'h0; + parameter [35:0] SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [1:0] DOA; + input [12:0] ADDRA; + input [1:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [31:0] DOB; + output [3:0] DOPB; + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S4_S4 (...); + parameter [3:0] INIT_A = 4'h0; + parameter [3:0] INIT_B = 4'h0; + parameter [3:0] SRVAL_A = 4'h0; + parameter [3:0] SRVAL_B = 4'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [3:0] DOA; + input [11:0] ADDRA; + input [3:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [3:0] DOB; + input [11:0] ADDRB; + input [3:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S4_S9 (...); + parameter [3:0] INIT_A = 4'h0; + parameter [8:0] INIT_B = 9'h0; + parameter [3:0] SRVAL_A = 4'h0; + parameter [8:0] SRVAL_B = 9'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [3:0] DOA; + input [11:0] ADDRA; + input [3:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [7:0] DOB; + output [0:0] DOPB; + input [10:0] ADDRB; + input [7:0] DIB; + input [0:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S4_S18 (...); + parameter [3:0] INIT_A = 4'h0; + parameter [17:0] INIT_B = 18'h0; + parameter [3:0] SRVAL_A = 4'h0; + parameter [17:0] SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [3:0] DOA; + input [11:0] ADDRA; + input [3:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [15:0] DOB; + output [1:0] DOPB; + input [9:0] ADDRB; + input [15:0] DIB; + input [1:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S4_S36 (...); + parameter [3:0] INIT_A = 4'h0; + parameter [35:0] INIT_B = 36'h0; + parameter [3:0] SRVAL_A = 4'h0; + parameter [35:0] SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [3:0] DOA; + input [11:0] ADDRA; + input [3:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [31:0] DOB; + output [3:0] DOPB; + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S9_S9 (...); + parameter [8:0] INIT_A = 9'h0; + parameter [8:0] INIT_B = 9'h0; + parameter [8:0] SRVAL_A = 9'h0; + parameter [8:0] SRVAL_B = 9'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [7:0] DOA; + output [0:0] DOPA; + input [10:0] ADDRA; + input [7:0] DIA; + input [0:0] DIPA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [7:0] DOB; + output [0:0] DOPB; + input [10:0] ADDRB; + input [7:0] DIB; + input [0:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S9_S18 (...); + parameter [8:0] INIT_A = 9'h0; + parameter [17:0] INIT_B = 18'h0; + parameter [8:0] SRVAL_A = 9'h0; + parameter [17:0] SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [7:0] DOA; + output [0:0] DOPA; + input [10:0] ADDRA; + input [7:0] DIA; + input [0:0] DIPA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [15:0] DOB; + output [1:0] DOPB; + input [9:0] ADDRB; + input [15:0] DIB; + input [1:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S9_S36 (...); + parameter [8:0] INIT_A = 9'h0; + parameter [35:0] INIT_B = 36'h0; + parameter [8:0] SRVAL_A = 9'h0; + parameter [35:0] SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [7:0] DOA; + output [0:0] DOPA; + input [10:0] ADDRA; + input [7:0] DIA; + input [0:0] DIPA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [31:0] DOB; + output [3:0] DOPB; + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S18_S18 (...); + parameter [17:0] INIT_A = 18'h0; + parameter [17:0] INIT_B = 18'h0; + parameter [17:0] SRVAL_A = 18'h0; + parameter [17:0] SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [15:0] DOA; + output [1:0] DOPA; + input [9:0] ADDRA; + input [15:0] DIA; + input [1:0] DIPA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [15:0] DOB; + output [1:0] DOPB; + input [9:0] ADDRB; + input [15:0] DIB; + input [1:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S18_S36 (...); + parameter [17:0] INIT_A = 18'h0; + parameter [35:0] INIT_B = 36'h0; + parameter [17:0] SRVAL_A = 18'h0; + parameter [35:0] SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [15:0] DOA; + output [1:0] DOPA; + input [9:0] ADDRA; + input [15:0] DIA; + input [1:0] DIPA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [31:0] DOB; + output [3:0] DOPB; + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S36_S36 (...); + parameter [35:0] INIT_A = 36'h0; + parameter [35:0] INIT_B = 36'h0; + parameter [35:0] SRVAL_A = 36'h0; + parameter [35:0] SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [31:0] DOA; + output [3:0] DOPA; + input [8:0] ADDRA; + input [31:0] DIA; + input [3:0] DIPA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [31:0] DOB; + output [3:0] DOPB; + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16BWE_S18 (...); + parameter [17:0] INIT = 18'h0; + parameter [255:0] INITP_00 = 256'h0; + parameter [255:0] INITP_01 = 256'h0; + parameter [255:0] INITP_02 = 256'h0; + parameter [255:0] INITP_03 = 256'h0; + parameter [255:0] INITP_04 = 256'h0; + parameter [255:0] INITP_05 = 256'h0; + parameter [255:0] INITP_06 = 256'h0; + parameter [255:0] INITP_07 = 256'h0; + parameter [255:0] INIT_00 = 256'h0; + parameter [255:0] INIT_01 = 256'h0; + parameter [255:0] INIT_02 = 256'h0; + parameter [255:0] INIT_03 = 256'h0; + parameter [255:0] INIT_04 = 256'h0; + parameter [255:0] INIT_05 = 256'h0; + parameter [255:0] INIT_06 = 256'h0; + parameter [255:0] INIT_07 = 256'h0; + parameter [255:0] INIT_08 = 256'h0; + parameter [255:0] INIT_09 = 256'h0; + parameter [255:0] INIT_0A = 256'h0; + parameter [255:0] INIT_0B = 256'h0; + parameter [255:0] INIT_0C = 256'h0; + parameter [255:0] INIT_0D = 256'h0; + parameter [255:0] INIT_0E = 256'h0; + parameter [255:0] INIT_0F = 256'h0; + parameter [255:0] INIT_10 = 256'h0; + parameter [255:0] INIT_11 = 256'h0; + parameter [255:0] INIT_12 = 256'h0; + parameter [255:0] INIT_13 = 256'h0; + parameter [255:0] INIT_14 = 256'h0; + parameter [255:0] INIT_15 = 256'h0; + parameter [255:0] INIT_16 = 256'h0; + parameter [255:0] INIT_17 = 256'h0; + parameter [255:0] INIT_18 = 256'h0; + parameter [255:0] INIT_19 = 256'h0; + parameter [255:0] INIT_1A = 256'h0; + parameter [255:0] INIT_1B = 256'h0; + parameter [255:0] INIT_1C = 256'h0; + parameter [255:0] INIT_1D = 256'h0; + parameter [255:0] INIT_1E = 256'h0; + parameter [255:0] INIT_1F = 256'h0; + parameter [255:0] INIT_20 = 256'h0; + parameter [255:0] INIT_21 = 256'h0; + parameter [255:0] INIT_22 = 256'h0; + parameter [255:0] INIT_23 = 256'h0; + parameter [255:0] INIT_24 = 256'h0; + parameter [255:0] INIT_25 = 256'h0; + parameter [255:0] INIT_26 = 256'h0; + parameter [255:0] INIT_27 = 256'h0; + parameter [255:0] INIT_28 = 256'h0; + parameter [255:0] INIT_29 = 256'h0; + parameter [255:0] INIT_2A = 256'h0; + parameter [255:0] INIT_2B = 256'h0; + parameter [255:0] INIT_2C = 256'h0; + parameter [255:0] INIT_2D = 256'h0; + parameter [255:0] INIT_2E = 256'h0; + parameter [255:0] INIT_2F = 256'h0; + parameter [255:0] INIT_30 = 256'h0; + parameter [255:0] INIT_31 = 256'h0; + parameter [255:0] INIT_32 = 256'h0; + parameter [255:0] INIT_33 = 256'h0; + parameter [255:0] INIT_34 = 256'h0; + parameter [255:0] INIT_35 = 256'h0; + parameter [255:0] INIT_36 = 256'h0; + parameter [255:0] INIT_37 = 256'h0; + parameter [255:0] INIT_38 = 256'h0; + parameter [255:0] INIT_39 = 256'h0; + parameter [255:0] INIT_3A = 256'h0; + parameter [255:0] INIT_3B = 256'h0; + parameter [255:0] INIT_3C = 256'h0; + parameter [255:0] INIT_3D = 256'h0; + parameter [255:0] INIT_3E = 256'h0; + parameter [255:0] INIT_3F = 256'h0; + parameter [17:0] SRVAL = 18'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + output [15:0] DO; + output [1:0] DOP; + (* clkbuf_sink *) + input CLK; + input EN; + input SSR; + input [1:0] WE; + input [15:0] DI; + input [1:0] DIP; + input [9:0] ADDR; +endmodule + +module RAMB16BWE_S36 (...); + parameter [35:0] INIT = 36'h0; + parameter [255:0] INITP_00 = 256'h0; + parameter [255:0] INITP_01 = 256'h0; + parameter [255:0] INITP_02 = 256'h0; + parameter [255:0] INITP_03 = 256'h0; + parameter [255:0] INITP_04 = 256'h0; + parameter [255:0] INITP_05 = 256'h0; + parameter [255:0] INITP_06 = 256'h0; + parameter [255:0] INITP_07 = 256'h0; + parameter [255:0] INIT_00 = 256'h0; + parameter [255:0] INIT_01 = 256'h0; + parameter [255:0] INIT_02 = 256'h0; + parameter [255:0] INIT_03 = 256'h0; + parameter [255:0] INIT_04 = 256'h0; + parameter [255:0] INIT_05 = 256'h0; + parameter [255:0] INIT_06 = 256'h0; + parameter [255:0] INIT_07 = 256'h0; + parameter [255:0] INIT_08 = 256'h0; + parameter [255:0] INIT_09 = 256'h0; + parameter [255:0] INIT_0A = 256'h0; + parameter [255:0] INIT_0B = 256'h0; + parameter [255:0] INIT_0C = 256'h0; + parameter [255:0] INIT_0D = 256'h0; + parameter [255:0] INIT_0E = 256'h0; + parameter [255:0] INIT_0F = 256'h0; + parameter [255:0] INIT_10 = 256'h0; + parameter [255:0] INIT_11 = 256'h0; + parameter [255:0] INIT_12 = 256'h0; + parameter [255:0] INIT_13 = 256'h0; + parameter [255:0] INIT_14 = 256'h0; + parameter [255:0] INIT_15 = 256'h0; + parameter [255:0] INIT_16 = 256'h0; + parameter [255:0] INIT_17 = 256'h0; + parameter [255:0] INIT_18 = 256'h0; + parameter [255:0] INIT_19 = 256'h0; + parameter [255:0] INIT_1A = 256'h0; + parameter [255:0] INIT_1B = 256'h0; + parameter [255:0] INIT_1C = 256'h0; + parameter [255:0] INIT_1D = 256'h0; + parameter [255:0] INIT_1E = 256'h0; + parameter [255:0] INIT_1F = 256'h0; + parameter [255:0] INIT_20 = 256'h0; + parameter [255:0] INIT_21 = 256'h0; + parameter [255:0] INIT_22 = 256'h0; + parameter [255:0] INIT_23 = 256'h0; + parameter [255:0] INIT_24 = 256'h0; + parameter [255:0] INIT_25 = 256'h0; + parameter [255:0] INIT_26 = 256'h0; + parameter [255:0] INIT_27 = 256'h0; + parameter [255:0] INIT_28 = 256'h0; + parameter [255:0] INIT_29 = 256'h0; + parameter [255:0] INIT_2A = 256'h0; + parameter [255:0] INIT_2B = 256'h0; + parameter [255:0] INIT_2C = 256'h0; + parameter [255:0] INIT_2D = 256'h0; + parameter [255:0] INIT_2E = 256'h0; + parameter [255:0] INIT_2F = 256'h0; + parameter [255:0] INIT_30 = 256'h0; + parameter [255:0] INIT_31 = 256'h0; + parameter [255:0] INIT_32 = 256'h0; + parameter [255:0] INIT_33 = 256'h0; + parameter [255:0] INIT_34 = 256'h0; + parameter [255:0] INIT_35 = 256'h0; + parameter [255:0] INIT_36 = 256'h0; + parameter [255:0] INIT_37 = 256'h0; + parameter [255:0] INIT_38 = 256'h0; + parameter [255:0] INIT_39 = 256'h0; + parameter [255:0] INIT_3A = 256'h0; + parameter [255:0] INIT_3B = 256'h0; + parameter [255:0] INIT_3C = 256'h0; + parameter [255:0] INIT_3D = 256'h0; + parameter [255:0] INIT_3E = 256'h0; + parameter [255:0] INIT_3F = 256'h0; + parameter [35:0] SRVAL = 36'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + output [31:0] DO; + output [3:0] DOP; + (* clkbuf_sink *) + input CLK; + input EN; + input SSR; + input [3:0] WE; + input [31:0] DI; + input [3:0] DIP; + input [8:0] ADDR; +endmodule + +module RAMB16BWE_S18_S9 (...); + parameter [255:0] INITP_00 = 256'h0; + parameter [255:0] INITP_01 = 256'h0; + parameter [255:0] INITP_02 = 256'h0; + parameter [255:0] INITP_03 = 256'h0; + parameter [255:0] INITP_04 = 256'h0; + parameter [255:0] INITP_05 = 256'h0; + parameter [255:0] INITP_06 = 256'h0; + parameter [255:0] INITP_07 = 256'h0; + parameter [255:0] INIT_00 = 256'h0; + parameter [255:0] INIT_01 = 256'h0; + parameter [255:0] INIT_02 = 256'h0; + parameter [255:0] INIT_03 = 256'h0; + parameter [255:0] INIT_04 = 256'h0; + parameter [255:0] INIT_05 = 256'h0; + parameter [255:0] INIT_06 = 256'h0; + parameter [255:0] INIT_07 = 256'h0; + parameter [255:0] INIT_08 = 256'h0; + parameter [255:0] INIT_09 = 256'h0; + parameter [255:0] INIT_0A = 256'h0; + parameter [255:0] INIT_0B = 256'h0; + parameter [255:0] INIT_0C = 256'h0; + parameter [255:0] INIT_0D = 256'h0; + parameter [255:0] INIT_0E = 256'h0; + parameter [255:0] INIT_0F = 256'h0; + parameter [255:0] INIT_10 = 256'h0; + parameter [255:0] INIT_11 = 256'h0; + parameter [255:0] INIT_12 = 256'h0; + parameter [255:0] INIT_13 = 256'h0; + parameter [255:0] INIT_14 = 256'h0; + parameter [255:0] INIT_15 = 256'h0; + parameter [255:0] INIT_16 = 256'h0; + parameter [255:0] INIT_17 = 256'h0; + parameter [255:0] INIT_18 = 256'h0; + parameter [255:0] INIT_19 = 256'h0; + parameter [255:0] INIT_1A = 256'h0; + parameter [255:0] INIT_1B = 256'h0; + parameter [255:0] INIT_1C = 256'h0; + parameter [255:0] INIT_1D = 256'h0; + parameter [255:0] INIT_1E = 256'h0; + parameter [255:0] INIT_1F = 256'h0; + parameter [255:0] INIT_20 = 256'h0; + parameter [255:0] INIT_21 = 256'h0; + parameter [255:0] INIT_22 = 256'h0; + parameter [255:0] INIT_23 = 256'h0; + parameter [255:0] INIT_24 = 256'h0; + parameter [255:0] INIT_25 = 256'h0; + parameter [255:0] INIT_26 = 256'h0; + parameter [255:0] INIT_27 = 256'h0; + parameter [255:0] INIT_28 = 256'h0; + parameter [255:0] INIT_29 = 256'h0; + parameter [255:0] INIT_2A = 256'h0; + parameter [255:0] INIT_2B = 256'h0; + parameter [255:0] INIT_2C = 256'h0; + parameter [255:0] INIT_2D = 256'h0; + parameter [255:0] INIT_2E = 256'h0; + parameter [255:0] INIT_2F = 256'h0; + parameter [255:0] INIT_30 = 256'h0; + parameter [255:0] INIT_31 = 256'h0; + parameter [255:0] INIT_32 = 256'h0; + parameter [255:0] INIT_33 = 256'h0; + parameter [255:0] INIT_34 = 256'h0; + parameter [255:0] INIT_35 = 256'h0; + parameter [255:0] INIT_36 = 256'h0; + parameter [255:0] INIT_37 = 256'h0; + parameter [255:0] INIT_38 = 256'h0; + parameter [255:0] INIT_39 = 256'h0; + parameter [255:0] INIT_3A = 256'h0; + parameter [255:0] INIT_3B = 256'h0; + parameter [255:0] INIT_3C = 256'h0; + parameter [255:0] INIT_3D = 256'h0; + parameter [255:0] INIT_3E = 256'h0; + parameter [255:0] INIT_3F = 256'h0; + parameter [17:0] INIT_A = 18'h0; + parameter [8:0] INIT_B = 9'h0; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [17:0] SRVAL_A = 18'h0; + parameter [8:0] SRVAL_B = 9'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + output [15:0] DOA; + output [7:0] DOB; + output [1:0] DOPA; + output [0:0] DOPB; + (* clkbuf_sink *) + input CLKA; + (* clkbuf_sink *) + input CLKB; + input ENA; + input ENB; + input SSRA; + input SSRB; + input WEB; + input [1:0] WEA; + input [15:0] DIA; + input [7:0] DIB; + input [1:0] DIPA; + input [0:0] DIPB; + input [9:0] ADDRA; + input [10:0] ADDRB; +endmodule + +module RAMB16BWE_S18_S18 (...); + parameter [255:0] INITP_00 = 256'h0; + parameter [255:0] INITP_01 = 256'h0; + parameter [255:0] INITP_02 = 256'h0; + parameter [255:0] INITP_03 = 256'h0; + parameter [255:0] INITP_04 = 256'h0; + parameter [255:0] INITP_05 = 256'h0; + parameter [255:0] INITP_06 = 256'h0; + parameter [255:0] INITP_07 = 256'h0; + parameter [255:0] INIT_00 = 256'h0; + parameter [255:0] INIT_01 = 256'h0; + parameter [255:0] INIT_02 = 256'h0; + parameter [255:0] INIT_03 = 256'h0; + parameter [255:0] INIT_04 = 256'h0; + parameter [255:0] INIT_05 = 256'h0; + parameter [255:0] INIT_06 = 256'h0; + parameter [255:0] INIT_07 = 256'h0; + parameter [255:0] INIT_08 = 256'h0; + parameter [255:0] INIT_09 = 256'h0; + parameter [255:0] INIT_0A = 256'h0; + parameter [255:0] INIT_0B = 256'h0; + parameter [255:0] INIT_0C = 256'h0; + parameter [255:0] INIT_0D = 256'h0; + parameter [255:0] INIT_0E = 256'h0; + parameter [255:0] INIT_0F = 256'h0; + parameter [255:0] INIT_10 = 256'h0; + parameter [255:0] INIT_11 = 256'h0; + parameter [255:0] INIT_12 = 256'h0; + parameter [255:0] INIT_13 = 256'h0; + parameter [255:0] INIT_14 = 256'h0; + parameter [255:0] INIT_15 = 256'h0; + parameter [255:0] INIT_16 = 256'h0; + parameter [255:0] INIT_17 = 256'h0; + parameter [255:0] INIT_18 = 256'h0; + parameter [255:0] INIT_19 = 256'h0; + parameter [255:0] INIT_1A = 256'h0; + parameter [255:0] INIT_1B = 256'h0; + parameter [255:0] INIT_1C = 256'h0; + parameter [255:0] INIT_1D = 256'h0; + parameter [255:0] INIT_1E = 256'h0; + parameter [255:0] INIT_1F = 256'h0; + parameter [255:0] INIT_20 = 256'h0; + parameter [255:0] INIT_21 = 256'h0; + parameter [255:0] INIT_22 = 256'h0; + parameter [255:0] INIT_23 = 256'h0; + parameter [255:0] INIT_24 = 256'h0; + parameter [255:0] INIT_25 = 256'h0; + parameter [255:0] INIT_26 = 256'h0; + parameter [255:0] INIT_27 = 256'h0; + parameter [255:0] INIT_28 = 256'h0; + parameter [255:0] INIT_29 = 256'h0; + parameter [255:0] INIT_2A = 256'h0; + parameter [255:0] INIT_2B = 256'h0; + parameter [255:0] INIT_2C = 256'h0; + parameter [255:0] INIT_2D = 256'h0; + parameter [255:0] INIT_2E = 256'h0; + parameter [255:0] INIT_2F = 256'h0; + parameter [255:0] INIT_30 = 256'h0; + parameter [255:0] INIT_31 = 256'h0; + parameter [255:0] INIT_32 = 256'h0; + parameter [255:0] INIT_33 = 256'h0; + parameter [255:0] INIT_34 = 256'h0; + parameter [255:0] INIT_35 = 256'h0; + parameter [255:0] INIT_36 = 256'h0; + parameter [255:0] INIT_37 = 256'h0; + parameter [255:0] INIT_38 = 256'h0; + parameter [255:0] INIT_39 = 256'h0; + parameter [255:0] INIT_3A = 256'h0; + parameter [255:0] INIT_3B = 256'h0; + parameter [255:0] INIT_3C = 256'h0; + parameter [255:0] INIT_3D = 256'h0; + parameter [255:0] INIT_3E = 256'h0; + parameter [255:0] INIT_3F = 256'h0; + parameter [17:0] INIT_A = 18'h0; + parameter [17:0] INIT_B = 18'h0; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [17:0] SRVAL_A = 18'h0; + parameter [17:0] SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + output [15:0] DOA; + output [15:0] DOB; + output [1:0] DOPA; + output [1:0] DOPB; + (* clkbuf_sink *) + input CLKA; + (* clkbuf_sink *) + input CLKB; + input ENA; + input ENB; + input SSRA; + input SSRB; + input [1:0] WEB; + input [1:0] WEA; + input [15:0] DIA; + input [15:0] DIB; + input [1:0] DIPA; + input [1:0] DIPB; + input [9:0] ADDRA; + input [9:0] ADDRB; +endmodule + +module RAMB16BWE_S36_S9 (...); + parameter [255:0] INITP_00 = 256'h0; + parameter [255:0] INITP_01 = 256'h0; + parameter [255:0] INITP_02 = 256'h0; + parameter [255:0] INITP_03 = 256'h0; + parameter [255:0] INITP_04 = 256'h0; + parameter [255:0] INITP_05 = 256'h0; + parameter [255:0] INITP_06 = 256'h0; + parameter [255:0] INITP_07 = 256'h0; + parameter [255:0] INIT_00 = 256'h0; + parameter [255:0] INIT_01 = 256'h0; + parameter [255:0] INIT_02 = 256'h0; + parameter [255:0] INIT_03 = 256'h0; + parameter [255:0] INIT_04 = 256'h0; + parameter [255:0] INIT_05 = 256'h0; + parameter [255:0] INIT_06 = 256'h0; + parameter [255:0] INIT_07 = 256'h0; + parameter [255:0] INIT_08 = 256'h0; + parameter [255:0] INIT_09 = 256'h0; + parameter [255:0] INIT_0A = 256'h0; + parameter [255:0] INIT_0B = 256'h0; + parameter [255:0] INIT_0C = 256'h0; + parameter [255:0] INIT_0D = 256'h0; + parameter [255:0] INIT_0E = 256'h0; + parameter [255:0] INIT_0F = 256'h0; + parameter [255:0] INIT_10 = 256'h0; + parameter [255:0] INIT_11 = 256'h0; + parameter [255:0] INIT_12 = 256'h0; + parameter [255:0] INIT_13 = 256'h0; + parameter [255:0] INIT_14 = 256'h0; + parameter [255:0] INIT_15 = 256'h0; + parameter [255:0] INIT_16 = 256'h0; + parameter [255:0] INIT_17 = 256'h0; + parameter [255:0] INIT_18 = 256'h0; + parameter [255:0] INIT_19 = 256'h0; + parameter [255:0] INIT_1A = 256'h0; + parameter [255:0] INIT_1B = 256'h0; + parameter [255:0] INIT_1C = 256'h0; + parameter [255:0] INIT_1D = 256'h0; + parameter [255:0] INIT_1E = 256'h0; + parameter [255:0] INIT_1F = 256'h0; + parameter [255:0] INIT_20 = 256'h0; + parameter [255:0] INIT_21 = 256'h0; + parameter [255:0] INIT_22 = 256'h0; + parameter [255:0] INIT_23 = 256'h0; + parameter [255:0] INIT_24 = 256'h0; + parameter [255:0] INIT_25 = 256'h0; + parameter [255:0] INIT_26 = 256'h0; + parameter [255:0] INIT_27 = 256'h0; + parameter [255:0] INIT_28 = 256'h0; + parameter [255:0] INIT_29 = 256'h0; + parameter [255:0] INIT_2A = 256'h0; + parameter [255:0] INIT_2B = 256'h0; + parameter [255:0] INIT_2C = 256'h0; + parameter [255:0] INIT_2D = 256'h0; + parameter [255:0] INIT_2E = 256'h0; + parameter [255:0] INIT_2F = 256'h0; + parameter [255:0] INIT_30 = 256'h0; + parameter [255:0] INIT_31 = 256'h0; + parameter [255:0] INIT_32 = 256'h0; + parameter [255:0] INIT_33 = 256'h0; + parameter [255:0] INIT_34 = 256'h0; + parameter [255:0] INIT_35 = 256'h0; + parameter [255:0] INIT_36 = 256'h0; + parameter [255:0] INIT_37 = 256'h0; + parameter [255:0] INIT_38 = 256'h0; + parameter [255:0] INIT_39 = 256'h0; + parameter [255:0] INIT_3A = 256'h0; + parameter [255:0] INIT_3B = 256'h0; + parameter [255:0] INIT_3C = 256'h0; + parameter [255:0] INIT_3D = 256'h0; + parameter [255:0] INIT_3E = 256'h0; + parameter [255:0] INIT_3F = 256'h0; + parameter [35:0] INIT_A = 36'h0; + parameter [8:0] INIT_B = 9'h0; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [35:0] SRVAL_A = 36'h0; + parameter [8:0] SRVAL_B = 9'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + output [31:0] DOA; + output [3:0] DOPA; + output [7:0] DOB; + output [0:0] DOPB; + (* clkbuf_sink *) + input CLKA; + (* clkbuf_sink *) + input CLKB; + input ENA; + input ENB; + input SSRA; + input SSRB; + input [3:0] WEA; + input WEB; + input [31:0] DIA; + input [3:0] DIPA; + input [7:0] DIB; + input [0:0] DIPB; + input [8:0] ADDRA; + input [10:0] ADDRB; +endmodule + +module RAMB16BWE_S36_S18 (...); + parameter [255:0] INITP_00 = 256'h0; + parameter [255:0] INITP_01 = 256'h0; + parameter [255:0] INITP_02 = 256'h0; + parameter [255:0] INITP_03 = 256'h0; + parameter [255:0] INITP_04 = 256'h0; + parameter [255:0] INITP_05 = 256'h0; + parameter [255:0] INITP_06 = 256'h0; + parameter [255:0] INITP_07 = 256'h0; + parameter [255:0] INIT_00 = 256'h0; + parameter [255:0] INIT_01 = 256'h0; + parameter [255:0] INIT_02 = 256'h0; + parameter [255:0] INIT_03 = 256'h0; + parameter [255:0] INIT_04 = 256'h0; + parameter [255:0] INIT_05 = 256'h0; + parameter [255:0] INIT_06 = 256'h0; + parameter [255:0] INIT_07 = 256'h0; + parameter [255:0] INIT_08 = 256'h0; + parameter [255:0] INIT_09 = 256'h0; + parameter [255:0] INIT_0A = 256'h0; + parameter [255:0] INIT_0B = 256'h0; + parameter [255:0] INIT_0C = 256'h0; + parameter [255:0] INIT_0D = 256'h0; + parameter [255:0] INIT_0E = 256'h0; + parameter [255:0] INIT_0F = 256'h0; + parameter [255:0] INIT_10 = 256'h0; + parameter [255:0] INIT_11 = 256'h0; + parameter [255:0] INIT_12 = 256'h0; + parameter [255:0] INIT_13 = 256'h0; + parameter [255:0] INIT_14 = 256'h0; + parameter [255:0] INIT_15 = 256'h0; + parameter [255:0] INIT_16 = 256'h0; + parameter [255:0] INIT_17 = 256'h0; + parameter [255:0] INIT_18 = 256'h0; + parameter [255:0] INIT_19 = 256'h0; + parameter [255:0] INIT_1A = 256'h0; + parameter [255:0] INIT_1B = 256'h0; + parameter [255:0] INIT_1C = 256'h0; + parameter [255:0] INIT_1D = 256'h0; + parameter [255:0] INIT_1E = 256'h0; + parameter [255:0] INIT_1F = 256'h0; + parameter [255:0] INIT_20 = 256'h0; + parameter [255:0] INIT_21 = 256'h0; + parameter [255:0] INIT_22 = 256'h0; + parameter [255:0] INIT_23 = 256'h0; + parameter [255:0] INIT_24 = 256'h0; + parameter [255:0] INIT_25 = 256'h0; + parameter [255:0] INIT_26 = 256'h0; + parameter [255:0] INIT_27 = 256'h0; + parameter [255:0] INIT_28 = 256'h0; + parameter [255:0] INIT_29 = 256'h0; + parameter [255:0] INIT_2A = 256'h0; + parameter [255:0] INIT_2B = 256'h0; + parameter [255:0] INIT_2C = 256'h0; + parameter [255:0] INIT_2D = 256'h0; + parameter [255:0] INIT_2E = 256'h0; + parameter [255:0] INIT_2F = 256'h0; + parameter [255:0] INIT_30 = 256'h0; + parameter [255:0] INIT_31 = 256'h0; + parameter [255:0] INIT_32 = 256'h0; + parameter [255:0] INIT_33 = 256'h0; + parameter [255:0] INIT_34 = 256'h0; + parameter [255:0] INIT_35 = 256'h0; + parameter [255:0] INIT_36 = 256'h0; + parameter [255:0] INIT_37 = 256'h0; + parameter [255:0] INIT_38 = 256'h0; + parameter [255:0] INIT_39 = 256'h0; + parameter [255:0] INIT_3A = 256'h0; + parameter [255:0] INIT_3B = 256'h0; + parameter [255:0] INIT_3C = 256'h0; + parameter [255:0] INIT_3D = 256'h0; + parameter [255:0] INIT_3E = 256'h0; + parameter [255:0] INIT_3F = 256'h0; + parameter [35:0] INIT_A = 36'h0; + parameter [17:0] INIT_B = 18'h0; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [35:0] SRVAL_A = 36'h0; + parameter [17:0] SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + output [31:0] DOA; + output [3:0] DOPA; + output [15:0] DOB; + output [1:0] DOPB; + (* clkbuf_sink *) + input CLKA; + (* clkbuf_sink *) + input CLKB; + input ENA; + input ENB; + input SSRA; + input SSRB; + input [3:0] WEA; + input [1:0] WEB; + input [31:0] DIA; + input [3:0] DIPA; + input [15:0] DIB; + input [1:0] DIPB; + input [8:0] ADDRA; + input [9:0] ADDRB; +endmodule + +module RAMB16BWE_S36_S36 (...); + parameter [255:0] INITP_00 = 256'h0; + parameter [255:0] INITP_01 = 256'h0; + parameter [255:0] INITP_02 = 256'h0; + parameter [255:0] INITP_03 = 256'h0; + parameter [255:0] INITP_04 = 256'h0; + parameter [255:0] INITP_05 = 256'h0; + parameter [255:0] INITP_06 = 256'h0; + parameter [255:0] INITP_07 = 256'h0; + parameter [255:0] INIT_00 = 256'h0; + parameter [255:0] INIT_01 = 256'h0; + parameter [255:0] INIT_02 = 256'h0; + parameter [255:0] INIT_03 = 256'h0; + parameter [255:0] INIT_04 = 256'h0; + parameter [255:0] INIT_05 = 256'h0; + parameter [255:0] INIT_06 = 256'h0; + parameter [255:0] INIT_07 = 256'h0; + parameter [255:0] INIT_08 = 256'h0; + parameter [255:0] INIT_09 = 256'h0; + parameter [255:0] INIT_0A = 256'h0; + parameter [255:0] INIT_0B = 256'h0; + parameter [255:0] INIT_0C = 256'h0; + parameter [255:0] INIT_0D = 256'h0; + parameter [255:0] INIT_0E = 256'h0; + parameter [255:0] INIT_0F = 256'h0; + parameter [255:0] INIT_10 = 256'h0; + parameter [255:0] INIT_11 = 256'h0; + parameter [255:0] INIT_12 = 256'h0; + parameter [255:0] INIT_13 = 256'h0; + parameter [255:0] INIT_14 = 256'h0; + parameter [255:0] INIT_15 = 256'h0; + parameter [255:0] INIT_16 = 256'h0; + parameter [255:0] INIT_17 = 256'h0; + parameter [255:0] INIT_18 = 256'h0; + parameter [255:0] INIT_19 = 256'h0; + parameter [255:0] INIT_1A = 256'h0; + parameter [255:0] INIT_1B = 256'h0; + parameter [255:0] INIT_1C = 256'h0; + parameter [255:0] INIT_1D = 256'h0; + parameter [255:0] INIT_1E = 256'h0; + parameter [255:0] INIT_1F = 256'h0; + parameter [255:0] INIT_20 = 256'h0; + parameter [255:0] INIT_21 = 256'h0; + parameter [255:0] INIT_22 = 256'h0; + parameter [255:0] INIT_23 = 256'h0; + parameter [255:0] INIT_24 = 256'h0; + parameter [255:0] INIT_25 = 256'h0; + parameter [255:0] INIT_26 = 256'h0; + parameter [255:0] INIT_27 = 256'h0; + parameter [255:0] INIT_28 = 256'h0; + parameter [255:0] INIT_29 = 256'h0; + parameter [255:0] INIT_2A = 256'h0; + parameter [255:0] INIT_2B = 256'h0; + parameter [255:0] INIT_2C = 256'h0; + parameter [255:0] INIT_2D = 256'h0; + parameter [255:0] INIT_2E = 256'h0; + parameter [255:0] INIT_2F = 256'h0; + parameter [255:0] INIT_30 = 256'h0; + parameter [255:0] INIT_31 = 256'h0; + parameter [255:0] INIT_32 = 256'h0; + parameter [255:0] INIT_33 = 256'h0; + parameter [255:0] INIT_34 = 256'h0; + parameter [255:0] INIT_35 = 256'h0; + parameter [255:0] INIT_36 = 256'h0; + parameter [255:0] INIT_37 = 256'h0; + parameter [255:0] INIT_38 = 256'h0; + parameter [255:0] INIT_39 = 256'h0; + parameter [255:0] INIT_3A = 256'h0; + parameter [255:0] INIT_3B = 256'h0; + parameter [255:0] INIT_3C = 256'h0; + parameter [255:0] INIT_3D = 256'h0; + parameter [255:0] INIT_3E = 256'h0; + parameter [255:0] INIT_3F = 256'h0; + parameter [35:0] INIT_A = 36'h0; + parameter [35:0] INIT_B = 36'h0; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [35:0] SRVAL_A = 36'h0; + parameter [35:0] SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + output [31:0] DOA; + output [3:0] DOPA; + output [31:0] DOB; + output [3:0] DOPB; + (* clkbuf_sink *) + input CLKA; + (* clkbuf_sink *) + input CLKB; + input ENA; + input ENB; + input SSRA; + input SSRB; + input [3:0] WEA; + input [3:0] WEB; + input [31:0] DIA; + input [3:0] DIPA; + input [31:0] DIB; + input [3:0] DIPB; + input [8:0] ADDRA; + input [8:0] ADDRB; +endmodule + +module RAMB16BWER (...); + parameter integer DATA_WIDTH_A = 0; + parameter integer DATA_WIDTH_B = 0; + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter EN_RSTRAM_A = "TRUE"; + parameter EN_RSTRAM_B = "TRUE"; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [35:0] INIT_A = 36'h0; + parameter [35:0] INIT_B = 36'h0; + parameter INIT_FILE = "NONE"; + parameter RSTTYPE = "SYNC"; + parameter RST_PRIORITY_A = "CE"; + parameter RST_PRIORITY_B = "CE"; + parameter SETUP_ALL = 1000; + parameter SETUP_READ_FIRST = 3000; + parameter SIM_DEVICE = "SPARTAN3ADSP"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [35:0] SRVAL_A = 36'h0; + parameter [35:0] SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + output [31:0] DOA; + output [31:0] DOB; + output [3:0] DOPA; + output [3:0] DOPB; + input [13:0] ADDRA; + input [13:0] ADDRB; + (* clkbuf_sink *) + input CLKA; + (* clkbuf_sink *) + input CLKB; + input [31:0] DIA; + input [31:0] DIB; + input [3:0] DIPA; + input [3:0] DIPB; + input ENA; + input ENB; + input REGCEA; + input REGCEB; + input RSTA; + input RSTB; + input [3:0] WEA; + input [3:0] WEB; +endmodule + +module RAMB8BWER (...); + parameter integer DATA_WIDTH_A = 0; + parameter integer DATA_WIDTH_B = 0; + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter EN_RSTRAM_A = "TRUE"; + parameter EN_RSTRAM_B = "TRUE"; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [17:0] INIT_A = 18'h0; + parameter [17:0] INIT_B = 18'h0; + parameter INIT_FILE = "NONE"; + parameter RAM_MODE = "TDP"; + parameter RSTTYPE = "SYNC"; + parameter RST_PRIORITY_A = "CE"; + parameter RST_PRIORITY_B = "CE"; + parameter SETUP_ALL = 1000; + parameter SETUP_READ_FIRST = 3000; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [17:0] SRVAL_A = 18'h0; + parameter [17:0] SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + output [15:0] DOADO; + output [15:0] DOBDO; + output [1:0] DOPADOP; + output [1:0] DOPBDOP; + input [12:0] ADDRAWRADDR; + input [12:0] ADDRBRDADDR; + (* clkbuf_sink *) + input CLKAWRCLK; + (* clkbuf_sink *) + input CLKBRDCLK; + input [15:0] DIADI; + input [15:0] DIBDI; + input [1:0] DIPADIP; + input [1:0] DIPBDIP; + input ENAWREN; + input ENBRDEN; + input REGCEA; + input REGCEBREGCE; + input RSTA; + input RSTBRST; + input [1:0] WEAWEL; + input [1:0] WEBWEU; +endmodule + +module FIFO16 (...); + parameter [11:0] ALMOST_FULL_OFFSET = 12'h080; + parameter [11:0] ALMOST_EMPTY_OFFSET = 12'h080; + parameter integer DATA_WIDTH = 36; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + output ALMOSTEMPTY; + output ALMOSTFULL; + output [31:0] DO; + output [3:0] DOP; + output EMPTY; + output FULL; + output [11:0] RDCOUNT; + output RDERR; + output [11:0] WRCOUNT; + output WRERR; + input [31:0] DI; + input [3:0] DIP; + (* clkbuf_sink *) + input RDCLK; + input RDEN; + input RST; + (* clkbuf_sink *) + input WRCLK; + input WREN; +endmodule + +module RAMB16 (...); + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [35:0] INIT_A = 36'h0; + parameter [35:0] INIT_B = 36'h0; + parameter INIT_FILE = "NONE"; + parameter INVERT_CLK_DOA_REG = "FALSE"; + parameter INVERT_CLK_DOB_REG = "FALSE"; + parameter RAM_EXTENSION_A = "NONE"; + parameter RAM_EXTENSION_B = "NONE"; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [35:0] SRVAL_A = 36'h0; + parameter [35:0] SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + output CASCADEOUTA; + output CASCADEOUTB; + output [31:0] DOA; + output [31:0] DOB; + output [3:0] DOPA; + output [3:0] DOPB; + input ENA; + (* clkbuf_sink *) + input CLKA; + input SSRA; + input CASCADEINA; + input REGCEA; + input ENB; + (* clkbuf_sink *) + input CLKB; + input SSRB; + input CASCADEINB; + input REGCEB; + input [14:0] ADDRA; + input [14:0] ADDRB; + input [31:0] DIA; + input [31:0] DIB; + input [3:0] DIPA; + input [3:0] DIPB; + input [3:0] WEA; + input [3:0] WEB; +endmodule + +module RAMB32_S64_ECC (...); + parameter DO_REG = 0; + parameter SIM_COLLISION_CHECK = "ALL"; + output [1:0] STATUS; + output [63:0] DO; + (* clkbuf_sink *) + input RDCLK; + input RDEN; + input SSR; + (* clkbuf_sink *) + input WRCLK; + input WREN; + input [63:0] DI; + input [8:0] RDADDR; + input [8:0] WRADDR; +endmodule + +module FIFO18 (...); + parameter [11:0] ALMOST_EMPTY_OFFSET = 12'h080; + parameter [11:0] ALMOST_FULL_OFFSET = 12'h080; + parameter integer DATA_WIDTH = 4; + parameter integer DO_REG = 1; + parameter EN_SYN = "FALSE"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter SIM_MODE = "SAFE"; + output ALMOSTEMPTY; + output ALMOSTFULL; + output [15:0] DO; + output [1:0] DOP; + output EMPTY; + output FULL; + output [11:0] RDCOUNT; + output RDERR; + output [11:0] WRCOUNT; + output WRERR; + input [15:0] DI; + input [1:0] DIP; + (* clkbuf_sink *) + input RDCLK; + input RDEN; + input RST; + (* clkbuf_sink *) + input WRCLK; + input WREN; +endmodule + +module FIFO18_36 (...); + parameter [8:0] ALMOST_EMPTY_OFFSET = 9'h080; + parameter [8:0] ALMOST_FULL_OFFSET = 9'h080; + parameter integer DO_REG = 1; + parameter EN_SYN = "FALSE"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter SIM_MODE = "SAFE"; + output ALMOSTEMPTY; + output ALMOSTFULL; + output [31:0] DO; + output [3:0] DOP; + output EMPTY; + output FULL; + output [8:0] RDCOUNT; + output RDERR; + output [8:0] WRCOUNT; + output WRERR; + input [31:0] DI; + input [3:0] DIP; + (* clkbuf_sink *) + input RDCLK; + input RDEN; + input RST; + (* clkbuf_sink *) + input WRCLK; + input WREN; +endmodule + +module FIFO36 (...); + parameter [12:0] ALMOST_EMPTY_OFFSET = 13'h080; + parameter [12:0] ALMOST_FULL_OFFSET = 13'h080; + parameter integer DATA_WIDTH = 4; + parameter integer DO_REG = 1; + parameter EN_SYN = "FALSE"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter SIM_MODE = "SAFE"; + output ALMOSTEMPTY; + output ALMOSTFULL; + output [31:0] DO; + output [3:0] DOP; + output EMPTY; + output FULL; + output [12:0] RDCOUNT; + output RDERR; + output [12:0] WRCOUNT; + output WRERR; + input [31:0] DI; + input [3:0] DIP; + (* clkbuf_sink *) + input RDCLK; + input RDEN; + input RST; + (* clkbuf_sink *) + input WRCLK; + input WREN; +endmodule + +module FIFO36_72 (...); + parameter [8:0] ALMOST_EMPTY_OFFSET = 9'h080; + parameter [8:0] ALMOST_FULL_OFFSET = 9'h080; + parameter integer DO_REG = 1; + parameter EN_ECC_WRITE = "FALSE"; + parameter EN_ECC_READ = "FALSE"; + parameter EN_SYN = "FALSE"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter SIM_MODE = "SAFE"; + output ALMOSTEMPTY; + output ALMOSTFULL; + output DBITERR; + output [63:0] DO; + output [7:0] DOP; + output [7:0] ECCPARITY; + output EMPTY; + output FULL; + output [8:0] RDCOUNT; + output RDERR; + output SBITERR; + output [8:0] WRCOUNT; + output WRERR; + input [63:0] DI; + input [7:0] DIP; + (* clkbuf_sink *) + input RDCLK; + input RDEN; + input RST; + (* clkbuf_sink *) + input WRCLK; + input WREN; +endmodule + +module RAMB18 (...); + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [17:0] INIT_A = 18'h0; + parameter [17:0] INIT_B = 18'h0; + parameter INIT_FILE = "NONE"; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SIM_MODE = "SAFE"; + parameter [17:0] SRVAL_A = 18'h0; + parameter [17:0] SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + output [15:0] DOA; + output [15:0] DOB; + output [1:0] DOPA; + output [1:0] DOPB; + input ENA; + (* clkbuf_sink *) + input CLKA; + input SSRA; + input REGCEA; + input ENB; + (* clkbuf_sink *) + input CLKB; + input SSRB; + input REGCEB; + input [13:0] ADDRA; + input [13:0] ADDRB; + input [15:0] DIA; + input [15:0] DIB; + input [1:0] DIPA; + input [1:0] DIPB; + input [1:0] WEA; + input [1:0] WEB; +endmodule + +module RAMB36 (...); + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [35:0] INIT_A = 36'h0; + parameter [35:0] INIT_B = 36'h0; + parameter INIT_FILE = "NONE"; + parameter RAM_EXTENSION_A = "NONE"; + parameter RAM_EXTENSION_B = "NONE"; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SIM_MODE = "SAFE"; + parameter [35:0] SRVAL_A = 36'h0; + parameter [35:0] SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + output CASCADEOUTLATA; + output CASCADEOUTREGA; + output CASCADEOUTLATB; + output CASCADEOUTREGB; + output [31:0] DOA; + output [31:0] DOB; + output [3:0] DOPA; + output [3:0] DOPB; + input ENA; + (* clkbuf_sink *) + input CLKA; + input SSRA; + input CASCADEINLATA; + input CASCADEINREGA; + input REGCEA; + input ENB; + (* clkbuf_sink *) + input CLKB; + input SSRB; + input CASCADEINLATB; + input CASCADEINREGB; + input REGCEB; + input [15:0] ADDRA; + input [15:0] ADDRB; + input [31:0] DIA; + input [31:0] DIB; + input [3:0] DIPA; + input [3:0] DIPB; + input [3:0] WEA; + input [3:0] WEB; +endmodule + +module RAMB18SDP (...); + parameter integer DO_REG = 0; + parameter [35:0] INIT = 36'h0; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_FILE = "NONE"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SIM_MODE = "SAFE"; + parameter [35:0] SRVAL = 36'h0; + output [31:0] DO; + output [3:0] DOP; + (* clkbuf_sink *) + input RDCLK; + input RDEN; + input REGCE; + input SSR; + (* clkbuf_sink *) + input WRCLK; + input WREN; + input [8:0] WRADDR; + input [8:0] RDADDR; + input [31:0] DI; + input [3:0] DIP; + input [3:0] WE; +endmodule + +module RAMB36SDP (...); + parameter integer DO_REG = 0; + parameter EN_ECC_READ = "FALSE"; + parameter EN_ECC_SCRUB = "FALSE"; + parameter EN_ECC_WRITE = "FALSE"; + parameter [71:0] INIT = 72'h0; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_FILE = "NONE"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SIM_MODE = "SAFE"; + parameter [71:0] SRVAL = 72'h0; + output DBITERR; + output SBITERR; + output [63:0] DO; + output [7:0] DOP; + output [7:0] ECCPARITY; + (* clkbuf_sink *) + input RDCLK; + input RDEN; + input REGCE; + input SSR; + (* clkbuf_sink *) + input WRCLK; + input WREN; + input [8:0] WRADDR; + input [8:0] RDADDR; + input [63:0] DI; + input [7:0] DIP; + input [7:0] WE; +endmodule + +module FIFO18E1 (...); + parameter ALMOST_EMPTY_OFFSET = 13'h0080; + parameter ALMOST_FULL_OFFSET = 13'h0080; + parameter integer DATA_WIDTH = 4; + parameter integer DO_REG = 1; + parameter EN_SYN = "FALSE"; + parameter FIFO_MODE = "FIFO18"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter INIT = 36'h0; + parameter SIM_DEVICE = "VIRTEX6"; + parameter SRVAL = 36'h0; + parameter IS_RDCLK_INVERTED = 1'b0; + parameter IS_RDEN_INVERTED = 1'b0; + parameter IS_RSTREG_INVERTED = 1'b0; + parameter IS_RST_INVERTED = 1'b0; + parameter IS_WRCLK_INVERTED = 1'b0; + parameter IS_WREN_INVERTED = 1'b0; + output ALMOSTEMPTY; + output ALMOSTFULL; + output [31:0] DO; + output [3:0] DOP; + output EMPTY; + output FULL; + output [11:0] RDCOUNT; + output RDERR; + output [11:0] WRCOUNT; + output WRERR; + input [31:0] DI; + input [3:0] DIP; + (* clkbuf_sink *) + (* invertible_pin = "IS_RDCLK_INVERTED" *) + input RDCLK; + (* invertible_pin = "IS_RDEN_INVERTED" *) + input RDEN; + input REGCE; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + (* invertible_pin = "IS_RSTREG_INVERTED" *) + input RSTREG; + (* clkbuf_sink *) + (* invertible_pin = "IS_WRCLK_INVERTED" *) + input WRCLK; + (* invertible_pin = "IS_WREN_INVERTED" *) + input WREN; +endmodule + +module FIFO36E1 (...); + parameter ALMOST_EMPTY_OFFSET = 13'h0080; + parameter ALMOST_FULL_OFFSET = 13'h0080; + parameter integer DATA_WIDTH = 4; + parameter integer DO_REG = 1; + parameter EN_ECC_READ = "FALSE"; + parameter EN_ECC_WRITE = "FALSE"; + parameter EN_SYN = "FALSE"; + parameter FIFO_MODE = "FIFO36"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter INIT = 72'h0; + parameter SIM_DEVICE = "VIRTEX6"; + parameter SRVAL = 72'h0; + parameter IS_RDCLK_INVERTED = 1'b0; + parameter IS_RDEN_INVERTED = 1'b0; + parameter IS_RSTREG_INVERTED = 1'b0; + parameter IS_RST_INVERTED = 1'b0; + parameter IS_WRCLK_INVERTED = 1'b0; + parameter IS_WREN_INVERTED = 1'b0; + output ALMOSTEMPTY; + output ALMOSTFULL; + output DBITERR; + output [63:0] DO; + output [7:0] DOP; + output [7:0] ECCPARITY; + output EMPTY; + output FULL; + output [12:0] RDCOUNT; + output RDERR; + output SBITERR; + output [12:0] WRCOUNT; + output WRERR; + input [63:0] DI; + input [7:0] DIP; + input INJECTDBITERR; + input INJECTSBITERR; + (* clkbuf_sink *) + (* invertible_pin = "IS_RDCLK_INVERTED" *) + input RDCLK; + (* invertible_pin = "IS_RDEN_INVERTED" *) + input RDEN; + input REGCE; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + (* invertible_pin = "IS_RSTREG_INVERTED" *) + input RSTREG; + (* clkbuf_sink *) + (* invertible_pin = "IS_WRCLK_INVERTED" *) + input WRCLK; + (* invertible_pin = "IS_WREN_INVERTED" *) + input WREN; +endmodule + +module FIFO18E2 (...); + parameter CASCADE_ORDER = "NONE"; + parameter CLOCK_DOMAINS = "INDEPENDENT"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter [35:0] INIT = 36'h000000000; + parameter [0:0] IS_RDCLK_INVERTED = 1'b0; + parameter [0:0] IS_RDEN_INVERTED = 1'b0; + parameter [0:0] IS_RSTREG_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter [0:0] IS_WRCLK_INVERTED = 1'b0; + parameter [0:0] IS_WREN_INVERTED = 1'b0; + parameter integer PROG_EMPTY_THRESH = 256; + parameter integer PROG_FULL_THRESH = 256; + parameter RDCOUNT_TYPE = "RAW_PNTR"; + parameter integer READ_WIDTH = 4; + parameter REGISTER_MODE = "UNREGISTERED"; + parameter RSTREG_PRIORITY = "RSTREG"; + parameter SLEEP_ASYNC = "FALSE"; + parameter [35:0] SRVAL = 36'h000000000; + parameter WRCOUNT_TYPE = "RAW_PNTR"; + parameter integer WRITE_WIDTH = 4; + output [31:0] CASDOUT; + output [3:0] CASDOUTP; + output CASNXTEMPTY; + output CASPRVRDEN; + output [31:0] DOUT; + output [3:0] DOUTP; + output EMPTY; + output FULL; + output PROGEMPTY; + output PROGFULL; + output [12:0] RDCOUNT; + output RDERR; + output RDRSTBUSY; + output [12:0] WRCOUNT; + output WRERR; + output WRRSTBUSY; + input [31:0] CASDIN; + input [3:0] CASDINP; + input CASDOMUX; + input CASDOMUXEN; + input CASNXTRDEN; + input CASOREGIMUX; + input CASOREGIMUXEN; + input CASPRVEMPTY; + input [31:0] DIN; + input [3:0] DINP; + (* clkbuf_sink *) + (* invertible_pin = "IS_RDCLK_INVERTED" *) + input RDCLK; + (* invertible_pin = "IS_RDEN_INVERTED" *) + input RDEN; + input REGCE; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + (* invertible_pin = "IS_RSTREG_INVERTED" *) + input RSTREG; + input SLEEP; + (* clkbuf_sink *) + (* invertible_pin = "IS_WRCLK_INVERTED" *) + input WRCLK; + (* invertible_pin = "IS_WREN_INVERTED" *) + input WREN; +endmodule + +module FIFO36E2 (...); + parameter CASCADE_ORDER = "NONE"; + parameter CLOCK_DOMAINS = "INDEPENDENT"; + parameter EN_ECC_PIPE = "FALSE"; + parameter EN_ECC_READ = "FALSE"; + parameter EN_ECC_WRITE = "FALSE"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter [71:0] INIT = 72'h000000000000000000; + parameter [0:0] IS_RDCLK_INVERTED = 1'b0; + parameter [0:0] IS_RDEN_INVERTED = 1'b0; + parameter [0:0] IS_RSTREG_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter [0:0] IS_WRCLK_INVERTED = 1'b0; + parameter [0:0] IS_WREN_INVERTED = 1'b0; + parameter integer PROG_EMPTY_THRESH = 256; + parameter integer PROG_FULL_THRESH = 256; + parameter RDCOUNT_TYPE = "RAW_PNTR"; + parameter integer READ_WIDTH = 4; + parameter REGISTER_MODE = "UNREGISTERED"; + parameter RSTREG_PRIORITY = "RSTREG"; + parameter SLEEP_ASYNC = "FALSE"; + parameter [71:0] SRVAL = 72'h000000000000000000; + parameter WRCOUNT_TYPE = "RAW_PNTR"; + parameter integer WRITE_WIDTH = 4; + output [63:0] CASDOUT; + output [7:0] CASDOUTP; + output CASNXTEMPTY; + output CASPRVRDEN; + output DBITERR; + output [63:0] DOUT; + output [7:0] DOUTP; + output [7:0] ECCPARITY; + output EMPTY; + output FULL; + output PROGEMPTY; + output PROGFULL; + output [13:0] RDCOUNT; + output RDERR; + output RDRSTBUSY; + output SBITERR; + output [13:0] WRCOUNT; + output WRERR; + output WRRSTBUSY; + input [63:0] CASDIN; + input [7:0] CASDINP; + input CASDOMUX; + input CASDOMUXEN; + input CASNXTRDEN; + input CASOREGIMUX; + input CASOREGIMUXEN; + input CASPRVEMPTY; + input [63:0] DIN; + input [7:0] DINP; + input INJECTDBITERR; + input INJECTSBITERR; + (* clkbuf_sink *) + (* invertible_pin = "IS_RDCLK_INVERTED" *) + input RDCLK; + (* invertible_pin = "IS_RDEN_INVERTED" *) + input RDEN; + input REGCE; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + (* invertible_pin = "IS_RSTREG_INVERTED" *) + input RSTREG; + input SLEEP; + (* clkbuf_sink *) + (* invertible_pin = "IS_WRCLK_INVERTED" *) + input WRCLK; + (* invertible_pin = "IS_WREN_INVERTED" *) + input WREN; +endmodule + +module RAMB18E2 (...); + parameter CASCADE_ORDER_A = "NONE"; + parameter CASCADE_ORDER_B = "NONE"; + parameter CLOCK_DOMAINS = "INDEPENDENT"; + parameter integer DOA_REG = 1; + parameter integer DOB_REG = 1; + parameter ENADDRENA = "FALSE"; + parameter ENADDRENB = "FALSE"; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [17:0] INIT_A = 18'h00000; + parameter [17:0] INIT_B = 18'h00000; + parameter INIT_FILE = "NONE"; + parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0; + parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0; + parameter [0:0] IS_ENARDEN_INVERTED = 1'b0; + parameter [0:0] IS_ENBWREN_INVERTED = 1'b0; + parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0; + parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0; + parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0; + parameter [0:0] IS_RSTREGB_INVERTED = 1'b0; + parameter RDADDRCHANGEA = "FALSE"; + parameter RDADDRCHANGEB = "FALSE"; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter RSTREG_PRIORITY_A = "RSTREG"; + parameter RSTREG_PRIORITY_B = "RSTREG"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SLEEP_ASYNC = "FALSE"; + parameter [17:0] SRVAL_A = 18'h00000; + parameter [17:0] SRVAL_B = 18'h00000; + parameter WRITE_MODE_A = "NO_CHANGE"; + parameter WRITE_MODE_B = "NO_CHANGE"; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + output [15:0] CASDOUTA; + output [15:0] CASDOUTB; + output [1:0] CASDOUTPA; + output [1:0] CASDOUTPB; + output [15:0] DOUTADOUT; + output [15:0] DOUTBDOUT; + output [1:0] DOUTPADOUTP; + output [1:0] DOUTPBDOUTP; + input [13:0] ADDRARDADDR; + input [13:0] ADDRBWRADDR; + input ADDRENA; + input ADDRENB; + input CASDIMUXA; + input CASDIMUXB; + input [15:0] CASDINA; + input [15:0] CASDINB; + input [1:0] CASDINPA; + input [1:0] CASDINPB; + input CASDOMUXA; + input CASDOMUXB; + input CASDOMUXEN_A; + input CASDOMUXEN_B; + input CASOREGIMUXA; + input CASOREGIMUXB; + input CASOREGIMUXEN_A; + input CASOREGIMUXEN_B; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) + input CLKARDCLK; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) + input CLKBWRCLK; + input [15:0] DINADIN; + input [15:0] DINBDIN; + input [1:0] DINPADINP; + input [1:0] DINPBDINP; + (* invertible_pin = "IS_ENARDEN_INVERTED" *) + input ENARDEN; + (* invertible_pin = "IS_ENBWREN_INVERTED" *) + input ENBWREN; + input REGCEAREGCE; + input REGCEB; + (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) + input RSTRAMARSTRAM; + (* invertible_pin = "IS_RSTRAMB_INVERTED" *) + input RSTRAMB; + (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) + input RSTREGARSTREG; + (* invertible_pin = "IS_RSTREGB_INVERTED" *) + input RSTREGB; + input SLEEP; + input [1:0] WEA; + input [3:0] WEBWE; +endmodule + +module RAMB36E2 (...); + parameter CASCADE_ORDER_A = "NONE"; + parameter CASCADE_ORDER_B = "NONE"; + parameter CLOCK_DOMAINS = "INDEPENDENT"; + parameter integer DOA_REG = 1; + parameter integer DOB_REG = 1; + parameter ENADDRENA = "FALSE"; + parameter ENADDRENB = "FALSE"; + parameter EN_ECC_PIPE = "FALSE"; + parameter EN_ECC_READ = "FALSE"; + parameter EN_ECC_WRITE = "FALSE"; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [35:0] INIT_A = 36'h000000000; + parameter [35:0] INIT_B = 36'h000000000; + parameter INIT_FILE = "NONE"; + parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0; + parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0; + parameter [0:0] IS_ENARDEN_INVERTED = 1'b0; + parameter [0:0] IS_ENBWREN_INVERTED = 1'b0; + parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0; + parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0; + parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0; + parameter [0:0] IS_RSTREGB_INVERTED = 1'b0; + parameter RDADDRCHANGEA = "FALSE"; + parameter RDADDRCHANGEB = "FALSE"; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter RSTREG_PRIORITY_A = "RSTREG"; + parameter RSTREG_PRIORITY_B = "RSTREG"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SLEEP_ASYNC = "FALSE"; + parameter [35:0] SRVAL_A = 36'h000000000; + parameter [35:0] SRVAL_B = 36'h000000000; + parameter WRITE_MODE_A = "NO_CHANGE"; + parameter WRITE_MODE_B = "NO_CHANGE"; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + output [31:0] CASDOUTA; + output [31:0] CASDOUTB; + output [3:0] CASDOUTPA; + output [3:0] CASDOUTPB; + output CASOUTDBITERR; + output CASOUTSBITERR; + output DBITERR; + output [31:0] DOUTADOUT; + output [31:0] DOUTBDOUT; + output [3:0] DOUTPADOUTP; + output [3:0] DOUTPBDOUTP; + output [7:0] ECCPARITY; + output [8:0] RDADDRECC; + output SBITERR; + input [14:0] ADDRARDADDR; + input [14:0] ADDRBWRADDR; + input ADDRENA; + input ADDRENB; + input CASDIMUXA; + input CASDIMUXB; + input [31:0] CASDINA; + input [31:0] CASDINB; + input [3:0] CASDINPA; + input [3:0] CASDINPB; + input CASDOMUXA; + input CASDOMUXB; + input CASDOMUXEN_A; + input CASDOMUXEN_B; + input CASINDBITERR; + input CASINSBITERR; + input CASOREGIMUXA; + input CASOREGIMUXB; + input CASOREGIMUXEN_A; + input CASOREGIMUXEN_B; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) + input CLKARDCLK; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) + input CLKBWRCLK; + input [31:0] DINADIN; + input [31:0] DINBDIN; + input [3:0] DINPADINP; + input [3:0] DINPBDINP; + input ECCPIPECE; + (* invertible_pin = "IS_ENARDEN_INVERTED" *) + input ENARDEN; + (* invertible_pin = "IS_ENBWREN_INVERTED" *) + input ENBWREN; + input INJECTDBITERR; + input INJECTSBITERR; + input REGCEAREGCE; + input REGCEB; + (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) + input RSTRAMARSTRAM; + (* invertible_pin = "IS_RSTRAMB_INVERTED" *) + input RSTRAMB; + (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) + input RSTREGARSTREG; + (* invertible_pin = "IS_RSTREGB_INVERTED" *) + input RSTREGB; + input SLEEP; + input [3:0] WEA; + input [7:0] WEBWE; +endmodule + +module URAM288 (...); + parameter integer AUTO_SLEEP_LATENCY = 8; + parameter integer AVG_CONS_INACTIVE_CYCLES = 10; + parameter BWE_MODE_A = "PARITY_INTERLEAVED"; + parameter BWE_MODE_B = "PARITY_INTERLEAVED"; + parameter CASCADE_ORDER_A = "NONE"; + parameter CASCADE_ORDER_B = "NONE"; + parameter EN_AUTO_SLEEP_MODE = "FALSE"; + parameter EN_ECC_RD_A = "FALSE"; + parameter EN_ECC_RD_B = "FALSE"; + parameter EN_ECC_WR_A = "FALSE"; + parameter EN_ECC_WR_B = "FALSE"; + parameter IREG_PRE_A = "FALSE"; + parameter IREG_PRE_B = "FALSE"; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [0:0] IS_EN_A_INVERTED = 1'b0; + parameter [0:0] IS_EN_B_INVERTED = 1'b0; + parameter [0:0] IS_RDB_WR_A_INVERTED = 1'b0; + parameter [0:0] IS_RDB_WR_B_INVERTED = 1'b0; + parameter [0:0] IS_RST_A_INVERTED = 1'b0; + parameter [0:0] IS_RST_B_INVERTED = 1'b0; + parameter MATRIX_ID = "NONE"; + parameter integer NUM_UNIQUE_SELF_ADDR_A = 1; + parameter integer NUM_UNIQUE_SELF_ADDR_B = 1; + parameter integer NUM_URAM_IN_MATRIX = 1; + parameter OREG_A = "FALSE"; + parameter OREG_B = "FALSE"; + parameter OREG_ECC_A = "FALSE"; + parameter OREG_ECC_B = "FALSE"; + parameter REG_CAS_A = "FALSE"; + parameter REG_CAS_B = "FALSE"; + parameter RST_MODE_A = "SYNC"; + parameter RST_MODE_B = "SYNC"; + parameter [10:0] SELF_ADDR_A = 11'h000; + parameter [10:0] SELF_ADDR_B = 11'h000; + parameter [10:0] SELF_MASK_A = 11'h7FF; + parameter [10:0] SELF_MASK_B = 11'h7FF; + parameter USE_EXT_CE_A = "FALSE"; + parameter USE_EXT_CE_B = "FALSE"; + output [22:0] CAS_OUT_ADDR_A; + output [22:0] CAS_OUT_ADDR_B; + output [8:0] CAS_OUT_BWE_A; + output [8:0] CAS_OUT_BWE_B; + output CAS_OUT_DBITERR_A; + output CAS_OUT_DBITERR_B; + output [71:0] CAS_OUT_DIN_A; + output [71:0] CAS_OUT_DIN_B; + output [71:0] CAS_OUT_DOUT_A; + output [71:0] CAS_OUT_DOUT_B; + output CAS_OUT_EN_A; + output CAS_OUT_EN_B; + output CAS_OUT_RDACCESS_A; + output CAS_OUT_RDACCESS_B; + output CAS_OUT_RDB_WR_A; + output CAS_OUT_RDB_WR_B; + output CAS_OUT_SBITERR_A; + output CAS_OUT_SBITERR_B; + output DBITERR_A; + output DBITERR_B; + output [71:0] DOUT_A; + output [71:0] DOUT_B; + output RDACCESS_A; + output RDACCESS_B; + output SBITERR_A; + output SBITERR_B; + input [22:0] ADDR_A; + input [22:0] ADDR_B; + input [8:0] BWE_A; + input [8:0] BWE_B; + input [22:0] CAS_IN_ADDR_A; + input [22:0] CAS_IN_ADDR_B; + input [8:0] CAS_IN_BWE_A; + input [8:0] CAS_IN_BWE_B; + input CAS_IN_DBITERR_A; + input CAS_IN_DBITERR_B; + input [71:0] CAS_IN_DIN_A; + input [71:0] CAS_IN_DIN_B; + input [71:0] CAS_IN_DOUT_A; + input [71:0] CAS_IN_DOUT_B; + input CAS_IN_EN_A; + input CAS_IN_EN_B; + input CAS_IN_RDACCESS_A; + input CAS_IN_RDACCESS_B; + input CAS_IN_RDB_WR_A; + input CAS_IN_RDB_WR_B; + input CAS_IN_SBITERR_A; + input CAS_IN_SBITERR_B; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + input [71:0] DIN_A; + input [71:0] DIN_B; + (* invertible_pin = "IS_EN_A_INVERTED" *) + input EN_A; + (* invertible_pin = "IS_EN_B_INVERTED" *) + input EN_B; + input INJECT_DBITERR_A; + input INJECT_DBITERR_B; + input INJECT_SBITERR_A; + input INJECT_SBITERR_B; + input OREG_CE_A; + input OREG_CE_B; + input OREG_ECC_CE_A; + input OREG_ECC_CE_B; + (* invertible_pin = "IS_RDB_WR_A_INVERTED" *) + input RDB_WR_A; + (* invertible_pin = "IS_RDB_WR_B_INVERTED" *) + input RDB_WR_B; + (* invertible_pin = "IS_RST_A_INVERTED" *) + input RST_A; + (* invertible_pin = "IS_RST_B_INVERTED" *) + input RST_B; + input SLEEP; +endmodule + +module URAM288_BASE (...); + parameter integer AUTO_SLEEP_LATENCY = 8; + parameter integer AVG_CONS_INACTIVE_CYCLES = 10; + parameter BWE_MODE_A = "PARITY_INTERLEAVED"; + parameter BWE_MODE_B = "PARITY_INTERLEAVED"; + parameter EN_AUTO_SLEEP_MODE = "FALSE"; + parameter EN_ECC_RD_A = "FALSE"; + parameter EN_ECC_RD_B = "FALSE"; + parameter EN_ECC_WR_A = "FALSE"; + parameter EN_ECC_WR_B = "FALSE"; + parameter IREG_PRE_A = "FALSE"; + parameter IREG_PRE_B = "FALSE"; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [0:0] IS_EN_A_INVERTED = 1'b0; + parameter [0:0] IS_EN_B_INVERTED = 1'b0; + parameter [0:0] IS_RDB_WR_A_INVERTED = 1'b0; + parameter [0:0] IS_RDB_WR_B_INVERTED = 1'b0; + parameter [0:0] IS_RST_A_INVERTED = 1'b0; + parameter [0:0] IS_RST_B_INVERTED = 1'b0; + parameter OREG_A = "FALSE"; + parameter OREG_B = "FALSE"; + parameter OREG_ECC_A = "FALSE"; + parameter OREG_ECC_B = "FALSE"; + parameter RST_MODE_A = "SYNC"; + parameter RST_MODE_B = "SYNC"; + parameter USE_EXT_CE_A = "FALSE"; + parameter USE_EXT_CE_B = "FALSE"; + output DBITERR_A; + output DBITERR_B; + output [71:0] DOUT_A; + output [71:0] DOUT_B; + output SBITERR_A; + output SBITERR_B; + input [22:0] ADDR_A; + input [22:0] ADDR_B; + input [8:0] BWE_A; + input [8:0] BWE_B; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + input [71:0] DIN_A; + input [71:0] DIN_B; + (* invertible_pin = "IS_EN_A_INVERTED" *) + input EN_A; + (* invertible_pin = "IS_EN_B_INVERTED" *) + input EN_B; + input INJECT_DBITERR_A; + input INJECT_DBITERR_B; + input INJECT_SBITERR_A; + input INJECT_SBITERR_B; + input OREG_CE_A; + input OREG_CE_B; + input OREG_ECC_CE_A; + input OREG_ECC_CE_B; + (* invertible_pin = "IS_RDB_WR_A_INVERTED" *) + input RDB_WR_A; + (* invertible_pin = "IS_RDB_WR_B_INVERTED" *) + input RDB_WR_B; + (* invertible_pin = "IS_RST_A_INVERTED" *) + input RST_A; + (* invertible_pin = "IS_RST_B_INVERTED" *) + input RST_B; + input SLEEP; +endmodule + +module DSP48E (...); + parameter SIM_MODE = "SAFE"; + parameter integer ACASCREG = 1; + parameter integer ALUMODEREG = 1; + parameter integer AREG = 1; + parameter AUTORESET_PATTERN_DETECT = "FALSE"; + parameter AUTORESET_PATTERN_DETECT_OPTINV = "MATCH"; + parameter A_INPUT = "DIRECT"; + parameter integer BCASCREG = 1; + parameter integer BREG = 1; + parameter B_INPUT = "DIRECT"; + parameter integer CARRYINREG = 1; + parameter integer CARRYINSELREG = 1; + parameter integer CREG = 1; + parameter [47:0] MASK = 48'h3FFFFFFFFFFF; + parameter integer MREG = 1; + parameter integer MULTCARRYINREG = 1; + parameter integer OPMODEREG = 1; + parameter [47:0] PATTERN = 48'h000000000000; + parameter integer PREG = 1; + parameter SEL_MASK = "MASK"; + parameter SEL_PATTERN = "PATTERN"; + parameter SEL_ROUNDING_MASK = "SEL_MASK"; + parameter USE_MULT = "MULT_S"; + parameter USE_PATTERN_DETECT = "NO_PATDET"; + parameter USE_SIMD = "ONE48"; + output [29:0] ACOUT; + output [17:0] BCOUT; + output CARRYCASCOUT; + output [3:0] CARRYOUT; + output MULTSIGNOUT; + output OVERFLOW; + output [47:0] P; + output PATTERNBDETECT; + output PATTERNDETECT; + output [47:0] PCOUT; + output UNDERFLOW; + input [29:0] A; + input [29:0] ACIN; + input [3:0] ALUMODE; + input [17:0] B; + input [17:0] BCIN; + input [47:0] C; + input CARRYCASCIN; + input CARRYIN; + input [2:0] CARRYINSEL; + input CEA1; + input CEA2; + input CEALUMODE; + input CEB1; + input CEB2; + input CEC; + input CECARRYIN; + input CECTRL; + input CEM; + input CEMULTCARRYIN; + input CEP; + (* clkbuf_sink *) + input CLK; + input MULTSIGNIN; + input [6:0] OPMODE; + input [47:0] PCIN; + input RSTA; + input RSTALLCARRYIN; + input RSTALUMODE; + input RSTB; + input RSTC; + input RSTCTRL; + input RSTM; + input RSTP; +endmodule + +module DSP48E2 (...); + parameter integer ACASCREG = 1; + parameter integer ADREG = 1; + parameter integer ALUMODEREG = 1; + parameter AMULTSEL = "A"; + parameter integer AREG = 1; + parameter AUTORESET_PATDET = "NO_RESET"; + parameter AUTORESET_PRIORITY = "RESET"; + parameter A_INPUT = "DIRECT"; + parameter integer BCASCREG = 1; + parameter BMULTSEL = "B"; + parameter integer BREG = 1; + parameter B_INPUT = "DIRECT"; + parameter integer CARRYINREG = 1; + parameter integer CARRYINSELREG = 1; + parameter integer CREG = 1; + parameter integer DREG = 1; + parameter integer INMODEREG = 1; + parameter [3:0] IS_ALUMODE_INVERTED = 4'b0000; + parameter [0:0] IS_CARRYIN_INVERTED = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [4:0] IS_INMODE_INVERTED = 5'b00000; + parameter [8:0] IS_OPMODE_INVERTED = 9'b000000000; + parameter [0:0] IS_RSTALLCARRYIN_INVERTED = 1'b0; + parameter [0:0] IS_RSTALUMODE_INVERTED = 1'b0; + parameter [0:0] IS_RSTA_INVERTED = 1'b0; + parameter [0:0] IS_RSTB_INVERTED = 1'b0; + parameter [0:0] IS_RSTCTRL_INVERTED = 1'b0; + parameter [0:0] IS_RSTC_INVERTED = 1'b0; + parameter [0:0] IS_RSTD_INVERTED = 1'b0; + parameter [0:0] IS_RSTINMODE_INVERTED = 1'b0; + parameter [0:0] IS_RSTM_INVERTED = 1'b0; + parameter [0:0] IS_RSTP_INVERTED = 1'b0; + parameter [47:0] MASK = 48'h3FFFFFFFFFFF; + parameter integer MREG = 1; + parameter integer OPMODEREG = 1; + parameter [47:0] PATTERN = 48'h000000000000; + parameter PREADDINSEL = "A"; + parameter integer PREG = 1; + parameter [47:0] RND = 48'h000000000000; + parameter SEL_MASK = "MASK"; + parameter SEL_PATTERN = "PATTERN"; + parameter USE_MULT = "MULTIPLY"; + parameter USE_PATTERN_DETECT = "NO_PATDET"; + parameter USE_SIMD = "ONE48"; + parameter USE_WIDEXOR = "FALSE"; + parameter XORSIMD = "XOR24_48_96"; + output [29:0] ACOUT; + output [17:0] BCOUT; + output CARRYCASCOUT; + output [3:0] CARRYOUT; + output MULTSIGNOUT; + output OVERFLOW; + output [47:0] P; + output PATTERNBDETECT; + output PATTERNDETECT; + output [47:0] PCOUT; + output UNDERFLOW; + output [7:0] XOROUT; + input [29:0] A; + input [29:0] ACIN; + (* invertible_pin = "IS_ALUMODE_INVERTED" *) + input [3:0] ALUMODE; + input [17:0] B; + input [17:0] BCIN; + input [47:0] C; + input CARRYCASCIN; + (* invertible_pin = "IS_CARRYIN_INVERTED" *) + input CARRYIN; + input [2:0] CARRYINSEL; + input CEA1; + input CEA2; + input CEAD; + input CEALUMODE; + input CEB1; + input CEB2; + input CEC; + input CECARRYIN; + input CECTRL; + input CED; + input CEINMODE; + input CEM; + input CEP; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + input [26:0] D; + (* invertible_pin = "IS_INMODE_INVERTED" *) + input [4:0] INMODE; + input MULTSIGNIN; + (* invertible_pin = "IS_OPMODE_INVERTED" *) + input [8:0] OPMODE; + input [47:0] PCIN; + (* invertible_pin = "IS_RSTA_INVERTED" *) + input RSTA; + (* invertible_pin = "IS_RSTALLCARRYIN_INVERTED" *) + input RSTALLCARRYIN; + (* invertible_pin = "IS_RSTALUMODE_INVERTED" *) + input RSTALUMODE; + (* invertible_pin = "IS_RSTB_INVERTED" *) + input RSTB; + (* invertible_pin = "IS_RSTC_INVERTED" *) + input RSTC; + (* invertible_pin = "IS_RSTCTRL_INVERTED" *) + input RSTCTRL; + (* invertible_pin = "IS_RSTD_INVERTED" *) + input RSTD; + (* invertible_pin = "IS_RSTINMODE_INVERTED" *) + input RSTINMODE; + (* invertible_pin = "IS_RSTM_INVERTED" *) + input RSTM; + (* invertible_pin = "IS_RSTP_INVERTED" *) + input RSTP; +endmodule + +module FDDRCPE (...); + parameter INIT = 1'b0; + (* clkbuf_sink *) + input C0; + (* clkbuf_sink *) + input C1; + input CE; + input D0; + input D1; + input CLR; + input PRE; + output Q; +endmodule + +module FDDRRSE (...); + parameter INIT = 1'b0; + output Q; + (* clkbuf_sink *) + input C0; + (* clkbuf_sink *) + input C1; + input CE; + input D0; + input D1; + input R; + input S; +endmodule + +module IFDDRCPE (...); + output Q0; + output Q1; + (* clkbuf_sink *) + input C0; + (* clkbuf_sink *) + input C1; + input CE; + input CLR; + (* iopad_external_pin *) + input D; + input PRE; +endmodule + +module IFDDRRSE (...); + output Q0; + output Q1; + (* clkbuf_sink *) + input C0; + (* clkbuf_sink *) + input C1; + input CE; + (* iopad_external_pin *) + input D; + input R; + input S; +endmodule + +module OFDDRCPE (...); + (* iopad_external_pin *) + output Q; + (* clkbuf_sink *) + input C0; + (* clkbuf_sink *) + input C1; + input CE; + input CLR; + input D0; + input D1; + input PRE; +endmodule + +module OFDDRRSE (...); + (* iopad_external_pin *) + output Q; + (* clkbuf_sink *) + input C0; + (* clkbuf_sink *) + input C1; + input CE; + input D0; + input D1; + input R; + input S; +endmodule + +module OFDDRTCPE (...); + (* iopad_external_pin *) + output O; + (* clkbuf_sink *) + input C0; + (* clkbuf_sink *) + input C1; + input CE; + input CLR; + input D0; + input D1; + input PRE; + input T; +endmodule + +module OFDDRTRSE (...); + (* iopad_external_pin *) + output O; + (* clkbuf_sink *) + input C0; + (* clkbuf_sink *) + input C1; + input CE; + input D0; + input D1; + input R; + input S; + input T; +endmodule + +module IDDR2 (...); + parameter DDR_ALIGNMENT = "NONE"; + parameter [0:0] INIT_Q0 = 1'b0; + parameter [0:0] INIT_Q1 = 1'b0; + parameter SRTYPE = "SYNC"; + output Q0; + output Q1; + (* clkbuf_sink *) + input C0; + (* clkbuf_sink *) + input C1; + input CE; + input D; + input R; + input S; +endmodule + +module ODDR2 (...); + parameter DDR_ALIGNMENT = "NONE"; + parameter [0:0] INIT = 1'b0; + parameter SRTYPE = "SYNC"; + output Q; + (* clkbuf_sink *) + input C0; + (* clkbuf_sink *) + input C1; + input CE; + input D0; + input D1; + input R; + input S; +endmodule + +module IDDR (...); + parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; + parameter INIT_Q1 = 1'b0; + parameter INIT_Q2 = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter SRTYPE = "SYNC"; + parameter MSGON = "TRUE"; + parameter XON = "TRUE"; + output Q1; + output Q2; + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C; + input CE; + (* invertible_pin = "IS_D_INVERTED" *) + input D; + input R; + input S; +endmodule + +module IDDR_2CLK (...); + parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; + parameter INIT_Q1 = 1'b0; + parameter INIT_Q2 = 1'b0; + parameter [0:0] IS_CB_INVERTED = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter SRTYPE = "SYNC"; + output Q1; + output Q2; + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C; + (* clkbuf_sink *) + (* invertible_pin = "IS_CB_INVERTED" *) + input CB; + input CE; + (* invertible_pin = "IS_D_INVERTED" *) + input D; + input R; + input S; +endmodule + +module ODDR (...); + parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; + parameter INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D1_INVERTED = 1'b0; + parameter [0:0] IS_D2_INVERTED = 1'b0; + parameter SRTYPE = "SYNC"; + parameter MSGON = "TRUE"; + parameter XON = "TRUE"; + output Q; + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C; + input CE; + (* invertible_pin = "IS_D1_INVERTED" *) + input D1; + (* invertible_pin = "IS_D2_INVERTED" *) + input D2; + input R; + input S; +endmodule + +(* keep *) +module IDELAYCTRL (...); + parameter SIM_DEVICE = "7SERIES"; + output RDY; + (* clkbuf_sink *) + input REFCLK; + input RST; +endmodule + +module IDELAY (...); + parameter IOBDELAY_TYPE = "DEFAULT"; + parameter integer IOBDELAY_VALUE = 0; + output O; + (* clkbuf_sink *) + input C; + input CE; + input I; + input INC; + input RST; +endmodule + +module ISERDES (...); + parameter BITSLIP_ENABLE = "FALSE"; + parameter DATA_RATE = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter [0:0] INIT_Q1 = 1'b0; + parameter [0:0] INIT_Q2 = 1'b0; + parameter [0:0] INIT_Q3 = 1'b0; + parameter [0:0] INIT_Q4 = 1'b0; + parameter INTERFACE_TYPE = "MEMORY"; + parameter IOBDELAY = "NONE"; + parameter IOBDELAY_TYPE = "DEFAULT"; + parameter integer IOBDELAY_VALUE = 0; + parameter integer NUM_CE = 2; + parameter SERDES_MODE = "MASTER"; + parameter integer SIM_DELAY_D = 0; + parameter integer SIM_SETUP_D_CLK = 0; + parameter integer SIM_HOLD_D_CLK = 0; + parameter [0:0] SRVAL_Q1 = 1'b0; + parameter [0:0] SRVAL_Q2 = 1'b0; + parameter [0:0] SRVAL_Q3 = 1'b0; + parameter [0:0] SRVAL_Q4 = 1'b0; + output O; + output Q1; + output Q2; + output Q3; + output Q4; + output Q5; + output Q6; + output SHIFTOUT1; + output SHIFTOUT2; + input BITSLIP; + input CE1; + input CE2; + (* clkbuf_sink *) + input CLK; + (* clkbuf_sink *) + input CLKDIV; + input D; + input DLYCE; + input DLYINC; + input DLYRST; + (* clkbuf_sink *) + input OCLK; + input REV; + input SHIFTIN1; + input SHIFTIN2; + input SR; +endmodule + +module OSERDES (...); + parameter DATA_RATE_OQ = "DDR"; + parameter DATA_RATE_TQ = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter [0:0] INIT_OQ = 1'b0; + parameter [0:0] INIT_TQ = 1'b0; + parameter SERDES_MODE = "MASTER"; + parameter [0:0] SRVAL_OQ = 1'b0; + parameter [0:0] SRVAL_TQ = 1'b0; + parameter integer TRISTATE_WIDTH = 4; + output OQ; + output SHIFTOUT1; + output SHIFTOUT2; + output TQ; + (* clkbuf_sink *) + input CLK; + (* clkbuf_sink *) + input CLKDIV; + input D1; + input D2; + input D3; + input D4; + input D5; + input D6; + input OCE; + input REV; + input SHIFTIN1; + input SHIFTIN2; + input SR; + input T1; + input T2; + input T3; + input T4; + input TCE; +endmodule + +module IODELAY (...); + parameter DELAY_SRC = "I"; + parameter HIGH_PERFORMANCE_MODE = "TRUE"; + parameter IDELAY_TYPE = "DEFAULT"; + parameter integer IDELAY_VALUE = 0; + parameter integer ODELAY_VALUE = 0; + parameter real REFCLK_FREQUENCY = 200.0; + parameter SIGNAL_PATTERN = "DATA"; + output DATAOUT; + (* clkbuf_sink *) + input C; + input CE; + input DATAIN; + input IDATAIN; + input INC; + input ODATAIN; + input RST; + input T; +endmodule + +module ISERDES_NODELAY (...); + parameter BITSLIP_ENABLE = "FALSE"; + parameter DATA_RATE = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter INIT_Q1 = 1'b0; + parameter INIT_Q2 = 1'b0; + parameter INIT_Q3 = 1'b0; + parameter INIT_Q4 = 1'b0; + parameter INTERFACE_TYPE = "MEMORY"; + parameter integer NUM_CE = 2; + parameter SERDES_MODE = "MASTER"; + output Q1; + output Q2; + output Q3; + output Q4; + output Q5; + output Q6; + output SHIFTOUT1; + output SHIFTOUT2; + input BITSLIP; + input CE1; + input CE2; + (* clkbuf_sink *) + input CLK; + (* clkbuf_sink *) + input CLKB; + (* clkbuf_sink *) + input CLKDIV; + input D; + (* clkbuf_sink *) + input OCLK; + input RST; + input SHIFTIN1; + input SHIFTIN2; +endmodule + +module IODELAYE1 (...); + parameter CINVCTRL_SEL = "FALSE"; + parameter DELAY_SRC = "I"; + parameter HIGH_PERFORMANCE_MODE = "FALSE"; + parameter IDELAY_TYPE = "DEFAULT"; + parameter integer IDELAY_VALUE = 0; + parameter ODELAY_TYPE = "FIXED"; + parameter integer ODELAY_VALUE = 0; + parameter real REFCLK_FREQUENCY = 200.0; + parameter SIGNAL_PATTERN = "DATA"; + output [4:0] CNTVALUEOUT; + output DATAOUT; + (* clkbuf_sink *) + input C; + input CE; + input CINVCTRL; + input CLKIN; + input [4:0] CNTVALUEIN; + input DATAIN; + input IDATAIN; + input INC; + input ODATAIN; + input RST; + input T; +endmodule + +module ISERDESE1 (...); + parameter DATA_RATE = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter DYN_CLKDIV_INV_EN = "FALSE"; + parameter DYN_CLK_INV_EN = "FALSE"; + parameter [0:0] INIT_Q1 = 1'b0; + parameter [0:0] INIT_Q2 = 1'b0; + parameter [0:0] INIT_Q3 = 1'b0; + parameter [0:0] INIT_Q4 = 1'b0; + parameter INTERFACE_TYPE = "MEMORY"; + parameter integer NUM_CE = 2; + parameter IOBDELAY = "NONE"; + parameter OFB_USED = "FALSE"; + parameter SERDES_MODE = "MASTER"; + parameter [0:0] SRVAL_Q1 = 1'b0; + parameter [0:0] SRVAL_Q2 = 1'b0; + parameter [0:0] SRVAL_Q3 = 1'b0; + parameter [0:0] SRVAL_Q4 = 1'b0; + output O; + output Q1; + output Q2; + output Q3; + output Q4; + output Q5; + output Q6; + output SHIFTOUT1; + output SHIFTOUT2; + input BITSLIP; + input CE1; + input CE2; + (* clkbuf_sink *) + input CLK; + (* clkbuf_sink *) + input CLKB; + (* clkbuf_sink *) + input CLKDIV; + input D; + input DDLY; + input DYNCLKDIVSEL; + input DYNCLKSEL; + (* clkbuf_sink *) + input OCLK; + input OFB; + input RST; + input SHIFTIN1; + input SHIFTIN2; +endmodule + +module OSERDESE1 (...); + parameter DATA_RATE_OQ = "DDR"; + parameter DATA_RATE_TQ = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter integer DDR3_DATA = 1; + parameter [0:0] INIT_OQ = 1'b0; + parameter [0:0] INIT_TQ = 1'b0; + parameter INTERFACE_TYPE = "DEFAULT"; + parameter integer ODELAY_USED = 0; + parameter SERDES_MODE = "MASTER"; + parameter [0:0] SRVAL_OQ = 1'b0; + parameter [0:0] SRVAL_TQ = 1'b0; + parameter integer TRISTATE_WIDTH = 4; + output OCBEXTEND; + output OFB; + output OQ; + output SHIFTOUT1; + output SHIFTOUT2; + output TFB; + output TQ; + (* clkbuf_sink *) + input CLK; + (* clkbuf_sink *) + input CLKDIV; + input CLKPERF; + input CLKPERFDELAY; + input D1; + input D2; + input D3; + input D4; + input D5; + input D6; + input OCE; + input ODV; + input RST; + input SHIFTIN1; + input SHIFTIN2; + input T1; + input T2; + input T3; + input T4; + input TCE; + input WC; +endmodule + +module IDELAYE2 (...); + parameter CINVCTRL_SEL = "FALSE"; + parameter DELAY_SRC = "IDATAIN"; + parameter HIGH_PERFORMANCE_MODE = "FALSE"; + parameter IDELAY_TYPE = "FIXED"; + parameter integer IDELAY_VALUE = 0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_DATAIN_INVERTED = 1'b0; + parameter [0:0] IS_IDATAIN_INVERTED = 1'b0; + parameter PIPE_SEL = "FALSE"; + parameter real REFCLK_FREQUENCY = 200.0; + parameter SIGNAL_PATTERN = "DATA"; + parameter integer SIM_DELAY_D = 0; + output [4:0] CNTVALUEOUT; + output DATAOUT; + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C; + input CE; + input CINVCTRL; + input [4:0] CNTVALUEIN; + (* invertible_pin = "IS_DATAIN_INVERTED" *) + input DATAIN; + (* invertible_pin = "IS_IDATAIN_INVERTED" *) + input IDATAIN; + input INC; + input LD; + input LDPIPEEN; + input REGRST; +endmodule + +module ODELAYE2 (...); + parameter CINVCTRL_SEL = "FALSE"; + parameter DELAY_SRC = "ODATAIN"; + parameter HIGH_PERFORMANCE_MODE = "FALSE"; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_ODATAIN_INVERTED = 1'b0; + parameter ODELAY_TYPE = "FIXED"; + parameter integer ODELAY_VALUE = 0; + parameter PIPE_SEL = "FALSE"; + parameter real REFCLK_FREQUENCY = 200.0; + parameter SIGNAL_PATTERN = "DATA"; + parameter integer SIM_DELAY_D = 0; + output [4:0] CNTVALUEOUT; + output DATAOUT; + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C; + input CE; + input CINVCTRL; + input CLKIN; + input [4:0] CNTVALUEIN; + input INC; + input LD; + input LDPIPEEN; + (* invertible_pin = "IS_ODATAIN_INVERTED" *) + input ODATAIN; + input REGRST; +endmodule + +module ISERDESE2 (...); + parameter DATA_RATE = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter DYN_CLKDIV_INV_EN = "FALSE"; + parameter DYN_CLK_INV_EN = "FALSE"; + parameter [0:0] INIT_Q1 = 1'b0; + parameter [0:0] INIT_Q2 = 1'b0; + parameter [0:0] INIT_Q3 = 1'b0; + parameter [0:0] INIT_Q4 = 1'b0; + parameter INTERFACE_TYPE = "MEMORY"; + parameter IOBDELAY = "NONE"; + parameter [0:0] IS_CLKB_INVERTED = 1'b0; + parameter [0:0] IS_CLKDIVP_INVERTED = 1'b0; + parameter [0:0] IS_CLKDIV_INVERTED = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_OCLKB_INVERTED = 1'b0; + parameter [0:0] IS_OCLK_INVERTED = 1'b0; + parameter integer NUM_CE = 2; + parameter OFB_USED = "FALSE"; + parameter SERDES_MODE = "MASTER"; + parameter [0:0] SRVAL_Q1 = 1'b0; + parameter [0:0] SRVAL_Q2 = 1'b0; + parameter [0:0] SRVAL_Q3 = 1'b0; + parameter [0:0] SRVAL_Q4 = 1'b0; + output O; + output Q1; + output Q2; + output Q3; + output Q4; + output Q5; + output Q6; + output Q7; + output Q8; + output SHIFTOUT1; + output SHIFTOUT2; + input BITSLIP; + input CE1; + input CE2; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKB_INVERTED" *) + input CLKB; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKDIV_INVERTED" *) + input CLKDIV; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKDIVP_INVERTED" *) + input CLKDIVP; + (* invertible_pin = "IS_D_INVERTED" *) + input D; + input DDLY; + input DYNCLKDIVSEL; + input DYNCLKSEL; + (* clkbuf_sink *) + (* invertible_pin = "IS_OCLK_INVERTED" *) + input OCLK; + (* clkbuf_sink *) + (* invertible_pin = "IS_OCLKB_INVERTED" *) + input OCLKB; + input OFB; + input RST; + input SHIFTIN1; + input SHIFTIN2; +endmodule + +module OSERDESE2 (...); + parameter DATA_RATE_OQ = "DDR"; + parameter DATA_RATE_TQ = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter [0:0] INIT_OQ = 1'b0; + parameter [0:0] INIT_TQ = 1'b0; + parameter [0:0] IS_CLKDIV_INVERTED = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [0:0] IS_D1_INVERTED = 1'b0; + parameter [0:0] IS_D2_INVERTED = 1'b0; + parameter [0:0] IS_D3_INVERTED = 1'b0; + parameter [0:0] IS_D4_INVERTED = 1'b0; + parameter [0:0] IS_D5_INVERTED = 1'b0; + parameter [0:0] IS_D6_INVERTED = 1'b0; + parameter [0:0] IS_D7_INVERTED = 1'b0; + parameter [0:0] IS_D8_INVERTED = 1'b0; + parameter [0:0] IS_T1_INVERTED = 1'b0; + parameter [0:0] IS_T2_INVERTED = 1'b0; + parameter [0:0] IS_T3_INVERTED = 1'b0; + parameter [0:0] IS_T4_INVERTED = 1'b0; + parameter SERDES_MODE = "MASTER"; + parameter [0:0] SRVAL_OQ = 1'b0; + parameter [0:0] SRVAL_TQ = 1'b0; + parameter TBYTE_CTL = "FALSE"; + parameter TBYTE_SRC = "FALSE"; + parameter integer TRISTATE_WIDTH = 4; + output OFB; + output OQ; + output SHIFTOUT1; + output SHIFTOUT2; + output TBYTEOUT; + output TFB; + output TQ; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKDIV_INVERTED" *) + input CLKDIV; + (* invertible_pin = "IS_D1_INVERTED" *) + input D1; + (* invertible_pin = "IS_D2_INVERTED" *) + input D2; + (* invertible_pin = "IS_D3_INVERTED" *) + input D3; + (* invertible_pin = "IS_D4_INVERTED" *) + input D4; + (* invertible_pin = "IS_D5_INVERTED" *) + input D5; + (* invertible_pin = "IS_D6_INVERTED" *) + input D6; + (* invertible_pin = "IS_D7_INVERTED" *) + input D7; + (* invertible_pin = "IS_D8_INVERTED" *) + input D8; + input OCE; + input RST; + input SHIFTIN1; + input SHIFTIN2; + (* invertible_pin = "IS_T1_INVERTED" *) + input T1; + (* invertible_pin = "IS_T2_INVERTED" *) + input T2; + (* invertible_pin = "IS_T3_INVERTED" *) + input T3; + (* invertible_pin = "IS_T4_INVERTED" *) + input T4; + input TBYTEIN; + input TCE; +endmodule + +(* keep *) +module PHASER_IN (...); + parameter integer CLKOUT_DIV = 4; + parameter DQS_BIAS_MODE = "FALSE"; + parameter EN_ISERDES_RST = "FALSE"; + parameter integer FINE_DELAY = 0; + parameter FREQ_REF_DIV = "NONE"; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real MEMREFCLK_PERIOD = 0.000; + parameter OUTPUT_CLK_SRC = "PHASE_REF"; + parameter real PHASEREFCLK_PERIOD = 0.000; + parameter real REFCLK_PERIOD = 0.000; + parameter integer SEL_CLK_OFFSET = 5; + parameter SYNC_IN_DIV_RST = "FALSE"; + output FINEOVERFLOW; + output ICLK; + output ICLKDIV; + output ISERDESRST; + output RCLK; + output [5:0] COUNTERREADVAL; + input COUNTERLOADEN; + input COUNTERREADEN; + input DIVIDERST; + input EDGEADV; + input FINEENABLE; + input FINEINC; + input FREQREFCLK; + input MEMREFCLK; + input PHASEREFCLK; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + input SYNCIN; + input SYSCLK; + input [1:0] RANKSEL; + input [5:0] COUNTERLOADVAL; +endmodule + +(* keep *) +module PHASER_IN_PHY (...); + parameter BURST_MODE = "FALSE"; + parameter integer CLKOUT_DIV = 4; + parameter [0:0] DQS_AUTO_RECAL = 1'b1; + parameter DQS_BIAS_MODE = "FALSE"; + parameter [2:0] DQS_FIND_PATTERN = 3'b001; + parameter integer FINE_DELAY = 0; + parameter FREQ_REF_DIV = "NONE"; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real MEMREFCLK_PERIOD = 0.000; + parameter OUTPUT_CLK_SRC = "PHASE_REF"; + parameter real PHASEREFCLK_PERIOD = 0.000; + parameter real REFCLK_PERIOD = 0.000; + parameter integer SEL_CLK_OFFSET = 5; + parameter SYNC_IN_DIV_RST = "FALSE"; + parameter WR_CYCLES = "FALSE"; + output DQSFOUND; + output DQSOUTOFRANGE; + output FINEOVERFLOW; + output ICLK; + output ICLKDIV; + output ISERDESRST; + output PHASELOCKED; + output RCLK; + output WRENABLE; + output [5:0] COUNTERREADVAL; + input BURSTPENDINGPHY; + input COUNTERLOADEN; + input COUNTERREADEN; + input FINEENABLE; + input FINEINC; + input FREQREFCLK; + input MEMREFCLK; + input PHASEREFCLK; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + input RSTDQSFIND; + input SYNCIN; + input SYSCLK; + input [1:0] ENCALIBPHY; + input [1:0] RANKSELPHY; + input [5:0] COUNTERLOADVAL; +endmodule + +(* keep *) +module PHASER_OUT (...); + parameter integer CLKOUT_DIV = 4; + parameter COARSE_BYPASS = "FALSE"; + parameter integer COARSE_DELAY = 0; + parameter EN_OSERDES_RST = "FALSE"; + parameter integer FINE_DELAY = 0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real MEMREFCLK_PERIOD = 0.000; + parameter OCLKDELAY_INV = "FALSE"; + parameter integer OCLK_DELAY = 0; + parameter OUTPUT_CLK_SRC = "PHASE_REF"; + parameter real PHASEREFCLK_PERIOD = 0.000; + parameter [2:0] PO = 3'b000; + parameter real REFCLK_PERIOD = 0.000; + parameter SYNC_IN_DIV_RST = "FALSE"; + output COARSEOVERFLOW; + output FINEOVERFLOW; + output OCLK; + output OCLKDELAYED; + output OCLKDIV; + output OSERDESRST; + output [8:0] COUNTERREADVAL; + input COARSEENABLE; + input COARSEINC; + input COUNTERLOADEN; + input COUNTERREADEN; + input DIVIDERST; + input EDGEADV; + input FINEENABLE; + input FINEINC; + input FREQREFCLK; + input MEMREFCLK; + input PHASEREFCLK; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + input SELFINEOCLKDELAY; + input SYNCIN; + input SYSCLK; + input [8:0] COUNTERLOADVAL; +endmodule + +(* keep *) +module PHASER_OUT_PHY (...); + parameter integer CLKOUT_DIV = 4; + parameter COARSE_BYPASS = "FALSE"; + parameter integer COARSE_DELAY = 0; + parameter DATA_CTL_N = "FALSE"; + parameter DATA_RD_CYCLES = "FALSE"; + parameter integer FINE_DELAY = 0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real MEMREFCLK_PERIOD = 0.000; + parameter OCLKDELAY_INV = "FALSE"; + parameter integer OCLK_DELAY = 0; + parameter OUTPUT_CLK_SRC = "PHASE_REF"; + parameter real PHASEREFCLK_PERIOD = 0.000; + parameter [2:0] PO = 3'b000; + parameter real REFCLK_PERIOD = 0.000; + parameter SYNC_IN_DIV_RST = "FALSE"; + output COARSEOVERFLOW; + output FINEOVERFLOW; + output OCLK; + output OCLKDELAYED; + output OCLKDIV; + output OSERDESRST; + output RDENABLE; + output [1:0] CTSBUS; + output [1:0] DQSBUS; + output [1:0] DTSBUS; + output [8:0] COUNTERREADVAL; + input BURSTPENDINGPHY; + input COARSEENABLE; + input COARSEINC; + input COUNTERLOADEN; + input COUNTERREADEN; + input FINEENABLE; + input FINEINC; + input FREQREFCLK; + input MEMREFCLK; + input PHASEREFCLK; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + input SELFINEOCLKDELAY; + input SYNCIN; + input SYSCLK; + input [1:0] ENCALIBPHY; + input [8:0] COUNTERLOADVAL; +endmodule + +(* keep *) +module PHASER_REF (...); + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + output LOCKED; + input CLKIN; + (* invertible_pin = "IS_PWRDWN_INVERTED" *) + input PWRDWN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +(* keep *) +module PHY_CONTROL (...); + parameter integer AO_TOGGLE = 0; + parameter [3:0] AO_WRLVL_EN = 4'b0000; + parameter BURST_MODE = "FALSE"; + parameter integer CLK_RATIO = 1; + parameter integer CMD_OFFSET = 0; + parameter integer CO_DURATION = 0; + parameter DATA_CTL_A_N = "FALSE"; + parameter DATA_CTL_B_N = "FALSE"; + parameter DATA_CTL_C_N = "FALSE"; + parameter DATA_CTL_D_N = "FALSE"; + parameter DISABLE_SEQ_MATCH = "TRUE"; + parameter integer DI_DURATION = 0; + parameter integer DO_DURATION = 0; + parameter integer EVENTS_DELAY = 63; + parameter integer FOUR_WINDOW_CLOCKS = 63; + parameter MULTI_REGION = "FALSE"; + parameter PHY_COUNT_ENABLE = "FALSE"; + parameter integer RD_CMD_OFFSET_0 = 0; + parameter integer RD_CMD_OFFSET_1 = 00; + parameter integer RD_CMD_OFFSET_2 = 0; + parameter integer RD_CMD_OFFSET_3 = 0; + parameter integer RD_DURATION_0 = 0; + parameter integer RD_DURATION_1 = 0; + parameter integer RD_DURATION_2 = 0; + parameter integer RD_DURATION_3 = 0; + parameter SYNC_MODE = "FALSE"; + parameter integer WR_CMD_OFFSET_0 = 0; + parameter integer WR_CMD_OFFSET_1 = 0; + parameter integer WR_CMD_OFFSET_2 = 0; + parameter integer WR_CMD_OFFSET_3 = 0; + parameter integer WR_DURATION_0 = 0; + parameter integer WR_DURATION_1 = 0; + parameter integer WR_DURATION_2 = 0; + parameter integer WR_DURATION_3 = 0; + output PHYCTLALMOSTFULL; + output PHYCTLEMPTY; + output PHYCTLFULL; + output PHYCTLREADY; + output [1:0] INRANKA; + output [1:0] INRANKB; + output [1:0] INRANKC; + output [1:0] INRANKD; + output [1:0] PCENABLECALIB; + output [3:0] AUXOUTPUT; + output [3:0] INBURSTPENDING; + output [3:0] OUTBURSTPENDING; + input MEMREFCLK; + input PHYCLK; + input PHYCTLMSTREMPTY; + input PHYCTLWRENABLE; + input PLLLOCK; + input READCALIBENABLE; + input REFDLLLOCK; + input RESET; + input SYNCIN; + input WRITECALIBENABLE; + input [31:0] PHYCTLWD; +endmodule + +module IDDRE1 (...); + parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; + parameter [0:0] IS_CB_INVERTED = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + output Q1; + output Q2; + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C; + (* clkbuf_sink *) + (* invertible_pin = "IS_CB_INVERTED" *) + input CB; + input D; + input R; +endmodule + +module ODDRE1 (...); + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D1_INVERTED = 1'b0; + parameter [0:0] IS_D2_INVERTED = 1'b0; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter [0:0] SRVAL = 1'b0; + output Q; + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C; + (* invertible_pin = "IS_D1_INVERTED" *) + input D1; + (* invertible_pin = "IS_D2_INVERTED" *) + input D2; + input SR; +endmodule + +module IDELAYE3 (...); + parameter CASCADE = "NONE"; + parameter DELAY_FORMAT = "TIME"; + parameter DELAY_SRC = "IDATAIN"; + parameter DELAY_TYPE = "FIXED"; + parameter integer DELAY_VALUE = 0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter LOOPBACK = "FALSE"; + parameter real REFCLK_FREQUENCY = 300.0; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter real SIM_VERSION = 2.0; + parameter UPDATE_MODE = "ASYNC"; + output CASC_OUT; + output [8:0] CNTVALUEOUT; + output DATAOUT; + input CASC_IN; + input CASC_RETURN; + input CE; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + input [8:0] CNTVALUEIN; + input DATAIN; + input EN_VTC; + input IDATAIN; + input INC; + input LOAD; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module ODELAYE3 (...); + parameter CASCADE = "NONE"; + parameter DELAY_FORMAT = "TIME"; + parameter DELAY_TYPE = "FIXED"; + parameter integer DELAY_VALUE = 0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REFCLK_FREQUENCY = 300.0; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter real SIM_VERSION = 2.0; + parameter UPDATE_MODE = "ASYNC"; + output CASC_OUT; + output [8:0] CNTVALUEOUT; + output DATAOUT; + input CASC_IN; + input CASC_RETURN; + input CE; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + input [8:0] CNTVALUEIN; + input EN_VTC; + input INC; + input LOAD; + input ODATAIN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module ISERDESE3 (...); + parameter integer DATA_WIDTH = 8; + parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; + parameter FIFO_ENABLE = "FALSE"; + parameter FIFO_SYNC_MODE = "FALSE"; + parameter IDDR_MODE = "FALSE"; + parameter [0:0] IS_CLK_B_INVERTED = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter real SIM_VERSION = 2.0; + output FIFO_EMPTY; + output INTERNAL_DIVCLK; + output [7:0] Q; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + (* clkbuf_sink *) + input CLKDIV; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_B_INVERTED" *) + input CLK_B; + input D; + (* clkbuf_sink *) + input FIFO_RD_CLK; + input FIFO_RD_EN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module OSERDESE3 (...); + parameter integer DATA_WIDTH = 8; + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_CLKDIV_INVERTED = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter ODDR_MODE = "FALSE"; + parameter OSERDES_D_BYPASS = "FALSE"; + parameter OSERDES_T_BYPASS = "FALSE"; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter real SIM_VERSION = 2.0; + output OQ; + output T_OUT; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKDIV_INVERTED" *) + input CLKDIV; + input [7:0] D; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + input T; +endmodule + +(* keep *) +module BITSLICE_CONTROL (...); + parameter CTRL_CLK = "EXTERNAL"; + parameter DIV_MODE = "DIV2"; + parameter EN_CLK_TO_EXT_NORTH = "DISABLE"; + parameter EN_CLK_TO_EXT_SOUTH = "DISABLE"; + parameter EN_DYN_ODLY_MODE = "FALSE"; + parameter EN_OTHER_NCLK = "FALSE"; + parameter EN_OTHER_PCLK = "FALSE"; + parameter IDLY_VT_TRACK = "TRUE"; + parameter INV_RXCLK = "FALSE"; + parameter ODLY_VT_TRACK = "TRUE"; + parameter QDLY_VT_TRACK = "TRUE"; + parameter [5:0] READ_IDLE_COUNT = 6'h00; + parameter REFCLK_SRC = "PLLCLK"; + parameter integer ROUNDING_FACTOR = 16; + parameter RXGATE_EXTEND = "FALSE"; + parameter RX_CLK_PHASE_N = "SHIFT_0"; + parameter RX_CLK_PHASE_P = "SHIFT_0"; + parameter RX_GATING = "DISABLE"; + parameter SELF_CALIBRATE = "ENABLE"; + parameter SERIAL_MODE = "FALSE"; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter SIM_SPEEDUP = "FAST"; + parameter real SIM_VERSION = 2.0; + parameter TX_GATING = "DISABLE"; + output CLK_TO_EXT_NORTH; + output CLK_TO_EXT_SOUTH; + output DLY_RDY; + output [6:0] DYN_DCI; + output NCLK_NIBBLE_OUT; + output PCLK_NIBBLE_OUT; + output [15:0] RIU_RD_DATA; + output RIU_VALID; + output [39:0] RX_BIT_CTRL_OUT0; + output [39:0] RX_BIT_CTRL_OUT1; + output [39:0] RX_BIT_CTRL_OUT2; + output [39:0] RX_BIT_CTRL_OUT3; + output [39:0] RX_BIT_CTRL_OUT4; + output [39:0] RX_BIT_CTRL_OUT5; + output [39:0] RX_BIT_CTRL_OUT6; + output [39:0] TX_BIT_CTRL_OUT0; + output [39:0] TX_BIT_CTRL_OUT1; + output [39:0] TX_BIT_CTRL_OUT2; + output [39:0] TX_BIT_CTRL_OUT3; + output [39:0] TX_BIT_CTRL_OUT4; + output [39:0] TX_BIT_CTRL_OUT5; + output [39:0] TX_BIT_CTRL_OUT6; + output [39:0] TX_BIT_CTRL_OUT_TRI; + output VTC_RDY; + input CLK_FROM_EXT; + input EN_VTC; + input NCLK_NIBBLE_IN; + input PCLK_NIBBLE_IN; + input [3:0] PHY_RDCS0; + input [3:0] PHY_RDCS1; + input [3:0] PHY_RDEN; + input [3:0] PHY_WRCS0; + input [3:0] PHY_WRCS1; + input PLL_CLK; + input REFCLK; + input [5:0] RIU_ADDR; + input RIU_CLK; + input RIU_NIBBLE_SEL; + input [15:0] RIU_WR_DATA; + input RIU_WR_EN; + input RST; + input [39:0] RX_BIT_CTRL_IN0; + input [39:0] RX_BIT_CTRL_IN1; + input [39:0] RX_BIT_CTRL_IN2; + input [39:0] RX_BIT_CTRL_IN3; + input [39:0] RX_BIT_CTRL_IN4; + input [39:0] RX_BIT_CTRL_IN5; + input [39:0] RX_BIT_CTRL_IN6; + input [3:0] TBYTE_IN; + input [39:0] TX_BIT_CTRL_IN0; + input [39:0] TX_BIT_CTRL_IN1; + input [39:0] TX_BIT_CTRL_IN2; + input [39:0] TX_BIT_CTRL_IN3; + input [39:0] TX_BIT_CTRL_IN4; + input [39:0] TX_BIT_CTRL_IN5; + input [39:0] TX_BIT_CTRL_IN6; + input [39:0] TX_BIT_CTRL_IN_TRI; +endmodule + +(* keep *) +module RIU_OR (...); + parameter SIM_DEVICE = "ULTRASCALE"; + parameter real SIM_VERSION = 2.0; + output [15:0] RIU_RD_DATA; + output RIU_RD_VALID; + input [15:0] RIU_RD_DATA_LOW; + input [15:0] RIU_RD_DATA_UPP; + input RIU_RD_VALID_LOW; + input RIU_RD_VALID_UPP; +endmodule + +module RX_BITSLICE (...); + parameter CASCADE = "TRUE"; + parameter DATA_TYPE = "NONE"; + parameter integer DATA_WIDTH = 8; + parameter DELAY_FORMAT = "TIME"; + parameter DELAY_TYPE = "FIXED"; + parameter integer DELAY_VALUE = 0; + parameter integer DELAY_VALUE_EXT = 0; + parameter FIFO_SYNC_MODE = "FALSE"; + parameter [0:0] IS_CLK_EXT_INVERTED = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [0:0] IS_RST_DLY_EXT_INVERTED = 1'b0; + parameter [0:0] IS_RST_DLY_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REFCLK_FREQUENCY = 300.0; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter real SIM_VERSION = 2.0; + parameter UPDATE_MODE = "ASYNC"; + parameter UPDATE_MODE_EXT = "ASYNC"; + output [8:0] CNTVALUEOUT; + output [8:0] CNTVALUEOUT_EXT; + output FIFO_EMPTY; + output FIFO_WRCLK_OUT; + output [7:0] Q; + output [39:0] RX_BIT_CTRL_OUT; + output [39:0] TX_BIT_CTRL_OUT; + input CE; + input CE_EXT; + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + (* invertible_pin = "IS_CLK_EXT_INVERTED" *) + input CLK_EXT; + input [8:0] CNTVALUEIN; + input [8:0] CNTVALUEIN_EXT; + input DATAIN; + input EN_VTC; + input EN_VTC_EXT; + input FIFO_RD_CLK; + input FIFO_RD_EN; + input INC; + input INC_EXT; + input LOAD; + input LOAD_EXT; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + (* invertible_pin = "IS_RST_DLY_INVERTED" *) + input RST_DLY; + (* invertible_pin = "IS_RST_DLY_EXT_INVERTED" *) + input RST_DLY_EXT; + input [39:0] RX_BIT_CTRL_IN; + input [39:0] TX_BIT_CTRL_IN; +endmodule + +module RXTX_BITSLICE (...); + parameter FIFO_SYNC_MODE = "FALSE"; + parameter [0:0] INIT = 1'b1; + parameter [0:0] IS_RX_CLK_INVERTED = 1'b0; + parameter [0:0] IS_RX_RST_DLY_INVERTED = 1'b0; + parameter [0:0] IS_RX_RST_INVERTED = 1'b0; + parameter [0:0] IS_TX_CLK_INVERTED = 1'b0; + parameter [0:0] IS_TX_RST_DLY_INVERTED = 1'b0; + parameter [0:0] IS_TX_RST_INVERTED = 1'b0; + parameter LOOPBACK = "FALSE"; + parameter NATIVE_ODELAY_BYPASS = "FALSE"; + parameter ENABLE_PRE_EMPHASIS = "FALSE"; + parameter RX_DATA_TYPE = "NONE"; + parameter integer RX_DATA_WIDTH = 8; + parameter RX_DELAY_FORMAT = "TIME"; + parameter RX_DELAY_TYPE = "FIXED"; + parameter integer RX_DELAY_VALUE = 0; + parameter real RX_REFCLK_FREQUENCY = 300.0; + parameter RX_UPDATE_MODE = "ASYNC"; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter real SIM_VERSION = 2.0; + parameter TBYTE_CTL = "TBYTE_IN"; + parameter integer TX_DATA_WIDTH = 8; + parameter TX_DELAY_FORMAT = "TIME"; + parameter TX_DELAY_TYPE = "FIXED"; + parameter integer TX_DELAY_VALUE = 0; + parameter TX_OUTPUT_PHASE_90 = "FALSE"; + parameter real TX_REFCLK_FREQUENCY = 300.0; + parameter TX_UPDATE_MODE = "ASYNC"; + output FIFO_EMPTY; + output FIFO_WRCLK_OUT; + output O; + output [7:0] Q; + output [39:0] RX_BIT_CTRL_OUT; + output [8:0] RX_CNTVALUEOUT; + output [39:0] TX_BIT_CTRL_OUT; + output [8:0] TX_CNTVALUEOUT; + output T_OUT; + input [7:0] D; + input DATAIN; + input FIFO_RD_CLK; + input FIFO_RD_EN; + input [39:0] RX_BIT_CTRL_IN; + input RX_CE; + (* invertible_pin = "IS_RX_CLK_INVERTED" *) + input RX_CLK; + input [8:0] RX_CNTVALUEIN; + input RX_EN_VTC; + input RX_INC; + input RX_LOAD; + (* invertible_pin = "IS_RX_RST_INVERTED" *) + input RX_RST; + (* invertible_pin = "IS_RX_RST_DLY_INVERTED" *) + input RX_RST_DLY; + input T; + input TBYTE_IN; + input [39:0] TX_BIT_CTRL_IN; + input TX_CE; + (* invertible_pin = "IS_TX_CLK_INVERTED" *) + input TX_CLK; + input [8:0] TX_CNTVALUEIN; + input TX_EN_VTC; + input TX_INC; + input TX_LOAD; + (* invertible_pin = "IS_TX_RST_INVERTED" *) + input TX_RST; + (* invertible_pin = "IS_TX_RST_DLY_INVERTED" *) + input TX_RST_DLY; +endmodule + +module TX_BITSLICE (...); + parameter integer DATA_WIDTH = 8; + parameter DELAY_FORMAT = "TIME"; + parameter DELAY_TYPE = "FIXED"; + parameter integer DELAY_VALUE = 0; + parameter ENABLE_PRE_EMPHASIS = "FALSE"; + parameter [0:0] INIT = 1'b1; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [0:0] IS_RST_DLY_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter NATIVE_ODELAY_BYPASS = "FALSE"; + parameter OUTPUT_PHASE_90 = "FALSE"; + parameter real REFCLK_FREQUENCY = 300.0; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter real SIM_VERSION = 2.0; + parameter TBYTE_CTL = "TBYTE_IN"; + parameter UPDATE_MODE = "ASYNC"; + output [8:0] CNTVALUEOUT; + output O; + output [39:0] RX_BIT_CTRL_OUT; + output [39:0] TX_BIT_CTRL_OUT; + output T_OUT; + input CE; + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + input [8:0] CNTVALUEIN; + input [7:0] D; + input EN_VTC; + input INC; + input LOAD; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + (* invertible_pin = "IS_RST_DLY_INVERTED" *) + input RST_DLY; + input [39:0] RX_BIT_CTRL_IN; + input T; + input TBYTE_IN; + input [39:0] TX_BIT_CTRL_IN; +endmodule + +module TX_BITSLICE_TRI (...); + parameter integer DATA_WIDTH = 8; + parameter DELAY_FORMAT = "TIME"; + parameter DELAY_TYPE = "FIXED"; + parameter integer DELAY_VALUE = 0; + parameter [0:0] INIT = 1'b1; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [0:0] IS_RST_DLY_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter NATIVE_ODELAY_BYPASS = "FALSE"; + parameter OUTPUT_PHASE_90 = "FALSE"; + parameter real REFCLK_FREQUENCY = 300.0; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter real SIM_VERSION = 2.0; + parameter UPDATE_MODE = "ASYNC"; + output [39:0] BIT_CTRL_OUT; + output [8:0] CNTVALUEOUT; + output TRI_OUT; + input [39:0] BIT_CTRL_IN; + input CE; + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + input [8:0] CNTVALUEIN; + input EN_VTC; + input INC; + input LOAD; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + (* invertible_pin = "IS_RST_DLY_INVERTED" *) + input RST_DLY; +endmodule + +module IODELAY2 (...); + parameter COUNTER_WRAPAROUND = "WRAPAROUND"; + parameter DATA_RATE = "SDR"; + parameter DELAY_SRC = "IO"; + parameter integer IDELAY2_VALUE = 0; + parameter IDELAY_MODE = "NORMAL"; + parameter IDELAY_TYPE = "DEFAULT"; + parameter integer IDELAY_VALUE = 0; + parameter integer ODELAY_VALUE = 0; + parameter SERDES_MODE = "NONE"; + parameter integer SIM_TAPDELAY_VALUE = 75; + output BUSY; + output DATAOUT2; + output DATAOUT; + output DOUT; + output TOUT; + input CAL; + input CE; + (* clkbuf_sink *) + input CLK; + input IDATAIN; + input INC; + (* clkbuf_sink *) + input IOCLK0; + (* clkbuf_sink *) + input IOCLK1; + input ODATAIN; + input RST; + input T; +endmodule + +module IODRP2 (...); + parameter DATA_RATE = "SDR"; + parameter integer SIM_TAPDELAY_VALUE = 75; + output DATAOUT2; + output DATAOUT; + output DOUT; + output SDO; + output TOUT; + input ADD; + input BKST; + (* clkbuf_sink *) + input CLK; + input CS; + input IDATAIN; + (* clkbuf_sink *) + input IOCLK0; + (* clkbuf_sink *) + input IOCLK1; + input ODATAIN; + input SDI; + input T; +endmodule + +module IODRP2_MCB (...); + parameter DATA_RATE = "SDR"; + parameter integer IDELAY_VALUE = 0; + parameter integer MCB_ADDRESS = 0; + parameter integer ODELAY_VALUE = 0; + parameter SERDES_MODE = "NONE"; + parameter integer SIM_TAPDELAY_VALUE = 75; + output AUXSDO; + output DATAOUT2; + output DATAOUT; + output DOUT; + output DQSOUTN; + output DQSOUTP; + output SDO; + output TOUT; + input ADD; + input AUXSDOIN; + input BKST; + (* clkbuf_sink *) + input CLK; + input CS; + input IDATAIN; + (* clkbuf_sink *) + input IOCLK0; + (* clkbuf_sink *) + input IOCLK1; + input MEMUPDATE; + input ODATAIN; + input SDI; + input T; + input [4:0] AUXADDR; +endmodule + +module ISERDES2 (...); + parameter BITSLIP_ENABLE = "FALSE"; + parameter DATA_RATE = "SDR"; + parameter integer DATA_WIDTH = 1; + parameter INTERFACE_TYPE = "NETWORKING"; + parameter SERDES_MODE = "NONE"; + output CFB0; + output CFB1; + output DFB; + output FABRICOUT; + output INCDEC; + output Q1; + output Q2; + output Q3; + output Q4; + output SHIFTOUT; + output VALID; + input BITSLIP; + input CE0; + (* clkbuf_sink *) + input CLK0; + (* clkbuf_sink *) + input CLK1; + (* clkbuf_sink *) + input CLKDIV; + input D; + input IOCE; + input RST; + input SHIFTIN; +endmodule + +module OSERDES2 (...); + parameter BYPASS_GCLK_FF = "FALSE"; + parameter DATA_RATE_OQ = "DDR"; + parameter DATA_RATE_OT = "DDR"; + parameter integer DATA_WIDTH = 2; + parameter OUTPUT_MODE = "SINGLE_ENDED"; + parameter SERDES_MODE = "NONE"; + parameter integer TRAIN_PATTERN = 0; + output OQ; + output SHIFTOUT1; + output SHIFTOUT2; + output SHIFTOUT3; + output SHIFTOUT4; + output TQ; + (* clkbuf_sink *) + input CLK0; + (* clkbuf_sink *) + input CLK1; + (* clkbuf_sink *) + input CLKDIV; + input D1; + input D2; + input D3; + input D4; + input IOCE; + input OCE; + input RST; + input SHIFTIN1; + input SHIFTIN2; + input SHIFTIN3; + input SHIFTIN4; + input T1; + input T2; + input T3; + input T4; + input TCE; + input TRAIN; +endmodule + +module IBUF_DLY_ADJ (...); + parameter DELAY_OFFSET = "OFF"; + parameter IOSTANDARD = "DEFAULT"; + output O; + (* iopad_external_pin *) + input I; + input [2:0] S; +endmodule + +module IBUF_IBUFDISABLE (...); + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter USE_IBUFDISABLE = "TRUE"; + output O; + (* iopad_external_pin *) + input I; + input IBUFDISABLE; +endmodule + +module IBUF_INTERMDISABLE (...); + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter USE_IBUFDISABLE = "TRUE"; + output O; + (* iopad_external_pin *) + input I; + input IBUFDISABLE; + input INTERMDISABLE; +endmodule + +module IBUF_ANALOG (...); + output O; + (* iopad_external_pin *) + input I; +endmodule + +module IBUFE3 (...); + parameter CCIO_EN = "TRUE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter integer SIM_INPUT_BUFFER_OFFSET = 0; + parameter USE_IBUFDISABLE = "FALSE"; + output O; + (* iopad_external_pin *) + input I; + input IBUFDISABLE; + input [3:0] OSC; + input OSC_EN; + input VREF; +endmodule + +module IBUFDS (...); + parameter CAPACITANCE = "DONT_CARE"; + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IFD_DELAY_VALUE = "AUTO"; + parameter IOSTANDARD = "DEFAULT"; + output O; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; +endmodule + +module IBUFDS_DLY_ADJ (...); + parameter DELAY_OFFSET = "OFF"; + parameter DIFF_TERM = "FALSE"; + parameter IOSTANDARD = "DEFAULT"; + output O; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; + input [2:0] S; +endmodule + +module IBUFDS_IBUFDISABLE (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter USE_IBUFDISABLE = "TRUE"; + output O; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; + input IBUFDISABLE; +endmodule + +module IBUFDS_INTERMDISABLE (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter USE_IBUFDISABLE = "TRUE"; + output O; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; + input IBUFDISABLE; + input INTERMDISABLE; +endmodule + +module IBUFDS_DIFF_OUT (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + output O; + output OB; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; +endmodule + +module IBUFDS_DIFF_OUT_IBUFDISABLE (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter USE_IBUFDISABLE = "TRUE"; + output O; + output OB; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; + input IBUFDISABLE; +endmodule + +module IBUFDS_DIFF_OUT_INTERMDISABLE (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter USE_IBUFDISABLE = "TRUE"; + output O; + output OB; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; + input IBUFDISABLE; + input INTERMDISABLE; +endmodule + +module IBUFDSE3 (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter USE_IBUFDISABLE = "FALSE"; + parameter integer SIM_INPUT_BUFFER_OFFSET = 0; + output O; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; + input IBUFDISABLE; + input [3:0] OSC; + input [1:0] OSC_EN; +endmodule + +module IBUFDS_DPHY (...); + parameter DIFF_TERM = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + output HSRX_O; + output LPRX_O_N; + output LPRX_O_P; + input HSRX_DISABLE; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; + input LPRX_DISABLE; +endmodule + +module IBUFGDS (...); + parameter CAPACITANCE = "DONT_CARE"; + parameter DIFF_TERM = "FALSE"; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + output O; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; +endmodule + +module IBUFGDS_DIFF_OUT (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + output O; + output OB; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; +endmodule + +module IOBUF_DCIEN (...); + parameter integer DRIVE = 12; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter SLEW = "SLOW"; + parameter USE_IBUFDISABLE = "TRUE"; + output O; + (* iopad_external_pin *) + inout IO; + input DCITERMDISABLE; + input I; + input IBUFDISABLE; + input T; +endmodule + +module IOBUF_INTERMDISABLE (...); + parameter integer DRIVE = 12; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter SLEW = "SLOW"; + parameter USE_IBUFDISABLE = "TRUE"; + output O; + (* iopad_external_pin *) + inout IO; + input I; + input IBUFDISABLE; + input INTERMDISABLE; + input T; +endmodule + +module IOBUFE3 (...); + parameter integer DRIVE = 12; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter integer SIM_INPUT_BUFFER_OFFSET = 0; + parameter USE_IBUFDISABLE = "FALSE"; + output O; + (* iopad_external_pin *) + inout IO; + input DCITERMDISABLE; + input I; + input IBUFDISABLE; + input [3:0] OSC; + input OSC_EN; + input T; + input VREF; +endmodule + +module IOBUFDS (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + output O; + (* iopad_external_pin *) + inout IO; + (* iopad_external_pin *) + inout IOB; + input I; + input T; +endmodule + +module IOBUFDS_DCIEN (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter SLEW = "SLOW"; + parameter USE_IBUFDISABLE = "TRUE"; + output O; + (* iopad_external_pin *) + inout IO; + (* iopad_external_pin *) + inout IOB; + input DCITERMDISABLE; + input I; + input IBUFDISABLE; + input T; +endmodule + +module IOBUFDS_INTERMDISABLE (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter SLEW = "SLOW"; + parameter USE_IBUFDISABLE = "TRUE"; + output O; + (* iopad_external_pin *) + inout IO; + (* iopad_external_pin *) + inout IOB; + input I; + input IBUFDISABLE; + input INTERMDISABLE; + input T; +endmodule + +module IOBUFDS_DIFF_OUT (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + output O; + output OB; + (* iopad_external_pin *) + inout IO; + (* iopad_external_pin *) + inout IOB; + input I; + input TM; + input TS; +endmodule + +module IOBUFDS_DIFF_OUT_DCIEN (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter USE_IBUFDISABLE = "TRUE"; + output O; + output OB; + (* iopad_external_pin *) + inout IO; + (* iopad_external_pin *) + inout IOB; + input DCITERMDISABLE; + input I; + input IBUFDISABLE; + input TM; + input TS; +endmodule + +module IOBUFDS_DIFF_OUT_INTERMDISABLE (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter USE_IBUFDISABLE = "TRUE"; + output O; + output OB; + (* iopad_external_pin *) + inout IO; + (* iopad_external_pin *) + inout IOB; + input I; + input IBUFDISABLE; + input INTERMDISABLE; + input TM; + input TS; +endmodule + +module IOBUFDSE3 (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter integer SIM_INPUT_BUFFER_OFFSET = 0; + parameter USE_IBUFDISABLE = "FALSE"; + output O; + (* iopad_external_pin *) + inout IO; + (* iopad_external_pin *) + inout IOB; + input DCITERMDISABLE; + input I; + input IBUFDISABLE; + input [3:0] OSC; + input [1:0] OSC_EN; + input T; +endmodule + +module OBUFDS (...); + parameter CAPACITANCE = "DONT_CARE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + (* iopad_external_pin *) + output O; + (* iopad_external_pin *) + output OB; + input I; +endmodule + +module OBUFDS_DPHY (...); + parameter IOSTANDARD = "DEFAULT"; + (* iopad_external_pin *) + output O; + (* iopad_external_pin *) + output OB; + input HSTX_I; + input HSTX_T; + input LPTX_I_N; + input LPTX_I_P; + input LPTX_T; +endmodule + +module OBUFTDS (...); + parameter CAPACITANCE = "DONT_CARE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + (* iopad_external_pin *) + output O; + (* iopad_external_pin *) + output OB; + input I; + input T; +endmodule + +module KEEPER (...); + inout O; +endmodule + +module PULLDOWN (...); + output O; +endmodule + +module PULLUP (...); + output O; +endmodule + +(* keep *) +module DCIRESET (...); + output LOCKED; + input RST; +endmodule + +(* keep *) +module HPIO_VREF (...); + parameter VREF_CNTR = "OFF"; + output VREF; + input [6:0] FABRIC_VREF_TUNE; +endmodule + +module BUFGCE (...); + parameter CE_TYPE = "SYNC"; + parameter [0:0] IS_CE_INVERTED = 1'b0; + parameter [0:0] IS_I_INVERTED = 1'b0; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter STARTUP_SYNC = "FALSE"; + (* clkbuf_driver *) + output O; + (* invertible_pin = "IS_CE_INVERTED" *) + input CE; + (* invertible_pin = "IS_I_INVERTED" *) + input I; +endmodule + +module BUFGCE_1 (...); + (* clkbuf_driver *) + output O; + input CE; + input I; +endmodule + +module BUFGMUX (...); + parameter CLK_SEL_TYPE = "SYNC"; + (* clkbuf_driver *) + output O; + input I0; + input I1; + input S; +endmodule + +module BUFGMUX_1 (...); + parameter CLK_SEL_TYPE = "SYNC"; + (* clkbuf_driver *) + output O; + input I0; + input I1; + input S; +endmodule + +module BUFGMUX_CTRL (...); + (* clkbuf_driver *) + output O; + input I0; + input I1; + input S; +endmodule + +module BUFGMUX_VIRTEX4 (...); + (* clkbuf_driver *) + output O; + input I0; + input I1; + input S; +endmodule + +module BUFG_GT (...); + parameter SIM_DEVICE = "ULTRASCALE"; + parameter STARTUP_SYNC = "FALSE"; + (* clkbuf_driver *) + output O; + input CE; + input CEMASK; + input CLR; + input CLRMASK; + input [2:0] DIV; + input I; +endmodule + +module BUFG_GT_SYNC (...); + output CESYNC; + output CLRSYNC; + input CE; + input CLK; + input CLR; +endmodule + +module BUFG_PS (...); + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter STARTUP_SYNC = "FALSE"; + (* clkbuf_driver *) + output O; + input I; +endmodule + +module BUFGCE_DIV (...); + parameter integer BUFGCE_DIVIDE = 1; + parameter CE_TYPE = "SYNC"; + parameter HARDSYNC_CLR = "FALSE"; + parameter [0:0] IS_CE_INVERTED = 1'b0; + parameter [0:0] IS_CLR_INVERTED = 1'b0; + parameter [0:0] IS_I_INVERTED = 1'b0; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter STARTUP_SYNC = "FALSE"; + (* clkbuf_driver *) + output O; + (* invertible_pin = "IS_CE_INVERTED" *) + input CE; + (* invertible_pin = "IS_CLR_INVERTED" *) + input CLR; + (* invertible_pin = "IS_I_INVERTED" *) + input I; +endmodule + +module BUFH (...); + (* clkbuf_driver *) + output O; + input I; +endmodule + +module BUFIO2 (...); + parameter DIVIDE_BYPASS = "TRUE"; + parameter integer DIVIDE = 1; + parameter I_INVERT = "FALSE"; + parameter USE_DOUBLER = "FALSE"; + (* clkbuf_driver *) + output DIVCLK; + (* clkbuf_driver *) + output IOCLK; + output SERDESSTROBE; + input I; +endmodule + +module BUFIO2_2CLK (...); + parameter integer DIVIDE = 2; + (* clkbuf_driver *) + output DIVCLK; + (* clkbuf_driver *) + output IOCLK; + output SERDESSTROBE; + input I; + input IB; +endmodule + +module BUFIO2FB (...); + parameter DIVIDE_BYPASS = "TRUE"; + (* clkbuf_driver *) + output O; + input I; +endmodule + +module BUFPLL (...); + parameter integer DIVIDE = 1; + parameter ENABLE_SYNC = "TRUE"; + (* clkbuf_driver *) + output IOCLK; + output LOCK; + output SERDESSTROBE; + input GCLK; + input LOCKED; + input PLLIN; +endmodule + +module BUFPLL_MCB (...); + parameter integer DIVIDE = 2; + parameter LOCK_SRC = "LOCK_TO_0"; + (* clkbuf_driver *) + output IOCLK0; + (* clkbuf_driver *) + output IOCLK1; + output LOCK; + output SERDESSTROBE0; + output SERDESSTROBE1; + input GCLK; + input LOCKED; + input PLLIN0; + input PLLIN1; +endmodule + +module BUFIO (...); + (* clkbuf_driver *) + output O; + input I; +endmodule + +module BUFIODQS (...); + parameter DQSMASK_ENABLE = "FALSE"; + (* clkbuf_driver *) + output O; + input DQSMASK; + input I; +endmodule + +module BUFR (...); + parameter BUFR_DIVIDE = "BYPASS"; + parameter SIM_DEVICE = "7SERIES"; + (* clkbuf_driver *) + output O; + input CE; + input CLR; + input I; +endmodule + +module BUFMR (...); + (* clkbuf_driver *) + output O; + input I; +endmodule + +module BUFMRCE (...); + parameter CE_TYPE = "SYNC"; + parameter integer INIT_OUT = 0; + parameter [0:0] IS_CE_INVERTED = 1'b0; + (* clkbuf_driver *) + output O; + (* invertible_pin = "IS_CE_INVERTED" *) + input CE; + input I; +endmodule + +module DCM (...); + parameter real CLKDV_DIVIDE = 2.0; + parameter integer CLKFX_DIVIDE = 1; + parameter integer CLKFX_MULTIPLY = 4; + parameter CLKIN_DIVIDE_BY_2 = "FALSE"; + parameter real CLKIN_PERIOD = 10.0; + parameter CLKOUT_PHASE_SHIFT = "NONE"; + parameter CLK_FEEDBACK = "1X"; + parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + parameter DFS_FREQUENCY_MODE = "LOW"; + parameter DLL_FREQUENCY_MODE = "LOW"; + parameter DSS_MODE = "NONE"; + parameter DUTY_CYCLE_CORRECTION = "TRUE"; + parameter [15:0] FACTORY_JF = 16'hC080; + parameter integer PHASE_SHIFT = 0; + parameter SIM_MODE = "SAFE"; + parameter STARTUP_WAIT = "FALSE"; + input CLKFB; + input CLKIN; + input DSSEN; + input PSCLK; + input PSEN; + input PSINCDEC; + input RST; + output CLK0; + output CLK180; + output CLK270; + output CLK2X; + output CLK2X180; + output CLK90; + output CLKDV; + output CLKFX; + output CLKFX180; + output LOCKED; + output PSDONE; + output [7:0] STATUS; +endmodule + +module DCM_SP (...); + parameter real CLKDV_DIVIDE = 2.0; + parameter integer CLKFX_DIVIDE = 1; + parameter integer CLKFX_MULTIPLY = 4; + parameter CLKIN_DIVIDE_BY_2 = "FALSE"; + parameter real CLKIN_PERIOD = 10.0; + parameter CLKOUT_PHASE_SHIFT = "NONE"; + parameter CLK_FEEDBACK = "1X"; + parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + parameter DFS_FREQUENCY_MODE = "LOW"; + parameter DLL_FREQUENCY_MODE = "LOW"; + parameter DSS_MODE = "NONE"; + parameter DUTY_CYCLE_CORRECTION = "TRUE"; + parameter FACTORY_JF = 16'hC080; + parameter integer PHASE_SHIFT = 0; + parameter STARTUP_WAIT = "FALSE"; + input CLKFB; + input CLKIN; + input DSSEN; + input PSCLK; + input PSEN; + input PSINCDEC; + input RST; + output CLK0; + output CLK180; + output CLK270; + output CLK2X; + output CLK2X180; + output CLK90; + output CLKDV; + output CLKFX; + output CLKFX180; + output LOCKED; + output PSDONE; + output [7:0] STATUS; +endmodule + +module DCM_CLKGEN (...); + parameter SPREAD_SPECTRUM = "NONE"; + parameter STARTUP_WAIT = "FALSE"; + parameter integer CLKFXDV_DIVIDE = 2; + parameter integer CLKFX_DIVIDE = 1; + parameter integer CLKFX_MULTIPLY = 4; + parameter real CLKFX_MD_MAX = 0.0; + parameter real CLKIN_PERIOD = 0.0; + output CLKFX180; + output CLKFX; + output CLKFXDV; + output LOCKED; + output PROGDONE; + output [2:1] STATUS; + input CLKIN; + input FREEZEDCM; + input PROGCLK; + input PROGDATA; + input PROGEN; + input RST; +endmodule + +module DCM_ADV (...); + parameter real CLKDV_DIVIDE = 2.0; + parameter integer CLKFX_DIVIDE = 1; + parameter integer CLKFX_MULTIPLY = 4; + parameter CLKIN_DIVIDE_BY_2 = "FALSE"; + parameter real CLKIN_PERIOD = 10.0; + parameter CLKOUT_PHASE_SHIFT = "NONE"; + parameter CLK_FEEDBACK = "1X"; + parameter DCM_AUTOCALIBRATION = "TRUE"; + parameter DCM_PERFORMANCE_MODE = "MAX_SPEED"; + parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + parameter DFS_FREQUENCY_MODE = "LOW"; + parameter DLL_FREQUENCY_MODE = "LOW"; + parameter DUTY_CYCLE_CORRECTION = "TRUE"; + parameter FACTORY_JF = 16'hF0F0; + parameter integer PHASE_SHIFT = 0; + parameter SIM_DEVICE ="VIRTEX4"; + parameter STARTUP_WAIT = "FALSE"; + output CLK0; + output CLK180; + output CLK270; + output CLK2X180; + output CLK2X; + output CLK90; + output CLKDV; + output CLKFX180; + output CLKFX; + output DRDY; + output LOCKED; + output PSDONE; + output [15:0] DO; + input CLKFB; + input CLKIN; + input DCLK; + input DEN; + input DWE; + input PSCLK; + input PSEN; + input PSINCDEC; + input RST; + input [15:0] DI; + input [6:0] DADDR; +endmodule + +module DCM_BASE (...); + parameter real CLKDV_DIVIDE = 2.0; + parameter integer CLKFX_DIVIDE = 1; + parameter integer CLKFX_MULTIPLY = 4; + parameter CLKIN_DIVIDE_BY_2 = "FALSE"; + parameter real CLKIN_PERIOD = 10.0; + parameter CLKOUT_PHASE_SHIFT = "NONE"; + parameter CLK_FEEDBACK = "1X"; + parameter DCM_AUTOCALIBRATION = "TRUE"; + parameter DCM_PERFORMANCE_MODE = "MAX_SPEED"; + parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + parameter DFS_FREQUENCY_MODE = "LOW"; + parameter DLL_FREQUENCY_MODE = "LOW"; + parameter DUTY_CYCLE_CORRECTION = "TRUE"; + parameter [15:0] FACTORY_JF = 16'hF0F0; + parameter integer PHASE_SHIFT = 0; + parameter STARTUP_WAIT = "FALSE"; + output CLK0; + output CLK180; + output CLK270; + output CLK2X180; + output CLK2X; + output CLK90; + output CLKDV; + output CLKFX180; + output CLKFX; + output LOCKED; + input CLKFB; + input CLKIN; + input RST; +endmodule + +module DCM_PS (...); + parameter real CLKDV_DIVIDE = 2.0; + parameter integer CLKFX_DIVIDE = 1; + parameter integer CLKFX_MULTIPLY = 4; + parameter CLKIN_DIVIDE_BY_2 = "FALSE"; + parameter real CLKIN_PERIOD = 10.0; + parameter CLKOUT_PHASE_SHIFT = "NONE"; + parameter CLK_FEEDBACK = "1X"; + parameter DCM_AUTOCALIBRATION = "TRUE"; + parameter DCM_PERFORMANCE_MODE = "MAX_SPEED"; + parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + parameter DFS_FREQUENCY_MODE = "LOW"; + parameter DLL_FREQUENCY_MODE = "LOW"; + parameter DUTY_CYCLE_CORRECTION = "TRUE"; + parameter [15:0] FACTORY_JF = 16'hF0F0; + parameter integer PHASE_SHIFT = 0; + parameter STARTUP_WAIT = "FALSE"; + output CLK0; + output CLK180; + output CLK270; + output CLK2X180; + output CLK2X; + output CLK90; + output CLKDV; + output CLKFX180; + output CLKFX; + output LOCKED; + output PSDONE; + output [15:0] DO; + input CLKFB; + input CLKIN; + input PSCLK; + input PSEN; + input PSINCDEC; + input RST; +endmodule + +module PMCD (...); + parameter EN_REL = "FALSE"; + parameter RST_DEASSERT_CLK = "CLKA"; + output CLKA1; + output CLKA1D2; + output CLKA1D4; + output CLKA1D8; + output CLKB1; + output CLKC1; + output CLKD1; + input CLKA; + input CLKB; + input CLKC; + input CLKD; + input REL; + input RST; +endmodule + +module PLL_ADV (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter CLK_FEEDBACK = "CLKFBOUT"; + parameter CLKFBOUT_DESKEW_ADJUST = "NONE"; + parameter CLKOUT0_DESKEW_ADJUST = "NONE"; + parameter CLKOUT1_DESKEW_ADJUST = "NONE"; + parameter CLKOUT2_DESKEW_ADJUST = "NONE"; + parameter CLKOUT3_DESKEW_ADJUST = "NONE"; + parameter CLKOUT4_DESKEW_ADJUST = "NONE"; + parameter CLKOUT5_DESKEW_ADJUST = "NONE"; + parameter integer CLKFBOUT_MULT = 1; + parameter real CLKFBOUT_PHASE = 0.0; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKIN2_PERIOD = 0.000; + parameter integer CLKOUT0_DIVIDE = 1; + parameter real CLKOUT0_DUTY_CYCLE = 0.5; + parameter real CLKOUT0_PHASE = 0.0; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.5; + parameter real CLKOUT1_PHASE = 0.0; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.5; + parameter real CLKOUT2_PHASE = 0.0; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.5; + parameter real CLKOUT3_PHASE = 0.0; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.5; + parameter real CLKOUT4_PHASE = 0.0; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.5; + parameter real CLKOUT5_PHASE = 0.0; + parameter COMPENSATION = "SYSTEM_SYNCHRONOUS"; + parameter integer DIVCLK_DIVIDE = 1; + parameter EN_REL = "FALSE"; + parameter PLL_PMCD_MODE = "FALSE"; + parameter real REF_JITTER = 0.100; + parameter RESET_ON_LOSS_OF_LOCK = "FALSE"; + parameter RST_DEASSERT_CLK = "CLKIN1"; + parameter SIM_DEVICE = "VIRTEX5"; + parameter real VCOCLK_FREQ_MAX = 1440.0; + parameter real VCOCLK_FREQ_MIN = 400.0; + parameter real CLKIN_FREQ_MAX = 710.0; + parameter real CLKIN_FREQ_MIN = 19.0; + parameter real CLKPFD_FREQ_MAX = 550.0; + parameter real CLKPFD_FREQ_MIN = 19.0; + output CLKFBDCM; + output CLKFBOUT; + output CLKOUT0; + output CLKOUT1; + output CLKOUT2; + output CLKOUT3; + output CLKOUT4; + output CLKOUT5; + output CLKOUTDCM0; + output CLKOUTDCM1; + output CLKOUTDCM2; + output CLKOUTDCM3; + output CLKOUTDCM4; + output CLKOUTDCM5; + output DRDY; + output LOCKED; + output [15:0] DO; + input CLKFBIN; + input CLKIN1; + input CLKIN2; + input CLKINSEL; + input DCLK; + input DEN; + input DWE; + input REL; + input RST; + input [15:0] DI; + input [4:0] DADDR; +endmodule + +module PLL_BASE (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter integer CLKFBOUT_MULT = 1; + parameter real CLKFBOUT_PHASE = 0.0; + parameter real CLKIN_PERIOD = 0.000; + parameter integer CLKOUT0_DIVIDE = 1; + parameter real CLKOUT0_DUTY_CYCLE = 0.5; + parameter real CLKOUT0_PHASE = 0.0; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.5; + parameter real CLKOUT1_PHASE = 0.0; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.5; + parameter real CLKOUT2_PHASE = 0.0; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.5; + parameter real CLKOUT3_PHASE = 0.0; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.5; + parameter real CLKOUT4_PHASE = 0.0; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.5; + parameter real CLKOUT5_PHASE = 0.0; + parameter CLK_FEEDBACK = "CLKFBOUT"; + parameter COMPENSATION = "SYSTEM_SYNCHRONOUS"; + parameter integer DIVCLK_DIVIDE = 1; + parameter real REF_JITTER = 0.100; + parameter RESET_ON_LOSS_OF_LOCK = "FALSE"; + output CLKFBOUT; + output CLKOUT0; + output CLKOUT1; + output CLKOUT2; + output CLKOUT3; + output CLKOUT4; + output CLKOUT5; + output LOCKED; + input CLKFBIN; + input CLKIN; + input RST; +endmodule + +module MMCM_ADV (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter CLKFBOUT_USE_FINE_PS = "FALSE"; + parameter CLKOUT0_USE_FINE_PS = "FALSE"; + parameter CLKOUT1_USE_FINE_PS = "FALSE"; + parameter CLKOUT2_USE_FINE_PS = "FALSE"; + parameter CLKOUT3_USE_FINE_PS = "FALSE"; + parameter CLKOUT4_CASCADE = "FALSE"; + parameter CLKOUT4_USE_FINE_PS = "FALSE"; + parameter CLKOUT5_USE_FINE_PS = "FALSE"; + parameter CLKOUT6_USE_FINE_PS = "FALSE"; + parameter CLOCK_HOLD = "FALSE"; + parameter COMPENSATION = "ZHOLD"; + parameter STARTUP_WAIT = "FALSE"; + parameter integer CLKOUT1_DIVIDE = 1; + parameter integer CLKOUT2_DIVIDE = 1; + parameter integer CLKOUT3_DIVIDE = 1; + parameter integer CLKOUT4_DIVIDE = 1; + parameter integer CLKOUT5_DIVIDE = 1; + parameter integer CLKOUT6_DIVIDE = 1; + parameter integer DIVCLK_DIVIDE = 1; + parameter real CLKFBOUT_MULT_F = 5.000; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKIN2_PERIOD = 0.000; + parameter real CLKOUT0_DIVIDE_F = 1.000; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter real CLKOUT6_DUTY_CYCLE = 0.500; + parameter real CLKOUT6_PHASE = 0.000; + parameter real REF_JITTER1 = 0.010; + parameter real REF_JITTER2 = 0.010; + parameter real VCOCLK_FREQ_MAX = 1600.0; + parameter real VCOCLK_FREQ_MIN = 600.0; + parameter real CLKIN_FREQ_MAX = 800.0; + parameter real CLKIN_FREQ_MIN = 10.0; + parameter real CLKPFD_FREQ_MAX = 550.0; + parameter real CLKPFD_FREQ_MIN = 10.0; + output CLKFBOUT; + output CLKFBOUTB; + output CLKFBSTOPPED; + output CLKINSTOPPED; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUT2; + output CLKOUT2B; + output CLKOUT3; + output CLKOUT3B; + output CLKOUT4; + output CLKOUT5; + output CLKOUT6; + output DRDY; + output LOCKED; + output PSDONE; + output [15:0] DO; + input CLKFBIN; + input CLKIN1; + input CLKIN2; + input CLKINSEL; + input DCLK; + input DEN; + input DWE; + input PSCLK; + input PSEN; + input PSINCDEC; + input PWRDWN; + input RST; + input [15:0] DI; + input [6:0] DADDR; +endmodule + +module MMCM_BASE (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter real CLKFBOUT_MULT_F = 5.000; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKOUT0_DIVIDE_F = 1.000; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter CLKOUT4_CASCADE = "FALSE"; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter integer CLKOUT6_DIVIDE = 1; + parameter real CLKOUT6_DUTY_CYCLE = 0.500; + parameter real CLKOUT6_PHASE = 0.000; + parameter CLOCK_HOLD = "FALSE"; + parameter integer DIVCLK_DIVIDE = 1; + parameter real REF_JITTER1 = 0.010; + parameter STARTUP_WAIT = "FALSE"; + output CLKFBOUT; + output CLKFBOUTB; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUT2; + output CLKOUT2B; + output CLKOUT3; + output CLKOUT3B; + output CLKOUT4; + output CLKOUT5; + output CLKOUT6; + output LOCKED; + input CLKFBIN; + input CLKIN1; + input PWRDWN; + input RST; +endmodule + +module MMCME2_ADV (...); + parameter real CLKIN_FREQ_MAX = 1066.000; + parameter real CLKIN_FREQ_MIN = 10.000; + parameter real CLKPFD_FREQ_MAX = 550.000; + parameter real CLKPFD_FREQ_MIN = 10.000; + parameter real VCOCLK_FREQ_MAX = 1600.000; + parameter real VCOCLK_FREQ_MIN = 600.000; + parameter BANDWIDTH = "OPTIMIZED"; + parameter real CLKFBOUT_MULT_F = 5.000; + parameter real CLKFBOUT_PHASE = 0.000; + parameter CLKFBOUT_USE_FINE_PS = "FALSE"; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKIN2_PERIOD = 0.000; + parameter real CLKOUT0_DIVIDE_F = 1.000; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter CLKOUT0_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter CLKOUT1_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter CLKOUT2_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter CLKOUT3_USE_FINE_PS = "FALSE"; + parameter CLKOUT4_CASCADE = "FALSE"; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter CLKOUT4_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter CLKOUT5_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT6_DIVIDE = 1; + parameter real CLKOUT6_DUTY_CYCLE = 0.500; + parameter real CLKOUT6_PHASE = 0.000; + parameter CLKOUT6_USE_FINE_PS = "FALSE"; + parameter COMPENSATION = "ZHOLD"; + parameter integer DIVCLK_DIVIDE = 1; + parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0; + parameter [0:0] IS_PSEN_INVERTED = 1'b0; + parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0; + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REF_JITTER1 = 0.010; + parameter real REF_JITTER2 = 0.010; + parameter SS_EN = "FALSE"; + parameter SS_MODE = "CENTER_HIGH"; + parameter integer SS_MOD_PERIOD = 10000; + parameter STARTUP_WAIT = "FALSE"; + output CLKFBOUT; + output CLKFBOUTB; + output CLKFBSTOPPED; + output CLKINSTOPPED; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUT2; + output CLKOUT2B; + output CLKOUT3; + output CLKOUT3B; + output CLKOUT4; + output CLKOUT5; + output CLKOUT6; + output [15:0] DO; + output DRDY; + output LOCKED; + output PSDONE; + input CLKFBIN; + input CLKIN1; + input CLKIN2; + (* invertible_pin = "IS_CLKINSEL_INVERTED" *) + input CLKINSEL; + input [6:0] DADDR; + input DCLK; + input DEN; + input [15:0] DI; + input DWE; + input PSCLK; + (* invertible_pin = "IS_PSEN_INVERTED" *) + input PSEN; + (* invertible_pin = "IS_PSINCDEC_INVERTED" *) + input PSINCDEC; + (* invertible_pin = "IS_PWRDWN_INVERTED" *) + input PWRDWN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module MMCME2_BASE (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter real CLKFBOUT_MULT_F = 5.000; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKOUT0_DIVIDE_F = 1.000; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter CLKOUT4_CASCADE = "FALSE"; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter integer CLKOUT6_DIVIDE = 1; + parameter real CLKOUT6_DUTY_CYCLE = 0.500; + parameter real CLKOUT6_PHASE = 0.000; + parameter integer DIVCLK_DIVIDE = 1; + parameter real REF_JITTER1 = 0.010; + parameter STARTUP_WAIT = "FALSE"; + output CLKFBOUT; + output CLKFBOUTB; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUT2; + output CLKOUT2B; + output CLKOUT3; + output CLKOUT3B; + output CLKOUT4; + output CLKOUT5; + output CLKOUT6; + output LOCKED; + input CLKFBIN; + input CLKIN1; + input PWRDWN; + input RST; +endmodule + +module PLLE2_ADV (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter COMPENSATION = "ZHOLD"; + parameter STARTUP_WAIT = "FALSE"; + parameter integer CLKOUT0_DIVIDE = 1; + parameter integer CLKOUT1_DIVIDE = 1; + parameter integer CLKOUT2_DIVIDE = 1; + parameter integer CLKOUT3_DIVIDE = 1; + parameter integer CLKOUT4_DIVIDE = 1; + parameter integer CLKOUT5_DIVIDE = 1; + parameter integer DIVCLK_DIVIDE = 1; + parameter integer CLKFBOUT_MULT = 5; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKIN2_PERIOD = 0.000; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0; + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REF_JITTER1 = 0.010; + parameter real REF_JITTER2 = 0.010; + parameter real VCOCLK_FREQ_MAX = 2133.000; + parameter real VCOCLK_FREQ_MIN = 800.000; + parameter real CLKIN_FREQ_MAX = 1066.000; + parameter real CLKIN_FREQ_MIN = 19.000; + parameter real CLKPFD_FREQ_MAX = 550.0; + parameter real CLKPFD_FREQ_MIN = 19.0; + output CLKFBOUT; + output CLKOUT0; + output CLKOUT1; + output CLKOUT2; + output CLKOUT3; + output CLKOUT4; + output CLKOUT5; + output DRDY; + output LOCKED; + output [15:0] DO; + input CLKFBIN; + input CLKIN1; + input CLKIN2; + (* invertible_pin = "IS_CLKINSEL_INVERTED" *) + input CLKINSEL; + input DCLK; + input DEN; + input DWE; + (* invertible_pin = "IS_PWRDWN_INVERTED" *) + input PWRDWN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + input [15:0] DI; + input [6:0] DADDR; +endmodule + +module PLLE2_BASE (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter integer CLKFBOUT_MULT = 5; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN1_PERIOD = 0.000; + parameter integer CLKOUT0_DIVIDE = 1; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter integer DIVCLK_DIVIDE = 1; + parameter real REF_JITTER1 = 0.010; + parameter STARTUP_WAIT = "FALSE"; + output CLKFBOUT; + output CLKOUT0; + output CLKOUT1; + output CLKOUT2; + output CLKOUT3; + output CLKOUT4; + output CLKOUT5; + output LOCKED; + input CLKFBIN; + input CLKIN1; + input PWRDWN; + input RST; +endmodule + +module MMCME3_ADV (...); + parameter real CLKIN_FREQ_MAX = 1066.000; + parameter real CLKIN_FREQ_MIN = 10.000; + parameter real CLKPFD_FREQ_MAX = 550.000; + parameter real CLKPFD_FREQ_MIN = 10.000; + parameter real VCOCLK_FREQ_MAX = 1600.000; + parameter real VCOCLK_FREQ_MIN = 600.000; + parameter BANDWIDTH = "OPTIMIZED"; + parameter real CLKFBOUT_MULT_F = 5.000; + parameter real CLKFBOUT_PHASE = 0.000; + parameter CLKFBOUT_USE_FINE_PS = "FALSE"; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKIN2_PERIOD = 0.000; + parameter real CLKOUT0_DIVIDE_F = 1.000; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter CLKOUT0_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter CLKOUT1_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter CLKOUT2_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter CLKOUT3_USE_FINE_PS = "FALSE"; + parameter CLKOUT4_CASCADE = "FALSE"; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter CLKOUT4_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter CLKOUT5_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT6_DIVIDE = 1; + parameter real CLKOUT6_DUTY_CYCLE = 0.500; + parameter real CLKOUT6_PHASE = 0.000; + parameter CLKOUT6_USE_FINE_PS = "FALSE"; + parameter COMPENSATION = "AUTO"; + parameter integer DIVCLK_DIVIDE = 1; + parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; + parameter [0:0] IS_CLKIN1_INVERTED = 1'b0; + parameter [0:0] IS_CLKIN2_INVERTED = 1'b0; + parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0; + parameter [0:0] IS_PSEN_INVERTED = 1'b0; + parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0; + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REF_JITTER1 = 0.010; + parameter real REF_JITTER2 = 0.010; + parameter SS_EN = "FALSE"; + parameter SS_MODE = "CENTER_HIGH"; + parameter integer SS_MOD_PERIOD = 10000; + parameter STARTUP_WAIT = "FALSE"; + output CDDCDONE; + output CLKFBOUT; + output CLKFBOUTB; + output CLKFBSTOPPED; + output CLKINSTOPPED; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUT2; + output CLKOUT2B; + output CLKOUT3; + output CLKOUT3B; + output CLKOUT4; + output CLKOUT5; + output CLKOUT6; + output [15:0] DO; + output DRDY; + output LOCKED; + output PSDONE; + input CDDCREQ; + (* invertible_pin = "IS_CLKFBIN_INVERTED" *) + input CLKFBIN; + (* invertible_pin = "IS_CLKIN1_INVERTED" *) + input CLKIN1; + (* invertible_pin = "IS_CLKIN2_INVERTED" *) + input CLKIN2; + (* invertible_pin = "IS_CLKINSEL_INVERTED" *) + input CLKINSEL; + input [6:0] DADDR; + input DCLK; + input DEN; + input [15:0] DI; + input DWE; + input PSCLK; + (* invertible_pin = "IS_PSEN_INVERTED" *) + input PSEN; + (* invertible_pin = "IS_PSINCDEC_INVERTED" *) + input PSINCDEC; + (* invertible_pin = "IS_PWRDWN_INVERTED" *) + input PWRDWN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module MMCME3_BASE (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter real CLKFBOUT_MULT_F = 5.000; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKOUT0_DIVIDE_F = 1.000; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter CLKOUT4_CASCADE = "FALSE"; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter integer CLKOUT6_DIVIDE = 1; + parameter real CLKOUT6_DUTY_CYCLE = 0.500; + parameter real CLKOUT6_PHASE = 0.000; + parameter integer DIVCLK_DIVIDE = 1; + parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; + parameter [0:0] IS_CLKIN1_INVERTED = 1'b0; + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REF_JITTER1 = 0.010; + parameter STARTUP_WAIT = "FALSE"; + output CLKFBOUT; + output CLKFBOUTB; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUT2; + output CLKOUT2B; + output CLKOUT3; + output CLKOUT3B; + output CLKOUT4; + output CLKOUT5; + output CLKOUT6; + output LOCKED; + (* invertible_pin = "IS_CLKFBIN_INVERTED" *) + input CLKFBIN; + (* invertible_pin = "IS_CLKIN1_INVERTED" *) + input CLKIN1; + (* invertible_pin = "IS_PWRDWN_INVERTED" *) + input PWRDWN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module PLLE3_ADV (...); + parameter real CLKIN_FREQ_MAX = 1066.000; + parameter real CLKIN_FREQ_MIN = 70.000; + parameter real CLKPFD_FREQ_MAX = 667.500; + parameter real CLKPFD_FREQ_MIN = 70.000; + parameter real VCOCLK_FREQ_MAX = 1335.000; + parameter real VCOCLK_FREQ_MIN = 600.000; + parameter integer CLKFBOUT_MULT = 5; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN_PERIOD = 0.000; + parameter integer CLKOUT0_DIVIDE = 1; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter CLKOUTPHY_MODE = "VCO_2X"; + parameter COMPENSATION = "AUTO"; + parameter integer DIVCLK_DIVIDE = 1; + parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; + parameter [0:0] IS_CLKIN_INVERTED = 1'b0; + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REF_JITTER = 0.010; + parameter STARTUP_WAIT = "FALSE"; + output CLKFBOUT; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUTPHY; + output [15:0] DO; + output DRDY; + output LOCKED; + (* invertible_pin = "IS_CLKFBIN_INVERTED" *) + input CLKFBIN; + (* invertible_pin = "IS_CLKIN_INVERTED" *) + input CLKIN; + input CLKOUTPHYEN; + input [6:0] DADDR; + input DCLK; + input DEN; + input [15:0] DI; + input DWE; + (* invertible_pin = "IS_PWRDWN_INVERTED" *) + input PWRDWN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module PLLE3_BASE (...); + parameter integer CLKFBOUT_MULT = 5; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN_PERIOD = 0.000; + parameter integer CLKOUT0_DIVIDE = 1; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter CLKOUTPHY_MODE = "VCO_2X"; + parameter integer DIVCLK_DIVIDE = 1; + parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; + parameter [0:0] IS_CLKIN_INVERTED = 1'b0; + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REF_JITTER = 0.010; + parameter STARTUP_WAIT = "FALSE"; + output CLKFBOUT; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUTPHY; + output LOCKED; + (* invertible_pin = "IS_CLKFBIN_INVERTED" *) + input CLKFBIN; + (* invertible_pin = "IS_CLKIN_INVERTED" *) + input CLKIN; + input CLKOUTPHYEN; + (* invertible_pin = "IS_PWRDWN_INVERTED" *) + input PWRDWN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module MMCME4_ADV (...); + parameter real CLKIN_FREQ_MAX = 1066.000; + parameter real CLKIN_FREQ_MIN = 10.000; + parameter real CLKPFD_FREQ_MAX = 550.000; + parameter real CLKPFD_FREQ_MIN = 10.000; + parameter real VCOCLK_FREQ_MAX = 1600.000; + parameter real VCOCLK_FREQ_MIN = 800.000; + parameter BANDWIDTH = "OPTIMIZED"; + parameter real CLKFBOUT_MULT_F = 5.000; + parameter real CLKFBOUT_PHASE = 0.000; + parameter CLKFBOUT_USE_FINE_PS = "FALSE"; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKIN2_PERIOD = 0.000; + parameter real CLKOUT0_DIVIDE_F = 1.000; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter CLKOUT0_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter CLKOUT1_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter CLKOUT2_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter CLKOUT3_USE_FINE_PS = "FALSE"; + parameter CLKOUT4_CASCADE = "FALSE"; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter CLKOUT4_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter CLKOUT5_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT6_DIVIDE = 1; + parameter real CLKOUT6_DUTY_CYCLE = 0.500; + parameter real CLKOUT6_PHASE = 0.000; + parameter CLKOUT6_USE_FINE_PS = "FALSE"; + parameter COMPENSATION = "AUTO"; + parameter integer DIVCLK_DIVIDE = 1; + parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; + parameter [0:0] IS_CLKIN1_INVERTED = 1'b0; + parameter [0:0] IS_CLKIN2_INVERTED = 1'b0; + parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0; + parameter [0:0] IS_PSEN_INVERTED = 1'b0; + parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0; + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REF_JITTER1 = 0.010; + parameter real REF_JITTER2 = 0.010; + parameter SS_EN = "FALSE"; + parameter SS_MODE = "CENTER_HIGH"; + parameter integer SS_MOD_PERIOD = 10000; + parameter STARTUP_WAIT = "FALSE"; + output CDDCDONE; + output CLKFBOUT; + output CLKFBOUTB; + output CLKFBSTOPPED; + output CLKINSTOPPED; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUT2; + output CLKOUT2B; + output CLKOUT3; + output CLKOUT3B; + output CLKOUT4; + output CLKOUT5; + output CLKOUT6; + output [15:0] DO; + output DRDY; + output LOCKED; + output PSDONE; + input CDDCREQ; + (* invertible_pin = "IS_CLKFBIN_INVERTED" *) + input CLKFBIN; + (* invertible_pin = "IS_CLKIN1_INVERTED" *) + input CLKIN1; + (* invertible_pin = "IS_CLKIN2_INVERTED" *) + input CLKIN2; + (* invertible_pin = "IS_CLKINSEL_INVERTED" *) + input CLKINSEL; + input [6:0] DADDR; + input DCLK; + input DEN; + input [15:0] DI; + input DWE; + input PSCLK; + (* invertible_pin = "IS_PSEN_INVERTED" *) + input PSEN; + (* invertible_pin = "IS_PSINCDEC_INVERTED" *) + input PSINCDEC; + (* invertible_pin = "IS_PWRDWN_INVERTED" *) + input PWRDWN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module MMCME4_BASE (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter real CLKFBOUT_MULT_F = 5.000; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKOUT0_DIVIDE_F = 1.000; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter CLKOUT4_CASCADE = "FALSE"; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter integer CLKOUT6_DIVIDE = 1; + parameter real CLKOUT6_DUTY_CYCLE = 0.500; + parameter real CLKOUT6_PHASE = 0.000; + parameter integer DIVCLK_DIVIDE = 1; + parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; + parameter [0:0] IS_CLKIN1_INVERTED = 1'b0; + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REF_JITTER1 = 0.010; + parameter STARTUP_WAIT = "FALSE"; + output CLKFBOUT; + output CLKFBOUTB; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUT2; + output CLKOUT2B; + output CLKOUT3; + output CLKOUT3B; + output CLKOUT4; + output CLKOUT5; + output CLKOUT6; + output LOCKED; + (* invertible_pin = "IS_CLKFBIN_INVERTED" *) + input CLKFBIN; + (* invertible_pin = "IS_CLKIN1_INVERTED" *) + input CLKIN1; + (* invertible_pin = "IS_PWRDWN_INVERTED" *) + input PWRDWN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module PLLE4_ADV (...); + parameter real CLKIN_FREQ_MAX = 1066.000; + parameter real CLKIN_FREQ_MIN = 70.000; + parameter real CLKPFD_FREQ_MAX = 667.500; + parameter real CLKPFD_FREQ_MIN = 70.000; + parameter real VCOCLK_FREQ_MAX = 1500.000; + parameter real VCOCLK_FREQ_MIN = 750.000; + parameter integer CLKFBOUT_MULT = 5; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN_PERIOD = 0.000; + parameter integer CLKOUT0_DIVIDE = 1; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter CLKOUTPHY_MODE = "VCO_2X"; + parameter COMPENSATION = "AUTO"; + parameter integer DIVCLK_DIVIDE = 1; + parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; + parameter [0:0] IS_CLKIN_INVERTED = 1'b0; + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REF_JITTER = 0.010; + parameter STARTUP_WAIT = "FALSE"; + output CLKFBOUT; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUTPHY; + output [15:0] DO; + output DRDY; + output LOCKED; + (* invertible_pin = "IS_CLKFBIN_INVERTED" *) + input CLKFBIN; + (* invertible_pin = "IS_CLKIN_INVERTED" *) + input CLKIN; + input CLKOUTPHYEN; + input [6:0] DADDR; + input DCLK; + input DEN; + input [15:0] DI; + input DWE; + (* invertible_pin = "IS_PWRDWN_INVERTED" *) + input PWRDWN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module PLLE4_BASE (...); + parameter integer CLKFBOUT_MULT = 5; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN_PERIOD = 0.000; + parameter integer CLKOUT0_DIVIDE = 1; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter CLKOUTPHY_MODE = "VCO_2X"; + parameter integer DIVCLK_DIVIDE = 1; + parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; + parameter [0:0] IS_CLKIN_INVERTED = 1'b0; + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REF_JITTER = 0.010; + parameter STARTUP_WAIT = "FALSE"; + output CLKFBOUT; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUTPHY; + output LOCKED; + (* invertible_pin = "IS_CLKFBIN_INVERTED" *) + input CLKFBIN; + (* invertible_pin = "IS_CLKIN_INVERTED" *) + input CLKIN; + input CLKOUTPHYEN; + (* invertible_pin = "IS_PWRDWN_INVERTED" *) + input PWRDWN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module BUFT (...); + output O; + input I; + input T; +endmodule + +module IN_FIFO (...); + parameter integer ALMOST_EMPTY_VALUE = 1; + parameter integer ALMOST_FULL_VALUE = 1; + parameter ARRAY_MODE = "ARRAY_MODE_4_X_8"; + parameter SYNCHRONOUS_MODE = "FALSE"; + output ALMOSTEMPTY; + output ALMOSTFULL; + output EMPTY; + output FULL; + output [7:0] Q0; + output [7:0] Q1; + output [7:0] Q2; + output [7:0] Q3; + output [7:0] Q4; + output [7:0] Q5; + output [7:0] Q6; + output [7:0] Q7; + output [7:0] Q8; + output [7:0] Q9; + (* clkbuf_sink *) + input RDCLK; + input RDEN; + input RESET; + (* clkbuf_sink *) + input WRCLK; + input WREN; + input [3:0] D0; + input [3:0] D1; + input [3:0] D2; + input [3:0] D3; + input [3:0] D4; + input [3:0] D7; + input [3:0] D8; + input [3:0] D9; + input [7:0] D5; + input [7:0] D6; +endmodule + +module OUT_FIFO (...); + parameter integer ALMOST_EMPTY_VALUE = 1; + parameter integer ALMOST_FULL_VALUE = 1; + parameter ARRAY_MODE = "ARRAY_MODE_8_X_4"; + parameter OUTPUT_DISABLE = "FALSE"; + parameter SYNCHRONOUS_MODE = "FALSE"; + output ALMOSTEMPTY; + output ALMOSTFULL; + output EMPTY; + output FULL; + output [3:0] Q0; + output [3:0] Q1; + output [3:0] Q2; + output [3:0] Q3; + output [3:0] Q4; + output [3:0] Q7; + output [3:0] Q8; + output [3:0] Q9; + output [7:0] Q5; + output [7:0] Q6; + (* clkbuf_sink *) + input RDCLK; + input RDEN; + input RESET; + (* clkbuf_sink *) + input WRCLK; + input WREN; + input [7:0] D0; + input [7:0] D1; + input [7:0] D2; + input [7:0] D3; + input [7:0] D4; + input [7:0] D5; + input [7:0] D6; + input [7:0] D7; + input [7:0] D8; + input [7:0] D9; +endmodule + +module HARD_SYNC (...); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter integer LATENCY = 2; + output DOUT; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + input DIN; +endmodule + +(* keep *) +module STARTUP_SPARTAN3 (...); + input CLK; + input GSR; + input GTS; +endmodule + +(* keep *) +module STARTUP_SPARTAN3E (...); + input CLK; + input GSR; + input GTS; + input MBT; +endmodule + +(* keep *) +module STARTUP_SPARTAN3A (...); + input CLK; + input GSR; + input GTS; +endmodule + +(* keep *) +module STARTUP_SPARTAN6 (...); + output CFGCLK; + output CFGMCLK; + output EOS; + input CLK; + input GSR; + input GTS; + input KEYCLEARB; +endmodule + +(* keep *) +module STARTUP_VIRTEX4 (...); + output EOS; + input CLK; + input GSR; + input GTS; + input USRCCLKO; + input USRCCLKTS; + input USRDONEO; + input USRDONETS; +endmodule + +(* keep *) +module STARTUP_VIRTEX5 (...); + output CFGCLK; + output CFGMCLK; + output DINSPI; + output EOS; + output TCKSPI; + input CLK; + input GSR; + input GTS; + input USRCCLKO; + input USRCCLKTS; + input USRDONEO; + input USRDONETS; +endmodule + +(* keep *) +module STARTUP_VIRTEX6 (...); + parameter PROG_USR = "FALSE"; + output CFGCLK; + output CFGMCLK; + output DINSPI; + output EOS; + output PREQ; + output TCKSPI; + input CLK; + input GSR; + input GTS; + input KEYCLEARB; + input PACK; + input USRCCLKO; + input USRCCLKTS; + input USRDONEO; + input USRDONETS; +endmodule + +(* keep *) +module STARTUPE2 (...); + parameter PROG_USR = "FALSE"; + parameter real SIM_CCLK_FREQ = 0.0; + output CFGCLK; + output CFGMCLK; + output EOS; + output PREQ; + input CLK; + input GSR; + input GTS; + input KEYCLEARB; + input PACK; + input USRCCLKO; + input USRCCLKTS; + input USRDONEO; + input USRDONETS; +endmodule + +(* keep *) +module STARTUPE3 (...); + parameter PROG_USR = "FALSE"; + parameter real SIM_CCLK_FREQ = 0.0; + output CFGCLK; + output CFGMCLK; + output [3:0] DI; + output EOS; + output PREQ; + input [3:0] DO; + input [3:0] DTS; + input FCSBO; + input FCSBTS; + input GSR; + input GTS; + input KEYCLEARB; + input PACK; + input USRCCLKO; + input USRCCLKTS; + input USRDONEO; + input USRDONETS; +endmodule + +(* keep *) +module CAPTURE_SPARTAN3 (...); + parameter ONESHOT = "FALSE"; + input CAP; + input CLK; +endmodule + +(* keep *) +module CAPTURE_SPARTAN3A (...); + parameter ONESHOT = "TRUE"; + input CAP; + input CLK; +endmodule + +(* keep *) +module CAPTURE_VIRTEX4 (...); + parameter ONESHOT = "TRUE"; + input CAP; + input CLK; +endmodule + +(* keep *) +module CAPTURE_VIRTEX5 (...); + parameter ONESHOT = "TRUE"; + input CAP; + input CLK; +endmodule + +(* keep *) +module CAPTURE_VIRTEX6 (...); + parameter ONESHOT = "TRUE"; + input CAP; + input CLK; +endmodule + +(* keep *) +module CAPTUREE2 (...); + parameter ONESHOT = "TRUE"; + input CAP; + input CLK; +endmodule + +(* keep *) +module ICAP_SPARTAN3A (...); + output BUSY; + output [7:0] O; + input CE; + input CLK; + input WRITE; + input [7:0] I; +endmodule + +(* keep *) +module ICAP_SPARTAN6 (...); + parameter DEVICE_ID = 32'h04000093; + parameter SIM_CFG_FILE_NAME = "NONE"; + output BUSY; + output [15:0] O; + input CLK; + input CE; + input WRITE; + input [15:0] I; +endmodule + +(* keep *) +module ICAP_VIRTEX4 (...); + parameter ICAP_WIDTH = "X8"; + output BUSY; + output [31:0] O; + input CE; + input CLK; + input WRITE; + input [31:0] I; +endmodule + +(* keep *) +module ICAP_VIRTEX5 (...); + parameter ICAP_WIDTH = "X8"; + output BUSY; + output [31:0] O; + input CE; + input CLK; + input WRITE; + input [31:0] I; +endmodule + +(* keep *) +module ICAP_VIRTEX6 (...); + parameter [31:0] DEVICE_ID = 32'h04244093; + parameter ICAP_WIDTH = "X8"; + parameter SIM_CFG_FILE_NAME = "NONE"; + output BUSY; + output [31:0] O; + input CLK; + input CSB; + input RDWRB; + input [31:0] I; +endmodule + +(* keep *) +module ICAPE2 (...); + parameter [31:0] DEVICE_ID = 32'h04244093; + parameter ICAP_WIDTH = "X32"; + parameter SIM_CFG_FILE_NAME = "NONE"; + output [31:0] O; + input CLK; + input CSIB; + input RDWRB; + input [31:0] I; +endmodule + +(* keep *) +module ICAPE3 (...); + parameter [31:0] DEVICE_ID = 32'h03628093; + parameter ICAP_AUTO_SWITCH = "DISABLE"; + parameter SIM_CFG_FILE_NAME = "NONE"; + output AVAIL; + output [31:0] O; + output PRDONE; + output PRERROR; + input CLK; + input CSIB; + input RDWRB; + input [31:0] I; +endmodule + +(* keep *) +module BSCAN_SPARTAN3 (...); + output CAPTURE; + output DRCK1; + output DRCK2; + output RESET; + output SEL1; + output SEL2; + output SHIFT; + output TDI; + output UPDATE; + input TDO1; + input TDO2; +endmodule + +(* keep *) +module BSCAN_SPARTAN3A (...); + output CAPTURE; + output DRCK1; + output DRCK2; + output RESET; + output SEL1; + output SEL2; + output SHIFT; + output TCK; + output TDI; + output TMS; + output UPDATE; + input TDO1; + input TDO2; +endmodule + +(* keep *) +module BSCAN_SPARTAN6 (...); + parameter integer JTAG_CHAIN = 1; + output CAPTURE; + output DRCK; + output RESET; + output RUNTEST; + output SEL; + output SHIFT; + output TCK; + output TDI; + output TMS; + output UPDATE; + input TDO; +endmodule + +(* keep *) +module BSCAN_VIRTEX4 (...); + parameter integer JTAG_CHAIN = 1; + output CAPTURE; + output DRCK; + output RESET; + output SEL; + output SHIFT; + output TDI; + output UPDATE; + input TDO; +endmodule + +(* keep *) +module BSCAN_VIRTEX5 (...); + parameter integer JTAG_CHAIN = 1; + output CAPTURE; + output DRCK; + output RESET; + output SEL; + output SHIFT; + output TDI; + output UPDATE; + input TDO; +endmodule + +(* keep *) +module BSCAN_VIRTEX6 (...); + parameter DISABLE_JTAG = "FALSE"; + parameter integer JTAG_CHAIN = 1; + output CAPTURE; + output DRCK; + output RESET; + output RUNTEST; + output SEL; + output SHIFT; + output TCK; + output TDI; + output TMS; + output UPDATE; + input TDO; +endmodule + +(* keep *) +module BSCANE2 (...); + parameter DISABLE_JTAG = "FALSE"; + parameter integer JTAG_CHAIN = 1; + output CAPTURE; + output DRCK; + output RESET; + output RUNTEST; + output SEL; + output SHIFT; + output TCK; + output TDI; + output TMS; + output UPDATE; + input TDO; +endmodule + +module DNA_PORT (...); + parameter [56:0] SIM_DNA_VALUE = 57'h0; + output DOUT; + input CLK; + input DIN; + input READ; + input SHIFT; +endmodule + +module DNA_PORTE2 (...); + parameter [95:0] SIM_DNA_VALUE = 96'h000000000000000000000000; + output DOUT; + input CLK; + input DIN; + input READ; + input SHIFT; +endmodule + +module FRAME_ECC_VIRTEX4 (...); + output ERROR; + output [11:0] SYNDROME; + output SYNDROMEVALID; +endmodule + +module FRAME_ECC_VIRTEX5 (...); + output CRCERROR; + output ECCERROR; + output SYNDROMEVALID; + output [11:0] SYNDROME; +endmodule + +module FRAME_ECC_VIRTEX6 (...); + parameter FARSRC = "EFAR"; + parameter FRAME_RBT_IN_FILENAME = "NONE"; + output CRCERROR; + output ECCERROR; + output ECCERRORSINGLE; + output SYNDROMEVALID; + output [12:0] SYNDROME; + output [23:0] FAR; + output [4:0] SYNBIT; + output [6:0] SYNWORD; +endmodule + +module FRAME_ECCE2 (...); + parameter FARSRC = "EFAR"; + parameter FRAME_RBT_IN_FILENAME = "NONE"; + output CRCERROR; + output ECCERROR; + output ECCERRORSINGLE; + output SYNDROMEVALID; + output [12:0] SYNDROME; + output [25:0] FAR; + output [4:0] SYNBIT; + output [6:0] SYNWORD; +endmodule + +module FRAME_ECCE3 (...); + output CRCERROR; + output ECCERRORNOTSINGLE; + output ECCERRORSINGLE; + output ENDOFFRAME; + output ENDOFSCAN; + output [25:0] FAR; + input [1:0] FARSEL; + input ICAPBOTCLK; + input ICAPTOPCLK; +endmodule + +module FRAME_ECCE4 (...); + output CRCERROR; + output ECCERRORNOTSINGLE; + output ECCERRORSINGLE; + output ENDOFFRAME; + output ENDOFSCAN; + output [26:0] FAR; + input [1:0] FARSEL; + input ICAPBOTCLK; + input ICAPTOPCLK; +endmodule + +module USR_ACCESS_VIRTEX4 (...); + output [31:0] DATA; + output DATAVALID; +endmodule + +module USR_ACCESS_VIRTEX5 (...); + output CFGCLK; + output [31:0] DATA; + output DATAVALID; +endmodule + +module USR_ACCESS_VIRTEX6 (...); + output CFGCLK; + output [31:0] DATA; + output DATAVALID; +endmodule + +module USR_ACCESSE2 (...); + output CFGCLK; + output DATAVALID; + output [31:0] DATA; +endmodule + +module POST_CRC_INTERNAL (...); + output CRCERROR; +endmodule + +(* keep *) +module SUSPEND_SYNC (...); + output SREQ; + input CLK; + input SACK; +endmodule + +(* keep *) +module KEY_CLEAR (...); + input KEYCLEARB; +endmodule + +(* keep *) +module MASTER_JTAG (...); + output TDO; + input TCK; + input TDI; + input TMS; +endmodule + +(* keep *) +module SPI_ACCESS (...); + parameter SIM_DELAY_TYPE = "SCALED"; + parameter SIM_DEVICE = "3S1400AN"; + parameter SIM_FACTORY_ID = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter SIM_MEM_FILE = "NONE"; + parameter SIM_USER_ID = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; + output MISO; + input CLK; + input CSB; + input MOSI; +endmodule + +module EFUSE_USR (...); + parameter [31:0] SIM_EFUSE_VALUE = 32'h00000000; + output [31:0] EFUSEUSR; +endmodule + +(* keep *) +module SYSMON (...); + parameter [15:0] INIT_40 = 16'h0; + parameter [15:0] INIT_41 = 16'h0; + parameter [15:0] INIT_42 = 16'h0800; + parameter [15:0] INIT_43 = 16'h0; + parameter [15:0] INIT_44 = 16'h0; + parameter [15:0] INIT_45 = 16'h0; + parameter [15:0] INIT_46 = 16'h0; + parameter [15:0] INIT_47 = 16'h0; + parameter [15:0] INIT_48 = 16'h0; + parameter [15:0] INIT_49 = 16'h0; + parameter [15:0] INIT_4A = 16'h0; + parameter [15:0] INIT_4B = 16'h0; + parameter [15:0] INIT_4C = 16'h0; + parameter [15:0] INIT_4D = 16'h0; + parameter [15:0] INIT_4E = 16'h0; + parameter [15:0] INIT_4F = 16'h0; + parameter [15:0] INIT_50 = 16'h0; + parameter [15:0] INIT_51 = 16'h0; + parameter [15:0] INIT_52 = 16'h0; + parameter [15:0] INIT_53 = 16'h0; + parameter [15:0] INIT_54 = 16'h0; + parameter [15:0] INIT_55 = 16'h0; + parameter [15:0] INIT_56 = 16'h0; + parameter [15:0] INIT_57 = 16'h0; + parameter SIM_DEVICE = "VIRTEX5"; + parameter SIM_MONITOR_FILE = "design.txt"; + output BUSY; + output DRDY; + output EOC; + output EOS; + output JTAGBUSY; + output JTAGLOCKED; + output JTAGMODIFIED; + output OT; + output [15:0] DO; + output [2:0] ALM; + output [4:0] CHANNEL; + input CONVST; + input CONVSTCLK; + input DCLK; + input DEN; + input DWE; + input RESET; + input VN; + input VP; + input [15:0] DI; + input [15:0] VAUXN; + input [15:0] VAUXP; + input [6:0] DADDR; +endmodule + +(* keep *) +module XADC (...); + parameter [15:0] INIT_40 = 16'h0; + parameter [15:0] INIT_41 = 16'h0; + parameter [15:0] INIT_42 = 16'h0800; + parameter [15:0] INIT_43 = 16'h0; + parameter [15:0] INIT_44 = 16'h0; + parameter [15:0] INIT_45 = 16'h0; + parameter [15:0] INIT_46 = 16'h0; + parameter [15:0] INIT_47 = 16'h0; + parameter [15:0] INIT_48 = 16'h0; + parameter [15:0] INIT_49 = 16'h0; + parameter [15:0] INIT_4A = 16'h0; + parameter [15:0] INIT_4B = 16'h0; + parameter [15:0] INIT_4C = 16'h0; + parameter [15:0] INIT_4D = 16'h0; + parameter [15:0] INIT_4E = 16'h0; + parameter [15:0] INIT_4F = 16'h0; + parameter [15:0] INIT_50 = 16'h0; + parameter [15:0] INIT_51 = 16'h0; + parameter [15:0] INIT_52 = 16'h0; + parameter [15:0] INIT_53 = 16'h0; + parameter [15:0] INIT_54 = 16'h0; + parameter [15:0] INIT_55 = 16'h0; + parameter [15:0] INIT_56 = 16'h0; + parameter [15:0] INIT_57 = 16'h0; + parameter [15:0] INIT_58 = 16'h0; + parameter [15:0] INIT_59 = 16'h0; + parameter [15:0] INIT_5A = 16'h0; + parameter [15:0] INIT_5B = 16'h0; + parameter [15:0] INIT_5C = 16'h0; + parameter [15:0] INIT_5D = 16'h0; + parameter [15:0] INIT_5E = 16'h0; + parameter [15:0] INIT_5F = 16'h0; + parameter IS_CONVSTCLK_INVERTED = 1'b0; + parameter IS_DCLK_INVERTED = 1'b0; + parameter SIM_DEVICE = "7SERIES"; + parameter SIM_MONITOR_FILE = "design.txt"; + output BUSY; + output DRDY; + output EOC; + output EOS; + output JTAGBUSY; + output JTAGLOCKED; + output JTAGMODIFIED; + output OT; + output [15:0] DO; + output [7:0] ALM; + output [4:0] CHANNEL; + output [4:0] MUXADDR; + input CONVST; + (* invertible_pin = "IS_CONVSTCLK_INVERTED" *) + input CONVSTCLK; + (* invertible_pin = "IS_DCLK_INVERTED" *) + input DCLK; + input DEN; + input DWE; + input RESET; + input VN; + input VP; + input [15:0] DI; + input [15:0] VAUXN; + input [15:0] VAUXP; + input [6:0] DADDR; +endmodule + +(* keep *) +module SYSMONE1 (...); + parameter [15:0] INIT_40 = 16'h0; + parameter [15:0] INIT_41 = 16'h0; + parameter [15:0] INIT_42 = 16'h0; + parameter [15:0] INIT_43 = 16'h0; + parameter [15:0] INIT_44 = 16'h0; + parameter [15:0] INIT_45 = 16'h0; + parameter [15:0] INIT_46 = 16'h0; + parameter [15:0] INIT_47 = 16'h0; + parameter [15:0] INIT_48 = 16'h0; + parameter [15:0] INIT_49 = 16'h0; + parameter [15:0] INIT_4A = 16'h0; + parameter [15:0] INIT_4B = 16'h0; + parameter [15:0] INIT_4C = 16'h0; + parameter [15:0] INIT_4D = 16'h0; + parameter [15:0] INIT_4E = 16'h0; + parameter [15:0] INIT_4F = 16'h0; + parameter [15:0] INIT_50 = 16'h0; + parameter [15:0] INIT_51 = 16'h0; + parameter [15:0] INIT_52 = 16'h0; + parameter [15:0] INIT_53 = 16'h0; + parameter [15:0] INIT_54 = 16'h0; + parameter [15:0] INIT_55 = 16'h0; + parameter [15:0] INIT_56 = 16'h0; + parameter [15:0] INIT_57 = 16'h0; + parameter [15:0] INIT_58 = 16'h0; + parameter [15:0] INIT_59 = 16'h0; + parameter [15:0] INIT_5A = 16'h0; + parameter [15:0] INIT_5B = 16'h0; + parameter [15:0] INIT_5C = 16'h0; + parameter [15:0] INIT_5D = 16'h0; + parameter [15:0] INIT_5E = 16'h0; + parameter [15:0] INIT_5F = 16'h0; + parameter [15:0] INIT_60 = 16'h0; + parameter [15:0] INIT_61 = 16'h0; + parameter [15:0] INIT_62 = 16'h0; + parameter [15:0] INIT_63 = 16'h0; + parameter [15:0] INIT_64 = 16'h0; + parameter [15:0] INIT_65 = 16'h0; + parameter [15:0] INIT_66 = 16'h0; + parameter [15:0] INIT_67 = 16'h0; + parameter [15:0] INIT_68 = 16'h0; + parameter [15:0] INIT_69 = 16'h0; + parameter [15:0] INIT_6A = 16'h0; + parameter [15:0] INIT_6B = 16'h0; + parameter [15:0] INIT_6C = 16'h0; + parameter [15:0] INIT_6D = 16'h0; + parameter [15:0] INIT_6E = 16'h0; + parameter [15:0] INIT_6F = 16'h0; + parameter [15:0] INIT_70 = 16'h0; + parameter [15:0] INIT_71 = 16'h0; + parameter [15:0] INIT_72 = 16'h0; + parameter [15:0] INIT_73 = 16'h0; + parameter [15:0] INIT_74 = 16'h0; + parameter [15:0] INIT_75 = 16'h0; + parameter [15:0] INIT_76 = 16'h0; + parameter [15:0] INIT_77 = 16'h0; + parameter [15:0] INIT_78 = 16'h0; + parameter [15:0] INIT_79 = 16'h0; + parameter [15:0] INIT_7A = 16'h0; + parameter [15:0] INIT_7B = 16'h0; + parameter [15:0] INIT_7C = 16'h0; + parameter [15:0] INIT_7D = 16'h0; + parameter [15:0] INIT_7E = 16'h0; + parameter [15:0] INIT_7F = 16'h0; + parameter [0:0] IS_CONVSTCLK_INVERTED = 1'b0; + parameter [0:0] IS_DCLK_INVERTED = 1'b0; + parameter SIM_MONITOR_FILE = "design.txt"; + parameter integer SYSMON_VUSER0_BANK = 0; + parameter SYSMON_VUSER0_MONITOR = "NONE"; + parameter integer SYSMON_VUSER1_BANK = 0; + parameter SYSMON_VUSER1_MONITOR = "NONE"; + parameter integer SYSMON_VUSER2_BANK = 0; + parameter SYSMON_VUSER2_MONITOR = "NONE"; + parameter integer SYSMON_VUSER3_BANK = 0; + parameter SYSMON_VUSER3_MONITOR = "NONE"; + output [15:0] ALM; + output BUSY; + output [5:0] CHANNEL; + output [15:0] DO; + output DRDY; + output EOC; + output EOS; + output I2C_SCLK_TS; + output I2C_SDA_TS; + output JTAGBUSY; + output JTAGLOCKED; + output JTAGMODIFIED; + output [4:0] MUXADDR; + output OT; + input CONVST; + (* invertible_pin = "IS_CONVSTCLK_INVERTED" *) + input CONVSTCLK; + input [7:0] DADDR; + (* invertible_pin = "IS_DCLK_INVERTED" *) + input DCLK; + input DEN; + input [15:0] DI; + input DWE; + input I2C_SCLK; + input I2C_SDA; + input RESET; + input [15:0] VAUXN; + input [15:0] VAUXP; + input VN; + input VP; +endmodule + +(* keep *) +module SYSMONE4 (...); + parameter [15:0] COMMON_N_SOURCE = 16'hFFFF; + parameter [15:0] INIT_40 = 16'h0000; + parameter [15:0] INIT_41 = 16'h0000; + parameter [15:0] INIT_42 = 16'h0000; + parameter [15:0] INIT_43 = 16'h0000; + parameter [15:0] INIT_44 = 16'h0000; + parameter [15:0] INIT_45 = 16'h0000; + parameter [15:0] INIT_46 = 16'h0000; + parameter [15:0] INIT_47 = 16'h0000; + parameter [15:0] INIT_48 = 16'h0000; + parameter [15:0] INIT_49 = 16'h0000; + parameter [15:0] INIT_4A = 16'h0000; + parameter [15:0] INIT_4B = 16'h0000; + parameter [15:0] INIT_4C = 16'h0000; + parameter [15:0] INIT_4D = 16'h0000; + parameter [15:0] INIT_4E = 16'h0000; + parameter [15:0] INIT_4F = 16'h0000; + parameter [15:0] INIT_50 = 16'h0000; + parameter [15:0] INIT_51 = 16'h0000; + parameter [15:0] INIT_52 = 16'h0000; + parameter [15:0] INIT_53 = 16'h0000; + parameter [15:0] INIT_54 = 16'h0000; + parameter [15:0] INIT_55 = 16'h0000; + parameter [15:0] INIT_56 = 16'h0000; + parameter [15:0] INIT_57 = 16'h0000; + parameter [15:0] INIT_58 = 16'h0000; + parameter [15:0] INIT_59 = 16'h0000; + parameter [15:0] INIT_5A = 16'h0000; + parameter [15:0] INIT_5B = 16'h0000; + parameter [15:0] INIT_5C = 16'h0000; + parameter [15:0] INIT_5D = 16'h0000; + parameter [15:0] INIT_5E = 16'h0000; + parameter [15:0] INIT_5F = 16'h0000; + parameter [15:0] INIT_60 = 16'h0000; + parameter [15:0] INIT_61 = 16'h0000; + parameter [15:0] INIT_62 = 16'h0000; + parameter [15:0] INIT_63 = 16'h0000; + parameter [15:0] INIT_64 = 16'h0000; + parameter [15:0] INIT_65 = 16'h0000; + parameter [15:0] INIT_66 = 16'h0000; + parameter [15:0] INIT_67 = 16'h0000; + parameter [15:0] INIT_68 = 16'h0000; + parameter [15:0] INIT_69 = 16'h0000; + parameter [15:0] INIT_6A = 16'h0000; + parameter [15:0] INIT_6B = 16'h0000; + parameter [15:0] INIT_6C = 16'h0000; + parameter [15:0] INIT_6D = 16'h0000; + parameter [15:0] INIT_6E = 16'h0000; + parameter [15:0] INIT_6F = 16'h0000; + parameter [15:0] INIT_70 = 16'h0000; + parameter [15:0] INIT_71 = 16'h0000; + parameter [15:0] INIT_72 = 16'h0000; + parameter [15:0] INIT_73 = 16'h0000; + parameter [15:0] INIT_74 = 16'h0000; + parameter [15:0] INIT_75 = 16'h0000; + parameter [15:0] INIT_76 = 16'h0000; + parameter [15:0] INIT_77 = 16'h0000; + parameter [15:0] INIT_78 = 16'h0000; + parameter [15:0] INIT_79 = 16'h0000; + parameter [15:0] INIT_7A = 16'h0000; + parameter [15:0] INIT_7B = 16'h0000; + parameter [15:0] INIT_7C = 16'h0000; + parameter [15:0] INIT_7D = 16'h0000; + parameter [15:0] INIT_7E = 16'h0000; + parameter [15:0] INIT_7F = 16'h0000; + parameter [0:0] IS_CONVSTCLK_INVERTED = 1'b0; + parameter [0:0] IS_DCLK_INVERTED = 1'b0; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter SIM_MONITOR_FILE = "design.txt"; + parameter integer SYSMON_VUSER0_BANK = 0; + parameter SYSMON_VUSER0_MONITOR = "NONE"; + parameter integer SYSMON_VUSER1_BANK = 0; + parameter SYSMON_VUSER1_MONITOR = "NONE"; + parameter integer SYSMON_VUSER2_BANK = 0; + parameter SYSMON_VUSER2_MONITOR = "NONE"; + parameter integer SYSMON_VUSER3_BANK = 0; + parameter SYSMON_VUSER3_MONITOR = "NONE"; + output [15:0] ADC_DATA; + output [15:0] ALM; + output BUSY; + output [5:0] CHANNEL; + output [15:0] DO; + output DRDY; + output EOC; + output EOS; + output I2C_SCLK_TS; + output I2C_SDA_TS; + output JTAGBUSY; + output JTAGLOCKED; + output JTAGMODIFIED; + output [4:0] MUXADDR; + output OT; + output SMBALERT_TS; + input CONVST; + (* invertible_pin = "IS_CONVSTCLK_INVERTED" *) + input CONVSTCLK; + input [7:0] DADDR; + (* invertible_pin = "IS_DCLK_INVERTED" *) + input DCLK; + input DEN; + input [15:0] DI; + input DWE; + input I2C_SCLK; + input I2C_SDA; + input RESET; + input [15:0] VAUXN; + input [15:0] VAUXP; + input VN; + input VP; +endmodule + +module GTPA1_DUAL (...); + parameter AC_CAP_DIS_0 = "TRUE"; + parameter AC_CAP_DIS_1 = "TRUE"; + parameter integer ALIGN_COMMA_WORD_0 = 1; + parameter integer ALIGN_COMMA_WORD_1 = 1; + parameter integer CB2_INH_CC_PERIOD_0 = 8; + parameter integer CB2_INH_CC_PERIOD_1 = 8; + parameter [4:0] CDR_PH_ADJ_TIME_0 = 5'b01010; + parameter [4:0] CDR_PH_ADJ_TIME_1 = 5'b01010; + parameter integer CHAN_BOND_1_MAX_SKEW_0 = 7; + parameter integer CHAN_BOND_1_MAX_SKEW_1 = 7; + parameter integer CHAN_BOND_2_MAX_SKEW_0 = 1; + parameter integer CHAN_BOND_2_MAX_SKEW_1 = 1; + parameter CHAN_BOND_KEEP_ALIGN_0 = "FALSE"; + parameter CHAN_BOND_KEEP_ALIGN_1 = "FALSE"; + parameter [9:0] CHAN_BOND_SEQ_1_1_0 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_1_1 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_2_0 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_2_1 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_3_0 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_3_1 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_4_0 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_1_4_1 = 10'b0110111100; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_0 = 4'b1111; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_1 = 4'b1111; + parameter [9:0] CHAN_BOND_SEQ_2_1_0 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_2_1_1 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_2_2_0 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_2_1 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_3_0 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_3_1 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_4_0 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_4_1 = 10'b0100111100; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_0 = 4'b1111; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_1 = 4'b1111; + parameter CHAN_BOND_SEQ_2_USE_0 = "FALSE"; + parameter CHAN_BOND_SEQ_2_USE_1 = "FALSE"; + parameter integer CHAN_BOND_SEQ_LEN_0 = 1; + parameter integer CHAN_BOND_SEQ_LEN_1 = 1; + parameter integer CLK25_DIVIDER_0 = 4; + parameter integer CLK25_DIVIDER_1 = 4; + parameter CLKINDC_B_0 = "TRUE"; + parameter CLKINDC_B_1 = "TRUE"; + parameter CLKRCV_TRST_0 = "TRUE"; + parameter CLKRCV_TRST_1 = "TRUE"; + parameter CLK_CORRECT_USE_0 = "TRUE"; + parameter CLK_CORRECT_USE_1 = "TRUE"; + parameter integer CLK_COR_ADJ_LEN_0 = 1; + parameter integer CLK_COR_ADJ_LEN_1 = 1; + parameter integer CLK_COR_DET_LEN_0 = 1; + parameter integer CLK_COR_DET_LEN_1 = 1; + parameter CLK_COR_INSERT_IDLE_FLAG_0 = "FALSE"; + parameter CLK_COR_INSERT_IDLE_FLAG_1 = "FALSE"; + parameter CLK_COR_KEEP_IDLE_0 = "FALSE"; + parameter CLK_COR_KEEP_IDLE_1 = "FALSE"; + parameter integer CLK_COR_MAX_LAT_0 = 20; + parameter integer CLK_COR_MAX_LAT_1 = 20; + parameter integer CLK_COR_MIN_LAT_0 = 18; + parameter integer CLK_COR_MIN_LAT_1 = 18; + parameter CLK_COR_PRECEDENCE_0 = "TRUE"; + parameter CLK_COR_PRECEDENCE_1 = "TRUE"; + parameter integer CLK_COR_REPEAT_WAIT_0 = 0; + parameter integer CLK_COR_REPEAT_WAIT_1 = 0; + parameter [9:0] CLK_COR_SEQ_1_1_0 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2_0 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_2_1 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3_0 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3_1 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4_0 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4_1 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_1_ENABLE_0 = 4'b1111; + parameter [3:0] CLK_COR_SEQ_1_ENABLE_1 = 4'b1111; + parameter [9:0] CLK_COR_SEQ_2_1_0 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_1_1 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_2_0 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_2_1 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_3_0 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_3_1 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_4_0 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_4_1 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_2_ENABLE_0 = 4'b1111; + parameter [3:0] CLK_COR_SEQ_2_ENABLE_1 = 4'b1111; + parameter CLK_COR_SEQ_2_USE_0 = "FALSE"; + parameter CLK_COR_SEQ_2_USE_1 = "FALSE"; + parameter CLK_OUT_GTP_SEL_0 = "REFCLKPLL0"; + parameter CLK_OUT_GTP_SEL_1 = "REFCLKPLL1"; + parameter [1:0] CM_TRIM_0 = 2'b00; + parameter [1:0] CM_TRIM_1 = 2'b00; + parameter [9:0] COMMA_10B_ENABLE_0 = 10'b1111111111; + parameter [9:0] COMMA_10B_ENABLE_1 = 10'b1111111111; + parameter [3:0] COM_BURST_VAL_0 = 4'b1111; + parameter [3:0] COM_BURST_VAL_1 = 4'b1111; + parameter DEC_MCOMMA_DETECT_0 = "TRUE"; + parameter DEC_MCOMMA_DETECT_1 = "TRUE"; + parameter DEC_PCOMMA_DETECT_0 = "TRUE"; + parameter DEC_PCOMMA_DETECT_1 = "TRUE"; + parameter DEC_VALID_COMMA_ONLY_0 = "TRUE"; + parameter DEC_VALID_COMMA_ONLY_1 = "TRUE"; + parameter GTP_CFG_PWRUP_0 = "TRUE"; + parameter GTP_CFG_PWRUP_1 = "TRUE"; + parameter [9:0] MCOMMA_10B_VALUE_0 = 10'b1010000011; + parameter [9:0] MCOMMA_10B_VALUE_1 = 10'b1010000011; + parameter MCOMMA_DETECT_0 = "TRUE"; + parameter MCOMMA_DETECT_1 = "TRUE"; + parameter [2:0] OOBDETECT_THRESHOLD_0 = 3'b110; + parameter [2:0] OOBDETECT_THRESHOLD_1 = 3'b110; + parameter integer OOB_CLK_DIVIDER_0 = 4; + parameter integer OOB_CLK_DIVIDER_1 = 4; + parameter PCI_EXPRESS_MODE_0 = "FALSE"; + parameter PCI_EXPRESS_MODE_1 = "FALSE"; + parameter [9:0] PCOMMA_10B_VALUE_0 = 10'b0101111100; + parameter [9:0] PCOMMA_10B_VALUE_1 = 10'b0101111100; + parameter PCOMMA_DETECT_0 = "TRUE"; + parameter PCOMMA_DETECT_1 = "TRUE"; + parameter [2:0] PLLLKDET_CFG_0 = 3'b101; + parameter [2:0] PLLLKDET_CFG_1 = 3'b101; + parameter [23:0] PLL_COM_CFG_0 = 24'h21680A; + parameter [23:0] PLL_COM_CFG_1 = 24'h21680A; + parameter [7:0] PLL_CP_CFG_0 = 8'h00; + parameter [7:0] PLL_CP_CFG_1 = 8'h00; + parameter integer PLL_DIVSEL_FB_0 = 5; + parameter integer PLL_DIVSEL_FB_1 = 5; + parameter integer PLL_DIVSEL_REF_0 = 2; + parameter integer PLL_DIVSEL_REF_1 = 2; + parameter integer PLL_RXDIVSEL_OUT_0 = 1; + parameter integer PLL_RXDIVSEL_OUT_1 = 1; + parameter PLL_SATA_0 = "FALSE"; + parameter PLL_SATA_1 = "FALSE"; + parameter PLL_SOURCE_0 = "PLL0"; + parameter PLL_SOURCE_1 = "PLL0"; + parameter integer PLL_TXDIVSEL_OUT_0 = 1; + parameter integer PLL_TXDIVSEL_OUT_1 = 1; + parameter [26:0] PMA_CDR_SCAN_0 = 27'h6404040; + parameter [26:0] PMA_CDR_SCAN_1 = 27'h6404040; + parameter [35:0] PMA_COM_CFG_EAST = 36'h000008000; + parameter [35:0] PMA_COM_CFG_WEST = 36'h00000A000; + parameter [6:0] PMA_RXSYNC_CFG_0 = 7'h00; + parameter [6:0] PMA_RXSYNC_CFG_1 = 7'h00; + parameter [24:0] PMA_RX_CFG_0 = 25'h05CE048; + parameter [24:0] PMA_RX_CFG_1 = 25'h05CE048; + parameter [19:0] PMA_TX_CFG_0 = 20'h00082; + parameter [19:0] PMA_TX_CFG_1 = 20'h00082; + parameter RCV_TERM_GND_0 = "FALSE"; + parameter RCV_TERM_GND_1 = "FALSE"; + parameter RCV_TERM_VTTRX_0 = "TRUE"; + parameter RCV_TERM_VTTRX_1 = "TRUE"; + parameter [7:0] RXEQ_CFG_0 = 8'b01111011; + parameter [7:0] RXEQ_CFG_1 = 8'b01111011; + parameter [0:0] RXPRBSERR_LOOPBACK_0 = 1'b0; + parameter [0:0] RXPRBSERR_LOOPBACK_1 = 1'b0; + parameter RX_BUFFER_USE_0 = "TRUE"; + parameter RX_BUFFER_USE_1 = "TRUE"; + parameter RX_DECODE_SEQ_MATCH_0 = "TRUE"; + parameter RX_DECODE_SEQ_MATCH_1 = "TRUE"; + parameter RX_EN_IDLE_HOLD_CDR_0 = "FALSE"; + parameter RX_EN_IDLE_HOLD_CDR_1 = "FALSE"; + parameter RX_EN_IDLE_RESET_BUF_0 = "TRUE"; + parameter RX_EN_IDLE_RESET_BUF_1 = "TRUE"; + parameter RX_EN_IDLE_RESET_FR_0 = "TRUE"; + parameter RX_EN_IDLE_RESET_FR_1 = "TRUE"; + parameter RX_EN_IDLE_RESET_PH_0 = "TRUE"; + parameter RX_EN_IDLE_RESET_PH_1 = "TRUE"; + parameter RX_EN_MODE_RESET_BUF_0 = "TRUE"; + parameter RX_EN_MODE_RESET_BUF_1 = "TRUE"; + parameter [3:0] RX_IDLE_HI_CNT_0 = 4'b1000; + parameter [3:0] RX_IDLE_HI_CNT_1 = 4'b1000; + parameter [3:0] RX_IDLE_LO_CNT_0 = 4'b0000; + parameter [3:0] RX_IDLE_LO_CNT_1 = 4'b0000; + parameter RX_LOSS_OF_SYNC_FSM_0 = "FALSE"; + parameter RX_LOSS_OF_SYNC_FSM_1 = "FALSE"; + parameter integer RX_LOS_INVALID_INCR_0 = 1; + parameter integer RX_LOS_INVALID_INCR_1 = 1; + parameter integer RX_LOS_THRESHOLD_0 = 4; + parameter integer RX_LOS_THRESHOLD_1 = 4; + parameter RX_SLIDE_MODE_0 = "PCS"; + parameter RX_SLIDE_MODE_1 = "PCS"; + parameter RX_STATUS_FMT_0 = "PCIE"; + parameter RX_STATUS_FMT_1 = "PCIE"; + parameter RX_XCLK_SEL_0 = "RXREC"; + parameter RX_XCLK_SEL_1 = "RXREC"; + parameter [2:0] SATA_BURST_VAL_0 = 3'b100; + parameter [2:0] SATA_BURST_VAL_1 = 3'b100; + parameter [2:0] SATA_IDLE_VAL_0 = 3'b011; + parameter [2:0] SATA_IDLE_VAL_1 = 3'b011; + parameter integer SATA_MAX_BURST_0 = 7; + parameter integer SATA_MAX_BURST_1 = 7; + parameter integer SATA_MAX_INIT_0 = 22; + parameter integer SATA_MAX_INIT_1 = 22; + parameter integer SATA_MAX_WAKE_0 = 7; + parameter integer SATA_MAX_WAKE_1 = 7; + parameter integer SATA_MIN_BURST_0 = 4; + parameter integer SATA_MIN_BURST_1 = 4; + parameter integer SATA_MIN_INIT_0 = 12; + parameter integer SATA_MIN_INIT_1 = 12; + parameter integer SATA_MIN_WAKE_0 = 4; + parameter integer SATA_MIN_WAKE_1 = 4; + parameter integer SIM_GTPRESET_SPEEDUP = 0; + parameter SIM_RECEIVER_DETECT_PASS = "FALSE"; + parameter [2:0] SIM_REFCLK0_SOURCE = 3'b000; + parameter [2:0] SIM_REFCLK1_SOURCE = 3'b000; + parameter SIM_TX_ELEC_IDLE_LEVEL = "X"; + parameter SIM_VERSION = "2.0"; + parameter [4:0] TERMINATION_CTRL_0 = 5'b10100; + parameter [4:0] TERMINATION_CTRL_1 = 5'b10100; + parameter TERMINATION_OVRD_0 = "FALSE"; + parameter TERMINATION_OVRD_1 = "FALSE"; + parameter [11:0] TRANS_TIME_FROM_P2_0 = 12'h03C; + parameter [11:0] TRANS_TIME_FROM_P2_1 = 12'h03C; + parameter [7:0] TRANS_TIME_NON_P2_0 = 8'h19; + parameter [7:0] TRANS_TIME_NON_P2_1 = 8'h19; + parameter [9:0] TRANS_TIME_TO_P2_0 = 10'h064; + parameter [9:0] TRANS_TIME_TO_P2_1 = 10'h064; + parameter [31:0] TST_ATTR_0 = 32'h00000000; + parameter [31:0] TST_ATTR_1 = 32'h00000000; + parameter [2:0] TXRX_INVERT_0 = 3'b011; + parameter [2:0] TXRX_INVERT_1 = 3'b011; + parameter TX_BUFFER_USE_0 = "FALSE"; + parameter TX_BUFFER_USE_1 = "FALSE"; + parameter [13:0] TX_DETECT_RX_CFG_0 = 14'h1832; + parameter [13:0] TX_DETECT_RX_CFG_1 = 14'h1832; + parameter [2:0] TX_IDLE_DELAY_0 = 3'b011; + parameter [2:0] TX_IDLE_DELAY_1 = 3'b011; + parameter [1:0] TX_TDCC_CFG_0 = 2'b00; + parameter [1:0] TX_TDCC_CFG_1 = 2'b00; + parameter TX_XCLK_SEL_0 = "TXUSR"; + parameter TX_XCLK_SEL_1 = "TXUSR"; + output DRDY; + output PHYSTATUS0; + output PHYSTATUS1; + output PLLLKDET0; + output PLLLKDET1; + output REFCLKOUT0; + output REFCLKOUT1; + output REFCLKPLL0; + output REFCLKPLL1; + output RESETDONE0; + output RESETDONE1; + output RXBYTEISALIGNED0; + output RXBYTEISALIGNED1; + output RXBYTEREALIGN0; + output RXBYTEREALIGN1; + output RXCHANBONDSEQ0; + output RXCHANBONDSEQ1; + output RXCHANISALIGNED0; + output RXCHANISALIGNED1; + output RXCHANREALIGN0; + output RXCHANREALIGN1; + output RXCOMMADET0; + output RXCOMMADET1; + output RXELECIDLE0; + output RXELECIDLE1; + output RXPRBSERR0; + output RXPRBSERR1; + output RXRECCLK0; + output RXRECCLK1; + output RXVALID0; + output RXVALID1; + output TXN0; + output TXN1; + output TXOUTCLK0; + output TXOUTCLK1; + output TXP0; + output TXP1; + output [15:0] DRPDO; + output [1:0] GTPCLKFBEAST; + output [1:0] GTPCLKFBWEST; + output [1:0] GTPCLKOUT0; + output [1:0] GTPCLKOUT1; + output [1:0] RXLOSSOFSYNC0; + output [1:0] RXLOSSOFSYNC1; + output [1:0] TXBUFSTATUS0; + output [1:0] TXBUFSTATUS1; + output [2:0] RXBUFSTATUS0; + output [2:0] RXBUFSTATUS1; + output [2:0] RXCHBONDO; + output [2:0] RXCLKCORCNT0; + output [2:0] RXCLKCORCNT1; + output [2:0] RXSTATUS0; + output [2:0] RXSTATUS1; + output [31:0] RXDATA0; + output [31:0] RXDATA1; + output [3:0] RXCHARISCOMMA0; + output [3:0] RXCHARISCOMMA1; + output [3:0] RXCHARISK0; + output [3:0] RXCHARISK1; + output [3:0] RXDISPERR0; + output [3:0] RXDISPERR1; + output [3:0] RXNOTINTABLE0; + output [3:0] RXNOTINTABLE1; + output [3:0] RXRUNDISP0; + output [3:0] RXRUNDISP1; + output [3:0] TXKERR0; + output [3:0] TXKERR1; + output [3:0] TXRUNDISP0; + output [3:0] TXRUNDISP1; + output [4:0] RCALOUTEAST; + output [4:0] RCALOUTWEST; + output [4:0] TSTOUT0; + output [4:0] TSTOUT1; + input CLK00; + input CLK01; + input CLK10; + input CLK11; + input CLKINEAST0; + input CLKINEAST1; + input CLKINWEST0; + input CLKINWEST1; + input DCLK; + input DEN; + input DWE; + input GATERXELECIDLE0; + input GATERXELECIDLE1; + input GCLK00; + input GCLK01; + input GCLK10; + input GCLK11; + input GTPRESET0; + input GTPRESET1; + input IGNORESIGDET0; + input IGNORESIGDET1; + input INTDATAWIDTH0; + input INTDATAWIDTH1; + input PLLCLK00; + input PLLCLK01; + input PLLCLK10; + input PLLCLK11; + input PLLLKDETEN0; + input PLLLKDETEN1; + input PLLPOWERDOWN0; + input PLLPOWERDOWN1; + input PRBSCNTRESET0; + input PRBSCNTRESET1; + input REFCLKPWRDNB0; + input REFCLKPWRDNB1; + input RXBUFRESET0; + input RXBUFRESET1; + input RXCDRRESET0; + input RXCDRRESET1; + input RXCHBONDMASTER0; + input RXCHBONDMASTER1; + input RXCHBONDSLAVE0; + input RXCHBONDSLAVE1; + input RXCOMMADETUSE0; + input RXCOMMADETUSE1; + input RXDEC8B10BUSE0; + input RXDEC8B10BUSE1; + input RXENCHANSYNC0; + input RXENCHANSYNC1; + input RXENMCOMMAALIGN0; + input RXENMCOMMAALIGN1; + input RXENPCOMMAALIGN0; + input RXENPCOMMAALIGN1; + input RXENPMAPHASEALIGN0; + input RXENPMAPHASEALIGN1; + input RXN0; + input RXN1; + input RXP0; + input RXP1; + input RXPMASETPHASE0; + input RXPMASETPHASE1; + input RXPOLARITY0; + input RXPOLARITY1; + input RXRESET0; + input RXRESET1; + input RXSLIDE0; + input RXSLIDE1; + input RXUSRCLK0; + input RXUSRCLK1; + input RXUSRCLK20; + input RXUSRCLK21; + input TSTCLK0; + input TSTCLK1; + input TXCOMSTART0; + input TXCOMSTART1; + input TXCOMTYPE0; + input TXCOMTYPE1; + input TXDETECTRX0; + input TXDETECTRX1; + input TXELECIDLE0; + input TXELECIDLE1; + input TXENC8B10BUSE0; + input TXENC8B10BUSE1; + input TXENPMAPHASEALIGN0; + input TXENPMAPHASEALIGN1; + input TXINHIBIT0; + input TXINHIBIT1; + input TXPDOWNASYNCH0; + input TXPDOWNASYNCH1; + input TXPMASETPHASE0; + input TXPMASETPHASE1; + input TXPOLARITY0; + input TXPOLARITY1; + input TXPRBSFORCEERR0; + input TXPRBSFORCEERR1; + input TXRESET0; + input TXRESET1; + input TXUSRCLK0; + input TXUSRCLK1; + input TXUSRCLK20; + input TXUSRCLK21; + input USRCODEERR0; + input USRCODEERR1; + input [11:0] TSTIN0; + input [11:0] TSTIN1; + input [15:0] DI; + input [1:0] GTPCLKFBSEL0EAST; + input [1:0] GTPCLKFBSEL0WEST; + input [1:0] GTPCLKFBSEL1EAST; + input [1:0] GTPCLKFBSEL1WEST; + input [1:0] RXDATAWIDTH0; + input [1:0] RXDATAWIDTH1; + input [1:0] RXEQMIX0; + input [1:0] RXEQMIX1; + input [1:0] RXPOWERDOWN0; + input [1:0] RXPOWERDOWN1; + input [1:0] TXDATAWIDTH0; + input [1:0] TXDATAWIDTH1; + input [1:0] TXPOWERDOWN0; + input [1:0] TXPOWERDOWN1; + input [2:0] LOOPBACK0; + input [2:0] LOOPBACK1; + input [2:0] REFSELDYPLL0; + input [2:0] REFSELDYPLL1; + input [2:0] RXCHBONDI; + input [2:0] RXENPRBSTST0; + input [2:0] RXENPRBSTST1; + input [2:0] TXBUFDIFFCTRL0; + input [2:0] TXBUFDIFFCTRL1; + input [2:0] TXENPRBSTST0; + input [2:0] TXENPRBSTST1; + input [2:0] TXPREEMPHASIS0; + input [2:0] TXPREEMPHASIS1; + input [31:0] TXDATA0; + input [31:0] TXDATA1; + input [3:0] TXBYPASS8B10B0; + input [3:0] TXBYPASS8B10B1; + input [3:0] TXCHARDISPMODE0; + input [3:0] TXCHARDISPMODE1; + input [3:0] TXCHARDISPVAL0; + input [3:0] TXCHARDISPVAL1; + input [3:0] TXCHARISK0; + input [3:0] TXCHARISK1; + input [3:0] TXDIFFCTRL0; + input [3:0] TXDIFFCTRL1; + input [4:0] RCALINEAST; + input [4:0] RCALINWEST; + input [7:0] DADDR; + input [7:0] GTPTEST0; + input [7:0] GTPTEST1; +endmodule + +module GT11_CUSTOM (...); + parameter ALIGN_COMMA_WORD = 1; + parameter BANDGAPSEL = "FALSE"; + parameter BIASRESSEL = "TRUE"; + parameter CCCB_ARBITRATOR_DISABLE = "FALSE"; + parameter CHAN_BOND_LIMIT = 16; + parameter CHAN_BOND_MODE = "NONE"; + parameter CHAN_BOND_ONE_SHOT = "FALSE"; + parameter CHAN_BOND_SEQ_1_1 = 11'b00000000000; + parameter CHAN_BOND_SEQ_1_2 = 11'b00000000000; + parameter CHAN_BOND_SEQ_1_3 = 11'b00000000000; + parameter CHAN_BOND_SEQ_1_4 = 11'b00000000000; + parameter CHAN_BOND_SEQ_1_MASK = 4'b0000; + parameter CHAN_BOND_SEQ_2_1 = 11'b00000000000; + parameter CHAN_BOND_SEQ_2_2 = 11'b00000000000; + parameter CHAN_BOND_SEQ_2_3 = 11'b00000000000; + parameter CHAN_BOND_SEQ_2_4 = 11'b00000000000; + parameter CHAN_BOND_SEQ_2_MASK = 4'b0000; + parameter CHAN_BOND_SEQ_2_USE = "FALSE"; + parameter CHAN_BOND_SEQ_LEN = 1; + parameter CLK_CORRECT_USE = "TRUE"; + parameter CLK_COR_8B10B_DE = "FALSE"; + parameter CLK_COR_MAX_LAT = 36; + parameter CLK_COR_MIN_LAT = 28; + parameter CLK_COR_SEQ_1_1 = 11'b00000000000; + parameter CLK_COR_SEQ_1_2 = 11'b00000000000; + parameter CLK_COR_SEQ_1_3 = 11'b00000000000; + parameter CLK_COR_SEQ_1_4 = 11'b00000000000; + parameter CLK_COR_SEQ_1_MASK = 4'b0000; + parameter CLK_COR_SEQ_2_1 = 11'b00000000000; + parameter CLK_COR_SEQ_2_2 = 11'b00000000000; + parameter CLK_COR_SEQ_2_3 = 11'b00000000000; + parameter CLK_COR_SEQ_2_4 = 11'b00000000000; + parameter CLK_COR_SEQ_2_MASK = 4'b0000; + parameter CLK_COR_SEQ_2_USE = "FALSE"; + parameter CLK_COR_SEQ_DROP = "FALSE"; + parameter CLK_COR_SEQ_LEN = 1; + parameter COMMA32 = "FALSE"; + parameter COMMA_10B_MASK = 10'h3FF; + parameter CYCLE_LIMIT_SEL = 2'b00; + parameter DCDR_FILTER = 3'b010; + parameter DEC_MCOMMA_DETECT = "TRUE"; + parameter DEC_PCOMMA_DETECT = "TRUE"; + parameter DEC_VALID_COMMA_ONLY = "TRUE"; + parameter DIGRX_FWDCLK = 2'b00; + parameter DIGRX_SYNC_MODE = "FALSE"; + parameter ENABLE_DCDR = "FALSE"; + parameter FDET_HYS_CAL = 3'b110; + parameter FDET_HYS_SEL = 3'b110; + parameter FDET_LCK_CAL = 3'b101; + parameter FDET_LCK_SEL = 3'b101; + parameter GT11_MODE = "SINGLE"; + parameter IREFBIASMODE = 2'b11; + parameter LOOPCAL_WAIT = 2'b00; + parameter MCOMMA_32B_VALUE = 32'h000000F6; + parameter MCOMMA_DETECT = "TRUE"; + parameter OPPOSITE_SELECT = "FALSE"; + parameter PCOMMA_32B_VALUE = 32'hF6F62828; + parameter PCOMMA_DETECT = "TRUE"; + parameter PCS_BIT_SLIP = "FALSE"; + parameter PMACLKENABLE = "TRUE"; + parameter PMACOREPWRENABLE = "TRUE"; + parameter PMAIREFTRIM = 4'b0111; + parameter PMAVBGCTRL = 5'b00000; + parameter PMAVREFTRIM = 4'b0111; + parameter PMA_BIT_SLIP = "FALSE"; + parameter REPEATER = "FALSE"; + parameter RXACTST = "FALSE"; + parameter RXAFEEQ = 9'b000000000; + parameter RXAFEPD = "FALSE"; + parameter RXAFETST = "FALSE"; + parameter RXAPD = "FALSE"; + parameter RXASYNCDIVIDE = 2'b11; + parameter RXBY_32 = "TRUE"; + parameter RXCDRLOS = 6'b000000; + parameter RXCLK0_FORCE_PMACLK = "FALSE"; + parameter RXCLKMODE = 6'b110001; + parameter RXCMADJ = 2'b10; + parameter RXCPSEL = "TRUE"; + parameter RXCPTST = "FALSE"; + parameter RXCRCCLOCKDOUBLE = "FALSE"; + parameter RXCRCENABLE = "FALSE"; + parameter RXCRCINITVAL = 32'h00000000; + parameter RXCRCINVERTGEN = "FALSE"; + parameter RXCRCSAMECLOCK = "FALSE"; + parameter RXCTRL1 = 10'h200; + parameter RXCYCLE_LIMIT_SEL = 2'b00; + parameter RXDATA_SEL = 2'b00; + parameter RXDCCOUPLE = "FALSE"; + parameter RXDIGRESET = "FALSE"; + parameter RXDIGRX = "FALSE"; + parameter RXEQ = 64'h4000000000000000; + parameter RXFDCAL_CLOCK_DIVIDE = "NONE"; + parameter RXFDET_HYS_CAL = 3'b110; + parameter RXFDET_HYS_SEL = 3'b110; + parameter RXFDET_LCK_CAL = 3'b101; + parameter RXFDET_LCK_SEL = 3'b101; + parameter RXFECONTROL1 = 2'b00; + parameter RXFECONTROL2 = 3'b000; + parameter RXFETUNE = 2'b01; + parameter RXLB = "FALSE"; + parameter RXLKADJ = 5'b00000; + parameter RXLKAPD = "FALSE"; + parameter RXLOOPCAL_WAIT = 2'b00; + parameter RXLOOPFILT = 4'b0111; + parameter RXOUTDIV2SEL = 1; + parameter RXPD = "FALSE"; + parameter RXPDDTST = "FALSE"; + parameter RXPLLNDIVSEL = 8; + parameter RXPMACLKSEL = "REFCLK1"; + parameter RXRCPADJ = 3'b011; + parameter RXRCPPD = "FALSE"; + parameter RXRECCLK1_USE_SYNC = "FALSE"; + parameter RXRIBADJ = 2'b11; + parameter RXRPDPD = "FALSE"; + parameter RXRSDPD = "FALSE"; + parameter RXSLOWDOWN_CAL = 2'b00; + parameter RXUSRDIVISOR = 1; + parameter RXVCODAC_INIT = 10'b1010000000; + parameter RXVCO_CTRL_ENABLE = "TRUE"; + parameter RX_BUFFER_USE = "TRUE"; + parameter RX_CLOCK_DIVIDER = 2'b00; + parameter RX_LOS_INVALID_INCR = 1; + parameter RX_LOS_THRESHOLD = 4; + parameter SAMPLE_8X = "FALSE"; + parameter SH_CNT_MAX = 64; + parameter SH_INVALID_CNT_MAX = 16; + parameter SLOWDOWN_CAL = 2'b00; + parameter TXABPMACLKSEL = "REFCLK1"; + parameter TXAPD = "FALSE"; + parameter TXAREFBIASSEL = "FALSE"; + parameter TXASYNCDIVIDE = 2'b11; + parameter TXCLK0_FORCE_PMACLK = "FALSE"; + parameter TXCLKMODE = 4'b1001; + parameter TXCPSEL = "TRUE"; + parameter TXCRCCLOCKDOUBLE = "FALSE"; + parameter TXCRCENABLE = "FALSE"; + parameter TXCRCINITVAL = 32'h00000000; + parameter TXCRCINVERTGEN = "FALSE"; + parameter TXCRCSAMECLOCK = "FALSE"; + parameter TXCTRL1 = 10'h200; + parameter TXDATA_SEL = 2'b00; + parameter TXDAT_PRDRV_DAC = 3'b111; + parameter TXDAT_TAP_DAC = 5'b10110; + parameter TXDIGPD = "FALSE"; + parameter TXFDCAL_CLOCK_DIVIDE = "NONE"; + parameter TXHIGHSIGNALEN = "TRUE"; + parameter TXLOOPFILT = 4'b0111; + parameter TXLVLSHFTPD = "FALSE"; + parameter TXOUTCLK1_USE_SYNC = "FALSE"; + parameter TXOUTDIV2SEL = 1; + parameter TXPD = "FALSE"; + parameter TXPHASESEL = "FALSE"; + parameter TXPLLNDIVSEL = 8; + parameter TXPOST_PRDRV_DAC = 3'b111; + parameter TXPOST_TAP_DAC = 5'b01110; + parameter TXPOST_TAP_PD = "TRUE"; + parameter TXPRE_PRDRV_DAC = 3'b111; + parameter TXPRE_TAP_DAC = 5'b00000; + parameter TXPRE_TAP_PD = "TRUE"; + parameter TXSLEWRATE = "FALSE"; + parameter TXTERMTRIM = 4'b1100; + parameter TX_BUFFER_USE = "TRUE"; + parameter TX_CLOCK_DIVIDER = 2'b00; + parameter VCODAC_INIT = 10'b1010000000; + parameter VCO_CTRL_ENABLE = "TRUE"; + parameter VREFBIASMODE = 2'b11; + output DRDY; + output RXBUFERR; + output RXCALFAIL; + output RXCOMMADET; + output RXCYCLELIMIT; + output RXLOCK; + output RXMCLK; + output RXPCSHCLKOUT; + output RXREALIGN; + output RXRECCLK1; + output RXRECCLK2; + output RXSIGDET; + output TX1N; + output TX1P; + output TXBUFERR; + output TXCALFAIL; + output TXCYCLELIMIT; + output TXLOCK; + output TXOUTCLK1; + output TXOUTCLK2; + output TXPCSHCLKOUT; + output [15:0] DO; + output [1:0] RXLOSSOFSYNC; + output [31:0] RXCRCOUT; + output [31:0] TXCRCOUT; + output [4:0] CHBONDO; + output [5:0] RXSTATUS; + output [63:0] RXDATA; + output [7:0] RXCHARISCOMMA; + output [7:0] RXCHARISK; + output [7:0] RXDISPERR; + output [7:0] RXNOTINTABLE; + output [7:0] RXRUNDISP; + output [7:0] TXKERR; + output [7:0] TXRUNDISP; + input DCLK; + input DEN; + input DWE; + input ENCHANSYNC; + input ENMCOMMAALIGN; + input ENPCOMMAALIGN; + input GREFCLK; + input POWERDOWN; + input REFCLK1; + input REFCLK2; + input RX1N; + input RX1P; + input RXBLOCKSYNC64B66BUSE; + input RXCLKSTABLE; + input RXCOMMADETUSE; + input RXCRCCLK; + input RXCRCDATAVALID; + input RXCRCINIT; + input RXCRCINTCLK; + input RXCRCPD; + input RXCRCRESET; + input RXDEC64B66BUSE; + input RXDEC8B10BUSE; + input RXDESCRAM64B66BUSE; + input RXIGNOREBTF; + input RXPMARESET; + input RXPOLARITY; + input RXRESET; + input RXSLIDE; + input RXSYNC; + input RXUSRCLK2; + input RXUSRCLK; + input TXCLKSTABLE; + input TXCRCCLK; + input TXCRCDATAVALID; + input TXCRCINIT; + input TXCRCINTCLK; + input TXCRCPD; + input TXCRCRESET; + input TXENC64B66BUSE; + input TXENC8B10BUSE; + input TXENOOB; + input TXGEARBOX64B66BUSE; + input TXINHIBIT; + input TXPMARESET; + input TXPOLARITY; + input TXRESET; + input TXSCRAM64B66BUSE; + input TXSYNC; + input TXUSRCLK2; + input TXUSRCLK; + input [15:0] DI; + input [1:0] LOOPBACK; + input [1:0] RXDATAWIDTH; + input [1:0] RXINTDATAWIDTH; + input [1:0] TXDATAWIDTH; + input [1:0] TXINTDATAWIDTH; + input [2:0] RXCRCDATAWIDTH; + input [2:0] TXCRCDATAWIDTH; + input [4:0] CHBONDI; + input [63:0] RXCRCIN; + input [63:0] TXCRCIN; + input [63:0] TXDATA; + input [7:0] DADDR; + input [7:0] TXBYPASS8B10B; + input [7:0] TXCHARDISPMODE; + input [7:0] TXCHARDISPVAL; + input [7:0] TXCHARISK; +endmodule + +module GT11_DUAL (...); + parameter ALIGN_COMMA_WORD_A = 1; + parameter ALIGN_COMMA_WORD_B = 1; + parameter BANDGAPSEL_A = "FALSE"; + parameter BANDGAPSEL_B = "FALSE"; + parameter BIASRESSEL_A = "TRUE"; + parameter BIASRESSEL_B = "TRUE"; + parameter CCCB_ARBITRATOR_DISABLE_A = "FALSE"; + parameter CCCB_ARBITRATOR_DISABLE_B = "FALSE"; + parameter CHAN_BOND_LIMIT_A = 16; + parameter CHAN_BOND_LIMIT_B = 16; + parameter CHAN_BOND_MODE_A = "NONE"; + parameter CHAN_BOND_MODE_B = "NONE"; + parameter CHAN_BOND_ONE_SHOT_A = "FALSE"; + parameter CHAN_BOND_ONE_SHOT_B = "FALSE"; + parameter CHAN_BOND_SEQ_1_1_A = 11'b00000000000; + parameter CHAN_BOND_SEQ_1_1_B = 11'b00000000000; + parameter CHAN_BOND_SEQ_1_2_A = 11'b00000000000; + parameter CHAN_BOND_SEQ_1_2_B = 11'b00000000000; + parameter CHAN_BOND_SEQ_1_3_A = 11'b00000000000; + parameter CHAN_BOND_SEQ_1_3_B = 11'b00000000000; + parameter CHAN_BOND_SEQ_1_4_A = 11'b00000000000; + parameter CHAN_BOND_SEQ_1_4_B = 11'b00000000000; + parameter CHAN_BOND_SEQ_1_MASK_A = 4'b0000; + parameter CHAN_BOND_SEQ_1_MASK_B = 4'b0000; + parameter CHAN_BOND_SEQ_2_1_A = 11'b00000000000; + parameter CHAN_BOND_SEQ_2_1_B = 11'b00000000000; + parameter CHAN_BOND_SEQ_2_2_A = 11'b00000000000; + parameter CHAN_BOND_SEQ_2_2_B = 11'b00000000000; + parameter CHAN_BOND_SEQ_2_3_A = 11'b00000000000; + parameter CHAN_BOND_SEQ_2_3_B = 11'b00000000000; + parameter CHAN_BOND_SEQ_2_4_A = 11'b00000000000; + parameter CHAN_BOND_SEQ_2_4_B = 11'b00000000000; + parameter CHAN_BOND_SEQ_2_MASK_A = 4'b0000; + parameter CHAN_BOND_SEQ_2_MASK_B = 4'b0000; + parameter CHAN_BOND_SEQ_2_USE_A = "FALSE"; + parameter CHAN_BOND_SEQ_2_USE_B = "FALSE"; + parameter CHAN_BOND_SEQ_LEN_A = 1; + parameter CHAN_BOND_SEQ_LEN_B = 1; + parameter CLK_CORRECT_USE_A = "TRUE"; + parameter CLK_CORRECT_USE_B = "TRUE"; + parameter CLK_COR_8B10B_DE_A = "FALSE"; + parameter CLK_COR_8B10B_DE_B = "FALSE"; + parameter CLK_COR_MAX_LAT_A = 36; + parameter CLK_COR_MAX_LAT_B = 36; + parameter CLK_COR_MIN_LAT_A = 28; + parameter CLK_COR_MIN_LAT_B = 28; + parameter CLK_COR_SEQ_1_1_A = 11'b00000000000; + parameter CLK_COR_SEQ_1_1_B = 11'b00000000000; + parameter CLK_COR_SEQ_1_2_A = 11'b00000000000; + parameter CLK_COR_SEQ_1_2_B = 11'b00000000000; + parameter CLK_COR_SEQ_1_3_A = 11'b00000000000; + parameter CLK_COR_SEQ_1_3_B = 11'b00000000000; + parameter CLK_COR_SEQ_1_4_A = 11'b00000000000; + parameter CLK_COR_SEQ_1_4_B = 11'b00000000000; + parameter CLK_COR_SEQ_1_MASK_A = 4'b0000; + parameter CLK_COR_SEQ_1_MASK_B = 4'b0000; + parameter CLK_COR_SEQ_2_1_A = 11'b00000000000; + parameter CLK_COR_SEQ_2_1_B = 11'b00000000000; + parameter CLK_COR_SEQ_2_2_A = 11'b00000000000; + parameter CLK_COR_SEQ_2_2_B = 11'b00000000000; + parameter CLK_COR_SEQ_2_3_A = 11'b00000000000; + parameter CLK_COR_SEQ_2_3_B = 11'b00000000000; + parameter CLK_COR_SEQ_2_4_A = 11'b00000000000; + parameter CLK_COR_SEQ_2_4_B = 11'b00000000000; + parameter CLK_COR_SEQ_2_MASK_A = 4'b0000; + parameter CLK_COR_SEQ_2_MASK_B = 4'b0000; + parameter CLK_COR_SEQ_2_USE_A = "FALSE"; + parameter CLK_COR_SEQ_2_USE_B = "FALSE"; + parameter CLK_COR_SEQ_DROP_A = "FALSE"; + parameter CLK_COR_SEQ_DROP_B = "FALSE"; + parameter CLK_COR_SEQ_LEN_A = 1; + parameter CLK_COR_SEQ_LEN_B = 1; + parameter COMMA32_A = "FALSE"; + parameter COMMA32_B = "FALSE"; + parameter COMMA_10B_MASK_A = 10'h3FF; + parameter COMMA_10B_MASK_B = 10'h3FF; + parameter CYCLE_LIMIT_SEL_A = 2'b00; + parameter CYCLE_LIMIT_SEL_B = 2'b00; + parameter DCDR_FILTER_A = 3'b010; + parameter DCDR_FILTER_B = 3'b010; + parameter DEC_MCOMMA_DETECT_A = "TRUE"; + parameter DEC_MCOMMA_DETECT_B = "TRUE"; + parameter DEC_PCOMMA_DETECT_A = "TRUE"; + parameter DEC_PCOMMA_DETECT_B = "TRUE"; + parameter DEC_VALID_COMMA_ONLY_A = "TRUE"; + parameter DEC_VALID_COMMA_ONLY_B = "TRUE"; + parameter DIGRX_FWDCLK_A = 2'b00; + parameter DIGRX_FWDCLK_B = 2'b00; + parameter DIGRX_SYNC_MODE_A = "FALSE"; + parameter DIGRX_SYNC_MODE_B = "FALSE"; + parameter ENABLE_DCDR_A = "FALSE"; + parameter ENABLE_DCDR_B = "FALSE"; + parameter FDET_HYS_CAL_A = 3'b110; + parameter FDET_HYS_CAL_B = 3'b110; + parameter FDET_HYS_SEL_A = 3'b110; + parameter FDET_HYS_SEL_B = 3'b110; + parameter FDET_LCK_CAL_A = 3'b101; + parameter FDET_LCK_CAL_B = 3'b101; + parameter FDET_LCK_SEL_A = 3'b101; + parameter FDET_LCK_SEL_B = 3'b101; + parameter IREFBIASMODE_A = 2'b11; + parameter IREFBIASMODE_B = 2'b11; + parameter LOOPCAL_WAIT_A = 2'b00; + parameter LOOPCAL_WAIT_B = 2'b00; + parameter MCOMMA_32B_VALUE_A = 32'hA1A1A2A2; + parameter MCOMMA_32B_VALUE_B = 32'hA1A1A2A2; + parameter MCOMMA_DETECT_A = "TRUE"; + parameter MCOMMA_DETECT_B = "TRUE"; + parameter OPPOSITE_SELECT_A = "FALSE"; + parameter OPPOSITE_SELECT_B = "FALSE"; + parameter PCOMMA_32B_VALUE_A = 32'hA1A1A2A2; + parameter PCOMMA_32B_VALUE_B = 32'hA1A1A2A2; + parameter PCOMMA_DETECT_A = "TRUE"; + parameter PCOMMA_DETECT_B = "TRUE"; + parameter PCS_BIT_SLIP_A = "FALSE"; + parameter PCS_BIT_SLIP_B = "FALSE"; + parameter PMACLKENABLE_A = "TRUE"; + parameter PMACLKENABLE_B = "TRUE"; + parameter PMACOREPWRENABLE_A = "TRUE"; + parameter PMACOREPWRENABLE_B = "TRUE"; + parameter PMAIREFTRIM_A = 4'b0111; + parameter PMAIREFTRIM_B = 4'b0111; + parameter PMAVBGCTRL_A = 5'b00000; + parameter PMAVBGCTRL_B = 5'b00000; + parameter PMAVREFTRIM_A = 4'b0111; + parameter PMAVREFTRIM_B = 4'b0111; + parameter PMA_BIT_SLIP_A = "FALSE"; + parameter PMA_BIT_SLIP_B = "FALSE"; + parameter POWER_ENABLE_A = "TRUE"; + parameter POWER_ENABLE_B = "TRUE"; + parameter REPEATER_A = "FALSE"; + parameter REPEATER_B = "FALSE"; + parameter RXACTST_A = "FALSE"; + parameter RXACTST_B = "FALSE"; + parameter RXAFEEQ_A = 9'b000000000; + parameter RXAFEEQ_B = 9'b000000000; + parameter RXAFEPD_A = "FALSE"; + parameter RXAFEPD_B = "FALSE"; + parameter RXAFETST_A = "FALSE"; + parameter RXAFETST_B = "FALSE"; + parameter RXAPD_A = "FALSE"; + parameter RXAPD_B = "FALSE"; + parameter RXASYNCDIVIDE_A = 2'b00; + parameter RXASYNCDIVIDE_B = 2'b00; + parameter RXBY_32_A = "TRUE"; + parameter RXBY_32_B = "TRUE"; + parameter RXCDRLOS_A = 6'b000000; + parameter RXCDRLOS_B = 6'b000000; + parameter RXCLK0_FORCE_PMACLK_A = "FALSE"; + parameter RXCLK0_FORCE_PMACLK_B = "FALSE"; + parameter RXCLKMODE_A = 6'b110001; + parameter RXCLKMODE_B = 6'b110001; + parameter RXCMADJ_A = 2'b10; + parameter RXCMADJ_B = 2'b10; + parameter RXCPSEL_A = "TRUE"; + parameter RXCPSEL_B = "TRUE"; + parameter RXCPTST_A = "FALSE"; + parameter RXCPTST_B = "FALSE"; + parameter RXCRCCLOCKDOUBLE_A = "FALSE"; + parameter RXCRCCLOCKDOUBLE_B = "FALSE"; + parameter RXCRCENABLE_A = "FALSE"; + parameter RXCRCENABLE_B = "FALSE"; + parameter RXCRCINITVAL_A = 32'h00000000; + parameter RXCRCINITVAL_B = 32'h00000000; + parameter RXCRCINVERTGEN_A = "FALSE"; + parameter RXCRCINVERTGEN_B = "FALSE"; + parameter RXCRCSAMECLOCK_A = "FALSE"; + parameter RXCRCSAMECLOCK_B = "FALSE"; + parameter RXCTRL1_A = 10'h006; + parameter RXCTRL1_B = 10'h006; + parameter RXCYCLE_LIMIT_SEL_A = 2'b00; + parameter RXCYCLE_LIMIT_SEL_B = 2'b00; + parameter RXDATA_SEL_A = 2'b00; + parameter RXDATA_SEL_B = 2'b00; + parameter RXDCCOUPLE_A = "FALSE"; + parameter RXDCCOUPLE_B = "FALSE"; + parameter RXDIGRESET_A = "FALSE"; + parameter RXDIGRESET_B = "FALSE"; + parameter RXDIGRX_A = "FALSE"; + parameter RXDIGRX_B = "FALSE"; + parameter RXEQ_A = 64'h4000000000000000; + parameter RXEQ_B = 64'h4000000000000000; + parameter RXFDCAL_CLOCK_DIVIDE_A = "NONE"; + parameter RXFDCAL_CLOCK_DIVIDE_B = "NONE"; + parameter RXFDET_HYS_CAL_A = 3'b110; + parameter RXFDET_HYS_CAL_B = 3'b110; + parameter RXFDET_HYS_SEL_A = 3'b110; + parameter RXFDET_HYS_SEL_B = 3'b110; + parameter RXFDET_LCK_CAL_A = 3'b101; + parameter RXFDET_LCK_CAL_B = 3'b101; + parameter RXFDET_LCK_SEL_A = 3'b101; + parameter RXFDET_LCK_SEL_B = 3'b101; + parameter RXFECONTROL1_A = 2'b00; + parameter RXFECONTROL1_B = 2'b00; + parameter RXFECONTROL2_A = 3'b000; + parameter RXFECONTROL2_B = 3'b000; + parameter RXFETUNE_A = 2'b01; + parameter RXFETUNE_B = 2'b01; + parameter RXLB_A = "FALSE"; + parameter RXLB_B = "FALSE"; + parameter RXLKADJ_A = 5'b00000; + parameter RXLKADJ_B = 5'b00000; + parameter RXLKAPD_A = "FALSE"; + parameter RXLKAPD_B = "FALSE"; + parameter RXLOOPCAL_WAIT_A = 2'b00; + parameter RXLOOPCAL_WAIT_B = 2'b00; + parameter RXLOOPFILT_A = 4'b0111; + parameter RXLOOPFILT_B = 4'b0111; + parameter RXOUTDIV2SEL_A = 1; + parameter RXOUTDIV2SEL_B = 1; + parameter RXPDDTST_A = "FALSE"; + parameter RXPDDTST_B = "FALSE"; + parameter RXPD_A = "FALSE"; + parameter RXPD_B = "FALSE"; + parameter RXPLLNDIVSEL_A = 8; + parameter RXPLLNDIVSEL_B = 8; + parameter RXPMACLKSEL_A = "REFCLK1"; + parameter RXPMACLKSEL_B = "REFCLK1"; + parameter RXRCPADJ_A = 3'b011; + parameter RXRCPADJ_B = 3'b011; + parameter RXRCPPD_A = "FALSE"; + parameter RXRCPPD_B = "FALSE"; + parameter RXRECCLK1_USE_SYNC_A = "FALSE"; + parameter RXRECCLK1_USE_SYNC_B = "FALSE"; + parameter RXRIBADJ_A = 2'b11; + parameter RXRIBADJ_B = 2'b11; + parameter RXRPDPD_A = "FALSE"; + parameter RXRPDPD_B = "FALSE"; + parameter RXRSDPD_A = "FALSE"; + parameter RXRSDPD_B = "FALSE"; + parameter RXSLOWDOWN_CAL_A = 2'b00; + parameter RXSLOWDOWN_CAL_B = 2'b00; + parameter RXUSRDIVISOR_A = 1; + parameter RXUSRDIVISOR_B = 1; + parameter RXVCODAC_INIT_A = 10'b1010000000; + parameter RXVCODAC_INIT_B = 10'b1010000000; + parameter RXVCO_CTRL_ENABLE_A = "TRUE"; + parameter RXVCO_CTRL_ENABLE_B = "TRUE"; + parameter RX_BUFFER_USE_A = "TRUE"; + parameter RX_BUFFER_USE_B = "TRUE"; + parameter RX_CLOCK_DIVIDER_A = 2'b00; + parameter RX_CLOCK_DIVIDER_B = 2'b00; + parameter RX_LOS_INVALID_INCR_A = 1; + parameter RX_LOS_INVALID_INCR_B = 1; + parameter RX_LOS_THRESHOLD_A = 4; + parameter RX_LOS_THRESHOLD_B = 4; + parameter SAMPLE_8X_A = "FALSE"; + parameter SAMPLE_8X_B = "FALSE"; + parameter SH_CNT_MAX_A = 64; + parameter SH_CNT_MAX_B = 64; + parameter SH_INVALID_CNT_MAX_A = 16; + parameter SH_INVALID_CNT_MAX_B = 16; + parameter SLOWDOWN_CAL_A = 2'b00; + parameter SLOWDOWN_CAL_B = 2'b00; + parameter TXABPMACLKSEL_A = "REFCLK1"; + parameter TXABPMACLKSEL_B = "REFCLK1"; + parameter TXAPD_A = "FALSE"; + parameter TXAPD_B = "FALSE"; + parameter TXAREFBIASSEL_A = "FALSE"; + parameter TXAREFBIASSEL_B = "FALSE"; + parameter TXASYNCDIVIDE_A = 2'b00; + parameter TXASYNCDIVIDE_B = 2'b00; + parameter TXCLK0_FORCE_PMACLK_A = "FALSE"; + parameter TXCLK0_FORCE_PMACLK_B = "FALSE"; + parameter TXCLKMODE_A = 4'b1001; + parameter TXCLKMODE_B = 4'b1001; + parameter TXCPSEL_A = "TRUE"; + parameter TXCPSEL_B = "TRUE"; + parameter TXCRCCLOCKDOUBLE_A = "FALSE"; + parameter TXCRCCLOCKDOUBLE_B = "FALSE"; + parameter TXCRCENABLE_A = "FALSE"; + parameter TXCRCENABLE_B = "FALSE"; + parameter TXCRCINITVAL_A = 32'h00000000; + parameter TXCRCINITVAL_B = 32'h00000000; + parameter TXCRCINVERTGEN_A = "FALSE"; + parameter TXCRCINVERTGEN_B = "FALSE"; + parameter TXCRCSAMECLOCK_A = "FALSE"; + parameter TXCRCSAMECLOCK_B = "FALSE"; + parameter TXCTRL1_A = 10'h006; + parameter TXCTRL1_B = 10'h006; + parameter TXDATA_SEL_A = 2'b00; + parameter TXDATA_SEL_B = 2'b00; + parameter TXDAT_PRDRV_DAC_A = 3'b111; + parameter TXDAT_PRDRV_DAC_B = 3'b111; + parameter TXDAT_TAP_DAC_A = 5'b10110; + parameter TXDAT_TAP_DAC_B = 5'b10110; + parameter TXDIGPD_A = "FALSE"; + parameter TXDIGPD_B = "FALSE"; + parameter TXFDCAL_CLOCK_DIVIDE_A = "NONE"; + parameter TXFDCAL_CLOCK_DIVIDE_B = "NONE"; + parameter TXHIGHSIGNALEN_A = "TRUE"; + parameter TXHIGHSIGNALEN_B = "TRUE"; + parameter TXLOOPFILT_A = 4'b0111; + parameter TXLOOPFILT_B = 4'b0111; + parameter TXLVLSHFTPD_A = "FALSE"; + parameter TXLVLSHFTPD_B = "FALSE"; + parameter TXOUTCLK1_USE_SYNC_A = "FALSE"; + parameter TXOUTCLK1_USE_SYNC_B = "FALSE"; + parameter TXOUTDIV2SEL_A = 1; + parameter TXOUTDIV2SEL_B = 1; + parameter TXPD_A = "FALSE"; + parameter TXPD_B = "FALSE"; + parameter TXPHASESEL_A = "FALSE"; + parameter TXPHASESEL_B = "FALSE"; + parameter TXPLLNDIVSEL_A = 8; + parameter TXPLLNDIVSEL_B = 8; + parameter TXPOST_PRDRV_DAC_A = 3'b111; + parameter TXPOST_PRDRV_DAC_B = 3'b111; + parameter TXPOST_TAP_DAC_A = 5'b01110; + parameter TXPOST_TAP_DAC_B = 5'b01110; + parameter TXPOST_TAP_PD_A = "TRUE"; + parameter TXPOST_TAP_PD_B = "TRUE"; + parameter TXPRE_PRDRV_DAC_A = 3'b111; + parameter TXPRE_PRDRV_DAC_B = 3'b111; + parameter TXPRE_TAP_DAC_A = 5'b00000; + parameter TXPRE_TAP_DAC_B = 5'b00000; + parameter TXPRE_TAP_PD_A = "TRUE"; + parameter TXPRE_TAP_PD_B = "TRUE"; + parameter TXSLEWRATE_A = "FALSE"; + parameter TXSLEWRATE_B = "FALSE"; + parameter TXTERMTRIM_A = 4'b1100; + parameter TXTERMTRIM_B = 4'b1100; + parameter TX_BUFFER_USE_A = "TRUE"; + parameter TX_BUFFER_USE_B = "TRUE"; + parameter TX_CLOCK_DIVIDER_A = 2'b00; + parameter TX_CLOCK_DIVIDER_B = 2'b00; + parameter VCODAC_INIT_A = 10'b1010000000; + parameter VCODAC_INIT_B = 10'b1010000000; + parameter VCO_CTRL_ENABLE_A = "TRUE"; + parameter VCO_CTRL_ENABLE_B = "TRUE"; + parameter VREFBIASMODE_A = 2'b11; + parameter VREFBIASMODE_B = 2'b11; + output DRDYA; + output DRDYB; + output RXBUFERRA; + output RXBUFERRB; + output RXCALFAILA; + output RXCALFAILB; + output RXCOMMADETA; + output RXCOMMADETB; + output RXCYCLELIMITA; + output RXCYCLELIMITB; + output RXLOCKA; + output RXLOCKB; + output RXMCLKA; + output RXMCLKB; + output RXPCSHCLKOUTA; + output RXPCSHCLKOUTB; + output RXREALIGNA; + output RXREALIGNB; + output RXRECCLK1A; + output RXRECCLK1B; + output RXRECCLK2A; + output RXRECCLK2B; + output RXSIGDETA; + output RXSIGDETB; + output TX1NA; + output TX1NB; + output TX1PA; + output TX1PB; + output TXBUFERRA; + output TXBUFERRB; + output TXCALFAILA; + output TXCALFAILB; + output TXCYCLELIMITA; + output TXCYCLELIMITB; + output TXLOCKA; + output TXLOCKB; + output TXOUTCLK1A; + output TXOUTCLK1B; + output TXOUTCLK2A; + output TXOUTCLK2B; + output TXPCSHCLKOUTA; + output TXPCSHCLKOUTB; + output [15:0] DOA; + output [15:0] DOB; + output [1:0] RXLOSSOFSYNCA; + output [1:0] RXLOSSOFSYNCB; + output [31:0] RXCRCOUTA; + output [31:0] RXCRCOUTB; + output [31:0] TXCRCOUTA; + output [31:0] TXCRCOUTB; + output [4:0] CHBONDOA; + output [4:0] CHBONDOB; + output [5:0] RXSTATUSA; + output [5:0] RXSTATUSB; + output [63:0] RXDATAA; + output [63:0] RXDATAB; + output [7:0] RXCHARISCOMMAA; + output [7:0] RXCHARISCOMMAB; + output [7:0] RXCHARISKA; + output [7:0] RXCHARISKB; + output [7:0] RXDISPERRA; + output [7:0] RXDISPERRB; + output [7:0] RXNOTINTABLEA; + output [7:0] RXNOTINTABLEB; + output [7:0] RXRUNDISPA; + output [7:0] RXRUNDISPB; + output [7:0] TXKERRA; + output [7:0] TXKERRB; + output [7:0] TXRUNDISPA; + output [7:0] TXRUNDISPB; + input DCLKA; + input DCLKB; + input DENA; + input DENB; + input DWEA; + input DWEB; + input ENCHANSYNCA; + input ENCHANSYNCB; + input ENMCOMMAALIGNA; + input ENMCOMMAALIGNB; + input ENPCOMMAALIGNA; + input ENPCOMMAALIGNB; + input GREFCLKA; + input GREFCLKB; + input POWERDOWNA; + input POWERDOWNB; + input REFCLK1A; + input REFCLK1B; + input REFCLK2A; + input REFCLK2B; + input RX1NA; + input RX1NB; + input RX1PA; + input RX1PB; + input RXBLOCKSYNC64B66BUSEA; + input RXBLOCKSYNC64B66BUSEB; + input RXCLKSTABLEA; + input RXCLKSTABLEB; + input RXCOMMADETUSEA; + input RXCOMMADETUSEB; + input RXCRCCLKA; + input RXCRCCLKB; + input RXCRCDATAVALIDA; + input RXCRCDATAVALIDB; + input RXCRCINITA; + input RXCRCINITB; + input RXCRCINTCLKA; + input RXCRCINTCLKB; + input RXCRCPDA; + input RXCRCPDB; + input RXCRCRESETA; + input RXCRCRESETB; + input RXDEC64B66BUSEA; + input RXDEC64B66BUSEB; + input RXDEC8B10BUSEA; + input RXDEC8B10BUSEB; + input RXDESCRAM64B66BUSEA; + input RXDESCRAM64B66BUSEB; + input RXIGNOREBTFA; + input RXIGNOREBTFB; + input RXPMARESETA; + input RXPMARESETB; + input RXPOLARITYA; + input RXPOLARITYB; + input RXRESETA; + input RXRESETB; + input RXSLIDEA; + input RXSLIDEB; + input RXSYNCA; + input RXSYNCB; + input RXUSRCLK2A; + input RXUSRCLK2B; + input RXUSRCLKA; + input RXUSRCLKB; + input TXCLKSTABLEA; + input TXCLKSTABLEB; + input TXCRCCLKA; + input TXCRCCLKB; + input TXCRCDATAVALIDA; + input TXCRCDATAVALIDB; + input TXCRCINITA; + input TXCRCINITB; + input TXCRCINTCLKA; + input TXCRCINTCLKB; + input TXCRCPDA; + input TXCRCPDB; + input TXCRCRESETA; + input TXCRCRESETB; + input TXENC64B66BUSEA; + input TXENC64B66BUSEB; + input TXENC8B10BUSEA; + input TXENC8B10BUSEB; + input TXENOOBA; + input TXENOOBB; + input TXGEARBOX64B66BUSEA; + input TXGEARBOX64B66BUSEB; + input TXINHIBITA; + input TXINHIBITB; + input TXPMARESETA; + input TXPMARESETB; + input TXPOLARITYA; + input TXPOLARITYB; + input TXRESETA; + input TXRESETB; + input TXSCRAM64B66BUSEA; + input TXSCRAM64B66BUSEB; + input TXSYNCA; + input TXSYNCB; + input TXUSRCLK2A; + input TXUSRCLK2B; + input TXUSRCLKA; + input TXUSRCLKB; + input [15:0] DIA; + input [15:0] DIB; + input [1:0] LOOPBACKA; + input [1:0] LOOPBACKB; + input [1:0] RXDATAWIDTHA; + input [1:0] RXDATAWIDTHB; + input [1:0] RXINTDATAWIDTHA; + input [1:0] RXINTDATAWIDTHB; + input [1:0] TXDATAWIDTHA; + input [1:0] TXDATAWIDTHB; + input [1:0] TXINTDATAWIDTHA; + input [1:0] TXINTDATAWIDTHB; + input [2:0] RXCRCDATAWIDTHA; + input [2:0] RXCRCDATAWIDTHB; + input [2:0] TXCRCDATAWIDTHA; + input [2:0] TXCRCDATAWIDTHB; + input [4:0] CHBONDIA; + input [4:0] CHBONDIB; + input [63:0] RXCRCINA; + input [63:0] RXCRCINB; + input [63:0] TXCRCINA; + input [63:0] TXCRCINB; + input [63:0] TXDATAA; + input [63:0] TXDATAB; + input [7:0] DADDRA; + input [7:0] DADDRB; + input [7:0] TXBYPASS8B10BA; + input [7:0] TXBYPASS8B10BB; + input [7:0] TXCHARDISPMODEA; + input [7:0] TXCHARDISPMODEB; + input [7:0] TXCHARDISPVALA; + input [7:0] TXCHARDISPVALB; + input [7:0] TXCHARISKA; + input [7:0] TXCHARISKB; +endmodule + +module GT11CLK (...); + parameter REFCLKSEL = "MGTCLK"; + parameter SYNCLK1OUTEN = "ENABLE"; + parameter SYNCLK2OUTEN = "DISABLE"; + output SYNCLK1OUT; + output SYNCLK2OUT; + input MGTCLKN; + input MGTCLKP; + input REFCLK; + input RXBCLK; + input SYNCLK1IN; + input SYNCLK2IN; +endmodule + +module GT11CLK_MGT (...); + parameter SYNCLK1OUTEN = "ENABLE"; + parameter SYNCLK2OUTEN = "DISABLE"; + output SYNCLK1OUT; + output SYNCLK2OUT; + input MGTCLKN; + input MGTCLKP; +endmodule + +module GTP_DUAL (...); + parameter AC_CAP_DIS_0 = "TRUE"; + parameter AC_CAP_DIS_1 = "TRUE"; + parameter CHAN_BOND_MODE_0 = "OFF"; + parameter CHAN_BOND_MODE_1 = "OFF"; + parameter CHAN_BOND_SEQ_2_USE_0 = "TRUE"; + parameter CHAN_BOND_SEQ_2_USE_1 = "TRUE"; + parameter CLKINDC_B = "TRUE"; + parameter CLK_CORRECT_USE_0 = "TRUE"; + parameter CLK_CORRECT_USE_1 = "TRUE"; + parameter CLK_COR_INSERT_IDLE_FLAG_0 = "FALSE"; + parameter CLK_COR_INSERT_IDLE_FLAG_1 = "FALSE"; + parameter CLK_COR_KEEP_IDLE_0 = "FALSE"; + parameter CLK_COR_KEEP_IDLE_1 = "FALSE"; + parameter CLK_COR_PRECEDENCE_0 = "TRUE"; + parameter CLK_COR_PRECEDENCE_1 = "TRUE"; + parameter CLK_COR_SEQ_2_USE_0 = "FALSE"; + parameter CLK_COR_SEQ_2_USE_1 = "FALSE"; + parameter COMMA_DOUBLE_0 = "FALSE"; + parameter COMMA_DOUBLE_1 = "FALSE"; + parameter DEC_MCOMMA_DETECT_0 = "TRUE"; + parameter DEC_MCOMMA_DETECT_1 = "TRUE"; + parameter DEC_PCOMMA_DETECT_0 = "TRUE"; + parameter DEC_PCOMMA_DETECT_1 = "TRUE"; + parameter DEC_VALID_COMMA_ONLY_0 = "TRUE"; + parameter DEC_VALID_COMMA_ONLY_1 = "TRUE"; + parameter MCOMMA_DETECT_0 = "TRUE"; + parameter MCOMMA_DETECT_1 = "TRUE"; + parameter OVERSAMPLE_MODE = "FALSE"; + parameter PCI_EXPRESS_MODE_0 = "TRUE"; + parameter PCI_EXPRESS_MODE_1 = "TRUE"; + parameter PCOMMA_DETECT_0 = "TRUE"; + parameter PCOMMA_DETECT_1 = "TRUE"; + parameter PLL_SATA_0 = "FALSE"; + parameter PLL_SATA_1 = "FALSE"; + parameter RCV_TERM_GND_0 = "TRUE"; + parameter RCV_TERM_GND_1 = "TRUE"; + parameter RCV_TERM_MID_0 = "FALSE"; + parameter RCV_TERM_MID_1 = "FALSE"; + parameter RCV_TERM_VTTRX_0 = "FALSE"; + parameter RCV_TERM_VTTRX_1 = "FALSE"; + parameter RX_BUFFER_USE_0 = "TRUE"; + parameter RX_BUFFER_USE_1 = "TRUE"; + parameter RX_DECODE_SEQ_MATCH_0 = "TRUE"; + parameter RX_DECODE_SEQ_MATCH_1 = "TRUE"; + parameter RX_LOSS_OF_SYNC_FSM_0 = "FALSE"; + parameter RX_LOSS_OF_SYNC_FSM_1 = "FALSE"; + parameter RX_SLIDE_MODE_0 = "PCS"; + parameter RX_SLIDE_MODE_1 = "PCS"; + parameter RX_STATUS_FMT_0 = "PCIE"; + parameter RX_STATUS_FMT_1 = "PCIE"; + parameter RX_XCLK_SEL_0 = "RXREC"; + parameter RX_XCLK_SEL_1 = "RXREC"; + parameter SIM_PLL_PERDIV2 = 9'h190; + parameter SIM_RECEIVER_DETECT_PASS0 = "FALSE"; + parameter SIM_RECEIVER_DETECT_PASS1 = "FALSE"; + parameter TERMINATION_OVRD = "FALSE"; + parameter TX_BUFFER_USE_0 = "TRUE"; + parameter TX_BUFFER_USE_1 = "TRUE"; + parameter TX_DIFF_BOOST_0 = "TRUE"; + parameter TX_DIFF_BOOST_1 = "TRUE"; + parameter TX_XCLK_SEL_0 = "TXUSR"; + parameter TX_XCLK_SEL_1 = "TXUSR"; + parameter [15:0] TRANS_TIME_FROM_P2_0 = 16'h003c; + parameter [15:0] TRANS_TIME_FROM_P2_1 = 16'h003c; + parameter [15:0] TRANS_TIME_NON_P2_0 = 16'h0019; + parameter [15:0] TRANS_TIME_NON_P2_1 = 16'h0019; + parameter [15:0] TRANS_TIME_TO_P2_0 = 16'h0064; + parameter [15:0] TRANS_TIME_TO_P2_1 = 16'h0064; + parameter [24:0] PMA_RX_CFG_0 = 25'h09f0089; + parameter [24:0] PMA_RX_CFG_1 = 25'h09f0089; + parameter [26:0] PMA_CDR_SCAN_0 = 27'h6c07640; + parameter [26:0] PMA_CDR_SCAN_1 = 27'h6c07640; + parameter [27:0] PCS_COM_CFG = 28'h1680a0e; + parameter [2:0] OOBDETECT_THRESHOLD_0 = 3'b001; + parameter [2:0] OOBDETECT_THRESHOLD_1 = 3'b001; + parameter [2:0] SATA_BURST_VAL_0 = 3'b100; + parameter [2:0] SATA_BURST_VAL_1 = 3'b100; + parameter [2:0] SATA_IDLE_VAL_0 = 3'b011; + parameter [2:0] SATA_IDLE_VAL_1 = 3'b011; + parameter [31:0] PRBS_ERR_THRESHOLD_0 = 32'h1; + parameter [31:0] PRBS_ERR_THRESHOLD_1 = 32'h1; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_0 = 4'b1111; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_1 = 4'b1111; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_0 = 4'b1111; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_1 = 4'b1111; + parameter [3:0] CLK_COR_SEQ_1_ENABLE_0 = 4'b1111; + parameter [3:0] CLK_COR_SEQ_1_ENABLE_1 = 4'b1111; + parameter [3:0] CLK_COR_SEQ_2_ENABLE_0 = 4'b1111; + parameter [3:0] CLK_COR_SEQ_2_ENABLE_1 = 4'b1111; + parameter [3:0] COM_BURST_VAL_0 = 4'b1111; + parameter [3:0] COM_BURST_VAL_1 = 4'b1111; + parameter [4:0] TERMINATION_CTRL = 5'b10100; + parameter [4:0] TXRX_INVERT_0 = 5'b00000; + parameter [4:0] TXRX_INVERT_1 = 5'b00000; + parameter [9:0] CHAN_BOND_SEQ_1_1_0 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_1_1 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_2_0 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_2_1 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_3_0 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_3_1 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_4_0 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_1_4_1 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_2_1_0 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_2_1_1 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_2_2_0 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_2_1 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_3_0 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_3_1 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_4_0 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_4_1 = 10'b0100111100; + parameter [9:0] CLK_COR_SEQ_1_1_0 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_1_2_1 = 10'b0; + parameter [9:0] CLK_COR_SEQ_1_3_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_1_3_1 = 10'b0; + parameter [9:0] CLK_COR_SEQ_1_4_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_1_4_1 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_1_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_1_1 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_2_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_2_1 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_3_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_3_1 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_4_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_4_1 = 10'b0; + parameter [9:0] COMMA_10B_ENABLE_0 = 10'b1111111111; + parameter [9:0] COMMA_10B_ENABLE_1 = 10'b1111111111; + parameter [9:0] MCOMMA_10B_VALUE_0 = 10'b1010000011; + parameter [9:0] MCOMMA_10B_VALUE_1 = 10'b1010000011; + parameter [9:0] PCOMMA_10B_VALUE_0 = 10'b0101111100; + parameter [9:0] PCOMMA_10B_VALUE_1 = 10'b0101111100; + parameter ALIGN_COMMA_WORD_0 = 1; + parameter ALIGN_COMMA_WORD_1 = 1; + parameter CHAN_BOND_1_MAX_SKEW_0 = 7; + parameter CHAN_BOND_1_MAX_SKEW_1 = 7; + parameter CHAN_BOND_2_MAX_SKEW_0 = 1; + parameter CHAN_BOND_2_MAX_SKEW_1 = 1; + parameter CHAN_BOND_LEVEL_0 = 0; + parameter CHAN_BOND_LEVEL_1 = 0; + parameter CHAN_BOND_SEQ_LEN_0 = 4; + parameter CHAN_BOND_SEQ_LEN_1 = 4; + parameter CLK25_DIVIDER = 4; + parameter CLK_COR_ADJ_LEN_0 = 1; + parameter CLK_COR_ADJ_LEN_1 = 1; + parameter CLK_COR_DET_LEN_0 = 1; + parameter CLK_COR_DET_LEN_1 = 1; + parameter CLK_COR_MAX_LAT_0 = 18; + parameter CLK_COR_MAX_LAT_1 = 18; + parameter CLK_COR_MIN_LAT_0 = 16; + parameter CLK_COR_MIN_LAT_1 = 16; + parameter CLK_COR_REPEAT_WAIT_0 = 5; + parameter CLK_COR_REPEAT_WAIT_1 = 5; + parameter OOB_CLK_DIVIDER = 4; + parameter PLL_DIVSEL_FB = 5; + parameter PLL_DIVSEL_REF = 2; + parameter PLL_RXDIVSEL_OUT_0 = 1; + parameter PLL_RXDIVSEL_OUT_1 = 1; + parameter PLL_TXDIVSEL_COMM_OUT = 1; + parameter PLL_TXDIVSEL_OUT_0 = 1; + parameter PLL_TXDIVSEL_OUT_1 = 1; + parameter RX_LOS_INVALID_INCR_0 = 8; + parameter RX_LOS_INVALID_INCR_1 = 8; + parameter RX_LOS_THRESHOLD_0 = 128; + parameter RX_LOS_THRESHOLD_1 = 128; + parameter SATA_MAX_BURST_0 = 7; + parameter SATA_MAX_BURST_1 = 7; + parameter SATA_MAX_INIT_0 = 22; + parameter SATA_MAX_INIT_1 = 22; + parameter SATA_MAX_WAKE_0 = 7; + parameter SATA_MAX_WAKE_1 = 7; + parameter SATA_MIN_BURST_0 = 4; + parameter SATA_MIN_BURST_1 = 4; + parameter SATA_MIN_INIT_0 = 12; + parameter SATA_MIN_INIT_1 = 12; + parameter SATA_MIN_WAKE_0 = 4; + parameter SATA_MIN_WAKE_1 = 4; + parameter SIM_GTPRESET_SPEEDUP = 0; + parameter TERMINATION_IMP_0 = 50; + parameter TERMINATION_IMP_1 = 50; + parameter TX_SYNC_FILTERB = 1; + output DRDY; + output PHYSTATUS0; + output PHYSTATUS1; + output PLLLKDET; + output REFCLKOUT; + output RESETDONE0; + output RESETDONE1; + output RXBYTEISALIGNED0; + output RXBYTEISALIGNED1; + output RXBYTEREALIGN0; + output RXBYTEREALIGN1; + output RXCHANBONDSEQ0; + output RXCHANBONDSEQ1; + output RXCHANISALIGNED0; + output RXCHANISALIGNED1; + output RXCHANREALIGN0; + output RXCHANREALIGN1; + output RXCOMMADET0; + output RXCOMMADET1; + output RXELECIDLE0; + output RXELECIDLE1; + output RXOVERSAMPLEERR0; + output RXOVERSAMPLEERR1; + output RXPRBSERR0; + output RXPRBSERR1; + output RXRECCLK0; + output RXRECCLK1; + output RXVALID0; + output RXVALID1; + output TXN0; + output TXN1; + output TXOUTCLK0; + output TXOUTCLK1; + output TXP0; + output TXP1; + output [15:0] DO; + output [15:0] RXDATA0; + output [15:0] RXDATA1; + output [1:0] RXCHARISCOMMA0; + output [1:0] RXCHARISCOMMA1; + output [1:0] RXCHARISK0; + output [1:0] RXCHARISK1; + output [1:0] RXDISPERR0; + output [1:0] RXDISPERR1; + output [1:0] RXLOSSOFSYNC0; + output [1:0] RXLOSSOFSYNC1; + output [1:0] RXNOTINTABLE0; + output [1:0] RXNOTINTABLE1; + output [1:0] RXRUNDISP0; + output [1:0] RXRUNDISP1; + output [1:0] TXBUFSTATUS0; + output [1:0] TXBUFSTATUS1; + output [1:0] TXKERR0; + output [1:0] TXKERR1; + output [1:0] TXRUNDISP0; + output [1:0] TXRUNDISP1; + output [2:0] RXBUFSTATUS0; + output [2:0] RXBUFSTATUS1; + output [2:0] RXCHBONDO0; + output [2:0] RXCHBONDO1; + output [2:0] RXCLKCORCNT0; + output [2:0] RXCLKCORCNT1; + output [2:0] RXSTATUS0; + output [2:0] RXSTATUS1; + input CLKIN; + input DCLK; + input DEN; + input DWE; + input GTPRESET; + input INTDATAWIDTH; + input PLLLKDETEN; + input PLLPOWERDOWN; + input PRBSCNTRESET0; + input PRBSCNTRESET1; + input REFCLKPWRDNB; + input RXBUFRESET0; + input RXBUFRESET1; + input RXCDRRESET0; + input RXCDRRESET1; + input RXCOMMADETUSE0; + input RXCOMMADETUSE1; + input RXDATAWIDTH0; + input RXDATAWIDTH1; + input RXDEC8B10BUSE0; + input RXDEC8B10BUSE1; + input RXELECIDLERESET0; + input RXELECIDLERESET1; + input RXENCHANSYNC0; + input RXENCHANSYNC1; + input RXENELECIDLERESETB; + input RXENEQB0; + input RXENEQB1; + input RXENMCOMMAALIGN0; + input RXENMCOMMAALIGN1; + input RXENPCOMMAALIGN0; + input RXENPCOMMAALIGN1; + input RXENSAMPLEALIGN0; + input RXENSAMPLEALIGN1; + input RXN0; + input RXN1; + input RXP0; + input RXP1; + input RXPMASETPHASE0; + input RXPMASETPHASE1; + input RXPOLARITY0; + input RXPOLARITY1; + input RXRESET0; + input RXRESET1; + input RXSLIDE0; + input RXSLIDE1; + input RXUSRCLK0; + input RXUSRCLK1; + input RXUSRCLK20; + input RXUSRCLK21; + input TXCOMSTART0; + input TXCOMSTART1; + input TXCOMTYPE0; + input TXCOMTYPE1; + input TXDATAWIDTH0; + input TXDATAWIDTH1; + input TXDETECTRX0; + input TXDETECTRX1; + input TXELECIDLE0; + input TXELECIDLE1; + input TXENC8B10BUSE0; + input TXENC8B10BUSE1; + input TXENPMAPHASEALIGN; + input TXINHIBIT0; + input TXINHIBIT1; + input TXPMASETPHASE; + input TXPOLARITY0; + input TXPOLARITY1; + input TXRESET0; + input TXRESET1; + input TXUSRCLK0; + input TXUSRCLK1; + input TXUSRCLK20; + input TXUSRCLK21; + input [15:0] DI; + input [15:0] TXDATA0; + input [15:0] TXDATA1; + input [1:0] RXENPRBSTST0; + input [1:0] RXENPRBSTST1; + input [1:0] RXEQMIX0; + input [1:0] RXEQMIX1; + input [1:0] RXPOWERDOWN0; + input [1:0] RXPOWERDOWN1; + input [1:0] TXBYPASS8B10B0; + input [1:0] TXBYPASS8B10B1; + input [1:0] TXCHARDISPMODE0; + input [1:0] TXCHARDISPMODE1; + input [1:0] TXCHARDISPVAL0; + input [1:0] TXCHARDISPVAL1; + input [1:0] TXCHARISK0; + input [1:0] TXCHARISK1; + input [1:0] TXENPRBSTST0; + input [1:0] TXENPRBSTST1; + input [1:0] TXPOWERDOWN0; + input [1:0] TXPOWERDOWN1; + input [2:0] LOOPBACK0; + input [2:0] LOOPBACK1; + input [2:0] RXCHBONDI0; + input [2:0] RXCHBONDI1; + input [2:0] TXBUFDIFFCTRL0; + input [2:0] TXBUFDIFFCTRL1; + input [2:0] TXDIFFCTRL0; + input [2:0] TXDIFFCTRL1; + input [2:0] TXPREEMPHASIS0; + input [2:0] TXPREEMPHASIS1; + input [3:0] GTPTEST; + input [3:0] RXEQPOLE0; + input [3:0] RXEQPOLE1; + input [6:0] DADDR; +endmodule + +module GTX_DUAL (...); + parameter STEPPING = "0"; + parameter AC_CAP_DIS_0 = "TRUE"; + parameter AC_CAP_DIS_1 = "TRUE"; + parameter CHAN_BOND_KEEP_ALIGN_0 = "FALSE"; + parameter CHAN_BOND_KEEP_ALIGN_1 = "FALSE"; + parameter CHAN_BOND_MODE_0 = "OFF"; + parameter CHAN_BOND_MODE_1 = "OFF"; + parameter CHAN_BOND_SEQ_2_USE_0 = "TRUE"; + parameter CHAN_BOND_SEQ_2_USE_1 = "TRUE"; + parameter CLKINDC_B = "TRUE"; + parameter CLKRCV_TRST = "FALSE"; + parameter CLK_CORRECT_USE_0 = "TRUE"; + parameter CLK_CORRECT_USE_1 = "TRUE"; + parameter CLK_COR_INSERT_IDLE_FLAG_0 = "FALSE"; + parameter CLK_COR_INSERT_IDLE_FLAG_1 = "FALSE"; + parameter CLK_COR_KEEP_IDLE_0 = "FALSE"; + parameter CLK_COR_KEEP_IDLE_1 = "FALSE"; + parameter CLK_COR_PRECEDENCE_0 = "TRUE"; + parameter CLK_COR_PRECEDENCE_1 = "TRUE"; + parameter CLK_COR_SEQ_2_USE_0 = "FALSE"; + parameter CLK_COR_SEQ_2_USE_1 = "FALSE"; + parameter COMMA_DOUBLE_0 = "FALSE"; + parameter COMMA_DOUBLE_1 = "FALSE"; + parameter DEC_MCOMMA_DETECT_0 = "TRUE"; + parameter DEC_MCOMMA_DETECT_1 = "TRUE"; + parameter DEC_PCOMMA_DETECT_0 = "TRUE"; + parameter DEC_PCOMMA_DETECT_1 = "TRUE"; + parameter DEC_VALID_COMMA_ONLY_0 = "TRUE"; + parameter DEC_VALID_COMMA_ONLY_1 = "TRUE"; + parameter MCOMMA_DETECT_0 = "TRUE"; + parameter MCOMMA_DETECT_1 = "TRUE"; + parameter OVERSAMPLE_MODE = "FALSE"; + parameter PCI_EXPRESS_MODE_0 = "TRUE"; + parameter PCI_EXPRESS_MODE_1 = "TRUE"; + parameter PCOMMA_DETECT_0 = "TRUE"; + parameter PCOMMA_DETECT_1 = "TRUE"; + parameter PLL_FB_DCCEN = "FALSE"; + parameter PLL_SATA_0 = "FALSE"; + parameter PLL_SATA_1 = "FALSE"; + parameter RCV_TERM_GND_0 = "TRUE"; + parameter RCV_TERM_GND_1 = "TRUE"; + parameter RCV_TERM_VTTRX_0 = "FALSE"; + parameter RCV_TERM_VTTRX_1 = "FALSE"; + parameter RXGEARBOX_USE_0 = "FALSE"; + parameter RXGEARBOX_USE_1 = "FALSE"; + parameter RX_BUFFER_USE_0 = "TRUE"; + parameter RX_BUFFER_USE_1 = "TRUE"; + parameter RX_DECODE_SEQ_MATCH_0 = "TRUE"; + parameter RX_DECODE_SEQ_MATCH_1 = "TRUE"; + parameter RX_EN_IDLE_HOLD_CDR = "FALSE"; + parameter RX_EN_IDLE_HOLD_DFE_0 = "TRUE"; + parameter RX_EN_IDLE_HOLD_DFE_1 = "TRUE"; + parameter RX_EN_IDLE_RESET_BUF_0 = "TRUE"; + parameter RX_EN_IDLE_RESET_BUF_1 = "TRUE"; + parameter RX_EN_IDLE_RESET_FR = "TRUE"; + parameter RX_EN_IDLE_RESET_PH = "TRUE"; + parameter RX_LOSS_OF_SYNC_FSM_0 = "FALSE"; + parameter RX_LOSS_OF_SYNC_FSM_1 = "FALSE"; + parameter RX_SLIDE_MODE_0 = "PCS"; + parameter RX_SLIDE_MODE_1 = "PCS"; + parameter RX_STATUS_FMT_0 = "PCIE"; + parameter RX_STATUS_FMT_1 = "PCIE"; + parameter RX_XCLK_SEL_0 = "RXREC"; + parameter RX_XCLK_SEL_1 = "RXREC"; + parameter SIM_PLL_PERDIV2 = 9'h190; + parameter SIM_RECEIVER_DETECT_PASS_0 = "FALSE"; + parameter SIM_RECEIVER_DETECT_PASS_1 = "FALSE"; + parameter TERMINATION_OVRD = "FALSE"; + parameter TXGEARBOX_USE_0 = "FALSE"; + parameter TXGEARBOX_USE_1 = "FALSE"; + parameter TX_BUFFER_USE_0 = "TRUE"; + parameter TX_BUFFER_USE_1 = "TRUE"; + parameter TX_XCLK_SEL_0 = "TXUSR"; + parameter TX_XCLK_SEL_1 = "TXUSR"; + parameter [11:0] TRANS_TIME_FROM_P2_0 = 12'h03c; + parameter [11:0] TRANS_TIME_FROM_P2_1 = 12'h03c; + parameter [13:0] TX_DETECT_RX_CFG_0 = 14'h1832; + parameter [13:0] TX_DETECT_RX_CFG_1 = 14'h1832; + parameter [19:0] PMA_TX_CFG_0 = 20'h00082; + parameter [19:0] PMA_TX_CFG_1 = 20'h00082; + parameter [1:0] CM_TRIM_0 = 2'b10; + parameter [1:0] CM_TRIM_1 = 2'b10; + parameter [23:0] PLL_COM_CFG = 24'h21680a; + parameter [24:0] PMA_RX_CFG_0 = 25'h05ce109; + parameter [24:0] PMA_RX_CFG_1 = 25'h05ce109; + parameter [26:0] PMA_CDR_SCAN_0 = 27'h6c08040; + parameter [26:0] PMA_CDR_SCAN_1 = 27'h6c08040; + parameter [2:0] GEARBOX_ENDEC_0 = 3'b000; + parameter [2:0] GEARBOX_ENDEC_1 = 3'b000; + parameter [2:0] OOBDETECT_THRESHOLD_0 = 3'b111; + parameter [2:0] OOBDETECT_THRESHOLD_1 = 3'b111; + parameter [2:0] PLL_LKDET_CFG = 3'b111; + parameter [2:0] PLL_TDCC_CFG = 3'b000; + parameter [2:0] SATA_BURST_VAL_0 = 3'b100; + parameter [2:0] SATA_BURST_VAL_1 = 3'b100; + parameter [2:0] SATA_IDLE_VAL_0 = 3'b011; + parameter [2:0] SATA_IDLE_VAL_1 = 3'b011; + parameter [2:0] TXRX_INVERT_0 = 3'b000; + parameter [2:0] TXRX_INVERT_1 = 3'b000; + parameter [2:0] TX_IDLE_DELAY_0 = 3'b010; + parameter [2:0] TX_IDLE_DELAY_1 = 3'b010; + parameter [31:0] PRBS_ERR_THRESHOLD_0 = 32'h1; + parameter [31:0] PRBS_ERR_THRESHOLD_1 = 32'h1; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_0 = 4'b1111; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_1 = 4'b1111; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_0 = 4'b1111; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_1 = 4'b1111; + parameter [3:0] CLK_COR_SEQ_1_ENABLE_0 = 4'b1111; + parameter [3:0] CLK_COR_SEQ_1_ENABLE_1 = 4'b1111; + parameter [3:0] CLK_COR_SEQ_2_ENABLE_0 = 4'b1111; + parameter [3:0] CLK_COR_SEQ_2_ENABLE_1 = 4'b1111; + parameter [3:0] COM_BURST_VAL_0 = 4'b1111; + parameter [3:0] COM_BURST_VAL_1 = 4'b1111; + parameter [3:0] RX_IDLE_HI_CNT_0 = 4'b1000; + parameter [3:0] RX_IDLE_HI_CNT_1 = 4'b1000; + parameter [3:0] RX_IDLE_LO_CNT_0 = 4'b0000; + parameter [3:0] RX_IDLE_LO_CNT_1 = 4'b0000; + parameter [4:0] CDR_PH_ADJ_TIME = 5'b01010; + parameter [4:0] DFE_CAL_TIME = 5'b00110; + parameter [4:0] TERMINATION_CTRL = 5'b10100; + parameter [68:0] PMA_COM_CFG = 69'h0; + parameter [6:0] PMA_RXSYNC_CFG_0 = 7'h0; + parameter [6:0] PMA_RXSYNC_CFG_1 = 7'h0; + parameter [7:0] PLL_CP_CFG = 8'h00; + parameter [7:0] TRANS_TIME_NON_P2_0 = 8'h19; + parameter [7:0] TRANS_TIME_NON_P2_1 = 8'h19; + parameter [9:0] CHAN_BOND_SEQ_1_1_0 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_1_1 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_2_0 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_2_1 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_3_0 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_3_1 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_4_0 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_1_4_1 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_2_1_0 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_2_1_1 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_2_2_0 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_2_1 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_3_0 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_3_1 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_4_0 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_4_1 = 10'b0100111100; + parameter [9:0] CLK_COR_SEQ_1_1_0 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_1_2_1 = 10'b0; + parameter [9:0] CLK_COR_SEQ_1_3_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_1_3_1 = 10'b0; + parameter [9:0] CLK_COR_SEQ_1_4_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_1_4_1 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_1_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_1_1 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_2_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_2_1 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_3_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_3_1 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_4_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_4_1 = 10'b0; + parameter [9:0] COMMA_10B_ENABLE_0 = 10'b1111111111; + parameter [9:0] COMMA_10B_ENABLE_1 = 10'b1111111111; + parameter [9:0] DFE_CFG_0 = 10'b0001111011; + parameter [9:0] DFE_CFG_1 = 10'b0001111011; + parameter [9:0] MCOMMA_10B_VALUE_0 = 10'b1010000011; + parameter [9:0] MCOMMA_10B_VALUE_1 = 10'b1010000011; + parameter [9:0] PCOMMA_10B_VALUE_0 = 10'b0101111100; + parameter [9:0] PCOMMA_10B_VALUE_1 = 10'b0101111100; + parameter [9:0] TRANS_TIME_TO_P2_0 = 10'h064; + parameter [9:0] TRANS_TIME_TO_P2_1 = 10'h064; + parameter ALIGN_COMMA_WORD_0 = 1; + parameter ALIGN_COMMA_WORD_1 = 1; + parameter CB2_INH_CC_PERIOD_0 = 8; + parameter CB2_INH_CC_PERIOD_1 = 8; + parameter CHAN_BOND_1_MAX_SKEW_0 = 7; + parameter CHAN_BOND_1_MAX_SKEW_1 = 7; + parameter CHAN_BOND_2_MAX_SKEW_0 = 1; + parameter CHAN_BOND_2_MAX_SKEW_1 = 1; + parameter CHAN_BOND_LEVEL_0 = 0; + parameter CHAN_BOND_LEVEL_1 = 0; + parameter CHAN_BOND_SEQ_LEN_0 = 4; + parameter CHAN_BOND_SEQ_LEN_1 = 4; + parameter CLK25_DIVIDER = 4; + parameter CLK_COR_ADJ_LEN_0 = 1; + parameter CLK_COR_ADJ_LEN_1 = 1; + parameter CLK_COR_DET_LEN_0 = 1; + parameter CLK_COR_DET_LEN_1 = 1; + parameter CLK_COR_MAX_LAT_0 = 18; + parameter CLK_COR_MAX_LAT_1 = 18; + parameter CLK_COR_MIN_LAT_0 = 16; + parameter CLK_COR_MIN_LAT_1 = 16; + parameter CLK_COR_REPEAT_WAIT_0 = 5; + parameter CLK_COR_REPEAT_WAIT_1 = 5; + parameter OOB_CLK_DIVIDER = 4; + parameter PLL_DIVSEL_FB = 5; + parameter PLL_DIVSEL_REF = 2; + parameter PLL_RXDIVSEL_OUT_0 = 1; + parameter PLL_RXDIVSEL_OUT_1 = 1; + parameter PLL_TXDIVSEL_OUT_0 = 1; + parameter PLL_TXDIVSEL_OUT_1 = 1; + parameter RX_LOS_INVALID_INCR_0 = 8; + parameter RX_LOS_INVALID_INCR_1 = 8; + parameter RX_LOS_THRESHOLD_0 = 128; + parameter RX_LOS_THRESHOLD_1 = 128; + parameter SATA_MAX_BURST_0 = 7; + parameter SATA_MAX_BURST_1 = 7; + parameter SATA_MAX_INIT_0 = 22; + parameter SATA_MAX_INIT_1 = 22; + parameter SATA_MAX_WAKE_0 = 7; + parameter SATA_MAX_WAKE_1 = 7; + parameter SATA_MIN_BURST_0 = 4; + parameter SATA_MIN_BURST_1 = 4; + parameter SATA_MIN_INIT_0 = 12; + parameter SATA_MIN_INIT_1 = 12; + parameter SATA_MIN_WAKE_0 = 4; + parameter SATA_MIN_WAKE_1 = 4; + parameter SIM_GTXRESET_SPEEDUP = 0; + parameter TERMINATION_IMP_0 = 50; + parameter TERMINATION_IMP_1 = 50; + output DRDY; + output PHYSTATUS0; + output PHYSTATUS1; + output PLLLKDET; + output REFCLKOUT; + output RESETDONE0; + output RESETDONE1; + output RXBYTEISALIGNED0; + output RXBYTEISALIGNED1; + output RXBYTEREALIGN0; + output RXBYTEREALIGN1; + output RXCHANBONDSEQ0; + output RXCHANBONDSEQ1; + output RXCHANISALIGNED0; + output RXCHANISALIGNED1; + output RXCHANREALIGN0; + output RXCHANREALIGN1; + output RXCOMMADET0; + output RXCOMMADET1; + output RXDATAVALID0; + output RXDATAVALID1; + output RXELECIDLE0; + output RXELECIDLE1; + output RXHEADERVALID0; + output RXHEADERVALID1; + output RXOVERSAMPLEERR0; + output RXOVERSAMPLEERR1; + output RXPRBSERR0; + output RXPRBSERR1; + output RXRECCLK0; + output RXRECCLK1; + output RXSTARTOFSEQ0; + output RXSTARTOFSEQ1; + output RXVALID0; + output RXVALID1; + output TXGEARBOXREADY0; + output TXGEARBOXREADY1; + output TXN0; + output TXN1; + output TXOUTCLK0; + output TXOUTCLK1; + output TXP0; + output TXP1; + output [15:0] DO; + output [1:0] RXLOSSOFSYNC0; + output [1:0] RXLOSSOFSYNC1; + output [1:0] TXBUFSTATUS0; + output [1:0] TXBUFSTATUS1; + output [2:0] DFESENSCAL0; + output [2:0] DFESENSCAL1; + output [2:0] RXBUFSTATUS0; + output [2:0] RXBUFSTATUS1; + output [2:0] RXCLKCORCNT0; + output [2:0] RXCLKCORCNT1; + output [2:0] RXHEADER0; + output [2:0] RXHEADER1; + output [2:0] RXSTATUS0; + output [2:0] RXSTATUS1; + output [31:0] RXDATA0; + output [31:0] RXDATA1; + output [3:0] DFETAP3MONITOR0; + output [3:0] DFETAP3MONITOR1; + output [3:0] DFETAP4MONITOR0; + output [3:0] DFETAP4MONITOR1; + output [3:0] RXCHARISCOMMA0; + output [3:0] RXCHARISCOMMA1; + output [3:0] RXCHARISK0; + output [3:0] RXCHARISK1; + output [3:0] RXCHBONDO0; + output [3:0] RXCHBONDO1; + output [3:0] RXDISPERR0; + output [3:0] RXDISPERR1; + output [3:0] RXNOTINTABLE0; + output [3:0] RXNOTINTABLE1; + output [3:0] RXRUNDISP0; + output [3:0] RXRUNDISP1; + output [3:0] TXKERR0; + output [3:0] TXKERR1; + output [3:0] TXRUNDISP0; + output [3:0] TXRUNDISP1; + output [4:0] DFEEYEDACMONITOR0; + output [4:0] DFEEYEDACMONITOR1; + output [4:0] DFETAP1MONITOR0; + output [4:0] DFETAP1MONITOR1; + output [4:0] DFETAP2MONITOR0; + output [4:0] DFETAP2MONITOR1; + output [5:0] DFECLKDLYADJMONITOR0; + output [5:0] DFECLKDLYADJMONITOR1; + input CLKIN; + input DCLK; + input DEN; + input DWE; + input GTXRESET; + input INTDATAWIDTH; + input PLLLKDETEN; + input PLLPOWERDOWN; + input PRBSCNTRESET0; + input PRBSCNTRESET1; + input REFCLKPWRDNB; + input RXBUFRESET0; + input RXBUFRESET1; + input RXCDRRESET0; + input RXCDRRESET1; + input RXCOMMADETUSE0; + input RXCOMMADETUSE1; + input RXDEC8B10BUSE0; + input RXDEC8B10BUSE1; + input RXENCHANSYNC0; + input RXENCHANSYNC1; + input RXENEQB0; + input RXENEQB1; + input RXENMCOMMAALIGN0; + input RXENMCOMMAALIGN1; + input RXENPCOMMAALIGN0; + input RXENPCOMMAALIGN1; + input RXENPMAPHASEALIGN0; + input RXENPMAPHASEALIGN1; + input RXENSAMPLEALIGN0; + input RXENSAMPLEALIGN1; + input RXGEARBOXSLIP0; + input RXGEARBOXSLIP1; + input RXN0; + input RXN1; + input RXP0; + input RXP1; + input RXPMASETPHASE0; + input RXPMASETPHASE1; + input RXPOLARITY0; + input RXPOLARITY1; + input RXRESET0; + input RXRESET1; + input RXSLIDE0; + input RXSLIDE1; + input RXUSRCLK0; + input RXUSRCLK1; + input RXUSRCLK20; + input RXUSRCLK21; + input TXCOMSTART0; + input TXCOMSTART1; + input TXCOMTYPE0; + input TXCOMTYPE1; + input TXDETECTRX0; + input TXDETECTRX1; + input TXELECIDLE0; + input TXELECIDLE1; + input TXENC8B10BUSE0; + input TXENC8B10BUSE1; + input TXENPMAPHASEALIGN0; + input TXENPMAPHASEALIGN1; + input TXINHIBIT0; + input TXINHIBIT1; + input TXPMASETPHASE0; + input TXPMASETPHASE1; + input TXPOLARITY0; + input TXPOLARITY1; + input TXRESET0; + input TXRESET1; + input TXSTARTSEQ0; + input TXSTARTSEQ1; + input TXUSRCLK0; + input TXUSRCLK1; + input TXUSRCLK20; + input TXUSRCLK21; + input [13:0] GTXTEST; + input [15:0] DI; + input [1:0] RXDATAWIDTH0; + input [1:0] RXDATAWIDTH1; + input [1:0] RXENPRBSTST0; + input [1:0] RXENPRBSTST1; + input [1:0] RXEQMIX0; + input [1:0] RXEQMIX1; + input [1:0] RXPOWERDOWN0; + input [1:0] RXPOWERDOWN1; + input [1:0] TXDATAWIDTH0; + input [1:0] TXDATAWIDTH1; + input [1:0] TXENPRBSTST0; + input [1:0] TXENPRBSTST1; + input [1:0] TXPOWERDOWN0; + input [1:0] TXPOWERDOWN1; + input [2:0] LOOPBACK0; + input [2:0] LOOPBACK1; + input [2:0] TXBUFDIFFCTRL0; + input [2:0] TXBUFDIFFCTRL1; + input [2:0] TXDIFFCTRL0; + input [2:0] TXDIFFCTRL1; + input [2:0] TXHEADER0; + input [2:0] TXHEADER1; + input [31:0] TXDATA0; + input [31:0] TXDATA1; + input [3:0] DFETAP30; + input [3:0] DFETAP31; + input [3:0] DFETAP40; + input [3:0] DFETAP41; + input [3:0] RXCHBONDI0; + input [3:0] RXCHBONDI1; + input [3:0] RXEQPOLE0; + input [3:0] RXEQPOLE1; + input [3:0] TXBYPASS8B10B0; + input [3:0] TXBYPASS8B10B1; + input [3:0] TXCHARDISPMODE0; + input [3:0] TXCHARDISPMODE1; + input [3:0] TXCHARDISPVAL0; + input [3:0] TXCHARDISPVAL1; + input [3:0] TXCHARISK0; + input [3:0] TXCHARISK1; + input [3:0] TXPREEMPHASIS0; + input [3:0] TXPREEMPHASIS1; + input [4:0] DFETAP10; + input [4:0] DFETAP11; + input [4:0] DFETAP20; + input [4:0] DFETAP21; + input [5:0] DFECLKDLYADJ0; + input [5:0] DFECLKDLYADJ1; + input [6:0] DADDR; + input [6:0] TXSEQUENCE0; + input [6:0] TXSEQUENCE1; +endmodule + +module CRC32 (...); + parameter CRC_INIT = 32'hFFFFFFFF; + output [31:0] CRCOUT; + (* clkbuf_sink *) + input CRCCLK; + input CRCDATAVALID; + input [2:0] CRCDATAWIDTH; + input [31:0] CRCIN; + input CRCRESET; +endmodule + +module CRC64 (...); + parameter CRC_INIT = 32'hFFFFFFFF; + output [31:0] CRCOUT; + (* clkbuf_sink *) + input CRCCLK; + input CRCDATAVALID; + input [2:0] CRCDATAWIDTH; + input [63:0] CRCIN; + input CRCRESET; +endmodule + +module GTHE1_QUAD (...); + parameter [15:0] BER_CONST_PTRN0 = 16'h0000; + parameter [15:0] BER_CONST_PTRN1 = 16'h0000; + parameter [15:0] BUFFER_CONFIG_LANE0 = 16'h4004; + parameter [15:0] BUFFER_CONFIG_LANE1 = 16'h4004; + parameter [15:0] BUFFER_CONFIG_LANE2 = 16'h4004; + parameter [15:0] BUFFER_CONFIG_LANE3 = 16'h4004; + parameter [15:0] DFE_TRAIN_CTRL_LANE0 = 16'h0000; + parameter [15:0] DFE_TRAIN_CTRL_LANE1 = 16'h0000; + parameter [15:0] DFE_TRAIN_CTRL_LANE2 = 16'h0000; + parameter [15:0] DFE_TRAIN_CTRL_LANE3 = 16'h0000; + parameter [15:0] DLL_CFG0 = 16'h8202; + parameter [15:0] DLL_CFG1 = 16'h0000; + parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE0 = 16'h0000; + parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE1 = 16'h0000; + parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE2 = 16'h0000; + parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE3 = 16'h0000; + parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE0 = 16'h0000; + parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE1 = 16'h0000; + parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE2 = 16'h0000; + parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE3 = 16'h0000; + parameter [15:0] E10GBASEKR_PMA_CTRL_LANE0 = 16'h0002; + parameter [15:0] E10GBASEKR_PMA_CTRL_LANE1 = 16'h0002; + parameter [15:0] E10GBASEKR_PMA_CTRL_LANE2 = 16'h0002; + parameter [15:0] E10GBASEKR_PMA_CTRL_LANE3 = 16'h0002; + parameter [15:0] E10GBASEKX_CTRL_LANE0 = 16'h0000; + parameter [15:0] E10GBASEKX_CTRL_LANE1 = 16'h0000; + parameter [15:0] E10GBASEKX_CTRL_LANE2 = 16'h0000; + parameter [15:0] E10GBASEKX_CTRL_LANE3 = 16'h0000; + parameter [15:0] E10GBASER_PCS_CFG_LANE0 = 16'h070C; + parameter [15:0] E10GBASER_PCS_CFG_LANE1 = 16'h070C; + parameter [15:0] E10GBASER_PCS_CFG_LANE2 = 16'h070C; + parameter [15:0] E10GBASER_PCS_CFG_LANE3 = 16'h070C; + parameter [15:0] E10GBASER_PCS_SEEDA0_LANE0 = 16'h0001; + parameter [15:0] E10GBASER_PCS_SEEDA0_LANE1 = 16'h0001; + parameter [15:0] E10GBASER_PCS_SEEDA0_LANE2 = 16'h0001; + parameter [15:0] E10GBASER_PCS_SEEDA0_LANE3 = 16'h0001; + parameter [15:0] E10GBASER_PCS_SEEDA1_LANE0 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA1_LANE1 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA1_LANE2 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA1_LANE3 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA2_LANE0 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA2_LANE1 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA2_LANE2 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA2_LANE3 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA3_LANE0 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA3_LANE1 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA3_LANE2 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA3_LANE3 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB0_LANE0 = 16'h0001; + parameter [15:0] E10GBASER_PCS_SEEDB0_LANE1 = 16'h0001; + parameter [15:0] E10GBASER_PCS_SEEDB0_LANE2 = 16'h0001; + parameter [15:0] E10GBASER_PCS_SEEDB0_LANE3 = 16'h0001; + parameter [15:0] E10GBASER_PCS_SEEDB1_LANE0 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB1_LANE1 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB1_LANE2 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB1_LANE3 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB2_LANE0 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB2_LANE1 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB2_LANE2 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB2_LANE3 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB3_LANE0 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB3_LANE1 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB3_LANE2 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB3_LANE3 = 16'h0000; + parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE0 = 16'h0000; + parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE1 = 16'h0000; + parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE2 = 16'h0000; + parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE3 = 16'h0000; + parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE0 = 16'h0000; + parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE1 = 16'h0000; + parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE2 = 16'h0000; + parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE3 = 16'h0000; + parameter [15:0] GLBL0_NOISE_CTRL = 16'hF0B8; + parameter [15:0] GLBL_AMON_SEL = 16'h0000; + parameter [15:0] GLBL_DMON_SEL = 16'h0200; + parameter [15:0] GLBL_PWR_CTRL = 16'h0000; + parameter [0:0] GTH_CFG_PWRUP_LANE0 = 1'b1; + parameter [0:0] GTH_CFG_PWRUP_LANE1 = 1'b1; + parameter [0:0] GTH_CFG_PWRUP_LANE2 = 1'b1; + parameter [0:0] GTH_CFG_PWRUP_LANE3 = 1'b1; + parameter [15:0] LANE_AMON_SEL = 16'h00F0; + parameter [15:0] LANE_DMON_SEL = 16'h0000; + parameter [15:0] LANE_LNK_CFGOVRD = 16'h0000; + parameter [15:0] LANE_PWR_CTRL_LANE0 = 16'h0400; + parameter [15:0] LANE_PWR_CTRL_LANE1 = 16'h0400; + parameter [15:0] LANE_PWR_CTRL_LANE2 = 16'h0400; + parameter [15:0] LANE_PWR_CTRL_LANE3 = 16'h0400; + parameter [15:0] LNK_TRN_CFG_LANE0 = 16'h0000; + parameter [15:0] LNK_TRN_CFG_LANE1 = 16'h0000; + parameter [15:0] LNK_TRN_CFG_LANE2 = 16'h0000; + parameter [15:0] LNK_TRN_CFG_LANE3 = 16'h0000; + parameter [15:0] LNK_TRN_COEFF_REQ_LANE0 = 16'h0000; + parameter [15:0] LNK_TRN_COEFF_REQ_LANE1 = 16'h0000; + parameter [15:0] LNK_TRN_COEFF_REQ_LANE2 = 16'h0000; + parameter [15:0] LNK_TRN_COEFF_REQ_LANE3 = 16'h0000; + parameter [15:0] MISC_CFG = 16'h0008; + parameter [15:0] MODE_CFG1 = 16'h0000; + parameter [15:0] MODE_CFG2 = 16'h0000; + parameter [15:0] MODE_CFG3 = 16'h0000; + parameter [15:0] MODE_CFG4 = 16'h0000; + parameter [15:0] MODE_CFG5 = 16'h0000; + parameter [15:0] MODE_CFG6 = 16'h0000; + parameter [15:0] MODE_CFG7 = 16'h0000; + parameter [15:0] PCS_ABILITY_LANE0 = 16'h0010; + parameter [15:0] PCS_ABILITY_LANE1 = 16'h0010; + parameter [15:0] PCS_ABILITY_LANE2 = 16'h0010; + parameter [15:0] PCS_ABILITY_LANE3 = 16'h0010; + parameter [15:0] PCS_CTRL1_LANE0 = 16'h2040; + parameter [15:0] PCS_CTRL1_LANE1 = 16'h2040; + parameter [15:0] PCS_CTRL1_LANE2 = 16'h2040; + parameter [15:0] PCS_CTRL1_LANE3 = 16'h2040; + parameter [15:0] PCS_CTRL2_LANE0 = 16'h0000; + parameter [15:0] PCS_CTRL2_LANE1 = 16'h0000; + parameter [15:0] PCS_CTRL2_LANE2 = 16'h0000; + parameter [15:0] PCS_CTRL2_LANE3 = 16'h0000; + parameter [15:0] PCS_MISC_CFG_0_LANE0 = 16'h1116; + parameter [15:0] PCS_MISC_CFG_0_LANE1 = 16'h1116; + parameter [15:0] PCS_MISC_CFG_0_LANE2 = 16'h1116; + parameter [15:0] PCS_MISC_CFG_0_LANE3 = 16'h1116; + parameter [15:0] PCS_MISC_CFG_1_LANE0 = 16'h0000; + parameter [15:0] PCS_MISC_CFG_1_LANE1 = 16'h0000; + parameter [15:0] PCS_MISC_CFG_1_LANE2 = 16'h0000; + parameter [15:0] PCS_MISC_CFG_1_LANE3 = 16'h0000; + parameter [15:0] PCS_MODE_LANE0 = 16'h0000; + parameter [15:0] PCS_MODE_LANE1 = 16'h0000; + parameter [15:0] PCS_MODE_LANE2 = 16'h0000; + parameter [15:0] PCS_MODE_LANE3 = 16'h0000; + parameter [15:0] PCS_RESET_1_LANE0 = 16'h0002; + parameter [15:0] PCS_RESET_1_LANE1 = 16'h0002; + parameter [15:0] PCS_RESET_1_LANE2 = 16'h0002; + parameter [15:0] PCS_RESET_1_LANE3 = 16'h0002; + parameter [15:0] PCS_RESET_LANE0 = 16'h0000; + parameter [15:0] PCS_RESET_LANE1 = 16'h0000; + parameter [15:0] PCS_RESET_LANE2 = 16'h0000; + parameter [15:0] PCS_RESET_LANE3 = 16'h0000; + parameter [15:0] PCS_TYPE_LANE0 = 16'h002C; + parameter [15:0] PCS_TYPE_LANE1 = 16'h002C; + parameter [15:0] PCS_TYPE_LANE2 = 16'h002C; + parameter [15:0] PCS_TYPE_LANE3 = 16'h002C; + parameter [15:0] PLL_CFG0 = 16'h95DF; + parameter [15:0] PLL_CFG1 = 16'h81C0; + parameter [15:0] PLL_CFG2 = 16'h0424; + parameter [15:0] PMA_CTRL1_LANE0 = 16'h0000; + parameter [15:0] PMA_CTRL1_LANE1 = 16'h0000; + parameter [15:0] PMA_CTRL1_LANE2 = 16'h0000; + parameter [15:0] PMA_CTRL1_LANE3 = 16'h0000; + parameter [15:0] PMA_CTRL2_LANE0 = 16'h000B; + parameter [15:0] PMA_CTRL2_LANE1 = 16'h000B; + parameter [15:0] PMA_CTRL2_LANE2 = 16'h000B; + parameter [15:0] PMA_CTRL2_LANE3 = 16'h000B; + parameter [15:0] PMA_LPBK_CTRL_LANE0 = 16'h0004; + parameter [15:0] PMA_LPBK_CTRL_LANE1 = 16'h0004; + parameter [15:0] PMA_LPBK_CTRL_LANE2 = 16'h0004; + parameter [15:0] PMA_LPBK_CTRL_LANE3 = 16'h0004; + parameter [15:0] PRBS_BER_CFG0_LANE0 = 16'h0000; + parameter [15:0] PRBS_BER_CFG0_LANE1 = 16'h0000; + parameter [15:0] PRBS_BER_CFG0_LANE2 = 16'h0000; + parameter [15:0] PRBS_BER_CFG0_LANE3 = 16'h0000; + parameter [15:0] PRBS_BER_CFG1_LANE0 = 16'h0000; + parameter [15:0] PRBS_BER_CFG1_LANE1 = 16'h0000; + parameter [15:0] PRBS_BER_CFG1_LANE2 = 16'h0000; + parameter [15:0] PRBS_BER_CFG1_LANE3 = 16'h0000; + parameter [15:0] PRBS_CFG_LANE0 = 16'h000A; + parameter [15:0] PRBS_CFG_LANE1 = 16'h000A; + parameter [15:0] PRBS_CFG_LANE2 = 16'h000A; + parameter [15:0] PRBS_CFG_LANE3 = 16'h000A; + parameter [15:0] PTRN_CFG0_LSB = 16'h5555; + parameter [15:0] PTRN_CFG0_MSB = 16'h5555; + parameter [15:0] PTRN_LEN_CFG = 16'h001F; + parameter [15:0] PWRUP_DLY = 16'h0000; + parameter [15:0] RX_AEQ_VAL0_LANE0 = 16'h03C0; + parameter [15:0] RX_AEQ_VAL0_LANE1 = 16'h03C0; + parameter [15:0] RX_AEQ_VAL0_LANE2 = 16'h03C0; + parameter [15:0] RX_AEQ_VAL0_LANE3 = 16'h03C0; + parameter [15:0] RX_AEQ_VAL1_LANE0 = 16'h0000; + parameter [15:0] RX_AEQ_VAL1_LANE1 = 16'h0000; + parameter [15:0] RX_AEQ_VAL1_LANE2 = 16'h0000; + parameter [15:0] RX_AEQ_VAL1_LANE3 = 16'h0000; + parameter [15:0] RX_AGC_CTRL_LANE0 = 16'h0000; + parameter [15:0] RX_AGC_CTRL_LANE1 = 16'h0000; + parameter [15:0] RX_AGC_CTRL_LANE2 = 16'h0000; + parameter [15:0] RX_AGC_CTRL_LANE3 = 16'h0000; + parameter [15:0] RX_CDR_CTRL0_LANE0 = 16'h0005; + parameter [15:0] RX_CDR_CTRL0_LANE1 = 16'h0005; + parameter [15:0] RX_CDR_CTRL0_LANE2 = 16'h0005; + parameter [15:0] RX_CDR_CTRL0_LANE3 = 16'h0005; + parameter [15:0] RX_CDR_CTRL1_LANE0 = 16'h4200; + parameter [15:0] RX_CDR_CTRL1_LANE1 = 16'h4200; + parameter [15:0] RX_CDR_CTRL1_LANE2 = 16'h4200; + parameter [15:0] RX_CDR_CTRL1_LANE3 = 16'h4200; + parameter [15:0] RX_CDR_CTRL2_LANE0 = 16'h2000; + parameter [15:0] RX_CDR_CTRL2_LANE1 = 16'h2000; + parameter [15:0] RX_CDR_CTRL2_LANE2 = 16'h2000; + parameter [15:0] RX_CDR_CTRL2_LANE3 = 16'h2000; + parameter [15:0] RX_CFG0_LANE0 = 16'h0500; + parameter [15:0] RX_CFG0_LANE1 = 16'h0500; + parameter [15:0] RX_CFG0_LANE2 = 16'h0500; + parameter [15:0] RX_CFG0_LANE3 = 16'h0500; + parameter [15:0] RX_CFG1_LANE0 = 16'h821F; + parameter [15:0] RX_CFG1_LANE1 = 16'h821F; + parameter [15:0] RX_CFG1_LANE2 = 16'h821F; + parameter [15:0] RX_CFG1_LANE3 = 16'h821F; + parameter [15:0] RX_CFG2_LANE0 = 16'h1001; + parameter [15:0] RX_CFG2_LANE1 = 16'h1001; + parameter [15:0] RX_CFG2_LANE2 = 16'h1001; + parameter [15:0] RX_CFG2_LANE3 = 16'h1001; + parameter [15:0] RX_CTLE_CTRL_LANE0 = 16'h008F; + parameter [15:0] RX_CTLE_CTRL_LANE1 = 16'h008F; + parameter [15:0] RX_CTLE_CTRL_LANE2 = 16'h008F; + parameter [15:0] RX_CTLE_CTRL_LANE3 = 16'h008F; + parameter [15:0] RX_CTRL_OVRD_LANE0 = 16'h000C; + parameter [15:0] RX_CTRL_OVRD_LANE1 = 16'h000C; + parameter [15:0] RX_CTRL_OVRD_LANE2 = 16'h000C; + parameter [15:0] RX_CTRL_OVRD_LANE3 = 16'h000C; + parameter integer RX_FABRIC_WIDTH0 = 6466; + parameter integer RX_FABRIC_WIDTH1 = 6466; + parameter integer RX_FABRIC_WIDTH2 = 6466; + parameter integer RX_FABRIC_WIDTH3 = 6466; + parameter [15:0] RX_LOOP_CTRL_LANE0 = 16'h007F; + parameter [15:0] RX_LOOP_CTRL_LANE1 = 16'h007F; + parameter [15:0] RX_LOOP_CTRL_LANE2 = 16'h007F; + parameter [15:0] RX_LOOP_CTRL_LANE3 = 16'h007F; + parameter [15:0] RX_MVAL0_LANE0 = 16'h0000; + parameter [15:0] RX_MVAL0_LANE1 = 16'h0000; + parameter [15:0] RX_MVAL0_LANE2 = 16'h0000; + parameter [15:0] RX_MVAL0_LANE3 = 16'h0000; + parameter [15:0] RX_MVAL1_LANE0 = 16'h0000; + parameter [15:0] RX_MVAL1_LANE1 = 16'h0000; + parameter [15:0] RX_MVAL1_LANE2 = 16'h0000; + parameter [15:0] RX_MVAL1_LANE3 = 16'h0000; + parameter [15:0] RX_P0S_CTRL = 16'h1206; + parameter [15:0] RX_P0_CTRL = 16'h11F0; + parameter [15:0] RX_P1_CTRL = 16'h120F; + parameter [15:0] RX_P2_CTRL = 16'h0E0F; + parameter [15:0] RX_PI_CTRL0 = 16'hD2F0; + parameter [15:0] RX_PI_CTRL1 = 16'h0080; + parameter integer SIM_GTHRESET_SPEEDUP = 1; + parameter SIM_VERSION = "1.0"; + parameter [15:0] SLICE_CFG = 16'h0000; + parameter [15:0] SLICE_NOISE_CTRL_0_LANE01 = 16'h0000; + parameter [15:0] SLICE_NOISE_CTRL_0_LANE23 = 16'h0000; + parameter [15:0] SLICE_NOISE_CTRL_1_LANE01 = 16'h0000; + parameter [15:0] SLICE_NOISE_CTRL_1_LANE23 = 16'h0000; + parameter [15:0] SLICE_NOISE_CTRL_2_LANE01 = 16'h7FFF; + parameter [15:0] SLICE_NOISE_CTRL_2_LANE23 = 16'h7FFF; + parameter [15:0] SLICE_TX_RESET_LANE01 = 16'h0000; + parameter [15:0] SLICE_TX_RESET_LANE23 = 16'h0000; + parameter [15:0] TERM_CTRL_LANE0 = 16'h5007; + parameter [15:0] TERM_CTRL_LANE1 = 16'h5007; + parameter [15:0] TERM_CTRL_LANE2 = 16'h5007; + parameter [15:0] TERM_CTRL_LANE3 = 16'h5007; + parameter [15:0] TX_CFG0_LANE0 = 16'h203D; + parameter [15:0] TX_CFG0_LANE1 = 16'h203D; + parameter [15:0] TX_CFG0_LANE2 = 16'h203D; + parameter [15:0] TX_CFG0_LANE3 = 16'h203D; + parameter [15:0] TX_CFG1_LANE0 = 16'h0F00; + parameter [15:0] TX_CFG1_LANE1 = 16'h0F00; + parameter [15:0] TX_CFG1_LANE2 = 16'h0F00; + parameter [15:0] TX_CFG1_LANE3 = 16'h0F00; + parameter [15:0] TX_CFG2_LANE0 = 16'h0081; + parameter [15:0] TX_CFG2_LANE1 = 16'h0081; + parameter [15:0] TX_CFG2_LANE2 = 16'h0081; + parameter [15:0] TX_CFG2_LANE3 = 16'h0081; + parameter [15:0] TX_CLK_SEL0_LANE0 = 16'h2121; + parameter [15:0] TX_CLK_SEL0_LANE1 = 16'h2121; + parameter [15:0] TX_CLK_SEL0_LANE2 = 16'h2121; + parameter [15:0] TX_CLK_SEL0_LANE3 = 16'h2121; + parameter [15:0] TX_CLK_SEL1_LANE0 = 16'h2121; + parameter [15:0] TX_CLK_SEL1_LANE1 = 16'h2121; + parameter [15:0] TX_CLK_SEL1_LANE2 = 16'h2121; + parameter [15:0] TX_CLK_SEL1_LANE3 = 16'h2121; + parameter [15:0] TX_DISABLE_LANE0 = 16'h0000; + parameter [15:0] TX_DISABLE_LANE1 = 16'h0000; + parameter [15:0] TX_DISABLE_LANE2 = 16'h0000; + parameter [15:0] TX_DISABLE_LANE3 = 16'h0000; + parameter integer TX_FABRIC_WIDTH0 = 6466; + parameter integer TX_FABRIC_WIDTH1 = 6466; + parameter integer TX_FABRIC_WIDTH2 = 6466; + parameter integer TX_FABRIC_WIDTH3 = 6466; + parameter [15:0] TX_P0P0S_CTRL = 16'h060C; + parameter [15:0] TX_P1P2_CTRL = 16'h0C39; + parameter [15:0] TX_PREEMPH_LANE0 = 16'h00A1; + parameter [15:0] TX_PREEMPH_LANE1 = 16'h00A1; + parameter [15:0] TX_PREEMPH_LANE2 = 16'h00A1; + parameter [15:0] TX_PREEMPH_LANE3 = 16'h00A1; + parameter [15:0] TX_PWR_RATE_OVRD_LANE0 = 16'h0060; + parameter [15:0] TX_PWR_RATE_OVRD_LANE1 = 16'h0060; + parameter [15:0] TX_PWR_RATE_OVRD_LANE2 = 16'h0060; + parameter [15:0] TX_PWR_RATE_OVRD_LANE3 = 16'h0060; + output DRDY; + output GTHINITDONE; + output MGMTPCSRDACK; + output RXCTRLACK0; + output RXCTRLACK1; + output RXCTRLACK2; + output RXCTRLACK3; + output RXDATATAP0; + output RXDATATAP1; + output RXDATATAP2; + output RXDATATAP3; + output RXPCSCLKSMPL0; + output RXPCSCLKSMPL1; + output RXPCSCLKSMPL2; + output RXPCSCLKSMPL3; + output RXUSERCLKOUT0; + output RXUSERCLKOUT1; + output RXUSERCLKOUT2; + output RXUSERCLKOUT3; + output TSTPATH; + output TSTREFCLKFAB; + output TSTREFCLKOUT; + output TXCTRLACK0; + output TXCTRLACK1; + output TXCTRLACK2; + output TXCTRLACK3; + output TXDATATAP10; + output TXDATATAP11; + output TXDATATAP12; + output TXDATATAP13; + output TXDATATAP20; + output TXDATATAP21; + output TXDATATAP22; + output TXDATATAP23; + output TXN0; + output TXN1; + output TXN2; + output TXN3; + output TXP0; + output TXP1; + output TXP2; + output TXP3; + output TXPCSCLKSMPL0; + output TXPCSCLKSMPL1; + output TXPCSCLKSMPL2; + output TXPCSCLKSMPL3; + output TXUSERCLKOUT0; + output TXUSERCLKOUT1; + output TXUSERCLKOUT2; + output TXUSERCLKOUT3; + output [15:0] DRPDO; + output [15:0] MGMTPCSRDDATA; + output [63:0] RXDATA0; + output [63:0] RXDATA1; + output [63:0] RXDATA2; + output [63:0] RXDATA3; + output [7:0] RXCODEERR0; + output [7:0] RXCODEERR1; + output [7:0] RXCODEERR2; + output [7:0] RXCODEERR3; + output [7:0] RXCTRL0; + output [7:0] RXCTRL1; + output [7:0] RXCTRL2; + output [7:0] RXCTRL3; + output [7:0] RXDISPERR0; + output [7:0] RXDISPERR1; + output [7:0] RXDISPERR2; + output [7:0] RXDISPERR3; + output [7:0] RXVALID0; + output [7:0] RXVALID1; + output [7:0] RXVALID2; + output [7:0] RXVALID3; + input DCLK; + input DEN; + input DFETRAINCTRL0; + input DFETRAINCTRL1; + input DFETRAINCTRL2; + input DFETRAINCTRL3; + input DISABLEDRP; + input DWE; + input GTHINIT; + input GTHRESET; + input GTHX2LANE01; + input GTHX2LANE23; + input GTHX4LANE; + input MGMTPCSREGRD; + input MGMTPCSREGWR; + input POWERDOWN0; + input POWERDOWN1; + input POWERDOWN2; + input POWERDOWN3; + input REFCLK; + input RXBUFRESET0; + input RXBUFRESET1; + input RXBUFRESET2; + input RXBUFRESET3; + input RXENCOMMADET0; + input RXENCOMMADET1; + input RXENCOMMADET2; + input RXENCOMMADET3; + input RXN0; + input RXN1; + input RXN2; + input RXN3; + input RXP0; + input RXP1; + input RXP2; + input RXP3; + input RXPOLARITY0; + input RXPOLARITY1; + input RXPOLARITY2; + input RXPOLARITY3; + input RXSLIP0; + input RXSLIP1; + input RXSLIP2; + input RXSLIP3; + input RXUSERCLKIN0; + input RXUSERCLKIN1; + input RXUSERCLKIN2; + input RXUSERCLKIN3; + input TXBUFRESET0; + input TXBUFRESET1; + input TXBUFRESET2; + input TXBUFRESET3; + input TXDEEMPH0; + input TXDEEMPH1; + input TXDEEMPH2; + input TXDEEMPH3; + input TXUSERCLKIN0; + input TXUSERCLKIN1; + input TXUSERCLKIN2; + input TXUSERCLKIN3; + input [15:0] DADDR; + input [15:0] DI; + input [15:0] MGMTPCSREGADDR; + input [15:0] MGMTPCSWRDATA; + input [1:0] RXPOWERDOWN0; + input [1:0] RXPOWERDOWN1; + input [1:0] RXPOWERDOWN2; + input [1:0] RXPOWERDOWN3; + input [1:0] RXRATE0; + input [1:0] RXRATE1; + input [1:0] RXRATE2; + input [1:0] RXRATE3; + input [1:0] TXPOWERDOWN0; + input [1:0] TXPOWERDOWN1; + input [1:0] TXPOWERDOWN2; + input [1:0] TXPOWERDOWN3; + input [1:0] TXRATE0; + input [1:0] TXRATE1; + input [1:0] TXRATE2; + input [1:0] TXRATE3; + input [2:0] PLLREFCLKSEL; + input [2:0] SAMPLERATE0; + input [2:0] SAMPLERATE1; + input [2:0] SAMPLERATE2; + input [2:0] SAMPLERATE3; + input [2:0] TXMARGIN0; + input [2:0] TXMARGIN1; + input [2:0] TXMARGIN2; + input [2:0] TXMARGIN3; + input [3:0] MGMTPCSLANESEL; + input [4:0] MGMTPCSMMDADDR; + input [5:0] PLLPCSCLKDIV; + input [63:0] TXDATA0; + input [63:0] TXDATA1; + input [63:0] TXDATA2; + input [63:0] TXDATA3; + input [7:0] TXCTRL0; + input [7:0] TXCTRL1; + input [7:0] TXCTRL2; + input [7:0] TXCTRL3; + input [7:0] TXDATAMSB0; + input [7:0] TXDATAMSB1; + input [7:0] TXDATAMSB2; + input [7:0] TXDATAMSB3; +endmodule + +module GTXE1 (...); + parameter AC_CAP_DIS = "TRUE"; + parameter integer ALIGN_COMMA_WORD = 1; + parameter [1:0] BGTEST_CFG = 2'b00; + parameter [16:0] BIAS_CFG = 17'h00000; + parameter [4:0] CDR_PH_ADJ_TIME = 5'b10100; + parameter integer CHAN_BOND_1_MAX_SKEW = 7; + parameter integer CHAN_BOND_2_MAX_SKEW = 1; + parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; + parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0110111100; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100111100; + parameter [4:0] CHAN_BOND_SEQ_2_CFG = 5'b00000; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; + parameter CHAN_BOND_SEQ_2_USE = "FALSE"; + parameter integer CHAN_BOND_SEQ_LEN = 1; + parameter CLK_CORRECT_USE = "TRUE"; + parameter integer CLK_COR_ADJ_LEN = 1; + parameter integer CLK_COR_DET_LEN = 1; + parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE"; + parameter CLK_COR_KEEP_IDLE = "FALSE"; + parameter integer CLK_COR_MAX_LAT = 20; + parameter integer CLK_COR_MIN_LAT = 18; + parameter CLK_COR_PRECEDENCE = "TRUE"; + parameter integer CLK_COR_REPEAT_WAIT = 0; + parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; + parameter CLK_COR_SEQ_2_USE = "FALSE"; + parameter [1:0] CM_TRIM = 2'b01; + parameter [9:0] COMMA_10B_ENABLE = 10'b1111111111; + parameter COMMA_DOUBLE = "FALSE"; + parameter [3:0] COM_BURST_VAL = 4'b1111; + parameter DEC_MCOMMA_DETECT = "TRUE"; + parameter DEC_PCOMMA_DETECT = "TRUE"; + parameter DEC_VALID_COMMA_ONLY = "TRUE"; + parameter [4:0] DFE_CAL_TIME = 5'b01100; + parameter [7:0] DFE_CFG = 8'b00011011; + parameter [2:0] GEARBOX_ENDEC = 3'b000; + parameter GEN_RXUSRCLK = "TRUE"; + parameter GEN_TXUSRCLK = "TRUE"; + parameter GTX_CFG_PWRUP = "TRUE"; + parameter [9:0] MCOMMA_10B_VALUE = 10'b1010000011; + parameter MCOMMA_DETECT = "TRUE"; + parameter [2:0] OOBDETECT_THRESHOLD = 3'b011; + parameter PCI_EXPRESS_MODE = "FALSE"; + parameter [9:0] PCOMMA_10B_VALUE = 10'b0101111100; + parameter PCOMMA_DETECT = "TRUE"; + parameter PMA_CAS_CLK_EN = "FALSE"; + parameter [26:0] PMA_CDR_SCAN = 27'h640404C; + parameter [75:0] PMA_CFG = 76'h0040000040000000003; + parameter [6:0] PMA_RXSYNC_CFG = 7'h00; + parameter [24:0] PMA_RX_CFG = 25'h05CE048; + parameter [19:0] PMA_TX_CFG = 20'h00082; + parameter [9:0] POWER_SAVE = 10'b0000110100; + parameter RCV_TERM_GND = "FALSE"; + parameter RCV_TERM_VTTRX = "TRUE"; + parameter RXGEARBOX_USE = "FALSE"; + parameter [23:0] RXPLL_COM_CFG = 24'h21680A; + parameter [7:0] RXPLL_CP_CFG = 8'h00; + parameter integer RXPLL_DIVSEL45_FB = 5; + parameter integer RXPLL_DIVSEL_FB = 2; + parameter integer RXPLL_DIVSEL_OUT = 1; + parameter integer RXPLL_DIVSEL_REF = 1; + parameter [2:0] RXPLL_LKDET_CFG = 3'b111; + parameter [0:0] RXPRBSERR_LOOPBACK = 1'b0; + parameter RXRECCLK_CTRL = "RXRECCLKPCS"; + parameter [9:0] RXRECCLK_DLY = 10'b0000000000; + parameter [15:0] RXUSRCLK_DLY = 16'h0000; + parameter RX_BUFFER_USE = "TRUE"; + parameter integer RX_CLK25_DIVIDER = 6; + parameter integer RX_DATA_WIDTH = 20; + parameter RX_DECODE_SEQ_MATCH = "TRUE"; + parameter [3:0] RX_DLYALIGN_CTRINC = 4'b0100; + parameter [4:0] RX_DLYALIGN_EDGESET = 5'b00110; + parameter [3:0] RX_DLYALIGN_LPFINC = 4'b0111; + parameter [2:0] RX_DLYALIGN_MONSEL = 3'b000; + parameter [7:0] RX_DLYALIGN_OVRDSETTING = 8'b00000000; + parameter RX_EN_IDLE_HOLD_CDR = "FALSE"; + parameter RX_EN_IDLE_HOLD_DFE = "TRUE"; + parameter RX_EN_IDLE_RESET_BUF = "TRUE"; + parameter RX_EN_IDLE_RESET_FR = "TRUE"; + parameter RX_EN_IDLE_RESET_PH = "TRUE"; + parameter RX_EN_MODE_RESET_BUF = "TRUE"; + parameter RX_EN_RATE_RESET_BUF = "TRUE"; + parameter RX_EN_REALIGN_RESET_BUF = "FALSE"; + parameter RX_EN_REALIGN_RESET_BUF2 = "FALSE"; + parameter [7:0] RX_EYE_OFFSET = 8'h4C; + parameter [1:0] RX_EYE_SCANMODE = 2'b00; + parameter RX_FIFO_ADDR_MODE = "FULL"; + parameter [3:0] RX_IDLE_HI_CNT = 4'b1000; + parameter [3:0] RX_IDLE_LO_CNT = 4'b0000; + parameter RX_LOSS_OF_SYNC_FSM = "FALSE"; + parameter integer RX_LOS_INVALID_INCR = 1; + parameter integer RX_LOS_THRESHOLD = 4; + parameter RX_OVERSAMPLE_MODE = "FALSE"; + parameter integer RX_SLIDE_AUTO_WAIT = 5; + parameter RX_SLIDE_MODE = "OFF"; + parameter RX_XCLK_SEL = "RXREC"; + parameter integer SAS_MAX_COMSAS = 52; + parameter integer SAS_MIN_COMSAS = 40; + parameter [2:0] SATA_BURST_VAL = 3'b100; + parameter [2:0] SATA_IDLE_VAL = 3'b100; + parameter integer SATA_MAX_BURST = 7; + parameter integer SATA_MAX_INIT = 22; + parameter integer SATA_MAX_WAKE = 7; + parameter integer SATA_MIN_BURST = 4; + parameter integer SATA_MIN_INIT = 12; + parameter integer SATA_MIN_WAKE = 4; + parameter SHOW_REALIGN_COMMA = "TRUE"; + parameter integer SIM_GTXRESET_SPEEDUP = 1; + parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; + parameter [2:0] SIM_RXREFCLK_SOURCE = 3'b000; + parameter [2:0] SIM_TXREFCLK_SOURCE = 3'b000; + parameter SIM_TX_ELEC_IDLE_LEVEL = "X"; + parameter SIM_VERSION = "2.0"; + parameter [4:0] TERMINATION_CTRL = 5'b10100; + parameter TERMINATION_OVRD = "FALSE"; + parameter [11:0] TRANS_TIME_FROM_P2 = 12'h03C; + parameter [7:0] TRANS_TIME_NON_P2 = 8'h19; + parameter [7:0] TRANS_TIME_RATE = 8'h0E; + parameter [9:0] TRANS_TIME_TO_P2 = 10'h064; + parameter [31:0] TST_ATTR = 32'h00000000; + parameter TXDRIVE_LOOPBACK_HIZ = "FALSE"; + parameter TXDRIVE_LOOPBACK_PD = "FALSE"; + parameter TXGEARBOX_USE = "FALSE"; + parameter TXOUTCLK_CTRL = "TXOUTCLKPCS"; + parameter [9:0] TXOUTCLK_DLY = 10'b0000000000; + parameter [23:0] TXPLL_COM_CFG = 24'h21680A; + parameter [7:0] TXPLL_CP_CFG = 8'h00; + parameter integer TXPLL_DIVSEL45_FB = 5; + parameter integer TXPLL_DIVSEL_FB = 2; + parameter integer TXPLL_DIVSEL_OUT = 1; + parameter integer TXPLL_DIVSEL_REF = 1; + parameter [2:0] TXPLL_LKDET_CFG = 3'b111; + parameter [1:0] TXPLL_SATA = 2'b00; + parameter TX_BUFFER_USE = "TRUE"; + parameter [5:0] TX_BYTECLK_CFG = 6'h00; + parameter integer TX_CLK25_DIVIDER = 6; + parameter TX_CLK_SOURCE = "RXPLL"; + parameter integer TX_DATA_WIDTH = 20; + parameter [4:0] TX_DEEMPH_0 = 5'b11010; + parameter [4:0] TX_DEEMPH_1 = 5'b10000; + parameter [13:0] TX_DETECT_RX_CFG = 14'h1832; + parameter [3:0] TX_DLYALIGN_CTRINC = 4'b0100; + parameter [3:0] TX_DLYALIGN_LPFINC = 4'b0110; + parameter [2:0] TX_DLYALIGN_MONSEL = 3'b000; + parameter [7:0] TX_DLYALIGN_OVRDSETTING = 8'b10000000; + parameter TX_DRIVE_MODE = "DIRECT"; + parameter TX_EN_RATE_RESET_BUF = "TRUE"; + parameter [2:0] TX_IDLE_ASSERT_DELAY = 3'b100; + parameter [2:0] TX_IDLE_DEASSERT_DELAY = 3'b010; + parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; + parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; + parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; + parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; + parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; + parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; + parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; + parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; + parameter TX_OVERSAMPLE_MODE = "FALSE"; + parameter [0:0] TX_PMADATA_OPT = 1'b0; + parameter [1:0] TX_TDCC_CFG = 2'b11; + parameter [5:0] TX_USRCLK_CFG = 6'h00; + parameter TX_XCLK_SEL = "TXUSR"; + output COMFINISH; + output COMINITDET; + output COMSASDET; + output COMWAKEDET; + output DRDY; + output PHYSTATUS; + output RXBYTEISALIGNED; + output RXBYTEREALIGN; + output RXCHANBONDSEQ; + output RXCHANISALIGNED; + output RXCHANREALIGN; + output RXCOMMADET; + output RXDATAVALID; + output RXELECIDLE; + output RXHEADERVALID; + output RXOVERSAMPLEERR; + output RXPLLLKDET; + output RXPRBSERR; + output RXRATEDONE; + output RXRECCLK; + output RXRECCLKPCS; + output RXRESETDONE; + output RXSTARTOFSEQ; + output RXVALID; + output TXGEARBOXREADY; + output TXN; + output TXOUTCLK; + output TXOUTCLKPCS; + output TXP; + output TXPLLLKDET; + output TXRATEDONE; + output TXRESETDONE; + output [15:0] DRPDO; + output [1:0] MGTREFCLKFAB; + output [1:0] RXLOSSOFSYNC; + output [1:0] TXBUFSTATUS; + output [2:0] DFESENSCAL; + output [2:0] RXBUFSTATUS; + output [2:0] RXCLKCORCNT; + output [2:0] RXHEADER; + output [2:0] RXSTATUS; + output [31:0] RXDATA; + output [3:0] DFETAP3MONITOR; + output [3:0] DFETAP4MONITOR; + output [3:0] RXCHARISCOMMA; + output [3:0] RXCHARISK; + output [3:0] RXCHBONDO; + output [3:0] RXDISPERR; + output [3:0] RXNOTINTABLE; + output [3:0] RXRUNDISP; + output [3:0] TXKERR; + output [3:0] TXRUNDISP; + output [4:0] DFEEYEDACMON; + output [4:0] DFETAP1MONITOR; + output [4:0] DFETAP2MONITOR; + output [5:0] DFECLKDLYADJMON; + output [7:0] RXDLYALIGNMONITOR; + output [7:0] TXDLYALIGNMONITOR; + output [9:0] TSTOUT; + input DCLK; + input DEN; + input DFEDLYOVRD; + input DFETAPOVRD; + input DWE; + input GATERXELECIDLE; + input GREFCLKRX; + input GREFCLKTX; + input GTXRXRESET; + input GTXTXRESET; + input IGNORESIGDET; + input PERFCLKRX; + input PERFCLKTX; + input PLLRXRESET; + input PLLTXRESET; + input PRBSCNTRESET; + input RXBUFRESET; + input RXCDRRESET; + input RXCHBONDMASTER; + input RXCHBONDSLAVE; + input RXCOMMADETUSE; + input RXDEC8B10BUSE; + input RXDLYALIGNDISABLE; + input RXDLYALIGNMONENB; + input RXDLYALIGNOVERRIDE; + input RXDLYALIGNRESET; + input RXDLYALIGNSWPPRECURB; + input RXDLYALIGNUPDSW; + input RXENCHANSYNC; + input RXENMCOMMAALIGN; + input RXENPCOMMAALIGN; + input RXENPMAPHASEALIGN; + input RXENSAMPLEALIGN; + input RXGEARBOXSLIP; + input RXN; + input RXP; + input RXPLLLKDETEN; + input RXPLLPOWERDOWN; + input RXPMASETPHASE; + input RXPOLARITY; + input RXRESET; + input RXSLIDE; + input RXUSRCLK2; + input RXUSRCLK; + input TSTCLK0; + input TSTCLK1; + input TXCOMINIT; + input TXCOMSAS; + input TXCOMWAKE; + input TXDEEMPH; + input TXDETECTRX; + input TXDLYALIGNDISABLE; + input TXDLYALIGNMONENB; + input TXDLYALIGNOVERRIDE; + input TXDLYALIGNRESET; + input TXDLYALIGNUPDSW; + input TXELECIDLE; + input TXENC8B10BUSE; + input TXENPMAPHASEALIGN; + input TXINHIBIT; + input TXPDOWNASYNCH; + input TXPLLLKDETEN; + input TXPLLPOWERDOWN; + input TXPMASETPHASE; + input TXPOLARITY; + input TXPRBSFORCEERR; + input TXRESET; + input TXSTARTSEQ; + input TXSWING; + input TXUSRCLK2; + input TXUSRCLK; + input USRCODEERR; + input [12:0] GTXTEST; + input [15:0] DI; + input [19:0] TSTIN; + input [1:0] MGTREFCLKRX; + input [1:0] MGTREFCLKTX; + input [1:0] NORTHREFCLKRX; + input [1:0] NORTHREFCLKTX; + input [1:0] RXPOWERDOWN; + input [1:0] RXRATE; + input [1:0] SOUTHREFCLKRX; + input [1:0] SOUTHREFCLKTX; + input [1:0] TXPOWERDOWN; + input [1:0] TXRATE; + input [2:0] LOOPBACK; + input [2:0] RXCHBONDLEVEL; + input [2:0] RXENPRBSTST; + input [2:0] RXPLLREFSELDY; + input [2:0] TXBUFDIFFCTRL; + input [2:0] TXENPRBSTST; + input [2:0] TXHEADER; + input [2:0] TXMARGIN; + input [2:0] TXPLLREFSELDY; + input [31:0] TXDATA; + input [3:0] DFETAP3; + input [3:0] DFETAP4; + input [3:0] RXCHBONDI; + input [3:0] TXBYPASS8B10B; + input [3:0] TXCHARDISPMODE; + input [3:0] TXCHARDISPVAL; + input [3:0] TXCHARISK; + input [3:0] TXDIFFCTRL; + input [3:0] TXPREEMPHASIS; + input [4:0] DFETAP1; + input [4:0] DFETAP2; + input [4:0] TXPOSTEMPHASIS; + input [5:0] DFECLKDLYADJ; + input [6:0] TXSEQUENCE; + input [7:0] DADDR; + input [9:0] RXEQMIX; +endmodule + +module IBUFDS_GTXE1 (...); + parameter CLKCM_CFG = "TRUE"; + parameter CLKRCV_TRST = "TRUE"; + parameter [9:0] REFCLKOUT_DLY = 10'b0000000000; + output O; + output ODIV2; + input CEB; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; +endmodule + +module IBUFDS_GTHE1 (...); + output O; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; +endmodule + +module GTHE2_CHANNEL (...); + parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; + parameter [0:0] ACJTAG_MODE = 1'b0; + parameter [0:0] ACJTAG_RESET = 1'b0; + parameter [19:0] ADAPT_CFG0 = 20'h00C10; + parameter ALIGN_COMMA_DOUBLE = "FALSE"; + parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; + parameter integer ALIGN_COMMA_WORD = 1; + parameter ALIGN_MCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; + parameter ALIGN_PCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; + parameter [0:0] A_RXOSCALRESET = 1'b0; + parameter CBCC_DATA_SOURCE_SEL = "DECODED"; + parameter [41:0] CFOK_CFG = 42'h24800040E80; + parameter [5:0] CFOK_CFG2 = 6'b100000; + parameter [5:0] CFOK_CFG3 = 6'b100000; + parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; + parameter integer CHAN_BOND_MAX_SKEW = 7; + parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; + parameter CHAN_BOND_SEQ_2_USE = "FALSE"; + parameter integer CHAN_BOND_SEQ_LEN = 1; + parameter CLK_CORRECT_USE = "TRUE"; + parameter CLK_COR_KEEP_IDLE = "FALSE"; + parameter integer CLK_COR_MAX_LAT = 20; + parameter integer CLK_COR_MIN_LAT = 18; + parameter CLK_COR_PRECEDENCE = "TRUE"; + parameter integer CLK_COR_REPEAT_WAIT = 0; + parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; + parameter CLK_COR_SEQ_2_USE = "FALSE"; + parameter integer CLK_COR_SEQ_LEN = 1; + parameter [28:0] CPLL_CFG = 29'h00BC07DC; + parameter integer CPLL_FBDIV = 4; + parameter integer CPLL_FBDIV_45 = 5; + parameter [23:0] CPLL_INIT_CFG = 24'h00001E; + parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; + parameter integer CPLL_REFCLK_DIV = 1; + parameter DEC_MCOMMA_DETECT = "TRUE"; + parameter DEC_PCOMMA_DETECT = "TRUE"; + parameter DEC_VALID_COMMA_ONLY = "TRUE"; + parameter [23:0] DMONITOR_CFG = 24'h000A00; + parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; + parameter [5:0] ES_CONTROL = 6'b000000; + parameter ES_ERRDET_EN = "FALSE"; + parameter ES_EYE_SCAN_EN = "TRUE"; + parameter [11:0] ES_HORZ_OFFSET = 12'h000; + parameter [9:0] ES_PMA_CFG = 10'b0000000000; + parameter [4:0] ES_PRESCALE = 5'b00000; + parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000; + parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000; + parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000; + parameter [8:0] ES_VERT_OFFSET = 9'b000000000; + parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; + parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; + parameter FTS_LANE_DESKEW_EN = "FALSE"; + parameter [2:0] GEARBOX_MODE = 3'b000; + parameter [0:0] IS_CLKRSVD0_INVERTED = 1'b0; + parameter [0:0] IS_CLKRSVD1_INVERTED = 1'b0; + parameter [0:0] IS_CPLLLOCKDETCLK_INVERTED = 1'b0; + parameter [0:0] IS_DMONITORCLK_INVERTED = 1'b0; + parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; + parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0; + parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0; + parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0; + parameter [0:0] IS_SIGVALIDCLK_INVERTED = 1'b0; + parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0; + parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0; + parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0; + parameter [0:0] LOOPBACK_CFG = 1'b0; + parameter [1:0] OUTREFCLK_SEL_INV = 2'b11; + parameter PCS_PCIE_EN = "FALSE"; + parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000; + parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; + parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; + parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; + parameter [31:0] PMA_RSV = 32'b00000000000000000000000010000000; + parameter [31:0] PMA_RSV2 = 32'b00011100000000000000000000001010; + parameter [1:0] PMA_RSV3 = 2'b00; + parameter [14:0] PMA_RSV4 = 15'b000000000001000; + parameter [3:0] PMA_RSV5 = 4'b0000; + parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0; + parameter [4:0] RXBUFRESET_TIME = 5'b00001; + parameter RXBUF_ADDR_MODE = "FULL"; + parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; + parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; + parameter RXBUF_EN = "TRUE"; + parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; + parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; + parameter RXBUF_RESET_ON_EIDLE = "FALSE"; + parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; + parameter integer RXBUF_THRESH_OVFLW = 61; + parameter RXBUF_THRESH_OVRD = "FALSE"; + parameter integer RXBUF_THRESH_UNDFLW = 4; + parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; + parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; + parameter [82:0] RXCDR_CFG = 83'h0002007FE2000C208001A; + parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; + parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; + parameter [5:0] RXCDR_LOCK_CFG = 6'b001001; + parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; + parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; + parameter [15:0] RXDLY_CFG = 16'h001F; + parameter [8:0] RXDLY_LCFG = 9'h030; + parameter [15:0] RXDLY_TAP_CFG = 16'h0000; + parameter RXGEARBOX_EN = "FALSE"; + parameter [4:0] RXISCANRESET_TIME = 5'b00001; + parameter [13:0] RXLPM_HF_CFG = 14'b00001000000000; + parameter [17:0] RXLPM_LF_CFG = 18'b001001000000000000; + parameter [6:0] RXOOB_CFG = 7'b0000110; + parameter RXOOB_CLK_CFG = "PMA"; + parameter [4:0] RXOSCALRESET_TIME = 5'b00011; + parameter [4:0] RXOSCALRESET_TIMEOUT = 5'b00000; + parameter integer RXOUT_DIV = 2; + parameter [4:0] RXPCSRESET_TIME = 5'b00001; + parameter [23:0] RXPHDLY_CFG = 24'h084020; + parameter [23:0] RXPH_CFG = 24'hC00002; + parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; + parameter [1:0] RXPI_CFG0 = 2'b00; + parameter [1:0] RXPI_CFG1 = 2'b00; + parameter [1:0] RXPI_CFG2 = 2'b00; + parameter [1:0] RXPI_CFG3 = 2'b00; + parameter [0:0] RXPI_CFG4 = 1'b0; + parameter [0:0] RXPI_CFG5 = 1'b0; + parameter [2:0] RXPI_CFG6 = 3'b100; + parameter [4:0] RXPMARESET_TIME = 5'b00011; + parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; + parameter integer RXSLIDE_AUTO_WAIT = 7; + parameter RXSLIDE_MODE = "OFF"; + parameter [0:0] RXSYNC_MULTILANE = 1'b0; + parameter [0:0] RXSYNC_OVRD = 1'b0; + parameter [0:0] RXSYNC_SKIP_DA = 1'b0; + parameter [23:0] RX_BIAS_CFG = 24'b000011000000000000010000; + parameter [5:0] RX_BUFFER_CFG = 6'b000000; + parameter integer RX_CLK25_DIV = 7; + parameter [0:0] RX_CLKMUX_PD = 1'b1; + parameter [1:0] RX_CM_SEL = 2'b11; + parameter [3:0] RX_CM_TRIM = 4'b0100; + parameter integer RX_DATA_WIDTH = 20; + parameter [5:0] RX_DDI_SEL = 6'b000000; + parameter [13:0] RX_DEBUG_CFG = 14'b00000000000000; + parameter RX_DEFER_RESET_BUF_EN = "TRUE"; + parameter [3:0] RX_DFELPM_CFG0 = 4'b0110; + parameter [0:0] RX_DFELPM_CFG1 = 1'b0; + parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1; + parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00; + parameter [2:0] RX_DFE_AGC_CFG1 = 3'b010; + parameter [3:0] RX_DFE_AGC_CFG2 = 4'b0000; + parameter [0:0] RX_DFE_AGC_OVRDEN = 1'b1; + parameter [22:0] RX_DFE_GAIN_CFG = 23'h0020C0; + parameter [11:0] RX_DFE_H2_CFG = 12'b000000000000; + parameter [11:0] RX_DFE_H3_CFG = 12'b000001000000; + parameter [10:0] RX_DFE_H4_CFG = 11'b00011100000; + parameter [10:0] RX_DFE_H5_CFG = 11'b00011100000; + parameter [10:0] RX_DFE_H6_CFG = 11'b00000100000; + parameter [10:0] RX_DFE_H7_CFG = 11'b00000100000; + parameter [32:0] RX_DFE_KL_CFG = 33'b000000000000000000000001100010000; + parameter [1:0] RX_DFE_KL_LPM_KH_CFG0 = 2'b01; + parameter [2:0] RX_DFE_KL_LPM_KH_CFG1 = 3'b010; + parameter [3:0] RX_DFE_KL_LPM_KH_CFG2 = 4'b0010; + parameter [0:0] RX_DFE_KL_LPM_KH_OVRDEN = 1'b1; + parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b10; + parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010; + parameter [3:0] RX_DFE_KL_LPM_KL_CFG2 = 4'b0010; + parameter [0:0] RX_DFE_KL_LPM_KL_OVRDEN = 1'b1; + parameter [15:0] RX_DFE_LPM_CFG = 16'h0080; + parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; + parameter [53:0] RX_DFE_ST_CFG = 54'h00E100000C003F; + parameter [16:0] RX_DFE_UT_CFG = 17'b00011100000000000; + parameter [16:0] RX_DFE_VP_CFG = 17'b00011101010100011; + parameter RX_DISPERR_SEQ_MATCH = "TRUE"; + parameter integer RX_INT_DATAWIDTH = 0; + parameter [12:0] RX_OS_CFG = 13'b0000010000000; + parameter integer RX_SIG_VALID_DLY = 10; + parameter RX_XCLK_SEL = "RXREC"; + parameter integer SAS_MAX_COM = 64; + parameter integer SAS_MIN_COM = 36; + parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; + parameter [2:0] SATA_BURST_VAL = 3'b100; + parameter SATA_CPLL_CFG = "VCO_3000MHZ"; + parameter [2:0] SATA_EIDLE_VAL = 3'b100; + parameter integer SATA_MAX_BURST = 8; + parameter integer SATA_MAX_INIT = 21; + parameter integer SATA_MAX_WAKE = 7; + parameter integer SATA_MIN_BURST = 4; + parameter integer SATA_MIN_INIT = 12; + parameter integer SATA_MIN_WAKE = 4; + parameter SHOW_REALIGN_COMMA = "TRUE"; + parameter [2:0] SIM_CPLLREFCLK_SEL = 3'b001; + parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X"; + parameter SIM_VERSION = "1.1"; + parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; + parameter [2:0] TERM_RCAL_OVRD = 3'b000; + parameter [7:0] TRANS_TIME_RATE = 8'h0E; + parameter [31:0] TST_RSV = 32'h00000000; + parameter TXBUF_EN = "TRUE"; + parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; + parameter [15:0] TXDLY_CFG = 16'h001F; + parameter [8:0] TXDLY_LCFG = 9'h030; + parameter [15:0] TXDLY_TAP_CFG = 16'h0000; + parameter TXGEARBOX_EN = "FALSE"; + parameter [0:0] TXOOB_CFG = 1'b0; + parameter integer TXOUT_DIV = 2; + parameter [4:0] TXPCSRESET_TIME = 5'b00001; + parameter [23:0] TXPHDLY_CFG = 24'h084020; + parameter [15:0] TXPH_CFG = 16'h0780; + parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; + parameter [1:0] TXPI_CFG0 = 2'b00; + parameter [1:0] TXPI_CFG1 = 2'b00; + parameter [1:0] TXPI_CFG2 = 2'b00; + parameter [0:0] TXPI_CFG3 = 1'b0; + parameter [0:0] TXPI_CFG4 = 1'b0; + parameter [2:0] TXPI_CFG5 = 3'b100; + parameter [0:0] TXPI_GREY_SEL = 1'b0; + parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; + parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; + parameter [7:0] TXPI_PPM_CFG = 8'b00000000; + parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; + parameter [4:0] TXPMARESET_TIME = 5'b00001; + parameter [0:0] TXSYNC_MULTILANE = 1'b0; + parameter [0:0] TXSYNC_OVRD = 1'b0; + parameter [0:0] TXSYNC_SKIP_DA = 1'b0; + parameter integer TX_CLK25_DIV = 7; + parameter [0:0] TX_CLKMUX_PD = 1'b1; + parameter integer TX_DATA_WIDTH = 20; + parameter [5:0] TX_DEEMPH0 = 6'b000000; + parameter [5:0] TX_DEEMPH1 = 6'b000000; + parameter TX_DRIVE_MODE = "DIRECT"; + parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; + parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; + parameter integer TX_INT_DATAWIDTH = 0; + parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; + parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; + parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; + parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; + parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; + parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; + parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; + parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; + parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; + parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; + parameter [0:0] TX_QPI_STATUS_EN = 1'b0; + parameter [13:0] TX_RXDETECT_CFG = 14'h1832; + parameter [16:0] TX_RXDETECT_PRECHARGE_TIME = 17'h00000; + parameter [2:0] TX_RXDETECT_REF = 3'b100; + parameter TX_XCLK_SEL = "TXUSR"; + parameter [0:0] UCODEER_CLR = 1'b0; + parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; + output CPLLFBCLKLOST; + output CPLLLOCK; + output CPLLREFCLKLOST; + output DRPRDY; + output EYESCANDATAERROR; + output GTHTXN; + output GTHTXP; + output GTREFCLKMONITOR; + output PHYSTATUS; + output RSOSINTDONE; + output RXBYTEISALIGNED; + output RXBYTEREALIGN; + output RXCDRLOCK; + output RXCHANBONDSEQ; + output RXCHANISALIGNED; + output RXCHANREALIGN; + output RXCOMINITDET; + output RXCOMMADET; + output RXCOMSASDET; + output RXCOMWAKEDET; + output RXDFESLIDETAPSTARTED; + output RXDFESLIDETAPSTROBEDONE; + output RXDFESLIDETAPSTROBESTARTED; + output RXDFESTADAPTDONE; + output RXDLYSRESETDONE; + output RXELECIDLE; + output RXOSINTSTARTED; + output RXOSINTSTROBEDONE; + output RXOSINTSTROBESTARTED; + output RXOUTCLK; + output RXOUTCLKFABRIC; + output RXOUTCLKPCS; + output RXPHALIGNDONE; + output RXPMARESETDONE; + output RXPRBSERR; + output RXQPISENN; + output RXQPISENP; + output RXRATEDONE; + output RXRESETDONE; + output RXSYNCDONE; + output RXSYNCOUT; + output RXVALID; + output TXCOMFINISH; + output TXDLYSRESETDONE; + output TXGEARBOXREADY; + output TXOUTCLK; + output TXOUTCLKFABRIC; + output TXOUTCLKPCS; + output TXPHALIGNDONE; + output TXPHINITDONE; + output TXPMARESETDONE; + output TXQPISENN; + output TXQPISENP; + output TXRATEDONE; + output TXRESETDONE; + output TXSYNCDONE; + output TXSYNCOUT; + output [14:0] DMONITOROUT; + output [15:0] DRPDO; + output [15:0] PCSRSVDOUT; + output [1:0] RXCLKCORCNT; + output [1:0] RXDATAVALID; + output [1:0] RXHEADERVALID; + output [1:0] RXSTARTOFSEQ; + output [1:0] TXBUFSTATUS; + output [2:0] RXBUFSTATUS; + output [2:0] RXSTATUS; + output [4:0] RXCHBONDO; + output [4:0] RXPHMONITOR; + output [4:0] RXPHSLIPMONITOR; + output [5:0] RXHEADER; + output [63:0] RXDATA; + output [6:0] RXMONITOROUT; + output [7:0] RXCHARISCOMMA; + output [7:0] RXCHARISK; + output [7:0] RXDISPERR; + output [7:0] RXNOTINTABLE; + input CFGRESET; + (* invertible_pin = "IS_CLKRSVD0_INVERTED" *) + input CLKRSVD0; + (* invertible_pin = "IS_CLKRSVD1_INVERTED" *) + input CLKRSVD1; + (* invertible_pin = "IS_CPLLLOCKDETCLK_INVERTED" *) + input CPLLLOCKDETCLK; + input CPLLLOCKEN; + input CPLLPD; + input CPLLRESET; + input DMONFIFORESET; + (* invertible_pin = "IS_DMONITORCLK_INVERTED" *) + input DMONITORCLK; + (* invertible_pin = "IS_DRPCLK_INVERTED" *) + input DRPCLK; + input DRPEN; + input DRPWE; + input EYESCANMODE; + input EYESCANRESET; + input EYESCANTRIGGER; + (* invertible_pin = "IS_GTGREFCLK_INVERTED" *) + input GTGREFCLK; + input GTHRXN; + input GTHRXP; + input GTNORTHREFCLK0; + input GTNORTHREFCLK1; + input GTREFCLK0; + input GTREFCLK1; + input GTRESETSEL; + input GTRXRESET; + input GTSOUTHREFCLK0; + input GTSOUTHREFCLK1; + input GTTXRESET; + input QPLLCLK; + input QPLLREFCLK; + input RESETOVRD; + input RX8B10BEN; + input RXBUFRESET; + input RXCDRFREQRESET; + input RXCDRHOLD; + input RXCDROVRDEN; + input RXCDRRESET; + input RXCDRRESETRSV; + input RXCHBONDEN; + input RXCHBONDMASTER; + input RXCHBONDSLAVE; + input RXCOMMADETEN; + input RXDDIEN; + input RXDFEAGCHOLD; + input RXDFEAGCOVRDEN; + input RXDFECM1EN; + input RXDFELFHOLD; + input RXDFELFOVRDEN; + input RXDFELPMRESET; + input RXDFESLIDETAPADAPTEN; + input RXDFESLIDETAPHOLD; + input RXDFESLIDETAPINITOVRDEN; + input RXDFESLIDETAPONLYADAPTEN; + input RXDFESLIDETAPOVRDEN; + input RXDFESLIDETAPSTROBE; + input RXDFETAP2HOLD; + input RXDFETAP2OVRDEN; + input RXDFETAP3HOLD; + input RXDFETAP3OVRDEN; + input RXDFETAP4HOLD; + input RXDFETAP4OVRDEN; + input RXDFETAP5HOLD; + input RXDFETAP5OVRDEN; + input RXDFETAP6HOLD; + input RXDFETAP6OVRDEN; + input RXDFETAP7HOLD; + input RXDFETAP7OVRDEN; + input RXDFEUTHOLD; + input RXDFEUTOVRDEN; + input RXDFEVPHOLD; + input RXDFEVPOVRDEN; + input RXDFEVSEN; + input RXDFEXYDEN; + input RXDLYBYPASS; + input RXDLYEN; + input RXDLYOVRDEN; + input RXDLYSRESET; + input RXGEARBOXSLIP; + input RXLPMEN; + input RXLPMHFHOLD; + input RXLPMHFOVRDEN; + input RXLPMLFHOLD; + input RXLPMLFKLOVRDEN; + input RXMCOMMAALIGNEN; + input RXOOBRESET; + input RXOSCALRESET; + input RXOSHOLD; + input RXOSINTEN; + input RXOSINTHOLD; + input RXOSINTNTRLEN; + input RXOSINTOVRDEN; + input RXOSINTSTROBE; + input RXOSINTTESTOVRDEN; + input RXOSOVRDEN; + input RXPCOMMAALIGNEN; + input RXPCSRESET; + input RXPHALIGN; + input RXPHALIGNEN; + input RXPHDLYPD; + input RXPHDLYRESET; + input RXPHOVRDEN; + input RXPMARESET; + input RXPOLARITY; + input RXPRBSCNTRESET; + input RXQPIEN; + input RXRATEMODE; + input RXSLIDE; + input RXSYNCALLIN; + input RXSYNCIN; + input RXSYNCMODE; + input RXUSERRDY; + (* invertible_pin = "IS_RXUSRCLK2_INVERTED" *) + input RXUSRCLK2; + (* invertible_pin = "IS_RXUSRCLK_INVERTED" *) + input RXUSRCLK; + input SETERRSTATUS; + (* invertible_pin = "IS_SIGVALIDCLK_INVERTED" *) + input SIGVALIDCLK; + input TX8B10BEN; + input TXCOMINIT; + input TXCOMSAS; + input TXCOMWAKE; + input TXDEEMPH; + input TXDETECTRX; + input TXDIFFPD; + input TXDLYBYPASS; + input TXDLYEN; + input TXDLYHOLD; + input TXDLYOVRDEN; + input TXDLYSRESET; + input TXDLYUPDOWN; + input TXELECIDLE; + input TXINHIBIT; + input TXPCSRESET; + input TXPDELECIDLEMODE; + input TXPHALIGN; + input TXPHALIGNEN; + input TXPHDLYPD; + input TXPHDLYRESET; + (* invertible_pin = "IS_TXPHDLYTSTCLK_INVERTED" *) + input TXPHDLYTSTCLK; + input TXPHINIT; + input TXPHOVRDEN; + input TXPIPPMEN; + input TXPIPPMOVRDEN; + input TXPIPPMPD; + input TXPIPPMSEL; + input TXPISOPD; + input TXPMARESET; + input TXPOLARITY; + input TXPOSTCURSORINV; + input TXPRBSFORCEERR; + input TXPRECURSORINV; + input TXQPIBIASEN; + input TXQPISTRONGPDOWN; + input TXQPIWEAKPUP; + input TXRATEMODE; + input TXSTARTSEQ; + input TXSWING; + input TXSYNCALLIN; + input TXSYNCIN; + input TXSYNCMODE; + input TXUSERRDY; + (* invertible_pin = "IS_TXUSRCLK2_INVERTED" *) + input TXUSRCLK2; + (* invertible_pin = "IS_TXUSRCLK_INVERTED" *) + input TXUSRCLK; + input [13:0] RXADAPTSELTEST; + input [15:0] DRPDI; + input [15:0] GTRSVD; + input [15:0] PCSRSVDIN; + input [19:0] TSTIN; + input [1:0] RXELECIDLEMODE; + input [1:0] RXMONITORSEL; + input [1:0] RXPD; + input [1:0] RXSYSCLKSEL; + input [1:0] TXPD; + input [1:0] TXSYSCLKSEL; + input [2:0] CPLLREFCLKSEL; + input [2:0] LOOPBACK; + input [2:0] RXCHBONDLEVEL; + input [2:0] RXOUTCLKSEL; + input [2:0] RXPRBSSEL; + input [2:0] RXRATE; + input [2:0] TXBUFDIFFCTRL; + input [2:0] TXHEADER; + input [2:0] TXMARGIN; + input [2:0] TXOUTCLKSEL; + input [2:0] TXPRBSSEL; + input [2:0] TXRATE; + input [3:0] RXOSINTCFG; + input [3:0] RXOSINTID0; + input [3:0] TXDIFFCTRL; + input [4:0] PCSRSVDIN2; + input [4:0] PMARSVDIN; + input [4:0] RXCHBONDI; + input [4:0] RXDFEAGCTRL; + input [4:0] RXDFESLIDETAP; + input [4:0] TXPIPPMSTEPSIZE; + input [4:0] TXPOSTCURSOR; + input [4:0] TXPRECURSOR; + input [5:0] RXDFESLIDETAPID; + input [63:0] TXDATA; + input [6:0] TXMAINCURSOR; + input [6:0] TXSEQUENCE; + input [7:0] TX8B10BBYPASS; + input [7:0] TXCHARDISPMODE; + input [7:0] TXCHARDISPVAL; + input [7:0] TXCHARISK; + input [8:0] DRPADDR; +endmodule + +module GTHE2_COMMON (...); + parameter [63:0] BIAS_CFG = 64'h0000040000001000; + parameter [31:0] COMMON_CFG = 32'h0000001C; + parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; + parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0; + parameter [0:0] IS_QPLLLOCKDETCLK_INVERTED = 1'b0; + parameter [26:0] QPLL_CFG = 27'h0480181; + parameter [3:0] QPLL_CLKOUT_CFG = 4'b0000; + parameter [5:0] QPLL_COARSE_FREQ_OVRD = 6'b010000; + parameter [0:0] QPLL_COARSE_FREQ_OVRD_EN = 1'b0; + parameter [9:0] QPLL_CP = 10'b0000011111; + parameter [0:0] QPLL_CP_MONITOR_EN = 1'b0; + parameter [0:0] QPLL_DMONITOR_SEL = 1'b0; + parameter [9:0] QPLL_FBDIV = 10'b0000000000; + parameter [0:0] QPLL_FBDIV_MONITOR_EN = 1'b0; + parameter [0:0] QPLL_FBDIV_RATIO = 1'b0; + parameter [23:0] QPLL_INIT_CFG = 24'h000006; + parameter [15:0] QPLL_LOCK_CFG = 16'h01E8; + parameter [3:0] QPLL_LPF = 4'b1111; + parameter integer QPLL_REFCLK_DIV = 2; + parameter [0:0] QPLL_RP_COMP = 1'b0; + parameter [1:0] QPLL_VTRL_RESET = 2'b00; + parameter [1:0] RCAL_CFG = 2'b00; + parameter [15:0] RSVD_ATTR0 = 16'h0000; + parameter [15:0] RSVD_ATTR1 = 16'h0000; + parameter [2:0] SIM_QPLLREFCLK_SEL = 3'b001; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter SIM_VERSION = "1.1"; + output DRPRDY; + output QPLLFBCLKLOST; + output QPLLLOCK; + output QPLLOUTCLK; + output QPLLOUTREFCLK; + output QPLLREFCLKLOST; + output REFCLKOUTMONITOR; + output [15:0] DRPDO; + output [15:0] PMARSVDOUT; + output [7:0] QPLLDMONITOR; + input BGBYPASSB; + input BGMONITORENB; + input BGPDB; + input BGRCALOVRDENB; + (* invertible_pin = "IS_DRPCLK_INVERTED" *) + input DRPCLK; + input DRPEN; + input DRPWE; + (* invertible_pin = "IS_GTGREFCLK_INVERTED" *) + input GTGREFCLK; + input GTNORTHREFCLK0; + input GTNORTHREFCLK1; + input GTREFCLK0; + input GTREFCLK1; + input GTSOUTHREFCLK0; + input GTSOUTHREFCLK1; + (* invertible_pin = "IS_QPLLLOCKDETCLK_INVERTED" *) + input QPLLLOCKDETCLK; + input QPLLLOCKEN; + input QPLLOUTRESET; + input QPLLPD; + input QPLLRESET; + input RCALENB; + input [15:0] DRPDI; + input [15:0] QPLLRSVD1; + input [2:0] QPLLREFCLKSEL; + input [4:0] BGRCALOVRD; + input [4:0] QPLLRSVD2; + input [7:0] DRPADDR; + input [7:0] PMARSVD; +endmodule + +module GTPE2_CHANNEL (...); + parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; + parameter [0:0] ACJTAG_MODE = 1'b0; + parameter [0:0] ACJTAG_RESET = 1'b0; + parameter [19:0] ADAPT_CFG0 = 20'b00000000000000000000; + parameter ALIGN_COMMA_DOUBLE = "FALSE"; + parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; + parameter integer ALIGN_COMMA_WORD = 1; + parameter ALIGN_MCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; + parameter ALIGN_PCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; + parameter CBCC_DATA_SOURCE_SEL = "DECODED"; + parameter [42:0] CFOK_CFG = 43'b1001001000000000000000001000000111010000000; + parameter [6:0] CFOK_CFG2 = 7'b0100000; + parameter [6:0] CFOK_CFG3 = 7'b0100000; + parameter [0:0] CFOK_CFG4 = 1'b0; + parameter [1:0] CFOK_CFG5 = 2'b00; + parameter [3:0] CFOK_CFG6 = 4'b0000; + parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; + parameter integer CHAN_BOND_MAX_SKEW = 7; + parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; + parameter CHAN_BOND_SEQ_2_USE = "FALSE"; + parameter integer CHAN_BOND_SEQ_LEN = 1; + parameter [0:0] CLK_COMMON_SWING = 1'b0; + parameter CLK_CORRECT_USE = "TRUE"; + parameter CLK_COR_KEEP_IDLE = "FALSE"; + parameter integer CLK_COR_MAX_LAT = 20; + parameter integer CLK_COR_MIN_LAT = 18; + parameter CLK_COR_PRECEDENCE = "TRUE"; + parameter integer CLK_COR_REPEAT_WAIT = 0; + parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; + parameter CLK_COR_SEQ_2_USE = "FALSE"; + parameter integer CLK_COR_SEQ_LEN = 1; + parameter DEC_MCOMMA_DETECT = "TRUE"; + parameter DEC_PCOMMA_DETECT = "TRUE"; + parameter DEC_VALID_COMMA_ONLY = "TRUE"; + parameter [23:0] DMONITOR_CFG = 24'h000A00; + parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; + parameter [5:0] ES_CONTROL = 6'b000000; + parameter ES_ERRDET_EN = "FALSE"; + parameter ES_EYE_SCAN_EN = "FALSE"; + parameter [11:0] ES_HORZ_OFFSET = 12'h010; + parameter [9:0] ES_PMA_CFG = 10'b0000000000; + parameter [4:0] ES_PRESCALE = 5'b00000; + parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000; + parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000; + parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000; + parameter [8:0] ES_VERT_OFFSET = 9'b000000000; + parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; + parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; + parameter FTS_LANE_DESKEW_EN = "FALSE"; + parameter [2:0] GEARBOX_MODE = 3'b000; + parameter [0:0] IS_CLKRSVD0_INVERTED = 1'b0; + parameter [0:0] IS_CLKRSVD1_INVERTED = 1'b0; + parameter [0:0] IS_DMONITORCLK_INVERTED = 1'b0; + parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; + parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0; + parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0; + parameter [0:0] IS_SIGVALIDCLK_INVERTED = 1'b0; + parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0; + parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0; + parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0; + parameter [0:0] LOOPBACK_CFG = 1'b0; + parameter [1:0] OUTREFCLK_SEL_INV = 2'b11; + parameter PCS_PCIE_EN = "FALSE"; + parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000; + parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; + parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; + parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; + parameter [0:0] PMA_LOOPBACK_CFG = 1'b0; + parameter [31:0] PMA_RSV = 32'h00000333; + parameter [31:0] PMA_RSV2 = 32'h00002050; + parameter [1:0] PMA_RSV3 = 2'b00; + parameter [3:0] PMA_RSV4 = 4'b0000; + parameter [0:0] PMA_RSV5 = 1'b0; + parameter [0:0] PMA_RSV6 = 1'b0; + parameter [0:0] PMA_RSV7 = 1'b0; + parameter [4:0] RXBUFRESET_TIME = 5'b00001; + parameter RXBUF_ADDR_MODE = "FULL"; + parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; + parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; + parameter RXBUF_EN = "TRUE"; + parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; + parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; + parameter RXBUF_RESET_ON_EIDLE = "FALSE"; + parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; + parameter integer RXBUF_THRESH_OVFLW = 61; + parameter RXBUF_THRESH_OVRD = "FALSE"; + parameter integer RXBUF_THRESH_UNDFLW = 4; + parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; + parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; + parameter [82:0] RXCDR_CFG = 83'h0000107FE406001041010; + parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; + parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; + parameter [5:0] RXCDR_LOCK_CFG = 6'b001001; + parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; + parameter [15:0] RXDLY_CFG = 16'h0010; + parameter [8:0] RXDLY_LCFG = 9'h020; + parameter [15:0] RXDLY_TAP_CFG = 16'h0000; + parameter RXGEARBOX_EN = "FALSE"; + parameter [4:0] RXISCANRESET_TIME = 5'b00001; + parameter [6:0] RXLPMRESET_TIME = 7'b0001111; + parameter [0:0] RXLPM_BIAS_STARTUP_DISABLE = 1'b0; + parameter [3:0] RXLPM_CFG = 4'b0110; + parameter [0:0] RXLPM_CFG1 = 1'b0; + parameter [0:0] RXLPM_CM_CFG = 1'b0; + parameter [8:0] RXLPM_GC_CFG = 9'b111100010; + parameter [2:0] RXLPM_GC_CFG2 = 3'b001; + parameter [13:0] RXLPM_HF_CFG = 14'b00001111110000; + parameter [4:0] RXLPM_HF_CFG2 = 5'b01010; + parameter [3:0] RXLPM_HF_CFG3 = 4'b0000; + parameter [0:0] RXLPM_HOLD_DURING_EIDLE = 1'b0; + parameter [0:0] RXLPM_INCM_CFG = 1'b0; + parameter [0:0] RXLPM_IPCM_CFG = 1'b0; + parameter [17:0] RXLPM_LF_CFG = 18'b000000001111110000; + parameter [4:0] RXLPM_LF_CFG2 = 5'b01010; + parameter [2:0] RXLPM_OSINT_CFG = 3'b100; + parameter [6:0] RXOOB_CFG = 7'b0000110; + parameter RXOOB_CLK_CFG = "PMA"; + parameter [4:0] RXOSCALRESET_TIME = 5'b00011; + parameter [4:0] RXOSCALRESET_TIMEOUT = 5'b00000; + parameter integer RXOUT_DIV = 2; + parameter [4:0] RXPCSRESET_TIME = 5'b00001; + parameter [23:0] RXPHDLY_CFG = 24'h084000; + parameter [23:0] RXPH_CFG = 24'hC00002; + parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; + parameter [2:0] RXPI_CFG0 = 3'b000; + parameter [0:0] RXPI_CFG1 = 1'b0; + parameter [0:0] RXPI_CFG2 = 1'b0; + parameter [4:0] RXPMARESET_TIME = 5'b00011; + parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; + parameter integer RXSLIDE_AUTO_WAIT = 7; + parameter RXSLIDE_MODE = "OFF"; + parameter [0:0] RXSYNC_MULTILANE = 1'b0; + parameter [0:0] RXSYNC_OVRD = 1'b0; + parameter [0:0] RXSYNC_SKIP_DA = 1'b0; + parameter [15:0] RX_BIAS_CFG = 16'b0000111100110011; + parameter [5:0] RX_BUFFER_CFG = 6'b000000; + parameter integer RX_CLK25_DIV = 7; + parameter [0:0] RX_CLKMUX_EN = 1'b1; + parameter [1:0] RX_CM_SEL = 2'b11; + parameter [3:0] RX_CM_TRIM = 4'b0100; + parameter integer RX_DATA_WIDTH = 20; + parameter [5:0] RX_DDI_SEL = 6'b000000; + parameter [13:0] RX_DEBUG_CFG = 14'b00000000000000; + parameter RX_DEFER_RESET_BUF_EN = "TRUE"; + parameter RX_DISPERR_SEQ_MATCH = "TRUE"; + parameter [12:0] RX_OS_CFG = 13'b0001111110000; + parameter integer RX_SIG_VALID_DLY = 10; + parameter RX_XCLK_SEL = "RXREC"; + parameter integer SAS_MAX_COM = 64; + parameter integer SAS_MIN_COM = 36; + parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; + parameter [2:0] SATA_BURST_VAL = 3'b100; + parameter [2:0] SATA_EIDLE_VAL = 3'b100; + parameter integer SATA_MAX_BURST = 8; + parameter integer SATA_MAX_INIT = 21; + parameter integer SATA_MAX_WAKE = 7; + parameter integer SATA_MIN_BURST = 4; + parameter integer SATA_MIN_INIT = 12; + parameter integer SATA_MIN_WAKE = 4; + parameter SATA_PLL_CFG = "VCO_3000MHZ"; + parameter SHOW_REALIGN_COMMA = "TRUE"; + parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X"; + parameter SIM_VERSION = "1.0"; + parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; + parameter [2:0] TERM_RCAL_OVRD = 3'b000; + parameter [7:0] TRANS_TIME_RATE = 8'h0E; + parameter [31:0] TST_RSV = 32'h00000000; + parameter TXBUF_EN = "TRUE"; + parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; + parameter [15:0] TXDLY_CFG = 16'h0010; + parameter [8:0] TXDLY_LCFG = 9'h020; + parameter [15:0] TXDLY_TAP_CFG = 16'h0000; + parameter TXGEARBOX_EN = "FALSE"; + parameter [0:0] TXOOB_CFG = 1'b0; + parameter integer TXOUT_DIV = 2; + parameter [4:0] TXPCSRESET_TIME = 5'b00001; + parameter [23:0] TXPHDLY_CFG = 24'h084000; + parameter [15:0] TXPH_CFG = 16'h0400; + parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; + parameter [1:0] TXPI_CFG0 = 2'b00; + parameter [1:0] TXPI_CFG1 = 2'b00; + parameter [1:0] TXPI_CFG2 = 2'b00; + parameter [0:0] TXPI_CFG3 = 1'b0; + parameter [0:0] TXPI_CFG4 = 1'b0; + parameter [2:0] TXPI_CFG5 = 3'b000; + parameter [0:0] TXPI_GREY_SEL = 1'b0; + parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; + parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; + parameter [7:0] TXPI_PPM_CFG = 8'b00000000; + parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; + parameter [4:0] TXPMARESET_TIME = 5'b00001; + parameter [0:0] TXSYNC_MULTILANE = 1'b0; + parameter [0:0] TXSYNC_OVRD = 1'b0; + parameter [0:0] TXSYNC_SKIP_DA = 1'b0; + parameter integer TX_CLK25_DIV = 7; + parameter [0:0] TX_CLKMUX_EN = 1'b1; + parameter integer TX_DATA_WIDTH = 20; + parameter [5:0] TX_DEEMPH0 = 6'b000000; + parameter [5:0] TX_DEEMPH1 = 6'b000000; + parameter TX_DRIVE_MODE = "DIRECT"; + parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; + parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; + parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; + parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; + parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; + parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; + parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; + parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; + parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; + parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; + parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; + parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; + parameter [0:0] TX_PREDRIVER_MODE = 1'b0; + parameter [13:0] TX_RXDETECT_CFG = 14'h1832; + parameter [2:0] TX_RXDETECT_REF = 3'b100; + parameter TX_XCLK_SEL = "TXUSR"; + parameter [0:0] UCODEER_CLR = 1'b0; + parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; + output DRPRDY; + output EYESCANDATAERROR; + output GTPTXN; + output GTPTXP; + output PHYSTATUS; + output PMARSVDOUT0; + output PMARSVDOUT1; + output RXBYTEISALIGNED; + output RXBYTEREALIGN; + output RXCDRLOCK; + output RXCHANBONDSEQ; + output RXCHANISALIGNED; + output RXCHANREALIGN; + output RXCOMINITDET; + output RXCOMMADET; + output RXCOMSASDET; + output RXCOMWAKEDET; + output RXDLYSRESETDONE; + output RXELECIDLE; + output RXHEADERVALID; + output RXOSINTDONE; + output RXOSINTSTARTED; + output RXOSINTSTROBEDONE; + output RXOSINTSTROBESTARTED; + output RXOUTCLK; + output RXOUTCLKFABRIC; + output RXOUTCLKPCS; + output RXPHALIGNDONE; + output RXPMARESETDONE; + output RXPRBSERR; + output RXRATEDONE; + output RXRESETDONE; + output RXSYNCDONE; + output RXSYNCOUT; + output RXVALID; + output TXCOMFINISH; + output TXDLYSRESETDONE; + output TXGEARBOXREADY; + output TXOUTCLK; + output TXOUTCLKFABRIC; + output TXOUTCLKPCS; + output TXPHALIGNDONE; + output TXPHINITDONE; + output TXPMARESETDONE; + output TXRATEDONE; + output TXRESETDONE; + output TXSYNCDONE; + output TXSYNCOUT; + output [14:0] DMONITOROUT; + output [15:0] DRPDO; + output [15:0] PCSRSVDOUT; + output [1:0] RXCLKCORCNT; + output [1:0] RXDATAVALID; + output [1:0] RXSTARTOFSEQ; + output [1:0] TXBUFSTATUS; + output [2:0] RXBUFSTATUS; + output [2:0] RXHEADER; + output [2:0] RXSTATUS; + output [31:0] RXDATA; + output [3:0] RXCHARISCOMMA; + output [3:0] RXCHARISK; + output [3:0] RXCHBONDO; + output [3:0] RXDISPERR; + output [3:0] RXNOTINTABLE; + output [4:0] RXPHMONITOR; + output [4:0] RXPHSLIPMONITOR; + input CFGRESET; + (* invertible_pin = "IS_CLKRSVD0_INVERTED" *) + input CLKRSVD0; + (* invertible_pin = "IS_CLKRSVD1_INVERTED" *) + input CLKRSVD1; + input DMONFIFORESET; + (* invertible_pin = "IS_DMONITORCLK_INVERTED" *) + input DMONITORCLK; + (* invertible_pin = "IS_DRPCLK_INVERTED" *) + input DRPCLK; + input DRPEN; + input DRPWE; + input EYESCANMODE; + input EYESCANRESET; + input EYESCANTRIGGER; + input GTPRXN; + input GTPRXP; + input GTRESETSEL; + input GTRXRESET; + input GTTXRESET; + input PLL0CLK; + input PLL0REFCLK; + input PLL1CLK; + input PLL1REFCLK; + input PMARSVDIN0; + input PMARSVDIN1; + input PMARSVDIN2; + input PMARSVDIN3; + input PMARSVDIN4; + input RESETOVRD; + input RX8B10BEN; + input RXBUFRESET; + input RXCDRFREQRESET; + input RXCDRHOLD; + input RXCDROVRDEN; + input RXCDRRESET; + input RXCDRRESETRSV; + input RXCHBONDEN; + input RXCHBONDMASTER; + input RXCHBONDSLAVE; + input RXCOMMADETEN; + input RXDDIEN; + input RXDFEXYDEN; + input RXDLYBYPASS; + input RXDLYEN; + input RXDLYOVRDEN; + input RXDLYSRESET; + input RXGEARBOXSLIP; + input RXLPMHFHOLD; + input RXLPMHFOVRDEN; + input RXLPMLFHOLD; + input RXLPMLFOVRDEN; + input RXLPMOSINTNTRLEN; + input RXLPMRESET; + input RXMCOMMAALIGNEN; + input RXOOBRESET; + input RXOSCALRESET; + input RXOSHOLD; + input RXOSINTEN; + input RXOSINTHOLD; + input RXOSINTNTRLEN; + input RXOSINTOVRDEN; + input RXOSINTPD; + input RXOSINTSTROBE; + input RXOSINTTESTOVRDEN; + input RXOSOVRDEN; + input RXPCOMMAALIGNEN; + input RXPCSRESET; + input RXPHALIGN; + input RXPHALIGNEN; + input RXPHDLYPD; + input RXPHDLYRESET; + input RXPHOVRDEN; + input RXPMARESET; + input RXPOLARITY; + input RXPRBSCNTRESET; + input RXRATEMODE; + input RXSLIDE; + input RXSYNCALLIN; + input RXSYNCIN; + input RXSYNCMODE; + input RXUSERRDY; + (* invertible_pin = "IS_RXUSRCLK2_INVERTED" *) + input RXUSRCLK2; + (* invertible_pin = "IS_RXUSRCLK_INVERTED" *) + input RXUSRCLK; + input SETERRSTATUS; + (* invertible_pin = "IS_SIGVALIDCLK_INVERTED" *) + input SIGVALIDCLK; + input TX8B10BEN; + input TXCOMINIT; + input TXCOMSAS; + input TXCOMWAKE; + input TXDEEMPH; + input TXDETECTRX; + input TXDIFFPD; + input TXDLYBYPASS; + input TXDLYEN; + input TXDLYHOLD; + input TXDLYOVRDEN; + input TXDLYSRESET; + input TXDLYUPDOWN; + input TXELECIDLE; + input TXINHIBIT; + input TXPCSRESET; + input TXPDELECIDLEMODE; + input TXPHALIGN; + input TXPHALIGNEN; + input TXPHDLYPD; + input TXPHDLYRESET; + (* invertible_pin = "IS_TXPHDLYTSTCLK_INVERTED" *) + input TXPHDLYTSTCLK; + input TXPHINIT; + input TXPHOVRDEN; + input TXPIPPMEN; + input TXPIPPMOVRDEN; + input TXPIPPMPD; + input TXPIPPMSEL; + input TXPISOPD; + input TXPMARESET; + input TXPOLARITY; + input TXPOSTCURSORINV; + input TXPRBSFORCEERR; + input TXPRECURSORINV; + input TXRATEMODE; + input TXSTARTSEQ; + input TXSWING; + input TXSYNCALLIN; + input TXSYNCIN; + input TXSYNCMODE; + input TXUSERRDY; + (* invertible_pin = "IS_TXUSRCLK2_INVERTED" *) + input TXUSRCLK2; + (* invertible_pin = "IS_TXUSRCLK_INVERTED" *) + input TXUSRCLK; + input [13:0] RXADAPTSELTEST; + input [15:0] DRPDI; + input [15:0] GTRSVD; + input [15:0] PCSRSVDIN; + input [19:0] TSTIN; + input [1:0] RXELECIDLEMODE; + input [1:0] RXPD; + input [1:0] RXSYSCLKSEL; + input [1:0] TXPD; + input [1:0] TXSYSCLKSEL; + input [2:0] LOOPBACK; + input [2:0] RXCHBONDLEVEL; + input [2:0] RXOUTCLKSEL; + input [2:0] RXPRBSSEL; + input [2:0] RXRATE; + input [2:0] TXBUFDIFFCTRL; + input [2:0] TXHEADER; + input [2:0] TXMARGIN; + input [2:0] TXOUTCLKSEL; + input [2:0] TXPRBSSEL; + input [2:0] TXRATE; + input [31:0] TXDATA; + input [3:0] RXCHBONDI; + input [3:0] RXOSINTCFG; + input [3:0] RXOSINTID0; + input [3:0] TX8B10BBYPASS; + input [3:0] TXCHARDISPMODE; + input [3:0] TXCHARDISPVAL; + input [3:0] TXCHARISK; + input [3:0] TXDIFFCTRL; + input [4:0] TXPIPPMSTEPSIZE; + input [4:0] TXPOSTCURSOR; + input [4:0] TXPRECURSOR; + input [6:0] TXMAINCURSOR; + input [6:0] TXSEQUENCE; + input [8:0] DRPADDR; +endmodule + +module GTPE2_COMMON (...); + parameter [63:0] BIAS_CFG = 64'h0000000000000000; + parameter [31:0] COMMON_CFG = 32'h00000000; + parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; + parameter [0:0] IS_GTGREFCLK0_INVERTED = 1'b0; + parameter [0:0] IS_GTGREFCLK1_INVERTED = 1'b0; + parameter [0:0] IS_PLL0LOCKDETCLK_INVERTED = 1'b0; + parameter [0:0] IS_PLL1LOCKDETCLK_INVERTED = 1'b0; + parameter [26:0] PLL0_CFG = 27'h01F03DC; + parameter [0:0] PLL0_DMON_CFG = 1'b0; + parameter integer PLL0_FBDIV = 4; + parameter integer PLL0_FBDIV_45 = 5; + parameter [23:0] PLL0_INIT_CFG = 24'h00001E; + parameter [8:0] PLL0_LOCK_CFG = 9'h1E8; + parameter integer PLL0_REFCLK_DIV = 1; + parameter [26:0] PLL1_CFG = 27'h01F03DC; + parameter [0:0] PLL1_DMON_CFG = 1'b0; + parameter integer PLL1_FBDIV = 4; + parameter integer PLL1_FBDIV_45 = 5; + parameter [23:0] PLL1_INIT_CFG = 24'h00001E; + parameter [8:0] PLL1_LOCK_CFG = 9'h1E8; + parameter integer PLL1_REFCLK_DIV = 1; + parameter [7:0] PLL_CLKOUT_CFG = 8'b00000000; + parameter [15:0] RSVD_ATTR0 = 16'h0000; + parameter [15:0] RSVD_ATTR1 = 16'h0000; + parameter [2:0] SIM_PLL0REFCLK_SEL = 3'b001; + parameter [2:0] SIM_PLL1REFCLK_SEL = 3'b001; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter SIM_VERSION = "1.0"; + output DRPRDY; + output PLL0FBCLKLOST; + output PLL0LOCK; + output PLL0OUTCLK; + output PLL0OUTREFCLK; + output PLL0REFCLKLOST; + output PLL1FBCLKLOST; + output PLL1LOCK; + output PLL1OUTCLK; + output PLL1OUTREFCLK; + output PLL1REFCLKLOST; + output REFCLKOUTMONITOR0; + output REFCLKOUTMONITOR1; + output [15:0] DRPDO; + output [15:0] PMARSVDOUT; + output [7:0] DMONITOROUT; + input BGBYPASSB; + input BGMONITORENB; + input BGPDB; + input BGRCALOVRDENB; + (* invertible_pin = "IS_DRPCLK_INVERTED" *) + input DRPCLK; + input DRPEN; + input DRPWE; + input GTEASTREFCLK0; + input GTEASTREFCLK1; + (* invertible_pin = "IS_GTGREFCLK0_INVERTED" *) + input GTGREFCLK0; + (* invertible_pin = "IS_GTGREFCLK1_INVERTED" *) + input GTGREFCLK1; + input GTREFCLK0; + input GTREFCLK1; + input GTWESTREFCLK0; + input GTWESTREFCLK1; + (* invertible_pin = "IS_PLL0LOCKDETCLK_INVERTED" *) + input PLL0LOCKDETCLK; + input PLL0LOCKEN; + input PLL0PD; + input PLL0RESET; + (* invertible_pin = "IS_PLL1LOCKDETCLK_INVERTED" *) + input PLL1LOCKDETCLK; + input PLL1LOCKEN; + input PLL1PD; + input PLL1RESET; + input RCALENB; + input [15:0] DRPDI; + input [15:0] PLLRSVD1; + input [2:0] PLL0REFCLKSEL; + input [2:0] PLL1REFCLKSEL; + input [4:0] BGRCALOVRD; + input [4:0] PLLRSVD2; + input [7:0] DRPADDR; + input [7:0] PMARSVD; +endmodule + +module GTXE2_CHANNEL (...); + parameter ALIGN_COMMA_DOUBLE = "FALSE"; + parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; + parameter integer ALIGN_COMMA_WORD = 1; + parameter ALIGN_MCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; + parameter ALIGN_PCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; + parameter CBCC_DATA_SOURCE_SEL = "DECODED"; + parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; + parameter integer CHAN_BOND_MAX_SKEW = 7; + parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; + parameter CHAN_BOND_SEQ_2_USE = "FALSE"; + parameter integer CHAN_BOND_SEQ_LEN = 1; + parameter CLK_CORRECT_USE = "TRUE"; + parameter CLK_COR_KEEP_IDLE = "FALSE"; + parameter integer CLK_COR_MAX_LAT = 20; + parameter integer CLK_COR_MIN_LAT = 18; + parameter CLK_COR_PRECEDENCE = "TRUE"; + parameter integer CLK_COR_REPEAT_WAIT = 0; + parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; + parameter CLK_COR_SEQ_2_USE = "FALSE"; + parameter integer CLK_COR_SEQ_LEN = 1; + parameter [23:0] CPLL_CFG = 24'hB007D8; + parameter integer CPLL_FBDIV = 4; + parameter integer CPLL_FBDIV_45 = 5; + parameter [23:0] CPLL_INIT_CFG = 24'h00001E; + parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; + parameter integer CPLL_REFCLK_DIV = 1; + parameter DEC_MCOMMA_DETECT = "TRUE"; + parameter DEC_PCOMMA_DETECT = "TRUE"; + parameter DEC_VALID_COMMA_ONLY = "TRUE"; + parameter [23:0] DMONITOR_CFG = 24'h000A00; + parameter [5:0] ES_CONTROL = 6'b000000; + parameter ES_ERRDET_EN = "FALSE"; + parameter ES_EYE_SCAN_EN = "FALSE"; + parameter [11:0] ES_HORZ_OFFSET = 12'h000; + parameter [9:0] ES_PMA_CFG = 10'b0000000000; + parameter [4:0] ES_PRESCALE = 5'b00000; + parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000; + parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000; + parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000; + parameter [8:0] ES_VERT_OFFSET = 9'b000000000; + parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; + parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; + parameter FTS_LANE_DESKEW_EN = "FALSE"; + parameter [2:0] GEARBOX_MODE = 3'b000; + parameter [0:0] IS_CPLLLOCKDETCLK_INVERTED = 1'b0; + parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; + parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0; + parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0; + parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0; + parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0; + parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0; + parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0; + parameter [1:0] OUTREFCLK_SEL_INV = 2'b11; + parameter PCS_PCIE_EN = "FALSE"; + parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000; + parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; + parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; + parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; + parameter [31:0] PMA_RSV = 32'h00000000; + parameter [15:0] PMA_RSV2 = 16'h2050; + parameter [1:0] PMA_RSV3 = 2'b00; + parameter [31:0] PMA_RSV4 = 32'h00000000; + parameter [4:0] RXBUFRESET_TIME = 5'b00001; + parameter RXBUF_ADDR_MODE = "FULL"; + parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; + parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; + parameter RXBUF_EN = "TRUE"; + parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; + parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; + parameter RXBUF_RESET_ON_EIDLE = "FALSE"; + parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; + parameter integer RXBUF_THRESH_OVFLW = 61; + parameter RXBUF_THRESH_OVRD = "FALSE"; + parameter integer RXBUF_THRESH_UNDFLW = 4; + parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; + parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; + parameter [71:0] RXCDR_CFG = 72'h0B000023FF20400020; + parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; + parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; + parameter [5:0] RXCDR_LOCK_CFG = 6'b010101; + parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; + parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; + parameter [15:0] RXDLY_CFG = 16'h001F; + parameter [8:0] RXDLY_LCFG = 9'h030; + parameter [15:0] RXDLY_TAP_CFG = 16'h0000; + parameter RXGEARBOX_EN = "FALSE"; + parameter [4:0] RXISCANRESET_TIME = 5'b00001; + parameter [13:0] RXLPM_HF_CFG = 14'b00000011110000; + parameter [13:0] RXLPM_LF_CFG = 14'b00000011110000; + parameter [6:0] RXOOB_CFG = 7'b0000110; + parameter integer RXOUT_DIV = 2; + parameter [4:0] RXPCSRESET_TIME = 5'b00001; + parameter [23:0] RXPHDLY_CFG = 24'h084020; + parameter [23:0] RXPH_CFG = 24'h000000; + parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; + parameter [4:0] RXPMARESET_TIME = 5'b00011; + parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; + parameter integer RXSLIDE_AUTO_WAIT = 7; + parameter RXSLIDE_MODE = "OFF"; + parameter [11:0] RX_BIAS_CFG = 12'b000000000000; + parameter [5:0] RX_BUFFER_CFG = 6'b000000; + parameter integer RX_CLK25_DIV = 7; + parameter [0:0] RX_CLKMUX_PD = 1'b1; + parameter [1:0] RX_CM_SEL = 2'b11; + parameter [2:0] RX_CM_TRIM = 3'b100; + parameter integer RX_DATA_WIDTH = 20; + parameter [5:0] RX_DDI_SEL = 6'b000000; + parameter [11:0] RX_DEBUG_CFG = 12'b000000000000; + parameter RX_DEFER_RESET_BUF_EN = "TRUE"; + parameter [22:0] RX_DFE_GAIN_CFG = 23'h180E0F; + parameter [11:0] RX_DFE_H2_CFG = 12'b000111100000; + parameter [11:0] RX_DFE_H3_CFG = 12'b000111100000; + parameter [10:0] RX_DFE_H4_CFG = 11'b00011110000; + parameter [10:0] RX_DFE_H5_CFG = 11'b00011110000; + parameter [12:0] RX_DFE_KL_CFG = 13'b0001111110000; + parameter [31:0] RX_DFE_KL_CFG2 = 32'h3008E56A; + parameter [15:0] RX_DFE_LPM_CFG = 16'h0904; + parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; + parameter [16:0] RX_DFE_UT_CFG = 17'b00111111000000000; + parameter [16:0] RX_DFE_VP_CFG = 17'b00011111100000000; + parameter [12:0] RX_DFE_XYD_CFG = 13'b0000000010000; + parameter RX_DISPERR_SEQ_MATCH = "TRUE"; + parameter integer RX_INT_DATAWIDTH = 0; + parameter [12:0] RX_OS_CFG = 13'b0001111110000; + parameter integer RX_SIG_VALID_DLY = 10; + parameter RX_XCLK_SEL = "RXREC"; + parameter integer SAS_MAX_COM = 64; + parameter integer SAS_MIN_COM = 36; + parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; + parameter [2:0] SATA_BURST_VAL = 3'b100; + parameter SATA_CPLL_CFG = "VCO_3000MHZ"; + parameter [2:0] SATA_EIDLE_VAL = 3'b100; + parameter integer SATA_MAX_BURST = 8; + parameter integer SATA_MAX_INIT = 21; + parameter integer SATA_MAX_WAKE = 7; + parameter integer SATA_MIN_BURST = 4; + parameter integer SATA_MIN_INIT = 12; + parameter integer SATA_MIN_WAKE = 4; + parameter SHOW_REALIGN_COMMA = "TRUE"; + parameter [2:0] SIM_CPLLREFCLK_SEL = 3'b001; + parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X"; + parameter SIM_VERSION = "4.0"; + parameter [4:0] TERM_RCAL_CFG = 5'b10000; + parameter [0:0] TERM_RCAL_OVRD = 1'b0; + parameter [7:0] TRANS_TIME_RATE = 8'h0E; + parameter [31:0] TST_RSV = 32'h00000000; + parameter TXBUF_EN = "TRUE"; + parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; + parameter [15:0] TXDLY_CFG = 16'h001F; + parameter [8:0] TXDLY_LCFG = 9'h030; + parameter [15:0] TXDLY_TAP_CFG = 16'h0000; + parameter TXGEARBOX_EN = "FALSE"; + parameter integer TXOUT_DIV = 2; + parameter [4:0] TXPCSRESET_TIME = 5'b00001; + parameter [23:0] TXPHDLY_CFG = 24'h084020; + parameter [15:0] TXPH_CFG = 16'h0780; + parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; + parameter [4:0] TXPMARESET_TIME = 5'b00001; + parameter integer TX_CLK25_DIV = 7; + parameter [0:0] TX_CLKMUX_PD = 1'b1; + parameter integer TX_DATA_WIDTH = 20; + parameter [4:0] TX_DEEMPH0 = 5'b00000; + parameter [4:0] TX_DEEMPH1 = 5'b00000; + parameter TX_DRIVE_MODE = "DIRECT"; + parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; + parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; + parameter integer TX_INT_DATAWIDTH = 0; + parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; + parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; + parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; + parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; + parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; + parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; + parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; + parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; + parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; + parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; + parameter [0:0] TX_PREDRIVER_MODE = 1'b0; + parameter [0:0] TX_QPI_STATUS_EN = 1'b0; + parameter [13:0] TX_RXDETECT_CFG = 14'h1832; + parameter [2:0] TX_RXDETECT_REF = 3'b100; + parameter TX_XCLK_SEL = "TXUSR"; + parameter [0:0] UCODEER_CLR = 1'b0; + output CPLLFBCLKLOST; + output CPLLLOCK; + output CPLLREFCLKLOST; + output DRPRDY; + output EYESCANDATAERROR; + output GTREFCLKMONITOR; + output GTXTXN; + output GTXTXP; + output PHYSTATUS; + output RXBYTEISALIGNED; + output RXBYTEREALIGN; + output RXCDRLOCK; + output RXCHANBONDSEQ; + output RXCHANISALIGNED; + output RXCHANREALIGN; + output RXCOMINITDET; + output RXCOMMADET; + output RXCOMSASDET; + output RXCOMWAKEDET; + output RXDATAVALID; + output RXDLYSRESETDONE; + output RXELECIDLE; + output RXHEADERVALID; + output RXOUTCLK; + output RXOUTCLKFABRIC; + output RXOUTCLKPCS; + output RXPHALIGNDONE; + output RXPRBSERR; + output RXQPISENN; + output RXQPISENP; + output RXRATEDONE; + output RXRESETDONE; + output RXSTARTOFSEQ; + output RXVALID; + output TXCOMFINISH; + output TXDLYSRESETDONE; + output TXGEARBOXREADY; + output TXOUTCLK; + output TXOUTCLKFABRIC; + output TXOUTCLKPCS; + output TXPHALIGNDONE; + output TXPHINITDONE; + output TXQPISENN; + output TXQPISENP; + output TXRATEDONE; + output TXRESETDONE; + output [15:0] DRPDO; + output [15:0] PCSRSVDOUT; + output [1:0] RXCLKCORCNT; + output [1:0] TXBUFSTATUS; + output [2:0] RXBUFSTATUS; + output [2:0] RXHEADER; + output [2:0] RXSTATUS; + output [4:0] RXCHBONDO; + output [4:0] RXPHMONITOR; + output [4:0] RXPHSLIPMONITOR; + output [63:0] RXDATA; + output [6:0] RXMONITOROUT; + output [7:0] DMONITOROUT; + output [7:0] RXCHARISCOMMA; + output [7:0] RXCHARISK; + output [7:0] RXDISPERR; + output [7:0] RXNOTINTABLE; + output [9:0] TSTOUT; + input CFGRESET; + (* invertible_pin = "IS_CPLLLOCKDETCLK_INVERTED" *) + input CPLLLOCKDETCLK; + input CPLLLOCKEN; + input CPLLPD; + input CPLLRESET; + (* invertible_pin = "IS_DRPCLK_INVERTED" *) + input DRPCLK; + input DRPEN; + input DRPWE; + input EYESCANMODE; + input EYESCANRESET; + input EYESCANTRIGGER; + (* invertible_pin = "IS_GTGREFCLK_INVERTED" *) + input GTGREFCLK; + input GTNORTHREFCLK0; + input GTNORTHREFCLK1; + input GTREFCLK0; + input GTREFCLK1; + input GTRESETSEL; + input GTRXRESET; + input GTSOUTHREFCLK0; + input GTSOUTHREFCLK1; + input GTTXRESET; + input GTXRXN; + input GTXRXP; + input QPLLCLK; + input QPLLREFCLK; + input RESETOVRD; + input RX8B10BEN; + input RXBUFRESET; + input RXCDRFREQRESET; + input RXCDRHOLD; + input RXCDROVRDEN; + input RXCDRRESET; + input RXCDRRESETRSV; + input RXCHBONDEN; + input RXCHBONDMASTER; + input RXCHBONDSLAVE; + input RXCOMMADETEN; + input RXDDIEN; + input RXDFEAGCHOLD; + input RXDFEAGCOVRDEN; + input RXDFECM1EN; + input RXDFELFHOLD; + input RXDFELFOVRDEN; + input RXDFELPMRESET; + input RXDFETAP2HOLD; + input RXDFETAP2OVRDEN; + input RXDFETAP3HOLD; + input RXDFETAP3OVRDEN; + input RXDFETAP4HOLD; + input RXDFETAP4OVRDEN; + input RXDFETAP5HOLD; + input RXDFETAP5OVRDEN; + input RXDFEUTHOLD; + input RXDFEUTOVRDEN; + input RXDFEVPHOLD; + input RXDFEVPOVRDEN; + input RXDFEVSEN; + input RXDFEXYDEN; + input RXDFEXYDHOLD; + input RXDFEXYDOVRDEN; + input RXDLYBYPASS; + input RXDLYEN; + input RXDLYOVRDEN; + input RXDLYSRESET; + input RXGEARBOXSLIP; + input RXLPMEN; + input RXLPMHFHOLD; + input RXLPMHFOVRDEN; + input RXLPMLFHOLD; + input RXLPMLFKLOVRDEN; + input RXMCOMMAALIGNEN; + input RXOOBRESET; + input RXOSHOLD; + input RXOSOVRDEN; + input RXPCOMMAALIGNEN; + input RXPCSRESET; + input RXPHALIGN; + input RXPHALIGNEN; + input RXPHDLYPD; + input RXPHDLYRESET; + input RXPHOVRDEN; + input RXPMARESET; + input RXPOLARITY; + input RXPRBSCNTRESET; + input RXQPIEN; + input RXSLIDE; + input RXUSERRDY; + (* invertible_pin = "IS_RXUSRCLK2_INVERTED" *) + input RXUSRCLK2; + (* invertible_pin = "IS_RXUSRCLK_INVERTED" *) + input RXUSRCLK; + input SETERRSTATUS; + input TX8B10BEN; + input TXCOMINIT; + input TXCOMSAS; + input TXCOMWAKE; + input TXDEEMPH; + input TXDETECTRX; + input TXDIFFPD; + input TXDLYBYPASS; + input TXDLYEN; + input TXDLYHOLD; + input TXDLYOVRDEN; + input TXDLYSRESET; + input TXDLYUPDOWN; + input TXELECIDLE; + input TXINHIBIT; + input TXPCSRESET; + input TXPDELECIDLEMODE; + input TXPHALIGN; + input TXPHALIGNEN; + input TXPHDLYPD; + input TXPHDLYRESET; + (* invertible_pin = "IS_TXPHDLYTSTCLK_INVERTED" *) + input TXPHDLYTSTCLK; + input TXPHINIT; + input TXPHOVRDEN; + input TXPISOPD; + input TXPMARESET; + input TXPOLARITY; + input TXPOSTCURSORINV; + input TXPRBSFORCEERR; + input TXPRECURSORINV; + input TXQPIBIASEN; + input TXQPISTRONGPDOWN; + input TXQPIWEAKPUP; + input TXSTARTSEQ; + input TXSWING; + input TXUSERRDY; + (* invertible_pin = "IS_TXUSRCLK2_INVERTED" *) + input TXUSRCLK2; + (* invertible_pin = "IS_TXUSRCLK_INVERTED" *) + input TXUSRCLK; + input [15:0] DRPDI; + input [15:0] GTRSVD; + input [15:0] PCSRSVDIN; + input [19:0] TSTIN; + input [1:0] RXELECIDLEMODE; + input [1:0] RXMONITORSEL; + input [1:0] RXPD; + input [1:0] RXSYSCLKSEL; + input [1:0] TXPD; + input [1:0] TXSYSCLKSEL; + input [2:0] CPLLREFCLKSEL; + input [2:0] LOOPBACK; + input [2:0] RXCHBONDLEVEL; + input [2:0] RXOUTCLKSEL; + input [2:0] RXPRBSSEL; + input [2:0] RXRATE; + input [2:0] TXBUFDIFFCTRL; + input [2:0] TXHEADER; + input [2:0] TXMARGIN; + input [2:0] TXOUTCLKSEL; + input [2:0] TXPRBSSEL; + input [2:0] TXRATE; + input [3:0] CLKRSVD; + input [3:0] TXDIFFCTRL; + input [4:0] PCSRSVDIN2; + input [4:0] PMARSVDIN2; + input [4:0] PMARSVDIN; + input [4:0] RXCHBONDI; + input [4:0] TXPOSTCURSOR; + input [4:0] TXPRECURSOR; + input [63:0] TXDATA; + input [6:0] TXMAINCURSOR; + input [6:0] TXSEQUENCE; + input [7:0] TX8B10BBYPASS; + input [7:0] TXCHARDISPMODE; + input [7:0] TXCHARDISPVAL; + input [7:0] TXCHARISK; + input [8:0] DRPADDR; +endmodule + +module GTXE2_COMMON (...); + parameter [63:0] BIAS_CFG = 64'h0000040000001000; + parameter [31:0] COMMON_CFG = 32'h00000000; + parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; + parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0; + parameter [0:0] IS_QPLLLOCKDETCLK_INVERTED = 1'b0; + parameter [26:0] QPLL_CFG = 27'h0680181; + parameter [3:0] QPLL_CLKOUT_CFG = 4'b0000; + parameter [5:0] QPLL_COARSE_FREQ_OVRD = 6'b010000; + parameter [0:0] QPLL_COARSE_FREQ_OVRD_EN = 1'b0; + parameter [9:0] QPLL_CP = 10'b0000011111; + parameter [0:0] QPLL_CP_MONITOR_EN = 1'b0; + parameter [0:0] QPLL_DMONITOR_SEL = 1'b0; + parameter [9:0] QPLL_FBDIV = 10'b0000000000; + parameter [0:0] QPLL_FBDIV_MONITOR_EN = 1'b0; + parameter [0:0] QPLL_FBDIV_RATIO = 1'b0; + parameter [23:0] QPLL_INIT_CFG = 24'h000006; + parameter [15:0] QPLL_LOCK_CFG = 16'h21E8; + parameter [3:0] QPLL_LPF = 4'b1111; + parameter integer QPLL_REFCLK_DIV = 2; + parameter [2:0] SIM_QPLLREFCLK_SEL = 3'b001; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter SIM_VERSION = "4.0"; + output DRPRDY; + output QPLLFBCLKLOST; + output QPLLLOCK; + output QPLLOUTCLK; + output QPLLOUTREFCLK; + output QPLLREFCLKLOST; + output REFCLKOUTMONITOR; + output [15:0] DRPDO; + output [7:0] QPLLDMONITOR; + input BGBYPASSB; + input BGMONITORENB; + input BGPDB; + (* invertible_pin = "IS_DRPCLK_INVERTED" *) + input DRPCLK; + input DRPEN; + input DRPWE; + (* invertible_pin = "IS_GTGREFCLK_INVERTED" *) + input GTGREFCLK; + input GTNORTHREFCLK0; + input GTNORTHREFCLK1; + input GTREFCLK0; + input GTREFCLK1; + input GTSOUTHREFCLK0; + input GTSOUTHREFCLK1; + (* invertible_pin = "IS_QPLLLOCKDETCLK_INVERTED" *) + input QPLLLOCKDETCLK; + input QPLLLOCKEN; + input QPLLOUTRESET; + input QPLLPD; + input QPLLRESET; + input RCALENB; + input [15:0] DRPDI; + input [15:0] QPLLRSVD1; + input [2:0] QPLLREFCLKSEL; + input [4:0] BGRCALOVRD; + input [4:0] QPLLRSVD2; + input [7:0] DRPADDR; + input [7:0] PMARSVD; +endmodule + +module IBUFDS_GTE2 (...); + parameter CLKCM_CFG = "TRUE"; + parameter CLKRCV_TRST = "TRUE"; + parameter CLKSWING_CFG = "TRUE"; + output O; + output ODIV2; + input CEB; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; +endmodule + +module GTHE3_CHANNEL (...); + parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; + parameter [0:0] ACJTAG_MODE = 1'b0; + parameter [0:0] ACJTAG_RESET = 1'b0; + parameter [15:0] ADAPT_CFG0 = 16'hF800; + parameter [15:0] ADAPT_CFG1 = 16'h0000; + parameter ALIGN_COMMA_DOUBLE = "FALSE"; + parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; + parameter integer ALIGN_COMMA_WORD = 1; + parameter ALIGN_MCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; + parameter ALIGN_PCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; + parameter [0:0] A_RXOSCALRESET = 1'b0; + parameter [0:0] A_RXPROGDIVRESET = 1'b0; + parameter [0:0] A_TXPROGDIVRESET = 1'b0; + parameter CBCC_DATA_SOURCE_SEL = "DECODED"; + parameter [0:0] CDR_SWAP_MODE_EN = 1'b0; + parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; + parameter integer CHAN_BOND_MAX_SKEW = 7; + parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; + parameter CHAN_BOND_SEQ_2_USE = "FALSE"; + parameter integer CHAN_BOND_SEQ_LEN = 2; + parameter CLK_CORRECT_USE = "TRUE"; + parameter CLK_COR_KEEP_IDLE = "FALSE"; + parameter integer CLK_COR_MAX_LAT = 20; + parameter integer CLK_COR_MIN_LAT = 18; + parameter CLK_COR_PRECEDENCE = "TRUE"; + parameter integer CLK_COR_REPEAT_WAIT = 0; + parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; + parameter CLK_COR_SEQ_2_USE = "FALSE"; + parameter integer CLK_COR_SEQ_LEN = 2; + parameter [15:0] CPLL_CFG0 = 16'h20F8; + parameter [15:0] CPLL_CFG1 = 16'hA494; + parameter [15:0] CPLL_CFG2 = 16'hF001; + parameter [5:0] CPLL_CFG3 = 6'h00; + parameter integer CPLL_FBDIV = 4; + parameter integer CPLL_FBDIV_45 = 4; + parameter [15:0] CPLL_INIT_CFG0 = 16'h001E; + parameter [7:0] CPLL_INIT_CFG1 = 8'h00; + parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; + parameter integer CPLL_REFCLK_DIV = 1; + parameter [1:0] DDI_CTRL = 2'b00; + parameter integer DDI_REALIGN_WAIT = 15; + parameter DEC_MCOMMA_DETECT = "TRUE"; + parameter DEC_PCOMMA_DETECT = "TRUE"; + parameter DEC_VALID_COMMA_ONLY = "TRUE"; + parameter [0:0] DFE_D_X_REL_POS = 1'b0; + parameter [0:0] DFE_VCM_COMP_EN = 1'b0; + parameter [9:0] DMONITOR_CFG0 = 10'h000; + parameter [7:0] DMONITOR_CFG1 = 8'h00; + parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; + parameter [5:0] ES_CONTROL = 6'b000000; + parameter ES_ERRDET_EN = "FALSE"; + parameter ES_EYE_SCAN_EN = "FALSE"; + parameter [11:0] ES_HORZ_OFFSET = 12'h000; + parameter [9:0] ES_PMA_CFG = 10'b0000000000; + parameter [4:0] ES_PRESCALE = 5'b00000; + parameter [15:0] ES_QUALIFIER0 = 16'h0000; + parameter [15:0] ES_QUALIFIER1 = 16'h0000; + parameter [15:0] ES_QUALIFIER2 = 16'h0000; + parameter [15:0] ES_QUALIFIER3 = 16'h0000; + parameter [15:0] ES_QUALIFIER4 = 16'h0000; + parameter [15:0] ES_QUAL_MASK0 = 16'h0000; + parameter [15:0] ES_QUAL_MASK1 = 16'h0000; + parameter [15:0] ES_QUAL_MASK2 = 16'h0000; + parameter [15:0] ES_QUAL_MASK3 = 16'h0000; + parameter [15:0] ES_QUAL_MASK4 = 16'h0000; + parameter [15:0] ES_SDATA_MASK0 = 16'h0000; + parameter [15:0] ES_SDATA_MASK1 = 16'h0000; + parameter [15:0] ES_SDATA_MASK2 = 16'h0000; + parameter [15:0] ES_SDATA_MASK3 = 16'h0000; + parameter [15:0] ES_SDATA_MASK4 = 16'h0000; + parameter [10:0] EVODD_PHI_CFG = 11'b00000000000; + parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0; + parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; + parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; + parameter FTS_LANE_DESKEW_EN = "FALSE"; + parameter [4:0] GEARBOX_MODE = 5'b00000; + parameter [0:0] GM_BIAS_SELECT = 1'b0; + parameter [0:0] LOCAL_MASTER = 1'b0; + parameter [1:0] OOBDIVCTL = 2'b00; + parameter [0:0] OOB_PWRUP = 1'b0; + parameter PCI3_AUTO_REALIGN = "FRST_SMPL"; + parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1; + parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00; + parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0; + parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000; + parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000; + parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000; + parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0; + parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0; + parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000; + parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000; + parameter [15:0] PCIE_RXPMA_CFG = 16'h0000; + parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000; + parameter [15:0] PCIE_TXPMA_CFG = 16'h0000; + parameter PCS_PCIE_EN = "FALSE"; + parameter [15:0] PCS_RSVD0 = 16'b0000000000000000; + parameter [2:0] PCS_RSVD1 = 3'b000; + parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; + parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; + parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; + parameter [1:0] PLL_SEL_MODE_GEN12 = 2'h0; + parameter [1:0] PLL_SEL_MODE_GEN3 = 2'h0; + parameter [15:0] PMA_RSV1 = 16'h0000; + parameter [2:0] PROCESS_PAR = 3'b010; + parameter [0:0] RATE_SW_USE_DRP = 1'b0; + parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0; + parameter [4:0] RXBUFRESET_TIME = 5'b00001; + parameter RXBUF_ADDR_MODE = "FULL"; + parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; + parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; + parameter RXBUF_EN = "TRUE"; + parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; + parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; + parameter RXBUF_RESET_ON_EIDLE = "FALSE"; + parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; + parameter integer RXBUF_THRESH_OVFLW = 0; + parameter RXBUF_THRESH_OVRD = "FALSE"; + parameter integer RXBUF_THRESH_UNDFLW = 4; + parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; + parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; + parameter [15:0] RXCDR_CFG0 = 16'h0000; + parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0000; + parameter [15:0] RXCDR_CFG1 = 16'h0080; + parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000; + parameter [15:0] RXCDR_CFG2 = 16'h07E6; + parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0000; + parameter [15:0] RXCDR_CFG3 = 16'h0000; + parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0000; + parameter [15:0] RXCDR_CFG4 = 16'h0000; + parameter [15:0] RXCDR_CFG4_GEN3 = 16'h0000; + parameter [15:0] RXCDR_CFG5 = 16'h0000; + parameter [15:0] RXCDR_CFG5_GEN3 = 16'h0000; + parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; + parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; + parameter [15:0] RXCDR_LOCK_CFG0 = 16'h5080; + parameter [15:0] RXCDR_LOCK_CFG1 = 16'h07E0; + parameter [15:0] RXCDR_LOCK_CFG2 = 16'h7C42; + parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; + parameter [15:0] RXCFOK_CFG0 = 16'h4000; + parameter [15:0] RXCFOK_CFG1 = 16'h0060; + parameter [15:0] RXCFOK_CFG2 = 16'h000E; + parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; + parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000; + parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0032; + parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0000; + parameter [15:0] RXDFE_CFG0 = 16'h0A00; + parameter [15:0] RXDFE_CFG1 = 16'h0000; + parameter [15:0] RXDFE_GC_CFG0 = 16'h0000; + parameter [15:0] RXDFE_GC_CFG1 = 16'h7840; + parameter [15:0] RXDFE_GC_CFG2 = 16'h0000; + parameter [15:0] RXDFE_H2_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H2_CFG1 = 16'h0000; + parameter [15:0] RXDFE_H3_CFG0 = 16'h4000; + parameter [15:0] RXDFE_H3_CFG1 = 16'h0000; + parameter [15:0] RXDFE_H4_CFG0 = 16'h2000; + parameter [15:0] RXDFE_H4_CFG1 = 16'h0003; + parameter [15:0] RXDFE_H5_CFG0 = 16'h2000; + parameter [15:0] RXDFE_H5_CFG1 = 16'h0003; + parameter [15:0] RXDFE_H6_CFG0 = 16'h2000; + parameter [15:0] RXDFE_H6_CFG1 = 16'h0000; + parameter [15:0] RXDFE_H7_CFG0 = 16'h2000; + parameter [15:0] RXDFE_H7_CFG1 = 16'h0000; + parameter [15:0] RXDFE_H8_CFG0 = 16'h2000; + parameter [15:0] RXDFE_H8_CFG1 = 16'h0000; + parameter [15:0] RXDFE_H9_CFG0 = 16'h2000; + parameter [15:0] RXDFE_H9_CFG1 = 16'h0000; + parameter [15:0] RXDFE_HA_CFG0 = 16'h2000; + parameter [15:0] RXDFE_HA_CFG1 = 16'h0000; + parameter [15:0] RXDFE_HB_CFG0 = 16'h2000; + parameter [15:0] RXDFE_HB_CFG1 = 16'h0000; + parameter [15:0] RXDFE_HC_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HC_CFG1 = 16'h0000; + parameter [15:0] RXDFE_HD_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HD_CFG1 = 16'h0000; + parameter [15:0] RXDFE_HE_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HE_CFG1 = 16'h0000; + parameter [15:0] RXDFE_HF_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HF_CFG1 = 16'h0000; + parameter [15:0] RXDFE_OS_CFG0 = 16'h8000; + parameter [15:0] RXDFE_OS_CFG1 = 16'h0000; + parameter [15:0] RXDFE_UT_CFG0 = 16'h8000; + parameter [15:0] RXDFE_UT_CFG1 = 16'h0003; + parameter [15:0] RXDFE_VP_CFG0 = 16'hAA00; + parameter [15:0] RXDFE_VP_CFG1 = 16'h0033; + parameter [15:0] RXDLY_CFG = 16'h001F; + parameter [15:0] RXDLY_LCFG = 16'h0030; + parameter RXELECIDLE_CFG = "Sigcfg_4"; + parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4; + parameter RXGEARBOX_EN = "FALSE"; + parameter [4:0] RXISCANRESET_TIME = 5'b00001; + parameter [15:0] RXLPM_CFG = 16'h0000; + parameter [15:0] RXLPM_GC_CFG = 16'h0000; + parameter [15:0] RXLPM_KH_CFG0 = 16'h0000; + parameter [15:0] RXLPM_KH_CFG1 = 16'h0002; + parameter [15:0] RXLPM_OS_CFG0 = 16'h8000; + parameter [15:0] RXLPM_OS_CFG1 = 16'h0002; + parameter [8:0] RXOOB_CFG = 9'b000000110; + parameter RXOOB_CLK_CFG = "PMA"; + parameter [4:0] RXOSCALRESET_TIME = 5'b00011; + parameter integer RXOUT_DIV = 4; + parameter [4:0] RXPCSRESET_TIME = 5'b00001; + parameter [15:0] RXPHBEACON_CFG = 16'h0000; + parameter [15:0] RXPHDLY_CFG = 16'h2020; + parameter [15:0] RXPHSAMP_CFG = 16'h2100; + parameter [15:0] RXPHSLIP_CFG = 16'h6622; + parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; + parameter [1:0] RXPI_CFG0 = 2'b00; + parameter [1:0] RXPI_CFG1 = 2'b00; + parameter [1:0] RXPI_CFG2 = 2'b00; + parameter [1:0] RXPI_CFG3 = 2'b00; + parameter [0:0] RXPI_CFG4 = 1'b0; + parameter [0:0] RXPI_CFG5 = 1'b1; + parameter [2:0] RXPI_CFG6 = 3'b000; + parameter [0:0] RXPI_LPM = 1'b0; + parameter [0:0] RXPI_VREFSEL = 1'b0; + parameter RXPMACLK_SEL = "DATA"; + parameter [4:0] RXPMARESET_TIME = 5'b00001; + parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; + parameter integer RXPRBS_LINKACQ_CNT = 15; + parameter integer RXSLIDE_AUTO_WAIT = 7; + parameter RXSLIDE_MODE = "OFF"; + parameter [0:0] RXSYNC_MULTILANE = 1'b0; + parameter [0:0] RXSYNC_OVRD = 1'b0; + parameter [0:0] RXSYNC_SKIP_DA = 1'b0; + parameter [0:0] RX_AFE_CM_EN = 1'b0; + parameter [15:0] RX_BIAS_CFG0 = 16'h0AD4; + parameter [5:0] RX_BUFFER_CFG = 6'b000000; + parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0; + parameter integer RX_CLK25_DIV = 8; + parameter [0:0] RX_CLKMUX_EN = 1'b1; + parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000; + parameter [3:0] RX_CM_BUF_CFG = 4'b1010; + parameter [0:0] RX_CM_BUF_PD = 1'b0; + parameter [1:0] RX_CM_SEL = 2'b11; + parameter [3:0] RX_CM_TRIM = 4'b0100; + parameter [7:0] RX_CTLE3_LPF = 8'b00000000; + parameter integer RX_DATA_WIDTH = 20; + parameter [5:0] RX_DDI_SEL = 6'b000000; + parameter RX_DEFER_RESET_BUF_EN = "TRUE"; + parameter [3:0] RX_DFELPM_CFG0 = 4'b0110; + parameter [0:0] RX_DFELPM_CFG1 = 1'b0; + parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1; + parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00; + parameter [2:0] RX_DFE_AGC_CFG1 = 3'b100; + parameter [1:0] RX_DFE_KL_LPM_KH_CFG0 = 2'b01; + parameter [2:0] RX_DFE_KL_LPM_KH_CFG1 = 3'b010; + parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01; + parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010; + parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; + parameter RX_DISPERR_SEQ_MATCH = "TRUE"; + parameter [4:0] RX_DIVRESET_TIME = 5'b00001; + parameter [0:0] RX_EN_HI_LR = 1'b0; + parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000; + parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0; + parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00; + parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0; + parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0; + parameter integer RX_INT_DATAWIDTH = 1; + parameter [0:0] RX_PMA_POWER_SAVE = 1'b0; + parameter real RX_PROGDIV_CFG = 4.0; + parameter [2:0] RX_SAMPLE_PERIOD = 3'b101; + parameter integer RX_SIG_VALID_DLY = 11; + parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0; + parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000; + parameter [1:0] RX_SUM_RES_CTRL = 2'b00; + parameter [3:0] RX_SUM_VCMTUNE = 4'b0000; + parameter [0:0] RX_SUM_VCM_OVWR = 1'b0; + parameter [2:0] RX_SUM_VREF_TUNE = 3'b000; + parameter [1:0] RX_TUNE_AFE_OS = 2'b00; + parameter [0:0] RX_WIDEMODE_CDR = 1'b0; + parameter RX_XCLK_SEL = "RXDES"; + parameter integer SAS_MAX_COM = 64; + parameter integer SAS_MIN_COM = 36; + parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; + parameter [2:0] SATA_BURST_VAL = 3'b100; + parameter SATA_CPLL_CFG = "VCO_3000MHZ"; + parameter [2:0] SATA_EIDLE_VAL = 3'b100; + parameter integer SATA_MAX_BURST = 8; + parameter integer SATA_MAX_INIT = 21; + parameter integer SATA_MAX_WAKE = 7; + parameter integer SATA_MIN_BURST = 4; + parameter integer SATA_MIN_INIT = 12; + parameter integer SATA_MIN_WAKE = 4; + parameter SHOW_REALIGN_COMMA = "TRUE"; + parameter SIM_MODE = "FAST"; + parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter [0:0] SIM_TX_EIDLE_DRIVE_LEVEL = 1'b0; + parameter integer SIM_VERSION = 2; + parameter [1:0] TAPDLY_SET_TX = 2'h0; + parameter [3:0] TEMPERATUR_PAR = 4'b0010; + parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; + parameter [2:0] TERM_RCAL_OVRD = 3'b000; + parameter [7:0] TRANS_TIME_RATE = 8'h0E; + parameter [7:0] TST_RSV0 = 8'h00; + parameter [7:0] TST_RSV1 = 8'h00; + parameter TXBUF_EN = "TRUE"; + parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; + parameter [15:0] TXDLY_CFG = 16'h001F; + parameter [15:0] TXDLY_LCFG = 16'h0030; + parameter [3:0] TXDRVBIAS_N = 4'b1010; + parameter [3:0] TXDRVBIAS_P = 4'b1100; + parameter TXFIFO_ADDR_CFG = "LOW"; + parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4; + parameter TXGEARBOX_EN = "FALSE"; + parameter integer TXOUT_DIV = 4; + parameter [4:0] TXPCSRESET_TIME = 5'b00001; + parameter [15:0] TXPHDLY_CFG0 = 16'h2020; + parameter [15:0] TXPHDLY_CFG1 = 16'h0001; + parameter [15:0] TXPH_CFG = 16'h0980; + parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; + parameter [1:0] TXPI_CFG0 = 2'b00; + parameter [1:0] TXPI_CFG1 = 2'b00; + parameter [1:0] TXPI_CFG2 = 2'b00; + parameter [0:0] TXPI_CFG3 = 1'b0; + parameter [0:0] TXPI_CFG4 = 1'b1; + parameter [2:0] TXPI_CFG5 = 3'b000; + parameter [0:0] TXPI_GRAY_SEL = 1'b0; + parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; + parameter [0:0] TXPI_LPM = 1'b0; + parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; + parameter [7:0] TXPI_PPM_CFG = 8'b00000000; + parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; + parameter [0:0] TXPI_VREFSEL = 1'b0; + parameter [4:0] TXPMARESET_TIME = 5'b00001; + parameter [0:0] TXSYNC_MULTILANE = 1'b0; + parameter [0:0] TXSYNC_OVRD = 1'b0; + parameter [0:0] TXSYNC_SKIP_DA = 1'b0; + parameter integer TX_CLK25_DIV = 8; + parameter [0:0] TX_CLKMUX_EN = 1'b1; + parameter integer TX_DATA_WIDTH = 20; + parameter [5:0] TX_DCD_CFG = 6'b000010; + parameter [0:0] TX_DCD_EN = 1'b0; + parameter [5:0] TX_DEEMPH0 = 6'b000000; + parameter [5:0] TX_DEEMPH1 = 6'b000000; + parameter [4:0] TX_DIVRESET_TIME = 5'b00001; + parameter TX_DRIVE_MODE = "DIRECT"; + parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; + parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; + parameter [0:0] TX_EML_PHI_TUNE = 1'b0; + parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0; + parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0; + parameter integer TX_INT_DATAWIDTH = 1; + parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; + parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; + parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; + parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; + parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; + parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; + parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; + parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; + parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; + parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; + parameter [2:0] TX_MODE_SEL = 3'b000; + parameter [0:0] TX_PMADATA_OPT = 1'b0; + parameter [0:0] TX_PMA_POWER_SAVE = 1'b0; + parameter TX_PROGCLK_SEL = "POSTPI"; + parameter real TX_PROGDIV_CFG = 4.0; + parameter [0:0] TX_QPI_STATUS_EN = 1'b0; + parameter [13:0] TX_RXDETECT_CFG = 14'h0032; + parameter [2:0] TX_RXDETECT_REF = 3'b100; + parameter [2:0] TX_SAMPLE_PERIOD = 3'b101; + parameter [0:0] TX_SARC_LPBK_ENB = 1'b0; + parameter TX_XCLK_SEL = "TXOUT"; + parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; + parameter [1:0] WB_MODE = 2'b00; + output [2:0] BUFGTCE; + output [2:0] BUFGTCEMASK; + output [8:0] BUFGTDIV; + output [2:0] BUFGTRESET; + output [2:0] BUFGTRSTMASK; + output CPLLFBCLKLOST; + output CPLLLOCK; + output CPLLREFCLKLOST; + output [16:0] DMONITOROUT; + output [15:0] DRPDO; + output DRPRDY; + output EYESCANDATAERROR; + output GTHTXN; + output GTHTXP; + output GTPOWERGOOD; + output GTREFCLKMONITOR; + output PCIERATEGEN3; + output PCIERATEIDLE; + output [1:0] PCIERATEQPLLPD; + output [1:0] PCIERATEQPLLRESET; + output PCIESYNCTXSYNCDONE; + output PCIEUSERGEN3RDY; + output PCIEUSERPHYSTATUSRST; + output PCIEUSERRATESTART; + output [11:0] PCSRSVDOUT; + output PHYSTATUS; + output [7:0] PINRSRVDAS; + output RESETEXCEPTION; + output [2:0] RXBUFSTATUS; + output RXBYTEISALIGNED; + output RXBYTEREALIGN; + output RXCDRLOCK; + output RXCDRPHDONE; + output RXCHANBONDSEQ; + output RXCHANISALIGNED; + output RXCHANREALIGN; + output [4:0] RXCHBONDO; + output [1:0] RXCLKCORCNT; + output RXCOMINITDET; + output RXCOMMADET; + output RXCOMSASDET; + output RXCOMWAKEDET; + output [15:0] RXCTRL0; + output [15:0] RXCTRL1; + output [7:0] RXCTRL2; + output [7:0] RXCTRL3; + output [127:0] RXDATA; + output [7:0] RXDATAEXTENDRSVD; + output [1:0] RXDATAVALID; + output RXDLYSRESETDONE; + output RXELECIDLE; + output [5:0] RXHEADER; + output [1:0] RXHEADERVALID; + output [6:0] RXMONITOROUT; + output RXOSINTDONE; + output RXOSINTSTARTED; + output RXOSINTSTROBEDONE; + output RXOSINTSTROBESTARTED; + output RXOUTCLK; + output RXOUTCLKFABRIC; + output RXOUTCLKPCS; + output RXPHALIGNDONE; + output RXPHALIGNERR; + output RXPMARESETDONE; + output RXPRBSERR; + output RXPRBSLOCKED; + output RXPRGDIVRESETDONE; + output RXQPISENN; + output RXQPISENP; + output RXRATEDONE; + output RXRECCLKOUT; + output RXRESETDONE; + output RXSLIDERDY; + output RXSLIPDONE; + output RXSLIPOUTCLKRDY; + output RXSLIPPMARDY; + output [1:0] RXSTARTOFSEQ; + output [2:0] RXSTATUS; + output RXSYNCDONE; + output RXSYNCOUT; + output RXVALID; + output [1:0] TXBUFSTATUS; + output TXCOMFINISH; + output TXDLYSRESETDONE; + output TXOUTCLK; + output TXOUTCLKFABRIC; + output TXOUTCLKPCS; + output TXPHALIGNDONE; + output TXPHINITDONE; + output TXPMARESETDONE; + output TXPRGDIVRESETDONE; + output TXQPISENN; + output TXQPISENP; + output TXRATEDONE; + output TXRESETDONE; + output TXSYNCDONE; + output TXSYNCOUT; + input CFGRESET; + input CLKRSVD0; + input CLKRSVD1; + input CPLLLOCKDETCLK; + input CPLLLOCKEN; + input CPLLPD; + input [2:0] CPLLREFCLKSEL; + input CPLLRESET; + input DMONFIFORESET; + input DMONITORCLK; + input [8:0] DRPADDR; + input DRPCLK; + input [15:0] DRPDI; + input DRPEN; + input DRPWE; + input EVODDPHICALDONE; + input EVODDPHICALSTART; + input EVODDPHIDRDEN; + input EVODDPHIDWREN; + input EVODDPHIXRDEN; + input EVODDPHIXWREN; + input EYESCANMODE; + input EYESCANRESET; + input EYESCANTRIGGER; + input GTGREFCLK; + input GTHRXN; + input GTHRXP; + input GTNORTHREFCLK0; + input GTNORTHREFCLK1; + input GTREFCLK0; + input GTREFCLK1; + input GTRESETSEL; + input [15:0] GTRSVD; + input GTRXRESET; + input GTSOUTHREFCLK0; + input GTSOUTHREFCLK1; + input GTTXRESET; + input [2:0] LOOPBACK; + input LPBKRXTXSEREN; + input LPBKTXRXSEREN; + input PCIEEQRXEQADAPTDONE; + input PCIERSTIDLE; + input PCIERSTTXSYNCSTART; + input PCIEUSERRATEDONE; + input [15:0] PCSRSVDIN; + input [4:0] PCSRSVDIN2; + input [4:0] PMARSVDIN; + input QPLL0CLK; + input QPLL0REFCLK; + input QPLL1CLK; + input QPLL1REFCLK; + input RESETOVRD; + input RSTCLKENTX; + input RX8B10BEN; + input RXBUFRESET; + input RXCDRFREQRESET; + input RXCDRHOLD; + input RXCDROVRDEN; + input RXCDRRESET; + input RXCDRRESETRSV; + input RXCHBONDEN; + input [4:0] RXCHBONDI; + input [2:0] RXCHBONDLEVEL; + input RXCHBONDMASTER; + input RXCHBONDSLAVE; + input RXCOMMADETEN; + input [1:0] RXDFEAGCCTRL; + input RXDFEAGCHOLD; + input RXDFEAGCOVRDEN; + input RXDFELFHOLD; + input RXDFELFOVRDEN; + input RXDFELPMRESET; + input RXDFETAP10HOLD; + input RXDFETAP10OVRDEN; + input RXDFETAP11HOLD; + input RXDFETAP11OVRDEN; + input RXDFETAP12HOLD; + input RXDFETAP12OVRDEN; + input RXDFETAP13HOLD; + input RXDFETAP13OVRDEN; + input RXDFETAP14HOLD; + input RXDFETAP14OVRDEN; + input RXDFETAP15HOLD; + input RXDFETAP15OVRDEN; + input RXDFETAP2HOLD; + input RXDFETAP2OVRDEN; + input RXDFETAP3HOLD; + input RXDFETAP3OVRDEN; + input RXDFETAP4HOLD; + input RXDFETAP4OVRDEN; + input RXDFETAP5HOLD; + input RXDFETAP5OVRDEN; + input RXDFETAP6HOLD; + input RXDFETAP6OVRDEN; + input RXDFETAP7HOLD; + input RXDFETAP7OVRDEN; + input RXDFETAP8HOLD; + input RXDFETAP8OVRDEN; + input RXDFETAP9HOLD; + input RXDFETAP9OVRDEN; + input RXDFEUTHOLD; + input RXDFEUTOVRDEN; + input RXDFEVPHOLD; + input RXDFEVPOVRDEN; + input RXDFEVSEN; + input RXDFEXYDEN; + input RXDLYBYPASS; + input RXDLYEN; + input RXDLYOVRDEN; + input RXDLYSRESET; + input [1:0] RXELECIDLEMODE; + input RXGEARBOXSLIP; + input RXLATCLK; + input RXLPMEN; + input RXLPMGCHOLD; + input RXLPMGCOVRDEN; + input RXLPMHFHOLD; + input RXLPMHFOVRDEN; + input RXLPMLFHOLD; + input RXLPMLFKLOVRDEN; + input RXLPMOSHOLD; + input RXLPMOSOVRDEN; + input RXMCOMMAALIGNEN; + input [1:0] RXMONITORSEL; + input RXOOBRESET; + input RXOSCALRESET; + input RXOSHOLD; + input [3:0] RXOSINTCFG; + input RXOSINTEN; + input RXOSINTHOLD; + input RXOSINTOVRDEN; + input RXOSINTSTROBE; + input RXOSINTTESTOVRDEN; + input RXOSOVRDEN; + input [2:0] RXOUTCLKSEL; + input RXPCOMMAALIGNEN; + input RXPCSRESET; + input [1:0] RXPD; + input RXPHALIGN; + input RXPHALIGNEN; + input RXPHDLYPD; + input RXPHDLYRESET; + input RXPHOVRDEN; + input [1:0] RXPLLCLKSEL; + input RXPMARESET; + input RXPOLARITY; + input RXPRBSCNTRESET; + input [3:0] RXPRBSSEL; + input RXPROGDIVRESET; + input RXQPIEN; + input [2:0] RXRATE; + input RXRATEMODE; + input RXSLIDE; + input RXSLIPOUTCLK; + input RXSLIPPMA; + input RXSYNCALLIN; + input RXSYNCIN; + input RXSYNCMODE; + input [1:0] RXSYSCLKSEL; + input RXUSERRDY; + input RXUSRCLK; + input RXUSRCLK2; + input SIGVALIDCLK; + input [19:0] TSTIN; + input [7:0] TX8B10BBYPASS; + input TX8B10BEN; + input [2:0] TXBUFDIFFCTRL; + input TXCOMINIT; + input TXCOMSAS; + input TXCOMWAKE; + input [15:0] TXCTRL0; + input [15:0] TXCTRL1; + input [7:0] TXCTRL2; + input [127:0] TXDATA; + input [7:0] TXDATAEXTENDRSVD; + input TXDEEMPH; + input TXDETECTRX; + input [3:0] TXDIFFCTRL; + input TXDIFFPD; + input TXDLYBYPASS; + input TXDLYEN; + input TXDLYHOLD; + input TXDLYOVRDEN; + input TXDLYSRESET; + input TXDLYUPDOWN; + input TXELECIDLE; + input [5:0] TXHEADER; + input TXINHIBIT; + input TXLATCLK; + input [6:0] TXMAINCURSOR; + input [2:0] TXMARGIN; + input [2:0] TXOUTCLKSEL; + input TXPCSRESET; + input [1:0] TXPD; + input TXPDELECIDLEMODE; + input TXPHALIGN; + input TXPHALIGNEN; + input TXPHDLYPD; + input TXPHDLYRESET; + input TXPHDLYTSTCLK; + input TXPHINIT; + input TXPHOVRDEN; + input TXPIPPMEN; + input TXPIPPMOVRDEN; + input TXPIPPMPD; + input TXPIPPMSEL; + input [4:0] TXPIPPMSTEPSIZE; + input TXPISOPD; + input [1:0] TXPLLCLKSEL; + input TXPMARESET; + input TXPOLARITY; + input [4:0] TXPOSTCURSOR; + input TXPOSTCURSORINV; + input TXPRBSFORCEERR; + input [3:0] TXPRBSSEL; + input [4:0] TXPRECURSOR; + input TXPRECURSORINV; + input TXPROGDIVRESET; + input TXQPIBIASEN; + input TXQPISTRONGPDOWN; + input TXQPIWEAKPUP; + input [2:0] TXRATE; + input TXRATEMODE; + input [6:0] TXSEQUENCE; + input TXSWING; + input TXSYNCALLIN; + input TXSYNCIN; + input TXSYNCMODE; + input [1:0] TXSYSCLKSEL; + input TXUSERRDY; + input TXUSRCLK; + input TXUSRCLK2; +endmodule + +module GTHE3_COMMON (...); + parameter [15:0] BIAS_CFG0 = 16'h0000; + parameter [15:0] BIAS_CFG1 = 16'h0000; + parameter [15:0] BIAS_CFG2 = 16'h0000; + parameter [15:0] BIAS_CFG3 = 16'h0000; + parameter [15:0] BIAS_CFG4 = 16'h0000; + parameter [9:0] BIAS_CFG_RSVD = 10'b0000000000; + parameter [15:0] COMMON_CFG0 = 16'h0000; + parameter [15:0] COMMON_CFG1 = 16'h0000; + parameter [15:0] POR_CFG = 16'h0004; + parameter [15:0] QPLL0_CFG0 = 16'h3018; + parameter [15:0] QPLL0_CFG1 = 16'h0000; + parameter [15:0] QPLL0_CFG1_G3 = 16'h0020; + parameter [15:0] QPLL0_CFG2 = 16'h0000; + parameter [15:0] QPLL0_CFG2_G3 = 16'h0000; + parameter [15:0] QPLL0_CFG3 = 16'h0120; + parameter [15:0] QPLL0_CFG4 = 16'h0009; + parameter [9:0] QPLL0_CP = 10'b0000011111; + parameter [9:0] QPLL0_CP_G3 = 10'b0000011111; + parameter integer QPLL0_FBDIV = 66; + parameter integer QPLL0_FBDIV_G3 = 80; + parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000; + parameter [7:0] QPLL0_INIT_CFG1 = 8'h00; + parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8; + parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h01E8; + parameter [9:0] QPLL0_LPF = 10'b1111111111; + parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111; + parameter integer QPLL0_REFCLK_DIV = 2; + parameter [15:0] QPLL0_SDM_CFG0 = 16'b0000000000000000; + parameter [15:0] QPLL0_SDM_CFG1 = 16'b0000000000000000; + parameter [15:0] QPLL0_SDM_CFG2 = 16'b0000000000000000; + parameter [15:0] QPLL1_CFG0 = 16'h3018; + parameter [15:0] QPLL1_CFG1 = 16'h0000; + parameter [15:0] QPLL1_CFG1_G3 = 16'h0020; + parameter [15:0] QPLL1_CFG2 = 16'h0000; + parameter [15:0] QPLL1_CFG2_G3 = 16'h0000; + parameter [15:0] QPLL1_CFG3 = 16'h0120; + parameter [15:0] QPLL1_CFG4 = 16'h0009; + parameter [9:0] QPLL1_CP = 10'b0000011111; + parameter [9:0] QPLL1_CP_G3 = 10'b0000011111; + parameter integer QPLL1_FBDIV = 66; + parameter integer QPLL1_FBDIV_G3 = 80; + parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000; + parameter [7:0] QPLL1_INIT_CFG1 = 8'h00; + parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8; + parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8; + parameter [9:0] QPLL1_LPF = 10'b1111111111; + parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111; + parameter integer QPLL1_REFCLK_DIV = 2; + parameter [15:0] QPLL1_SDM_CFG0 = 16'b0000000000000000; + parameter [15:0] QPLL1_SDM_CFG1 = 16'b0000000000000000; + parameter [15:0] QPLL1_SDM_CFG2 = 16'b0000000000000000; + parameter [15:0] RSVD_ATTR0 = 16'h0000; + parameter [15:0] RSVD_ATTR1 = 16'h0000; + parameter [15:0] RSVD_ATTR2 = 16'h0000; + parameter [15:0] RSVD_ATTR3 = 16'h0000; + parameter [1:0] RXRECCLKOUT0_SEL = 2'b00; + parameter [1:0] RXRECCLKOUT1_SEL = 2'b00; + parameter [0:0] SARC_EN = 1'b1; + parameter [0:0] SARC_SEL = 1'b0; + parameter [15:0] SDM0DATA1_0 = 16'b0000000000000000; + parameter [8:0] SDM0DATA1_1 = 9'b000000000; + parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000; + parameter [8:0] SDM0INITSEED0_1 = 9'b000000000; + parameter [0:0] SDM0_DATA_PIN_SEL = 1'b0; + parameter [0:0] SDM0_WIDTH_PIN_SEL = 1'b0; + parameter [15:0] SDM1DATA1_0 = 16'b0000000000000000; + parameter [8:0] SDM1DATA1_1 = 9'b000000000; + parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000; + parameter [8:0] SDM1INITSEED0_1 = 9'b000000000; + parameter [0:0] SDM1_DATA_PIN_SEL = 1'b0; + parameter [0:0] SDM1_WIDTH_PIN_SEL = 1'b0; + parameter SIM_MODE = "FAST"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter integer SIM_VERSION = 2; + output [15:0] DRPDO; + output DRPRDY; + output [7:0] PMARSVDOUT0; + output [7:0] PMARSVDOUT1; + output QPLL0FBCLKLOST; + output QPLL0LOCK; + output QPLL0OUTCLK; + output QPLL0OUTREFCLK; + output QPLL0REFCLKLOST; + output QPLL1FBCLKLOST; + output QPLL1LOCK; + output QPLL1OUTCLK; + output QPLL1OUTREFCLK; + output QPLL1REFCLKLOST; + output [7:0] QPLLDMONITOR0; + output [7:0] QPLLDMONITOR1; + output REFCLKOUTMONITOR0; + output REFCLKOUTMONITOR1; + output [1:0] RXRECCLK0_SEL; + output [1:0] RXRECCLK1_SEL; + input BGBYPASSB; + input BGMONITORENB; + input BGPDB; + input [4:0] BGRCALOVRD; + input BGRCALOVRDENB; + input [8:0] DRPADDR; + input DRPCLK; + input [15:0] DRPDI; + input DRPEN; + input DRPWE; + input GTGREFCLK0; + input GTGREFCLK1; + input GTNORTHREFCLK00; + input GTNORTHREFCLK01; + input GTNORTHREFCLK10; + input GTNORTHREFCLK11; + input GTREFCLK00; + input GTREFCLK01; + input GTREFCLK10; + input GTREFCLK11; + input GTSOUTHREFCLK00; + input GTSOUTHREFCLK01; + input GTSOUTHREFCLK10; + input GTSOUTHREFCLK11; + input [7:0] PMARSVD0; + input [7:0] PMARSVD1; + input QPLL0CLKRSVD0; + input QPLL0CLKRSVD1; + input QPLL0LOCKDETCLK; + input QPLL0LOCKEN; + input QPLL0PD; + input [2:0] QPLL0REFCLKSEL; + input QPLL0RESET; + input QPLL1CLKRSVD0; + input QPLL1CLKRSVD1; + input QPLL1LOCKDETCLK; + input QPLL1LOCKEN; + input QPLL1PD; + input [2:0] QPLL1REFCLKSEL; + input QPLL1RESET; + input [7:0] QPLLRSVD1; + input [4:0] QPLLRSVD2; + input [4:0] QPLLRSVD3; + input [7:0] QPLLRSVD4; + input RCALENB; +endmodule + +module GTYE3_CHANNEL (...); + parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; + parameter [0:0] ACJTAG_MODE = 1'b0; + parameter [0:0] ACJTAG_RESET = 1'b0; + parameter [15:0] ADAPT_CFG0 = 16'h9200; + parameter [15:0] ADAPT_CFG1 = 16'h801C; + parameter [15:0] ADAPT_CFG2 = 16'b0000000000000000; + parameter ALIGN_COMMA_DOUBLE = "FALSE"; + parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; + parameter integer ALIGN_COMMA_WORD = 1; + parameter ALIGN_MCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; + parameter ALIGN_PCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; + parameter [0:0] AUTO_BW_SEL_BYPASS = 1'b0; + parameter [0:0] A_RXOSCALRESET = 1'b0; + parameter [0:0] A_RXPROGDIVRESET = 1'b0; + parameter [4:0] A_TXDIFFCTRL = 5'b01100; + parameter [0:0] A_TXPROGDIVRESET = 1'b0; + parameter [0:0] CAPBYPASS_FORCE = 1'b0; + parameter CBCC_DATA_SOURCE_SEL = "DECODED"; + parameter [0:0] CDR_SWAP_MODE_EN = 1'b0; + parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; + parameter integer CHAN_BOND_MAX_SKEW = 7; + parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; + parameter CHAN_BOND_SEQ_2_USE = "FALSE"; + parameter integer CHAN_BOND_SEQ_LEN = 2; + parameter [15:0] CH_HSPMUX = 16'h0000; + parameter [15:0] CKCAL1_CFG_0 = 16'b0000000000000000; + parameter [15:0] CKCAL1_CFG_1 = 16'b0000000000000000; + parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000; + parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_0 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_1 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000; + parameter [15:0] CKCAL_RSVD0 = 16'h0000; + parameter [15:0] CKCAL_RSVD1 = 16'h0000; + parameter CLK_CORRECT_USE = "TRUE"; + parameter CLK_COR_KEEP_IDLE = "FALSE"; + parameter integer CLK_COR_MAX_LAT = 20; + parameter integer CLK_COR_MIN_LAT = 18; + parameter CLK_COR_PRECEDENCE = "TRUE"; + parameter integer CLK_COR_REPEAT_WAIT = 0; + parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; + parameter CLK_COR_SEQ_2_USE = "FALSE"; + parameter integer CLK_COR_SEQ_LEN = 2; + parameter [15:0] CPLL_CFG0 = 16'h20F8; + parameter [15:0] CPLL_CFG1 = 16'hA494; + parameter [15:0] CPLL_CFG2 = 16'hF001; + parameter [5:0] CPLL_CFG3 = 6'h00; + parameter integer CPLL_FBDIV = 4; + parameter integer CPLL_FBDIV_45 = 4; + parameter [15:0] CPLL_INIT_CFG0 = 16'h001E; + parameter [7:0] CPLL_INIT_CFG1 = 8'h00; + parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; + parameter integer CPLL_REFCLK_DIV = 1; + parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000; + parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0; + parameter [1:0] DDI_CTRL = 2'b00; + parameter integer DDI_REALIGN_WAIT = 15; + parameter DEC_MCOMMA_DETECT = "TRUE"; + parameter DEC_PCOMMA_DETECT = "TRUE"; + parameter DEC_VALID_COMMA_ONLY = "TRUE"; + parameter [0:0] DFE_D_X_REL_POS = 1'b0; + parameter [0:0] DFE_VCM_COMP_EN = 1'b0; + parameter [9:0] DMONITOR_CFG0 = 10'h000; + parameter [7:0] DMONITOR_CFG1 = 8'h00; + parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; + parameter [5:0] ES_CONTROL = 6'b000000; + parameter ES_ERRDET_EN = "FALSE"; + parameter ES_EYE_SCAN_EN = "FALSE"; + parameter [11:0] ES_HORZ_OFFSET = 12'h000; + parameter [9:0] ES_PMA_CFG = 10'b0000000000; + parameter [4:0] ES_PRESCALE = 5'b00000; + parameter [15:0] ES_QUALIFIER0 = 16'h0000; + parameter [15:0] ES_QUALIFIER1 = 16'h0000; + parameter [15:0] ES_QUALIFIER2 = 16'h0000; + parameter [15:0] ES_QUALIFIER3 = 16'h0000; + parameter [15:0] ES_QUALIFIER4 = 16'h0000; + parameter [15:0] ES_QUALIFIER5 = 16'h0000; + parameter [15:0] ES_QUALIFIER6 = 16'h0000; + parameter [15:0] ES_QUALIFIER7 = 16'h0000; + parameter [15:0] ES_QUALIFIER8 = 16'h0000; + parameter [15:0] ES_QUALIFIER9 = 16'h0000; + parameter [15:0] ES_QUAL_MASK0 = 16'h0000; + parameter [15:0] ES_QUAL_MASK1 = 16'h0000; + parameter [15:0] ES_QUAL_MASK2 = 16'h0000; + parameter [15:0] ES_QUAL_MASK3 = 16'h0000; + parameter [15:0] ES_QUAL_MASK4 = 16'h0000; + parameter [15:0] ES_QUAL_MASK5 = 16'h0000; + parameter [15:0] ES_QUAL_MASK6 = 16'h0000; + parameter [15:0] ES_QUAL_MASK7 = 16'h0000; + parameter [15:0] ES_QUAL_MASK8 = 16'h0000; + parameter [15:0] ES_QUAL_MASK9 = 16'h0000; + parameter [15:0] ES_SDATA_MASK0 = 16'h0000; + parameter [15:0] ES_SDATA_MASK1 = 16'h0000; + parameter [15:0] ES_SDATA_MASK2 = 16'h0000; + parameter [15:0] ES_SDATA_MASK3 = 16'h0000; + parameter [15:0] ES_SDATA_MASK4 = 16'h0000; + parameter [15:0] ES_SDATA_MASK5 = 16'h0000; + parameter [15:0] ES_SDATA_MASK6 = 16'h0000; + parameter [15:0] ES_SDATA_MASK7 = 16'h0000; + parameter [15:0] ES_SDATA_MASK8 = 16'h0000; + parameter [15:0] ES_SDATA_MASK9 = 16'h0000; + parameter [10:0] EVODD_PHI_CFG = 11'b00000000000; + parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0; + parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; + parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; + parameter FTS_LANE_DESKEW_EN = "FALSE"; + parameter [4:0] GEARBOX_MODE = 5'b00000; + parameter [0:0] GM_BIAS_SELECT = 1'b0; + parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0; + parameter [0:0] LOCAL_MASTER = 1'b0; + parameter [15:0] LOOP0_CFG = 16'h0000; + parameter [15:0] LOOP10_CFG = 16'h0000; + parameter [15:0] LOOP11_CFG = 16'h0000; + parameter [15:0] LOOP12_CFG = 16'h0000; + parameter [15:0] LOOP13_CFG = 16'h0000; + parameter [15:0] LOOP1_CFG = 16'h0000; + parameter [15:0] LOOP2_CFG = 16'h0000; + parameter [15:0] LOOP3_CFG = 16'h0000; + parameter [15:0] LOOP4_CFG = 16'h0000; + parameter [15:0] LOOP5_CFG = 16'h0000; + parameter [15:0] LOOP6_CFG = 16'h0000; + parameter [15:0] LOOP7_CFG = 16'h0000; + parameter [15:0] LOOP8_CFG = 16'h0000; + parameter [15:0] LOOP9_CFG = 16'h0000; + parameter [2:0] LPBK_BIAS_CTRL = 3'b000; + parameter [0:0] LPBK_EN_RCAL_B = 1'b0; + parameter [3:0] LPBK_EXT_RCAL = 4'b0000; + parameter [3:0] LPBK_RG_CTRL = 4'b0000; + parameter [1:0] OOBDIVCTL = 2'b00; + parameter [0:0] OOB_PWRUP = 1'b0; + parameter PCI3_AUTO_REALIGN = "FRST_SMPL"; + parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1; + parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00; + parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0; + parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000; + parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000; + parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000; + parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0; + parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0; + parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000; + parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000; + parameter [15:0] PCIE_RXPMA_CFG = 16'h0000; + parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000; + parameter [15:0] PCIE_TXPMA_CFG = 16'h0000; + parameter PCS_PCIE_EN = "FALSE"; + parameter [15:0] PCS_RSVD0 = 16'b0000000000000000; + parameter [2:0] PCS_RSVD1 = 3'b000; + parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; + parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; + parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; + parameter [1:0] PLL_SEL_MODE_GEN12 = 2'h0; + parameter [1:0] PLL_SEL_MODE_GEN3 = 2'h0; + parameter [15:0] PMA_RSV0 = 16'h0000; + parameter [15:0] PMA_RSV1 = 16'h0000; + parameter integer PREIQ_FREQ_BST = 0; + parameter [2:0] PROCESS_PAR = 3'b010; + parameter [0:0] RATE_SW_USE_DRP = 1'b0; + parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0; + parameter [4:0] RXBUFRESET_TIME = 5'b00001; + parameter RXBUF_ADDR_MODE = "FULL"; + parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; + parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; + parameter RXBUF_EN = "TRUE"; + parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; + parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; + parameter RXBUF_RESET_ON_EIDLE = "FALSE"; + parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; + parameter integer RXBUF_THRESH_OVFLW = 0; + parameter RXBUF_THRESH_OVRD = "FALSE"; + parameter integer RXBUF_THRESH_UNDFLW = 4; + parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; + parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; + parameter [15:0] RXCDR_CFG0 = 16'h0000; + parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0000; + parameter [15:0] RXCDR_CFG1 = 16'h0300; + parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0300; + parameter [15:0] RXCDR_CFG2 = 16'h0060; + parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0060; + parameter [15:0] RXCDR_CFG3 = 16'h0000; + parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0000; + parameter [15:0] RXCDR_CFG4 = 16'h0002; + parameter [15:0] RXCDR_CFG4_GEN3 = 16'h0002; + parameter [15:0] RXCDR_CFG5 = 16'h0000; + parameter [15:0] RXCDR_CFG5_GEN3 = 16'h0000; + parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; + parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; + parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0001; + parameter [15:0] RXCDR_LOCK_CFG1 = 16'h0000; + parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000; + parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000; + parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; + parameter [1:0] RXCFOKDONE_SRC = 2'b00; + parameter [15:0] RXCFOK_CFG0 = 16'h3E00; + parameter [15:0] RXCFOK_CFG1 = 16'h0042; + parameter [15:0] RXCFOK_CFG2 = 16'h002D; + parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; + parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000; + parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022; + parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100; + parameter [15:0] RXDFE_CFG0 = 16'h4C00; + parameter [15:0] RXDFE_CFG1 = 16'h0000; + parameter [15:0] RXDFE_GC_CFG0 = 16'h1E00; + parameter [15:0] RXDFE_GC_CFG1 = 16'h1900; + parameter [15:0] RXDFE_GC_CFG2 = 16'h0000; + parameter [15:0] RXDFE_H2_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H2_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H3_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H3_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H4_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H4_CFG1 = 16'h0003; + parameter [15:0] RXDFE_H5_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H5_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H6_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H6_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H7_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H7_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H8_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H8_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H9_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H9_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HA_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HA_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HB_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HB_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HC_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HC_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HD_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HD_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HE_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HE_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HF_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HF_CFG1 = 16'h0002; + parameter [15:0] RXDFE_OS_CFG0 = 16'h0000; + parameter [15:0] RXDFE_OS_CFG1 = 16'h0200; + parameter [0:0] RXDFE_PWR_SAVING = 1'b0; + parameter [15:0] RXDFE_UT_CFG0 = 16'h0000; + parameter [15:0] RXDFE_UT_CFG1 = 16'h0002; + parameter [15:0] RXDFE_VP_CFG0 = 16'h0000; + parameter [15:0] RXDFE_VP_CFG1 = 16'h0022; + parameter [15:0] RXDLY_CFG = 16'h001F; + parameter [15:0] RXDLY_LCFG = 16'h0030; + parameter RXELECIDLE_CFG = "SIGCFG_4"; + parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4; + parameter RXGEARBOX_EN = "FALSE"; + parameter [4:0] RXISCANRESET_TIME = 5'b00001; + parameter [15:0] RXLPM_CFG = 16'h0000; + parameter [15:0] RXLPM_GC_CFG = 16'h0200; + parameter [15:0] RXLPM_KH_CFG0 = 16'h0000; + parameter [15:0] RXLPM_KH_CFG1 = 16'h0002; + parameter [15:0] RXLPM_OS_CFG0 = 16'h0400; + parameter [15:0] RXLPM_OS_CFG1 = 16'h0000; + parameter [8:0] RXOOB_CFG = 9'b000000110; + parameter RXOOB_CLK_CFG = "PMA"; + parameter [4:0] RXOSCALRESET_TIME = 5'b00011; + parameter integer RXOUT_DIV = 4; + parameter [4:0] RXPCSRESET_TIME = 5'b00001; + parameter [15:0] RXPHBEACON_CFG = 16'h0000; + parameter [15:0] RXPHDLY_CFG = 16'h2020; + parameter [15:0] RXPHSAMP_CFG = 16'h2100; + parameter [15:0] RXPHSLIP_CFG = 16'h9933; + parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; + parameter [0:0] RXPI_AUTO_BW_SEL_BYPASS = 1'b0; + parameter [15:0] RXPI_CFG = 16'h0100; + parameter [0:0] RXPI_LPM = 1'b0; + parameter [15:0] RXPI_RSV0 = 16'h0000; + parameter [1:0] RXPI_SEL_LC = 2'b00; + parameter [1:0] RXPI_STARTCODE = 2'b00; + parameter [0:0] RXPI_VREFSEL = 1'b0; + parameter RXPMACLK_SEL = "DATA"; + parameter [4:0] RXPMARESET_TIME = 5'b00001; + parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; + parameter integer RXPRBS_LINKACQ_CNT = 15; + parameter integer RXSLIDE_AUTO_WAIT = 7; + parameter RXSLIDE_MODE = "OFF"; + parameter [0:0] RXSYNC_MULTILANE = 1'b0; + parameter [0:0] RXSYNC_OVRD = 1'b0; + parameter [0:0] RXSYNC_SKIP_DA = 1'b0; + parameter [0:0] RX_AFE_CM_EN = 1'b0; + parameter [15:0] RX_BIAS_CFG0 = 16'h1534; + parameter [5:0] RX_BUFFER_CFG = 6'b000000; + parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0; + parameter integer RX_CLK25_DIV = 8; + parameter [0:0] RX_CLKMUX_EN = 1'b1; + parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000; + parameter [3:0] RX_CM_BUF_CFG = 4'b1010; + parameter [0:0] RX_CM_BUF_PD = 1'b0; + parameter integer RX_CM_SEL = 3; + parameter integer RX_CM_TRIM = 10; + parameter [0:0] RX_CTLE1_KHKL = 1'b0; + parameter [0:0] RX_CTLE2_KHKL = 1'b0; + parameter [0:0] RX_CTLE3_AGC = 1'b0; + parameter integer RX_DATA_WIDTH = 20; + parameter [5:0] RX_DDI_SEL = 6'b000000; + parameter RX_DEFER_RESET_BUF_EN = "TRUE"; + parameter [2:0] RX_DEGEN_CTRL = 3'b010; + parameter integer RX_DFELPM_CFG0 = 6; + parameter [0:0] RX_DFELPM_CFG1 = 1'b0; + parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1; + parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00; + parameter integer RX_DFE_AGC_CFG1 = 4; + parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1; + parameter integer RX_DFE_KL_LPM_KH_CFG1 = 2; + parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01; + parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010; + parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; + parameter RX_DISPERR_SEQ_MATCH = "TRUE"; + parameter [0:0] RX_DIV2_MODE_B = 1'b0; + parameter [4:0] RX_DIVRESET_TIME = 5'b00001; + parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0; + parameter [0:0] RX_EN_HI_LR = 1'b0; + parameter [8:0] RX_EXT_RL_CTRL = 9'b000000000; + parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000; + parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0; + parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00; + parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0; + parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0; + parameter integer RX_INT_DATAWIDTH = 1; + parameter [0:0] RX_PMA_POWER_SAVE = 1'b0; + parameter real RX_PROGDIV_CFG = 0.0; + parameter [15:0] RX_PROGDIV_RATE = 16'h0001; + parameter [3:0] RX_RESLOAD_CTRL = 4'b0000; + parameter [0:0] RX_RESLOAD_OVRD = 1'b0; + parameter [2:0] RX_SAMPLE_PERIOD = 3'b101; + parameter integer RX_SIG_VALID_DLY = 11; + parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0; + parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000; + parameter [3:0] RX_SUM_VCMTUNE = 4'b1000; + parameter [0:0] RX_SUM_VCM_OVWR = 1'b0; + parameter [2:0] RX_SUM_VREF_TUNE = 3'b100; + parameter [1:0] RX_TUNE_AFE_OS = 2'b00; + parameter [2:0] RX_VREG_CTRL = 3'b101; + parameter [0:0] RX_VREG_PDB = 1'b1; + parameter [1:0] RX_WIDEMODE_CDR = 2'b01; + parameter RX_XCLK_SEL = "RXDES"; + parameter [0:0] RX_XMODE_SEL = 1'b0; + parameter integer SAS_MAX_COM = 64; + parameter integer SAS_MIN_COM = 36; + parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; + parameter [2:0] SATA_BURST_VAL = 3'b100; + parameter SATA_CPLL_CFG = "VCO_3000MHZ"; + parameter [2:0] SATA_EIDLE_VAL = 3'b100; + parameter integer SATA_MAX_BURST = 8; + parameter integer SATA_MAX_INIT = 21; + parameter integer SATA_MAX_WAKE = 7; + parameter integer SATA_MIN_BURST = 4; + parameter integer SATA_MIN_INIT = 12; + parameter integer SATA_MIN_WAKE = 4; + parameter SHOW_REALIGN_COMMA = "TRUE"; + parameter SIM_MODE = "FAST"; + parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter [0:0] SIM_TX_EIDLE_DRIVE_LEVEL = 1'b0; + parameter integer SIM_VERSION = 2; + parameter [1:0] TAPDLY_SET_TX = 2'h0; + parameter [3:0] TEMPERATURE_PAR = 4'b0010; + parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; + parameter [2:0] TERM_RCAL_OVRD = 3'b000; + parameter [7:0] TRANS_TIME_RATE = 8'h0E; + parameter [7:0] TST_RSV0 = 8'h00; + parameter [7:0] TST_RSV1 = 8'h00; + parameter TXBUF_EN = "TRUE"; + parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; + parameter [15:0] TXDLY_CFG = 16'h001F; + parameter [15:0] TXDLY_LCFG = 16'h0030; + parameter TXFIFO_ADDR_CFG = "LOW"; + parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4; + parameter TXGEARBOX_EN = "FALSE"; + parameter integer TXOUT_DIV = 4; + parameter [4:0] TXPCSRESET_TIME = 5'b00001; + parameter [15:0] TXPHDLY_CFG0 = 16'h2020; + parameter [15:0] TXPHDLY_CFG1 = 16'h0001; + parameter [15:0] TXPH_CFG = 16'h0123; + parameter [15:0] TXPH_CFG2 = 16'h0000; + parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; + parameter [1:0] TXPI_CFG0 = 2'b00; + parameter [1:0] TXPI_CFG1 = 2'b00; + parameter [1:0] TXPI_CFG2 = 2'b00; + parameter [0:0] TXPI_CFG3 = 1'b0; + parameter [0:0] TXPI_CFG4 = 1'b1; + parameter [2:0] TXPI_CFG5 = 3'b000; + parameter [0:0] TXPI_GRAY_SEL = 1'b0; + parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; + parameter [0:0] TXPI_LPM = 1'b0; + parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; + parameter [7:0] TXPI_PPM_CFG = 8'b00000000; + parameter [15:0] TXPI_RSV0 = 16'h0000; + parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; + parameter [0:0] TXPI_VREFSEL = 1'b0; + parameter [4:0] TXPMARESET_TIME = 5'b00001; + parameter [0:0] TXSYNC_MULTILANE = 1'b0; + parameter [0:0] TXSYNC_OVRD = 1'b0; + parameter [0:0] TXSYNC_SKIP_DA = 1'b0; + parameter integer TX_CLK25_DIV = 8; + parameter [0:0] TX_CLKMUX_EN = 1'b1; + parameter [0:0] TX_CLKREG_PDB = 1'b0; + parameter [2:0] TX_CLKREG_SET = 3'b000; + parameter integer TX_DATA_WIDTH = 20; + parameter [5:0] TX_DCD_CFG = 6'b000010; + parameter [0:0] TX_DCD_EN = 1'b0; + parameter [5:0] TX_DEEMPH0 = 6'b000000; + parameter [5:0] TX_DEEMPH1 = 6'b000000; + parameter [4:0] TX_DIVRESET_TIME = 5'b00001; + parameter TX_DRIVE_MODE = "DIRECT"; + parameter integer TX_DRVMUX_CTRL = 2; + parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; + parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; + parameter [0:0] TX_EML_PHI_TUNE = 1'b0; + parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0; + parameter [0:0] TX_FIFO_BYP_EN = 1'b0; + parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0; + parameter integer TX_INT_DATAWIDTH = 1; + parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; + parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; + parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; + parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; + parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; + parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; + parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; + parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; + parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; + parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; + parameter [2:0] TX_MODE_SEL = 3'b000; + parameter [15:0] TX_PHICAL_CFG0 = 16'h0000; + parameter [15:0] TX_PHICAL_CFG1 = 16'h7E00; + parameter [15:0] TX_PHICAL_CFG2 = 16'h0000; + parameter integer TX_PI_BIASSET = 0; + parameter [15:0] TX_PI_CFG0 = 16'h0000; + parameter [15:0] TX_PI_CFG1 = 16'h0000; + parameter [0:0] TX_PI_DIV2_MODE_B = 1'b0; + parameter [0:0] TX_PI_SEL_QPLL0 = 1'b0; + parameter [0:0] TX_PI_SEL_QPLL1 = 1'b0; + parameter [0:0] TX_PMADATA_OPT = 1'b0; + parameter [0:0] TX_PMA_POWER_SAVE = 1'b0; + parameter integer TX_PREDRV_CTRL = 2; + parameter TX_PROGCLK_SEL = "POSTPI"; + parameter real TX_PROGDIV_CFG = 0.0; + parameter [15:0] TX_PROGDIV_RATE = 16'h0001; + parameter [13:0] TX_RXDETECT_CFG = 14'h0032; + parameter integer TX_RXDETECT_REF = 4; + parameter [2:0] TX_SAMPLE_PERIOD = 3'b101; + parameter [0:0] TX_SARC_LPBK_ENB = 1'b0; + parameter TX_XCLK_SEL = "TXOUT"; + parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; + output [2:0] BUFGTCE; + output [2:0] BUFGTCEMASK; + output [8:0] BUFGTDIV; + output [2:0] BUFGTRESET; + output [2:0] BUFGTRSTMASK; + output CPLLFBCLKLOST; + output CPLLLOCK; + output CPLLREFCLKLOST; + output [16:0] DMONITOROUT; + output [15:0] DRPDO; + output DRPRDY; + output EYESCANDATAERROR; + output GTPOWERGOOD; + output GTREFCLKMONITOR; + output GTYTXN; + output GTYTXP; + output PCIERATEGEN3; + output PCIERATEIDLE; + output [1:0] PCIERATEQPLLPD; + output [1:0] PCIERATEQPLLRESET; + output PCIESYNCTXSYNCDONE; + output PCIEUSERGEN3RDY; + output PCIEUSERPHYSTATUSRST; + output PCIEUSERRATESTART; + output [15:0] PCSRSVDOUT; + output PHYSTATUS; + output [7:0] PINRSRVDAS; + output RESETEXCEPTION; + output [2:0] RXBUFSTATUS; + output RXBYTEISALIGNED; + output RXBYTEREALIGN; + output RXCDRLOCK; + output RXCDRPHDONE; + output RXCHANBONDSEQ; + output RXCHANISALIGNED; + output RXCHANREALIGN; + output [4:0] RXCHBONDO; + output RXCKCALDONE; + output [1:0] RXCLKCORCNT; + output RXCOMINITDET; + output RXCOMMADET; + output RXCOMSASDET; + output RXCOMWAKEDET; + output [15:0] RXCTRL0; + output [15:0] RXCTRL1; + output [7:0] RXCTRL2; + output [7:0] RXCTRL3; + output [127:0] RXDATA; + output [7:0] RXDATAEXTENDRSVD; + output [1:0] RXDATAVALID; + output RXDLYSRESETDONE; + output RXELECIDLE; + output [5:0] RXHEADER; + output [1:0] RXHEADERVALID; + output [6:0] RXMONITOROUT; + output RXOSINTDONE; + output RXOSINTSTARTED; + output RXOSINTSTROBEDONE; + output RXOSINTSTROBESTARTED; + output RXOUTCLK; + output RXOUTCLKFABRIC; + output RXOUTCLKPCS; + output RXPHALIGNDONE; + output RXPHALIGNERR; + output RXPMARESETDONE; + output RXPRBSERR; + output RXPRBSLOCKED; + output RXPRGDIVRESETDONE; + output RXRATEDONE; + output RXRECCLKOUT; + output RXRESETDONE; + output RXSLIDERDY; + output RXSLIPDONE; + output RXSLIPOUTCLKRDY; + output RXSLIPPMARDY; + output [1:0] RXSTARTOFSEQ; + output [2:0] RXSTATUS; + output RXSYNCDONE; + output RXSYNCOUT; + output RXVALID; + output [1:0] TXBUFSTATUS; + output TXCOMFINISH; + output TXDCCDONE; + output TXDLYSRESETDONE; + output TXOUTCLK; + output TXOUTCLKFABRIC; + output TXOUTCLKPCS; + output TXPHALIGNDONE; + output TXPHINITDONE; + output TXPMARESETDONE; + output TXPRGDIVRESETDONE; + output TXRATEDONE; + output TXRESETDONE; + output TXSYNCDONE; + output TXSYNCOUT; + input CDRSTEPDIR; + input CDRSTEPSQ; + input CDRSTEPSX; + input CFGRESET; + input CLKRSVD0; + input CLKRSVD1; + input CPLLLOCKDETCLK; + input CPLLLOCKEN; + input CPLLPD; + input [2:0] CPLLREFCLKSEL; + input CPLLRESET; + input DMONFIFORESET; + input DMONITORCLK; + input [9:0] DRPADDR; + input DRPCLK; + input [15:0] DRPDI; + input DRPEN; + input DRPWE; + input ELPCALDVORWREN; + input ELPCALPAORWREN; + input EVODDPHICALDONE; + input EVODDPHICALSTART; + input EVODDPHIDRDEN; + input EVODDPHIDWREN; + input EVODDPHIXRDEN; + input EVODDPHIXWREN; + input EYESCANMODE; + input EYESCANRESET; + input EYESCANTRIGGER; + input GTGREFCLK; + input GTNORTHREFCLK0; + input GTNORTHREFCLK1; + input GTREFCLK0; + input GTREFCLK1; + input GTRESETSEL; + input [15:0] GTRSVD; + input GTRXRESET; + input GTSOUTHREFCLK0; + input GTSOUTHREFCLK1; + input GTTXRESET; + input GTYRXN; + input GTYRXP; + input [2:0] LOOPBACK; + input [15:0] LOOPRSVD; + input LPBKRXTXSEREN; + input LPBKTXRXSEREN; + input PCIEEQRXEQADAPTDONE; + input PCIERSTIDLE; + input PCIERSTTXSYNCSTART; + input PCIEUSERRATEDONE; + input [15:0] PCSRSVDIN; + input [4:0] PCSRSVDIN2; + input [4:0] PMARSVDIN; + input QPLL0CLK; + input QPLL0REFCLK; + input QPLL1CLK; + input QPLL1REFCLK; + input RESETOVRD; + input RSTCLKENTX; + input RX8B10BEN; + input RXBUFRESET; + input RXCDRFREQRESET; + input RXCDRHOLD; + input RXCDROVRDEN; + input RXCDRRESET; + input RXCDRRESETRSV; + input RXCHBONDEN; + input [4:0] RXCHBONDI; + input [2:0] RXCHBONDLEVEL; + input RXCHBONDMASTER; + input RXCHBONDSLAVE; + input RXCKCALRESET; + input RXCOMMADETEN; + input RXDCCFORCESTART; + input RXDFEAGCHOLD; + input RXDFEAGCOVRDEN; + input RXDFELFHOLD; + input RXDFELFOVRDEN; + input RXDFELPMRESET; + input RXDFETAP10HOLD; + input RXDFETAP10OVRDEN; + input RXDFETAP11HOLD; + input RXDFETAP11OVRDEN; + input RXDFETAP12HOLD; + input RXDFETAP12OVRDEN; + input RXDFETAP13HOLD; + input RXDFETAP13OVRDEN; + input RXDFETAP14HOLD; + input RXDFETAP14OVRDEN; + input RXDFETAP15HOLD; + input RXDFETAP15OVRDEN; + input RXDFETAP2HOLD; + input RXDFETAP2OVRDEN; + input RXDFETAP3HOLD; + input RXDFETAP3OVRDEN; + input RXDFETAP4HOLD; + input RXDFETAP4OVRDEN; + input RXDFETAP5HOLD; + input RXDFETAP5OVRDEN; + input RXDFETAP6HOLD; + input RXDFETAP6OVRDEN; + input RXDFETAP7HOLD; + input RXDFETAP7OVRDEN; + input RXDFETAP8HOLD; + input RXDFETAP8OVRDEN; + input RXDFETAP9HOLD; + input RXDFETAP9OVRDEN; + input RXDFEUTHOLD; + input RXDFEUTOVRDEN; + input RXDFEVPHOLD; + input RXDFEVPOVRDEN; + input RXDFEVSEN; + input RXDFEXYDEN; + input RXDLYBYPASS; + input RXDLYEN; + input RXDLYOVRDEN; + input RXDLYSRESET; + input [1:0] RXELECIDLEMODE; + input RXGEARBOXSLIP; + input RXLATCLK; + input RXLPMEN; + input RXLPMGCHOLD; + input RXLPMGCOVRDEN; + input RXLPMHFHOLD; + input RXLPMHFOVRDEN; + input RXLPMLFHOLD; + input RXLPMLFKLOVRDEN; + input RXLPMOSHOLD; + input RXLPMOSOVRDEN; + input RXMCOMMAALIGNEN; + input [1:0] RXMONITORSEL; + input RXOOBRESET; + input RXOSCALRESET; + input RXOSHOLD; + input [3:0] RXOSINTCFG; + input RXOSINTEN; + input RXOSINTHOLD; + input RXOSINTOVRDEN; + input RXOSINTSTROBE; + input RXOSINTTESTOVRDEN; + input RXOSOVRDEN; + input [2:0] RXOUTCLKSEL; + input RXPCOMMAALIGNEN; + input RXPCSRESET; + input [1:0] RXPD; + input RXPHALIGN; + input RXPHALIGNEN; + input RXPHDLYPD; + input RXPHDLYRESET; + input RXPHOVRDEN; + input [1:0] RXPLLCLKSEL; + input RXPMARESET; + input RXPOLARITY; + input RXPRBSCNTRESET; + input [3:0] RXPRBSSEL; + input RXPROGDIVRESET; + input [2:0] RXRATE; + input RXRATEMODE; + input RXSLIDE; + input RXSLIPOUTCLK; + input RXSLIPPMA; + input RXSYNCALLIN; + input RXSYNCIN; + input RXSYNCMODE; + input [1:0] RXSYSCLKSEL; + input RXUSERRDY; + input RXUSRCLK; + input RXUSRCLK2; + input SIGVALIDCLK; + input [19:0] TSTIN; + input [7:0] TX8B10BBYPASS; + input TX8B10BEN; + input [2:0] TXBUFDIFFCTRL; + input TXCOMINIT; + input TXCOMSAS; + input TXCOMWAKE; + input [15:0] TXCTRL0; + input [15:0] TXCTRL1; + input [7:0] TXCTRL2; + input [127:0] TXDATA; + input [7:0] TXDATAEXTENDRSVD; + input TXDCCFORCESTART; + input TXDCCRESET; + input TXDEEMPH; + input TXDETECTRX; + input [4:0] TXDIFFCTRL; + input TXDIFFPD; + input TXDLYBYPASS; + input TXDLYEN; + input TXDLYHOLD; + input TXDLYOVRDEN; + input TXDLYSRESET; + input TXDLYUPDOWN; + input TXELECIDLE; + input TXELFORCESTART; + input [5:0] TXHEADER; + input TXINHIBIT; + input TXLATCLK; + input [6:0] TXMAINCURSOR; + input [2:0] TXMARGIN; + input [2:0] TXOUTCLKSEL; + input TXPCSRESET; + input [1:0] TXPD; + input TXPDELECIDLEMODE; + input TXPHALIGN; + input TXPHALIGNEN; + input TXPHDLYPD; + input TXPHDLYRESET; + input TXPHDLYTSTCLK; + input TXPHINIT; + input TXPHOVRDEN; + input TXPIPPMEN; + input TXPIPPMOVRDEN; + input TXPIPPMPD; + input TXPIPPMSEL; + input [4:0] TXPIPPMSTEPSIZE; + input TXPISOPD; + input [1:0] TXPLLCLKSEL; + input TXPMARESET; + input TXPOLARITY; + input [4:0] TXPOSTCURSOR; + input TXPRBSFORCEERR; + input [3:0] TXPRBSSEL; + input [4:0] TXPRECURSOR; + input TXPROGDIVRESET; + input [2:0] TXRATE; + input TXRATEMODE; + input [6:0] TXSEQUENCE; + input TXSWING; + input TXSYNCALLIN; + input TXSYNCIN; + input TXSYNCMODE; + input [1:0] TXSYSCLKSEL; + input TXUSERRDY; + input TXUSRCLK; + input TXUSRCLK2; +endmodule + +module GTYE3_COMMON (...); + parameter [15:0] A_SDM1DATA1_0 = 16'b0000000000000000; + parameter [8:0] A_SDM1DATA1_1 = 9'b000000000; + parameter [15:0] BIAS_CFG0 = 16'h0000; + parameter [15:0] BIAS_CFG1 = 16'h0000; + parameter [15:0] BIAS_CFG2 = 16'h0000; + parameter [15:0] BIAS_CFG3 = 16'h0000; + parameter [15:0] BIAS_CFG4 = 16'h0000; + parameter [9:0] BIAS_CFG_RSVD = 10'b0000000000; + parameter [15:0] COMMON_CFG0 = 16'h0000; + parameter [15:0] COMMON_CFG1 = 16'h0000; + parameter [15:0] POR_CFG = 16'h0004; + parameter [15:0] PPF0_CFG = 16'h0FFF; + parameter [15:0] PPF1_CFG = 16'h0FFF; + parameter QPLL0CLKOUT_RATE = "FULL"; + parameter [15:0] QPLL0_CFG0 = 16'h301C; + parameter [15:0] QPLL0_CFG1 = 16'h0000; + parameter [15:0] QPLL0_CFG1_G3 = 16'h0020; + parameter [15:0] QPLL0_CFG2 = 16'h0780; + parameter [15:0] QPLL0_CFG2_G3 = 16'h0780; + parameter [15:0] QPLL0_CFG3 = 16'h0120; + parameter [15:0] QPLL0_CFG4 = 16'h0021; + parameter [9:0] QPLL0_CP = 10'b0000011111; + parameter [9:0] QPLL0_CP_G3 = 10'b0000011111; + parameter integer QPLL0_FBDIV = 66; + parameter integer QPLL0_FBDIV_G3 = 80; + parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000; + parameter [7:0] QPLL0_INIT_CFG1 = 8'h00; + parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8; + parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8; + parameter [9:0] QPLL0_LPF = 10'b1111111111; + parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111; + parameter integer QPLL0_REFCLK_DIV = 2; + parameter [15:0] QPLL0_SDM_CFG0 = 16'h0040; + parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000; + parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000; + parameter QPLL1CLKOUT_RATE = "FULL"; + parameter [15:0] QPLL1_CFG0 = 16'h301C; + parameter [15:0] QPLL1_CFG1 = 16'h0000; + parameter [15:0] QPLL1_CFG1_G3 = 16'h0020; + parameter [15:0] QPLL1_CFG2 = 16'h0780; + parameter [15:0] QPLL1_CFG2_G3 = 16'h0780; + parameter [15:0] QPLL1_CFG3 = 16'h0120; + parameter [15:0] QPLL1_CFG4 = 16'h0021; + parameter [9:0] QPLL1_CP = 10'b0000011111; + parameter [9:0] QPLL1_CP_G3 = 10'b0000011111; + parameter integer QPLL1_FBDIV = 66; + parameter integer QPLL1_FBDIV_G3 = 80; + parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000; + parameter [7:0] QPLL1_INIT_CFG1 = 8'h00; + parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8; + parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8; + parameter [9:0] QPLL1_LPF = 10'b1111111111; + parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111; + parameter integer QPLL1_REFCLK_DIV = 2; + parameter [15:0] QPLL1_SDM_CFG0 = 16'h0040; + parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000; + parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000; + parameter [15:0] RSVD_ATTR0 = 16'h0000; + parameter [15:0] RSVD_ATTR1 = 16'h0000; + parameter [15:0] RSVD_ATTR2 = 16'h0000; + parameter [15:0] RSVD_ATTR3 = 16'h0000; + parameter [1:0] RXRECCLKOUT0_SEL = 2'b00; + parameter [1:0] RXRECCLKOUT1_SEL = 2'b00; + parameter [0:0] SARC_EN = 1'b1; + parameter [0:0] SARC_SEL = 1'b0; + parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000; + parameter [8:0] SDM0INITSEED0_1 = 9'b000000000; + parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000; + parameter [8:0] SDM1INITSEED0_1 = 9'b000000000; + parameter SIM_MODE = "FAST"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter integer SIM_VERSION = 2; + output [15:0] DRPDO; + output DRPRDY; + output [7:0] PMARSVDOUT0; + output [7:0] PMARSVDOUT1; + output QPLL0FBCLKLOST; + output QPLL0LOCK; + output QPLL0OUTCLK; + output QPLL0OUTREFCLK; + output QPLL0REFCLKLOST; + output QPLL1FBCLKLOST; + output QPLL1LOCK; + output QPLL1OUTCLK; + output QPLL1OUTREFCLK; + output QPLL1REFCLKLOST; + output [7:0] QPLLDMONITOR0; + output [7:0] QPLLDMONITOR1; + output REFCLKOUTMONITOR0; + output REFCLKOUTMONITOR1; + output [1:0] RXRECCLK0_SEL; + output [1:0] RXRECCLK1_SEL; + output [3:0] SDM0FINALOUT; + output [14:0] SDM0TESTDATA; + output [3:0] SDM1FINALOUT; + output [14:0] SDM1TESTDATA; + input BGBYPASSB; + input BGMONITORENB; + input BGPDB; + input [4:0] BGRCALOVRD; + input BGRCALOVRDENB; + input [9:0] DRPADDR; + input DRPCLK; + input [15:0] DRPDI; + input DRPEN; + input DRPWE; + input GTGREFCLK0; + input GTGREFCLK1; + input GTNORTHREFCLK00; + input GTNORTHREFCLK01; + input GTNORTHREFCLK10; + input GTNORTHREFCLK11; + input GTREFCLK00; + input GTREFCLK01; + input GTREFCLK10; + input GTREFCLK11; + input GTSOUTHREFCLK00; + input GTSOUTHREFCLK01; + input GTSOUTHREFCLK10; + input GTSOUTHREFCLK11; + input [7:0] PMARSVD0; + input [7:0] PMARSVD1; + input QPLL0CLKRSVD0; + input QPLL0LOCKDETCLK; + input QPLL0LOCKEN; + input QPLL0PD; + input [2:0] QPLL0REFCLKSEL; + input QPLL0RESET; + input QPLL1CLKRSVD0; + input QPLL1LOCKDETCLK; + input QPLL1LOCKEN; + input QPLL1PD; + input [2:0] QPLL1REFCLKSEL; + input QPLL1RESET; + input [7:0] QPLLRSVD1; + input [4:0] QPLLRSVD2; + input [4:0] QPLLRSVD3; + input [7:0] QPLLRSVD4; + input RCALENB; + input [24:0] SDM0DATA; + input SDM0RESET; + input [1:0] SDM0WIDTH; + input [24:0] SDM1DATA; + input SDM1RESET; + input [1:0] SDM1WIDTH; +endmodule + +module IBUFDS_GTE3 (...); + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; + parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00; + parameter [1:0] REFCLK_ICNTL_RX = 2'b00; + output O; + output ODIV2; + input CEB; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; +endmodule + +module OBUFDS_GTE3 (...); + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; + parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; + (* iopad_external_pin *) + output O; + (* iopad_external_pin *) + output OB; + input CEB; + input I; +endmodule + +module OBUFDS_GTE3_ADV (...); + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; + parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; + (* iopad_external_pin *) + output O; + (* iopad_external_pin *) + output OB; + input CEB; + input [3:0] I; + input [1:0] RXRECCLK_SEL; +endmodule + +module GTHE4_CHANNEL (...); + parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; + parameter [0:0] ACJTAG_MODE = 1'b0; + parameter [0:0] ACJTAG_RESET = 1'b0; + parameter [15:0] ADAPT_CFG0 = 16'h9200; + parameter [15:0] ADAPT_CFG1 = 16'h801C; + parameter [15:0] ADAPT_CFG2 = 16'h0000; + parameter ALIGN_COMMA_DOUBLE = "FALSE"; + parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; + parameter integer ALIGN_COMMA_WORD = 1; + parameter ALIGN_MCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; + parameter ALIGN_PCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; + parameter [0:0] A_RXOSCALRESET = 1'b0; + parameter [0:0] A_RXPROGDIVRESET = 1'b0; + parameter [0:0] A_RXTERMINATION = 1'b1; + parameter [4:0] A_TXDIFFCTRL = 5'b01100; + parameter [0:0] A_TXPROGDIVRESET = 1'b0; + parameter [0:0] CAPBYPASS_FORCE = 1'b0; + parameter CBCC_DATA_SOURCE_SEL = "DECODED"; + parameter [0:0] CDR_SWAP_MODE_EN = 1'b0; + parameter [0:0] CFOK_PWRSVE_EN = 1'b1; + parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; + parameter integer CHAN_BOND_MAX_SKEW = 7; + parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; + parameter CHAN_BOND_SEQ_2_USE = "FALSE"; + parameter integer CHAN_BOND_SEQ_LEN = 2; + parameter [15:0] CH_HSPMUX = 16'h2424; + parameter [15:0] CKCAL1_CFG_0 = 16'b0000000000000000; + parameter [15:0] CKCAL1_CFG_1 = 16'b0000000000000000; + parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000; + parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_0 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_1 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000; + parameter [15:0] CKCAL_RSVD0 = 16'h4000; + parameter [15:0] CKCAL_RSVD1 = 16'h0000; + parameter CLK_CORRECT_USE = "TRUE"; + parameter CLK_COR_KEEP_IDLE = "FALSE"; + parameter integer CLK_COR_MAX_LAT = 20; + parameter integer CLK_COR_MIN_LAT = 18; + parameter CLK_COR_PRECEDENCE = "TRUE"; + parameter integer CLK_COR_REPEAT_WAIT = 0; + parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; + parameter CLK_COR_SEQ_2_USE = "FALSE"; + parameter integer CLK_COR_SEQ_LEN = 2; + parameter [15:0] CPLL_CFG0 = 16'h01FA; + parameter [15:0] CPLL_CFG1 = 16'h24A9; + parameter [15:0] CPLL_CFG2 = 16'h6807; + parameter [15:0] CPLL_CFG3 = 16'h0000; + parameter integer CPLL_FBDIV = 4; + parameter integer CPLL_FBDIV_45 = 4; + parameter [15:0] CPLL_INIT_CFG0 = 16'h001E; + parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; + parameter integer CPLL_REFCLK_DIV = 1; + parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000; + parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0; + parameter [1:0] DDI_CTRL = 2'b00; + parameter integer DDI_REALIGN_WAIT = 15; + parameter DEC_MCOMMA_DETECT = "TRUE"; + parameter DEC_PCOMMA_DETECT = "TRUE"; + parameter DEC_VALID_COMMA_ONLY = "TRUE"; + parameter [0:0] DELAY_ELEC = 1'b0; + parameter [9:0] DMONITOR_CFG0 = 10'h000; + parameter [7:0] DMONITOR_CFG1 = 8'h00; + parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; + parameter [5:0] ES_CONTROL = 6'b000000; + parameter ES_ERRDET_EN = "FALSE"; + parameter ES_EYE_SCAN_EN = "FALSE"; + parameter [11:0] ES_HORZ_OFFSET = 12'h800; + parameter [4:0] ES_PRESCALE = 5'b00000; + parameter [15:0] ES_QUALIFIER0 = 16'h0000; + parameter [15:0] ES_QUALIFIER1 = 16'h0000; + parameter [15:0] ES_QUALIFIER2 = 16'h0000; + parameter [15:0] ES_QUALIFIER3 = 16'h0000; + parameter [15:0] ES_QUALIFIER4 = 16'h0000; + parameter [15:0] ES_QUALIFIER5 = 16'h0000; + parameter [15:0] ES_QUALIFIER6 = 16'h0000; + parameter [15:0] ES_QUALIFIER7 = 16'h0000; + parameter [15:0] ES_QUALIFIER8 = 16'h0000; + parameter [15:0] ES_QUALIFIER9 = 16'h0000; + parameter [15:0] ES_QUAL_MASK0 = 16'h0000; + parameter [15:0] ES_QUAL_MASK1 = 16'h0000; + parameter [15:0] ES_QUAL_MASK2 = 16'h0000; + parameter [15:0] ES_QUAL_MASK3 = 16'h0000; + parameter [15:0] ES_QUAL_MASK4 = 16'h0000; + parameter [15:0] ES_QUAL_MASK5 = 16'h0000; + parameter [15:0] ES_QUAL_MASK6 = 16'h0000; + parameter [15:0] ES_QUAL_MASK7 = 16'h0000; + parameter [15:0] ES_QUAL_MASK8 = 16'h0000; + parameter [15:0] ES_QUAL_MASK9 = 16'h0000; + parameter [15:0] ES_SDATA_MASK0 = 16'h0000; + parameter [15:0] ES_SDATA_MASK1 = 16'h0000; + parameter [15:0] ES_SDATA_MASK2 = 16'h0000; + parameter [15:0] ES_SDATA_MASK3 = 16'h0000; + parameter [15:0] ES_SDATA_MASK4 = 16'h0000; + parameter [15:0] ES_SDATA_MASK5 = 16'h0000; + parameter [15:0] ES_SDATA_MASK6 = 16'h0000; + parameter [15:0] ES_SDATA_MASK7 = 16'h0000; + parameter [15:0] ES_SDATA_MASK8 = 16'h0000; + parameter [15:0] ES_SDATA_MASK9 = 16'h0000; + parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0; + parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; + parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; + parameter FTS_LANE_DESKEW_EN = "FALSE"; + parameter [4:0] GEARBOX_MODE = 5'b00000; + parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0; + parameter [0:0] LOCAL_MASTER = 1'b0; + parameter [2:0] LPBK_BIAS_CTRL = 3'b000; + parameter [0:0] LPBK_EN_RCAL_B = 1'b0; + parameter [3:0] LPBK_EXT_RCAL = 4'b0000; + parameter [2:0] LPBK_IND_CTRL0 = 3'b000; + parameter [2:0] LPBK_IND_CTRL1 = 3'b000; + parameter [2:0] LPBK_IND_CTRL2 = 3'b000; + parameter [3:0] LPBK_RG_CTRL = 4'b0000; + parameter [1:0] OOBDIVCTL = 2'b00; + parameter [0:0] OOB_PWRUP = 1'b0; + parameter PCI3_AUTO_REALIGN = "FRST_SMPL"; + parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1; + parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00; + parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0; + parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000; + parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000; + parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000; + parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0; + parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0; + parameter [4:0] PCIE3_CLK_COR_EMPTY_THRSH = 5'b00000; + parameter [5:0] PCIE3_CLK_COR_FULL_THRSH = 6'b010000; + parameter [4:0] PCIE3_CLK_COR_MAX_LAT = 5'b01000; + parameter [4:0] PCIE3_CLK_COR_MIN_LAT = 5'b00100; + parameter [5:0] PCIE3_CLK_COR_THRSH_TIMER = 6'b001000; + parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000; + parameter [1:0] PCIE_PLL_SEL_MODE_GEN12 = 2'h0; + parameter [1:0] PCIE_PLL_SEL_MODE_GEN3 = 2'h0; + parameter [1:0] PCIE_PLL_SEL_MODE_GEN4 = 2'h0; + parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000; + parameter [15:0] PCIE_RXPMA_CFG = 16'h0000; + parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000; + parameter [15:0] PCIE_TXPMA_CFG = 16'h0000; + parameter PCS_PCIE_EN = "FALSE"; + parameter [15:0] PCS_RSVD0 = 16'b0000000000000000; + parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; + parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; + parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; + parameter integer PREIQ_FREQ_BST = 0; + parameter [2:0] PROCESS_PAR = 3'b010; + parameter [0:0] RATE_SW_USE_DRP = 1'b0; + parameter [0:0] RCLK_SIPO_DLY_ENB = 1'b0; + parameter [0:0] RCLK_SIPO_INV_EN = 1'b0; + parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0; + parameter [2:0] RTX_BUF_CML_CTRL = 3'b010; + parameter [1:0] RTX_BUF_TERM_CTRL = 2'b00; + parameter [4:0] RXBUFRESET_TIME = 5'b00001; + parameter RXBUF_ADDR_MODE = "FULL"; + parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; + parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; + parameter RXBUF_EN = "TRUE"; + parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; + parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; + parameter RXBUF_RESET_ON_EIDLE = "FALSE"; + parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; + parameter integer RXBUF_THRESH_OVFLW = 0; + parameter RXBUF_THRESH_OVRD = "FALSE"; + parameter integer RXBUF_THRESH_UNDFLW = 4; + parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; + parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; + parameter [15:0] RXCDR_CFG0 = 16'h0003; + parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0003; + parameter [15:0] RXCDR_CFG1 = 16'h0000; + parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000; + parameter [15:0] RXCDR_CFG2 = 16'h0164; + parameter [9:0] RXCDR_CFG2_GEN2 = 10'h164; + parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0034; + parameter [15:0] RXCDR_CFG2_GEN4 = 16'h0034; + parameter [15:0] RXCDR_CFG3 = 16'h0024; + parameter [5:0] RXCDR_CFG3_GEN2 = 6'h24; + parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0024; + parameter [15:0] RXCDR_CFG3_GEN4 = 16'h0024; + parameter [15:0] RXCDR_CFG4 = 16'h5CF6; + parameter [15:0] RXCDR_CFG4_GEN3 = 16'h5CF6; + parameter [15:0] RXCDR_CFG5 = 16'hB46B; + parameter [15:0] RXCDR_CFG5_GEN3 = 16'h146B; + parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; + parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; + parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0040; + parameter [15:0] RXCDR_LOCK_CFG1 = 16'h8000; + parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000; + parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000; + parameter [15:0] RXCDR_LOCK_CFG4 = 16'h0000; + parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; + parameter [15:0] RXCFOK_CFG0 = 16'h0000; + parameter [15:0] RXCFOK_CFG1 = 16'h0002; + parameter [15:0] RXCFOK_CFG2 = 16'h002D; + parameter [15:0] RXCKCAL1_IQ_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL1_I_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL1_Q_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL2_DX_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL2_D_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL2_S_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL2_X_LOOP_RST_CFG = 16'h0000; + parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; + parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000; + parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022; + parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100; + parameter [15:0] RXDFE_CFG0 = 16'h4000; + parameter [15:0] RXDFE_CFG1 = 16'h0000; + parameter [15:0] RXDFE_GC_CFG0 = 16'h0000; + parameter [15:0] RXDFE_GC_CFG1 = 16'h0000; + parameter [15:0] RXDFE_GC_CFG2 = 16'h0000; + parameter [15:0] RXDFE_H2_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H2_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H3_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H3_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H4_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H4_CFG1 = 16'h0003; + parameter [15:0] RXDFE_H5_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H5_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H6_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H6_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H7_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H7_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H8_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H8_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H9_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H9_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HA_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HA_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HB_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HB_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HC_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HC_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HD_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HD_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HE_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HE_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HF_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HF_CFG1 = 16'h0002; + parameter [15:0] RXDFE_KH_CFG0 = 16'h0000; + parameter [15:0] RXDFE_KH_CFG1 = 16'h0000; + parameter [15:0] RXDFE_KH_CFG2 = 16'h0000; + parameter [15:0] RXDFE_KH_CFG3 = 16'h0000; + parameter [15:0] RXDFE_OS_CFG0 = 16'h0000; + parameter [15:0] RXDFE_OS_CFG1 = 16'h0002; + parameter [0:0] RXDFE_PWR_SAVING = 1'b0; + parameter [15:0] RXDFE_UT_CFG0 = 16'h0000; + parameter [15:0] RXDFE_UT_CFG1 = 16'h0002; + parameter [15:0] RXDFE_UT_CFG2 = 16'h0000; + parameter [15:0] RXDFE_VP_CFG0 = 16'h0000; + parameter [15:0] RXDFE_VP_CFG1 = 16'h0022; + parameter [15:0] RXDLY_CFG = 16'h0010; + parameter [15:0] RXDLY_LCFG = 16'h0030; + parameter RXELECIDLE_CFG = "SIGCFG_4"; + parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4; + parameter RXGEARBOX_EN = "FALSE"; + parameter [4:0] RXISCANRESET_TIME = 5'b00001; + parameter [15:0] RXLPM_CFG = 16'h0000; + parameter [15:0] RXLPM_GC_CFG = 16'h1000; + parameter [15:0] RXLPM_KH_CFG0 = 16'h0000; + parameter [15:0] RXLPM_KH_CFG1 = 16'h0002; + parameter [15:0] RXLPM_OS_CFG0 = 16'h0000; + parameter [15:0] RXLPM_OS_CFG1 = 16'h0000; + parameter [8:0] RXOOB_CFG = 9'b000110000; + parameter RXOOB_CLK_CFG = "PMA"; + parameter [4:0] RXOSCALRESET_TIME = 5'b00011; + parameter integer RXOUT_DIV = 4; + parameter [4:0] RXPCSRESET_TIME = 5'b00001; + parameter [15:0] RXPHBEACON_CFG = 16'h0000; + parameter [15:0] RXPHDLY_CFG = 16'h2020; + parameter [15:0] RXPHSAMP_CFG = 16'h2100; + parameter [15:0] RXPHSLIP_CFG = 16'h9933; + parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; + parameter [0:0] RXPI_AUTO_BW_SEL_BYPASS = 1'b0; + parameter [15:0] RXPI_CFG0 = 16'h0002; + parameter [15:0] RXPI_CFG1 = 16'b0000000000000000; + parameter [0:0] RXPI_LPM = 1'b0; + parameter [1:0] RXPI_SEL_LC = 2'b00; + parameter [1:0] RXPI_STARTCODE = 2'b00; + parameter [0:0] RXPI_VREFSEL = 1'b0; + parameter RXPMACLK_SEL = "DATA"; + parameter [4:0] RXPMARESET_TIME = 5'b00001; + parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; + parameter integer RXPRBS_LINKACQ_CNT = 15; + parameter [0:0] RXREFCLKDIV2_SEL = 1'b0; + parameter integer RXSLIDE_AUTO_WAIT = 7; + parameter RXSLIDE_MODE = "OFF"; + parameter [0:0] RXSYNC_MULTILANE = 1'b0; + parameter [0:0] RXSYNC_OVRD = 1'b0; + parameter [0:0] RXSYNC_SKIP_DA = 1'b0; + parameter [0:0] RX_AFE_CM_EN = 1'b0; + parameter [15:0] RX_BIAS_CFG0 = 16'h12B0; + parameter [5:0] RX_BUFFER_CFG = 6'b000000; + parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0; + parameter integer RX_CLK25_DIV = 8; + parameter [0:0] RX_CLKMUX_EN = 1'b1; + parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000; + parameter [3:0] RX_CM_BUF_CFG = 4'b1010; + parameter [0:0] RX_CM_BUF_PD = 1'b0; + parameter integer RX_CM_SEL = 3; + parameter integer RX_CM_TRIM = 12; + parameter [7:0] RX_CTLE3_LPF = 8'b00000000; + parameter integer RX_DATA_WIDTH = 20; + parameter [5:0] RX_DDI_SEL = 6'b000000; + parameter RX_DEFER_RESET_BUF_EN = "TRUE"; + parameter [2:0] RX_DEGEN_CTRL = 3'b011; + parameter integer RX_DFELPM_CFG0 = 0; + parameter [0:0] RX_DFELPM_CFG1 = 1'b1; + parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1; + parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00; + parameter integer RX_DFE_AGC_CFG1 = 4; + parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1; + parameter integer RX_DFE_KL_LPM_KH_CFG1 = 4; + parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01; + parameter integer RX_DFE_KL_LPM_KL_CFG1 = 4; + parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; + parameter RX_DISPERR_SEQ_MATCH = "TRUE"; + parameter [0:0] RX_DIV2_MODE_B = 1'b0; + parameter [4:0] RX_DIVRESET_TIME = 5'b00001; + parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0; + parameter [0:0] RX_EN_HI_LR = 1'b1; + parameter [8:0] RX_EXT_RL_CTRL = 9'b000000000; + parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000; + parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0; + parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00; + parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0; + parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0; + parameter integer RX_INT_DATAWIDTH = 1; + parameter [0:0] RX_PMA_POWER_SAVE = 1'b0; + parameter [15:0] RX_PMA_RSV0 = 16'h0000; + parameter real RX_PROGDIV_CFG = 0.0; + parameter [15:0] RX_PROGDIV_RATE = 16'h0001; + parameter [3:0] RX_RESLOAD_CTRL = 4'b0000; + parameter [0:0] RX_RESLOAD_OVRD = 1'b0; + parameter [2:0] RX_SAMPLE_PERIOD = 3'b101; + parameter integer RX_SIG_VALID_DLY = 11; + parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0; + parameter [3:0] RX_SUM_IREF_TUNE = 4'b1001; + parameter [3:0] RX_SUM_RESLOAD_CTRL = 4'b0000; + parameter [3:0] RX_SUM_VCMTUNE = 4'b1010; + parameter [0:0] RX_SUM_VCM_OVWR = 1'b0; + parameter [2:0] RX_SUM_VREF_TUNE = 3'b100; + parameter [1:0] RX_TUNE_AFE_OS = 2'b00; + parameter [2:0] RX_VREG_CTRL = 3'b101; + parameter [0:0] RX_VREG_PDB = 1'b1; + parameter [1:0] RX_WIDEMODE_CDR = 2'b01; + parameter [1:0] RX_WIDEMODE_CDR_GEN3 = 2'b01; + parameter [1:0] RX_WIDEMODE_CDR_GEN4 = 2'b01; + parameter RX_XCLK_SEL = "RXDES"; + parameter [0:0] RX_XMODE_SEL = 1'b0; + parameter [0:0] SAMPLE_CLK_PHASE = 1'b0; + parameter [0:0] SAS_12G_MODE = 1'b0; + parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; + parameter [2:0] SATA_BURST_VAL = 3'b100; + parameter SATA_CPLL_CFG = "VCO_3000MHZ"; + parameter [2:0] SATA_EIDLE_VAL = 3'b100; + parameter SHOW_REALIGN_COMMA = "TRUE"; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter SIM_MODE = "FAST"; + parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter SIM_TX_EIDLE_DRIVE_LEVEL = "Z"; + parameter [0:0] SRSTMODE = 1'b0; + parameter [1:0] TAPDLY_SET_TX = 2'h0; + parameter [3:0] TEMPERATURE_PAR = 4'b0010; + parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; + parameter [2:0] TERM_RCAL_OVRD = 3'b000; + parameter [7:0] TRANS_TIME_RATE = 8'h0E; + parameter [7:0] TST_RSV0 = 8'h00; + parameter [7:0] TST_RSV1 = 8'h00; + parameter TXBUF_EN = "TRUE"; + parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; + parameter [15:0] TXDLY_CFG = 16'h0010; + parameter [15:0] TXDLY_LCFG = 16'h0030; + parameter [3:0] TXDRVBIAS_N = 4'b1010; + parameter TXFIFO_ADDR_CFG = "LOW"; + parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4; + parameter TXGEARBOX_EN = "FALSE"; + parameter integer TXOUT_DIV = 4; + parameter [4:0] TXPCSRESET_TIME = 5'b00001; + parameter [15:0] TXPHDLY_CFG0 = 16'h6020; + parameter [15:0] TXPHDLY_CFG1 = 16'h0002; + parameter [15:0] TXPH_CFG = 16'h0123; + parameter [15:0] TXPH_CFG2 = 16'h0000; + parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; + parameter [15:0] TXPI_CFG = 16'h0000; + parameter [1:0] TXPI_CFG0 = 2'b00; + parameter [1:0] TXPI_CFG1 = 2'b00; + parameter [1:0] TXPI_CFG2 = 2'b00; + parameter [0:0] TXPI_CFG3 = 1'b0; + parameter [0:0] TXPI_CFG4 = 1'b1; + parameter [2:0] TXPI_CFG5 = 3'b000; + parameter [0:0] TXPI_GRAY_SEL = 1'b0; + parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; + parameter [0:0] TXPI_LPM = 1'b0; + parameter [0:0] TXPI_PPM = 1'b0; + parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; + parameter [7:0] TXPI_PPM_CFG = 8'b00000000; + parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; + parameter [0:0] TXPI_VREFSEL = 1'b0; + parameter [4:0] TXPMARESET_TIME = 5'b00001; + parameter [0:0] TXREFCLKDIV2_SEL = 1'b0; + parameter [0:0] TXSYNC_MULTILANE = 1'b0; + parameter [0:0] TXSYNC_OVRD = 1'b0; + parameter [0:0] TXSYNC_SKIP_DA = 1'b0; + parameter integer TX_CLK25_DIV = 8; + parameter [0:0] TX_CLKMUX_EN = 1'b1; + parameter integer TX_DATA_WIDTH = 20; + parameter [15:0] TX_DCC_LOOP_RST_CFG = 16'h0000; + parameter [5:0] TX_DEEMPH0 = 6'b000000; + parameter [5:0] TX_DEEMPH1 = 6'b000000; + parameter [5:0] TX_DEEMPH2 = 6'b000000; + parameter [5:0] TX_DEEMPH3 = 6'b000000; + parameter [4:0] TX_DIVRESET_TIME = 5'b00001; + parameter TX_DRIVE_MODE = "DIRECT"; + parameter integer TX_DRVMUX_CTRL = 2; + parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; + parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; + parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0; + parameter [0:0] TX_FIFO_BYP_EN = 1'b0; + parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0; + parameter integer TX_INT_DATAWIDTH = 1; + parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; + parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; + parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; + parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; + parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; + parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; + parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; + parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; + parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; + parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; + parameter [15:0] TX_PHICAL_CFG0 = 16'h0000; + parameter [15:0] TX_PHICAL_CFG1 = 16'h003F; + parameter [15:0] TX_PHICAL_CFG2 = 16'h0000; + parameter integer TX_PI_BIASSET = 0; + parameter [1:0] TX_PI_IBIAS_MID = 2'b00; + parameter [0:0] TX_PMADATA_OPT = 1'b0; + parameter [0:0] TX_PMA_POWER_SAVE = 1'b0; + parameter [15:0] TX_PMA_RSV0 = 16'h0008; + parameter integer TX_PREDRV_CTRL = 2; + parameter TX_PROGCLK_SEL = "POSTPI"; + parameter real TX_PROGDIV_CFG = 0.0; + parameter [15:0] TX_PROGDIV_RATE = 16'h0001; + parameter [0:0] TX_QPI_STATUS_EN = 1'b0; + parameter [13:0] TX_RXDETECT_CFG = 14'h0032; + parameter integer TX_RXDETECT_REF = 3; + parameter [2:0] TX_SAMPLE_PERIOD = 3'b101; + parameter [0:0] TX_SARC_LPBK_ENB = 1'b0; + parameter [1:0] TX_SW_MEAS = 2'b00; + parameter [2:0] TX_VREG_CTRL = 3'b000; + parameter [0:0] TX_VREG_PDB = 1'b0; + parameter [1:0] TX_VREG_VREFSEL = 2'b00; + parameter TX_XCLK_SEL = "TXOUT"; + parameter [0:0] USB_BOTH_BURST_IDLE = 1'b0; + parameter [6:0] USB_BURSTMAX_U3WAKE = 7'b1111111; + parameter [6:0] USB_BURSTMIN_U3WAKE = 7'b1100011; + parameter [0:0] USB_CLK_COR_EQ_EN = 1'b0; + parameter [0:0] USB_EXT_CNTL = 1'b1; + parameter [9:0] USB_IDLEMAX_POLLING = 10'b1010111011; + parameter [9:0] USB_IDLEMIN_POLLING = 10'b0100101011; + parameter [8:0] USB_LFPSPING_BURST = 9'b000000101; + parameter [8:0] USB_LFPSPOLLING_BURST = 9'b000110001; + parameter [8:0] USB_LFPSPOLLING_IDLE_MS = 9'b000000100; + parameter [8:0] USB_LFPSU1EXIT_BURST = 9'b000011101; + parameter [8:0] USB_LFPSU2LPEXIT_BURST_MS = 9'b001100011; + parameter [8:0] USB_LFPSU3WAKE_BURST_MS = 9'b111110011; + parameter [3:0] USB_LFPS_TPERIOD = 4'b0011; + parameter [0:0] USB_LFPS_TPERIOD_ACCURATE = 1'b1; + parameter [0:0] USB_MODE = 1'b0; + parameter [0:0] USB_PCIE_ERR_REP_DIS = 1'b0; + parameter integer USB_PING_SATA_MAX_INIT = 21; + parameter integer USB_PING_SATA_MIN_INIT = 12; + parameter integer USB_POLL_SATA_MAX_BURST = 8; + parameter integer USB_POLL_SATA_MIN_BURST = 4; + parameter [0:0] USB_RAW_ELEC = 1'b0; + parameter [0:0] USB_RXIDLE_P0_CTRL = 1'b1; + parameter [0:0] USB_TXIDLE_TUNE_ENABLE = 1'b1; + parameter integer USB_U1_SATA_MAX_WAKE = 7; + parameter integer USB_U1_SATA_MIN_WAKE = 4; + parameter integer USB_U2_SAS_MAX_COM = 64; + parameter integer USB_U2_SAS_MIN_COM = 36; + parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; + parameter [0:0] Y_ALL_MODE = 1'b0; + output BUFGTCE; + output [2:0] BUFGTCEMASK; + output [8:0] BUFGTDIV; + output BUFGTRESET; + output [2:0] BUFGTRSTMASK; + output CPLLFBCLKLOST; + output CPLLLOCK; + output CPLLREFCLKLOST; + output [15:0] DMONITOROUT; + output DMONITOROUTCLK; + output [15:0] DRPDO; + output DRPRDY; + output EYESCANDATAERROR; + output GTHTXN; + output GTHTXP; + output GTPOWERGOOD; + output GTREFCLKMONITOR; + output PCIERATEGEN3; + output PCIERATEIDLE; + output [1:0] PCIERATEQPLLPD; + output [1:0] PCIERATEQPLLRESET; + output PCIESYNCTXSYNCDONE; + output PCIEUSERGEN3RDY; + output PCIEUSERPHYSTATUSRST; + output PCIEUSERRATESTART; + output [15:0] PCSRSVDOUT; + output PHYSTATUS; + output [15:0] PINRSRVDAS; + output POWERPRESENT; + output RESETEXCEPTION; + output [2:0] RXBUFSTATUS; + output RXBYTEISALIGNED; + output RXBYTEREALIGN; + output RXCDRLOCK; + output RXCDRPHDONE; + output RXCHANBONDSEQ; + output RXCHANISALIGNED; + output RXCHANREALIGN; + output [4:0] RXCHBONDO; + output RXCKCALDONE; + output [1:0] RXCLKCORCNT; + output RXCOMINITDET; + output RXCOMMADET; + output RXCOMSASDET; + output RXCOMWAKEDET; + output [15:0] RXCTRL0; + output [15:0] RXCTRL1; + output [7:0] RXCTRL2; + output [7:0] RXCTRL3; + output [127:0] RXDATA; + output [7:0] RXDATAEXTENDRSVD; + output [1:0] RXDATAVALID; + output RXDLYSRESETDONE; + output RXELECIDLE; + output [5:0] RXHEADER; + output [1:0] RXHEADERVALID; + output RXLFPSTRESETDET; + output RXLFPSU2LPEXITDET; + output RXLFPSU3WAKEDET; + output [7:0] RXMONITOROUT; + output RXOSINTDONE; + output RXOSINTSTARTED; + output RXOSINTSTROBEDONE; + output RXOSINTSTROBESTARTED; + output RXOUTCLK; + output RXOUTCLKFABRIC; + output RXOUTCLKPCS; + output RXPHALIGNDONE; + output RXPHALIGNERR; + output RXPMARESETDONE; + output RXPRBSERR; + output RXPRBSLOCKED; + output RXPRGDIVRESETDONE; + output RXQPISENN; + output RXQPISENP; + output RXRATEDONE; + output RXRECCLKOUT; + output RXRESETDONE; + output RXSLIDERDY; + output RXSLIPDONE; + output RXSLIPOUTCLKRDY; + output RXSLIPPMARDY; + output [1:0] RXSTARTOFSEQ; + output [2:0] RXSTATUS; + output RXSYNCDONE; + output RXSYNCOUT; + output RXVALID; + output [1:0] TXBUFSTATUS; + output TXCOMFINISH; + output TXDCCDONE; + output TXDLYSRESETDONE; + output TXOUTCLK; + output TXOUTCLKFABRIC; + output TXOUTCLKPCS; + output TXPHALIGNDONE; + output TXPHINITDONE; + output TXPMARESETDONE; + output TXPRGDIVRESETDONE; + output TXQPISENN; + output TXQPISENP; + output TXRATEDONE; + output TXRESETDONE; + output TXSYNCDONE; + output TXSYNCOUT; + input CDRSTEPDIR; + input CDRSTEPSQ; + input CDRSTEPSX; + input CFGRESET; + input CLKRSVD0; + input CLKRSVD1; + input CPLLFREQLOCK; + input CPLLLOCKDETCLK; + input CPLLLOCKEN; + input CPLLPD; + input [2:0] CPLLREFCLKSEL; + input CPLLRESET; + input DMONFIFORESET; + input DMONITORCLK; + input [9:0] DRPADDR; + input DRPCLK; + input [15:0] DRPDI; + input DRPEN; + input DRPRST; + input DRPWE; + input EYESCANRESET; + input EYESCANTRIGGER; + input FREQOS; + input GTGREFCLK; + input GTHRXN; + input GTHRXP; + input GTNORTHREFCLK0; + input GTNORTHREFCLK1; + input GTREFCLK0; + input GTREFCLK1; + input [15:0] GTRSVD; + input GTRXRESET; + input GTRXRESETSEL; + input GTSOUTHREFCLK0; + input GTSOUTHREFCLK1; + input GTTXRESET; + input GTTXRESETSEL; + input INCPCTRL; + input [2:0] LOOPBACK; + input PCIEEQRXEQADAPTDONE; + input PCIERSTIDLE; + input PCIERSTTXSYNCSTART; + input PCIEUSERRATEDONE; + input [15:0] PCSRSVDIN; + input QPLL0CLK; + input QPLL0FREQLOCK; + input QPLL0REFCLK; + input QPLL1CLK; + input QPLL1FREQLOCK; + input QPLL1REFCLK; + input RESETOVRD; + input RX8B10BEN; + input RXAFECFOKEN; + input RXBUFRESET; + input RXCDRFREQRESET; + input RXCDRHOLD; + input RXCDROVRDEN; + input RXCDRRESET; + input RXCHBONDEN; + input [4:0] RXCHBONDI; + input [2:0] RXCHBONDLEVEL; + input RXCHBONDMASTER; + input RXCHBONDSLAVE; + input RXCKCALRESET; + input [6:0] RXCKCALSTART; + input RXCOMMADETEN; + input [1:0] RXDFEAGCCTRL; + input RXDFEAGCHOLD; + input RXDFEAGCOVRDEN; + input [3:0] RXDFECFOKFCNUM; + input RXDFECFOKFEN; + input RXDFECFOKFPULSE; + input RXDFECFOKHOLD; + input RXDFECFOKOVREN; + input RXDFEKHHOLD; + input RXDFEKHOVRDEN; + input RXDFELFHOLD; + input RXDFELFOVRDEN; + input RXDFELPMRESET; + input RXDFETAP10HOLD; + input RXDFETAP10OVRDEN; + input RXDFETAP11HOLD; + input RXDFETAP11OVRDEN; + input RXDFETAP12HOLD; + input RXDFETAP12OVRDEN; + input RXDFETAP13HOLD; + input RXDFETAP13OVRDEN; + input RXDFETAP14HOLD; + input RXDFETAP14OVRDEN; + input RXDFETAP15HOLD; + input RXDFETAP15OVRDEN; + input RXDFETAP2HOLD; + input RXDFETAP2OVRDEN; + input RXDFETAP3HOLD; + input RXDFETAP3OVRDEN; + input RXDFETAP4HOLD; + input RXDFETAP4OVRDEN; + input RXDFETAP5HOLD; + input RXDFETAP5OVRDEN; + input RXDFETAP6HOLD; + input RXDFETAP6OVRDEN; + input RXDFETAP7HOLD; + input RXDFETAP7OVRDEN; + input RXDFETAP8HOLD; + input RXDFETAP8OVRDEN; + input RXDFETAP9HOLD; + input RXDFETAP9OVRDEN; + input RXDFEUTHOLD; + input RXDFEUTOVRDEN; + input RXDFEVPHOLD; + input RXDFEVPOVRDEN; + input RXDFEXYDEN; + input RXDLYBYPASS; + input RXDLYEN; + input RXDLYOVRDEN; + input RXDLYSRESET; + input [1:0] RXELECIDLEMODE; + input RXEQTRAINING; + input RXGEARBOXSLIP; + input RXLATCLK; + input RXLPMEN; + input RXLPMGCHOLD; + input RXLPMGCOVRDEN; + input RXLPMHFHOLD; + input RXLPMHFOVRDEN; + input RXLPMLFHOLD; + input RXLPMLFKLOVRDEN; + input RXLPMOSHOLD; + input RXLPMOSOVRDEN; + input RXMCOMMAALIGNEN; + input [1:0] RXMONITORSEL; + input RXOOBRESET; + input RXOSCALRESET; + input RXOSHOLD; + input RXOSOVRDEN; + input [2:0] RXOUTCLKSEL; + input RXPCOMMAALIGNEN; + input RXPCSRESET; + input [1:0] RXPD; + input RXPHALIGN; + input RXPHALIGNEN; + input RXPHDLYPD; + input RXPHDLYRESET; + input RXPHOVRDEN; + input [1:0] RXPLLCLKSEL; + input RXPMARESET; + input RXPOLARITY; + input RXPRBSCNTRESET; + input [3:0] RXPRBSSEL; + input RXPROGDIVRESET; + input RXQPIEN; + input [2:0] RXRATE; + input RXRATEMODE; + input RXSLIDE; + input RXSLIPOUTCLK; + input RXSLIPPMA; + input RXSYNCALLIN; + input RXSYNCIN; + input RXSYNCMODE; + input [1:0] RXSYSCLKSEL; + input RXTERMINATION; + input RXUSERRDY; + input RXUSRCLK; + input RXUSRCLK2; + input SIGVALIDCLK; + input [19:0] TSTIN; + input [7:0] TX8B10BBYPASS; + input TX8B10BEN; + input TXCOMINIT; + input TXCOMSAS; + input TXCOMWAKE; + input [15:0] TXCTRL0; + input [15:0] TXCTRL1; + input [7:0] TXCTRL2; + input [127:0] TXDATA; + input [7:0] TXDATAEXTENDRSVD; + input TXDCCFORCESTART; + input TXDCCRESET; + input [1:0] TXDEEMPH; + input TXDETECTRX; + input [4:0] TXDIFFCTRL; + input TXDLYBYPASS; + input TXDLYEN; + input TXDLYHOLD; + input TXDLYOVRDEN; + input TXDLYSRESET; + input TXDLYUPDOWN; + input TXELECIDLE; + input [5:0] TXHEADER; + input TXINHIBIT; + input TXLATCLK; + input TXLFPSTRESET; + input TXLFPSU2LPEXIT; + input TXLFPSU3WAKE; + input [6:0] TXMAINCURSOR; + input [2:0] TXMARGIN; + input TXMUXDCDEXHOLD; + input TXMUXDCDORWREN; + input TXONESZEROS; + input [2:0] TXOUTCLKSEL; + input TXPCSRESET; + input [1:0] TXPD; + input TXPDELECIDLEMODE; + input TXPHALIGN; + input TXPHALIGNEN; + input TXPHDLYPD; + input TXPHDLYRESET; + input TXPHDLYTSTCLK; + input TXPHINIT; + input TXPHOVRDEN; + input TXPIPPMEN; + input TXPIPPMOVRDEN; + input TXPIPPMPD; + input TXPIPPMSEL; + input [4:0] TXPIPPMSTEPSIZE; + input TXPISOPD; + input [1:0] TXPLLCLKSEL; + input TXPMARESET; + input TXPOLARITY; + input [4:0] TXPOSTCURSOR; + input TXPRBSFORCEERR; + input [3:0] TXPRBSSEL; + input [4:0] TXPRECURSOR; + input TXPROGDIVRESET; + input TXQPIBIASEN; + input TXQPIWEAKPUP; + input [2:0] TXRATE; + input TXRATEMODE; + input [6:0] TXSEQUENCE; + input TXSWING; + input TXSYNCALLIN; + input TXSYNCIN; + input TXSYNCMODE; + input [1:0] TXSYSCLKSEL; + input TXUSERRDY; + input TXUSRCLK; + input TXUSRCLK2; +endmodule + +module GTHE4_COMMON (...); + parameter [0:0] AEN_QPLL0_FBDIV = 1'b1; + parameter [0:0] AEN_QPLL1_FBDIV = 1'b1; + parameter [0:0] AEN_SDM0TOGGLE = 1'b0; + parameter [0:0] AEN_SDM1TOGGLE = 1'b0; + parameter [0:0] A_SDM0TOGGLE = 1'b0; + parameter [8:0] A_SDM1DATA_HIGH = 9'b000000000; + parameter [15:0] A_SDM1DATA_LOW = 16'b0000000000000000; + parameter [0:0] A_SDM1TOGGLE = 1'b0; + parameter [15:0] BIAS_CFG0 = 16'h0000; + parameter [15:0] BIAS_CFG1 = 16'h0000; + parameter [15:0] BIAS_CFG2 = 16'h0000; + parameter [15:0] BIAS_CFG3 = 16'h0000; + parameter [15:0] BIAS_CFG4 = 16'h0000; + parameter [15:0] BIAS_CFG_RSVD = 16'h0000; + parameter [15:0] COMMON_CFG0 = 16'h0000; + parameter [15:0] COMMON_CFG1 = 16'h0000; + parameter [15:0] POR_CFG = 16'h0000; + parameter [15:0] PPF0_CFG = 16'h0F00; + parameter [15:0] PPF1_CFG = 16'h0F00; + parameter QPLL0CLKOUT_RATE = "FULL"; + parameter [15:0] QPLL0_CFG0 = 16'h391C; + parameter [15:0] QPLL0_CFG1 = 16'h0000; + parameter [15:0] QPLL0_CFG1_G3 = 16'h0020; + parameter [15:0] QPLL0_CFG2 = 16'h0F80; + parameter [15:0] QPLL0_CFG2_G3 = 16'h0F80; + parameter [15:0] QPLL0_CFG3 = 16'h0120; + parameter [15:0] QPLL0_CFG4 = 16'h0002; + parameter [9:0] QPLL0_CP = 10'b0000011111; + parameter [9:0] QPLL0_CP_G3 = 10'b0000011111; + parameter integer QPLL0_FBDIV = 66; + parameter integer QPLL0_FBDIV_G3 = 80; + parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000; + parameter [7:0] QPLL0_INIT_CFG1 = 8'h00; + parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8; + parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8; + parameter [9:0] QPLL0_LPF = 10'b1011111111; + parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111; + parameter [0:0] QPLL0_PCI_EN = 1'b0; + parameter [0:0] QPLL0_RATE_SW_USE_DRP = 1'b0; + parameter integer QPLL0_REFCLK_DIV = 1; + parameter [15:0] QPLL0_SDM_CFG0 = 16'h0040; + parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000; + parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000; + parameter QPLL1CLKOUT_RATE = "FULL"; + parameter [15:0] QPLL1_CFG0 = 16'h691C; + parameter [15:0] QPLL1_CFG1 = 16'h0020; + parameter [15:0] QPLL1_CFG1_G3 = 16'h0020; + parameter [15:0] QPLL1_CFG2 = 16'h0F80; + parameter [15:0] QPLL1_CFG2_G3 = 16'h0F80; + parameter [15:0] QPLL1_CFG3 = 16'h0120; + parameter [15:0] QPLL1_CFG4 = 16'h0002; + parameter [9:0] QPLL1_CP = 10'b0000011111; + parameter [9:0] QPLL1_CP_G3 = 10'b0000011111; + parameter integer QPLL1_FBDIV = 66; + parameter integer QPLL1_FBDIV_G3 = 80; + parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000; + parameter [7:0] QPLL1_INIT_CFG1 = 8'h00; + parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8; + parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8; + parameter [9:0] QPLL1_LPF = 10'b1011111111; + parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111; + parameter [0:0] QPLL1_PCI_EN = 1'b0; + parameter [0:0] QPLL1_RATE_SW_USE_DRP = 1'b0; + parameter integer QPLL1_REFCLK_DIV = 1; + parameter [15:0] QPLL1_SDM_CFG0 = 16'h0000; + parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000; + parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000; + parameter [15:0] RSVD_ATTR0 = 16'h0000; + parameter [15:0] RSVD_ATTR1 = 16'h0000; + parameter [15:0] RSVD_ATTR2 = 16'h0000; + parameter [15:0] RSVD_ATTR3 = 16'h0000; + parameter [1:0] RXRECCLKOUT0_SEL = 2'b00; + parameter [1:0] RXRECCLKOUT1_SEL = 2'b00; + parameter [0:0] SARC_ENB = 1'b0; + parameter [0:0] SARC_SEL = 1'b0; + parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000; + parameter [8:0] SDM0INITSEED0_1 = 9'b000000000; + parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000; + parameter [8:0] SDM1INITSEED0_1 = 9'b000000000; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter SIM_MODE = "FAST"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + output [15:0] DRPDO; + output DRPRDY; + output [7:0] PMARSVDOUT0; + output [7:0] PMARSVDOUT1; + output QPLL0FBCLKLOST; + output QPLL0LOCK; + output QPLL0OUTCLK; + output QPLL0OUTREFCLK; + output QPLL0REFCLKLOST; + output QPLL1FBCLKLOST; + output QPLL1LOCK; + output QPLL1OUTCLK; + output QPLL1OUTREFCLK; + output QPLL1REFCLKLOST; + output [7:0] QPLLDMONITOR0; + output [7:0] QPLLDMONITOR1; + output REFCLKOUTMONITOR0; + output REFCLKOUTMONITOR1; + output [1:0] RXRECCLK0SEL; + output [1:0] RXRECCLK1SEL; + output [3:0] SDM0FINALOUT; + output [14:0] SDM0TESTDATA; + output [3:0] SDM1FINALOUT; + output [14:0] SDM1TESTDATA; + output [9:0] TCONGPO; + output TCONRSVDOUT0; + input BGBYPASSB; + input BGMONITORENB; + input BGPDB; + input [4:0] BGRCALOVRD; + input BGRCALOVRDENB; + input [15:0] DRPADDR; + input DRPCLK; + input [15:0] DRPDI; + input DRPEN; + input DRPWE; + input GTGREFCLK0; + input GTGREFCLK1; + input GTNORTHREFCLK00; + input GTNORTHREFCLK01; + input GTNORTHREFCLK10; + input GTNORTHREFCLK11; + input GTREFCLK00; + input GTREFCLK01; + input GTREFCLK10; + input GTREFCLK11; + input GTSOUTHREFCLK00; + input GTSOUTHREFCLK01; + input GTSOUTHREFCLK10; + input GTSOUTHREFCLK11; + input [2:0] PCIERATEQPLL0; + input [2:0] PCIERATEQPLL1; + input [7:0] PMARSVD0; + input [7:0] PMARSVD1; + input QPLL0CLKRSVD0; + input QPLL0CLKRSVD1; + input [7:0] QPLL0FBDIV; + input QPLL0LOCKDETCLK; + input QPLL0LOCKEN; + input QPLL0PD; + input [2:0] QPLL0REFCLKSEL; + input QPLL0RESET; + input QPLL1CLKRSVD0; + input QPLL1CLKRSVD1; + input [7:0] QPLL1FBDIV; + input QPLL1LOCKDETCLK; + input QPLL1LOCKEN; + input QPLL1PD; + input [2:0] QPLL1REFCLKSEL; + input QPLL1RESET; + input [7:0] QPLLRSVD1; + input [4:0] QPLLRSVD2; + input [4:0] QPLLRSVD3; + input [7:0] QPLLRSVD4; + input RCALENB; + input [24:0] SDM0DATA; + input SDM0RESET; + input SDM0TOGGLE; + input [1:0] SDM0WIDTH; + input [24:0] SDM1DATA; + input SDM1RESET; + input SDM1TOGGLE; + input [1:0] SDM1WIDTH; + input [9:0] TCONGPI; + input TCONPOWERUP; + input [1:0] TCONRESET; + input [1:0] TCONRSVDIN1; +endmodule + +module GTYE4_CHANNEL (...); + parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; + parameter [0:0] ACJTAG_MODE = 1'b0; + parameter [0:0] ACJTAG_RESET = 1'b0; + parameter [15:0] ADAPT_CFG0 = 16'h9200; + parameter [15:0] ADAPT_CFG1 = 16'h801C; + parameter [15:0] ADAPT_CFG2 = 16'h0000; + parameter ALIGN_COMMA_DOUBLE = "FALSE"; + parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; + parameter integer ALIGN_COMMA_WORD = 1; + parameter ALIGN_MCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; + parameter ALIGN_PCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; + parameter [0:0] A_RXOSCALRESET = 1'b0; + parameter [0:0] A_RXPROGDIVRESET = 1'b0; + parameter [0:0] A_RXTERMINATION = 1'b1; + parameter [4:0] A_TXDIFFCTRL = 5'b01100; + parameter [0:0] A_TXPROGDIVRESET = 1'b0; + parameter CBCC_DATA_SOURCE_SEL = "DECODED"; + parameter [0:0] CDR_SWAP_MODE_EN = 1'b0; + parameter [0:0] CFOK_PWRSVE_EN = 1'b1; + parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; + parameter integer CHAN_BOND_MAX_SKEW = 7; + parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; + parameter CHAN_BOND_SEQ_2_USE = "FALSE"; + parameter integer CHAN_BOND_SEQ_LEN = 2; + parameter [15:0] CH_HSPMUX = 16'h2424; + parameter [15:0] CKCAL1_CFG_0 = 16'b1100000011000000; + parameter [15:0] CKCAL1_CFG_1 = 16'b0101000011000000; + parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000; + parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_0 = 16'b1100000011000000; + parameter [15:0] CKCAL2_CFG_1 = 16'b1000000011000000; + parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000; + parameter CLK_CORRECT_USE = "TRUE"; + parameter CLK_COR_KEEP_IDLE = "FALSE"; + parameter integer CLK_COR_MAX_LAT = 20; + parameter integer CLK_COR_MIN_LAT = 18; + parameter CLK_COR_PRECEDENCE = "TRUE"; + parameter integer CLK_COR_REPEAT_WAIT = 0; + parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; + parameter CLK_COR_SEQ_2_USE = "FALSE"; + parameter integer CLK_COR_SEQ_LEN = 2; + parameter [15:0] CPLL_CFG0 = 16'h01FA; + parameter [15:0] CPLL_CFG1 = 16'h24A9; + parameter [15:0] CPLL_CFG2 = 16'h6807; + parameter [15:0] CPLL_CFG3 = 16'h0000; + parameter integer CPLL_FBDIV = 4; + parameter integer CPLL_FBDIV_45 = 4; + parameter [15:0] CPLL_INIT_CFG0 = 16'h001E; + parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; + parameter integer CPLL_REFCLK_DIV = 1; + parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000; + parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0; + parameter [1:0] DDI_CTRL = 2'b00; + parameter integer DDI_REALIGN_WAIT = 15; + parameter DEC_MCOMMA_DETECT = "TRUE"; + parameter DEC_PCOMMA_DETECT = "TRUE"; + parameter DEC_VALID_COMMA_ONLY = "TRUE"; + parameter [0:0] DELAY_ELEC = 1'b0; + parameter [9:0] DMONITOR_CFG0 = 10'h000; + parameter [7:0] DMONITOR_CFG1 = 8'h00; + parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; + parameter [5:0] ES_CONTROL = 6'b000000; + parameter ES_ERRDET_EN = "FALSE"; + parameter ES_EYE_SCAN_EN = "FALSE"; + parameter [11:0] ES_HORZ_OFFSET = 12'h800; + parameter [4:0] ES_PRESCALE = 5'b00000; + parameter [15:0] ES_QUALIFIER0 = 16'h0000; + parameter [15:0] ES_QUALIFIER1 = 16'h0000; + parameter [15:0] ES_QUALIFIER2 = 16'h0000; + parameter [15:0] ES_QUALIFIER3 = 16'h0000; + parameter [15:0] ES_QUALIFIER4 = 16'h0000; + parameter [15:0] ES_QUALIFIER5 = 16'h0000; + parameter [15:0] ES_QUALIFIER6 = 16'h0000; + parameter [15:0] ES_QUALIFIER7 = 16'h0000; + parameter [15:0] ES_QUALIFIER8 = 16'h0000; + parameter [15:0] ES_QUALIFIER9 = 16'h0000; + parameter [15:0] ES_QUAL_MASK0 = 16'h0000; + parameter [15:0] ES_QUAL_MASK1 = 16'h0000; + parameter [15:0] ES_QUAL_MASK2 = 16'h0000; + parameter [15:0] ES_QUAL_MASK3 = 16'h0000; + parameter [15:0] ES_QUAL_MASK4 = 16'h0000; + parameter [15:0] ES_QUAL_MASK5 = 16'h0000; + parameter [15:0] ES_QUAL_MASK6 = 16'h0000; + parameter [15:0] ES_QUAL_MASK7 = 16'h0000; + parameter [15:0] ES_QUAL_MASK8 = 16'h0000; + parameter [15:0] ES_QUAL_MASK9 = 16'h0000; + parameter [15:0] ES_SDATA_MASK0 = 16'h0000; + parameter [15:0] ES_SDATA_MASK1 = 16'h0000; + parameter [15:0] ES_SDATA_MASK2 = 16'h0000; + parameter [15:0] ES_SDATA_MASK3 = 16'h0000; + parameter [15:0] ES_SDATA_MASK4 = 16'h0000; + parameter [15:0] ES_SDATA_MASK5 = 16'h0000; + parameter [15:0] ES_SDATA_MASK6 = 16'h0000; + parameter [15:0] ES_SDATA_MASK7 = 16'h0000; + parameter [15:0] ES_SDATA_MASK8 = 16'h0000; + parameter [15:0] ES_SDATA_MASK9 = 16'h0000; + parameter integer EYESCAN_VP_RANGE = 0; + parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0; + parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; + parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; + parameter FTS_LANE_DESKEW_EN = "FALSE"; + parameter [4:0] GEARBOX_MODE = 5'b00000; + parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0; + parameter [0:0] LOCAL_MASTER = 1'b0; + parameter integer LPBK_BIAS_CTRL = 4; + parameter [0:0] LPBK_EN_RCAL_B = 1'b0; + parameter [3:0] LPBK_EXT_RCAL = 4'b0000; + parameter integer LPBK_IND_CTRL0 = 5; + parameter integer LPBK_IND_CTRL1 = 5; + parameter integer LPBK_IND_CTRL2 = 5; + parameter integer LPBK_RG_CTRL = 2; + parameter [1:0] OOBDIVCTL = 2'b00; + parameter [0:0] OOB_PWRUP = 1'b0; + parameter PCI3_AUTO_REALIGN = "FRST_SMPL"; + parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1; + parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00; + parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0; + parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000; + parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000; + parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000; + parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0; + parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0; + parameter [4:0] PCIE3_CLK_COR_EMPTY_THRSH = 5'b00000; + parameter [5:0] PCIE3_CLK_COR_FULL_THRSH = 6'b010000; + parameter [4:0] PCIE3_CLK_COR_MAX_LAT = 5'b01000; + parameter [4:0] PCIE3_CLK_COR_MIN_LAT = 5'b00100; + parameter [5:0] PCIE3_CLK_COR_THRSH_TIMER = 6'b001000; + parameter PCIE_64B_DYN_CLKSW_DIS = "FALSE"; + parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000; + parameter PCIE_GEN4_64BIT_INT_EN = "FALSE"; + parameter [1:0] PCIE_PLL_SEL_MODE_GEN12 = 2'h0; + parameter [1:0] PCIE_PLL_SEL_MODE_GEN3 = 2'h0; + parameter [1:0] PCIE_PLL_SEL_MODE_GEN4 = 2'h0; + parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000; + parameter [15:0] PCIE_RXPMA_CFG = 16'h0000; + parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000; + parameter [15:0] PCIE_TXPMA_CFG = 16'h0000; + parameter PCS_PCIE_EN = "FALSE"; + parameter [15:0] PCS_RSVD0 = 16'h0000; + parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; + parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; + parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; + parameter integer PREIQ_FREQ_BST = 0; + parameter [0:0] RATE_SW_USE_DRP = 1'b0; + parameter [0:0] RCLK_SIPO_DLY_ENB = 1'b0; + parameter [0:0] RCLK_SIPO_INV_EN = 1'b0; + parameter [2:0] RTX_BUF_CML_CTRL = 3'b010; + parameter [1:0] RTX_BUF_TERM_CTRL = 2'b00; + parameter [4:0] RXBUFRESET_TIME = 5'b00001; + parameter RXBUF_ADDR_MODE = "FULL"; + parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; + parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; + parameter RXBUF_EN = "TRUE"; + parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; + parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; + parameter RXBUF_RESET_ON_EIDLE = "FALSE"; + parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; + parameter integer RXBUF_THRESH_OVFLW = 0; + parameter RXBUF_THRESH_OVRD = "FALSE"; + parameter integer RXBUF_THRESH_UNDFLW = 4; + parameter [4:0] RXCDRFREQRESET_TIME = 5'b10000; + parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; + parameter [15:0] RXCDR_CFG0 = 16'h0003; + parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0003; + parameter [15:0] RXCDR_CFG1 = 16'h0000; + parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000; + parameter [15:0] RXCDR_CFG2 = 16'h0164; + parameter [9:0] RXCDR_CFG2_GEN2 = 10'h164; + parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0034; + parameter [15:0] RXCDR_CFG2_GEN4 = 16'h0034; + parameter [15:0] RXCDR_CFG3 = 16'h0024; + parameter [5:0] RXCDR_CFG3_GEN2 = 6'h24; + parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0024; + parameter [15:0] RXCDR_CFG3_GEN4 = 16'h0024; + parameter [15:0] RXCDR_CFG4 = 16'h5CF6; + parameter [15:0] RXCDR_CFG4_GEN3 = 16'h5CF6; + parameter [15:0] RXCDR_CFG5 = 16'hB46B; + parameter [15:0] RXCDR_CFG5_GEN3 = 16'h146B; + parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; + parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; + parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0040; + parameter [15:0] RXCDR_LOCK_CFG1 = 16'h8000; + parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000; + parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000; + parameter [15:0] RXCDR_LOCK_CFG4 = 16'h0000; + parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; + parameter [15:0] RXCFOK_CFG0 = 16'h0000; + parameter [15:0] RXCFOK_CFG1 = 16'h0002; + parameter [15:0] RXCFOK_CFG2 = 16'h002D; + parameter [15:0] RXCKCAL1_IQ_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL1_I_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL1_Q_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL2_DX_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL2_D_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL2_S_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL2_X_LOOP_RST_CFG = 16'h0000; + parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; + parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000; + parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022; + parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100; + parameter [15:0] RXDFE_CFG0 = 16'h4000; + parameter [15:0] RXDFE_CFG1 = 16'h0000; + parameter [15:0] RXDFE_GC_CFG0 = 16'h0000; + parameter [15:0] RXDFE_GC_CFG1 = 16'h0000; + parameter [15:0] RXDFE_GC_CFG2 = 16'h0000; + parameter [15:0] RXDFE_H2_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H2_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H3_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H3_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H4_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H4_CFG1 = 16'h0003; + parameter [15:0] RXDFE_H5_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H5_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H6_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H6_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H7_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H7_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H8_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H8_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H9_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H9_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HA_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HA_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HB_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HB_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HC_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HC_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HD_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HD_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HE_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HE_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HF_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HF_CFG1 = 16'h0002; + parameter [15:0] RXDFE_KH_CFG0 = 16'h0000; + parameter [15:0] RXDFE_KH_CFG1 = 16'h0000; + parameter [15:0] RXDFE_KH_CFG2 = 16'h0000; + parameter [15:0] RXDFE_KH_CFG3 = 16'h2000; + parameter [15:0] RXDFE_OS_CFG0 = 16'h0000; + parameter [15:0] RXDFE_OS_CFG1 = 16'h0000; + parameter [15:0] RXDFE_UT_CFG0 = 16'h0000; + parameter [15:0] RXDFE_UT_CFG1 = 16'h0002; + parameter [15:0] RXDFE_UT_CFG2 = 16'h0000; + parameter [15:0] RXDFE_VP_CFG0 = 16'h0000; + parameter [15:0] RXDFE_VP_CFG1 = 16'h0022; + parameter [15:0] RXDLY_CFG = 16'h0010; + parameter [15:0] RXDLY_LCFG = 16'h0030; + parameter RXELECIDLE_CFG = "SIGCFG_4"; + parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4; + parameter RXGEARBOX_EN = "FALSE"; + parameter [4:0] RXISCANRESET_TIME = 5'b00001; + parameter [15:0] RXLPM_CFG = 16'h0000; + parameter [15:0] RXLPM_GC_CFG = 16'h1000; + parameter [15:0] RXLPM_KH_CFG0 = 16'h0000; + parameter [15:0] RXLPM_KH_CFG1 = 16'h0002; + parameter [15:0] RXLPM_OS_CFG0 = 16'h0000; + parameter [15:0] RXLPM_OS_CFG1 = 16'h0000; + parameter [8:0] RXOOB_CFG = 9'b000110000; + parameter RXOOB_CLK_CFG = "PMA"; + parameter [4:0] RXOSCALRESET_TIME = 5'b00011; + parameter integer RXOUT_DIV = 4; + parameter [4:0] RXPCSRESET_TIME = 5'b00001; + parameter [15:0] RXPHBEACON_CFG = 16'h0000; + parameter [15:0] RXPHDLY_CFG = 16'h2020; + parameter [15:0] RXPHSAMP_CFG = 16'h2100; + parameter [15:0] RXPHSLIP_CFG = 16'h9933; + parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; + parameter [15:0] RXPI_CFG0 = 16'h0102; + parameter [15:0] RXPI_CFG1 = 16'b0000000001010100; + parameter RXPMACLK_SEL = "DATA"; + parameter [4:0] RXPMARESET_TIME = 5'b00001; + parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; + parameter integer RXPRBS_LINKACQ_CNT = 15; + parameter [0:0] RXREFCLKDIV2_SEL = 1'b0; + parameter integer RXSLIDE_AUTO_WAIT = 7; + parameter RXSLIDE_MODE = "OFF"; + parameter [0:0] RXSYNC_MULTILANE = 1'b0; + parameter [0:0] RXSYNC_OVRD = 1'b0; + parameter [0:0] RXSYNC_SKIP_DA = 1'b0; + parameter [0:0] RX_AFE_CM_EN = 1'b0; + parameter [15:0] RX_BIAS_CFG0 = 16'h12B0; + parameter [5:0] RX_BUFFER_CFG = 6'b000000; + parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0; + parameter integer RX_CLK25_DIV = 8; + parameter [0:0] RX_CLKMUX_EN = 1'b1; + parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000; + parameter [3:0] RX_CM_BUF_CFG = 4'b1010; + parameter [0:0] RX_CM_BUF_PD = 1'b0; + parameter integer RX_CM_SEL = 2; + parameter integer RX_CM_TRIM = 12; + parameter [0:0] RX_CTLE_PWR_SAVING = 1'b0; + parameter [3:0] RX_CTLE_RES_CTRL = 4'b0000; + parameter integer RX_DATA_WIDTH = 20; + parameter [5:0] RX_DDI_SEL = 6'b000000; + parameter RX_DEFER_RESET_BUF_EN = "TRUE"; + parameter [2:0] RX_DEGEN_CTRL = 3'b100; + parameter integer RX_DFELPM_CFG0 = 10; + parameter [0:0] RX_DFELPM_CFG1 = 1'b1; + parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1; + parameter integer RX_DFE_AGC_CFG1 = 4; + parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1; + parameter integer RX_DFE_KL_LPM_KH_CFG1 = 2; + parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01; + parameter integer RX_DFE_KL_LPM_KL_CFG1 = 4; + parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; + parameter RX_DISPERR_SEQ_MATCH = "TRUE"; + parameter [4:0] RX_DIVRESET_TIME = 5'b00001; + parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0; + parameter integer RX_EN_SUM_RCAL_B = 0; + parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000; + parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0; + parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b10; + parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0; + parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0; + parameter [0:0] RX_I2V_FILTER_EN = 1'b1; + parameter integer RX_INT_DATAWIDTH = 1; + parameter [0:0] RX_PMA_POWER_SAVE = 1'b0; + parameter [15:0] RX_PMA_RSV0 = 16'h002F; + parameter real RX_PROGDIV_CFG = 0.0; + parameter [15:0] RX_PROGDIV_RATE = 16'h0001; + parameter [3:0] RX_RESLOAD_CTRL = 4'b0000; + parameter [0:0] RX_RESLOAD_OVRD = 1'b0; + parameter [2:0] RX_SAMPLE_PERIOD = 3'b101; + parameter integer RX_SIG_VALID_DLY = 11; + parameter integer RX_SUM_DEGEN_AVTT_OVERITE = 0; + parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0; + parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000; + parameter integer RX_SUM_PWR_SAVING = 0; + parameter [3:0] RX_SUM_RES_CTRL = 4'b0000; + parameter [3:0] RX_SUM_VCMTUNE = 4'b0011; + parameter [0:0] RX_SUM_VCM_BIAS_TUNE_EN = 1'b1; + parameter [0:0] RX_SUM_VCM_OVWR = 1'b0; + parameter [2:0] RX_SUM_VREF_TUNE = 3'b100; + parameter [1:0] RX_TUNE_AFE_OS = 2'b00; + parameter [2:0] RX_VREG_CTRL = 3'b010; + parameter [0:0] RX_VREG_PDB = 1'b1; + parameter [1:0] RX_WIDEMODE_CDR = 2'b01; + parameter [1:0] RX_WIDEMODE_CDR_GEN3 = 2'b01; + parameter [1:0] RX_WIDEMODE_CDR_GEN4 = 2'b01; + parameter RX_XCLK_SEL = "RXDES"; + parameter [0:0] RX_XMODE_SEL = 1'b0; + parameter [0:0] SAMPLE_CLK_PHASE = 1'b0; + parameter [0:0] SAS_12G_MODE = 1'b0; + parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; + parameter [2:0] SATA_BURST_VAL = 3'b100; + parameter SATA_CPLL_CFG = "VCO_3000MHZ"; + parameter [2:0] SATA_EIDLE_VAL = 3'b100; + parameter SHOW_REALIGN_COMMA = "TRUE"; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter SIM_MODE = "FAST"; + parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter SIM_TX_EIDLE_DRIVE_LEVEL = "Z"; + parameter [0:0] SRSTMODE = 1'b0; + parameter [1:0] TAPDLY_SET_TX = 2'h0; + parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; + parameter [2:0] TERM_RCAL_OVRD = 3'b000; + parameter [7:0] TRANS_TIME_RATE = 8'h0E; + parameter [7:0] TST_RSV0 = 8'h00; + parameter [7:0] TST_RSV1 = 8'h00; + parameter TXBUF_EN = "TRUE"; + parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; + parameter [15:0] TXDLY_CFG = 16'h0010; + parameter [15:0] TXDLY_LCFG = 16'h0030; + parameter integer TXDRV_FREQBAND = 0; + parameter [15:0] TXFE_CFG0 = 16'b0000000000000000; + parameter [15:0] TXFE_CFG1 = 16'b0000000000000000; + parameter [15:0] TXFE_CFG2 = 16'b0000000000000000; + parameter [15:0] TXFE_CFG3 = 16'b0000000000000000; + parameter TXFIFO_ADDR_CFG = "LOW"; + parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4; + parameter TXGEARBOX_EN = "FALSE"; + parameter integer TXOUT_DIV = 4; + parameter [4:0] TXPCSRESET_TIME = 5'b00001; + parameter [15:0] TXPHDLY_CFG0 = 16'h6020; + parameter [15:0] TXPHDLY_CFG1 = 16'h0002; + parameter [15:0] TXPH_CFG = 16'h0123; + parameter [15:0] TXPH_CFG2 = 16'h0000; + parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; + parameter [15:0] TXPI_CFG0 = 16'b0000000100000000; + parameter [15:0] TXPI_CFG1 = 16'b0000000000000000; + parameter [0:0] TXPI_GRAY_SEL = 1'b0; + parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; + parameter [0:0] TXPI_PPM = 1'b0; + parameter [7:0] TXPI_PPM_CFG = 8'b00000000; + parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; + parameter [4:0] TXPMARESET_TIME = 5'b00001; + parameter [0:0] TXREFCLKDIV2_SEL = 1'b0; + parameter integer TXSWBST_BST = 1; + parameter integer TXSWBST_EN = 0; + parameter integer TXSWBST_MAG = 6; + parameter [0:0] TXSYNC_MULTILANE = 1'b0; + parameter [0:0] TXSYNC_OVRD = 1'b0; + parameter [0:0] TXSYNC_SKIP_DA = 1'b0; + parameter integer TX_CLK25_DIV = 8; + parameter [0:0] TX_CLKMUX_EN = 1'b1; + parameter integer TX_DATA_WIDTH = 20; + parameter [15:0] TX_DCC_LOOP_RST_CFG = 16'h0000; + parameter [5:0] TX_DEEMPH0 = 6'b000000; + parameter [5:0] TX_DEEMPH1 = 6'b000000; + parameter [5:0] TX_DEEMPH2 = 6'b000000; + parameter [5:0] TX_DEEMPH3 = 6'b000000; + parameter [4:0] TX_DIVRESET_TIME = 5'b00001; + parameter TX_DRIVE_MODE = "DIRECT"; + parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; + parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; + parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0; + parameter [0:0] TX_FIFO_BYP_EN = 1'b0; + parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0; + parameter integer TX_INT_DATAWIDTH = 1; + parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; + parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; + parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; + parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; + parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; + parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; + parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; + parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; + parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; + parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; + parameter [15:0] TX_PHICAL_CFG0 = 16'h0000; + parameter [15:0] TX_PHICAL_CFG1 = 16'h003F; + parameter integer TX_PI_BIASSET = 0; + parameter [0:0] TX_PMADATA_OPT = 1'b0; + parameter [0:0] TX_PMA_POWER_SAVE = 1'b0; + parameter [15:0] TX_PMA_RSV0 = 16'h0000; + parameter [15:0] TX_PMA_RSV1 = 16'h0000; + parameter TX_PROGCLK_SEL = "POSTPI"; + parameter real TX_PROGDIV_CFG = 0.0; + parameter [15:0] TX_PROGDIV_RATE = 16'h0001; + parameter [13:0] TX_RXDETECT_CFG = 14'h0032; + parameter integer TX_RXDETECT_REF = 3; + parameter [2:0] TX_SAMPLE_PERIOD = 3'b101; + parameter [1:0] TX_SW_MEAS = 2'b00; + parameter [2:0] TX_VREG_CTRL = 3'b000; + parameter [0:0] TX_VREG_PDB = 1'b0; + parameter [1:0] TX_VREG_VREFSEL = 2'b00; + parameter TX_XCLK_SEL = "TXOUT"; + parameter [0:0] USB_BOTH_BURST_IDLE = 1'b0; + parameter [6:0] USB_BURSTMAX_U3WAKE = 7'b1111111; + parameter [6:0] USB_BURSTMIN_U3WAKE = 7'b1100011; + parameter [0:0] USB_CLK_COR_EQ_EN = 1'b0; + parameter [0:0] USB_EXT_CNTL = 1'b1; + parameter [9:0] USB_IDLEMAX_POLLING = 10'b1010111011; + parameter [9:0] USB_IDLEMIN_POLLING = 10'b0100101011; + parameter [8:0] USB_LFPSPING_BURST = 9'b000000101; + parameter [8:0] USB_LFPSPOLLING_BURST = 9'b000110001; + parameter [8:0] USB_LFPSPOLLING_IDLE_MS = 9'b000000100; + parameter [8:0] USB_LFPSU1EXIT_BURST = 9'b000011101; + parameter [8:0] USB_LFPSU2LPEXIT_BURST_MS = 9'b001100011; + parameter [8:0] USB_LFPSU3WAKE_BURST_MS = 9'b111110011; + parameter [3:0] USB_LFPS_TPERIOD = 4'b0011; + parameter [0:0] USB_LFPS_TPERIOD_ACCURATE = 1'b1; + parameter [0:0] USB_MODE = 1'b0; + parameter [0:0] USB_PCIE_ERR_REP_DIS = 1'b0; + parameter integer USB_PING_SATA_MAX_INIT = 21; + parameter integer USB_PING_SATA_MIN_INIT = 12; + parameter integer USB_POLL_SATA_MAX_BURST = 8; + parameter integer USB_POLL_SATA_MIN_BURST = 4; + parameter [0:0] USB_RAW_ELEC = 1'b0; + parameter [0:0] USB_RXIDLE_P0_CTRL = 1'b1; + parameter [0:0] USB_TXIDLE_TUNE_ENABLE = 1'b1; + parameter integer USB_U1_SATA_MAX_WAKE = 7; + parameter integer USB_U1_SATA_MIN_WAKE = 4; + parameter integer USB_U2_SAS_MAX_COM = 64; + parameter integer USB_U2_SAS_MIN_COM = 36; + parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; + parameter [0:0] Y_ALL_MODE = 1'b0; + output BUFGTCE; + output [2:0] BUFGTCEMASK; + output [8:0] BUFGTDIV; + output BUFGTRESET; + output [2:0] BUFGTRSTMASK; + output CPLLFBCLKLOST; + output CPLLLOCK; + output CPLLREFCLKLOST; + output [15:0] DMONITOROUT; + output DMONITOROUTCLK; + output [15:0] DRPDO; + output DRPRDY; + output EYESCANDATAERROR; + output GTPOWERGOOD; + output GTREFCLKMONITOR; + output GTYTXN; + output GTYTXP; + output PCIERATEGEN3; + output PCIERATEIDLE; + output [1:0] PCIERATEQPLLPD; + output [1:0] PCIERATEQPLLRESET; + output PCIESYNCTXSYNCDONE; + output PCIEUSERGEN3RDY; + output PCIEUSERPHYSTATUSRST; + output PCIEUSERRATESTART; + output [15:0] PCSRSVDOUT; + output PHYSTATUS; + output [15:0] PINRSRVDAS; + output POWERPRESENT; + output RESETEXCEPTION; + output [2:0] RXBUFSTATUS; + output RXBYTEISALIGNED; + output RXBYTEREALIGN; + output RXCDRLOCK; + output RXCDRPHDONE; + output RXCHANBONDSEQ; + output RXCHANISALIGNED; + output RXCHANREALIGN; + output [4:0] RXCHBONDO; + output RXCKCALDONE; + output [1:0] RXCLKCORCNT; + output RXCOMINITDET; + output RXCOMMADET; + output RXCOMSASDET; + output RXCOMWAKEDET; + output [15:0] RXCTRL0; + output [15:0] RXCTRL1; + output [7:0] RXCTRL2; + output [7:0] RXCTRL3; + output [127:0] RXDATA; + output [7:0] RXDATAEXTENDRSVD; + output [1:0] RXDATAVALID; + output RXDLYSRESETDONE; + output RXELECIDLE; + output [5:0] RXHEADER; + output [1:0] RXHEADERVALID; + output RXLFPSTRESETDET; + output RXLFPSU2LPEXITDET; + output RXLFPSU3WAKEDET; + output [7:0] RXMONITOROUT; + output RXOSINTDONE; + output RXOSINTSTARTED; + output RXOSINTSTROBEDONE; + output RXOSINTSTROBESTARTED; + output RXOUTCLK; + output RXOUTCLKFABRIC; + output RXOUTCLKPCS; + output RXPHALIGNDONE; + output RXPHALIGNERR; + output RXPMARESETDONE; + output RXPRBSERR; + output RXPRBSLOCKED; + output RXPRGDIVRESETDONE; + output RXRATEDONE; + output RXRECCLKOUT; + output RXRESETDONE; + output RXSLIDERDY; + output RXSLIPDONE; + output RXSLIPOUTCLKRDY; + output RXSLIPPMARDY; + output [1:0] RXSTARTOFSEQ; + output [2:0] RXSTATUS; + output RXSYNCDONE; + output RXSYNCOUT; + output RXVALID; + output [1:0] TXBUFSTATUS; + output TXCOMFINISH; + output TXDCCDONE; + output TXDLYSRESETDONE; + output TXOUTCLK; + output TXOUTCLKFABRIC; + output TXOUTCLKPCS; + output TXPHALIGNDONE; + output TXPHINITDONE; + output TXPMARESETDONE; + output TXPRGDIVRESETDONE; + output TXRATEDONE; + output TXRESETDONE; + output TXSYNCDONE; + output TXSYNCOUT; + input CDRSTEPDIR; + input CDRSTEPSQ; + input CDRSTEPSX; + input CFGRESET; + input CLKRSVD0; + input CLKRSVD1; + input CPLLFREQLOCK; + input CPLLLOCKDETCLK; + input CPLLLOCKEN; + input CPLLPD; + input [2:0] CPLLREFCLKSEL; + input CPLLRESET; + input DMONFIFORESET; + input DMONITORCLK; + input [9:0] DRPADDR; + input DRPCLK; + input [15:0] DRPDI; + input DRPEN; + input DRPRST; + input DRPWE; + input EYESCANRESET; + input EYESCANTRIGGER; + input FREQOS; + input GTGREFCLK; + input GTNORTHREFCLK0; + input GTNORTHREFCLK1; + input GTREFCLK0; + input GTREFCLK1; + input [15:0] GTRSVD; + input GTRXRESET; + input GTRXRESETSEL; + input GTSOUTHREFCLK0; + input GTSOUTHREFCLK1; + input GTTXRESET; + input GTTXRESETSEL; + input GTYRXN; + input GTYRXP; + input INCPCTRL; + input [2:0] LOOPBACK; + input PCIEEQRXEQADAPTDONE; + input PCIERSTIDLE; + input PCIERSTTXSYNCSTART; + input PCIEUSERRATEDONE; + input [15:0] PCSRSVDIN; + input QPLL0CLK; + input QPLL0FREQLOCK; + input QPLL0REFCLK; + input QPLL1CLK; + input QPLL1FREQLOCK; + input QPLL1REFCLK; + input RESETOVRD; + input RX8B10BEN; + input RXAFECFOKEN; + input RXBUFRESET; + input RXCDRFREQRESET; + input RXCDRHOLD; + input RXCDROVRDEN; + input RXCDRRESET; + input RXCHBONDEN; + input [4:0] RXCHBONDI; + input [2:0] RXCHBONDLEVEL; + input RXCHBONDMASTER; + input RXCHBONDSLAVE; + input RXCKCALRESET; + input [6:0] RXCKCALSTART; + input RXCOMMADETEN; + input RXDFEAGCHOLD; + input RXDFEAGCOVRDEN; + input [3:0] RXDFECFOKFCNUM; + input RXDFECFOKFEN; + input RXDFECFOKFPULSE; + input RXDFECFOKHOLD; + input RXDFECFOKOVREN; + input RXDFEKHHOLD; + input RXDFEKHOVRDEN; + input RXDFELFHOLD; + input RXDFELFOVRDEN; + input RXDFELPMRESET; + input RXDFETAP10HOLD; + input RXDFETAP10OVRDEN; + input RXDFETAP11HOLD; + input RXDFETAP11OVRDEN; + input RXDFETAP12HOLD; + input RXDFETAP12OVRDEN; + input RXDFETAP13HOLD; + input RXDFETAP13OVRDEN; + input RXDFETAP14HOLD; + input RXDFETAP14OVRDEN; + input RXDFETAP15HOLD; + input RXDFETAP15OVRDEN; + input RXDFETAP2HOLD; + input RXDFETAP2OVRDEN; + input RXDFETAP3HOLD; + input RXDFETAP3OVRDEN; + input RXDFETAP4HOLD; + input RXDFETAP4OVRDEN; + input RXDFETAP5HOLD; + input RXDFETAP5OVRDEN; + input RXDFETAP6HOLD; + input RXDFETAP6OVRDEN; + input RXDFETAP7HOLD; + input RXDFETAP7OVRDEN; + input RXDFETAP8HOLD; + input RXDFETAP8OVRDEN; + input RXDFETAP9HOLD; + input RXDFETAP9OVRDEN; + input RXDFEUTHOLD; + input RXDFEUTOVRDEN; + input RXDFEVPHOLD; + input RXDFEVPOVRDEN; + input RXDFEXYDEN; + input RXDLYBYPASS; + input RXDLYEN; + input RXDLYOVRDEN; + input RXDLYSRESET; + input [1:0] RXELECIDLEMODE; + input RXEQTRAINING; + input RXGEARBOXSLIP; + input RXLATCLK; + input RXLPMEN; + input RXLPMGCHOLD; + input RXLPMGCOVRDEN; + input RXLPMHFHOLD; + input RXLPMHFOVRDEN; + input RXLPMLFHOLD; + input RXLPMLFKLOVRDEN; + input RXLPMOSHOLD; + input RXLPMOSOVRDEN; + input RXMCOMMAALIGNEN; + input [1:0] RXMONITORSEL; + input RXOOBRESET; + input RXOSCALRESET; + input RXOSHOLD; + input RXOSOVRDEN; + input [2:0] RXOUTCLKSEL; + input RXPCOMMAALIGNEN; + input RXPCSRESET; + input [1:0] RXPD; + input RXPHALIGN; + input RXPHALIGNEN; + input RXPHDLYPD; + input RXPHDLYRESET; + input [1:0] RXPLLCLKSEL; + input RXPMARESET; + input RXPOLARITY; + input RXPRBSCNTRESET; + input [3:0] RXPRBSSEL; + input RXPROGDIVRESET; + input [2:0] RXRATE; + input RXRATEMODE; + input RXSLIDE; + input RXSLIPOUTCLK; + input RXSLIPPMA; + input RXSYNCALLIN; + input RXSYNCIN; + input RXSYNCMODE; + input [1:0] RXSYSCLKSEL; + input RXTERMINATION; + input RXUSERRDY; + input RXUSRCLK; + input RXUSRCLK2; + input SIGVALIDCLK; + input [19:0] TSTIN; + input [7:0] TX8B10BBYPASS; + input TX8B10BEN; + input TXCOMINIT; + input TXCOMSAS; + input TXCOMWAKE; + input [15:0] TXCTRL0; + input [15:0] TXCTRL1; + input [7:0] TXCTRL2; + input [127:0] TXDATA; + input [7:0] TXDATAEXTENDRSVD; + input TXDCCFORCESTART; + input TXDCCRESET; + input [1:0] TXDEEMPH; + input TXDETECTRX; + input [4:0] TXDIFFCTRL; + input TXDLYBYPASS; + input TXDLYEN; + input TXDLYHOLD; + input TXDLYOVRDEN; + input TXDLYSRESET; + input TXDLYUPDOWN; + input TXELECIDLE; + input [5:0] TXHEADER; + input TXINHIBIT; + input TXLATCLK; + input TXLFPSTRESET; + input TXLFPSU2LPEXIT; + input TXLFPSU3WAKE; + input [6:0] TXMAINCURSOR; + input [2:0] TXMARGIN; + input TXMUXDCDEXHOLD; + input TXMUXDCDORWREN; + input TXONESZEROS; + input [2:0] TXOUTCLKSEL; + input TXPCSRESET; + input [1:0] TXPD; + input TXPDELECIDLEMODE; + input TXPHALIGN; + input TXPHALIGNEN; + input TXPHDLYPD; + input TXPHDLYRESET; + input TXPHDLYTSTCLK; + input TXPHINIT; + input TXPHOVRDEN; + input TXPIPPMEN; + input TXPIPPMOVRDEN; + input TXPIPPMPD; + input TXPIPPMSEL; + input [4:0] TXPIPPMSTEPSIZE; + input TXPISOPD; + input [1:0] TXPLLCLKSEL; + input TXPMARESET; + input TXPOLARITY; + input [4:0] TXPOSTCURSOR; + input TXPRBSFORCEERR; + input [3:0] TXPRBSSEL; + input [4:0] TXPRECURSOR; + input TXPROGDIVRESET; + input [2:0] TXRATE; + input TXRATEMODE; + input [6:0] TXSEQUENCE; + input TXSWING; + input TXSYNCALLIN; + input TXSYNCIN; + input TXSYNCMODE; + input [1:0] TXSYSCLKSEL; + input TXUSERRDY; + input TXUSRCLK; + input TXUSRCLK2; +endmodule + +module GTYE4_COMMON (...); + parameter [0:0] AEN_QPLL0_FBDIV = 1'b1; + parameter [0:0] AEN_QPLL1_FBDIV = 1'b1; + parameter [0:0] AEN_SDM0TOGGLE = 1'b0; + parameter [0:0] AEN_SDM1TOGGLE = 1'b0; + parameter [0:0] A_SDM0TOGGLE = 1'b0; + parameter [8:0] A_SDM1DATA_HIGH = 9'b000000000; + parameter [15:0] A_SDM1DATA_LOW = 16'b0000000000000000; + parameter [0:0] A_SDM1TOGGLE = 1'b0; + parameter [15:0] BIAS_CFG0 = 16'h0000; + parameter [15:0] BIAS_CFG1 = 16'h0000; + parameter [15:0] BIAS_CFG2 = 16'h0000; + parameter [15:0] BIAS_CFG3 = 16'h0000; + parameter [15:0] BIAS_CFG4 = 16'h0000; + parameter [15:0] BIAS_CFG_RSVD = 16'h0000; + parameter [15:0] COMMON_CFG0 = 16'h0000; + parameter [15:0] COMMON_CFG1 = 16'h0000; + parameter [15:0] POR_CFG = 16'h0000; + parameter [15:0] PPF0_CFG = 16'h0F00; + parameter [15:0] PPF1_CFG = 16'h0F00; + parameter QPLL0CLKOUT_RATE = "FULL"; + parameter [15:0] QPLL0_CFG0 = 16'h391C; + parameter [15:0] QPLL0_CFG1 = 16'h0000; + parameter [15:0] QPLL0_CFG1_G3 = 16'h0020; + parameter [15:0] QPLL0_CFG2 = 16'h0F80; + parameter [15:0] QPLL0_CFG2_G3 = 16'h0F80; + parameter [15:0] QPLL0_CFG3 = 16'h0120; + parameter [15:0] QPLL0_CFG4 = 16'h0002; + parameter [9:0] QPLL0_CP = 10'b0000011111; + parameter [9:0] QPLL0_CP_G3 = 10'b0000011111; + parameter integer QPLL0_FBDIV = 66; + parameter integer QPLL0_FBDIV_G3 = 80; + parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000; + parameter [7:0] QPLL0_INIT_CFG1 = 8'h00; + parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8; + parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8; + parameter [9:0] QPLL0_LPF = 10'b1011111111; + parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111; + parameter [0:0] QPLL0_PCI_EN = 1'b0; + parameter [0:0] QPLL0_RATE_SW_USE_DRP = 1'b0; + parameter integer QPLL0_REFCLK_DIV = 1; + parameter [15:0] QPLL0_SDM_CFG0 = 16'h0040; + parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000; + parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000; + parameter QPLL1CLKOUT_RATE = "FULL"; + parameter [15:0] QPLL1_CFG0 = 16'h691C; + parameter [15:0] QPLL1_CFG1 = 16'h0020; + parameter [15:0] QPLL1_CFG1_G3 = 16'h0020; + parameter [15:0] QPLL1_CFG2 = 16'h0F80; + parameter [15:0] QPLL1_CFG2_G3 = 16'h0F80; + parameter [15:0] QPLL1_CFG3 = 16'h0120; + parameter [15:0] QPLL1_CFG4 = 16'h0002; + parameter [9:0] QPLL1_CP = 10'b0000011111; + parameter [9:0] QPLL1_CP_G3 = 10'b0000011111; + parameter integer QPLL1_FBDIV = 66; + parameter integer QPLL1_FBDIV_G3 = 80; + parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000; + parameter [7:0] QPLL1_INIT_CFG1 = 8'h00; + parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8; + parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8; + parameter [9:0] QPLL1_LPF = 10'b1011111111; + parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111; + parameter [0:0] QPLL1_PCI_EN = 1'b0; + parameter [0:0] QPLL1_RATE_SW_USE_DRP = 1'b0; + parameter integer QPLL1_REFCLK_DIV = 1; + parameter [15:0] QPLL1_SDM_CFG0 = 16'h0000; + parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000; + parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000; + parameter [15:0] RSVD_ATTR0 = 16'h0000; + parameter [15:0] RSVD_ATTR1 = 16'h0000; + parameter [15:0] RSVD_ATTR2 = 16'h0000; + parameter [15:0] RSVD_ATTR3 = 16'h0000; + parameter [1:0] RXRECCLKOUT0_SEL = 2'b00; + parameter [1:0] RXRECCLKOUT1_SEL = 2'b00; + parameter [0:0] SARC_ENB = 1'b0; + parameter [0:0] SARC_SEL = 1'b0; + parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000; + parameter [8:0] SDM0INITSEED0_1 = 9'b000000000; + parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000; + parameter [8:0] SDM1INITSEED0_1 = 9'b000000000; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter SIM_MODE = "FAST"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter [15:0] UB_CFG0 = 16'h0000; + parameter [15:0] UB_CFG1 = 16'h0000; + parameter [15:0] UB_CFG2 = 16'h0000; + parameter [15:0] UB_CFG3 = 16'h0000; + parameter [15:0] UB_CFG4 = 16'h0000; + parameter [15:0] UB_CFG5 = 16'h0400; + parameter [15:0] UB_CFG6 = 16'h0000; + output [15:0] DRPDO; + output DRPRDY; + output [7:0] PMARSVDOUT0; + output [7:0] PMARSVDOUT1; + output QPLL0FBCLKLOST; + output QPLL0LOCK; + output QPLL0OUTCLK; + output QPLL0OUTREFCLK; + output QPLL0REFCLKLOST; + output QPLL1FBCLKLOST; + output QPLL1LOCK; + output QPLL1OUTCLK; + output QPLL1OUTREFCLK; + output QPLL1REFCLKLOST; + output [7:0] QPLLDMONITOR0; + output [7:0] QPLLDMONITOR1; + output REFCLKOUTMONITOR0; + output REFCLKOUTMONITOR1; + output [1:0] RXRECCLK0SEL; + output [1:0] RXRECCLK1SEL; + output [3:0] SDM0FINALOUT; + output [14:0] SDM0TESTDATA; + output [3:0] SDM1FINALOUT; + output [14:0] SDM1TESTDATA; + output [15:0] UBDADDR; + output UBDEN; + output [15:0] UBDI; + output UBDWE; + output UBMDMTDO; + output UBRSVDOUT; + output UBTXUART; + input BGBYPASSB; + input BGMONITORENB; + input BGPDB; + input [4:0] BGRCALOVRD; + input BGRCALOVRDENB; + input [15:0] DRPADDR; + input DRPCLK; + input [15:0] DRPDI; + input DRPEN; + input DRPWE; + input GTGREFCLK0; + input GTGREFCLK1; + input GTNORTHREFCLK00; + input GTNORTHREFCLK01; + input GTNORTHREFCLK10; + input GTNORTHREFCLK11; + input GTREFCLK00; + input GTREFCLK01; + input GTREFCLK10; + input GTREFCLK11; + input GTSOUTHREFCLK00; + input GTSOUTHREFCLK01; + input GTSOUTHREFCLK10; + input GTSOUTHREFCLK11; + input [2:0] PCIERATEQPLL0; + input [2:0] PCIERATEQPLL1; + input [7:0] PMARSVD0; + input [7:0] PMARSVD1; + input QPLL0CLKRSVD0; + input QPLL0CLKRSVD1; + input [7:0] QPLL0FBDIV; + input QPLL0LOCKDETCLK; + input QPLL0LOCKEN; + input QPLL0PD; + input [2:0] QPLL0REFCLKSEL; + input QPLL0RESET; + input QPLL1CLKRSVD0; + input QPLL1CLKRSVD1; + input [7:0] QPLL1FBDIV; + input QPLL1LOCKDETCLK; + input QPLL1LOCKEN; + input QPLL1PD; + input [2:0] QPLL1REFCLKSEL; + input QPLL1RESET; + input [7:0] QPLLRSVD1; + input [4:0] QPLLRSVD2; + input [4:0] QPLLRSVD3; + input [7:0] QPLLRSVD4; + input RCALENB; + input [24:0] SDM0DATA; + input SDM0RESET; + input SDM0TOGGLE; + input [1:0] SDM0WIDTH; + input [24:0] SDM1DATA; + input SDM1RESET; + input SDM1TOGGLE; + input [1:0] SDM1WIDTH; + input UBCFGSTREAMEN; + input [15:0] UBDO; + input UBDRDY; + input UBENABLE; + input [1:0] UBGPI; + input [1:0] UBINTR; + input UBIOLMBRST; + input UBMBRST; + input UBMDMCAPTURE; + input UBMDMDBGRST; + input UBMDMDBGUPDATE; + input [3:0] UBMDMREGEN; + input UBMDMSHIFT; + input UBMDMSYSRST; + input UBMDMTCK; + input UBMDMTDI; +endmodule + +module IBUFDS_GTE4 (...); + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; + parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00; + parameter [1:0] REFCLK_ICNTL_RX = 2'b00; + output O; + output ODIV2; + input CEB; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; +endmodule + +module OBUFDS_GTE4 (...); + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; + parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; + (* iopad_external_pin *) + output O; + (* iopad_external_pin *) + output OB; + input CEB; + input I; +endmodule + +module OBUFDS_GTE4_ADV (...); + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; + parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; + (* iopad_external_pin *) + output O; + (* iopad_external_pin *) + output OB; + input CEB; + input [3:0] I; + input [1:0] RXRECCLK_SEL; +endmodule + +module GTM_DUAL (...); + parameter [15:0] A_CFG = 16'b0000100001000000; + parameter [15:0] A_SDM_DATA_CFG0 = 16'b0000000011010000; + parameter [15:0] A_SDM_DATA_CFG1 = 16'b0000000011010000; + parameter [15:0] BIAS_CFG0 = 16'b0000000000000000; + parameter [15:0] BIAS_CFG1 = 16'b0000000000000000; + parameter [15:0] BIAS_CFG2 = 16'b0001000000000000; + parameter [15:0] BIAS_CFG3 = 16'b0000000000000001; + parameter [15:0] BIAS_CFG4 = 16'b0000000000000000; + parameter [15:0] BIAS_CFG5 = 16'b0000000000000000; + parameter [15:0] BIAS_CFG6 = 16'b0000000010000000; + parameter [15:0] BIAS_CFG7 = 16'b0000000000000000; + parameter [15:0] CH0_A_CH_CFG0 = 16'b0000000000000011; + parameter [15:0] CH0_A_CH_CFG1 = 16'b0000000000000000; + parameter [15:0] CH0_A_CH_CFG2 = 16'b0111101111110000; + parameter [15:0] CH0_A_CH_CFG3 = 16'b0000000000000000; + parameter [15:0] CH0_A_CH_CFG4 = 16'b0000000000000000; + parameter [15:0] CH0_A_CH_CFG5 = 16'b0000000000000000; + parameter [15:0] CH0_A_CH_CFG6 = 16'b0000000000000000; + parameter [15:0] CH0_RST_LP_CFG0 = 16'b0001000000010000; + parameter [15:0] CH0_RST_LP_CFG1 = 16'b0011001000010000; + parameter [15:0] CH0_RST_LP_CFG2 = 16'b0110010100000100; + parameter [15:0] CH0_RST_LP_CFG3 = 16'b0011001000010000; + parameter [15:0] CH0_RST_LP_CFG4 = 16'b0000000001000100; + parameter [15:0] CH0_RST_LP_ID_CFG0 = 16'b0011000001110000; + parameter [15:0] CH0_RST_LP_ID_CFG1 = 16'b0001000000010000; + parameter [15:0] CH0_RST_TIME_CFG0 = 16'b0000010000100001; + parameter [15:0] CH0_RST_TIME_CFG1 = 16'b0000010000100001; + parameter [15:0] CH0_RST_TIME_CFG2 = 16'b0000010000100001; + parameter [15:0] CH0_RST_TIME_CFG3 = 16'b0000010000100000; + parameter [15:0] CH0_RST_TIME_CFG4 = 16'b0000010000100001; + parameter [15:0] CH0_RST_TIME_CFG5 = 16'b0000000000000001; + parameter [15:0] CH0_RST_TIME_CFG6 = 16'b0000000000100001; + parameter [15:0] CH0_RX_ADC_CFG0 = 16'b0011010010001111; + parameter [15:0] CH0_RX_ADC_CFG1 = 16'b0011111001010101; + parameter [15:0] CH0_RX_ANA_CFG0 = 16'b1000000000011101; + parameter [15:0] CH0_RX_ANA_CFG1 = 16'b1110100010000000; + parameter [15:0] CH0_RX_ANA_CFG2 = 16'b0000000010001010; + parameter [15:0] CH0_RX_APT_CFG0A = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG0B = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG10A = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG10B = 16'b0000000001010000; + parameter [15:0] CH0_RX_APT_CFG11A = 16'b0000000001000000; + parameter [15:0] CH0_RX_APT_CFG11B = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG12A = 16'b0000000001010000; + parameter [15:0] CH0_RX_APT_CFG12B = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG13A = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG13B = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG14A = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG14B = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG15A = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG15B = 16'b0000100000000000; + parameter [15:0] CH0_RX_APT_CFG16A = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG16B = 16'b0010000000000000; + parameter [15:0] CH0_RX_APT_CFG17A = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG17B = 16'b0001000001000000; + parameter [15:0] CH0_RX_APT_CFG18A = 16'b0000100000100000; + parameter [15:0] CH0_RX_APT_CFG18B = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG19A = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG19B = 16'b0000100000000000; + parameter [15:0] CH0_RX_APT_CFG1A = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG1B = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG20A = 16'b1110000000100000; + parameter [15:0] CH0_RX_APT_CFG20B = 16'b0000000001000000; + parameter [15:0] CH0_RX_APT_CFG21A = 16'b0001000000000100; + parameter [15:0] CH0_RX_APT_CFG21B = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG22A = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG22B = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG23A = 16'b0000100000000000; + parameter [15:0] CH0_RX_APT_CFG23B = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG24A = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG24B = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG25A = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG25B = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG26A = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG26B = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG27A = 16'b0100000000000000; + parameter [15:0] CH0_RX_APT_CFG27B = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG28A = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG28B = 16'b1000000000000000; + parameter [15:0] CH0_RX_APT_CFG2A = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG2B = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG3A = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG3B = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG4A = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG4B = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG5A = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG5B = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG6A = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG6B = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG7A = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG7B = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG8A = 16'b0000100000000000; + parameter [15:0] CH0_RX_APT_CFG8B = 16'b0000100000000000; + parameter [15:0] CH0_RX_APT_CFG9A = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG9B = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CTRL_CFG2 = 16'b0000000000000100; + parameter [15:0] CH0_RX_APT_CTRL_CFG3 = 16'b0000000000000000; + parameter [15:0] CH0_RX_CAL_CFG0A = 16'b0000000000000000; + parameter [15:0] CH0_RX_CAL_CFG0B = 16'b0011001100110000; + parameter [15:0] CH0_RX_CAL_CFG1A = 16'b1110111011100001; + parameter [15:0] CH0_RX_CAL_CFG1B = 16'b1111111100000100; + parameter [15:0] CH0_RX_CAL_CFG2A = 16'b0000000000000000; + parameter [15:0] CH0_RX_CAL_CFG2B = 16'b0011000000000000; + parameter [15:0] CH0_RX_CDR_CFG0A = 16'b0000000000000011; + parameter [15:0] CH0_RX_CDR_CFG0B = 16'b0000000000000000; + parameter [15:0] CH0_RX_CDR_CFG1A = 16'b0000000000000000; + parameter [15:0] CH0_RX_CDR_CFG1B = 16'b0000000000000000; + parameter [15:0] CH0_RX_CDR_CFG2A = 16'b1001000101100100; + parameter [15:0] CH0_RX_CDR_CFG2B = 16'b0000000100100100; + parameter [15:0] CH0_RX_CDR_CFG3A = 16'b0101110011110110; + parameter [15:0] CH0_RX_CDR_CFG3B = 16'b0000000000001011; + parameter [15:0] CH0_RX_CDR_CFG4A = 16'b0000000000000110; + parameter [15:0] CH0_RX_CDR_CFG4B = 16'b0000000000000000; + parameter [15:0] CH0_RX_CLKGN_CFG0 = 16'b1100000000000000; + parameter [15:0] CH0_RX_CLKGN_CFG1 = 16'b0000000110000000; + parameter [15:0] CH0_RX_CTLE_CFG0 = 16'b0011010010001000; + parameter [15:0] CH0_RX_CTLE_CFG1 = 16'b0010000000100010; + parameter [15:0] CH0_RX_CTLE_CFG2 = 16'b0000101000000000; + parameter [15:0] CH0_RX_CTLE_CFG3 = 16'b1111001001000000; + parameter [15:0] CH0_RX_DSP_CFG = 16'b0000000000000000; + parameter [15:0] CH0_RX_MON_CFG = 16'b0000000000000000; + parameter [15:0] CH0_RX_PAD_CFG0 = 16'b0001111000000000; + parameter [15:0] CH0_RX_PAD_CFG1 = 16'b0001100000001010; + parameter [15:0] CH0_RX_PCS_CFG0 = 16'b0000000100000000; + parameter [15:0] CH0_RX_PCS_CFG1 = 16'b0000000000000000; + parameter [15:0] CH0_TX_ANA_CFG0 = 16'b0000001010101111; + parameter [15:0] CH0_TX_ANA_CFG1 = 16'b0000000100000000; + parameter [15:0] CH0_TX_ANA_CFG2 = 16'b1000000000010100; + parameter [15:0] CH0_TX_ANA_CFG3 = 16'b0000101000100010; + parameter [15:0] CH0_TX_ANA_CFG4 = 16'b0000000000000000; + parameter [15:0] CH0_TX_CAL_CFG0 = 16'b0000000000100000; + parameter [15:0] CH0_TX_CAL_CFG1 = 16'b0000000001000000; + parameter [15:0] CH0_TX_DRV_CFG0 = 16'b0000000000000000; + parameter [15:0] CH0_TX_DRV_CFG1 = 16'b0000000000100111; + parameter [15:0] CH0_TX_DRV_CFG2 = 16'b0000000000000000; + parameter [15:0] CH0_TX_DRV_CFG3 = 16'b0110110000000000; + parameter [15:0] CH0_TX_DRV_CFG4 = 16'b0000000011000101; + parameter [15:0] CH0_TX_DRV_CFG5 = 16'b0000000000000000; + parameter [15:0] CH0_TX_LPBK_CFG0 = 16'b0000000000000011; + parameter [15:0] CH0_TX_LPBK_CFG1 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG0 = 16'b0000000101100000; + parameter [15:0] CH0_TX_PCS_CFG1 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG10 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG11 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG12 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG13 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG14 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG15 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG16 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG17 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG2 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG3 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG4 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG5 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG6 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG7 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG8 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG9 = 16'b0000000000000000; + parameter [15:0] CH1_A_CH_CFG0 = 16'b0000000000000011; + parameter [15:0] CH1_A_CH_CFG1 = 16'b0000000000000000; + parameter [15:0] CH1_A_CH_CFG2 = 16'b0111101111110000; + parameter [15:0] CH1_A_CH_CFG3 = 16'b0000000000000000; + parameter [15:0] CH1_A_CH_CFG4 = 16'b0000000000000000; + parameter [15:0] CH1_A_CH_CFG5 = 16'b0000000000000000; + parameter [15:0] CH1_A_CH_CFG6 = 16'b0000000000000000; + parameter [15:0] CH1_RST_LP_CFG0 = 16'b0001000000010000; + parameter [15:0] CH1_RST_LP_CFG1 = 16'b0011001000010000; + parameter [15:0] CH1_RST_LP_CFG2 = 16'b0110010100000100; + parameter [15:0] CH1_RST_LP_CFG3 = 16'b0011001000010000; + parameter [15:0] CH1_RST_LP_CFG4 = 16'b0000000001000100; + parameter [15:0] CH1_RST_LP_ID_CFG0 = 16'b0011000001110000; + parameter [15:0] CH1_RST_LP_ID_CFG1 = 16'b0001000000010000; + parameter [15:0] CH1_RST_TIME_CFG0 = 16'b0000010000100001; + parameter [15:0] CH1_RST_TIME_CFG1 = 16'b0000010000100001; + parameter [15:0] CH1_RST_TIME_CFG2 = 16'b0000010000100001; + parameter [15:0] CH1_RST_TIME_CFG3 = 16'b0000010000100000; + parameter [15:0] CH1_RST_TIME_CFG4 = 16'b0000010000100001; + parameter [15:0] CH1_RST_TIME_CFG5 = 16'b0000000000000001; + parameter [15:0] CH1_RST_TIME_CFG6 = 16'b0000000000100001; + parameter [15:0] CH1_RX_ADC_CFG0 = 16'b0011010010001111; + parameter [15:0] CH1_RX_ADC_CFG1 = 16'b0011111001010101; + parameter [15:0] CH1_RX_ANA_CFG0 = 16'b1000000000011101; + parameter [15:0] CH1_RX_ANA_CFG1 = 16'b1110100010000000; + parameter [15:0] CH1_RX_ANA_CFG2 = 16'b0000000010001010; + parameter [15:0] CH1_RX_APT_CFG0A = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG0B = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG10A = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG10B = 16'b0000000001010000; + parameter [15:0] CH1_RX_APT_CFG11A = 16'b0000000001000000; + parameter [15:0] CH1_RX_APT_CFG11B = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG12A = 16'b0000000001010000; + parameter [15:0] CH1_RX_APT_CFG12B = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG13A = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG13B = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG14A = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG14B = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG15A = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG15B = 16'b0000100000000000; + parameter [15:0] CH1_RX_APT_CFG16A = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG16B = 16'b0010000000000000; + parameter [15:0] CH1_RX_APT_CFG17A = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG17B = 16'b0001000001000000; + parameter [15:0] CH1_RX_APT_CFG18A = 16'b0000100000100000; + parameter [15:0] CH1_RX_APT_CFG18B = 16'b0000100010000000; + parameter [15:0] CH1_RX_APT_CFG19A = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG19B = 16'b0000100000000000; + parameter [15:0] CH1_RX_APT_CFG1A = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG1B = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG20A = 16'b1110000000100000; + parameter [15:0] CH1_RX_APT_CFG20B = 16'b0000000001000000; + parameter [15:0] CH1_RX_APT_CFG21A = 16'b0001000000000100; + parameter [15:0] CH1_RX_APT_CFG21B = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG22A = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG22B = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG23A = 16'b0000100000000000; + parameter [15:0] CH1_RX_APT_CFG23B = 16'b0000100000000000; + parameter [15:0] CH1_RX_APT_CFG24A = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG24B = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG25A = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG25B = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG26A = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG26B = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG27A = 16'b0100000000000000; + parameter [15:0] CH1_RX_APT_CFG27B = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG28A = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG28B = 16'b1000000000000000; + parameter [15:0] CH1_RX_APT_CFG2A = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG2B = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG3A = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG3B = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG4A = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG4B = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG5A = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG5B = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG6A = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG6B = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG7A = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG7B = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG8A = 16'b0000100000000000; + parameter [15:0] CH1_RX_APT_CFG8B = 16'b0000100000000000; + parameter [15:0] CH1_RX_APT_CFG9A = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG9B = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CTRL_CFG2 = 16'b0000000000000100; + parameter [15:0] CH1_RX_APT_CTRL_CFG3 = 16'b0000000000000000; + parameter [15:0] CH1_RX_CAL_CFG0A = 16'b0000000000000000; + parameter [15:0] CH1_RX_CAL_CFG0B = 16'b0011001100110000; + parameter [15:0] CH1_RX_CAL_CFG1A = 16'b1110111011100001; + parameter [15:0] CH1_RX_CAL_CFG1B = 16'b1111111100000100; + parameter [15:0] CH1_RX_CAL_CFG2A = 16'b0000000000000000; + parameter [15:0] CH1_RX_CAL_CFG2B = 16'b0011000000000000; + parameter [15:0] CH1_RX_CDR_CFG0A = 16'b0000000000000011; + parameter [15:0] CH1_RX_CDR_CFG0B = 16'b0000000000000000; + parameter [15:0] CH1_RX_CDR_CFG1A = 16'b0000000000000000; + parameter [15:0] CH1_RX_CDR_CFG1B = 16'b0000000000000000; + parameter [15:0] CH1_RX_CDR_CFG2A = 16'b1001000101100100; + parameter [15:0] CH1_RX_CDR_CFG2B = 16'b0000000100100100; + parameter [15:0] CH1_RX_CDR_CFG3A = 16'b0101110011110110; + parameter [15:0] CH1_RX_CDR_CFG3B = 16'b0000000000001011; + parameter [15:0] CH1_RX_CDR_CFG4A = 16'b0000000000000110; + parameter [15:0] CH1_RX_CDR_CFG4B = 16'b0000000000000000; + parameter [15:0] CH1_RX_CLKGN_CFG0 = 16'b1100000000000000; + parameter [15:0] CH1_RX_CLKGN_CFG1 = 16'b0000000110000000; + parameter [15:0] CH1_RX_CTLE_CFG0 = 16'b0011010010001000; + parameter [15:0] CH1_RX_CTLE_CFG1 = 16'b0010000000100010; + parameter [15:0] CH1_RX_CTLE_CFG2 = 16'b0000101000000000; + parameter [15:0] CH1_RX_CTLE_CFG3 = 16'b1111001001000000; + parameter [15:0] CH1_RX_DSP_CFG = 16'b0000000000000000; + parameter [15:0] CH1_RX_MON_CFG = 16'b0000000000000000; + parameter [15:0] CH1_RX_PAD_CFG0 = 16'b0001111000000000; + parameter [15:0] CH1_RX_PAD_CFG1 = 16'b0001100000001010; + parameter [15:0] CH1_RX_PCS_CFG0 = 16'b0000000100000000; + parameter [15:0] CH1_RX_PCS_CFG1 = 16'b0000000000000000; + parameter [15:0] CH1_TX_ANA_CFG0 = 16'b0000001010101111; + parameter [15:0] CH1_TX_ANA_CFG1 = 16'b0000000100000000; + parameter [15:0] CH1_TX_ANA_CFG2 = 16'b1000000000010100; + parameter [15:0] CH1_TX_ANA_CFG3 = 16'b0000101000100010; + parameter [15:0] CH1_TX_ANA_CFG4 = 16'b0000000000000000; + parameter [15:0] CH1_TX_CAL_CFG0 = 16'b0000000000100000; + parameter [15:0] CH1_TX_CAL_CFG1 = 16'b0000000001000000; + parameter [15:0] CH1_TX_DRV_CFG0 = 16'b0000000000000000; + parameter [15:0] CH1_TX_DRV_CFG1 = 16'b0000000000100111; + parameter [15:0] CH1_TX_DRV_CFG2 = 16'b0000000000000000; + parameter [15:0] CH1_TX_DRV_CFG3 = 16'b0110110000000000; + parameter [15:0] CH1_TX_DRV_CFG4 = 16'b0000000011000101; + parameter [15:0] CH1_TX_DRV_CFG5 = 16'b0000000000000000; + parameter [15:0] CH1_TX_LPBK_CFG0 = 16'b0000000000000011; + parameter [15:0] CH1_TX_LPBK_CFG1 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG0 = 16'b0000000101100000; + parameter [15:0] CH1_TX_PCS_CFG1 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG10 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG11 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG12 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG13 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG14 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG15 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG16 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG17 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG2 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG3 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG4 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG5 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG6 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG7 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG8 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG9 = 16'b0000000000000000; + parameter real DATARATE = 10.000; + parameter [15:0] DRPEN_CFG = 16'b0000000000000000; + parameter [15:0] FEC_CFG0 = 16'b0000000000000000; + parameter [15:0] FEC_CFG1 = 16'b0000000000000000; + parameter [15:0] FEC_CFG10 = 16'b0000000000000000; + parameter [15:0] FEC_CFG11 = 16'b0000000000000000; + parameter [15:0] FEC_CFG12 = 16'b0000000000000000; + parameter [15:0] FEC_CFG13 = 16'b0000000000000000; + parameter [15:0] FEC_CFG14 = 16'b0000000000000000; + parameter [15:0] FEC_CFG15 = 16'b0000000000000000; + parameter [15:0] FEC_CFG16 = 16'b0000000000000000; + parameter [15:0] FEC_CFG17 = 16'b0000000000000000; + parameter [15:0] FEC_CFG18 = 16'b0000000000000000; + parameter [15:0] FEC_CFG19 = 16'b0000000000000000; + parameter [15:0] FEC_CFG2 = 16'b0000000000000000; + parameter [15:0] FEC_CFG20 = 16'b0000000000000000; + parameter [15:0] FEC_CFG21 = 16'b0000000000000000; + parameter [15:0] FEC_CFG22 = 16'b0000000000000000; + parameter [15:0] FEC_CFG23 = 16'b0000000000000000; + parameter [15:0] FEC_CFG24 = 16'b0000000000000000; + parameter [15:0] FEC_CFG25 = 16'b0000000000000000; + parameter [15:0] FEC_CFG26 = 16'b0000000000000000; + parameter [15:0] FEC_CFG27 = 16'b0000000000000000; + parameter [15:0] FEC_CFG3 = 16'b0000000000000000; + parameter [15:0] FEC_CFG4 = 16'b0000000000000000; + parameter [15:0] FEC_CFG5 = 16'b0000000000000000; + parameter [15:0] FEC_CFG6 = 16'b0000000000000000; + parameter [15:0] FEC_CFG7 = 16'b0000000000000000; + parameter [15:0] FEC_CFG8 = 16'b0000000000000000; + parameter [15:0] FEC_CFG9 = 16'b0000000000000000; + parameter FEC_MODE = "BYPASS"; + parameter real INS_LOSS_NYQ = 20.000; + parameter integer INTERFACE_WIDTH = 64; + parameter MODULATION_MODE = "NRZ"; + parameter [15:0] PLL_CFG0 = 16'b0001100111110000; + parameter [15:0] PLL_CFG1 = 16'b0000111101110000; + parameter [15:0] PLL_CFG2 = 16'b1000000111101000; + parameter [15:0] PLL_CFG3 = 16'b0100000000000000; + parameter [15:0] PLL_CFG4 = 16'b0111111111101010; + parameter [15:0] PLL_CFG5 = 16'b0100101100111000; + parameter [15:0] PLL_CFG6 = 16'b0000000000100101; + parameter [15:0] PLL_CRS_CTRL_CFG0 = 16'b0000101100100000; + parameter [15:0] PLL_CRS_CTRL_CFG1 = 16'b1100010111010100; + parameter [0:0] PLL_IPS_PIN_EN = 1'b1; + parameter integer PLL_IPS_REFCLK_SEL = 0; + parameter [0:0] RCALSAP_TESTEN = 1'b0; + parameter [0:0] RCAL_APROBE = 1'b0; + parameter [15:0] RST_CFG = 16'b0000000000000010; + parameter [15:0] RST_PLL_CFG0 = 16'b0111011000010100; + parameter [15:0] SAP_CFG0 = 16'b0000000000000000; + parameter [15:0] SDM_CFG0 = 16'b0001100001000000; + parameter [15:0] SDM_CFG1 = 16'b0000000000000000; + parameter [15:0] SDM_CFG2 = 16'b0000000000000000; + parameter [15:0] SDM_SEED_CFG0 = 16'b0000000000000000; + parameter [15:0] SDM_SEED_CFG1 = 16'b0000000000000000; + parameter SIM_DEVICE = "ULTRASCALE_PLUS_ES1"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter integer TX_AMPLITUDE_SWING = 250; + output [27:0] CH0_AXISTDATA; + output CH0_AXISTLAST; + output CH0_AXISTVALID; + output [31:0] CH0_DMONITOROUT; + output CH0_DMONITOROUTCLK; + output CH0_GTMTXN; + output CH0_GTMTXP; + output [15:0] CH0_PCSRSVDOUT; + output [15:0] CH0_PMARSVDOUT; + output CH0_RESETEXCEPTION; + output [2:0] CH0_RXBUFSTATUS; + output [255:0] CH0_RXDATA; + output [3:0] CH0_RXDATAFLAGS; + output CH0_RXDATAISAM; + output CH0_RXDATASTART; + output CH0_RXOUTCLK; + output CH0_RXPMARESETDONE; + output CH0_RXPRBSERR; + output CH0_RXPRBSLOCKED; + output CH0_RXPRGDIVRESETDONE; + output CH0_RXPROGDIVCLK; + output CH0_RXRESETDONE; + output [1:0] CH0_TXBUFSTATUS; + output CH0_TXOUTCLK; + output CH0_TXPMARESETDONE; + output CH0_TXPRGDIVRESETDONE; + output CH0_TXPROGDIVCLK; + output CH0_TXRESETDONE; + output [27:0] CH1_AXISTDATA; + output CH1_AXISTLAST; + output CH1_AXISTVALID; + output [31:0] CH1_DMONITOROUT; + output CH1_DMONITOROUTCLK; + output CH1_GTMTXN; + output CH1_GTMTXP; + output [15:0] CH1_PCSRSVDOUT; + output [15:0] CH1_PMARSVDOUT; + output CH1_RESETEXCEPTION; + output [2:0] CH1_RXBUFSTATUS; + output [255:0] CH1_RXDATA; + output [3:0] CH1_RXDATAFLAGS; + output CH1_RXDATAISAM; + output CH1_RXDATASTART; + output CH1_RXOUTCLK; + output CH1_RXPMARESETDONE; + output CH1_RXPRBSERR; + output CH1_RXPRBSLOCKED; + output CH1_RXPRGDIVRESETDONE; + output CH1_RXPROGDIVCLK; + output CH1_RXRESETDONE; + output [1:0] CH1_TXBUFSTATUS; + output CH1_TXOUTCLK; + output CH1_TXPMARESETDONE; + output CH1_TXPRGDIVRESETDONE; + output CH1_TXPROGDIVCLK; + output CH1_TXRESETDONE; + output CLKTESTSIG2PAD; + output DMONITOROUTPLLCLK; + output [15:0] DRPDO; + output DRPRDY; + output FECRX0ALIGNED; + output FECRX0CORRCWINC; + output FECRX0CWINC; + output FECRX0UNCORRCWINC; + output FECRX1ALIGNED; + output FECRX1CORRCWINC; + output FECRX1CWINC; + output FECRX1UNCORRCWINC; + output [7:0] FECRXLN0BITERR0TO1INC; + output [7:0] FECRXLN0BITERR1TO0INC; + output [14:0] FECRXLN0DLY; + output [3:0] FECRXLN0ERRCNTINC; + output [1:0] FECRXLN0MAPPING; + output [7:0] FECRXLN1BITERR0TO1INC; + output [7:0] FECRXLN1BITERR1TO0INC; + output [14:0] FECRXLN1DLY; + output [3:0] FECRXLN1ERRCNTINC; + output [1:0] FECRXLN1MAPPING; + output [7:0] FECRXLN2BITERR0TO1INC; + output [7:0] FECRXLN2BITERR1TO0INC; + output [14:0] FECRXLN2DLY; + output [3:0] FECRXLN2ERRCNTINC; + output [1:0] FECRXLN2MAPPING; + output [7:0] FECRXLN3BITERR0TO1INC; + output [7:0] FECRXLN3BITERR1TO0INC; + output [14:0] FECRXLN3DLY; + output [3:0] FECRXLN3ERRCNTINC; + output [1:0] FECRXLN3MAPPING; + output FECTRXLN0LOCK; + output FECTRXLN1LOCK; + output FECTRXLN2LOCK; + output FECTRXLN3LOCK; + output GTPOWERGOOD; + output PLLFBCLKLOST; + output PLLLOCK; + output PLLREFCLKLOST; + output PLLREFCLKMONITOR; + output PLLRESETDONE; + output [15:0] PLLRSVDOUT; + output RCALCMP; + output [4:0] RCALOUT; + output RXRECCLK0; + output RXRECCLK1; + input BGBYPASSB; + input BGMONITORENB; + input BGPDB; + input [4:0] BGRCALOVRD; + input BGRCALOVRDENB; + input CH0_AXISEN; + input CH0_AXISRST; + input CH0_AXISTRDY; + input CH0_CFGRESET; + input CH0_DMONFIFORESET; + input CH0_DMONITORCLK; + input CH0_GTMRXN; + input CH0_GTMRXP; + input CH0_GTRXRESET; + input CH0_GTTXRESET; + input [2:0] CH0_LOOPBACK; + input [15:0] CH0_PCSRSVDIN; + input [15:0] CH0_PMARSVDIN; + input CH0_RESETOVRD; + input CH0_RXADAPTRESET; + input CH0_RXADCCALRESET; + input CH0_RXADCCLKGENRESET; + input CH0_RXBUFRESET; + input CH0_RXCDRFREQOS; + input CH0_RXCDRFRRESET; + input CH0_RXCDRHOLD; + input CH0_RXCDRINCPCTRL; + input CH0_RXCDROVRDEN; + input CH0_RXCDRPHRESET; + input CH0_RXDFERESET; + input CH0_RXDSPRESET; + input CH0_RXEQTRAINING; + input CH0_RXEYESCANRESET; + input CH0_RXFECRESET; + input [2:0] CH0_RXOUTCLKSEL; + input CH0_RXPCSRESET; + input [3:0] CH0_RXPCSRESETMASK; + input CH0_RXPMARESET; + input [7:0] CH0_RXPMARESETMASK; + input CH0_RXPOLARITY; + input CH0_RXPRBSCNTSTOP; + input CH0_RXPRBSCSCNTRST; + input [3:0] CH0_RXPRBSPTN; + input CH0_RXPROGDIVRESET; + input CH0_RXQPRBSEN; + input [1:0] CH0_RXRESETMODE; + input CH0_RXSPCSEQADV; + input CH0_RXUSRCLK; + input CH0_RXUSRCLK2; + input CH0_RXUSRRDY; + input CH0_RXUSRSTART; + input CH0_RXUSRSTOP; + input CH0_TXCKALRESET; + input [5:0] CH0_TXCTLFIRDAT; + input [255:0] CH0_TXDATA; + input CH0_TXDATASTART; + input [4:0] CH0_TXDRVAMP; + input [5:0] CH0_TXEMPMAIN; + input [4:0] CH0_TXEMPPOST; + input [4:0] CH0_TXEMPPRE; + input [3:0] CH0_TXEMPPRE2; + input CH0_TXFECRESET; + input CH0_TXINHIBIT; + input CH0_TXMUXDCDEXHOLD; + input CH0_TXMUXDCDORWREN; + input [2:0] CH0_TXOUTCLKSEL; + input CH0_TXPCSRESET; + input [1:0] CH0_TXPCSRESETMASK; + input CH0_TXPMARESET; + input [1:0] CH0_TXPMARESETMASK; + input CH0_TXPOLARITY; + input CH0_TXPRBSINERR; + input [3:0] CH0_TXPRBSPTN; + input CH0_TXPROGDIVRESET; + input CH0_TXQPRBSEN; + input [1:0] CH0_TXRESETMODE; + input CH0_TXSPCSEQADV; + input CH0_TXUSRCLK; + input CH0_TXUSRCLK2; + input CH0_TXUSRRDY; + input CH1_AXISEN; + input CH1_AXISRST; + input CH1_AXISTRDY; + input CH1_CFGRESET; + input CH1_DMONFIFORESET; + input CH1_DMONITORCLK; + input CH1_GTMRXN; + input CH1_GTMRXP; + input CH1_GTRXRESET; + input CH1_GTTXRESET; + input [2:0] CH1_LOOPBACK; + input [15:0] CH1_PCSRSVDIN; + input [15:0] CH1_PMARSVDIN; + input CH1_RESETOVRD; + input CH1_RXADAPTRESET; + input CH1_RXADCCALRESET; + input CH1_RXADCCLKGENRESET; + input CH1_RXBUFRESET; + input CH1_RXCDRFREQOS; + input CH1_RXCDRFRRESET; + input CH1_RXCDRHOLD; + input CH1_RXCDRINCPCTRL; + input CH1_RXCDROVRDEN; + input CH1_RXCDRPHRESET; + input CH1_RXDFERESET; + input CH1_RXDSPRESET; + input CH1_RXEQTRAINING; + input CH1_RXEYESCANRESET; + input CH1_RXFECRESET; + input [2:0] CH1_RXOUTCLKSEL; + input CH1_RXPCSRESET; + input [3:0] CH1_RXPCSRESETMASK; + input CH1_RXPMARESET; + input [7:0] CH1_RXPMARESETMASK; + input CH1_RXPOLARITY; + input CH1_RXPRBSCNTSTOP; + input CH1_RXPRBSCSCNTRST; + input [3:0] CH1_RXPRBSPTN; + input CH1_RXPROGDIVRESET; + input CH1_RXQPRBSEN; + input [1:0] CH1_RXRESETMODE; + input CH1_RXSPCSEQADV; + input CH1_RXUSRCLK; + input CH1_RXUSRCLK2; + input CH1_RXUSRRDY; + input CH1_RXUSRSTART; + input CH1_RXUSRSTOP; + input CH1_TXCKALRESET; + input [5:0] CH1_TXCTLFIRDAT; + input [255:0] CH1_TXDATA; + input CH1_TXDATASTART; + input [4:0] CH1_TXDRVAMP; + input [5:0] CH1_TXEMPMAIN; + input [4:0] CH1_TXEMPPOST; + input [4:0] CH1_TXEMPPRE; + input [3:0] CH1_TXEMPPRE2; + input CH1_TXFECRESET; + input CH1_TXINHIBIT; + input CH1_TXMUXDCDEXHOLD; + input CH1_TXMUXDCDORWREN; + input [2:0] CH1_TXOUTCLKSEL; + input CH1_TXPCSRESET; + input [1:0] CH1_TXPCSRESETMASK; + input CH1_TXPMARESET; + input [1:0] CH1_TXPMARESETMASK; + input CH1_TXPOLARITY; + input CH1_TXPRBSINERR; + input [3:0] CH1_TXPRBSPTN; + input CH1_TXPROGDIVRESET; + input CH1_TXQPRBSEN; + input [1:0] CH1_TXRESETMODE; + input CH1_TXSPCSEQADV; + input CH1_TXUSRCLK; + input CH1_TXUSRCLK2; + input CH1_TXUSRRDY; + input [10:0] DRPADDR; + input DRPCLK; + input [15:0] DRPDI; + input DRPEN; + input DRPRST; + input DRPWE; + input FECCTRLRX0BITSLIPFS; + input FECCTRLRX1BITSLIPFS; + input GTGREFCLK2PLL; + input GTNORTHREFCLK; + input GTREFCLK; + input GTSOUTHREFCLK; + input [7:0] PLLFBDIV; + input PLLMONCLK; + input PLLPD; + input [2:0] PLLREFCLKSEL; + input PLLRESET; + input PLLRESETBYPASSMODE; + input [1:0] PLLRESETMASK; + input [15:0] PLLRSVDIN; + input RCALENB; + input [25:0] SDMDATA; + input SDMTOGGLE; +endmodule + +module IBUFDS_GTM (...); + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; + parameter integer REFCLK_HROW_CK_SEL = 0; + parameter integer REFCLK_ICNTL_RX = 0; + output O; + output ODIV2; + input CEB; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; +endmodule + +module OBUFDS_GTM (...); + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; + parameter integer REFCLK_ICNTL_TX = 0; + (* iopad_external_pin *) + output O; + (* iopad_external_pin *) + output OB; + input CEB; + input I; +endmodule + +module OBUFDS_GTM_ADV (...); + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; + parameter integer REFCLK_ICNTL_TX = 0; + parameter [1:0] RXRECCLK_SEL = 2'b00; + (* iopad_external_pin *) + output O; + (* iopad_external_pin *) + output OB; + input CEB; + input [3:0] I; +endmodule + +module HSDAC (...); + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter integer XPA_CFG0 = 0; + parameter integer XPA_CFG1 = 0; + parameter integer XPA_NUM_DACS = 0; + parameter integer XPA_NUM_DUCS = 0; + parameter XPA_PLL_USED = "No"; + parameter integer XPA_SAMPLE_RATE_MSPS = 0; + output CLK_DAC; + output [15:0] DOUT; + output DRDY; + output PLL_DMON_OUT; + output PLL_REFCLK_OUT; + output [15:0] STATUS_COMMON; + output [15:0] STATUS_DAC0; + output [15:0] STATUS_DAC1; + output [15:0] STATUS_DAC2; + output [15:0] STATUS_DAC3; + output SYSREF_OUT_NORTH; + output SYSREF_OUT_SOUTH; + output VOUT0_N; + output VOUT0_P; + output VOUT1_N; + output VOUT1_P; + output VOUT2_N; + output VOUT2_P; + output VOUT3_N; + output VOUT3_P; + input CLK_FIFO_LM; + input [15:0] CONTROL_COMMON; + input [15:0] CONTROL_DAC0; + input [15:0] CONTROL_DAC1; + input [15:0] CONTROL_DAC2; + input [15:0] CONTROL_DAC3; + input DAC_CLK_N; + input DAC_CLK_P; + input [11:0] DADDR; + input [255:0] DATA_DAC0; + input [255:0] DATA_DAC1; + input [255:0] DATA_DAC2; + input [255:0] DATA_DAC3; + input DCLK; + input DEN; + input [15:0] DI; + input DWE; + input FABRIC_CLK; + input PLL_MONCLK; + input PLL_REFCLK_IN; + input SYSREF_IN_NORTH; + input SYSREF_IN_SOUTH; + input SYSREF_N; + input SYSREF_P; +endmodule + +module HSADC (...); + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter integer XPA_CFG0 = 0; + parameter integer XPA_CFG1 = 0; + parameter XPA_NUM_ADCS = "0"; + parameter integer XPA_NUM_DDCS = 0; + parameter XPA_PLL_USED = "No"; + parameter integer XPA_SAMPLE_RATE_MSPS = 0; + output CLK_ADC; + output [127:0] DATA_ADC0; + output [127:0] DATA_ADC1; + output [127:0] DATA_ADC2; + output [127:0] DATA_ADC3; + output [15:0] DOUT; + output DRDY; + output PLL_DMON_OUT; + output PLL_REFCLK_OUT; + output [15:0] STATUS_ADC0; + output [15:0] STATUS_ADC1; + output [15:0] STATUS_ADC2; + output [15:0] STATUS_ADC3; + output [15:0] STATUS_COMMON; + output SYSREF_OUT_NORTH; + output SYSREF_OUT_SOUTH; + input ADC_CLK_N; + input ADC_CLK_P; + input CLK_FIFO_LM; + input [15:0] CONTROL_ADC0; + input [15:0] CONTROL_ADC1; + input [15:0] CONTROL_ADC2; + input [15:0] CONTROL_ADC3; + input [15:0] CONTROL_COMMON; + input [11:0] DADDR; + input DCLK; + input DEN; + input [15:0] DI; + input DWE; + input FABRIC_CLK; + input PLL_MONCLK; + input PLL_REFCLK_IN; + input SYSREF_IN_NORTH; + input SYSREF_IN_SOUTH; + input SYSREF_N; + input SYSREF_P; + input VIN0_N; + input VIN0_P; + input VIN1_N; + input VIN1_P; + input VIN2_N; + input VIN2_P; + input VIN3_N; + input VIN3_P; + input VIN_I01_N; + input VIN_I01_P; + input VIN_I23_N; + input VIN_I23_P; +endmodule + +module RFDAC (...); + parameter integer LD_DEVICE = 0; + parameter integer OPT_CLK_DIST = 0; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter integer XPA_ACTIVE_DUTYCYCLE = 100; + parameter integer XPA_CFG0 = 0; + parameter integer XPA_CFG1 = 0; + parameter integer XPA_CFG2 = 0; + parameter integer XPA_NUM_DACS = 0; + parameter integer XPA_NUM_DUCS = 0; + parameter XPA_PLL_USED = "EXTERNAL"; + parameter integer XPA_SAMPLE_RATE_MSPS = 0; + output CLK_DAC; + output CLK_DIST_OUT_NORTH; + output CLK_DIST_OUT_SOUTH; + output [15:0] DOUT; + output DRDY; + output PLL_DMON_OUT; + output PLL_REFCLK_OUT; + output [23:0] STATUS_COMMON; + output [23:0] STATUS_DAC0; + output [23:0] STATUS_DAC1; + output [23:0] STATUS_DAC2; + output [23:0] STATUS_DAC3; + output SYSREF_OUT_NORTH; + output SYSREF_OUT_SOUTH; + output T1_ALLOWED_SOUTH; + output VOUT0_N; + output VOUT0_P; + output VOUT1_N; + output VOUT1_P; + output VOUT2_N; + output VOUT2_P; + output VOUT3_N; + output VOUT3_P; + input CLK_DIST_IN_NORTH; + input CLK_DIST_IN_SOUTH; + input CLK_FIFO_LM; + input [15:0] CONTROL_COMMON; + input [15:0] CONTROL_DAC0; + input [15:0] CONTROL_DAC1; + input [15:0] CONTROL_DAC2; + input [15:0] CONTROL_DAC3; + input DAC_CLK_N; + input DAC_CLK_P; + input [11:0] DADDR; + input [255:0] DATA_DAC0; + input [255:0] DATA_DAC1; + input [255:0] DATA_DAC2; + input [255:0] DATA_DAC3; + input DCLK; + input DEN; + input [15:0] DI; + input DWE; + input FABRIC_CLK; + input PLL_MONCLK; + input PLL_REFCLK_IN; + input SYSREF_IN_NORTH; + input SYSREF_IN_SOUTH; + input SYSREF_N; + input SYSREF_P; + input T1_ALLOWED_NORTH; +endmodule + +module RFADC (...); + parameter integer LD_DEVICE = 0; + parameter integer OPT_ANALOG = 0; + parameter integer OPT_CLK_DIST = 0; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter integer XPA_ACTIVE_DUTYCYCLE = 100; + parameter integer XPA_CFG0 = 0; + parameter integer XPA_CFG1 = 0; + parameter integer XPA_CFG2 = 0; + parameter XPA_NUM_ADCS = "0"; + parameter integer XPA_NUM_DDCS = 0; + parameter XPA_PLL_USED = "EXTERNAL"; + parameter integer XPA_SAMPLE_RATE_MSPS = 0; + output CLK_ADC; + output CLK_DIST_OUT_NORTH; + output CLK_DIST_OUT_SOUTH; + output [191:0] DATA_ADC0; + output [191:0] DATA_ADC1; + output [191:0] DATA_ADC2; + output [191:0] DATA_ADC3; + output [15:0] DOUT; + output DRDY; + output PLL_DMON_OUT; + output PLL_REFCLK_OUT; + output [23:0] STATUS_ADC0; + output [23:0] STATUS_ADC1; + output [23:0] STATUS_ADC2; + output [23:0] STATUS_ADC3; + output [23:0] STATUS_COMMON; + output SYSREF_OUT_NORTH; + output SYSREF_OUT_SOUTH; + output T1_ALLOWED_SOUTH; + input ADC_CLK_N; + input ADC_CLK_P; + input CLK_DIST_IN_NORTH; + input CLK_DIST_IN_SOUTH; + input CLK_FIFO_LM; + input [15:0] CONTROL_ADC0; + input [15:0] CONTROL_ADC1; + input [15:0] CONTROL_ADC2; + input [15:0] CONTROL_ADC3; + input [15:0] CONTROL_COMMON; + input [11:0] DADDR; + input DCLK; + input DEN; + input [15:0] DI; + input DWE; + input FABRIC_CLK; + input PLL_MONCLK; + input PLL_REFCLK_IN; + input SYSREF_IN_NORTH; + input SYSREF_IN_SOUTH; + input SYSREF_N; + input SYSREF_P; + input T1_ALLOWED_NORTH; + input VIN0_N; + input VIN0_P; + input VIN1_N; + input VIN1_P; + input VIN2_N; + input VIN2_P; + input VIN3_N; + input VIN3_P; + input VIN_I01_N; + input VIN_I01_P; + input VIN_I23_N; + input VIN_I23_P; +endmodule + +module PCIE_A1 (...); + parameter [31:0] BAR0 = 32'h00000000; + parameter [31:0] BAR1 = 32'h00000000; + parameter [31:0] BAR2 = 32'h00000000; + parameter [31:0] BAR3 = 32'h00000000; + parameter [31:0] BAR4 = 32'h00000000; + parameter [31:0] BAR5 = 32'h00000000; + parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000; + parameter [23:0] CLASS_CODE = 24'h000000; + parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 7; + parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 7; + parameter DEV_CAP_EXT_TAG_SUPPORTED = "FALSE"; + parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2; + parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0; + parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE"; + parameter DISABLE_BAR_FILTERING = "FALSE"; + parameter DISABLE_ID_CHECK = "FALSE"; + parameter DISABLE_SCRAMBLING = "FALSE"; + parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE"; + parameter [21:0] EXPANSION_ROM = 22'h000000; + parameter FAST_TRAIN = "FALSE"; + parameter integer GTP_SEL = 0; + parameter integer LINK_CAP_ASPM_SUPPORT = 1; + parameter integer LINK_CAP_L0S_EXIT_LATENCY = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY = 7; + parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "FALSE"; + parameter [14:0] LL_ACK_TIMEOUT = 15'h0204; + parameter LL_ACK_TIMEOUT_EN = "FALSE"; + parameter [14:0] LL_REPLAY_TIMEOUT = 15'h060D; + parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; + parameter integer MSI_CAP_MULTIMSGCAP = 0; + parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0; + parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h1; + parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0; + parameter [4:0] PCIE_CAP_INT_MSG_NUM = 5'b00000; + parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE"; + parameter [11:0] PCIE_GENERIC = 12'h000; + parameter PLM_AUTO_CONFIG = "FALSE"; + parameter integer PM_CAP_AUXCURRENT = 0; + parameter PM_CAP_D1SUPPORT = "TRUE"; + parameter PM_CAP_D2SUPPORT = "TRUE"; + parameter PM_CAP_DSI = "FALSE"; + parameter [4:0] PM_CAP_PMESUPPORT = 5'b01111; + parameter PM_CAP_PME_CLOCK = "FALSE"; + parameter integer PM_CAP_VERSION = 3; + parameter [7:0] PM_DATA0 = 8'h1E; + parameter [7:0] PM_DATA1 = 8'h1E; + parameter [7:0] PM_DATA2 = 8'h1E; + parameter [7:0] PM_DATA3 = 8'h1E; + parameter [7:0] PM_DATA4 = 8'h1E; + parameter [7:0] PM_DATA5 = 8'h1E; + parameter [7:0] PM_DATA6 = 8'h1E; + parameter [7:0] PM_DATA7 = 8'h1E; + parameter [1:0] PM_DATA_SCALE0 = 2'b01; + parameter [1:0] PM_DATA_SCALE1 = 2'b01; + parameter [1:0] PM_DATA_SCALE2 = 2'b01; + parameter [1:0] PM_DATA_SCALE3 = 2'b01; + parameter [1:0] PM_DATA_SCALE4 = 2'b01; + parameter [1:0] PM_DATA_SCALE5 = 2'b01; + parameter [1:0] PM_DATA_SCALE6 = 2'b01; + parameter [1:0] PM_DATA_SCALE7 = 2'b01; + parameter SIM_VERSION = "1.0"; + parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE"; + parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE"; + parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE"; + parameter integer TL_RX_RAM_RADDR_LATENCY = 1; + parameter integer TL_RX_RAM_RDATA_LATENCY = 2; + parameter integer TL_RX_RAM_WRITE_LATENCY = 0; + parameter TL_TFC_DISABLE = "FALSE"; + parameter TL_TX_CHECKS_DISABLE = "FALSE"; + parameter integer TL_TX_RAM_RADDR_LATENCY = 0; + parameter integer TL_TX_RAM_RDATA_LATENCY = 2; + parameter USR_CFG = "FALSE"; + parameter USR_EXT_CFG = "FALSE"; + parameter VC0_CPL_INFINITE = "TRUE"; + parameter [11:0] VC0_RX_RAM_LIMIT = 12'h01E; + parameter integer VC0_TOTAL_CREDITS_CD = 104; + parameter integer VC0_TOTAL_CREDITS_CH = 36; + parameter integer VC0_TOTAL_CREDITS_NPH = 8; + parameter integer VC0_TOTAL_CREDITS_PD = 288; + parameter integer VC0_TOTAL_CREDITS_PH = 32; + parameter integer VC0_TX_LASTPACKET = 31; + output CFGCOMMANDBUSMASTERENABLE; + output CFGCOMMANDINTERRUPTDISABLE; + output CFGCOMMANDIOENABLE; + output CFGCOMMANDMEMENABLE; + output CFGCOMMANDSERREN; + output CFGDEVCONTROLAUXPOWEREN; + output CFGDEVCONTROLCORRERRREPORTINGEN; + output CFGDEVCONTROLENABLERO; + output CFGDEVCONTROLEXTTAGEN; + output CFGDEVCONTROLFATALERRREPORTINGEN; + output CFGDEVCONTROLNONFATALREPORTINGEN; + output CFGDEVCONTROLNOSNOOPEN; + output CFGDEVCONTROLPHANTOMEN; + output CFGDEVCONTROLURERRREPORTINGEN; + output CFGDEVSTATUSCORRERRDETECTED; + output CFGDEVSTATUSFATALERRDETECTED; + output CFGDEVSTATUSNONFATALERRDETECTED; + output CFGDEVSTATUSURDETECTED; + output CFGERRCPLRDYN; + output CFGINTERRUPTMSIENABLE; + output CFGINTERRUPTRDYN; + output CFGLINKCONTOLRCB; + output CFGLINKCONTROLCOMMONCLOCK; + output CFGLINKCONTROLEXTENDEDSYNC; + output CFGRDWRDONEN; + output CFGTOTURNOFFN; + output DBGBADDLLPSTATUS; + output DBGBADTLPLCRC; + output DBGBADTLPSEQNUM; + output DBGBADTLPSTATUS; + output DBGDLPROTOCOLSTATUS; + output DBGFCPROTOCOLERRSTATUS; + output DBGMLFRMDLENGTH; + output DBGMLFRMDMPS; + output DBGMLFRMDTCVC; + output DBGMLFRMDTLPSTATUS; + output DBGMLFRMDUNRECTYPE; + output DBGPOISTLPSTATUS; + output DBGRCVROVERFLOWSTATUS; + output DBGREGDETECTEDCORRECTABLE; + output DBGREGDETECTEDFATAL; + output DBGREGDETECTEDNONFATAL; + output DBGREGDETECTEDUNSUPPORTED; + output DBGRPLYROLLOVERSTATUS; + output DBGRPLYTIMEOUTSTATUS; + output DBGURNOBARHIT; + output DBGURPOISCFGWR; + output DBGURSTATUS; + output DBGURUNSUPMSG; + output MIMRXREN; + output MIMRXWEN; + output MIMTXREN; + output MIMTXWEN; + output PIPEGTTXELECIDLEA; + output PIPEGTTXELECIDLEB; + output PIPERXPOLARITYA; + output PIPERXPOLARITYB; + output PIPERXRESETA; + output PIPERXRESETB; + output PIPETXRCVRDETA; + output PIPETXRCVRDETB; + output RECEIVEDHOTRESET; + output TRNLNKUPN; + output TRNREOFN; + output TRNRERRFWDN; + output TRNRSOFN; + output TRNRSRCDSCN; + output TRNRSRCRDYN; + output TRNTCFGREQN; + output TRNTDSTRDYN; + output TRNTERRDROPN; + output USERRSTN; + output [11:0] MIMRXRADDR; + output [11:0] MIMRXWADDR; + output [11:0] MIMTXRADDR; + output [11:0] MIMTXWADDR; + output [11:0] TRNFCCPLD; + output [11:0] TRNFCNPD; + output [11:0] TRNFCPD; + output [15:0] PIPETXDATAA; + output [15:0] PIPETXDATAB; + output [1:0] CFGLINKCONTROLASPMCONTROL; + output [1:0] PIPEGTPOWERDOWNA; + output [1:0] PIPEGTPOWERDOWNB; + output [1:0] PIPETXCHARDISPMODEA; + output [1:0] PIPETXCHARDISPMODEB; + output [1:0] PIPETXCHARDISPVALA; + output [1:0] PIPETXCHARDISPVALB; + output [1:0] PIPETXCHARISKA; + output [1:0] PIPETXCHARISKB; + output [2:0] CFGDEVCONTROLMAXPAYLOAD; + output [2:0] CFGDEVCONTROLMAXREADREQ; + output [2:0] CFGFUNCTIONNUMBER; + output [2:0] CFGINTERRUPTMMENABLE; + output [2:0] CFGPCIELINKSTATEN; + output [31:0] CFGDO; + output [31:0] TRNRD; + output [34:0] MIMRXWDATA; + output [35:0] MIMTXWDATA; + output [4:0] CFGDEVICENUMBER; + output [4:0] CFGLTSSMSTATE; + output [5:0] TRNTBUFAV; + output [6:0] TRNRBARHITN; + output [7:0] CFGBUSNUMBER; + output [7:0] CFGINTERRUPTDO; + output [7:0] TRNFCCPLH; + output [7:0] TRNFCNPH; + output [7:0] TRNFCPH; + input CFGERRCORN; + input CFGERRCPLABORTN; + input CFGERRCPLTIMEOUTN; + input CFGERRECRCN; + input CFGERRLOCKEDN; + input CFGERRPOSTEDN; + input CFGERRURN; + input CFGINTERRUPTASSERTN; + input CFGINTERRUPTN; + input CFGPMWAKEN; + input CFGRDENN; + input CFGTRNPENDINGN; + input CFGTURNOFFOKN; + input CLOCKLOCKED; + input MGTCLK; + input PIPEGTRESETDONEA; + input PIPEGTRESETDONEB; + input PIPEPHYSTATUSA; + input PIPEPHYSTATUSB; + input PIPERXENTERELECIDLEA; + input PIPERXENTERELECIDLEB; + input SYSRESETN; + input TRNRDSTRDYN; + input TRNRNPOKN; + input TRNTCFGGNTN; + input TRNTEOFN; + input TRNTERRFWDN; + input TRNTSOFN; + input TRNTSRCDSCN; + input TRNTSRCRDYN; + input TRNTSTRN; + input USERCLK; + input [15:0] CFGDEVID; + input [15:0] CFGSUBSYSID; + input [15:0] CFGSUBSYSVENID; + input [15:0] CFGVENID; + input [15:0] PIPERXDATAA; + input [15:0] PIPERXDATAB; + input [1:0] PIPERXCHARISKA; + input [1:0] PIPERXCHARISKB; + input [2:0] PIPERXSTATUSA; + input [2:0] PIPERXSTATUSB; + input [2:0] TRNFCSEL; + input [31:0] TRNTD; + input [34:0] MIMRXRDATA; + input [35:0] MIMTXRDATA; + input [47:0] CFGERRTLPCPLHEADER; + input [63:0] CFGDSN; + input [7:0] CFGINTERRUPTDI; + input [7:0] CFGREVID; + input [9:0] CFGDWADDR; +endmodule + +module PCIE_EP (...); + parameter BAR0EXIST = "TRUE"; + parameter BAR0PREFETCHABLE = "TRUE"; + parameter BAR1EXIST = "FALSE"; + parameter BAR1PREFETCHABLE = "FALSE"; + parameter BAR2EXIST = "FALSE"; + parameter BAR2PREFETCHABLE = "FALSE"; + parameter BAR3EXIST = "FALSE"; + parameter BAR3PREFETCHABLE = "FALSE"; + parameter BAR4EXIST = "FALSE"; + parameter BAR4PREFETCHABLE = "FALSE"; + parameter BAR5EXIST = "FALSE"; + parameter BAR5PREFETCHABLE = "FALSE"; + parameter CLKDIVIDED = "FALSE"; + parameter INFINITECOMPLETIONS = "TRUE"; + parameter LINKSTATUSSLOTCLOCKCONFIG = "FALSE"; + parameter PBCAPABILITYSYSTEMALLOCATED = "FALSE"; + parameter PMCAPABILITYD1SUPPORT = "FALSE"; + parameter PMCAPABILITYD2SUPPORT = "FALSE"; + parameter PMCAPABILITYDSI = "TRUE"; + parameter RESETMODE = "FALSE"; + parameter [10:0] VC0TOTALCREDITSCD = 11'h0; + parameter [10:0] VC0TOTALCREDITSPD = 11'h34; + parameter [10:0] VC1TOTALCREDITSCD = 11'h0; + parameter [10:0] VC1TOTALCREDITSPD = 11'h0; + parameter [11:0] AERBASEPTR = 12'h110; + parameter [11:0] AERCAPABILITYNEXTPTR = 12'h138; + parameter [11:0] DSNBASEPTR = 12'h148; + parameter [11:0] DSNCAPABILITYNEXTPTR = 12'h154; + parameter [11:0] MSIBASEPTR = 12'h48; + parameter [11:0] PBBASEPTR = 12'h138; + parameter [11:0] PBCAPABILITYNEXTPTR = 12'h148; + parameter [11:0] PMBASEPTR = 12'h40; + parameter [11:0] RETRYRAMSIZE = 12'h9; + parameter [11:0] VCBASEPTR = 12'h154; + parameter [11:0] VCCAPABILITYNEXTPTR = 12'h0; + parameter [12:0] VC0RXFIFOBASEC = 13'h98; + parameter [12:0] VC0RXFIFOBASENP = 13'h80; + parameter [12:0] VC0RXFIFOBASEP = 13'h0; + parameter [12:0] VC0RXFIFOLIMITC = 13'h117; + parameter [12:0] VC0RXFIFOLIMITNP = 13'h97; + parameter [12:0] VC0RXFIFOLIMITP = 13'h7f; + parameter [12:0] VC0TXFIFOBASEC = 13'h98; + parameter [12:0] VC0TXFIFOBASENP = 13'h80; + parameter [12:0] VC0TXFIFOBASEP = 13'h0; + parameter [12:0] VC0TXFIFOLIMITC = 13'h117; + parameter [12:0] VC0TXFIFOLIMITNP = 13'h97; + parameter [12:0] VC0TXFIFOLIMITP = 13'h7f; + parameter [12:0] VC1RXFIFOBASEC = 13'h118; + parameter [12:0] VC1RXFIFOBASENP = 13'h118; + parameter [12:0] VC1RXFIFOBASEP = 13'h118; + parameter [12:0] VC1RXFIFOLIMITC = 13'h118; + parameter [12:0] VC1RXFIFOLIMITNP = 13'h118; + parameter [12:0] VC1RXFIFOLIMITP = 13'h118; + parameter [12:0] VC1TXFIFOBASEC = 13'h118; + parameter [12:0] VC1TXFIFOBASENP = 13'h118; + parameter [12:0] VC1TXFIFOBASEP = 13'h118; + parameter [12:0] VC1TXFIFOLIMITC = 13'h118; + parameter [12:0] VC1TXFIFOLIMITNP = 13'h118; + parameter [12:0] VC1TXFIFOLIMITP = 13'h118; + parameter [15:0] DEVICEID = 16'h5050; + parameter [15:0] SUBSYSTEMID = 16'h5050; + parameter [15:0] SUBSYSTEMVENDORID = 16'h10EE; + parameter [15:0] VENDORID = 16'h10EE; + parameter [1:0] LINKCAPABILITYASPMSUPPORT = 2'h1; + parameter [1:0] PBCAPABILITYDW0DATASCALE = 2'h0; + parameter [1:0] PBCAPABILITYDW0PMSTATE = 2'h0; + parameter [1:0] PBCAPABILITYDW1DATASCALE = 2'h0; + parameter [1:0] PBCAPABILITYDW1PMSTATE = 2'h0; + parameter [1:0] PBCAPABILITYDW2DATASCALE = 2'h0; + parameter [1:0] PBCAPABILITYDW2PMSTATE = 2'h0; + parameter [1:0] PBCAPABILITYDW3DATASCALE = 2'h0; + parameter [1:0] PBCAPABILITYDW3PMSTATE = 2'h0; + parameter [23:0] CLASSCODE = 24'h058000; + parameter [2:0] DEVICECAPABILITYENDPOINTL0SLATENCY = 3'h0; + parameter [2:0] DEVICECAPABILITYENDPOINTL1LATENCY = 3'h0; + parameter [2:0] MSICAPABILITYMULTIMSGCAP = 3'h0; + parameter [2:0] PBCAPABILITYDW0PMSUBSTATE = 3'h0; + parameter [2:0] PBCAPABILITYDW0POWERRAIL = 3'h0; + parameter [2:0] PBCAPABILITYDW0TYPE = 3'h0; + parameter [2:0] PBCAPABILITYDW1PMSUBSTATE = 3'h0; + parameter [2:0] PBCAPABILITYDW1POWERRAIL = 3'h0; + parameter [2:0] PBCAPABILITYDW1TYPE = 3'h0; + parameter [2:0] PBCAPABILITYDW2PMSUBSTATE = 3'h0; + parameter [2:0] PBCAPABILITYDW2POWERRAIL = 3'h0; + parameter [2:0] PBCAPABILITYDW2TYPE = 3'h0; + parameter [2:0] PBCAPABILITYDW3PMSUBSTATE = 3'h0; + parameter [2:0] PBCAPABILITYDW3POWERRAIL = 3'h0; + parameter [2:0] PBCAPABILITYDW3TYPE = 3'h0; + parameter [2:0] PMCAPABILITYAUXCURRENT = 3'h0; + parameter [2:0] PORTVCCAPABILITYEXTENDEDVCCOUNT = 3'h0; + parameter [31:0] CARDBUSCISPOINTER = 32'h0; + parameter [3:0] XPDEVICEPORTTYPE = 4'h0; + parameter [4:0] PMCAPABILITYPMESUPPORT = 5'h0; + parameter [5:0] BAR0MASKWIDTH = 6'h14; + parameter [5:0] BAR1MASKWIDTH = 6'h0; + parameter [5:0] BAR2MASKWIDTH = 6'h0; + parameter [5:0] BAR3MASKWIDTH = 6'h0; + parameter [5:0] BAR4MASKWIDTH = 6'h0; + parameter [5:0] BAR5MASKWIDTH = 6'h0; + parameter [5:0] LINKCAPABILITYMAXLINKWIDTH = 6'h01; + parameter [63:0] DEVICESERIALNUMBER = 64'hE000000001000A35; + parameter [6:0] VC0TOTALCREDITSCH = 7'h0; + parameter [6:0] VC0TOTALCREDITSNPH = 7'h08; + parameter [6:0] VC0TOTALCREDITSPH = 7'h08; + parameter [6:0] VC1TOTALCREDITSCH = 7'h0; + parameter [6:0] VC1TOTALCREDITSNPH = 7'h0; + parameter [6:0] VC1TOTALCREDITSPH = 7'h0; + parameter [7:0] ACTIVELANESIN = 8'h1; + parameter [7:0] CAPABILITIESPOINTER = 8'h40; + parameter [7:0] INTERRUPTPIN = 8'h0; + parameter [7:0] MSICAPABILITYNEXTPTR = 8'h60; + parameter [7:0] PBCAPABILITYDW0BASEPOWER = 8'h0; + parameter [7:0] PBCAPABILITYDW1BASEPOWER = 8'h0; + parameter [7:0] PBCAPABILITYDW2BASEPOWER = 8'h0; + parameter [7:0] PBCAPABILITYDW3BASEPOWER = 8'h0; + parameter [7:0] PCIECAPABILITYNEXTPTR = 8'h0; + parameter [7:0] PMCAPABILITYNEXTPTR = 8'h60; + parameter [7:0] PMDATA0 = 8'h0; + parameter [7:0] PMDATA1 = 8'h0; + parameter [7:0] PMDATA2 = 8'h0; + parameter [7:0] PMDATA3 = 8'h0; + parameter [7:0] PMDATA4 = 8'h0; + parameter [7:0] PMDATA5 = 8'h0; + parameter [7:0] PMDATA6 = 8'h0; + parameter [7:0] PMDATA7 = 8'h0; + parameter [7:0] PORTVCCAPABILITYVCARBCAP = 8'h0; + parameter [7:0] PORTVCCAPABILITYVCARBTABLEOFFSET = 8'h0; + parameter [7:0] REVISIONID = 8'h0; + parameter [7:0] XPBASEPTR = 8'h60; + parameter BAR0ADDRWIDTH = 0; + parameter BAR0IOMEMN = 0; + parameter BAR1ADDRWIDTH = 0; + parameter BAR1IOMEMN = 0; + parameter BAR2ADDRWIDTH = 0; + parameter BAR2IOMEMN = 0; + parameter BAR3ADDRWIDTH = 0; + parameter BAR3IOMEMN = 0; + parameter BAR4ADDRWIDTH = 0; + parameter BAR4IOMEMN = 0; + parameter BAR5IOMEMN = 0; + parameter L0SEXITLATENCY = 7; + parameter L0SEXITLATENCYCOMCLK = 7; + parameter L1EXITLATENCY = 7; + parameter L1EXITLATENCYCOMCLK = 7; + parameter LOWPRIORITYVCCOUNT = 0; + parameter PMDATASCALE0 = 0; + parameter PMDATASCALE1 = 0; + parameter PMDATASCALE2 = 0; + parameter PMDATASCALE3 = 0; + parameter PMDATASCALE4 = 0; + parameter PMDATASCALE5 = 0; + parameter PMDATASCALE6 = 0; + parameter PMDATASCALE7 = 0; + parameter RETRYRAMREADLATENCY = 3; + parameter RETRYRAMWRITELATENCY = 1; + parameter TLRAMREADLATENCY = 3; + parameter TLRAMWRITELATENCY = 1; + parameter TXTSNFTS = 255; + parameter TXTSNFTSCOMCLK = 255; + parameter XPMAXPAYLOAD = 0; + output BUSMASTERENABLE; + output CRMDOHOTRESETN; + output CRMPWRSOFTRESETN; + output DLLTXPMDLLPOUTSTANDING; + output INTERRUPTDISABLE; + output IOSPACEENABLE; + output L0CFGLOOPBACKACK; + output L0DLLRXACKOUTSTANDING; + output L0DLLTXNONFCOUTSTANDING; + output L0DLLTXOUTSTANDING; + output L0FIRSTCFGWRITEOCCURRED; + output L0MACENTEREDL0; + output L0MACLINKTRAINING; + output L0MACLINKUP; + output L0MACNEWSTATEACK; + output L0MACRXL0SSTATE; + output L0MSIENABLE0; + output L0PMEACK; + output L0PMEEN; + output L0PMEREQOUT; + output L0PWRL1STATE; + output L0PWRL23READYSTATE; + output L0PWRTURNOFFREQ; + output L0PWRTXL0SSTATE; + output L0RXDLLPM; + output L0STATSCFGOTHERRECEIVED; + output L0STATSCFGOTHERTRANSMITTED; + output L0STATSCFGRECEIVED; + output L0STATSCFGTRANSMITTED; + output L0STATSDLLPRECEIVED; + output L0STATSDLLPTRANSMITTED; + output L0STATSOSRECEIVED; + output L0STATSOSTRANSMITTED; + output L0STATSTLPRECEIVED; + output L0STATSTLPTRANSMITTED; + output L0UNLOCKRECEIVED; + output LLKRXEOFN; + output LLKRXEOPN; + output LLKRXSOFN; + output LLKRXSOPN; + output LLKRXSRCLASTREQN; + output LLKRXSRCRDYN; + output LLKTXCONFIGREADYN; + output LLKTXDSTRDYN; + output MEMSPACEENABLE; + output MIMDLLBREN; + output MIMDLLBWEN; + output MIMRXBREN; + output MIMRXBWEN; + output MIMTXBREN; + output MIMTXBWEN; + output PARITYERRORRESPONSE; + output PIPEDESKEWLANESL0; + output PIPEDESKEWLANESL1; + output PIPEDESKEWLANESL2; + output PIPEDESKEWLANESL3; + output PIPEDESKEWLANESL4; + output PIPEDESKEWLANESL5; + output PIPEDESKEWLANESL6; + output PIPEDESKEWLANESL7; + output PIPERESETL0; + output PIPERESETL1; + output PIPERESETL2; + output PIPERESETL3; + output PIPERESETL4; + output PIPERESETL5; + output PIPERESETL6; + output PIPERESETL7; + output PIPERXPOLARITYL0; + output PIPERXPOLARITYL1; + output PIPERXPOLARITYL2; + output PIPERXPOLARITYL3; + output PIPERXPOLARITYL4; + output PIPERXPOLARITYL5; + output PIPERXPOLARITYL6; + output PIPERXPOLARITYL7; + output PIPETXCOMPLIANCEL0; + output PIPETXCOMPLIANCEL1; + output PIPETXCOMPLIANCEL2; + output PIPETXCOMPLIANCEL3; + output PIPETXCOMPLIANCEL4; + output PIPETXCOMPLIANCEL5; + output PIPETXCOMPLIANCEL6; + output PIPETXCOMPLIANCEL7; + output PIPETXDATAKL0; + output PIPETXDATAKL1; + output PIPETXDATAKL2; + output PIPETXDATAKL3; + output PIPETXDATAKL4; + output PIPETXDATAKL5; + output PIPETXDATAKL6; + output PIPETXDATAKL7; + output PIPETXDETECTRXLOOPBACKL0; + output PIPETXDETECTRXLOOPBACKL1; + output PIPETXDETECTRXLOOPBACKL2; + output PIPETXDETECTRXLOOPBACKL3; + output PIPETXDETECTRXLOOPBACKL4; + output PIPETXDETECTRXLOOPBACKL5; + output PIPETXDETECTRXLOOPBACKL6; + output PIPETXDETECTRXLOOPBACKL7; + output PIPETXELECIDLEL0; + output PIPETXELECIDLEL1; + output PIPETXELECIDLEL2; + output PIPETXELECIDLEL3; + output PIPETXELECIDLEL4; + output PIPETXELECIDLEL5; + output PIPETXELECIDLEL6; + output PIPETXELECIDLEL7; + output SERRENABLE; + output URREPORTINGENABLE; + output [11:0] MGMTSTATSCREDIT; + output [11:0] MIMDLLBRADD; + output [11:0] MIMDLLBWADD; + output [12:0] L0COMPLETERID; + output [12:0] MIMRXBRADD; + output [12:0] MIMRXBWADD; + output [12:0] MIMTXBRADD; + output [12:0] MIMTXBWADD; + output [15:0] LLKRXPREFERREDTYPE; + output [16:0] MGMTPSO; + output [1:0] L0PWRSTATE0; + output [1:0] L0RXMACLINKERROR; + output [1:0] LLKRXVALIDN; + output [1:0] PIPEPOWERDOWNL0; + output [1:0] PIPEPOWERDOWNL1; + output [1:0] PIPEPOWERDOWNL2; + output [1:0] PIPEPOWERDOWNL3; + output [1:0] PIPEPOWERDOWNL4; + output [1:0] PIPEPOWERDOWNL5; + output [1:0] PIPEPOWERDOWNL6; + output [1:0] PIPEPOWERDOWNL7; + output [2:0] L0MULTIMSGEN0; + output [2:0] L0RXDLLPMTYPE; + output [2:0] MAXPAYLOADSIZE; + output [2:0] MAXREADREQUESTSIZE; + output [31:0] MGMTRDATA; + output [3:0] L0LTSSMSTATE; + output [3:0] L0MACNEGOTIATEDLINKWIDTH; + output [63:0] LLKRXDATA; + output [63:0] MIMDLLBWDATA; + output [63:0] MIMRXBWDATA; + output [63:0] MIMTXBWDATA; + output [6:0] L0DLLERRORVECTOR; + output [7:0] L0DLLVCSTATUS; + output [7:0] L0DLUPDOWN; + output [7:0] LLKRXCHCOMPLETIONAVAILABLEN; + output [7:0] LLKRXCHNONPOSTEDAVAILABLEN; + output [7:0] LLKRXCHPOSTEDAVAILABLEN; + output [7:0] LLKTCSTATUS; + output [7:0] LLKTXCHCOMPLETIONREADYN; + output [7:0] LLKTXCHNONPOSTEDREADYN; + output [7:0] LLKTXCHPOSTEDREADYN; + output [7:0] PIPETXDATAL0; + output [7:0] PIPETXDATAL1; + output [7:0] PIPETXDATAL2; + output [7:0] PIPETXDATAL3; + output [7:0] PIPETXDATAL4; + output [7:0] PIPETXDATAL5; + output [7:0] PIPETXDATAL6; + output [7:0] PIPETXDATAL7; + output [9:0] LLKTXCHANSPACE; + input AUXPOWER; + input COMPLIANCEAVOID; + input CRMCORECLK; + input CRMCORECLKDLO; + input CRMCORECLKRXO; + input CRMCORECLKTXO; + input CRMLINKRSTN; + input CRMMACRSTN; + input CRMMGMTRSTN; + input CRMNVRSTN; + input CRMURSTN; + input CRMUSERCFGRSTN; + input CRMUSERCLK; + input CRMUSERCLKRXO; + input CRMUSERCLKTXO; + input L0CFGDISABLESCRAMBLE; + input L0CFGLOOPBACKMASTER; + input L0LEGACYINTFUNCT0; + input L0PMEREQIN; + input L0SETCOMPLETERABORTERROR; + input L0SETCOMPLETIONTIMEOUTCORRERROR; + input L0SETCOMPLETIONTIMEOUTUNCORRERROR; + input L0SETDETECTEDCORRERROR; + input L0SETDETECTEDFATALERROR; + input L0SETDETECTEDNONFATALERROR; + input L0SETUNEXPECTEDCOMPLETIONCORRERROR; + input L0SETUNEXPECTEDCOMPLETIONUNCORRERROR; + input L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR; + input L0SETUNSUPPORTEDREQUESTOTHERERROR; + input L0SETUSERDETECTEDPARITYERROR; + input L0SETUSERMASTERDATAPARITY; + input L0SETUSERRECEIVEDMASTERABORT; + input L0SETUSERRECEIVEDTARGETABORT; + input L0SETUSERSIGNALLEDTARGETABORT; + input L0SETUSERSYSTEMERROR; + input L0TRANSACTIONSPENDING; + input LLKRXDSTCONTREQN; + input LLKRXDSTREQN; + input LLKTXEOFN; + input LLKTXEOPN; + input LLKTXSOFN; + input LLKTXSOPN; + input LLKTXSRCDSCN; + input LLKTXSRCRDYN; + input MGMTRDEN; + input MGMTWREN; + input PIPEPHYSTATUSL0; + input PIPEPHYSTATUSL1; + input PIPEPHYSTATUSL2; + input PIPEPHYSTATUSL3; + input PIPEPHYSTATUSL4; + input PIPEPHYSTATUSL5; + input PIPEPHYSTATUSL6; + input PIPEPHYSTATUSL7; + input PIPERXCHANISALIGNEDL0; + input PIPERXCHANISALIGNEDL1; + input PIPERXCHANISALIGNEDL2; + input PIPERXCHANISALIGNEDL3; + input PIPERXCHANISALIGNEDL4; + input PIPERXCHANISALIGNEDL5; + input PIPERXCHANISALIGNEDL6; + input PIPERXCHANISALIGNEDL7; + input PIPERXDATAKL0; + input PIPERXDATAKL1; + input PIPERXDATAKL2; + input PIPERXDATAKL3; + input PIPERXDATAKL4; + input PIPERXDATAKL5; + input PIPERXDATAKL6; + input PIPERXDATAKL7; + input PIPERXELECIDLEL0; + input PIPERXELECIDLEL1; + input PIPERXELECIDLEL2; + input PIPERXELECIDLEL3; + input PIPERXELECIDLEL4; + input PIPERXELECIDLEL5; + input PIPERXELECIDLEL6; + input PIPERXELECIDLEL7; + input PIPERXVALIDL0; + input PIPERXVALIDL1; + input PIPERXVALIDL2; + input PIPERXVALIDL3; + input PIPERXVALIDL4; + input PIPERXVALIDL5; + input PIPERXVALIDL6; + input PIPERXVALIDL7; + input [10:0] MGMTADDR; + input [127:0] L0PACKETHEADERFROMUSER; + input [1:0] LLKRXCHFIFO; + input [1:0] LLKTXCHFIFO; + input [1:0] LLKTXENABLEN; + input [2:0] LLKRXCHTC; + input [2:0] LLKTXCHTC; + input [2:0] PIPERXSTATUSL0; + input [2:0] PIPERXSTATUSL1; + input [2:0] PIPERXSTATUSL2; + input [2:0] PIPERXSTATUSL3; + input [2:0] PIPERXSTATUSL4; + input [2:0] PIPERXSTATUSL5; + input [2:0] PIPERXSTATUSL6; + input [2:0] PIPERXSTATUSL7; + input [31:0] MGMTWDATA; + input [3:0] L0MSIREQUEST0; + input [3:0] MGMTBWREN; + input [63:0] LLKTXDATA; + input [63:0] MIMDLLBRDATA; + input [63:0] MIMRXBRDATA; + input [63:0] MIMTXBRDATA; + input [6:0] MGMTSTATSCREDITSEL; + input [7:0] PIPERXDATAL0; + input [7:0] PIPERXDATAL1; + input [7:0] PIPERXDATAL2; + input [7:0] PIPERXDATAL3; + input [7:0] PIPERXDATAL4; + input [7:0] PIPERXDATAL5; + input [7:0] PIPERXDATAL6; + input [7:0] PIPERXDATAL7; +endmodule + +module PCIE_2_0 (...); + parameter [11:0] AER_BASE_PTR = 12'h128; + parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; + parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; + parameter [15:0] AER_CAP_ID = 16'h0001; + parameter [4:0] AER_CAP_INT_MSG_NUM_MSI = 5'h0A; + parameter [4:0] AER_CAP_INT_MSG_NUM_MSIX = 5'h15; + parameter [11:0] AER_CAP_NEXTPTR = 12'h160; + parameter AER_CAP_ON = "FALSE"; + parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE"; + parameter [3:0] AER_CAP_VERSION = 4'h1; + parameter ALLOW_X8_GEN2 = "FALSE"; + parameter [31:0] BAR0 = 32'hFFFFFF00; + parameter [31:0] BAR1 = 32'hFFFF0000; + parameter [31:0] BAR2 = 32'hFFFF000C; + parameter [31:0] BAR3 = 32'hFFFFFFFF; + parameter [31:0] BAR4 = 32'h00000000; + parameter [31:0] BAR5 = 32'h00000000; + parameter [7:0] CAPABILITIES_PTR = 8'h40; + parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000; + parameter [23:0] CLASS_CODE = 24'h000000; + parameter CMD_INTX_IMPLEMENTED = "TRUE"; + parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE"; + parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0; + parameter [6:0] CRM_MODULE_RSTS = 7'h00; + parameter [15:0] DEVICE_ID = 16'h0007; + parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE"; + parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE"; + parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0; + parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0; + parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; + parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE"; + parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2; + parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0; + parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE"; + parameter integer DEV_CAP_RSVD_14_12 = 0; + parameter integer DEV_CAP_RSVD_17_16 = 0; + parameter integer DEV_CAP_RSVD_31_29 = 0; + parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE"; + parameter DISABLE_ASPM_L1_TIMER = "FALSE"; + parameter DISABLE_BAR_FILTERING = "FALSE"; + parameter DISABLE_ID_CHECK = "FALSE"; + parameter DISABLE_LANE_REVERSAL = "FALSE"; + parameter DISABLE_RX_TC_FILTER = "FALSE"; + parameter DISABLE_SCRAMBLING = "FALSE"; + parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; + parameter [11:0] DSN_BASE_PTR = 12'h100; + parameter [15:0] DSN_CAP_ID = 16'h0003; + parameter [11:0] DSN_CAP_NEXTPTR = 12'h000; + parameter DSN_CAP_ON = "TRUE"; + parameter [3:0] DSN_CAP_VERSION = 4'h1; + parameter [10:0] ENABLE_MSG_ROUTE = 11'h000; + parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE"; + parameter ENTER_RVRY_EI_L0 = "TRUE"; + parameter EXIT_LOOPBACK_ON_EI = "TRUE"; + parameter [31:0] EXPANSION_ROM = 32'hFFFFF001; + parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F; + parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF; + parameter [7:0] HEADER_TYPE = 8'h00; + parameter [4:0] INFER_EI = 5'h00; + parameter [7:0] INTERRUPT_PIN = 8'h01; + parameter IS_SWITCH = "FALSE"; + parameter [9:0] LAST_CONFIG_DWORD = 10'h042; + parameter integer LINK_CAP_ASPM_SUPPORT = 1; + parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE"; + parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE"; + parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; + parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; + parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE"; + parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1; + parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08; + parameter integer LINK_CAP_RSVD_23_22 = 0; + parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE"; + parameter integer LINK_CONTROL_RCB = 0; + parameter LINK_CTRL2_DEEMPHASIS = "FALSE"; + parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE"; + parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2; + parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; + parameter [14:0] LL_ACK_TIMEOUT = 15'h0000; + parameter LL_ACK_TIMEOUT_EN = "FALSE"; + parameter integer LL_ACK_TIMEOUT_FUNC = 0; + parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000; + parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; + parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; + parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01; + parameter [7:0] MSIX_BASE_PTR = 8'h9C; + parameter [7:0] MSIX_CAP_ID = 8'h11; + parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00; + parameter MSIX_CAP_ON = "FALSE"; + parameter integer MSIX_CAP_PBA_BIR = 0; + parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [7:0] MSI_BASE_PTR = 8'h48; + parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE"; + parameter [7:0] MSI_CAP_ID = 8'h05; + parameter integer MSI_CAP_MULTIMSGCAP = 0; + parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0; + parameter [7:0] MSI_CAP_NEXTPTR = 8'h60; + parameter MSI_CAP_ON = "FALSE"; + parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE"; + parameter integer N_FTS_COMCLK_GEN1 = 255; + parameter integer N_FTS_COMCLK_GEN2 = 255; + parameter integer N_FTS_GEN1 = 255; + parameter integer N_FTS_GEN2 = 255; + parameter [7:0] PCIE_BASE_PTR = 8'h60; + parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10; + parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2; + parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0; + parameter [4:0] PCIE_CAP_INT_MSG_NUM = 5'h00; + parameter [7:0] PCIE_CAP_NEXTPTR = 8'h00; + parameter PCIE_CAP_ON = "TRUE"; + parameter integer PCIE_CAP_RSVD_15_14 = 0; + parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE"; + parameter integer PCIE_REVISION = 2; + parameter integer PGL0_LANE = 0; + parameter integer PGL1_LANE = 1; + parameter integer PGL2_LANE = 2; + parameter integer PGL3_LANE = 3; + parameter integer PGL4_LANE = 4; + parameter integer PGL5_LANE = 5; + parameter integer PGL6_LANE = 6; + parameter integer PGL7_LANE = 7; + parameter integer PL_AUTO_CONFIG = 0; + parameter PL_FAST_TRAIN = "FALSE"; + parameter [7:0] PM_BASE_PTR = 8'h40; + parameter integer PM_CAP_AUXCURRENT = 0; + parameter PM_CAP_D1SUPPORT = "TRUE"; + parameter PM_CAP_D2SUPPORT = "TRUE"; + parameter PM_CAP_DSI = "FALSE"; + parameter [7:0] PM_CAP_ID = 8'h01; + parameter [7:0] PM_CAP_NEXTPTR = 8'h48; + parameter PM_CAP_ON = "TRUE"; + parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F; + parameter PM_CAP_PME_CLOCK = "FALSE"; + parameter integer PM_CAP_RSVD_04 = 0; + parameter integer PM_CAP_VERSION = 3; + parameter PM_CSR_B2B3 = "FALSE"; + parameter PM_CSR_BPCCEN = "FALSE"; + parameter PM_CSR_NOSOFTRST = "TRUE"; + parameter [7:0] PM_DATA0 = 8'h01; + parameter [7:0] PM_DATA1 = 8'h01; + parameter [7:0] PM_DATA2 = 8'h01; + parameter [7:0] PM_DATA3 = 8'h01; + parameter [7:0] PM_DATA4 = 8'h01; + parameter [7:0] PM_DATA5 = 8'h01; + parameter [7:0] PM_DATA6 = 8'h01; + parameter [7:0] PM_DATA7 = 8'h01; + parameter [1:0] PM_DATA_SCALE0 = 2'h1; + parameter [1:0] PM_DATA_SCALE1 = 2'h1; + parameter [1:0] PM_DATA_SCALE2 = 2'h1; + parameter [1:0] PM_DATA_SCALE3 = 2'h1; + parameter [1:0] PM_DATA_SCALE4 = 2'h1; + parameter [1:0] PM_DATA_SCALE5 = 2'h1; + parameter [1:0] PM_DATA_SCALE6 = 2'h1; + parameter [1:0] PM_DATA_SCALE7 = 2'h1; + parameter integer RECRC_CHK = 0; + parameter RECRC_CHK_TRIM = "FALSE"; + parameter [7:0] REVISION_ID = 8'h00; + parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE"; + parameter SELECT_DLL_IF = "FALSE"; + parameter SIM_VERSION = "1.0"; + parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE"; + parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE"; + parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE"; + parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE"; + parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE"; + parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE"; + parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE"; + parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000; + parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE"; + parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE"; + parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0; + parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00; + parameter integer SPARE_BIT0 = 0; + parameter integer SPARE_BIT1 = 0; + parameter integer SPARE_BIT2 = 0; + parameter integer SPARE_BIT3 = 0; + parameter integer SPARE_BIT4 = 0; + parameter integer SPARE_BIT5 = 0; + parameter integer SPARE_BIT6 = 0; + parameter integer SPARE_BIT7 = 0; + parameter integer SPARE_BIT8 = 0; + parameter [7:0] SPARE_BYTE0 = 8'h00; + parameter [7:0] SPARE_BYTE1 = 8'h00; + parameter [7:0] SPARE_BYTE2 = 8'h00; + parameter [7:0] SPARE_BYTE3 = 8'h00; + parameter [31:0] SPARE_WORD0 = 32'h00000000; + parameter [31:0] SPARE_WORD1 = 32'h00000000; + parameter [31:0] SPARE_WORD2 = 32'h00000000; + parameter [31:0] SPARE_WORD3 = 32'h00000000; + parameter [15:0] SUBSYSTEM_ID = 16'h0007; + parameter [15:0] SUBSYSTEM_VENDOR_ID = 16'h10EE; + parameter TL_RBYPASS = "FALSE"; + parameter integer TL_RX_RAM_RADDR_LATENCY = 0; + parameter integer TL_RX_RAM_RDATA_LATENCY = 2; + parameter integer TL_RX_RAM_WRITE_LATENCY = 0; + parameter TL_TFC_DISABLE = "FALSE"; + parameter TL_TX_CHECKS_DISABLE = "FALSE"; + parameter integer TL_TX_RAM_RADDR_LATENCY = 0; + parameter integer TL_TX_RAM_RDATA_LATENCY = 2; + parameter integer TL_TX_RAM_WRITE_LATENCY = 0; + parameter UPCONFIG_CAPABLE = "TRUE"; + parameter UPSTREAM_FACING = "TRUE"; + parameter UR_INV_REQ = "TRUE"; + parameter integer USER_CLK_FREQ = 3; + parameter VC0_CPL_INFINITE = "TRUE"; + parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF; + parameter integer VC0_TOTAL_CREDITS_CD = 127; + parameter integer VC0_TOTAL_CREDITS_CH = 31; + parameter integer VC0_TOTAL_CREDITS_NPH = 12; + parameter integer VC0_TOTAL_CREDITS_PD = 288; + parameter integer VC0_TOTAL_CREDITS_PH = 32; + parameter integer VC0_TX_LASTPACKET = 31; + parameter [11:0] VC_BASE_PTR = 12'h10C; + parameter [15:0] VC_CAP_ID = 16'h0002; + parameter [11:0] VC_CAP_NEXTPTR = 12'h000; + parameter VC_CAP_ON = "FALSE"; + parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE"; + parameter [3:0] VC_CAP_VERSION = 4'h1; + parameter [15:0] VENDOR_ID = 16'h10EE; + parameter [11:0] VSEC_BASE_PTR = 12'h160; + parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234; + parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018; + parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1; + parameter [15:0] VSEC_CAP_ID = 16'h000B; + parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE"; + parameter [11:0] VSEC_CAP_NEXTPTR = 12'h000; + parameter VSEC_CAP_ON = "FALSE"; + parameter [3:0] VSEC_CAP_VERSION = 4'h1; + output CFGAERECRCCHECKEN; + output CFGAERECRCGENEN; + output CFGCOMMANDBUSMASTERENABLE; + output CFGCOMMANDINTERRUPTDISABLE; + output CFGCOMMANDIOENABLE; + output CFGCOMMANDMEMENABLE; + output CFGCOMMANDSERREN; + output CFGDEVCONTROL2CPLTIMEOUTDIS; + output CFGDEVCONTROLAUXPOWEREN; + output CFGDEVCONTROLCORRERRREPORTINGEN; + output CFGDEVCONTROLENABLERO; + output CFGDEVCONTROLEXTTAGEN; + output CFGDEVCONTROLFATALERRREPORTINGEN; + output CFGDEVCONTROLNONFATALREPORTINGEN; + output CFGDEVCONTROLNOSNOOPEN; + output CFGDEVCONTROLPHANTOMEN; + output CFGDEVCONTROLURERRREPORTINGEN; + output CFGDEVSTATUSCORRERRDETECTED; + output CFGDEVSTATUSFATALERRDETECTED; + output CFGDEVSTATUSNONFATALERRDETECTED; + output CFGDEVSTATUSURDETECTED; + output CFGERRAERHEADERLOGSETN; + output CFGERRCPLRDYN; + output CFGINTERRUPTMSIENABLE; + output CFGINTERRUPTMSIXENABLE; + output CFGINTERRUPTMSIXFM; + output CFGINTERRUPTRDYN; + output CFGLINKCONTROLAUTOBANDWIDTHINTEN; + output CFGLINKCONTROLBANDWIDTHINTEN; + output CFGLINKCONTROLCLOCKPMEN; + output CFGLINKCONTROLCOMMONCLOCK; + output CFGLINKCONTROLEXTENDEDSYNC; + output CFGLINKCONTROLHWAUTOWIDTHDIS; + output CFGLINKCONTROLLINKDISABLE; + output CFGLINKCONTROLRCB; + output CFGLINKCONTROLRETRAINLINK; + output CFGLINKSTATUSAUTOBANDWIDTHSTATUS; + output CFGLINKSTATUSBANDWITHSTATUS; + output CFGLINKSTATUSDLLACTIVE; + output CFGLINKSTATUSLINKTRAINING; + output CFGMSGRECEIVED; + output CFGMSGRECEIVEDASSERTINTA; + output CFGMSGRECEIVEDASSERTINTB; + output CFGMSGRECEIVEDASSERTINTC; + output CFGMSGRECEIVEDASSERTINTD; + output CFGMSGRECEIVEDDEASSERTINTA; + output CFGMSGRECEIVEDDEASSERTINTB; + output CFGMSGRECEIVEDDEASSERTINTC; + output CFGMSGRECEIVEDDEASSERTINTD; + output CFGMSGRECEIVEDERRCOR; + output CFGMSGRECEIVEDERRFATAL; + output CFGMSGRECEIVEDERRNONFATAL; + output CFGMSGRECEIVEDPMASNAK; + output CFGMSGRECEIVEDPMETO; + output CFGMSGRECEIVEDPMETOACK; + output CFGMSGRECEIVEDPMPME; + output CFGMSGRECEIVEDSETSLOTPOWERLIMIT; + output CFGMSGRECEIVEDUNLOCK; + output CFGPMCSRPMEEN; + output CFGPMCSRPMESTATUS; + output CFGPMRCVASREQL1N; + output CFGPMRCVENTERL1N; + output CFGPMRCVENTERL23N; + output CFGPMRCVREQACKN; + output CFGRDWRDONEN; + output CFGSLOTCONTROLELECTROMECHILCTLPULSE; + output CFGTRANSACTION; + output CFGTRANSACTIONTYPE; + output DBGSCLRA; + output DBGSCLRB; + output DBGSCLRC; + output DBGSCLRD; + output DBGSCLRE; + output DBGSCLRF; + output DBGSCLRG; + output DBGSCLRH; + output DBGSCLRI; + output DBGSCLRJ; + output DBGSCLRK; + output DRPDRDY; + output LL2BADDLLPERRN; + output LL2BADTLPERRN; + output LL2PROTOCOLERRN; + output LL2REPLAYROERRN; + output LL2REPLAYTOERRN; + output LL2SUSPENDOKN; + output LL2TFCINIT1SEQN; + output LL2TFCINIT2SEQN; + output LNKCLKEN; + output MIMRXRCE; + output MIMRXREN; + output MIMRXWEN; + output MIMTXRCE; + output MIMTXREN; + output MIMTXWEN; + output PIPERX0POLARITY; + output PIPERX1POLARITY; + output PIPERX2POLARITY; + output PIPERX3POLARITY; + output PIPERX4POLARITY; + output PIPERX5POLARITY; + output PIPERX6POLARITY; + output PIPERX7POLARITY; + output PIPETX0COMPLIANCE; + output PIPETX0ELECIDLE; + output PIPETX1COMPLIANCE; + output PIPETX1ELECIDLE; + output PIPETX2COMPLIANCE; + output PIPETX2ELECIDLE; + output PIPETX3COMPLIANCE; + output PIPETX3ELECIDLE; + output PIPETX4COMPLIANCE; + output PIPETX4ELECIDLE; + output PIPETX5COMPLIANCE; + output PIPETX5ELECIDLE; + output PIPETX6COMPLIANCE; + output PIPETX6ELECIDLE; + output PIPETX7COMPLIANCE; + output PIPETX7ELECIDLE; + output PIPETXDEEMPH; + output PIPETXRATE; + output PIPETXRCVRDET; + output PIPETXRESET; + output PL2LINKUPN; + output PL2RECEIVERERRN; + output PL2RECOVERYN; + output PL2RXELECIDLE; + output PL2SUSPENDOK; + output PLLINKGEN2CAP; + output PLLINKPARTNERGEN2SUPPORTED; + output PLLINKUPCFGCAP; + output PLPHYLNKUPN; + output PLRECEIVEDHOTRST; + output PLSELLNKRATE; + output RECEIVEDFUNCLVLRSTN; + output TL2ASPMSUSPENDCREDITCHECKOKN; + output TL2ASPMSUSPENDREQN; + output TL2PPMSUSPENDOKN; + output TRNLNKUPN; + output TRNRDLLPSRCRDYN; + output TRNRECRCERRN; + output TRNREOFN; + output TRNRERRFWDN; + output TRNRREMN; + output TRNRSOFN; + output TRNRSRCDSCN; + output TRNRSRCRDYN; + output TRNTCFGREQN; + output TRNTDLLPDSTRDYN; + output TRNTDSTRDYN; + output TRNTERRDROPN; + output USERRSTN; + output [11:0] DBGVECC; + output [11:0] PLDBGVEC; + output [11:0] TRNFCCPLD; + output [11:0] TRNFCNPD; + output [11:0] TRNFCPD; + output [12:0] MIMRXRADDR; + output [12:0] MIMRXWADDR; + output [12:0] MIMTXRADDR; + output [12:0] MIMTXWADDR; + output [15:0] CFGMSGDATA; + output [15:0] DRPDO; + output [15:0] PIPETX0DATA; + output [15:0] PIPETX1DATA; + output [15:0] PIPETX2DATA; + output [15:0] PIPETX3DATA; + output [15:0] PIPETX4DATA; + output [15:0] PIPETX5DATA; + output [15:0] PIPETX6DATA; + output [15:0] PIPETX7DATA; + output [1:0] CFGLINKCONTROLASPMCONTROL; + output [1:0] CFGLINKSTATUSCURRENTSPEED; + output [1:0] CFGPMCSRPOWERSTATE; + output [1:0] PIPETX0CHARISK; + output [1:0] PIPETX0POWERDOWN; + output [1:0] PIPETX1CHARISK; + output [1:0] PIPETX1POWERDOWN; + output [1:0] PIPETX2CHARISK; + output [1:0] PIPETX2POWERDOWN; + output [1:0] PIPETX3CHARISK; + output [1:0] PIPETX3POWERDOWN; + output [1:0] PIPETX4CHARISK; + output [1:0] PIPETX4POWERDOWN; + output [1:0] PIPETX5CHARISK; + output [1:0] PIPETX5POWERDOWN; + output [1:0] PIPETX6CHARISK; + output [1:0] PIPETX6POWERDOWN; + output [1:0] PIPETX7CHARISK; + output [1:0] PIPETX7POWERDOWN; + output [1:0] PLLANEREVERSALMODE; + output [1:0] PLRXPMSTATE; + output [1:0] PLSELLNKWIDTH; + output [2:0] CFGDEVCONTROLMAXPAYLOAD; + output [2:0] CFGDEVCONTROLMAXREADREQ; + output [2:0] CFGINTERRUPTMMENABLE; + output [2:0] CFGPCIELINKSTATE; + output [2:0] PIPETXMARGIN; + output [2:0] PLINITIALLINKWIDTH; + output [2:0] PLTXPMSTATE; + output [31:0] CFGDO; + output [31:0] TRNRDLLPDATA; + output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL; + output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH; + output [5:0] PLLTSSMSTATE; + output [5:0] TRNTBUFAV; + output [63:0] DBGVECA; + output [63:0] DBGVECB; + output [63:0] TRNRD; + output [67:0] MIMRXWDATA; + output [68:0] MIMTXWDATA; + output [6:0] CFGTRANSACTIONADDR; + output [6:0] CFGVCTCVCMAP; + output [6:0] TRNRBARHITN; + output [7:0] CFGINTERRUPTDO; + output [7:0] TRNFCCPLH; + output [7:0] TRNFCNPH; + output [7:0] TRNFCPH; + input CFGERRACSN; + input CFGERRCORN; + input CFGERRCPLABORTN; + input CFGERRCPLTIMEOUTN; + input CFGERRCPLUNEXPECTN; + input CFGERRECRCN; + input CFGERRLOCKEDN; + input CFGERRPOSTEDN; + input CFGERRURN; + input CFGINTERRUPTASSERTN; + input CFGINTERRUPTN; + input CFGPMDIRECTASPML1N; + input CFGPMSENDPMACKN; + input CFGPMSENDPMETON; + input CFGPMSENDPMNAKN; + input CFGPMTURNOFFOKN; + input CFGPMWAKEN; + input CFGRDENN; + input CFGTRNPENDINGN; + input CFGWRENN; + input CFGWRREADONLYN; + input CFGWRRW1CASRWN; + input CMRSTN; + input CMSTICKYRSTN; + input DBGSUBMODE; + input DLRSTN; + input DRPCLK; + input DRPDEN; + input DRPDWE; + input FUNCLVLRSTN; + input LL2SENDASREQL1N; + input LL2SENDENTERL1N; + input LL2SENDENTERL23N; + input LL2SUSPENDNOWN; + input LL2TLPRCVN; + input PIPECLK; + input PIPERX0CHANISALIGNED; + input PIPERX0ELECIDLE; + input PIPERX0PHYSTATUS; + input PIPERX0VALID; + input PIPERX1CHANISALIGNED; + input PIPERX1ELECIDLE; + input PIPERX1PHYSTATUS; + input PIPERX1VALID; + input PIPERX2CHANISALIGNED; + input PIPERX2ELECIDLE; + input PIPERX2PHYSTATUS; + input PIPERX2VALID; + input PIPERX3CHANISALIGNED; + input PIPERX3ELECIDLE; + input PIPERX3PHYSTATUS; + input PIPERX3VALID; + input PIPERX4CHANISALIGNED; + input PIPERX4ELECIDLE; + input PIPERX4PHYSTATUS; + input PIPERX4VALID; + input PIPERX5CHANISALIGNED; + input PIPERX5ELECIDLE; + input PIPERX5PHYSTATUS; + input PIPERX5VALID; + input PIPERX6CHANISALIGNED; + input PIPERX6ELECIDLE; + input PIPERX6PHYSTATUS; + input PIPERX6VALID; + input PIPERX7CHANISALIGNED; + input PIPERX7ELECIDLE; + input PIPERX7PHYSTATUS; + input PIPERX7VALID; + input PLDIRECTEDLINKAUTON; + input PLDIRECTEDLINKSPEED; + input PLDOWNSTREAMDEEMPHSOURCE; + input PLRSTN; + input PLTRANSMITHOTRST; + input PLUPSTREAMPREFERDEEMPH; + input SYSRSTN; + input TL2ASPMSUSPENDCREDITCHECKN; + input TL2PPMSUSPENDREQN; + input TLRSTN; + input TRNRDSTRDYN; + input TRNRNPOKN; + input TRNTCFGGNTN; + input TRNTDLLPSRCRDYN; + input TRNTECRCGENN; + input TRNTEOFN; + input TRNTERRFWDN; + input TRNTREMN; + input TRNTSOFN; + input TRNTSRCDSCN; + input TRNTSRCRDYN; + input TRNTSTRN; + input USERCLK; + input [127:0] CFGERRAERHEADERLOG; + input [15:0] DRPDI; + input [15:0] PIPERX0DATA; + input [15:0] PIPERX1DATA; + input [15:0] PIPERX2DATA; + input [15:0] PIPERX3DATA; + input [15:0] PIPERX4DATA; + input [15:0] PIPERX5DATA; + input [15:0] PIPERX6DATA; + input [15:0] PIPERX7DATA; + input [1:0] DBGMODE; + input [1:0] PIPERX0CHARISK; + input [1:0] PIPERX1CHARISK; + input [1:0] PIPERX2CHARISK; + input [1:0] PIPERX3CHARISK; + input [1:0] PIPERX4CHARISK; + input [1:0] PIPERX5CHARISK; + input [1:0] PIPERX6CHARISK; + input [1:0] PIPERX7CHARISK; + input [1:0] PLDIRECTEDLINKCHANGE; + input [1:0] PLDIRECTEDLINKWIDTH; + input [2:0] CFGDSFUNCTIONNUMBER; + input [2:0] PIPERX0STATUS; + input [2:0] PIPERX1STATUS; + input [2:0] PIPERX2STATUS; + input [2:0] PIPERX3STATUS; + input [2:0] PIPERX4STATUS; + input [2:0] PIPERX5STATUS; + input [2:0] PIPERX6STATUS; + input [2:0] PIPERX7STATUS; + input [2:0] PLDBGMODE; + input [2:0] TRNFCSEL; + input [31:0] CFGDI; + input [31:0] TRNTDLLPDATA; + input [3:0] CFGBYTEENN; + input [47:0] CFGERRTLPCPLHEADER; + input [4:0] CFGDSDEVICENUMBER; + input [4:0] PL2DIRECTEDLSTATE; + input [63:0] CFGDSN; + input [63:0] TRNTD; + input [67:0] MIMRXRDATA; + input [68:0] MIMTXRDATA; + input [7:0] CFGDSBUSNUMBER; + input [7:0] CFGINTERRUPTDI; + input [7:0] CFGPORTNUMBER; + input [8:0] DRPDADDR; + input [9:0] CFGDWADDR; +endmodule + +module PCIE_2_1 (...); + parameter [11:0] AER_BASE_PTR = 12'h140; + parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; + parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; + parameter [15:0] AER_CAP_ID = 16'h0001; + parameter AER_CAP_MULTIHEADER = "FALSE"; + parameter [11:0] AER_CAP_NEXTPTR = 12'h178; + parameter AER_CAP_ON = "FALSE"; + parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000; + parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE"; + parameter [3:0] AER_CAP_VERSION = 4'h2; + parameter ALLOW_X8_GEN2 = "FALSE"; + parameter [31:0] BAR0 = 32'hFFFFFF00; + parameter [31:0] BAR1 = 32'hFFFF0000; + parameter [31:0] BAR2 = 32'hFFFF000C; + parameter [31:0] BAR3 = 32'hFFFFFFFF; + parameter [31:0] BAR4 = 32'h00000000; + parameter [31:0] BAR5 = 32'h00000000; + parameter [7:0] CAPABILITIES_PTR = 8'h40; + parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000; + parameter integer CFG_ECRC_ERR_CPLSTAT = 0; + parameter [23:0] CLASS_CODE = 24'h000000; + parameter CMD_INTX_IMPLEMENTED = "TRUE"; + parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE"; + parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0; + parameter [6:0] CRM_MODULE_RSTS = 7'h00; + parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE"; + parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE"; + parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE"; + parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE"; + parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE"; + parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE"; + parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE"; + parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE"; + parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0; + parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE"; + parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'h0; + parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE"; + parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE"; + parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0; + parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0; + parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; + parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE"; + parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2; + parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0; + parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE"; + parameter integer DEV_CAP_RSVD_14_12 = 0; + parameter integer DEV_CAP_RSVD_17_16 = 0; + parameter integer DEV_CAP_RSVD_31_29 = 0; + parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE"; + parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE"; + parameter DISABLE_ASPM_L1_TIMER = "FALSE"; + parameter DISABLE_BAR_FILTERING = "FALSE"; + parameter DISABLE_ERR_MSG = "FALSE"; + parameter DISABLE_ID_CHECK = "FALSE"; + parameter DISABLE_LANE_REVERSAL = "FALSE"; + parameter DISABLE_LOCKED_FILTER = "FALSE"; + parameter DISABLE_PPM_FILTER = "FALSE"; + parameter DISABLE_RX_POISONED_RESP = "FALSE"; + parameter DISABLE_RX_TC_FILTER = "FALSE"; + parameter DISABLE_SCRAMBLING = "FALSE"; + parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; + parameter [11:0] DSN_BASE_PTR = 12'h100; + parameter [15:0] DSN_CAP_ID = 16'h0003; + parameter [11:0] DSN_CAP_NEXTPTR = 12'h10C; + parameter DSN_CAP_ON = "TRUE"; + parameter [3:0] DSN_CAP_VERSION = 4'h1; + parameter [10:0] ENABLE_MSG_ROUTE = 11'h000; + parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE"; + parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE"; + parameter ENTER_RVRY_EI_L0 = "TRUE"; + parameter EXIT_LOOPBACK_ON_EI = "TRUE"; + parameter [31:0] EXPANSION_ROM = 32'hFFFFF001; + parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F; + parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF; + parameter [7:0] HEADER_TYPE = 8'h00; + parameter [4:0] INFER_EI = 5'h00; + parameter [7:0] INTERRUPT_PIN = 8'h01; + parameter INTERRUPT_STAT_AUTO = "TRUE"; + parameter IS_SWITCH = "FALSE"; + parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF; + parameter LINK_CAP_ASPM_OPTIONALITY = "TRUE"; + parameter integer LINK_CAP_ASPM_SUPPORT = 1; + parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE"; + parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE"; + parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; + parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; + parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE"; + parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1; + parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08; + parameter integer LINK_CAP_RSVD_23 = 0; + parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE"; + parameter integer LINK_CONTROL_RCB = 0; + parameter LINK_CTRL2_DEEMPHASIS = "FALSE"; + parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE"; + parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2; + parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; + parameter [14:0] LL_ACK_TIMEOUT = 15'h0000; + parameter LL_ACK_TIMEOUT_EN = "FALSE"; + parameter integer LL_ACK_TIMEOUT_FUNC = 0; + parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000; + parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; + parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; + parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01; + parameter MPS_FORCE = "FALSE"; + parameter [7:0] MSIX_BASE_PTR = 8'h9C; + parameter [7:0] MSIX_CAP_ID = 8'h11; + parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00; + parameter MSIX_CAP_ON = "FALSE"; + parameter integer MSIX_CAP_PBA_BIR = 0; + parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [7:0] MSI_BASE_PTR = 8'h48; + parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE"; + parameter [7:0] MSI_CAP_ID = 8'h05; + parameter integer MSI_CAP_MULTIMSGCAP = 0; + parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0; + parameter [7:0] MSI_CAP_NEXTPTR = 8'h60; + parameter MSI_CAP_ON = "FALSE"; + parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE"; + parameter integer N_FTS_COMCLK_GEN1 = 255; + parameter integer N_FTS_COMCLK_GEN2 = 255; + parameter integer N_FTS_GEN1 = 255; + parameter integer N_FTS_GEN2 = 255; + parameter [7:0] PCIE_BASE_PTR = 8'h60; + parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10; + parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2; + parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0; + parameter [7:0] PCIE_CAP_NEXTPTR = 8'h9C; + parameter PCIE_CAP_ON = "TRUE"; + parameter integer PCIE_CAP_RSVD_15_14 = 0; + parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE"; + parameter integer PCIE_REVISION = 2; + parameter integer PL_AUTO_CONFIG = 0; + parameter PL_FAST_TRAIN = "FALSE"; + parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000; + parameter PM_ASPML0S_TIMEOUT_EN = "FALSE"; + parameter integer PM_ASPML0S_TIMEOUT_FUNC = 0; + parameter PM_ASPM_FASTEXIT = "FALSE"; + parameter [7:0] PM_BASE_PTR = 8'h40; + parameter integer PM_CAP_AUXCURRENT = 0; + parameter PM_CAP_D1SUPPORT = "TRUE"; + parameter PM_CAP_D2SUPPORT = "TRUE"; + parameter PM_CAP_DSI = "FALSE"; + parameter [7:0] PM_CAP_ID = 8'h01; + parameter [7:0] PM_CAP_NEXTPTR = 8'h48; + parameter PM_CAP_ON = "TRUE"; + parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F; + parameter PM_CAP_PME_CLOCK = "FALSE"; + parameter integer PM_CAP_RSVD_04 = 0; + parameter integer PM_CAP_VERSION = 3; + parameter PM_CSR_B2B3 = "FALSE"; + parameter PM_CSR_BPCCEN = "FALSE"; + parameter PM_CSR_NOSOFTRST = "TRUE"; + parameter [7:0] PM_DATA0 = 8'h01; + parameter [7:0] PM_DATA1 = 8'h01; + parameter [7:0] PM_DATA2 = 8'h01; + parameter [7:0] PM_DATA3 = 8'h01; + parameter [7:0] PM_DATA4 = 8'h01; + parameter [7:0] PM_DATA5 = 8'h01; + parameter [7:0] PM_DATA6 = 8'h01; + parameter [7:0] PM_DATA7 = 8'h01; + parameter [1:0] PM_DATA_SCALE0 = 2'h1; + parameter [1:0] PM_DATA_SCALE1 = 2'h1; + parameter [1:0] PM_DATA_SCALE2 = 2'h1; + parameter [1:0] PM_DATA_SCALE3 = 2'h1; + parameter [1:0] PM_DATA_SCALE4 = 2'h1; + parameter [1:0] PM_DATA_SCALE5 = 2'h1; + parameter [1:0] PM_DATA_SCALE6 = 2'h1; + parameter [1:0] PM_DATA_SCALE7 = 2'h1; + parameter PM_MF = "FALSE"; + parameter [11:0] RBAR_BASE_PTR = 12'h178; + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00; + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00; + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00; + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00; + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00; + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00; + parameter [15:0] RBAR_CAP_ID = 16'h0015; + parameter [2:0] RBAR_CAP_INDEX0 = 3'h0; + parameter [2:0] RBAR_CAP_INDEX1 = 3'h0; + parameter [2:0] RBAR_CAP_INDEX2 = 3'h0; + parameter [2:0] RBAR_CAP_INDEX3 = 3'h0; + parameter [2:0] RBAR_CAP_INDEX4 = 3'h0; + parameter [2:0] RBAR_CAP_INDEX5 = 3'h0; + parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000; + parameter RBAR_CAP_ON = "FALSE"; + parameter [31:0] RBAR_CAP_SUP0 = 32'h00000000; + parameter [31:0] RBAR_CAP_SUP1 = 32'h00000000; + parameter [31:0] RBAR_CAP_SUP2 = 32'h00000000; + parameter [31:0] RBAR_CAP_SUP3 = 32'h00000000; + parameter [31:0] RBAR_CAP_SUP4 = 32'h00000000; + parameter [31:0] RBAR_CAP_SUP5 = 32'h00000000; + parameter [3:0] RBAR_CAP_VERSION = 4'h1; + parameter [2:0] RBAR_NUM = 3'h1; + parameter integer RECRC_CHK = 0; + parameter RECRC_CHK_TRIM = "FALSE"; + parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE"; + parameter [1:0] RP_AUTO_SPD = 2'h1; + parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1F; + parameter SELECT_DLL_IF = "FALSE"; + parameter SIM_VERSION = "1.0"; + parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE"; + parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE"; + parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE"; + parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE"; + parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE"; + parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE"; + parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE"; + parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000; + parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE"; + parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE"; + parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0; + parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00; + parameter integer SPARE_BIT0 = 0; + parameter integer SPARE_BIT1 = 0; + parameter integer SPARE_BIT2 = 0; + parameter integer SPARE_BIT3 = 0; + parameter integer SPARE_BIT4 = 0; + parameter integer SPARE_BIT5 = 0; + parameter integer SPARE_BIT6 = 0; + parameter integer SPARE_BIT7 = 0; + parameter integer SPARE_BIT8 = 0; + parameter [7:0] SPARE_BYTE0 = 8'h00; + parameter [7:0] SPARE_BYTE1 = 8'h00; + parameter [7:0] SPARE_BYTE2 = 8'h00; + parameter [7:0] SPARE_BYTE3 = 8'h00; + parameter [31:0] SPARE_WORD0 = 32'h00000000; + parameter [31:0] SPARE_WORD1 = 32'h00000000; + parameter [31:0] SPARE_WORD2 = 32'h00000000; + parameter [31:0] SPARE_WORD3 = 32'h00000000; + parameter SSL_MESSAGE_AUTO = "FALSE"; + parameter TECRC_EP_INV = "FALSE"; + parameter TL_RBYPASS = "FALSE"; + parameter integer TL_RX_RAM_RADDR_LATENCY = 0; + parameter integer TL_RX_RAM_RDATA_LATENCY = 2; + parameter integer TL_RX_RAM_WRITE_LATENCY = 0; + parameter TL_TFC_DISABLE = "FALSE"; + parameter TL_TX_CHECKS_DISABLE = "FALSE"; + parameter integer TL_TX_RAM_RADDR_LATENCY = 0; + parameter integer TL_TX_RAM_RDATA_LATENCY = 2; + parameter integer TL_TX_RAM_WRITE_LATENCY = 0; + parameter TRN_DW = "FALSE"; + parameter TRN_NP_FC = "FALSE"; + parameter UPCONFIG_CAPABLE = "TRUE"; + parameter UPSTREAM_FACING = "TRUE"; + parameter UR_ATOMIC = "TRUE"; + parameter UR_CFG1 = "TRUE"; + parameter UR_INV_REQ = "TRUE"; + parameter UR_PRS_RESPONSE = "TRUE"; + parameter USER_CLK2_DIV2 = "FALSE"; + parameter integer USER_CLK_FREQ = 3; + parameter USE_RID_PINS = "FALSE"; + parameter VC0_CPL_INFINITE = "TRUE"; + parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF; + parameter integer VC0_TOTAL_CREDITS_CD = 127; + parameter integer VC0_TOTAL_CREDITS_CH = 31; + parameter integer VC0_TOTAL_CREDITS_NPD = 24; + parameter integer VC0_TOTAL_CREDITS_NPH = 12; + parameter integer VC0_TOTAL_CREDITS_PD = 288; + parameter integer VC0_TOTAL_CREDITS_PH = 32; + parameter integer VC0_TX_LASTPACKET = 31; + parameter [11:0] VC_BASE_PTR = 12'h10C; + parameter [15:0] VC_CAP_ID = 16'h0002; + parameter [11:0] VC_CAP_NEXTPTR = 12'h000; + parameter VC_CAP_ON = "FALSE"; + parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE"; + parameter [3:0] VC_CAP_VERSION = 4'h1; + parameter [11:0] VSEC_BASE_PTR = 12'h128; + parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234; + parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018; + parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1; + parameter [15:0] VSEC_CAP_ID = 16'h000B; + parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE"; + parameter [11:0] VSEC_CAP_NEXTPTR = 12'h140; + parameter VSEC_CAP_ON = "FALSE"; + parameter [3:0] VSEC_CAP_VERSION = 4'h1; + output CFGAERECRCCHECKEN; + output CFGAERECRCGENEN; + output CFGAERROOTERRCORRERRRECEIVED; + output CFGAERROOTERRCORRERRREPORTINGEN; + output CFGAERROOTERRFATALERRRECEIVED; + output CFGAERROOTERRFATALERRREPORTINGEN; + output CFGAERROOTERRNONFATALERRRECEIVED; + output CFGAERROOTERRNONFATALERRREPORTINGEN; + output CFGBRIDGESERREN; + output CFGCOMMANDBUSMASTERENABLE; + output CFGCOMMANDINTERRUPTDISABLE; + output CFGCOMMANDIOENABLE; + output CFGCOMMANDMEMENABLE; + output CFGCOMMANDSERREN; + output CFGDEVCONTROL2ARIFORWARDEN; + output CFGDEVCONTROL2ATOMICEGRESSBLOCK; + output CFGDEVCONTROL2ATOMICREQUESTEREN; + output CFGDEVCONTROL2CPLTIMEOUTDIS; + output CFGDEVCONTROL2IDOCPLEN; + output CFGDEVCONTROL2IDOREQEN; + output CFGDEVCONTROL2LTREN; + output CFGDEVCONTROL2TLPPREFIXBLOCK; + output CFGDEVCONTROLAUXPOWEREN; + output CFGDEVCONTROLCORRERRREPORTINGEN; + output CFGDEVCONTROLENABLERO; + output CFGDEVCONTROLEXTTAGEN; + output CFGDEVCONTROLFATALERRREPORTINGEN; + output CFGDEVCONTROLNONFATALREPORTINGEN; + output CFGDEVCONTROLNOSNOOPEN; + output CFGDEVCONTROLPHANTOMEN; + output CFGDEVCONTROLURERRREPORTINGEN; + output CFGDEVSTATUSCORRERRDETECTED; + output CFGDEVSTATUSFATALERRDETECTED; + output CFGDEVSTATUSNONFATALERRDETECTED; + output CFGDEVSTATUSURDETECTED; + output CFGERRAERHEADERLOGSETN; + output CFGERRCPLRDYN; + output CFGINTERRUPTMSIENABLE; + output CFGINTERRUPTMSIXENABLE; + output CFGINTERRUPTMSIXFM; + output CFGINTERRUPTRDYN; + output CFGLINKCONTROLAUTOBANDWIDTHINTEN; + output CFGLINKCONTROLBANDWIDTHINTEN; + output CFGLINKCONTROLCLOCKPMEN; + output CFGLINKCONTROLCOMMONCLOCK; + output CFGLINKCONTROLEXTENDEDSYNC; + output CFGLINKCONTROLHWAUTOWIDTHDIS; + output CFGLINKCONTROLLINKDISABLE; + output CFGLINKCONTROLRCB; + output CFGLINKCONTROLRETRAINLINK; + output CFGLINKSTATUSAUTOBANDWIDTHSTATUS; + output CFGLINKSTATUSBANDWIDTHSTATUS; + output CFGLINKSTATUSDLLACTIVE; + output CFGLINKSTATUSLINKTRAINING; + output CFGMGMTRDWRDONEN; + output CFGMSGRECEIVED; + output CFGMSGRECEIVEDASSERTINTA; + output CFGMSGRECEIVEDASSERTINTB; + output CFGMSGRECEIVEDASSERTINTC; + output CFGMSGRECEIVEDASSERTINTD; + output CFGMSGRECEIVEDDEASSERTINTA; + output CFGMSGRECEIVEDDEASSERTINTB; + output CFGMSGRECEIVEDDEASSERTINTC; + output CFGMSGRECEIVEDDEASSERTINTD; + output CFGMSGRECEIVEDERRCOR; + output CFGMSGRECEIVEDERRFATAL; + output CFGMSGRECEIVEDERRNONFATAL; + output CFGMSGRECEIVEDPMASNAK; + output CFGMSGRECEIVEDPMETO; + output CFGMSGRECEIVEDPMETOACK; + output CFGMSGRECEIVEDPMPME; + output CFGMSGRECEIVEDSETSLOTPOWERLIMIT; + output CFGMSGRECEIVEDUNLOCK; + output CFGPMCSRPMEEN; + output CFGPMCSRPMESTATUS; + output CFGPMRCVASREQL1N; + output CFGPMRCVENTERL1N; + output CFGPMRCVENTERL23N; + output CFGPMRCVREQACKN; + output CFGROOTCONTROLPMEINTEN; + output CFGROOTCONTROLSYSERRCORRERREN; + output CFGROOTCONTROLSYSERRFATALERREN; + output CFGROOTCONTROLSYSERRNONFATALERREN; + output CFGSLOTCONTROLELECTROMECHILCTLPULSE; + output CFGTRANSACTION; + output CFGTRANSACTIONTYPE; + output DBGSCLRA; + output DBGSCLRB; + output DBGSCLRC; + output DBGSCLRD; + output DBGSCLRE; + output DBGSCLRF; + output DBGSCLRG; + output DBGSCLRH; + output DBGSCLRI; + output DBGSCLRJ; + output DBGSCLRK; + output DRPRDY; + output LL2BADDLLPERR; + output LL2BADTLPERR; + output LL2PROTOCOLERR; + output LL2RECEIVERERR; + output LL2REPLAYROERR; + output LL2REPLAYTOERR; + output LL2SUSPENDOK; + output LL2TFCINIT1SEQ; + output LL2TFCINIT2SEQ; + output LL2TXIDLE; + output LNKCLKEN; + output MIMRXREN; + output MIMRXWEN; + output MIMTXREN; + output MIMTXWEN; + output PIPERX0POLARITY; + output PIPERX1POLARITY; + output PIPERX2POLARITY; + output PIPERX3POLARITY; + output PIPERX4POLARITY; + output PIPERX5POLARITY; + output PIPERX6POLARITY; + output PIPERX7POLARITY; + output PIPETX0COMPLIANCE; + output PIPETX0ELECIDLE; + output PIPETX1COMPLIANCE; + output PIPETX1ELECIDLE; + output PIPETX2COMPLIANCE; + output PIPETX2ELECIDLE; + output PIPETX3COMPLIANCE; + output PIPETX3ELECIDLE; + output PIPETX4COMPLIANCE; + output PIPETX4ELECIDLE; + output PIPETX5COMPLIANCE; + output PIPETX5ELECIDLE; + output PIPETX6COMPLIANCE; + output PIPETX6ELECIDLE; + output PIPETX7COMPLIANCE; + output PIPETX7ELECIDLE; + output PIPETXDEEMPH; + output PIPETXRATE; + output PIPETXRCVRDET; + output PIPETXRESET; + output PL2L0REQ; + output PL2LINKUP; + output PL2RECEIVERERR; + output PL2RECOVERY; + output PL2RXELECIDLE; + output PL2SUSPENDOK; + output PLDIRECTEDCHANGEDONE; + output PLLINKGEN2CAP; + output PLLINKPARTNERGEN2SUPPORTED; + output PLLINKUPCFGCAP; + output PLPHYLNKUPN; + output PLRECEIVEDHOTRST; + output PLSELLNKRATE; + output RECEIVEDFUNCLVLRSTN; + output TL2ASPMSUSPENDCREDITCHECKOK; + output TL2ASPMSUSPENDREQ; + output TL2ERRFCPE; + output TL2ERRMALFORMED; + output TL2ERRRXOVERFLOW; + output TL2PPMSUSPENDOK; + output TRNLNKUP; + output TRNRECRCERR; + output TRNREOF; + output TRNRERRFWD; + output TRNRSOF; + output TRNRSRCDSC; + output TRNRSRCRDY; + output TRNTCFGREQ; + output TRNTDLLPDSTRDY; + output TRNTERRDROP; + output USERRSTN; + output [11:0] DBGVECC; + output [11:0] PLDBGVEC; + output [11:0] TRNFCCPLD; + output [11:0] TRNFCNPD; + output [11:0] TRNFCPD; + output [127:0] TRNRD; + output [12:0] MIMRXRADDR; + output [12:0] MIMRXWADDR; + output [12:0] MIMTXRADDR; + output [12:0] MIMTXWADDR; + output [15:0] CFGMSGDATA; + output [15:0] DRPDO; + output [15:0] PIPETX0DATA; + output [15:0] PIPETX1DATA; + output [15:0] PIPETX2DATA; + output [15:0] PIPETX3DATA; + output [15:0] PIPETX4DATA; + output [15:0] PIPETX5DATA; + output [15:0] PIPETX6DATA; + output [15:0] PIPETX7DATA; + output [1:0] CFGLINKCONTROLASPMCONTROL; + output [1:0] CFGLINKSTATUSCURRENTSPEED; + output [1:0] CFGPMCSRPOWERSTATE; + output [1:0] PIPETX0CHARISK; + output [1:0] PIPETX0POWERDOWN; + output [1:0] PIPETX1CHARISK; + output [1:0] PIPETX1POWERDOWN; + output [1:0] PIPETX2CHARISK; + output [1:0] PIPETX2POWERDOWN; + output [1:0] PIPETX3CHARISK; + output [1:0] PIPETX3POWERDOWN; + output [1:0] PIPETX4CHARISK; + output [1:0] PIPETX4POWERDOWN; + output [1:0] PIPETX5CHARISK; + output [1:0] PIPETX5POWERDOWN; + output [1:0] PIPETX6CHARISK; + output [1:0] PIPETX6POWERDOWN; + output [1:0] PIPETX7CHARISK; + output [1:0] PIPETX7POWERDOWN; + output [1:0] PL2RXPMSTATE; + output [1:0] PLLANEREVERSALMODE; + output [1:0] PLRXPMSTATE; + output [1:0] PLSELLNKWIDTH; + output [1:0] TRNRDLLPSRCRDY; + output [1:0] TRNRREM; + output [2:0] CFGDEVCONTROLMAXPAYLOAD; + output [2:0] CFGDEVCONTROLMAXREADREQ; + output [2:0] CFGINTERRUPTMMENABLE; + output [2:0] CFGPCIELINKSTATE; + output [2:0] PIPETXMARGIN; + output [2:0] PLINITIALLINKWIDTH; + output [2:0] PLTXPMSTATE; + output [31:0] CFGMGMTDO; + output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL; + output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH; + output [3:0] TRNTDSTRDY; + output [4:0] LL2LINKSTATUS; + output [5:0] PLLTSSMSTATE; + output [5:0] TRNTBUFAV; + output [63:0] DBGVECA; + output [63:0] DBGVECB; + output [63:0] TL2ERRHDR; + output [63:0] TRNRDLLPDATA; + output [67:0] MIMRXWDATA; + output [68:0] MIMTXWDATA; + output [6:0] CFGTRANSACTIONADDR; + output [6:0] CFGVCTCVCMAP; + output [7:0] CFGINTERRUPTDO; + output [7:0] TRNFCCPLH; + output [7:0] TRNFCNPH; + output [7:0] TRNFCPH; + output [7:0] TRNRBARHIT; + input CFGERRACSN; + input CFGERRATOMICEGRESSBLOCKEDN; + input CFGERRCORN; + input CFGERRCPLABORTN; + input CFGERRCPLTIMEOUTN; + input CFGERRCPLUNEXPECTN; + input CFGERRECRCN; + input CFGERRINTERNALCORN; + input CFGERRINTERNALUNCORN; + input CFGERRLOCKEDN; + input CFGERRMALFORMEDN; + input CFGERRMCBLOCKEDN; + input CFGERRNORECOVERYN; + input CFGERRPOISONEDN; + input CFGERRPOSTEDN; + input CFGERRURN; + input CFGFORCECOMMONCLOCKOFF; + input CFGFORCEEXTENDEDSYNCON; + input CFGINTERRUPTASSERTN; + input CFGINTERRUPTN; + input CFGINTERRUPTSTATN; + input CFGMGMTRDENN; + input CFGMGMTWRENN; + input CFGMGMTWRREADONLYN; + input CFGMGMTWRRW1CASRWN; + input CFGPMFORCESTATEENN; + input CFGPMHALTASPML0SN; + input CFGPMHALTASPML1N; + input CFGPMSENDPMETON; + input CFGPMTURNOFFOKN; + input CFGPMWAKEN; + input CFGTRNPENDINGN; + input CMRSTN; + input CMSTICKYRSTN; + input DBGSUBMODE; + input DLRSTN; + input DRPCLK; + input DRPEN; + input DRPWE; + input FUNCLVLRSTN; + input LL2SENDASREQL1; + input LL2SENDENTERL1; + input LL2SENDENTERL23; + input LL2SENDPMACK; + input LL2SUSPENDNOW; + input LL2TLPRCV; + input PIPECLK; + input PIPERX0CHANISALIGNED; + input PIPERX0ELECIDLE; + input PIPERX0PHYSTATUS; + input PIPERX0VALID; + input PIPERX1CHANISALIGNED; + input PIPERX1ELECIDLE; + input PIPERX1PHYSTATUS; + input PIPERX1VALID; + input PIPERX2CHANISALIGNED; + input PIPERX2ELECIDLE; + input PIPERX2PHYSTATUS; + input PIPERX2VALID; + input PIPERX3CHANISALIGNED; + input PIPERX3ELECIDLE; + input PIPERX3PHYSTATUS; + input PIPERX3VALID; + input PIPERX4CHANISALIGNED; + input PIPERX4ELECIDLE; + input PIPERX4PHYSTATUS; + input PIPERX4VALID; + input PIPERX5CHANISALIGNED; + input PIPERX5ELECIDLE; + input PIPERX5PHYSTATUS; + input PIPERX5VALID; + input PIPERX6CHANISALIGNED; + input PIPERX6ELECIDLE; + input PIPERX6PHYSTATUS; + input PIPERX6VALID; + input PIPERX7CHANISALIGNED; + input PIPERX7ELECIDLE; + input PIPERX7PHYSTATUS; + input PIPERX7VALID; + input PLDIRECTEDLINKAUTON; + input PLDIRECTEDLINKSPEED; + input PLDIRECTEDLTSSMNEWVLD; + input PLDIRECTEDLTSSMSTALL; + input PLDOWNSTREAMDEEMPHSOURCE; + input PLRSTN; + input PLTRANSMITHOTRST; + input PLUPSTREAMPREFERDEEMPH; + input SYSRSTN; + input TL2ASPMSUSPENDCREDITCHECK; + input TL2PPMSUSPENDREQ; + input TLRSTN; + input TRNRDSTRDY; + input TRNRFCPRET; + input TRNRNPOK; + input TRNRNPREQ; + input TRNTCFGGNT; + input TRNTDLLPSRCRDY; + input TRNTECRCGEN; + input TRNTEOF; + input TRNTERRFWD; + input TRNTSOF; + input TRNTSRCDSC; + input TRNTSRCRDY; + input TRNTSTR; + input USERCLK2; + input USERCLK; + input [127:0] CFGERRAERHEADERLOG; + input [127:0] TRNTD; + input [15:0] CFGDEVID; + input [15:0] CFGSUBSYSID; + input [15:0] CFGSUBSYSVENDID; + input [15:0] CFGVENDID; + input [15:0] DRPDI; + input [15:0] PIPERX0DATA; + input [15:0] PIPERX1DATA; + input [15:0] PIPERX2DATA; + input [15:0] PIPERX3DATA; + input [15:0] PIPERX4DATA; + input [15:0] PIPERX5DATA; + input [15:0] PIPERX6DATA; + input [15:0] PIPERX7DATA; + input [1:0] CFGPMFORCESTATE; + input [1:0] DBGMODE; + input [1:0] PIPERX0CHARISK; + input [1:0] PIPERX1CHARISK; + input [1:0] PIPERX2CHARISK; + input [1:0] PIPERX3CHARISK; + input [1:0] PIPERX4CHARISK; + input [1:0] PIPERX5CHARISK; + input [1:0] PIPERX6CHARISK; + input [1:0] PIPERX7CHARISK; + input [1:0] PLDIRECTEDLINKCHANGE; + input [1:0] PLDIRECTEDLINKWIDTH; + input [1:0] TRNTREM; + input [2:0] CFGDSFUNCTIONNUMBER; + input [2:0] CFGFORCEMPS; + input [2:0] PIPERX0STATUS; + input [2:0] PIPERX1STATUS; + input [2:0] PIPERX2STATUS; + input [2:0] PIPERX3STATUS; + input [2:0] PIPERX4STATUS; + input [2:0] PIPERX5STATUS; + input [2:0] PIPERX6STATUS; + input [2:0] PIPERX7STATUS; + input [2:0] PLDBGMODE; + input [2:0] TRNFCSEL; + input [31:0] CFGMGMTDI; + input [31:0] TRNTDLLPDATA; + input [3:0] CFGMGMTBYTEENN; + input [47:0] CFGERRTLPCPLHEADER; + input [4:0] CFGAERINTERRUPTMSGNUM; + input [4:0] CFGDSDEVICENUMBER; + input [4:0] CFGPCIECAPINTERRUPTMSGNUM; + input [4:0] PL2DIRECTEDLSTATE; + input [5:0] PLDIRECTEDLTSSMNEW; + input [63:0] CFGDSN; + input [67:0] MIMRXRDATA; + input [68:0] MIMTXRDATA; + input [7:0] CFGDSBUSNUMBER; + input [7:0] CFGINTERRUPTDI; + input [7:0] CFGPORTNUMBER; + input [7:0] CFGREVID; + input [8:0] DRPADDR; + input [9:0] CFGMGMTDWADDR; +endmodule + +module PCIE_3_0 (...); + parameter ARI_CAP_ENABLE = "FALSE"; + parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE"; + parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE"; + parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE"; + parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE"; + parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000; + parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE"; + parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE"; + parameter AXISTEN_IF_RC_STRADDLE = "FALSE"; + parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE"; + parameter AXISTEN_IF_RQ_PARITY_CHK = "TRUE"; + parameter [1:0] AXISTEN_IF_WIDTH = 2'h2; + parameter CRM_CORE_CLK_FREQ_500 = "TRUE"; + parameter [1:0] CRM_USER_CLK_FREQ = 2'h2; + parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; + parameter [1:0] GEN3_PCS_AUTO_REALIGN = 2'h1; + parameter GEN3_PCS_RX_ELECIDLE_INTERNAL = "TRUE"; + parameter [8:0] LL_ACK_TIMEOUT = 9'h000; + parameter LL_ACK_TIMEOUT_EN = "FALSE"; + parameter integer LL_ACK_TIMEOUT_FUNC = 0; + parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0000; + parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; + parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0000; + parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; + parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0000; + parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; + parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0000; + parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; + parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000; + parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; + parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; + parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0FA; + parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE"; + parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE"; + parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; + parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; + parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [3:0] PF0_ARI_CAP_VER = 4'h1; + parameter [4:0] PF0_BAR0_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR0_CONTROL = 3'h4; + parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF0_BAR1_CONTROL = 3'h0; + parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR2_CONTROL = 3'h4; + parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR3_CONTROL = 3'h0; + parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR4_CONTROL = 3'h4; + parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR5_CONTROL = 3'h0; + parameter [7:0] PF0_BIST_REGISTER = 8'h00; + parameter [7:0] PF0_CAPABILITY_POINTER = 8'h50; + parameter [23:0] PF0_CLASS_CODE = 24'h000000; + parameter [15:0] PF0_DEVICE_ID = 16'h0000; + parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE"; + parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE"; + parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0; + parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE"; + parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0; + parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0; + parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; + parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE"; + parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h000; + parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h00; + parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; + parameter [3:0] PF0_DPA_CAP_VER = 4'h1; + parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF0_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [7:0] PF0_INTERRUPT_LINE = 8'h00; + parameter [2:0] PF0_INTERRUPT_PIN = 3'h1; + parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7; + parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; + parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000; + parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000; + parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000; + parameter [3:0] PF0_LTR_CAP_VER = 4'h1; + parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF0_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF0_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00; + parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h000; + parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; + parameter [3:0] PF0_PB_CAP_VER = 4'h1; + parameter [7:0] PF0_PM_CAP_ID = 8'h01; + parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00; + parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE"; + parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE"; + parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE"; + parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE"; + parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3; + parameter PF0_PM_CSR_NOSOFTRESET = "TRUE"; + parameter PF0_RBAR_CAP_ENABLE = "FALSE"; + parameter [2:0] PF0_RBAR_CAP_INDEX0 = 3'h0; + parameter [2:0] PF0_RBAR_CAP_INDEX1 = 3'h0; + parameter [2:0] PF0_RBAR_CAP_INDEX2 = 3'h0; + parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h000; + parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h00000; + parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h00000; + parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h00000; + parameter [3:0] PF0_RBAR_CAP_VER = 4'h1; + parameter [2:0] PF0_RBAR_NUM = 3'h1; + parameter [7:0] PF0_REVISION_ID = 8'h00; + parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0; + parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0; + parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0000; + parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter PF0_TPHR_CAP_ENABLE = "FALSE"; + parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] PF0_TPHR_CAP_VER = 4'h1; + parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000; + parameter [3:0] PF0_VC_CAP_VER = 4'h1; + parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; + parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; + parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [4:0] PF1_BAR0_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR0_CONTROL = 3'h4; + parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF1_BAR1_CONTROL = 3'h0; + parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR2_CONTROL = 3'h4; + parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR3_CONTROL = 3'h0; + parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR4_CONTROL = 3'h4; + parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR5_CONTROL = 3'h0; + parameter [7:0] PF1_BIST_REGISTER = 8'h00; + parameter [7:0] PF1_CAPABILITY_POINTER = 8'h50; + parameter [23:0] PF1_CLASS_CODE = 24'h000000; + parameter [15:0] PF1_DEVICE_ID = 16'h0000; + parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h000; + parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h00; + parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; + parameter [3:0] PF1_DPA_CAP_VER = 4'h1; + parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF1_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [7:0] PF1_INTERRUPT_LINE = 8'h00; + parameter [2:0] PF1_INTERRUPT_PIN = 3'h1; + parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF1_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF1_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00; + parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h000; + parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; + parameter [3:0] PF1_PB_CAP_VER = 4'h1; + parameter [7:0] PF1_PM_CAP_ID = 8'h01; + parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] PF1_PM_CAP_VER_ID = 3'h3; + parameter PF1_RBAR_CAP_ENABLE = "FALSE"; + parameter [2:0] PF1_RBAR_CAP_INDEX0 = 3'h0; + parameter [2:0] PF1_RBAR_CAP_INDEX1 = 3'h0; + parameter [2:0] PF1_RBAR_CAP_INDEX2 = 3'h0; + parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h000; + parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h00000; + parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h00000; + parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h00000; + parameter [3:0] PF1_RBAR_CAP_VER = 4'h1; + parameter [2:0] PF1_RBAR_NUM = 3'h1; + parameter [7:0] PF1_REVISION_ID = 8'h00; + parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0; + parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0; + parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0000; + parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter PF1_TPHR_CAP_ENABLE = "FALSE"; + parameter PF1_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] PF1_TPHR_CAP_VER = 4'h1; + parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE"; + parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE"; + parameter PL_DISABLE_SCRAMBLING = "FALSE"; + parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE"; + parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE"; + parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE"; + parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02; + parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1; + parameter PL_EQ_BYPASS_PHASE23 = "FALSE"; + parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE"; + parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h3F00; + parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4; + parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h8; + parameter integer PL_N_FTS_COMCLK_GEN1 = 255; + parameter integer PL_N_FTS_COMCLK_GEN2 = 255; + parameter integer PL_N_FTS_COMCLK_GEN3 = 255; + parameter integer PL_N_FTS_GEN1 = 255; + parameter integer PL_N_FTS_GEN2 = 255; + parameter integer PL_N_FTS_GEN3 = 255; + parameter PL_SIM_FAST_LINK_TRAINING = "FALSE"; + parameter PL_UPSTREAM_FACING = "TRUE"; + parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h05DC; + parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h00000; + parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE"; + parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000000; + parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h186A0; + parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0064; + parameter SIM_VERSION = "1.0"; + parameter integer SPARE_BIT0 = 0; + parameter integer SPARE_BIT1 = 0; + parameter integer SPARE_BIT2 = 0; + parameter integer SPARE_BIT3 = 0; + parameter integer SPARE_BIT4 = 0; + parameter integer SPARE_BIT5 = 0; + parameter integer SPARE_BIT6 = 0; + parameter integer SPARE_BIT7 = 0; + parameter integer SPARE_BIT8 = 0; + parameter [7:0] SPARE_BYTE0 = 8'h00; + parameter [7:0] SPARE_BYTE1 = 8'h00; + parameter [7:0] SPARE_BYTE2 = 8'h00; + parameter [7:0] SPARE_BYTE3 = 8'h00; + parameter [31:0] SPARE_WORD0 = 32'h00000000; + parameter [31:0] SPARE_WORD1 = 32'h00000000; + parameter [31:0] SPARE_WORD2 = 32'h00000000; + parameter [31:0] SPARE_WORD3 = 32'h00000000; + parameter SRIOV_CAP_ENABLE = "FALSE"; + parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'hBEBC20; + parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h0000000; + parameter [11:0] TL_CREDITS_CD = 12'h3E0; + parameter [7:0] TL_CREDITS_CH = 8'h20; + parameter [11:0] TL_CREDITS_NPD = 12'h028; + parameter [7:0] TL_CREDITS_NPH = 8'h20; + parameter [11:0] TL_CREDITS_PD = 12'h198; + parameter [7:0] TL_CREDITS_PH = 8'h20; + parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "TRUE"; + parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; + parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; + parameter TL_LEGACY_MODE_ENABLE = "FALSE"; + parameter TL_PF_ENABLE_REG = "FALSE"; + parameter TL_TAG_MGMT_ENABLE = "TRUE"; + parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] VF0_CAPABILITY_POINTER = 8'h50; + parameter integer VF0_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF0_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF0_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF0_PM_CAP_ID = 8'h01; + parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF0_PM_CAP_VER_ID = 3'h3; + parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF0_TPHR_CAP_ENABLE = "FALSE"; + parameter VF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF0_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF1_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF1_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF1_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF1_PM_CAP_ID = 8'h01; + parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF1_PM_CAP_VER_ID = 3'h3; + parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF1_TPHR_CAP_ENABLE = "FALSE"; + parameter VF1_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF1_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF2_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF2_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF2_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF2_PM_CAP_ID = 8'h01; + parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF2_PM_CAP_VER_ID = 3'h3; + parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF2_TPHR_CAP_ENABLE = "FALSE"; + parameter VF2_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF2_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF3_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF3_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF3_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF3_PM_CAP_ID = 8'h01; + parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF3_PM_CAP_VER_ID = 3'h3; + parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF3_TPHR_CAP_ENABLE = "FALSE"; + parameter VF3_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF3_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF4_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF4_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF4_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF4_PM_CAP_ID = 8'h01; + parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF4_PM_CAP_VER_ID = 3'h3; + parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF4_TPHR_CAP_ENABLE = "FALSE"; + parameter VF4_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF4_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF5_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF5_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF5_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF5_PM_CAP_ID = 8'h01; + parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF5_PM_CAP_VER_ID = 3'h3; + parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF5_TPHR_CAP_ENABLE = "FALSE"; + parameter VF5_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF5_TPHR_CAP_VER = 4'h1; + output CFGERRCOROUT; + output CFGERRFATALOUT; + output CFGERRNONFATALOUT; + output CFGEXTREADRECEIVED; + output CFGEXTWRITERECEIVED; + output CFGHOTRESETOUT; + output CFGINPUTUPDATEDONE; + output CFGINTERRUPTAOUTPUT; + output CFGINTERRUPTBOUTPUT; + output CFGINTERRUPTCOUTPUT; + output CFGINTERRUPTDOUTPUT; + output CFGINTERRUPTMSIFAIL; + output CFGINTERRUPTMSIMASKUPDATE; + output CFGINTERRUPTMSISENT; + output CFGINTERRUPTMSIXFAIL; + output CFGINTERRUPTMSIXSENT; + output CFGINTERRUPTSENT; + output CFGLOCALERROR; + output CFGLTRENABLE; + output CFGMCUPDATEDONE; + output CFGMGMTREADWRITEDONE; + output CFGMSGRECEIVED; + output CFGMSGTRANSMITDONE; + output CFGPERFUNCTIONUPDATEDONE; + output CFGPHYLINKDOWN; + output CFGPLSTATUSCHANGE; + output CFGPOWERSTATECHANGEINTERRUPT; + output CFGTPHSTTREADENABLE; + output CFGTPHSTTWRITEENABLE; + output DRPRDY; + output MAXISCQTLAST; + output MAXISCQTVALID; + output MAXISRCTLAST; + output MAXISRCTVALID; + output PCIERQSEQNUMVLD; + output PCIERQTAGVLD; + output PIPERX0POLARITY; + output PIPERX1POLARITY; + output PIPERX2POLARITY; + output PIPERX3POLARITY; + output PIPERX4POLARITY; + output PIPERX5POLARITY; + output PIPERX6POLARITY; + output PIPERX7POLARITY; + output PIPETX0COMPLIANCE; + output PIPETX0DATAVALID; + output PIPETX0ELECIDLE; + output PIPETX0STARTBLOCK; + output PIPETX1COMPLIANCE; + output PIPETX1DATAVALID; + output PIPETX1ELECIDLE; + output PIPETX1STARTBLOCK; + output PIPETX2COMPLIANCE; + output PIPETX2DATAVALID; + output PIPETX2ELECIDLE; + output PIPETX2STARTBLOCK; + output PIPETX3COMPLIANCE; + output PIPETX3DATAVALID; + output PIPETX3ELECIDLE; + output PIPETX3STARTBLOCK; + output PIPETX4COMPLIANCE; + output PIPETX4DATAVALID; + output PIPETX4ELECIDLE; + output PIPETX4STARTBLOCK; + output PIPETX5COMPLIANCE; + output PIPETX5DATAVALID; + output PIPETX5ELECIDLE; + output PIPETX5STARTBLOCK; + output PIPETX6COMPLIANCE; + output PIPETX6DATAVALID; + output PIPETX6ELECIDLE; + output PIPETX6STARTBLOCK; + output PIPETX7COMPLIANCE; + output PIPETX7DATAVALID; + output PIPETX7ELECIDLE; + output PIPETX7STARTBLOCK; + output PIPETXDEEMPH; + output PIPETXRCVRDET; + output PIPETXRESET; + output PIPETXSWING; + output PLEQINPROGRESS; + output [11:0] CFGFCCPLD; + output [11:0] CFGFCNPD; + output [11:0] CFGFCPD; + output [11:0] CFGVFSTATUS; + output [143:0] MIREPLAYRAMWRITEDATA; + output [143:0] MIREQUESTRAMWRITEDATA; + output [15:0] CFGPERFUNCSTATUSDATA; + output [15:0] DBGDATAOUT; + output [15:0] DRPDO; + output [17:0] CFGVFPOWERSTATE; + output [17:0] CFGVFTPHSTMODE; + output [1:0] CFGDPASUBSTATECHANGE; + output [1:0] CFGFLRINPROCESS; + output [1:0] CFGINTERRUPTMSIENABLE; + output [1:0] CFGINTERRUPTMSIXENABLE; + output [1:0] CFGINTERRUPTMSIXMASK; + output [1:0] CFGLINKPOWERSTATE; + output [1:0] CFGOBFFENABLE; + output [1:0] CFGPHYLINKSTATUS; + output [1:0] CFGRCBSTATUS; + output [1:0] CFGTPHREQUESTERENABLE; + output [1:0] MIREPLAYRAMREADENABLE; + output [1:0] MIREPLAYRAMWRITEENABLE; + output [1:0] PCIERQTAGAV; + output [1:0] PCIETFCNPDAV; + output [1:0] PCIETFCNPHAV; + output [1:0] PIPERX0EQCONTROL; + output [1:0] PIPERX1EQCONTROL; + output [1:0] PIPERX2EQCONTROL; + output [1:0] PIPERX3EQCONTROL; + output [1:0] PIPERX4EQCONTROL; + output [1:0] PIPERX5EQCONTROL; + output [1:0] PIPERX6EQCONTROL; + output [1:0] PIPERX7EQCONTROL; + output [1:0] PIPETX0CHARISK; + output [1:0] PIPETX0EQCONTROL; + output [1:0] PIPETX0POWERDOWN; + output [1:0] PIPETX0SYNCHEADER; + output [1:0] PIPETX1CHARISK; + output [1:0] PIPETX1EQCONTROL; + output [1:0] PIPETX1POWERDOWN; + output [1:0] PIPETX1SYNCHEADER; + output [1:0] PIPETX2CHARISK; + output [1:0] PIPETX2EQCONTROL; + output [1:0] PIPETX2POWERDOWN; + output [1:0] PIPETX2SYNCHEADER; + output [1:0] PIPETX3CHARISK; + output [1:0] PIPETX3EQCONTROL; + output [1:0] PIPETX3POWERDOWN; + output [1:0] PIPETX3SYNCHEADER; + output [1:0] PIPETX4CHARISK; + output [1:0] PIPETX4EQCONTROL; + output [1:0] PIPETX4POWERDOWN; + output [1:0] PIPETX4SYNCHEADER; + output [1:0] PIPETX5CHARISK; + output [1:0] PIPETX5EQCONTROL; + output [1:0] PIPETX5POWERDOWN; + output [1:0] PIPETX5SYNCHEADER; + output [1:0] PIPETX6CHARISK; + output [1:0] PIPETX6EQCONTROL; + output [1:0] PIPETX6POWERDOWN; + output [1:0] PIPETX6SYNCHEADER; + output [1:0] PIPETX7CHARISK; + output [1:0] PIPETX7EQCONTROL; + output [1:0] PIPETX7POWERDOWN; + output [1:0] PIPETX7SYNCHEADER; + output [1:0] PIPETXRATE; + output [1:0] PLEQPHASE; + output [255:0] MAXISCQTDATA; + output [255:0] MAXISRCTDATA; + output [2:0] CFGCURRENTSPEED; + output [2:0] CFGMAXPAYLOAD; + output [2:0] CFGMAXREADREQ; + output [2:0] CFGTPHFUNCTIONNUM; + output [2:0] PIPERX0EQPRESET; + output [2:0] PIPERX1EQPRESET; + output [2:0] PIPERX2EQPRESET; + output [2:0] PIPERX3EQPRESET; + output [2:0] PIPERX4EQPRESET; + output [2:0] PIPERX5EQPRESET; + output [2:0] PIPERX6EQPRESET; + output [2:0] PIPERX7EQPRESET; + output [2:0] PIPETXMARGIN; + output [31:0] CFGEXTWRITEDATA; + output [31:0] CFGINTERRUPTMSIDATA; + output [31:0] CFGMGMTREADDATA; + output [31:0] CFGTPHSTTWRITEDATA; + output [31:0] PIPETX0DATA; + output [31:0] PIPETX1DATA; + output [31:0] PIPETX2DATA; + output [31:0] PIPETX3DATA; + output [31:0] PIPETX4DATA; + output [31:0] PIPETX5DATA; + output [31:0] PIPETX6DATA; + output [31:0] PIPETX7DATA; + output [3:0] CFGEXTWRITEBYTEENABLE; + output [3:0] CFGNEGOTIATEDWIDTH; + output [3:0] CFGTPHSTTWRITEBYTEVALID; + output [3:0] MICOMPLETIONRAMREADENABLEL; + output [3:0] MICOMPLETIONRAMREADENABLEU; + output [3:0] MICOMPLETIONRAMWRITEENABLEL; + output [3:0] MICOMPLETIONRAMWRITEENABLEU; + output [3:0] MIREQUESTRAMREADENABLE; + output [3:0] MIREQUESTRAMWRITEENABLE; + output [3:0] PCIERQSEQNUM; + output [3:0] PIPERX0EQLPTXPRESET; + output [3:0] PIPERX1EQLPTXPRESET; + output [3:0] PIPERX2EQLPTXPRESET; + output [3:0] PIPERX3EQLPTXPRESET; + output [3:0] PIPERX4EQLPTXPRESET; + output [3:0] PIPERX5EQLPTXPRESET; + output [3:0] PIPERX6EQLPTXPRESET; + output [3:0] PIPERX7EQLPTXPRESET; + output [3:0] PIPETX0EQPRESET; + output [3:0] PIPETX1EQPRESET; + output [3:0] PIPETX2EQPRESET; + output [3:0] PIPETX3EQPRESET; + output [3:0] PIPETX4EQPRESET; + output [3:0] PIPETX5EQPRESET; + output [3:0] PIPETX6EQPRESET; + output [3:0] PIPETX7EQPRESET; + output [3:0] SAXISCCTREADY; + output [3:0] SAXISRQTREADY; + output [4:0] CFGMSGRECEIVEDTYPE; + output [4:0] CFGTPHSTTADDRESS; + output [5:0] CFGFUNCTIONPOWERSTATE; + output [5:0] CFGINTERRUPTMSIMMENABLE; + output [5:0] CFGINTERRUPTMSIVFENABLE; + output [5:0] CFGINTERRUPTMSIXVFENABLE; + output [5:0] CFGINTERRUPTMSIXVFMASK; + output [5:0] CFGLTSSMSTATE; + output [5:0] CFGTPHSTMODE; + output [5:0] CFGVFFLRINPROCESS; + output [5:0] CFGVFTPHREQUESTERENABLE; + output [5:0] PCIECQNPREQCOUNT; + output [5:0] PCIERQTAG; + output [5:0] PIPERX0EQLPLFFS; + output [5:0] PIPERX1EQLPLFFS; + output [5:0] PIPERX2EQLPLFFS; + output [5:0] PIPERX3EQLPLFFS; + output [5:0] PIPERX4EQLPLFFS; + output [5:0] PIPERX5EQLPLFFS; + output [5:0] PIPERX6EQLPLFFS; + output [5:0] PIPERX7EQLPLFFS; + output [5:0] PIPETX0EQDEEMPH; + output [5:0] PIPETX1EQDEEMPH; + output [5:0] PIPETX2EQDEEMPH; + output [5:0] PIPETX3EQDEEMPH; + output [5:0] PIPETX4EQDEEMPH; + output [5:0] PIPETX5EQDEEMPH; + output [5:0] PIPETX6EQDEEMPH; + output [5:0] PIPETX7EQDEEMPH; + output [71:0] MICOMPLETIONRAMWRITEDATAL; + output [71:0] MICOMPLETIONRAMWRITEDATAU; + output [74:0] MAXISRCTUSER; + output [7:0] CFGEXTFUNCTIONNUMBER; + output [7:0] CFGFCCPLH; + output [7:0] CFGFCNPH; + output [7:0] CFGFCPH; + output [7:0] CFGFUNCTIONSTATUS; + output [7:0] CFGMSGRECEIVEDDATA; + output [7:0] MAXISCQTKEEP; + output [7:0] MAXISRCTKEEP; + output [7:0] PLGEN3PCSRXSLIDE; + output [84:0] MAXISCQTUSER; + output [8:0] MIREPLAYRAMADDRESS; + output [8:0] MIREQUESTRAMREADADDRESSA; + output [8:0] MIREQUESTRAMREADADDRESSB; + output [8:0] MIREQUESTRAMWRITEADDRESSA; + output [8:0] MIREQUESTRAMWRITEADDRESSB; + output [9:0] CFGEXTREGISTERNUMBER; + output [9:0] MICOMPLETIONRAMREADADDRESSAL; + output [9:0] MICOMPLETIONRAMREADADDRESSAU; + output [9:0] MICOMPLETIONRAMREADADDRESSBL; + output [9:0] MICOMPLETIONRAMREADADDRESSBU; + output [9:0] MICOMPLETIONRAMWRITEADDRESSAL; + output [9:0] MICOMPLETIONRAMWRITEADDRESSAU; + output [9:0] MICOMPLETIONRAMWRITEADDRESSBL; + output [9:0] MICOMPLETIONRAMWRITEADDRESSBU; + input CFGCONFIGSPACEENABLE; + input CFGERRCORIN; + input CFGERRUNCORIN; + input CFGEXTREADDATAVALID; + input CFGHOTRESETIN; + input CFGINPUTUPDATEREQUEST; + input CFGINTERRUPTMSITPHPRESENT; + input CFGINTERRUPTMSIXINT; + input CFGLINKTRAININGENABLE; + input CFGMCUPDATEREQUEST; + input CFGMGMTREAD; + input CFGMGMTTYPE1CFGREGACCESS; + input CFGMGMTWRITE; + input CFGMSGTRANSMIT; + input CFGPERFUNCTIONOUTPUTREQUEST; + input CFGPOWERSTATECHANGEACK; + input CFGREQPMTRANSITIONL23READY; + input CFGTPHSTTREADDATAVALID; + input CORECLK; + input CORECLKMICOMPLETIONRAML; + input CORECLKMICOMPLETIONRAMU; + input CORECLKMIREPLAYRAM; + input CORECLKMIREQUESTRAM; + input DRPCLK; + input DRPEN; + input DRPWE; + input MGMTRESETN; + input MGMTSTICKYRESETN; + input PCIECQNPREQ; + input PIPECLK; + input PIPERESETN; + input PIPERX0DATAVALID; + input PIPERX0ELECIDLE; + input PIPERX0EQDONE; + input PIPERX0EQLPADAPTDONE; + input PIPERX0EQLPLFFSSEL; + input PIPERX0PHYSTATUS; + input PIPERX0STARTBLOCK; + input PIPERX0VALID; + input PIPERX1DATAVALID; + input PIPERX1ELECIDLE; + input PIPERX1EQDONE; + input PIPERX1EQLPADAPTDONE; + input PIPERX1EQLPLFFSSEL; + input PIPERX1PHYSTATUS; + input PIPERX1STARTBLOCK; + input PIPERX1VALID; + input PIPERX2DATAVALID; + input PIPERX2ELECIDLE; + input PIPERX2EQDONE; + input PIPERX2EQLPADAPTDONE; + input PIPERX2EQLPLFFSSEL; + input PIPERX2PHYSTATUS; + input PIPERX2STARTBLOCK; + input PIPERX2VALID; + input PIPERX3DATAVALID; + input PIPERX3ELECIDLE; + input PIPERX3EQDONE; + input PIPERX3EQLPADAPTDONE; + input PIPERX3EQLPLFFSSEL; + input PIPERX3PHYSTATUS; + input PIPERX3STARTBLOCK; + input PIPERX3VALID; + input PIPERX4DATAVALID; + input PIPERX4ELECIDLE; + input PIPERX4EQDONE; + input PIPERX4EQLPADAPTDONE; + input PIPERX4EQLPLFFSSEL; + input PIPERX4PHYSTATUS; + input PIPERX4STARTBLOCK; + input PIPERX4VALID; + input PIPERX5DATAVALID; + input PIPERX5ELECIDLE; + input PIPERX5EQDONE; + input PIPERX5EQLPADAPTDONE; + input PIPERX5EQLPLFFSSEL; + input PIPERX5PHYSTATUS; + input PIPERX5STARTBLOCK; + input PIPERX5VALID; + input PIPERX6DATAVALID; + input PIPERX6ELECIDLE; + input PIPERX6EQDONE; + input PIPERX6EQLPADAPTDONE; + input PIPERX6EQLPLFFSSEL; + input PIPERX6PHYSTATUS; + input PIPERX6STARTBLOCK; + input PIPERX6VALID; + input PIPERX7DATAVALID; + input PIPERX7ELECIDLE; + input PIPERX7EQDONE; + input PIPERX7EQLPADAPTDONE; + input PIPERX7EQLPLFFSSEL; + input PIPERX7PHYSTATUS; + input PIPERX7STARTBLOCK; + input PIPERX7VALID; + input PIPETX0EQDONE; + input PIPETX1EQDONE; + input PIPETX2EQDONE; + input PIPETX3EQDONE; + input PIPETX4EQDONE; + input PIPETX5EQDONE; + input PIPETX6EQDONE; + input PIPETX7EQDONE; + input PLDISABLESCRAMBLER; + input PLEQRESETEIEOSCOUNT; + input PLGEN3PCSDISABLE; + input RECCLK; + input RESETN; + input SAXISCCTLAST; + input SAXISCCTVALID; + input SAXISRQTLAST; + input SAXISRQTVALID; + input USERCLK; + input [10:0] DRPADDR; + input [143:0] MICOMPLETIONRAMREADDATA; + input [143:0] MIREPLAYRAMREADDATA; + input [143:0] MIREQUESTRAMREADDATA; + input [15:0] CFGDEVID; + input [15:0] CFGSUBSYSID; + input [15:0] CFGSUBSYSVENDID; + input [15:0] CFGVENDID; + input [15:0] DRPDI; + input [17:0] PIPERX0EQLPNEWTXCOEFFORPRESET; + input [17:0] PIPERX1EQLPNEWTXCOEFFORPRESET; + input [17:0] PIPERX2EQLPNEWTXCOEFFORPRESET; + input [17:0] PIPERX3EQLPNEWTXCOEFFORPRESET; + input [17:0] PIPERX4EQLPNEWTXCOEFFORPRESET; + input [17:0] PIPERX5EQLPNEWTXCOEFFORPRESET; + input [17:0] PIPERX6EQLPNEWTXCOEFFORPRESET; + input [17:0] PIPERX7EQLPNEWTXCOEFFORPRESET; + input [17:0] PIPETX0EQCOEFF; + input [17:0] PIPETX1EQCOEFF; + input [17:0] PIPETX2EQCOEFF; + input [17:0] PIPETX3EQCOEFF; + input [17:0] PIPETX4EQCOEFF; + input [17:0] PIPETX5EQCOEFF; + input [17:0] PIPETX6EQCOEFF; + input [17:0] PIPETX7EQCOEFF; + input [18:0] CFGMGMTADDR; + input [1:0] CFGFLRDONE; + input [1:0] CFGINTERRUPTMSITPHTYPE; + input [1:0] CFGINTERRUPTPENDING; + input [1:0] PIPERX0CHARISK; + input [1:0] PIPERX0SYNCHEADER; + input [1:0] PIPERX1CHARISK; + input [1:0] PIPERX1SYNCHEADER; + input [1:0] PIPERX2CHARISK; + input [1:0] PIPERX2SYNCHEADER; + input [1:0] PIPERX3CHARISK; + input [1:0] PIPERX3SYNCHEADER; + input [1:0] PIPERX4CHARISK; + input [1:0] PIPERX4SYNCHEADER; + input [1:0] PIPERX5CHARISK; + input [1:0] PIPERX5SYNCHEADER; + input [1:0] PIPERX6CHARISK; + input [1:0] PIPERX6SYNCHEADER; + input [1:0] PIPERX7CHARISK; + input [1:0] PIPERX7SYNCHEADER; + input [21:0] MAXISCQTREADY; + input [21:0] MAXISRCTREADY; + input [255:0] SAXISCCTDATA; + input [255:0] SAXISRQTDATA; + input [2:0] CFGDSFUNCTIONNUMBER; + input [2:0] CFGFCSEL; + input [2:0] CFGINTERRUPTMSIATTR; + input [2:0] CFGINTERRUPTMSIFUNCTIONNUMBER; + input [2:0] CFGMSGTRANSMITTYPE; + input [2:0] CFGPERFUNCSTATUSCONTROL; + input [2:0] CFGPERFUNCTIONNUMBER; + input [2:0] PIPERX0STATUS; + input [2:0] PIPERX1STATUS; + input [2:0] PIPERX2STATUS; + input [2:0] PIPERX3STATUS; + input [2:0] PIPERX4STATUS; + input [2:0] PIPERX5STATUS; + input [2:0] PIPERX6STATUS; + input [2:0] PIPERX7STATUS; + input [31:0] CFGEXTREADDATA; + input [31:0] CFGINTERRUPTMSIINT; + input [31:0] CFGINTERRUPTMSIXDATA; + input [31:0] CFGMGMTWRITEDATA; + input [31:0] CFGMSGTRANSMITDATA; + input [31:0] CFGTPHSTTREADDATA; + input [31:0] PIPERX0DATA; + input [31:0] PIPERX1DATA; + input [31:0] PIPERX2DATA; + input [31:0] PIPERX3DATA; + input [31:0] PIPERX4DATA; + input [31:0] PIPERX5DATA; + input [31:0] PIPERX6DATA; + input [31:0] PIPERX7DATA; + input [32:0] SAXISCCTUSER; + input [3:0] CFGINTERRUPTINT; + input [3:0] CFGINTERRUPTMSISELECT; + input [3:0] CFGMGMTBYTEENABLE; + input [4:0] CFGDSDEVICENUMBER; + input [59:0] SAXISRQTUSER; + input [5:0] CFGVFFLRDONE; + input [5:0] PIPEEQFS; + input [5:0] PIPEEQLF; + input [63:0] CFGDSN; + input [63:0] CFGINTERRUPTMSIPENDINGSTATUS; + input [63:0] CFGINTERRUPTMSIXADDRESS; + input [7:0] CFGDSBUSNUMBER; + input [7:0] CFGDSPORTNUMBER; + input [7:0] CFGREVID; + input [7:0] PLGEN3PCSRXSYNCDONE; + input [7:0] SAXISCCTKEEP; + input [7:0] SAXISRQTKEEP; + input [8:0] CFGINTERRUPTMSITPHSTTAG; +endmodule + +module PCIE_3_1 (...); + parameter ARI_CAP_ENABLE = "FALSE"; + parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE"; + parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE"; + parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE"; + parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE"; + parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000; + parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE"; + parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE"; + parameter AXISTEN_IF_RC_STRADDLE = "FALSE"; + parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE"; + parameter AXISTEN_IF_RQ_PARITY_CHK = "TRUE"; + parameter [1:0] AXISTEN_IF_WIDTH = 2'h2; + parameter CRM_CORE_CLK_FREQ_500 = "TRUE"; + parameter [1:0] CRM_USER_CLK_FREQ = 2'h2; + parameter DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE = "FALSE"; + parameter DEBUG_PL_DISABLE_EI_INFER_IN_L0 = "FALSE"; + parameter DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS = "FALSE"; + parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; + parameter [8:0] LL_ACK_TIMEOUT = 9'h000; + parameter LL_ACK_TIMEOUT_EN = "FALSE"; + parameter integer LL_ACK_TIMEOUT_FUNC = 0; + parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0000; + parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; + parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0000; + parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; + parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0000; + parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; + parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0000; + parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; + parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000; + parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; + parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; + parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0FA; + parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE"; + parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE"; + parameter [11:0] MCAP_CAP_NEXTPTR = 12'h000; + parameter MCAP_CONFIGURE_OVERRIDE = "FALSE"; + parameter MCAP_ENABLE = "FALSE"; + parameter MCAP_EOS_DESIGN_SWITCH = "FALSE"; + parameter [31:0] MCAP_FPGA_BITSTREAM_VERSION = 32'h00000000; + parameter MCAP_GATE_IO_ENABLE_DESIGN_SWITCH = "FALSE"; + parameter MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH = "FALSE"; + parameter MCAP_INPUT_GATE_DESIGN_SWITCH = "FALSE"; + parameter MCAP_INTERRUPT_ON_MCAP_EOS = "FALSE"; + parameter MCAP_INTERRUPT_ON_MCAP_ERROR = "FALSE"; + parameter [15:0] MCAP_VSEC_ID = 16'h0000; + parameter [11:0] MCAP_VSEC_LEN = 12'h02C; + parameter [3:0] MCAP_VSEC_REV = 4'h0; + parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; + parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; + parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [3:0] PF0_ARI_CAP_VER = 4'h1; + parameter [5:0] PF0_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_BAR0_CONTROL = 3'h4; + parameter [5:0] PF0_BAR1_APERTURE_SIZE = 6'h00; + parameter [2:0] PF0_BAR1_CONTROL = 3'h0; + parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR2_CONTROL = 3'h4; + parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR3_CONTROL = 3'h0; + parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR4_CONTROL = 3'h4; + parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR5_CONTROL = 3'h0; + parameter [7:0] PF0_BIST_REGISTER = 8'h00; + parameter [7:0] PF0_CAPABILITY_POINTER = 8'h50; + parameter [23:0] PF0_CLASS_CODE = 24'h000000; + parameter [15:0] PF0_DEVICE_ID = 16'h0000; + parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_ARI_FORWARD_ENABLE = "FALSE"; + parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE"; + parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE"; + parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0; + parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE"; + parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0; + parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0; + parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; + parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE"; + parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h000; + parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h00; + parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; + parameter [3:0] PF0_DPA_CAP_VER = 4'h1; + parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF0_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [7:0] PF0_INTERRUPT_LINE = 8'h00; + parameter [2:0] PF0_INTERRUPT_PIN = 3'h1; + parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7; + parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; + parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000; + parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000; + parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000; + parameter [3:0] PF0_LTR_CAP_VER = 4'h1; + parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF0_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF0_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00; + parameter PF0_MSI_CAP_PERVECMASKCAP = "FALSE"; + parameter [31:0] PF0_PB_CAP_DATA_REG_D0 = 32'h00000000; + parameter [31:0] PF0_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000; + parameter [31:0] PF0_PB_CAP_DATA_REG_D1 = 32'h00000000; + parameter [31:0] PF0_PB_CAP_DATA_REG_D3HOT = 32'h00000000; + parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h000; + parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; + parameter [3:0] PF0_PB_CAP_VER = 4'h1; + parameter [7:0] PF0_PM_CAP_ID = 8'h01; + parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00; + parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE"; + parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE"; + parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE"; + parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE"; + parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3; + parameter PF0_PM_CSR_NOSOFTRESET = "TRUE"; + parameter PF0_RBAR_CAP_ENABLE = "FALSE"; + parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h000; + parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h00000; + parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h00000; + parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h00000; + parameter [3:0] PF0_RBAR_CAP_VER = 4'h1; + parameter [2:0] PF0_RBAR_CONTROL_INDEX0 = 3'h0; + parameter [2:0] PF0_RBAR_CONTROL_INDEX1 = 3'h0; + parameter [2:0] PF0_RBAR_CONTROL_INDEX2 = 3'h0; + parameter [4:0] PF0_RBAR_CONTROL_SIZE0 = 5'h00; + parameter [4:0] PF0_RBAR_CONTROL_SIZE1 = 5'h00; + parameter [4:0] PF0_RBAR_CONTROL_SIZE2 = 5'h00; + parameter [2:0] PF0_RBAR_NUM = 3'h1; + parameter [7:0] PF0_REVISION_ID = 8'h00; + parameter [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR = 12'h000; + parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0; + parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0; + parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0000; + parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter PF0_TPHR_CAP_ENABLE = "FALSE"; + parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] PF0_TPHR_CAP_VER = 4'h1; + parameter PF0_VC_CAP_ENABLE = "FALSE"; + parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000; + parameter [3:0] PF0_VC_CAP_VER = 4'h1; + parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; + parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; + parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [5:0] PF1_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_BAR0_CONTROL = 3'h4; + parameter [5:0] PF1_BAR1_APERTURE_SIZE = 6'h00; + parameter [2:0] PF1_BAR1_CONTROL = 3'h0; + parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR2_CONTROL = 3'h4; + parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR3_CONTROL = 3'h0; + parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR4_CONTROL = 3'h4; + parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR5_CONTROL = 3'h0; + parameter [7:0] PF1_BIST_REGISTER = 8'h00; + parameter [7:0] PF1_CAPABILITY_POINTER = 8'h50; + parameter [23:0] PF1_CLASS_CODE = 24'h000000; + parameter [15:0] PF1_DEVICE_ID = 16'h0000; + parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h000; + parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h00; + parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; + parameter [3:0] PF1_DPA_CAP_VER = 4'h1; + parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF1_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [7:0] PF1_INTERRUPT_LINE = 8'h00; + parameter [2:0] PF1_INTERRUPT_PIN = 3'h1; + parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF1_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF1_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00; + parameter PF1_MSI_CAP_PERVECMASKCAP = "FALSE"; + parameter [31:0] PF1_PB_CAP_DATA_REG_D0 = 32'h00000000; + parameter [31:0] PF1_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000; + parameter [31:0] PF1_PB_CAP_DATA_REG_D1 = 32'h00000000; + parameter [31:0] PF1_PB_CAP_DATA_REG_D3HOT = 32'h00000000; + parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h000; + parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; + parameter [3:0] PF1_PB_CAP_VER = 4'h1; + parameter [7:0] PF1_PM_CAP_ID = 8'h01; + parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] PF1_PM_CAP_VER_ID = 3'h3; + parameter PF1_RBAR_CAP_ENABLE = "FALSE"; + parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h000; + parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h00000; + parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h00000; + parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h00000; + parameter [3:0] PF1_RBAR_CAP_VER = 4'h1; + parameter [2:0] PF1_RBAR_CONTROL_INDEX0 = 3'h0; + parameter [2:0] PF1_RBAR_CONTROL_INDEX1 = 3'h0; + parameter [2:0] PF1_RBAR_CONTROL_INDEX2 = 3'h0; + parameter [4:0] PF1_RBAR_CONTROL_SIZE0 = 5'h00; + parameter [4:0] PF1_RBAR_CONTROL_SIZE1 = 5'h00; + parameter [4:0] PF1_RBAR_CONTROL_SIZE2 = 5'h00; + parameter [2:0] PF1_RBAR_NUM = 3'h1; + parameter [7:0] PF1_REVISION_ID = 8'h00; + parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0; + parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0; + parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0000; + parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter PF1_TPHR_CAP_ENABLE = "FALSE"; + parameter PF1_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] PF1_TPHR_CAP_VER = 4'h1; + parameter PF2_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; + parameter PF2_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; + parameter [11:0] PF2_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF2_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF2_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [5:0] PF2_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_BAR0_CONTROL = 3'h4; + parameter [5:0] PF2_BAR1_APERTURE_SIZE = 6'h00; + parameter [2:0] PF2_BAR1_CONTROL = 3'h0; + parameter [4:0] PF2_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_BAR2_CONTROL = 3'h4; + parameter [4:0] PF2_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_BAR3_CONTROL = 3'h0; + parameter [4:0] PF2_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_BAR4_CONTROL = 3'h4; + parameter [4:0] PF2_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_BAR5_CONTROL = 3'h0; + parameter [7:0] PF2_BIST_REGISTER = 8'h00; + parameter [7:0] PF2_CAPABILITY_POINTER = 8'h50; + parameter [23:0] PF2_CLASS_CODE = 24'h000000; + parameter [15:0] PF2_DEVICE_ID = 16'h0000; + parameter [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF2_DPA_CAP_NEXTPTR = 12'h000; + parameter [4:0] PF2_DPA_CAP_SUB_STATE_CONTROL = 5'h00; + parameter PF2_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; + parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; + parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; + parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; + parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; + parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; + parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; + parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; + parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; + parameter [3:0] PF2_DPA_CAP_VER = 4'h1; + parameter [11:0] PF2_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF2_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [7:0] PF2_INTERRUPT_LINE = 8'h00; + parameter [2:0] PF2_INTERRUPT_PIN = 3'h1; + parameter [7:0] PF2_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF2_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF2_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF2_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF2_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF2_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF2_MSI_CAP_NEXTPTR = 8'h00; + parameter PF2_MSI_CAP_PERVECMASKCAP = "FALSE"; + parameter [31:0] PF2_PB_CAP_DATA_REG_D0 = 32'h00000000; + parameter [31:0] PF2_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000; + parameter [31:0] PF2_PB_CAP_DATA_REG_D1 = 32'h00000000; + parameter [31:0] PF2_PB_CAP_DATA_REG_D3HOT = 32'h00000000; + parameter [11:0] PF2_PB_CAP_NEXTPTR = 12'h000; + parameter PF2_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; + parameter [3:0] PF2_PB_CAP_VER = 4'h1; + parameter [7:0] PF2_PM_CAP_ID = 8'h01; + parameter [7:0] PF2_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] PF2_PM_CAP_VER_ID = 3'h3; + parameter PF2_RBAR_CAP_ENABLE = "FALSE"; + parameter [11:0] PF2_RBAR_CAP_NEXTPTR = 12'h000; + parameter [19:0] PF2_RBAR_CAP_SIZE0 = 20'h00000; + parameter [19:0] PF2_RBAR_CAP_SIZE1 = 20'h00000; + parameter [19:0] PF2_RBAR_CAP_SIZE2 = 20'h00000; + parameter [3:0] PF2_RBAR_CAP_VER = 4'h1; + parameter [2:0] PF2_RBAR_CONTROL_INDEX0 = 3'h0; + parameter [2:0] PF2_RBAR_CONTROL_INDEX1 = 3'h0; + parameter [2:0] PF2_RBAR_CONTROL_INDEX2 = 3'h0; + parameter [4:0] PF2_RBAR_CONTROL_SIZE0 = 5'h00; + parameter [4:0] PF2_RBAR_CONTROL_SIZE1 = 5'h00; + parameter [4:0] PF2_RBAR_CONTROL_SIZE2 = 5'h00; + parameter [2:0] PF2_RBAR_NUM = 3'h1; + parameter [7:0] PF2_REVISION_ID = 8'h00; + parameter [4:0] PF2_SRIOV_BAR0_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF2_SRIOV_BAR1_CONTROL = 3'h0; + parameter [4:0] PF2_SRIOV_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_SRIOV_BAR3_CONTROL = 3'h0; + parameter [4:0] PF2_SRIOV_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF2_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF2_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF2_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF2_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF2_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF2_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF2_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [15:0] PF2_SUBSYSTEM_ID = 16'h0000; + parameter PF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter PF2_TPHR_CAP_ENABLE = "FALSE"; + parameter PF2_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] PF2_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF2_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] PF2_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] PF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] PF2_TPHR_CAP_VER = 4'h1; + parameter PF3_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; + parameter PF3_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; + parameter [11:0] PF3_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF3_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF3_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [5:0] PF3_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_BAR0_CONTROL = 3'h4; + parameter [5:0] PF3_BAR1_APERTURE_SIZE = 6'h00; + parameter [2:0] PF3_BAR1_CONTROL = 3'h0; + parameter [4:0] PF3_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_BAR2_CONTROL = 3'h4; + parameter [4:0] PF3_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_BAR3_CONTROL = 3'h0; + parameter [4:0] PF3_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_BAR4_CONTROL = 3'h4; + parameter [4:0] PF3_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_BAR5_CONTROL = 3'h0; + parameter [7:0] PF3_BIST_REGISTER = 8'h00; + parameter [7:0] PF3_CAPABILITY_POINTER = 8'h50; + parameter [23:0] PF3_CLASS_CODE = 24'h000000; + parameter [15:0] PF3_DEVICE_ID = 16'h0000; + parameter [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF3_DPA_CAP_NEXTPTR = 12'h000; + parameter [4:0] PF3_DPA_CAP_SUB_STATE_CONTROL = 5'h00; + parameter PF3_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; + parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; + parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; + parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; + parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; + parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; + parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; + parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; + parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; + parameter [3:0] PF3_DPA_CAP_VER = 4'h1; + parameter [11:0] PF3_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF3_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [7:0] PF3_INTERRUPT_LINE = 8'h00; + parameter [2:0] PF3_INTERRUPT_PIN = 3'h1; + parameter [7:0] PF3_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF3_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF3_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF3_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF3_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF3_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF3_MSI_CAP_NEXTPTR = 8'h00; + parameter PF3_MSI_CAP_PERVECMASKCAP = "FALSE"; + parameter [31:0] PF3_PB_CAP_DATA_REG_D0 = 32'h00000000; + parameter [31:0] PF3_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000; + parameter [31:0] PF3_PB_CAP_DATA_REG_D1 = 32'h00000000; + parameter [31:0] PF3_PB_CAP_DATA_REG_D3HOT = 32'h00000000; + parameter [11:0] PF3_PB_CAP_NEXTPTR = 12'h000; + parameter PF3_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; + parameter [3:0] PF3_PB_CAP_VER = 4'h1; + parameter [7:0] PF3_PM_CAP_ID = 8'h01; + parameter [7:0] PF3_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] PF3_PM_CAP_VER_ID = 3'h3; + parameter PF3_RBAR_CAP_ENABLE = "FALSE"; + parameter [11:0] PF3_RBAR_CAP_NEXTPTR = 12'h000; + parameter [19:0] PF3_RBAR_CAP_SIZE0 = 20'h00000; + parameter [19:0] PF3_RBAR_CAP_SIZE1 = 20'h00000; + parameter [19:0] PF3_RBAR_CAP_SIZE2 = 20'h00000; + parameter [3:0] PF3_RBAR_CAP_VER = 4'h1; + parameter [2:0] PF3_RBAR_CONTROL_INDEX0 = 3'h0; + parameter [2:0] PF3_RBAR_CONTROL_INDEX1 = 3'h0; + parameter [2:0] PF3_RBAR_CONTROL_INDEX2 = 3'h0; + parameter [4:0] PF3_RBAR_CONTROL_SIZE0 = 5'h00; + parameter [4:0] PF3_RBAR_CONTROL_SIZE1 = 5'h00; + parameter [4:0] PF3_RBAR_CONTROL_SIZE2 = 5'h00; + parameter [2:0] PF3_RBAR_NUM = 3'h1; + parameter [7:0] PF3_REVISION_ID = 8'h00; + parameter [4:0] PF3_SRIOV_BAR0_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF3_SRIOV_BAR1_CONTROL = 3'h0; + parameter [4:0] PF3_SRIOV_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_SRIOV_BAR3_CONTROL = 3'h0; + parameter [4:0] PF3_SRIOV_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF3_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF3_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF3_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF3_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF3_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF3_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF3_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [15:0] PF3_SUBSYSTEM_ID = 16'h0000; + parameter PF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter PF3_TPHR_CAP_ENABLE = "FALSE"; + parameter PF3_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] PF3_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF3_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] PF3_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] PF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] PF3_TPHR_CAP_VER = 4'h1; + parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 = "FALSE"; + parameter PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 = "FALSE"; + parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE"; + parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE"; + parameter PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP = "TRUE"; + parameter PL_DISABLE_RETRAIN_ON_FRAMING_ERROR = "FALSE"; + parameter PL_DISABLE_SCRAMBLING = "FALSE"; + parameter PL_DISABLE_SYNC_HEADER_FRAMING_ERROR = "FALSE"; + parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE"; + parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE"; + parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE"; + parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02; + parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1; + parameter PL_EQ_BYPASS_PHASE23 = "FALSE"; + parameter [2:0] PL_EQ_DEFAULT_GEN3_RX_PRESET_HINT = 3'h3; + parameter [3:0] PL_EQ_DEFAULT_GEN3_TX_PRESET = 4'h4; + parameter PL_EQ_PHASE01_RX_ADAPT = "FALSE"; + parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE"; + parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h3F00; + parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4; + parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h8; + parameter integer PL_N_FTS_COMCLK_GEN1 = 255; + parameter integer PL_N_FTS_COMCLK_GEN2 = 255; + parameter integer PL_N_FTS_COMCLK_GEN3 = 255; + parameter integer PL_N_FTS_GEN1 = 255; + parameter integer PL_N_FTS_GEN2 = 255; + parameter integer PL_N_FTS_GEN3 = 255; + parameter PL_REPORT_ALL_PHY_ERRORS = "TRUE"; + parameter PL_SIM_FAST_LINK_TRAINING = "FALSE"; + parameter PL_UPSTREAM_FACING = "TRUE"; + parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h05DC; + parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h00000; + parameter PM_ENABLE_L23_ENTRY = "FALSE"; + parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE"; + parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000000; + parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h186A0; + parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0064; + parameter [31:0] SIM_JTAG_IDCODE = 32'h00000000; + parameter SIM_VERSION = "1.0"; + parameter integer SPARE_BIT0 = 0; + parameter integer SPARE_BIT1 = 0; + parameter integer SPARE_BIT2 = 0; + parameter integer SPARE_BIT3 = 0; + parameter integer SPARE_BIT4 = 0; + parameter integer SPARE_BIT5 = 0; + parameter integer SPARE_BIT6 = 0; + parameter integer SPARE_BIT7 = 0; + parameter integer SPARE_BIT8 = 0; + parameter [7:0] SPARE_BYTE0 = 8'h00; + parameter [7:0] SPARE_BYTE1 = 8'h00; + parameter [7:0] SPARE_BYTE2 = 8'h00; + parameter [7:0] SPARE_BYTE3 = 8'h00; + parameter [31:0] SPARE_WORD0 = 32'h00000000; + parameter [31:0] SPARE_WORD1 = 32'h00000000; + parameter [31:0] SPARE_WORD2 = 32'h00000000; + parameter [31:0] SPARE_WORD3 = 32'h00000000; + parameter SRIOV_CAP_ENABLE = "FALSE"; + parameter TL_COMPLETION_RAM_SIZE_16K = "TRUE"; + parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'hBEBC20; + parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h2FAF080; + parameter [11:0] TL_CREDITS_CD = 12'h3E0; + parameter [7:0] TL_CREDITS_CH = 8'h20; + parameter [11:0] TL_CREDITS_NPD = 12'h028; + parameter [7:0] TL_CREDITS_NPH = 8'h20; + parameter [11:0] TL_CREDITS_PD = 12'h198; + parameter [7:0] TL_CREDITS_PH = 8'h20; + parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "TRUE"; + parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; + parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; + parameter TL_LEGACY_MODE_ENABLE = "FALSE"; + parameter [1:0] TL_PF_ENABLE_REG = 2'h0; + parameter TL_TX_MUX_STRICT_PRIORITY = "TRUE"; + parameter TWO_LAYER_MODE_DLCMSM_ENABLE = "TRUE"; + parameter TWO_LAYER_MODE_ENABLE = "FALSE"; + parameter TWO_LAYER_MODE_WIDTH_256 = "TRUE"; + parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] VF0_CAPABILITY_POINTER = 8'h50; + parameter integer VF0_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF0_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF0_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF0_PM_CAP_ID = 8'h01; + parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF0_PM_CAP_VER_ID = 3'h3; + parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF0_TPHR_CAP_ENABLE = "FALSE"; + parameter VF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF0_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF1_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF1_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF1_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF1_PM_CAP_ID = 8'h01; + parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF1_PM_CAP_VER_ID = 3'h3; + parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF1_TPHR_CAP_ENABLE = "FALSE"; + parameter VF1_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF1_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF2_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF2_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF2_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF2_PM_CAP_ID = 8'h01; + parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF2_PM_CAP_VER_ID = 3'h3; + parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF2_TPHR_CAP_ENABLE = "FALSE"; + parameter VF2_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF2_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF3_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF3_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF3_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF3_PM_CAP_ID = 8'h01; + parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF3_PM_CAP_VER_ID = 3'h3; + parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF3_TPHR_CAP_ENABLE = "FALSE"; + parameter VF3_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF3_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF4_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF4_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF4_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF4_PM_CAP_ID = 8'h01; + parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF4_PM_CAP_VER_ID = 3'h3; + parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF4_TPHR_CAP_ENABLE = "FALSE"; + parameter VF4_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF4_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF5_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF5_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF5_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF5_PM_CAP_ID = 8'h01; + parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF5_PM_CAP_VER_ID = 3'h3; + parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF5_TPHR_CAP_ENABLE = "FALSE"; + parameter VF5_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF5_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF6_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF6_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF6_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF6_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF6_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF6_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF6_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF6_PM_CAP_ID = 8'h01; + parameter [7:0] VF6_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF6_PM_CAP_VER_ID = 3'h3; + parameter VF6_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF6_TPHR_CAP_ENABLE = "FALSE"; + parameter VF6_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF6_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF6_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF6_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF6_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF6_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF7_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF7_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF7_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF7_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF7_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF7_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF7_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF7_PM_CAP_ID = 8'h01; + parameter [7:0] VF7_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF7_PM_CAP_VER_ID = 3'h3; + parameter VF7_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF7_TPHR_CAP_ENABLE = "FALSE"; + parameter VF7_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF7_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF7_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF7_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF7_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF7_TPHR_CAP_VER = 4'h1; + output [2:0] CFGCURRENTSPEED; + output [3:0] CFGDPASUBSTATECHANGE; + output CFGERRCOROUT; + output CFGERRFATALOUT; + output CFGERRNONFATALOUT; + output [7:0] CFGEXTFUNCTIONNUMBER; + output CFGEXTREADRECEIVED; + output [9:0] CFGEXTREGISTERNUMBER; + output [3:0] CFGEXTWRITEBYTEENABLE; + output [31:0] CFGEXTWRITEDATA; + output CFGEXTWRITERECEIVED; + output [11:0] CFGFCCPLD; + output [7:0] CFGFCCPLH; + output [11:0] CFGFCNPD; + output [7:0] CFGFCNPH; + output [11:0] CFGFCPD; + output [7:0] CFGFCPH; + output [3:0] CFGFLRINPROCESS; + output [11:0] CFGFUNCTIONPOWERSTATE; + output [15:0] CFGFUNCTIONSTATUS; + output CFGHOTRESETOUT; + output [31:0] CFGINTERRUPTMSIDATA; + output [3:0] CFGINTERRUPTMSIENABLE; + output CFGINTERRUPTMSIFAIL; + output CFGINTERRUPTMSIMASKUPDATE; + output [11:0] CFGINTERRUPTMSIMMENABLE; + output CFGINTERRUPTMSISENT; + output [7:0] CFGINTERRUPTMSIVFENABLE; + output [3:0] CFGINTERRUPTMSIXENABLE; + output CFGINTERRUPTMSIXFAIL; + output [3:0] CFGINTERRUPTMSIXMASK; + output CFGINTERRUPTMSIXSENT; + output [7:0] CFGINTERRUPTMSIXVFENABLE; + output [7:0] CFGINTERRUPTMSIXVFMASK; + output CFGINTERRUPTSENT; + output [1:0] CFGLINKPOWERSTATE; + output CFGLOCALERROR; + output CFGLTRENABLE; + output [5:0] CFGLTSSMSTATE; + output [2:0] CFGMAXPAYLOAD; + output [2:0] CFGMAXREADREQ; + output [31:0] CFGMGMTREADDATA; + output CFGMGMTREADWRITEDONE; + output CFGMSGRECEIVED; + output [7:0] CFGMSGRECEIVEDDATA; + output [4:0] CFGMSGRECEIVEDTYPE; + output CFGMSGTRANSMITDONE; + output [3:0] CFGNEGOTIATEDWIDTH; + output [1:0] CFGOBFFENABLE; + output [15:0] CFGPERFUNCSTATUSDATA; + output CFGPERFUNCTIONUPDATEDONE; + output CFGPHYLINKDOWN; + output [1:0] CFGPHYLINKSTATUS; + output CFGPLSTATUSCHANGE; + output CFGPOWERSTATECHANGEINTERRUPT; + output [3:0] CFGRCBSTATUS; + output [3:0] CFGTPHFUNCTIONNUM; + output [3:0] CFGTPHREQUESTERENABLE; + output [11:0] CFGTPHSTMODE; + output [4:0] CFGTPHSTTADDRESS; + output CFGTPHSTTREADENABLE; + output [3:0] CFGTPHSTTWRITEBYTEVALID; + output [31:0] CFGTPHSTTWRITEDATA; + output CFGTPHSTTWRITEENABLE; + output [7:0] CFGVFFLRINPROCESS; + output [23:0] CFGVFPOWERSTATE; + output [15:0] CFGVFSTATUS; + output [7:0] CFGVFTPHREQUESTERENABLE; + output [23:0] CFGVFTPHSTMODE; + output CONFMCAPDESIGNSWITCH; + output CONFMCAPEOS; + output CONFMCAPINUSEBYPCIE; + output CONFREQREADY; + output [31:0] CONFRESPRDATA; + output CONFRESPVALID; + output [15:0] DBGDATAOUT; + output DBGMCAPCSB; + output [31:0] DBGMCAPDATA; + output DBGMCAPEOS; + output DBGMCAPERROR; + output DBGMCAPMODE; + output DBGMCAPRDATAVALID; + output DBGMCAPRDWRB; + output DBGMCAPRESET; + output DBGPLDATABLOCKRECEIVEDAFTEREDS; + output DBGPLGEN3FRAMINGERRORDETECTED; + output DBGPLGEN3SYNCHEADERERRORDETECTED; + output [7:0] DBGPLINFERREDRXELECTRICALIDLE; + output [15:0] DRPDO; + output DRPRDY; + output LL2LMMASTERTLPSENT0; + output LL2LMMASTERTLPSENT1; + output [3:0] LL2LMMASTERTLPSENTTLPID0; + output [3:0] LL2LMMASTERTLPSENTTLPID1; + output [255:0] LL2LMMAXISRXTDATA; + output [17:0] LL2LMMAXISRXTUSER; + output [7:0] LL2LMMAXISRXTVALID; + output [7:0] LL2LMSAXISTXTREADY; + output [255:0] MAXISCQTDATA; + output [7:0] MAXISCQTKEEP; + output MAXISCQTLAST; + output [84:0] MAXISCQTUSER; + output MAXISCQTVALID; + output [255:0] MAXISRCTDATA; + output [7:0] MAXISRCTKEEP; + output MAXISRCTLAST; + output [74:0] MAXISRCTUSER; + output MAXISRCTVALID; + output [9:0] MICOMPLETIONRAMREADADDRESSAL; + output [9:0] MICOMPLETIONRAMREADADDRESSAU; + output [9:0] MICOMPLETIONRAMREADADDRESSBL; + output [9:0] MICOMPLETIONRAMREADADDRESSBU; + output [3:0] MICOMPLETIONRAMREADENABLEL; + output [3:0] MICOMPLETIONRAMREADENABLEU; + output [9:0] MICOMPLETIONRAMWRITEADDRESSAL; + output [9:0] MICOMPLETIONRAMWRITEADDRESSAU; + output [9:0] MICOMPLETIONRAMWRITEADDRESSBL; + output [9:0] MICOMPLETIONRAMWRITEADDRESSBU; + output [71:0] MICOMPLETIONRAMWRITEDATAL; + output [71:0] MICOMPLETIONRAMWRITEDATAU; + output [3:0] MICOMPLETIONRAMWRITEENABLEL; + output [3:0] MICOMPLETIONRAMWRITEENABLEU; + output [8:0] MIREPLAYRAMADDRESS; + output [1:0] MIREPLAYRAMREADENABLE; + output [143:0] MIREPLAYRAMWRITEDATA; + output [1:0] MIREPLAYRAMWRITEENABLE; + output [8:0] MIREQUESTRAMREADADDRESSA; + output [8:0] MIREQUESTRAMREADADDRESSB; + output [3:0] MIREQUESTRAMREADENABLE; + output [8:0] MIREQUESTRAMWRITEADDRESSA; + output [8:0] MIREQUESTRAMWRITEADDRESSB; + output [143:0] MIREQUESTRAMWRITEDATA; + output [3:0] MIREQUESTRAMWRITEENABLE; + output [5:0] PCIECQNPREQCOUNT; + output PCIEPERST0B; + output PCIEPERST1B; + output [3:0] PCIERQSEQNUM; + output PCIERQSEQNUMVLD; + output [5:0] PCIERQTAG; + output [1:0] PCIERQTAGAV; + output PCIERQTAGVLD; + output [1:0] PCIETFCNPDAV; + output [1:0] PCIETFCNPHAV; + output [1:0] PIPERX0EQCONTROL; + output [5:0] PIPERX0EQLPLFFS; + output [3:0] PIPERX0EQLPTXPRESET; + output [2:0] PIPERX0EQPRESET; + output PIPERX0POLARITY; + output [1:0] PIPERX1EQCONTROL; + output [5:0] PIPERX1EQLPLFFS; + output [3:0] PIPERX1EQLPTXPRESET; + output [2:0] PIPERX1EQPRESET; + output PIPERX1POLARITY; + output [1:0] PIPERX2EQCONTROL; + output [5:0] PIPERX2EQLPLFFS; + output [3:0] PIPERX2EQLPTXPRESET; + output [2:0] PIPERX2EQPRESET; + output PIPERX2POLARITY; + output [1:0] PIPERX3EQCONTROL; + output [5:0] PIPERX3EQLPLFFS; + output [3:0] PIPERX3EQLPTXPRESET; + output [2:0] PIPERX3EQPRESET; + output PIPERX3POLARITY; + output [1:0] PIPERX4EQCONTROL; + output [5:0] PIPERX4EQLPLFFS; + output [3:0] PIPERX4EQLPTXPRESET; + output [2:0] PIPERX4EQPRESET; + output PIPERX4POLARITY; + output [1:0] PIPERX5EQCONTROL; + output [5:0] PIPERX5EQLPLFFS; + output [3:0] PIPERX5EQLPTXPRESET; + output [2:0] PIPERX5EQPRESET; + output PIPERX5POLARITY; + output [1:0] PIPERX6EQCONTROL; + output [5:0] PIPERX6EQLPLFFS; + output [3:0] PIPERX6EQLPTXPRESET; + output [2:0] PIPERX6EQPRESET; + output PIPERX6POLARITY; + output [1:0] PIPERX7EQCONTROL; + output [5:0] PIPERX7EQLPLFFS; + output [3:0] PIPERX7EQLPTXPRESET; + output [2:0] PIPERX7EQPRESET; + output PIPERX7POLARITY; + output [1:0] PIPETX0CHARISK; + output PIPETX0COMPLIANCE; + output [31:0] PIPETX0DATA; + output PIPETX0DATAVALID; + output PIPETX0DEEMPH; + output PIPETX0ELECIDLE; + output [1:0] PIPETX0EQCONTROL; + output [5:0] PIPETX0EQDEEMPH; + output [3:0] PIPETX0EQPRESET; + output [2:0] PIPETX0MARGIN; + output [1:0] PIPETX0POWERDOWN; + output [1:0] PIPETX0RATE; + output PIPETX0RCVRDET; + output PIPETX0RESET; + output PIPETX0STARTBLOCK; + output PIPETX0SWING; + output [1:0] PIPETX0SYNCHEADER; + output [1:0] PIPETX1CHARISK; + output PIPETX1COMPLIANCE; + output [31:0] PIPETX1DATA; + output PIPETX1DATAVALID; + output PIPETX1DEEMPH; + output PIPETX1ELECIDLE; + output [1:0] PIPETX1EQCONTROL; + output [5:0] PIPETX1EQDEEMPH; + output [3:0] PIPETX1EQPRESET; + output [2:0] PIPETX1MARGIN; + output [1:0] PIPETX1POWERDOWN; + output [1:0] PIPETX1RATE; + output PIPETX1RCVRDET; + output PIPETX1RESET; + output PIPETX1STARTBLOCK; + output PIPETX1SWING; + output [1:0] PIPETX1SYNCHEADER; + output [1:0] PIPETX2CHARISK; + output PIPETX2COMPLIANCE; + output [31:0] PIPETX2DATA; + output PIPETX2DATAVALID; + output PIPETX2DEEMPH; + output PIPETX2ELECIDLE; + output [1:0] PIPETX2EQCONTROL; + output [5:0] PIPETX2EQDEEMPH; + output [3:0] PIPETX2EQPRESET; + output [2:0] PIPETX2MARGIN; + output [1:0] PIPETX2POWERDOWN; + output [1:0] PIPETX2RATE; + output PIPETX2RCVRDET; + output PIPETX2RESET; + output PIPETX2STARTBLOCK; + output PIPETX2SWING; + output [1:0] PIPETX2SYNCHEADER; + output [1:0] PIPETX3CHARISK; + output PIPETX3COMPLIANCE; + output [31:0] PIPETX3DATA; + output PIPETX3DATAVALID; + output PIPETX3DEEMPH; + output PIPETX3ELECIDLE; + output [1:0] PIPETX3EQCONTROL; + output [5:0] PIPETX3EQDEEMPH; + output [3:0] PIPETX3EQPRESET; + output [2:0] PIPETX3MARGIN; + output [1:0] PIPETX3POWERDOWN; + output [1:0] PIPETX3RATE; + output PIPETX3RCVRDET; + output PIPETX3RESET; + output PIPETX3STARTBLOCK; + output PIPETX3SWING; + output [1:0] PIPETX3SYNCHEADER; + output [1:0] PIPETX4CHARISK; + output PIPETX4COMPLIANCE; + output [31:0] PIPETX4DATA; + output PIPETX4DATAVALID; + output PIPETX4DEEMPH; + output PIPETX4ELECIDLE; + output [1:0] PIPETX4EQCONTROL; + output [5:0] PIPETX4EQDEEMPH; + output [3:0] PIPETX4EQPRESET; + output [2:0] PIPETX4MARGIN; + output [1:0] PIPETX4POWERDOWN; + output [1:0] PIPETX4RATE; + output PIPETX4RCVRDET; + output PIPETX4RESET; + output PIPETX4STARTBLOCK; + output PIPETX4SWING; + output [1:0] PIPETX4SYNCHEADER; + output [1:0] PIPETX5CHARISK; + output PIPETX5COMPLIANCE; + output [31:0] PIPETX5DATA; + output PIPETX5DATAVALID; + output PIPETX5DEEMPH; + output PIPETX5ELECIDLE; + output [1:0] PIPETX5EQCONTROL; + output [5:0] PIPETX5EQDEEMPH; + output [3:0] PIPETX5EQPRESET; + output [2:0] PIPETX5MARGIN; + output [1:0] PIPETX5POWERDOWN; + output [1:0] PIPETX5RATE; + output PIPETX5RCVRDET; + output PIPETX5RESET; + output PIPETX5STARTBLOCK; + output PIPETX5SWING; + output [1:0] PIPETX5SYNCHEADER; + output [1:0] PIPETX6CHARISK; + output PIPETX6COMPLIANCE; + output [31:0] PIPETX6DATA; + output PIPETX6DATAVALID; + output PIPETX6DEEMPH; + output PIPETX6ELECIDLE; + output [1:0] PIPETX6EQCONTROL; + output [5:0] PIPETX6EQDEEMPH; + output [3:0] PIPETX6EQPRESET; + output [2:0] PIPETX6MARGIN; + output [1:0] PIPETX6POWERDOWN; + output [1:0] PIPETX6RATE; + output PIPETX6RCVRDET; + output PIPETX6RESET; + output PIPETX6STARTBLOCK; + output PIPETX6SWING; + output [1:0] PIPETX6SYNCHEADER; + output [1:0] PIPETX7CHARISK; + output PIPETX7COMPLIANCE; + output [31:0] PIPETX7DATA; + output PIPETX7DATAVALID; + output PIPETX7DEEMPH; + output PIPETX7ELECIDLE; + output [1:0] PIPETX7EQCONTROL; + output [5:0] PIPETX7EQDEEMPH; + output [3:0] PIPETX7EQPRESET; + output [2:0] PIPETX7MARGIN; + output [1:0] PIPETX7POWERDOWN; + output [1:0] PIPETX7RATE; + output PIPETX7RCVRDET; + output PIPETX7RESET; + output PIPETX7STARTBLOCK; + output PIPETX7SWING; + output [1:0] PIPETX7SYNCHEADER; + output PLEQINPROGRESS; + output [1:0] PLEQPHASE; + output [3:0] SAXISCCTREADY; + output [3:0] SAXISRQTREADY; + output [31:0] SPAREOUT; + input CFGCONFIGSPACEENABLE; + input [15:0] CFGDEVID; + input [7:0] CFGDSBUSNUMBER; + input [4:0] CFGDSDEVICENUMBER; + input [2:0] CFGDSFUNCTIONNUMBER; + input [63:0] CFGDSN; + input [7:0] CFGDSPORTNUMBER; + input CFGERRCORIN; + input CFGERRUNCORIN; + input [31:0] CFGEXTREADDATA; + input CFGEXTREADDATAVALID; + input [2:0] CFGFCSEL; + input [3:0] CFGFLRDONE; + input CFGHOTRESETIN; + input [3:0] CFGINTERRUPTINT; + input [2:0] CFGINTERRUPTMSIATTR; + input [3:0] CFGINTERRUPTMSIFUNCTIONNUMBER; + input [31:0] CFGINTERRUPTMSIINT; + input [31:0] CFGINTERRUPTMSIPENDINGSTATUS; + input CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE; + input [3:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM; + input [3:0] CFGINTERRUPTMSISELECT; + input CFGINTERRUPTMSITPHPRESENT; + input [8:0] CFGINTERRUPTMSITPHSTTAG; + input [1:0] CFGINTERRUPTMSITPHTYPE; + input [63:0] CFGINTERRUPTMSIXADDRESS; + input [31:0] CFGINTERRUPTMSIXDATA; + input CFGINTERRUPTMSIXINT; + input [3:0] CFGINTERRUPTPENDING; + input CFGLINKTRAININGENABLE; + input [18:0] CFGMGMTADDR; + input [3:0] CFGMGMTBYTEENABLE; + input CFGMGMTREAD; + input CFGMGMTTYPE1CFGREGACCESS; + input CFGMGMTWRITE; + input [31:0] CFGMGMTWRITEDATA; + input CFGMSGTRANSMIT; + input [31:0] CFGMSGTRANSMITDATA; + input [2:0] CFGMSGTRANSMITTYPE; + input [2:0] CFGPERFUNCSTATUSCONTROL; + input [3:0] CFGPERFUNCTIONNUMBER; + input CFGPERFUNCTIONOUTPUTREQUEST; + input CFGPOWERSTATECHANGEACK; + input CFGREQPMTRANSITIONL23READY; + input [7:0] CFGREVID; + input [15:0] CFGSUBSYSID; + input [15:0] CFGSUBSYSVENDID; + input [31:0] CFGTPHSTTREADDATA; + input CFGTPHSTTREADDATAVALID; + input [15:0] CFGVENDID; + input [7:0] CFGVFFLRDONE; + input CONFMCAPREQUESTBYCONF; + input [31:0] CONFREQDATA; + input [3:0] CONFREQREGNUM; + input [1:0] CONFREQTYPE; + input CONFREQVALID; + input CORECLK; + input CORECLKMICOMPLETIONRAML; + input CORECLKMICOMPLETIONRAMU; + input CORECLKMIREPLAYRAM; + input CORECLKMIREQUESTRAM; + input DBGCFGLOCALMGMTREGOVERRIDE; + input [3:0] DBGDATASEL; + input [9:0] DRPADDR; + input DRPCLK; + input [15:0] DRPDI; + input DRPEN; + input DRPWE; + input [13:0] LL2LMSAXISTXTUSER; + input LL2LMSAXISTXTVALID; + input [3:0] LL2LMTXTLPID0; + input [3:0] LL2LMTXTLPID1; + input [21:0] MAXISCQTREADY; + input [21:0] MAXISRCTREADY; + input MCAPCLK; + input MCAPPERST0B; + input MCAPPERST1B; + input MGMTRESETN; + input MGMTSTICKYRESETN; + input [143:0] MICOMPLETIONRAMREADDATA; + input [143:0] MIREPLAYRAMREADDATA; + input [143:0] MIREQUESTRAMREADDATA; + input PCIECQNPREQ; + input PIPECLK; + input [5:0] PIPEEQFS; + input [5:0] PIPEEQLF; + input PIPERESETN; + input [1:0] PIPERX0CHARISK; + input [31:0] PIPERX0DATA; + input PIPERX0DATAVALID; + input PIPERX0ELECIDLE; + input PIPERX0EQDONE; + input PIPERX0EQLPADAPTDONE; + input PIPERX0EQLPLFFSSEL; + input [17:0] PIPERX0EQLPNEWTXCOEFFORPRESET; + input PIPERX0PHYSTATUS; + input PIPERX0STARTBLOCK; + input [2:0] PIPERX0STATUS; + input [1:0] PIPERX0SYNCHEADER; + input PIPERX0VALID; + input [1:0] PIPERX1CHARISK; + input [31:0] PIPERX1DATA; + input PIPERX1DATAVALID; + input PIPERX1ELECIDLE; + input PIPERX1EQDONE; + input PIPERX1EQLPADAPTDONE; + input PIPERX1EQLPLFFSSEL; + input [17:0] PIPERX1EQLPNEWTXCOEFFORPRESET; + input PIPERX1PHYSTATUS; + input PIPERX1STARTBLOCK; + input [2:0] PIPERX1STATUS; + input [1:0] PIPERX1SYNCHEADER; + input PIPERX1VALID; + input [1:0] PIPERX2CHARISK; + input [31:0] PIPERX2DATA; + input PIPERX2DATAVALID; + input PIPERX2ELECIDLE; + input PIPERX2EQDONE; + input PIPERX2EQLPADAPTDONE; + input PIPERX2EQLPLFFSSEL; + input [17:0] PIPERX2EQLPNEWTXCOEFFORPRESET; + input PIPERX2PHYSTATUS; + input PIPERX2STARTBLOCK; + input [2:0] PIPERX2STATUS; + input [1:0] PIPERX2SYNCHEADER; + input PIPERX2VALID; + input [1:0] PIPERX3CHARISK; + input [31:0] PIPERX3DATA; + input PIPERX3DATAVALID; + input PIPERX3ELECIDLE; + input PIPERX3EQDONE; + input PIPERX3EQLPADAPTDONE; + input PIPERX3EQLPLFFSSEL; + input [17:0] PIPERX3EQLPNEWTXCOEFFORPRESET; + input PIPERX3PHYSTATUS; + input PIPERX3STARTBLOCK; + input [2:0] PIPERX3STATUS; + input [1:0] PIPERX3SYNCHEADER; + input PIPERX3VALID; + input [1:0] PIPERX4CHARISK; + input [31:0] PIPERX4DATA; + input PIPERX4DATAVALID; + input PIPERX4ELECIDLE; + input PIPERX4EQDONE; + input PIPERX4EQLPADAPTDONE; + input PIPERX4EQLPLFFSSEL; + input [17:0] PIPERX4EQLPNEWTXCOEFFORPRESET; + input PIPERX4PHYSTATUS; + input PIPERX4STARTBLOCK; + input [2:0] PIPERX4STATUS; + input [1:0] PIPERX4SYNCHEADER; + input PIPERX4VALID; + input [1:0] PIPERX5CHARISK; + input [31:0] PIPERX5DATA; + input PIPERX5DATAVALID; + input PIPERX5ELECIDLE; + input PIPERX5EQDONE; + input PIPERX5EQLPADAPTDONE; + input PIPERX5EQLPLFFSSEL; + input [17:0] PIPERX5EQLPNEWTXCOEFFORPRESET; + input PIPERX5PHYSTATUS; + input PIPERX5STARTBLOCK; + input [2:0] PIPERX5STATUS; + input [1:0] PIPERX5SYNCHEADER; + input PIPERX5VALID; + input [1:0] PIPERX6CHARISK; + input [31:0] PIPERX6DATA; + input PIPERX6DATAVALID; + input PIPERX6ELECIDLE; + input PIPERX6EQDONE; + input PIPERX6EQLPADAPTDONE; + input PIPERX6EQLPLFFSSEL; + input [17:0] PIPERX6EQLPNEWTXCOEFFORPRESET; + input PIPERX6PHYSTATUS; + input PIPERX6STARTBLOCK; + input [2:0] PIPERX6STATUS; + input [1:0] PIPERX6SYNCHEADER; + input PIPERX6VALID; + input [1:0] PIPERX7CHARISK; + input [31:0] PIPERX7DATA; + input PIPERX7DATAVALID; + input PIPERX7ELECIDLE; + input PIPERX7EQDONE; + input PIPERX7EQLPADAPTDONE; + input PIPERX7EQLPLFFSSEL; + input [17:0] PIPERX7EQLPNEWTXCOEFFORPRESET; + input PIPERX7PHYSTATUS; + input PIPERX7STARTBLOCK; + input [2:0] PIPERX7STATUS; + input [1:0] PIPERX7SYNCHEADER; + input PIPERX7VALID; + input [17:0] PIPETX0EQCOEFF; + input PIPETX0EQDONE; + input [17:0] PIPETX1EQCOEFF; + input PIPETX1EQDONE; + input [17:0] PIPETX2EQCOEFF; + input PIPETX2EQDONE; + input [17:0] PIPETX3EQCOEFF; + input PIPETX3EQDONE; + input [17:0] PIPETX4EQCOEFF; + input PIPETX4EQDONE; + input [17:0] PIPETX5EQCOEFF; + input PIPETX5EQDONE; + input [17:0] PIPETX6EQCOEFF; + input PIPETX6EQDONE; + input [17:0] PIPETX7EQCOEFF; + input PIPETX7EQDONE; + input PLEQRESETEIEOSCOUNT; + input PLGEN2UPSTREAMPREFERDEEMPH; + input RESETN; + input [255:0] SAXISCCTDATA; + input [7:0] SAXISCCTKEEP; + input SAXISCCTLAST; + input [32:0] SAXISCCTUSER; + input SAXISCCTVALID; + input [255:0] SAXISRQTDATA; + input [7:0] SAXISRQTKEEP; + input SAXISRQTLAST; + input [59:0] SAXISRQTUSER; + input SAXISRQTVALID; + input [31:0] SPAREIN; + input USERCLK; +endmodule + +module PCIE40E4 (...); + parameter ARI_CAP_ENABLE = "FALSE"; + parameter AUTO_FLR_RESPONSE = "FALSE"; + parameter [1:0] AXISTEN_IF_CC_ALIGNMENT_MODE = 2'h0; + parameter [23:0] AXISTEN_IF_COMPL_TIMEOUT_REG0 = 24'hBEBC20; + parameter [27:0] AXISTEN_IF_COMPL_TIMEOUT_REG1 = 28'h2FAF080; + parameter [1:0] AXISTEN_IF_CQ_ALIGNMENT_MODE = 2'h0; + parameter AXISTEN_IF_CQ_EN_POISONED_MEM_WR = "FALSE"; + parameter AXISTEN_IF_ENABLE_256_TAGS = "FALSE"; + parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE"; + parameter AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = "FALSE"; + parameter AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK = "TRUE"; + parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000; + parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE"; + parameter AXISTEN_IF_EXT_512 = "FALSE"; + parameter AXISTEN_IF_EXT_512_CC_STRADDLE = "FALSE"; + parameter AXISTEN_IF_EXT_512_CQ_STRADDLE = "FALSE"; + parameter AXISTEN_IF_EXT_512_RC_STRADDLE = "FALSE"; + parameter AXISTEN_IF_EXT_512_RQ_STRADDLE = "FALSE"; + parameter AXISTEN_IF_LEGACY_MODE_ENABLE = "FALSE"; + parameter AXISTEN_IF_MSIX_FROM_RAM_PIPELINE = "FALSE"; + parameter AXISTEN_IF_MSIX_RX_PARITY_EN = "TRUE"; + parameter AXISTEN_IF_MSIX_TO_RAM_PIPELINE = "FALSE"; + parameter [1:0] AXISTEN_IF_RC_ALIGNMENT_MODE = 2'h0; + parameter AXISTEN_IF_RC_STRADDLE = "FALSE"; + parameter [1:0] AXISTEN_IF_RQ_ALIGNMENT_MODE = 2'h0; + parameter AXISTEN_IF_RX_PARITY_EN = "TRUE"; + parameter AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT = "FALSE"; + parameter AXISTEN_IF_TX_PARITY_EN = "TRUE"; + parameter [1:0] AXISTEN_IF_WIDTH = 2'h2; + parameter CFG_BYPASS_MODE_ENABLE = "FALSE"; + parameter CRM_CORE_CLK_FREQ_500 = "TRUE"; + parameter [1:0] CRM_USER_CLK_FREQ = 2'h2; + parameter [15:0] DEBUG_AXI4ST_SPARE = 16'h0000; + parameter [7:0] DEBUG_AXIST_DISABLE_FEATURE_BIT = 8'h00; + parameter [3:0] DEBUG_CAR_SPARE = 4'h0; + parameter [15:0] DEBUG_CFG_SPARE = 16'h0000; + parameter [15:0] DEBUG_LL_SPARE = 16'h0000; + parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR = "FALSE"; + parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR = "FALSE"; + parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR = "FALSE"; + parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL = "FALSE"; + parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW = "FALSE"; + parameter DEBUG_PL_DISABLE_SCRAMBLING = "FALSE"; + parameter DEBUG_PL_SIM_RESET_LFSR = "FALSE"; + parameter [15:0] DEBUG_PL_SPARE = 16'h0000; + parameter DEBUG_TL_DISABLE_FC_TIMEOUT = "FALSE"; + parameter DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS = "FALSE"; + parameter [15:0] DEBUG_TL_SPARE = 16'h0000; + parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; + parameter DSN_CAP_ENABLE = "FALSE"; + parameter EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; + parameter HEADER_TYPE_OVERRIDE = "FALSE"; + parameter IS_SWITCH_PORT = "FALSE"; + parameter LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; + parameter [8:0] LL_ACK_TIMEOUT = 9'h000; + parameter LL_ACK_TIMEOUT_EN = "FALSE"; + parameter integer LL_ACK_TIMEOUT_FUNC = 0; + parameter LL_DISABLE_SCHED_TX_NAK = "FALSE"; + parameter LL_REPLAY_FROM_RAM_PIPELINE = "FALSE"; + parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000; + parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; + parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; + parameter LL_REPLAY_TO_RAM_PIPELINE = "FALSE"; + parameter LL_RX_TLP_PARITY_GEN = "TRUE"; + parameter LL_TX_TLP_PARITY_CHK = "TRUE"; + parameter [15:0] LL_USER_SPARE = 16'h0000; + parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h250; + parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE"; + parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE"; + parameter [11:0] MCAP_CAP_NEXTPTR = 12'h000; + parameter MCAP_CONFIGURE_OVERRIDE = "FALSE"; + parameter MCAP_ENABLE = "FALSE"; + parameter MCAP_EOS_DESIGN_SWITCH = "FALSE"; + parameter [31:0] MCAP_FPGA_BITSTREAM_VERSION = 32'h00000000; + parameter MCAP_GATE_IO_ENABLE_DESIGN_SWITCH = "FALSE"; + parameter MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH = "FALSE"; + parameter MCAP_INPUT_GATE_DESIGN_SWITCH = "FALSE"; + parameter MCAP_INTERRUPT_ON_MCAP_EOS = "FALSE"; + parameter MCAP_INTERRUPT_ON_MCAP_ERROR = "FALSE"; + parameter [15:0] MCAP_VSEC_ID = 16'h0000; + parameter [11:0] MCAP_VSEC_LEN = 12'h02C; + parameter [3:0] MCAP_VSEC_REV = 4'h0; + parameter PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE = "FALSE"; + parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [3:0] PF0_ARI_CAP_VER = 4'h1; + parameter [5:0] PF0_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_BAR0_CONTROL = 3'h4; + parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF0_BAR1_CONTROL = 3'h0; + parameter [5:0] PF0_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_BAR2_CONTROL = 3'h4; + parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR3_CONTROL = 3'h0; + parameter [5:0] PF0_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_BAR4_CONTROL = 3'h4; + parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR5_CONTROL = 3'h0; + parameter [7:0] PF0_CAPABILITY_POINTER = 8'h80; + parameter [23:0] PF0_CLASS_CODE = 24'h000000; + parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_ARI_FORWARD_ENABLE = "FALSE"; + parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE"; + parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE"; + parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0; + parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE"; + parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0; + parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0; + parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; + parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE"; + parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF0_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [2:0] PF0_INTERRUPT_PIN = 3'h1; + parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4 = 7; + parameter [0:0] PF0_LINK_CONTROL_RCB = 1'h0; + parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; + parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000; + parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000; + parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000; + parameter [3:0] PF0_LTR_CAP_VER = 4'h1; + parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF0_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF0_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [5:0] PF0_MSIX_VECTOR_COUNT = 6'h04; + parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00; + parameter PF0_MSI_CAP_PERVECMASKCAP = "FALSE"; + parameter [7:0] PF0_PCIE_CAP_NEXTPTR = 8'h00; + parameter [7:0] PF0_PM_CAP_ID = 8'h01; + parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00; + parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE"; + parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE"; + parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE"; + parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE"; + parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3; + parameter PF0_PM_CSR_NOSOFTRESET = "TRUE"; + parameter [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR = 12'h000; + parameter PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; + parameter [5:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0; + parameter [5:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0; + parameter [5:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter PF0_TPHR_CAP_ENABLE = "FALSE"; + parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] PF0_TPHR_CAP_VER = 4'h1; + parameter PF0_VC_CAP_ENABLE = "FALSE"; + parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000; + parameter [3:0] PF0_VC_CAP_VER = 4'h1; + parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [5:0] PF1_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_BAR0_CONTROL = 3'h4; + parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF1_BAR1_CONTROL = 3'h0; + parameter [5:0] PF1_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_BAR2_CONTROL = 3'h4; + parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR3_CONTROL = 3'h0; + parameter [5:0] PF1_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_BAR4_CONTROL = 3'h4; + parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR5_CONTROL = 3'h0; + parameter [7:0] PF1_CAPABILITY_POINTER = 8'h80; + parameter [23:0] PF1_CLASS_CODE = 24'h000000; + parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF1_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [2:0] PF1_INTERRUPT_PIN = 3'h1; + parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF1_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF1_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00; + parameter PF1_MSI_CAP_PERVECMASKCAP = "FALSE"; + parameter [7:0] PF1_PCIE_CAP_NEXTPTR = 8'h00; + parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00; + parameter PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; + parameter [5:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0; + parameter [5:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0; + parameter [5:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [11:0] PF2_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF2_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF2_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [5:0] PF2_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_BAR0_CONTROL = 3'h4; + parameter [4:0] PF2_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF2_BAR1_CONTROL = 3'h0; + parameter [5:0] PF2_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_BAR2_CONTROL = 3'h4; + parameter [4:0] PF2_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_BAR3_CONTROL = 3'h0; + parameter [5:0] PF2_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_BAR4_CONTROL = 3'h4; + parameter [4:0] PF2_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_BAR5_CONTROL = 3'h0; + parameter [7:0] PF2_CAPABILITY_POINTER = 8'h80; + parameter [23:0] PF2_CLASS_CODE = 24'h000000; + parameter [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF2_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF2_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [2:0] PF2_INTERRUPT_PIN = 3'h1; + parameter [7:0] PF2_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF2_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF2_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF2_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF2_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF2_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF2_MSI_CAP_NEXTPTR = 8'h00; + parameter PF2_MSI_CAP_PERVECMASKCAP = "FALSE"; + parameter [7:0] PF2_PCIE_CAP_NEXTPTR = 8'h00; + parameter [7:0] PF2_PM_CAP_NEXTPTR = 8'h00; + parameter PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; + parameter [5:0] PF2_SRIOV_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF2_SRIOV_BAR1_CONTROL = 3'h0; + parameter [5:0] PF2_SRIOV_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_SRIOV_BAR3_CONTROL = 3'h0; + parameter [5:0] PF2_SRIOV_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF2_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF2_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF2_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF2_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF2_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF2_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF2_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [11:0] PF2_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF2_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [11:0] PF3_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF3_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF3_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [5:0] PF3_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_BAR0_CONTROL = 3'h4; + parameter [4:0] PF3_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF3_BAR1_CONTROL = 3'h0; + parameter [5:0] PF3_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_BAR2_CONTROL = 3'h4; + parameter [4:0] PF3_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_BAR3_CONTROL = 3'h0; + parameter [5:0] PF3_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_BAR4_CONTROL = 3'h4; + parameter [4:0] PF3_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_BAR5_CONTROL = 3'h0; + parameter [7:0] PF3_CAPABILITY_POINTER = 8'h80; + parameter [23:0] PF3_CLASS_CODE = 24'h000000; + parameter [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF3_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF3_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [2:0] PF3_INTERRUPT_PIN = 3'h1; + parameter [7:0] PF3_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF3_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF3_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF3_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF3_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF3_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF3_MSI_CAP_NEXTPTR = 8'h00; + parameter PF3_MSI_CAP_PERVECMASKCAP = "FALSE"; + parameter [7:0] PF3_PCIE_CAP_NEXTPTR = 8'h00; + parameter [7:0] PF3_PM_CAP_NEXTPTR = 8'h00; + parameter PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; + parameter [5:0] PF3_SRIOV_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF3_SRIOV_BAR1_CONTROL = 3'h0; + parameter [5:0] PF3_SRIOV_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_SRIOV_BAR3_CONTROL = 3'h0; + parameter [5:0] PF3_SRIOV_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF3_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF3_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF3_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF3_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF3_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF3_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF3_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [11:0] PF3_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF3_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter PL_CFG_STATE_ROBUSTNESS_ENABLE = "TRUE"; + parameter PL_DEEMPH_SOURCE_SELECT = "TRUE"; + parameter PL_DESKEW_ON_SKIP_IN_GEN12 = "FALSE"; + parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 = "FALSE"; + parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4 = "FALSE"; + parameter PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 = "FALSE"; + parameter PL_DISABLE_DC_BALANCE = "FALSE"; + parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE"; + parameter PL_DISABLE_LANE_REVERSAL = "FALSE"; + parameter [1:0] PL_DISABLE_LFSR_UPDATE_ON_SKP = 2'h0; + parameter PL_DISABLE_RETRAIN_ON_EB_ERROR = "FALSE"; + parameter PL_DISABLE_RETRAIN_ON_FRAMING_ERROR = "FALSE"; + parameter [15:0] PL_DISABLE_RETRAIN_ON_SPECIFIC_FRAMING_ERROR = 16'h0000; + parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE"; + parameter [1:0] PL_EQ_ADAPT_DISABLE_COEFF_CHECK = 2'h0; + parameter [1:0] PL_EQ_ADAPT_DISABLE_PRESET_CHECK = 2'h0; + parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02; + parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1; + parameter [1:0] PL_EQ_BYPASS_PHASE23 = 2'h0; + parameter [5:0] PL_EQ_DEFAULT_RX_PRESET_HINT = 6'h33; + parameter [7:0] PL_EQ_DEFAULT_TX_PRESET = 8'h44; + parameter PL_EQ_DISABLE_MISMATCH_CHECK = "TRUE"; + parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE0 = 2'h0; + parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE1 = 2'h0; + parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE"; + parameter PL_EQ_TX_8G_EQ_TS2_ENABLE = "FALSE"; + parameter PL_EXIT_LOOPBACK_ON_EI_ENTRY = "TRUE"; + parameter PL_INFER_EI_DISABLE_LPBK_ACTIVE = "TRUE"; + parameter PL_INFER_EI_DISABLE_REC_RC = "FALSE"; + parameter PL_INFER_EI_DISABLE_REC_SPD = "FALSE"; + parameter [31:0] PL_LANE0_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE10_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE11_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE12_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE13_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE14_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE15_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE1_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE2_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE3_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE4_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE5_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE6_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE7_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE8_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE9_EQ_CONTROL = 32'h00003F00; + parameter [3:0] PL_LINK_CAP_MAX_LINK_SPEED = 4'h4; + parameter [4:0] PL_LINK_CAP_MAX_LINK_WIDTH = 5'h08; + parameter integer PL_N_FTS = 255; + parameter PL_QUIESCE_GUARANTEE_DISABLE = "FALSE"; + parameter PL_REDO_EQ_SOURCE_SELECT = "TRUE"; + parameter [7:0] PL_REPORT_ALL_PHY_ERRORS = 8'h00; + parameter [1:0] PL_RX_ADAPT_TIMER_CLWS_CLOBBER_TX_TS = 2'h0; + parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN3 = 4'h0; + parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN4 = 4'h0; + parameter [1:0] PL_RX_ADAPT_TIMER_RRL_CLOBBER_TX_TS = 2'h0; + parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN3 = 4'h0; + parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN4 = 4'h0; + parameter [1:0] PL_RX_L0S_EXIT_TO_RECOVERY = 2'h0; + parameter [1:0] PL_SIM_FAST_LINK_TRAINING = 2'h0; + parameter PL_SRIS_ENABLE = "FALSE"; + parameter [6:0] PL_SRIS_SKPOS_GEN_SPD_VEC = 7'h00; + parameter [6:0] PL_SRIS_SKPOS_REC_SPD_VEC = 7'h00; + parameter PL_UPSTREAM_FACING = "TRUE"; + parameter [15:0] PL_USER_SPARE = 16'h0000; + parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h1500; + parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h003E8; + parameter PM_ENABLE_L23_ENTRY = "FALSE"; + parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE"; + parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000100; + parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h00000; + parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0100; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter [31:0] SIM_JTAG_IDCODE = 32'h00000000; + parameter SIM_VERSION = "1.0"; + parameter SPARE_BIT0 = "FALSE"; + parameter integer SPARE_BIT1 = 0; + parameter integer SPARE_BIT2 = 0; + parameter SPARE_BIT3 = "FALSE"; + parameter integer SPARE_BIT4 = 0; + parameter integer SPARE_BIT5 = 0; + parameter integer SPARE_BIT6 = 0; + parameter integer SPARE_BIT7 = 0; + parameter integer SPARE_BIT8 = 0; + parameter [7:0] SPARE_BYTE0 = 8'h00; + parameter [7:0] SPARE_BYTE1 = 8'h00; + parameter [7:0] SPARE_BYTE2 = 8'h00; + parameter [7:0] SPARE_BYTE3 = 8'h00; + parameter [31:0] SPARE_WORD0 = 32'h00000000; + parameter [31:0] SPARE_WORD1 = 32'h00000000; + parameter [31:0] SPARE_WORD2 = 32'h00000000; + parameter [31:0] SPARE_WORD3 = 32'h00000000; + parameter [3:0] SRIOV_CAP_ENABLE = 4'h0; + parameter TL2CFG_IF_PARITY_CHK = "TRUE"; + parameter [1:0] TL_COMPLETION_RAM_NUM_TLPS = 2'h0; + parameter [1:0] TL_COMPLETION_RAM_SIZE = 2'h1; + parameter [11:0] TL_CREDITS_CD = 12'h000; + parameter [7:0] TL_CREDITS_CH = 8'h00; + parameter [11:0] TL_CREDITS_NPD = 12'h004; + parameter [7:0] TL_CREDITS_NPH = 8'h20; + parameter [11:0] TL_CREDITS_PD = 12'h0E0; + parameter [7:0] TL_CREDITS_PH = 8'h20; + parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TIME = 5'h02; + parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT = 5'h08; + parameter [1:0] TL_PF_ENABLE_REG = 2'h0; + parameter [0:0] TL_POSTED_RAM_SIZE = 1'h0; + parameter TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE = "FALSE"; + parameter TL_RX_COMPLETION_TO_RAM_READ_PIPELINE = "FALSE"; + parameter TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE = "FALSE"; + parameter TL_RX_POSTED_FROM_RAM_READ_PIPELINE = "FALSE"; + parameter TL_RX_POSTED_TO_RAM_READ_PIPELINE = "FALSE"; + parameter TL_RX_POSTED_TO_RAM_WRITE_PIPELINE = "FALSE"; + parameter TL_TX_MUX_STRICT_PRIORITY = "TRUE"; + parameter TL_TX_TLP_STRADDLE_ENABLE = "FALSE"; + parameter TL_TX_TLP_TERMINATE_PARITY = "FALSE"; + parameter [15:0] TL_USER_SPARE = 16'h0000; + parameter TPH_FROM_RAM_PIPELINE = "FALSE"; + parameter TPH_TO_RAM_PIPELINE = "FALSE"; + parameter [7:0] VF0_CAPABILITY_POINTER = 8'h80; + parameter [11:0] VFG0_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] VFG0_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer VFG0_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VFG0_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VFG0_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VFG0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VFG0_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [7:0] VFG0_PCIE_CAP_NEXTPTR = 8'h00; + parameter [11:0] VFG0_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VFG0_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [11:0] VFG1_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] VFG1_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer VFG1_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VFG1_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VFG1_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VFG1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VFG1_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [7:0] VFG1_PCIE_CAP_NEXTPTR = 8'h00; + parameter [11:0] VFG1_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VFG1_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [11:0] VFG2_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] VFG2_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer VFG2_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VFG2_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VFG2_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VFG2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VFG2_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [7:0] VFG2_PCIE_CAP_NEXTPTR = 8'h00; + parameter [11:0] VFG2_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VFG2_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [11:0] VFG3_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] VFG3_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer VFG3_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VFG3_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VFG3_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VFG3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VFG3_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [7:0] VFG3_PCIE_CAP_NEXTPTR = 8'h00; + parameter [11:0] VFG3_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VFG3_TPHR_CAP_ST_MODE_SEL = 3'h0; + output [7:0] AXIUSEROUT; + output [7:0] CFGBUSNUMBER; + output [1:0] CFGCURRENTSPEED; + output CFGERRCOROUT; + output CFGERRFATALOUT; + output CFGERRNONFATALOUT; + output [7:0] CFGEXTFUNCTIONNUMBER; + output CFGEXTREADRECEIVED; + output [9:0] CFGEXTREGISTERNUMBER; + output [3:0] CFGEXTWRITEBYTEENABLE; + output [31:0] CFGEXTWRITEDATA; + output CFGEXTWRITERECEIVED; + output [11:0] CFGFCCPLD; + output [7:0] CFGFCCPLH; + output [11:0] CFGFCNPD; + output [7:0] CFGFCNPH; + output [11:0] CFGFCPD; + output [7:0] CFGFCPH; + output [3:0] CFGFLRINPROCESS; + output [11:0] CFGFUNCTIONPOWERSTATE; + output [15:0] CFGFUNCTIONSTATUS; + output CFGHOTRESETOUT; + output [31:0] CFGINTERRUPTMSIDATA; + output [3:0] CFGINTERRUPTMSIENABLE; + output CFGINTERRUPTMSIFAIL; + output CFGINTERRUPTMSIMASKUPDATE; + output [11:0] CFGINTERRUPTMSIMMENABLE; + output CFGINTERRUPTMSISENT; + output [3:0] CFGINTERRUPTMSIXENABLE; + output [3:0] CFGINTERRUPTMSIXMASK; + output CFGINTERRUPTMSIXVECPENDINGSTATUS; + output CFGINTERRUPTSENT; + output [1:0] CFGLINKPOWERSTATE; + output [4:0] CFGLOCALERROROUT; + output CFGLOCALERRORVALID; + output CFGLTRENABLE; + output [5:0] CFGLTSSMSTATE; + output [1:0] CFGMAXPAYLOAD; + output [2:0] CFGMAXREADREQ; + output [31:0] CFGMGMTREADDATA; + output CFGMGMTREADWRITEDONE; + output CFGMSGRECEIVED; + output [7:0] CFGMSGRECEIVEDDATA; + output [4:0] CFGMSGRECEIVEDTYPE; + output CFGMSGTRANSMITDONE; + output [12:0] CFGMSIXRAMADDRESS; + output CFGMSIXRAMREADENABLE; + output [3:0] CFGMSIXRAMWRITEBYTEENABLE; + output [35:0] CFGMSIXRAMWRITEDATA; + output [2:0] CFGNEGOTIATEDWIDTH; + output [1:0] CFGOBFFENABLE; + output CFGPHYLINKDOWN; + output [1:0] CFGPHYLINKSTATUS; + output CFGPLSTATUSCHANGE; + output CFGPOWERSTATECHANGEINTERRUPT; + output [3:0] CFGRCBSTATUS; + output [1:0] CFGRXPMSTATE; + output [11:0] CFGTPHRAMADDRESS; + output CFGTPHRAMREADENABLE; + output [3:0] CFGTPHRAMWRITEBYTEENABLE; + output [35:0] CFGTPHRAMWRITEDATA; + output [3:0] CFGTPHREQUESTERENABLE; + output [11:0] CFGTPHSTMODE; + output [1:0] CFGTXPMSTATE; + output CONFMCAPDESIGNSWITCH; + output CONFMCAPEOS; + output CONFMCAPINUSEBYPCIE; + output CONFREQREADY; + output [31:0] CONFRESPRDATA; + output CONFRESPVALID; + output [31:0] DBGCTRL0OUT; + output [31:0] DBGCTRL1OUT; + output [255:0] DBGDATA0OUT; + output [255:0] DBGDATA1OUT; + output [15:0] DRPDO; + output DRPRDY; + output [255:0] MAXISCQTDATA; + output [7:0] MAXISCQTKEEP; + output MAXISCQTLAST; + output [87:0] MAXISCQTUSER; + output MAXISCQTVALID; + output [255:0] MAXISRCTDATA; + output [7:0] MAXISRCTKEEP; + output MAXISRCTLAST; + output [74:0] MAXISRCTUSER; + output MAXISRCTVALID; + output [8:0] MIREPLAYRAMADDRESS0; + output [8:0] MIREPLAYRAMADDRESS1; + output MIREPLAYRAMREADENABLE0; + output MIREPLAYRAMREADENABLE1; + output [127:0] MIREPLAYRAMWRITEDATA0; + output [127:0] MIREPLAYRAMWRITEDATA1; + output MIREPLAYRAMWRITEENABLE0; + output MIREPLAYRAMWRITEENABLE1; + output [8:0] MIRXCOMPLETIONRAMREADADDRESS0; + output [8:0] MIRXCOMPLETIONRAMREADADDRESS1; + output [1:0] MIRXCOMPLETIONRAMREADENABLE0; + output [1:0] MIRXCOMPLETIONRAMREADENABLE1; + output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS0; + output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS1; + output [143:0] MIRXCOMPLETIONRAMWRITEDATA0; + output [143:0] MIRXCOMPLETIONRAMWRITEDATA1; + output [1:0] MIRXCOMPLETIONRAMWRITEENABLE0; + output [1:0] MIRXCOMPLETIONRAMWRITEENABLE1; + output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS0; + output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS1; + output MIRXPOSTEDREQUESTRAMREADENABLE0; + output MIRXPOSTEDREQUESTRAMREADENABLE1; + output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS0; + output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS1; + output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA0; + output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA1; + output MIRXPOSTEDREQUESTRAMWRITEENABLE0; + output MIRXPOSTEDREQUESTRAMWRITEENABLE1; + output [5:0] PCIECQNPREQCOUNT; + output PCIEPERST0B; + output PCIEPERST1B; + output [5:0] PCIERQSEQNUM0; + output [5:0] PCIERQSEQNUM1; + output PCIERQSEQNUMVLD0; + output PCIERQSEQNUMVLD1; + output [7:0] PCIERQTAG0; + output [7:0] PCIERQTAG1; + output [3:0] PCIERQTAGAV; + output PCIERQTAGVLD0; + output PCIERQTAGVLD1; + output [3:0] PCIETFCNPDAV; + output [3:0] PCIETFCNPHAV; + output [1:0] PIPERX00EQCONTROL; + output PIPERX00POLARITY; + output [1:0] PIPERX01EQCONTROL; + output PIPERX01POLARITY; + output [1:0] PIPERX02EQCONTROL; + output PIPERX02POLARITY; + output [1:0] PIPERX03EQCONTROL; + output PIPERX03POLARITY; + output [1:0] PIPERX04EQCONTROL; + output PIPERX04POLARITY; + output [1:0] PIPERX05EQCONTROL; + output PIPERX05POLARITY; + output [1:0] PIPERX06EQCONTROL; + output PIPERX06POLARITY; + output [1:0] PIPERX07EQCONTROL; + output PIPERX07POLARITY; + output [1:0] PIPERX08EQCONTROL; + output PIPERX08POLARITY; + output [1:0] PIPERX09EQCONTROL; + output PIPERX09POLARITY; + output [1:0] PIPERX10EQCONTROL; + output PIPERX10POLARITY; + output [1:0] PIPERX11EQCONTROL; + output PIPERX11POLARITY; + output [1:0] PIPERX12EQCONTROL; + output PIPERX12POLARITY; + output [1:0] PIPERX13EQCONTROL; + output PIPERX13POLARITY; + output [1:0] PIPERX14EQCONTROL; + output PIPERX14POLARITY; + output [1:0] PIPERX15EQCONTROL; + output PIPERX15POLARITY; + output [5:0] PIPERXEQLPLFFS; + output [3:0] PIPERXEQLPTXPRESET; + output [1:0] PIPETX00CHARISK; + output PIPETX00COMPLIANCE; + output [31:0] PIPETX00DATA; + output PIPETX00DATAVALID; + output PIPETX00ELECIDLE; + output [1:0] PIPETX00EQCONTROL; + output [5:0] PIPETX00EQDEEMPH; + output [1:0] PIPETX00POWERDOWN; + output PIPETX00STARTBLOCK; + output [1:0] PIPETX00SYNCHEADER; + output [1:0] PIPETX01CHARISK; + output PIPETX01COMPLIANCE; + output [31:0] PIPETX01DATA; + output PIPETX01DATAVALID; + output PIPETX01ELECIDLE; + output [1:0] PIPETX01EQCONTROL; + output [5:0] PIPETX01EQDEEMPH; + output [1:0] PIPETX01POWERDOWN; + output PIPETX01STARTBLOCK; + output [1:0] PIPETX01SYNCHEADER; + output [1:0] PIPETX02CHARISK; + output PIPETX02COMPLIANCE; + output [31:0] PIPETX02DATA; + output PIPETX02DATAVALID; + output PIPETX02ELECIDLE; + output [1:0] PIPETX02EQCONTROL; + output [5:0] PIPETX02EQDEEMPH; + output [1:0] PIPETX02POWERDOWN; + output PIPETX02STARTBLOCK; + output [1:0] PIPETX02SYNCHEADER; + output [1:0] PIPETX03CHARISK; + output PIPETX03COMPLIANCE; + output [31:0] PIPETX03DATA; + output PIPETX03DATAVALID; + output PIPETX03ELECIDLE; + output [1:0] PIPETX03EQCONTROL; + output [5:0] PIPETX03EQDEEMPH; + output [1:0] PIPETX03POWERDOWN; + output PIPETX03STARTBLOCK; + output [1:0] PIPETX03SYNCHEADER; + output [1:0] PIPETX04CHARISK; + output PIPETX04COMPLIANCE; + output [31:0] PIPETX04DATA; + output PIPETX04DATAVALID; + output PIPETX04ELECIDLE; + output [1:0] PIPETX04EQCONTROL; + output [5:0] PIPETX04EQDEEMPH; + output [1:0] PIPETX04POWERDOWN; + output PIPETX04STARTBLOCK; + output [1:0] PIPETX04SYNCHEADER; + output [1:0] PIPETX05CHARISK; + output PIPETX05COMPLIANCE; + output [31:0] PIPETX05DATA; + output PIPETX05DATAVALID; + output PIPETX05ELECIDLE; + output [1:0] PIPETX05EQCONTROL; + output [5:0] PIPETX05EQDEEMPH; + output [1:0] PIPETX05POWERDOWN; + output PIPETX05STARTBLOCK; + output [1:0] PIPETX05SYNCHEADER; + output [1:0] PIPETX06CHARISK; + output PIPETX06COMPLIANCE; + output [31:0] PIPETX06DATA; + output PIPETX06DATAVALID; + output PIPETX06ELECIDLE; + output [1:0] PIPETX06EQCONTROL; + output [5:0] PIPETX06EQDEEMPH; + output [1:0] PIPETX06POWERDOWN; + output PIPETX06STARTBLOCK; + output [1:0] PIPETX06SYNCHEADER; + output [1:0] PIPETX07CHARISK; + output PIPETX07COMPLIANCE; + output [31:0] PIPETX07DATA; + output PIPETX07DATAVALID; + output PIPETX07ELECIDLE; + output [1:0] PIPETX07EQCONTROL; + output [5:0] PIPETX07EQDEEMPH; + output [1:0] PIPETX07POWERDOWN; + output PIPETX07STARTBLOCK; + output [1:0] PIPETX07SYNCHEADER; + output [1:0] PIPETX08CHARISK; + output PIPETX08COMPLIANCE; + output [31:0] PIPETX08DATA; + output PIPETX08DATAVALID; + output PIPETX08ELECIDLE; + output [1:0] PIPETX08EQCONTROL; + output [5:0] PIPETX08EQDEEMPH; + output [1:0] PIPETX08POWERDOWN; + output PIPETX08STARTBLOCK; + output [1:0] PIPETX08SYNCHEADER; + output [1:0] PIPETX09CHARISK; + output PIPETX09COMPLIANCE; + output [31:0] PIPETX09DATA; + output PIPETX09DATAVALID; + output PIPETX09ELECIDLE; + output [1:0] PIPETX09EQCONTROL; + output [5:0] PIPETX09EQDEEMPH; + output [1:0] PIPETX09POWERDOWN; + output PIPETX09STARTBLOCK; + output [1:0] PIPETX09SYNCHEADER; + output [1:0] PIPETX10CHARISK; + output PIPETX10COMPLIANCE; + output [31:0] PIPETX10DATA; + output PIPETX10DATAVALID; + output PIPETX10ELECIDLE; + output [1:0] PIPETX10EQCONTROL; + output [5:0] PIPETX10EQDEEMPH; + output [1:0] PIPETX10POWERDOWN; + output PIPETX10STARTBLOCK; + output [1:0] PIPETX10SYNCHEADER; + output [1:0] PIPETX11CHARISK; + output PIPETX11COMPLIANCE; + output [31:0] PIPETX11DATA; + output PIPETX11DATAVALID; + output PIPETX11ELECIDLE; + output [1:0] PIPETX11EQCONTROL; + output [5:0] PIPETX11EQDEEMPH; + output [1:0] PIPETX11POWERDOWN; + output PIPETX11STARTBLOCK; + output [1:0] PIPETX11SYNCHEADER; + output [1:0] PIPETX12CHARISK; + output PIPETX12COMPLIANCE; + output [31:0] PIPETX12DATA; + output PIPETX12DATAVALID; + output PIPETX12ELECIDLE; + output [1:0] PIPETX12EQCONTROL; + output [5:0] PIPETX12EQDEEMPH; + output [1:0] PIPETX12POWERDOWN; + output PIPETX12STARTBLOCK; + output [1:0] PIPETX12SYNCHEADER; + output [1:0] PIPETX13CHARISK; + output PIPETX13COMPLIANCE; + output [31:0] PIPETX13DATA; + output PIPETX13DATAVALID; + output PIPETX13ELECIDLE; + output [1:0] PIPETX13EQCONTROL; + output [5:0] PIPETX13EQDEEMPH; + output [1:0] PIPETX13POWERDOWN; + output PIPETX13STARTBLOCK; + output [1:0] PIPETX13SYNCHEADER; + output [1:0] PIPETX14CHARISK; + output PIPETX14COMPLIANCE; + output [31:0] PIPETX14DATA; + output PIPETX14DATAVALID; + output PIPETX14ELECIDLE; + output [1:0] PIPETX14EQCONTROL; + output [5:0] PIPETX14EQDEEMPH; + output [1:0] PIPETX14POWERDOWN; + output PIPETX14STARTBLOCK; + output [1:0] PIPETX14SYNCHEADER; + output [1:0] PIPETX15CHARISK; + output PIPETX15COMPLIANCE; + output [31:0] PIPETX15DATA; + output PIPETX15DATAVALID; + output PIPETX15ELECIDLE; + output [1:0] PIPETX15EQCONTROL; + output [5:0] PIPETX15EQDEEMPH; + output [1:0] PIPETX15POWERDOWN; + output PIPETX15STARTBLOCK; + output [1:0] PIPETX15SYNCHEADER; + output PIPETXDEEMPH; + output [2:0] PIPETXMARGIN; + output [1:0] PIPETXRATE; + output PIPETXRCVRDET; + output PIPETXRESET; + output PIPETXSWING; + output PLEQINPROGRESS; + output [1:0] PLEQPHASE; + output PLGEN34EQMISMATCH; + output [3:0] SAXISCCTREADY; + output [3:0] SAXISRQTREADY; + output [31:0] USERSPAREOUT; + input [7:0] AXIUSERIN; + input CFGCONFIGSPACEENABLE; + input [15:0] CFGDEVIDPF0; + input [15:0] CFGDEVIDPF1; + input [15:0] CFGDEVIDPF2; + input [15:0] CFGDEVIDPF3; + input [7:0] CFGDSBUSNUMBER; + input [4:0] CFGDSDEVICENUMBER; + input [2:0] CFGDSFUNCTIONNUMBER; + input [63:0] CFGDSN; + input [7:0] CFGDSPORTNUMBER; + input CFGERRCORIN; + input CFGERRUNCORIN; + input [31:0] CFGEXTREADDATA; + input CFGEXTREADDATAVALID; + input [2:0] CFGFCSEL; + input [3:0] CFGFLRDONE; + input CFGHOTRESETIN; + input [3:0] CFGINTERRUPTINT; + input [2:0] CFGINTERRUPTMSIATTR; + input [7:0] CFGINTERRUPTMSIFUNCTIONNUMBER; + input [31:0] CFGINTERRUPTMSIINT; + input [31:0] CFGINTERRUPTMSIPENDINGSTATUS; + input CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE; + input [1:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM; + input [1:0] CFGINTERRUPTMSISELECT; + input CFGINTERRUPTMSITPHPRESENT; + input [7:0] CFGINTERRUPTMSITPHSTTAG; + input [1:0] CFGINTERRUPTMSITPHTYPE; + input [63:0] CFGINTERRUPTMSIXADDRESS; + input [31:0] CFGINTERRUPTMSIXDATA; + input CFGINTERRUPTMSIXINT; + input [1:0] CFGINTERRUPTMSIXVECPENDING; + input [3:0] CFGINTERRUPTPENDING; + input CFGLINKTRAININGENABLE; + input [9:0] CFGMGMTADDR; + input [3:0] CFGMGMTBYTEENABLE; + input CFGMGMTDEBUGACCESS; + input [7:0] CFGMGMTFUNCTIONNUMBER; + input CFGMGMTREAD; + input CFGMGMTWRITE; + input [31:0] CFGMGMTWRITEDATA; + input CFGMSGTRANSMIT; + input [31:0] CFGMSGTRANSMITDATA; + input [2:0] CFGMSGTRANSMITTYPE; + input [35:0] CFGMSIXRAMREADDATA; + input CFGPMASPML1ENTRYREJECT; + input CFGPMASPMTXL0SENTRYDISABLE; + input CFGPOWERSTATECHANGEACK; + input CFGREQPMTRANSITIONL23READY; + input [7:0] CFGREVIDPF0; + input [7:0] CFGREVIDPF1; + input [7:0] CFGREVIDPF2; + input [7:0] CFGREVIDPF3; + input [15:0] CFGSUBSYSIDPF0; + input [15:0] CFGSUBSYSIDPF1; + input [15:0] CFGSUBSYSIDPF2; + input [15:0] CFGSUBSYSIDPF3; + input [15:0] CFGSUBSYSVENDID; + input [35:0] CFGTPHRAMREADDATA; + input [15:0] CFGVENDID; + input CFGVFFLRDONE; + input [7:0] CFGVFFLRFUNCNUM; + input CONFMCAPREQUESTBYCONF; + input [31:0] CONFREQDATA; + input [3:0] CONFREQREGNUM; + input [1:0] CONFREQTYPE; + input CONFREQVALID; + input CORECLK; + input CORECLKMIREPLAYRAM0; + input CORECLKMIREPLAYRAM1; + input CORECLKMIRXCOMPLETIONRAM0; + input CORECLKMIRXCOMPLETIONRAM1; + input CORECLKMIRXPOSTEDREQUESTRAM0; + input CORECLKMIRXPOSTEDREQUESTRAM1; + input [5:0] DBGSEL0; + input [5:0] DBGSEL1; + input [9:0] DRPADDR; + input DRPCLK; + input [15:0] DRPDI; + input DRPEN; + input DRPWE; + input [21:0] MAXISCQTREADY; + input [21:0] MAXISRCTREADY; + input MCAPCLK; + input MCAPPERST0B; + input MCAPPERST1B; + input MGMTRESETN; + input MGMTSTICKYRESETN; + input [5:0] MIREPLAYRAMERRCOR; + input [5:0] MIREPLAYRAMERRUNCOR; + input [127:0] MIREPLAYRAMREADDATA0; + input [127:0] MIREPLAYRAMREADDATA1; + input [11:0] MIRXCOMPLETIONRAMERRCOR; + input [11:0] MIRXCOMPLETIONRAMERRUNCOR; + input [143:0] MIRXCOMPLETIONRAMREADDATA0; + input [143:0] MIRXCOMPLETIONRAMREADDATA1; + input [5:0] MIRXPOSTEDREQUESTRAMERRCOR; + input [5:0] MIRXPOSTEDREQUESTRAMERRUNCOR; + input [143:0] MIRXPOSTEDREQUESTRAMREADDATA0; + input [143:0] MIRXPOSTEDREQUESTRAMREADDATA1; + input [1:0] PCIECOMPLDELIVERED; + input [7:0] PCIECOMPLDELIVEREDTAG0; + input [7:0] PCIECOMPLDELIVEREDTAG1; + input [1:0] PCIECQNPREQ; + input PCIECQNPUSERCREDITRCVD; + input PCIECQPIPELINEEMPTY; + input PCIEPOSTEDREQDELIVERED; + input PIPECLK; + input PIPECLKEN; + input [5:0] PIPEEQFS; + input [5:0] PIPEEQLF; + input PIPERESETN; + input [1:0] PIPERX00CHARISK; + input [31:0] PIPERX00DATA; + input PIPERX00DATAVALID; + input PIPERX00ELECIDLE; + input PIPERX00EQDONE; + input PIPERX00EQLPADAPTDONE; + input PIPERX00EQLPLFFSSEL; + input [17:0] PIPERX00EQLPNEWTXCOEFFORPRESET; + input PIPERX00PHYSTATUS; + input [1:0] PIPERX00STARTBLOCK; + input [2:0] PIPERX00STATUS; + input [1:0] PIPERX00SYNCHEADER; + input PIPERX00VALID; + input [1:0] PIPERX01CHARISK; + input [31:0] PIPERX01DATA; + input PIPERX01DATAVALID; + input PIPERX01ELECIDLE; + input PIPERX01EQDONE; + input PIPERX01EQLPADAPTDONE; + input PIPERX01EQLPLFFSSEL; + input [17:0] PIPERX01EQLPNEWTXCOEFFORPRESET; + input PIPERX01PHYSTATUS; + input [1:0] PIPERX01STARTBLOCK; + input [2:0] PIPERX01STATUS; + input [1:0] PIPERX01SYNCHEADER; + input PIPERX01VALID; + input [1:0] PIPERX02CHARISK; + input [31:0] PIPERX02DATA; + input PIPERX02DATAVALID; + input PIPERX02ELECIDLE; + input PIPERX02EQDONE; + input PIPERX02EQLPADAPTDONE; + input PIPERX02EQLPLFFSSEL; + input [17:0] PIPERX02EQLPNEWTXCOEFFORPRESET; + input PIPERX02PHYSTATUS; + input [1:0] PIPERX02STARTBLOCK; + input [2:0] PIPERX02STATUS; + input [1:0] PIPERX02SYNCHEADER; + input PIPERX02VALID; + input [1:0] PIPERX03CHARISK; + input [31:0] PIPERX03DATA; + input PIPERX03DATAVALID; + input PIPERX03ELECIDLE; + input PIPERX03EQDONE; + input PIPERX03EQLPADAPTDONE; + input PIPERX03EQLPLFFSSEL; + input [17:0] PIPERX03EQLPNEWTXCOEFFORPRESET; + input PIPERX03PHYSTATUS; + input [1:0] PIPERX03STARTBLOCK; + input [2:0] PIPERX03STATUS; + input [1:0] PIPERX03SYNCHEADER; + input PIPERX03VALID; + input [1:0] PIPERX04CHARISK; + input [31:0] PIPERX04DATA; + input PIPERX04DATAVALID; + input PIPERX04ELECIDLE; + input PIPERX04EQDONE; + input PIPERX04EQLPADAPTDONE; + input PIPERX04EQLPLFFSSEL; + input [17:0] PIPERX04EQLPNEWTXCOEFFORPRESET; + input PIPERX04PHYSTATUS; + input [1:0] PIPERX04STARTBLOCK; + input [2:0] PIPERX04STATUS; + input [1:0] PIPERX04SYNCHEADER; + input PIPERX04VALID; + input [1:0] PIPERX05CHARISK; + input [31:0] PIPERX05DATA; + input PIPERX05DATAVALID; + input PIPERX05ELECIDLE; + input PIPERX05EQDONE; + input PIPERX05EQLPADAPTDONE; + input PIPERX05EQLPLFFSSEL; + input [17:0] PIPERX05EQLPNEWTXCOEFFORPRESET; + input PIPERX05PHYSTATUS; + input [1:0] PIPERX05STARTBLOCK; + input [2:0] PIPERX05STATUS; + input [1:0] PIPERX05SYNCHEADER; + input PIPERX05VALID; + input [1:0] PIPERX06CHARISK; + input [31:0] PIPERX06DATA; + input PIPERX06DATAVALID; + input PIPERX06ELECIDLE; + input PIPERX06EQDONE; + input PIPERX06EQLPADAPTDONE; + input PIPERX06EQLPLFFSSEL; + input [17:0] PIPERX06EQLPNEWTXCOEFFORPRESET; + input PIPERX06PHYSTATUS; + input [1:0] PIPERX06STARTBLOCK; + input [2:0] PIPERX06STATUS; + input [1:0] PIPERX06SYNCHEADER; + input PIPERX06VALID; + input [1:0] PIPERX07CHARISK; + input [31:0] PIPERX07DATA; + input PIPERX07DATAVALID; + input PIPERX07ELECIDLE; + input PIPERX07EQDONE; + input PIPERX07EQLPADAPTDONE; + input PIPERX07EQLPLFFSSEL; + input [17:0] PIPERX07EQLPNEWTXCOEFFORPRESET; + input PIPERX07PHYSTATUS; + input [1:0] PIPERX07STARTBLOCK; + input [2:0] PIPERX07STATUS; + input [1:0] PIPERX07SYNCHEADER; + input PIPERX07VALID; + input [1:0] PIPERX08CHARISK; + input [31:0] PIPERX08DATA; + input PIPERX08DATAVALID; + input PIPERX08ELECIDLE; + input PIPERX08EQDONE; + input PIPERX08EQLPADAPTDONE; + input PIPERX08EQLPLFFSSEL; + input [17:0] PIPERX08EQLPNEWTXCOEFFORPRESET; + input PIPERX08PHYSTATUS; + input [1:0] PIPERX08STARTBLOCK; + input [2:0] PIPERX08STATUS; + input [1:0] PIPERX08SYNCHEADER; + input PIPERX08VALID; + input [1:0] PIPERX09CHARISK; + input [31:0] PIPERX09DATA; + input PIPERX09DATAVALID; + input PIPERX09ELECIDLE; + input PIPERX09EQDONE; + input PIPERX09EQLPADAPTDONE; + input PIPERX09EQLPLFFSSEL; + input [17:0] PIPERX09EQLPNEWTXCOEFFORPRESET; + input PIPERX09PHYSTATUS; + input [1:0] PIPERX09STARTBLOCK; + input [2:0] PIPERX09STATUS; + input [1:0] PIPERX09SYNCHEADER; + input PIPERX09VALID; + input [1:0] PIPERX10CHARISK; + input [31:0] PIPERX10DATA; + input PIPERX10DATAVALID; + input PIPERX10ELECIDLE; + input PIPERX10EQDONE; + input PIPERX10EQLPADAPTDONE; + input PIPERX10EQLPLFFSSEL; + input [17:0] PIPERX10EQLPNEWTXCOEFFORPRESET; + input PIPERX10PHYSTATUS; + input [1:0] PIPERX10STARTBLOCK; + input [2:0] PIPERX10STATUS; + input [1:0] PIPERX10SYNCHEADER; + input PIPERX10VALID; + input [1:0] PIPERX11CHARISK; + input [31:0] PIPERX11DATA; + input PIPERX11DATAVALID; + input PIPERX11ELECIDLE; + input PIPERX11EQDONE; + input PIPERX11EQLPADAPTDONE; + input PIPERX11EQLPLFFSSEL; + input [17:0] PIPERX11EQLPNEWTXCOEFFORPRESET; + input PIPERX11PHYSTATUS; + input [1:0] PIPERX11STARTBLOCK; + input [2:0] PIPERX11STATUS; + input [1:0] PIPERX11SYNCHEADER; + input PIPERX11VALID; + input [1:0] PIPERX12CHARISK; + input [31:0] PIPERX12DATA; + input PIPERX12DATAVALID; + input PIPERX12ELECIDLE; + input PIPERX12EQDONE; + input PIPERX12EQLPADAPTDONE; + input PIPERX12EQLPLFFSSEL; + input [17:0] PIPERX12EQLPNEWTXCOEFFORPRESET; + input PIPERX12PHYSTATUS; + input [1:0] PIPERX12STARTBLOCK; + input [2:0] PIPERX12STATUS; + input [1:0] PIPERX12SYNCHEADER; + input PIPERX12VALID; + input [1:0] PIPERX13CHARISK; + input [31:0] PIPERX13DATA; + input PIPERX13DATAVALID; + input PIPERX13ELECIDLE; + input PIPERX13EQDONE; + input PIPERX13EQLPADAPTDONE; + input PIPERX13EQLPLFFSSEL; + input [17:0] PIPERX13EQLPNEWTXCOEFFORPRESET; + input PIPERX13PHYSTATUS; + input [1:0] PIPERX13STARTBLOCK; + input [2:0] PIPERX13STATUS; + input [1:0] PIPERX13SYNCHEADER; + input PIPERX13VALID; + input [1:0] PIPERX14CHARISK; + input [31:0] PIPERX14DATA; + input PIPERX14DATAVALID; + input PIPERX14ELECIDLE; + input PIPERX14EQDONE; + input PIPERX14EQLPADAPTDONE; + input PIPERX14EQLPLFFSSEL; + input [17:0] PIPERX14EQLPNEWTXCOEFFORPRESET; + input PIPERX14PHYSTATUS; + input [1:0] PIPERX14STARTBLOCK; + input [2:0] PIPERX14STATUS; + input [1:0] PIPERX14SYNCHEADER; + input PIPERX14VALID; + input [1:0] PIPERX15CHARISK; + input [31:0] PIPERX15DATA; + input PIPERX15DATAVALID; + input PIPERX15ELECIDLE; + input PIPERX15EQDONE; + input PIPERX15EQLPADAPTDONE; + input PIPERX15EQLPLFFSSEL; + input [17:0] PIPERX15EQLPNEWTXCOEFFORPRESET; + input PIPERX15PHYSTATUS; + input [1:0] PIPERX15STARTBLOCK; + input [2:0] PIPERX15STATUS; + input [1:0] PIPERX15SYNCHEADER; + input PIPERX15VALID; + input [17:0] PIPETX00EQCOEFF; + input PIPETX00EQDONE; + input [17:0] PIPETX01EQCOEFF; + input PIPETX01EQDONE; + input [17:0] PIPETX02EQCOEFF; + input PIPETX02EQDONE; + input [17:0] PIPETX03EQCOEFF; + input PIPETX03EQDONE; + input [17:0] PIPETX04EQCOEFF; + input PIPETX04EQDONE; + input [17:0] PIPETX05EQCOEFF; + input PIPETX05EQDONE; + input [17:0] PIPETX06EQCOEFF; + input PIPETX06EQDONE; + input [17:0] PIPETX07EQCOEFF; + input PIPETX07EQDONE; + input [17:0] PIPETX08EQCOEFF; + input PIPETX08EQDONE; + input [17:0] PIPETX09EQCOEFF; + input PIPETX09EQDONE; + input [17:0] PIPETX10EQCOEFF; + input PIPETX10EQDONE; + input [17:0] PIPETX11EQCOEFF; + input PIPETX11EQDONE; + input [17:0] PIPETX12EQCOEFF; + input PIPETX12EQDONE; + input [17:0] PIPETX13EQCOEFF; + input PIPETX13EQDONE; + input [17:0] PIPETX14EQCOEFF; + input PIPETX14EQDONE; + input [17:0] PIPETX15EQCOEFF; + input PIPETX15EQDONE; + input PLEQRESETEIEOSCOUNT; + input PLGEN2UPSTREAMPREFERDEEMPH; + input PLGEN34REDOEQSPEED; + input PLGEN34REDOEQUALIZATION; + input RESETN; + input [255:0] SAXISCCTDATA; + input [7:0] SAXISCCTKEEP; + input SAXISCCTLAST; + input [32:0] SAXISCCTUSER; + input SAXISCCTVALID; + input [255:0] SAXISRQTDATA; + input [7:0] SAXISRQTKEEP; + input SAXISRQTLAST; + input [61:0] SAXISRQTUSER; + input SAXISRQTVALID; + input USERCLK; + input USERCLK2; + input USERCLKEN; + input [31:0] USERSPAREIN; +endmodule + +module PCIE4CE4 (...); + parameter ARI_CAP_ENABLE = "FALSE"; + parameter AUTO_FLR_RESPONSE = "FALSE"; + parameter [7:0] AXISTEN_IF_CCIX_RX_CREDIT_LIMIT = 8'h08; + parameter [7:0] AXISTEN_IF_CCIX_TX_CREDIT_LIMIT = 8'h08; + parameter AXISTEN_IF_CCIX_TX_REGISTERED_TREADY = "FALSE"; + parameter [1:0] AXISTEN_IF_CC_ALIGNMENT_MODE = 2'h0; + parameter [23:0] AXISTEN_IF_COMPL_TIMEOUT_REG0 = 24'hBEBC20; + parameter [27:0] AXISTEN_IF_COMPL_TIMEOUT_REG1 = 28'h2FAF080; + parameter [1:0] AXISTEN_IF_CQ_ALIGNMENT_MODE = 2'h0; + parameter AXISTEN_IF_CQ_EN_POISONED_MEM_WR = "FALSE"; + parameter AXISTEN_IF_ENABLE_256_TAGS = "FALSE"; + parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE"; + parameter AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = "FALSE"; + parameter AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK = "TRUE"; + parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000; + parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE"; + parameter AXISTEN_IF_EXT_512 = "FALSE"; + parameter AXISTEN_IF_EXT_512_CC_STRADDLE = "FALSE"; + parameter AXISTEN_IF_EXT_512_CQ_STRADDLE = "FALSE"; + parameter AXISTEN_IF_EXT_512_RC_STRADDLE = "FALSE"; + parameter AXISTEN_IF_EXT_512_RQ_STRADDLE = "FALSE"; + parameter AXISTEN_IF_LEGACY_MODE_ENABLE = "FALSE"; + parameter AXISTEN_IF_MSIX_FROM_RAM_PIPELINE = "FALSE"; + parameter AXISTEN_IF_MSIX_RX_PARITY_EN = "TRUE"; + parameter AXISTEN_IF_MSIX_TO_RAM_PIPELINE = "FALSE"; + parameter [1:0] AXISTEN_IF_RC_ALIGNMENT_MODE = 2'h0; + parameter AXISTEN_IF_RC_STRADDLE = "FALSE"; + parameter [1:0] AXISTEN_IF_RQ_ALIGNMENT_MODE = 2'h0; + parameter AXISTEN_IF_RX_PARITY_EN = "TRUE"; + parameter AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT = "FALSE"; + parameter AXISTEN_IF_TX_PARITY_EN = "TRUE"; + parameter [1:0] AXISTEN_IF_WIDTH = 2'h2; + parameter CCIX_DIRECT_ATTACH_MODE = "FALSE"; + parameter CCIX_ENABLE = "FALSE"; + parameter [15:0] CCIX_VENDOR_ID = 16'h0000; + parameter CFG_BYPASS_MODE_ENABLE = "FALSE"; + parameter CRM_CORE_CLK_FREQ_500 = "TRUE"; + parameter [1:0] CRM_USER_CLK_FREQ = 2'h2; + parameter [15:0] DEBUG_AXI4ST_SPARE = 16'h0000; + parameter [7:0] DEBUG_AXIST_DISABLE_FEATURE_BIT = 8'h00; + parameter [3:0] DEBUG_CAR_SPARE = 4'h0; + parameter [15:0] DEBUG_CFG_SPARE = 16'h0000; + parameter [15:0] DEBUG_LL_SPARE = 16'h0000; + parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR = "FALSE"; + parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR = "FALSE"; + parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR = "FALSE"; + parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL = "FALSE"; + parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW = "FALSE"; + parameter DEBUG_PL_DISABLE_SCRAMBLING = "FALSE"; + parameter DEBUG_PL_SIM_RESET_LFSR = "FALSE"; + parameter [15:0] DEBUG_PL_SPARE = 16'h0000; + parameter DEBUG_TL_DISABLE_FC_TIMEOUT = "FALSE"; + parameter DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS = "FALSE"; + parameter [15:0] DEBUG_TL_SPARE = 16'h0000; + parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; + parameter DSN_CAP_ENABLE = "FALSE"; + parameter EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; + parameter HEADER_TYPE_OVERRIDE = "FALSE"; + parameter IS_SWITCH_PORT = "FALSE"; + parameter LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; + parameter [8:0] LL_ACK_TIMEOUT = 9'h000; + parameter LL_ACK_TIMEOUT_EN = "FALSE"; + parameter integer LL_ACK_TIMEOUT_FUNC = 0; + parameter LL_DISABLE_SCHED_TX_NAK = "FALSE"; + parameter LL_REPLAY_FROM_RAM_PIPELINE = "FALSE"; + parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000; + parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; + parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; + parameter LL_REPLAY_TO_RAM_PIPELINE = "FALSE"; + parameter LL_RX_TLP_PARITY_GEN = "TRUE"; + parameter LL_TX_TLP_PARITY_CHK = "TRUE"; + parameter [15:0] LL_USER_SPARE = 16'h0000; + parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h250; + parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE"; + parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE"; + parameter [11:0] MCAP_CAP_NEXTPTR = 12'h000; + parameter MCAP_CONFIGURE_OVERRIDE = "FALSE"; + parameter MCAP_ENABLE = "FALSE"; + parameter MCAP_EOS_DESIGN_SWITCH = "FALSE"; + parameter [31:0] MCAP_FPGA_BITSTREAM_VERSION = 32'h00000000; + parameter MCAP_GATE_IO_ENABLE_DESIGN_SWITCH = "FALSE"; + parameter MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH = "FALSE"; + parameter MCAP_INPUT_GATE_DESIGN_SWITCH = "FALSE"; + parameter MCAP_INTERRUPT_ON_MCAP_EOS = "FALSE"; + parameter MCAP_INTERRUPT_ON_MCAP_ERROR = "FALSE"; + parameter [15:0] MCAP_VSEC_ID = 16'h0000; + parameter [11:0] MCAP_VSEC_LEN = 12'h02C; + parameter [3:0] MCAP_VSEC_REV = 4'h0; + parameter PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE = "FALSE"; + parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [3:0] PF0_ARI_CAP_VER = 4'h1; + parameter [4:0] PF0_ATS_CAP_INV_QUEUE_DEPTH = 5'h00; + parameter [11:0] PF0_ATS_CAP_NEXTPTR = 12'h000; + parameter PF0_ATS_CAP_ON = "FALSE"; + parameter [5:0] PF0_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_BAR0_CONTROL = 3'h4; + parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF0_BAR1_CONTROL = 3'h0; + parameter [5:0] PF0_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_BAR2_CONTROL = 3'h4; + parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR3_CONTROL = 3'h0; + parameter [5:0] PF0_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_BAR4_CONTROL = 3'h4; + parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR5_CONTROL = 3'h0; + parameter [7:0] PF0_CAPABILITY_POINTER = 8'h80; + parameter [23:0] PF0_CLASS_CODE = 24'h000000; + parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_ARI_FORWARD_ENABLE = "FALSE"; + parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE"; + parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE"; + parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0; + parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE"; + parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0; + parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0; + parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; + parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE"; + parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF0_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [2:0] PF0_INTERRUPT_PIN = 3'h1; + parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4 = 7; + parameter [0:0] PF0_LINK_CONTROL_RCB = 1'h0; + parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; + parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000; + parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000; + parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000; + parameter [3:0] PF0_LTR_CAP_VER = 4'h1; + parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF0_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF0_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [5:0] PF0_MSIX_VECTOR_COUNT = 6'h04; + parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00; + parameter PF0_MSI_CAP_PERVECMASKCAP = "FALSE"; + parameter [7:0] PF0_PCIE_CAP_NEXTPTR = 8'h00; + parameter [7:0] PF0_PM_CAP_ID = 8'h01; + parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00; + parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE"; + parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE"; + parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE"; + parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE"; + parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3; + parameter PF0_PM_CSR_NOSOFTRESET = "TRUE"; + parameter [11:0] PF0_PRI_CAP_NEXTPTR = 12'h000; + parameter PF0_PRI_CAP_ON = "FALSE"; + parameter [31:0] PF0_PRI_OST_PR_CAPACITY = 32'h00000000; + parameter [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR = 12'h000; + parameter PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; + parameter [5:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0; + parameter [5:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0; + parameter [5:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter PF0_TPHR_CAP_ENABLE = "FALSE"; + parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] PF0_TPHR_CAP_VER = 4'h1; + parameter [3:0] PF0_VC_ARB_CAPABILITY = 4'h0; + parameter [7:0] PF0_VC_ARB_TBL_OFFSET = 8'h00; + parameter PF0_VC_CAP_ENABLE = "FALSE"; + parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000; + parameter [3:0] PF0_VC_CAP_VER = 4'h1; + parameter PF0_VC_EXTENDED_COUNT = "FALSE"; + parameter PF0_VC_LOW_PRIORITY_EXTENDED_COUNT = "FALSE"; + parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [4:0] PF1_ATS_CAP_INV_QUEUE_DEPTH = 5'h00; + parameter [11:0] PF1_ATS_CAP_NEXTPTR = 12'h000; + parameter PF1_ATS_CAP_ON = "FALSE"; + parameter [5:0] PF1_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_BAR0_CONTROL = 3'h4; + parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF1_BAR1_CONTROL = 3'h0; + parameter [5:0] PF1_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_BAR2_CONTROL = 3'h4; + parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR3_CONTROL = 3'h0; + parameter [5:0] PF1_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_BAR4_CONTROL = 3'h4; + parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR5_CONTROL = 3'h0; + parameter [7:0] PF1_CAPABILITY_POINTER = 8'h80; + parameter [23:0] PF1_CLASS_CODE = 24'h000000; + parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF1_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [2:0] PF1_INTERRUPT_PIN = 3'h1; + parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF1_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF1_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00; + parameter PF1_MSI_CAP_PERVECMASKCAP = "FALSE"; + parameter [7:0] PF1_PCIE_CAP_NEXTPTR = 8'h00; + parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00; + parameter [11:0] PF1_PRI_CAP_NEXTPTR = 12'h000; + parameter PF1_PRI_CAP_ON = "FALSE"; + parameter [31:0] PF1_PRI_OST_PR_CAPACITY = 32'h00000000; + parameter PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; + parameter [5:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0; + parameter [5:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0; + parameter [5:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [11:0] PF2_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF2_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF2_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [4:0] PF2_ATS_CAP_INV_QUEUE_DEPTH = 5'h00; + parameter [11:0] PF2_ATS_CAP_NEXTPTR = 12'h000; + parameter PF2_ATS_CAP_ON = "FALSE"; + parameter [5:0] PF2_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_BAR0_CONTROL = 3'h4; + parameter [4:0] PF2_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF2_BAR1_CONTROL = 3'h0; + parameter [5:0] PF2_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_BAR2_CONTROL = 3'h4; + parameter [4:0] PF2_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_BAR3_CONTROL = 3'h0; + parameter [5:0] PF2_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_BAR4_CONTROL = 3'h4; + parameter [4:0] PF2_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_BAR5_CONTROL = 3'h0; + parameter [7:0] PF2_CAPABILITY_POINTER = 8'h80; + parameter [23:0] PF2_CLASS_CODE = 24'h000000; + parameter [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF2_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF2_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [2:0] PF2_INTERRUPT_PIN = 3'h1; + parameter [7:0] PF2_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF2_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF2_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF2_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF2_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF2_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF2_MSI_CAP_NEXTPTR = 8'h00; + parameter PF2_MSI_CAP_PERVECMASKCAP = "FALSE"; + parameter [7:0] PF2_PCIE_CAP_NEXTPTR = 8'h00; + parameter [7:0] PF2_PM_CAP_NEXTPTR = 8'h00; + parameter [11:0] PF2_PRI_CAP_NEXTPTR = 12'h000; + parameter PF2_PRI_CAP_ON = "FALSE"; + parameter [31:0] PF2_PRI_OST_PR_CAPACITY = 32'h00000000; + parameter PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; + parameter [5:0] PF2_SRIOV_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF2_SRIOV_BAR1_CONTROL = 3'h0; + parameter [5:0] PF2_SRIOV_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_SRIOV_BAR3_CONTROL = 3'h0; + parameter [5:0] PF2_SRIOV_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF2_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF2_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF2_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF2_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF2_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF2_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF2_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [11:0] PF2_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF2_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [11:0] PF3_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF3_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF3_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [4:0] PF3_ATS_CAP_INV_QUEUE_DEPTH = 5'h00; + parameter [11:0] PF3_ATS_CAP_NEXTPTR = 12'h000; + parameter PF3_ATS_CAP_ON = "FALSE"; + parameter [5:0] PF3_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_BAR0_CONTROL = 3'h4; + parameter [4:0] PF3_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF3_BAR1_CONTROL = 3'h0; + parameter [5:0] PF3_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_BAR2_CONTROL = 3'h4; + parameter [4:0] PF3_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_BAR3_CONTROL = 3'h0; + parameter [5:0] PF3_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_BAR4_CONTROL = 3'h4; + parameter [4:0] PF3_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_BAR5_CONTROL = 3'h0; + parameter [7:0] PF3_CAPABILITY_POINTER = 8'h80; + parameter [23:0] PF3_CLASS_CODE = 24'h000000; + parameter [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF3_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF3_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [2:0] PF3_INTERRUPT_PIN = 3'h1; + parameter [7:0] PF3_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF3_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF3_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF3_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF3_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF3_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF3_MSI_CAP_NEXTPTR = 8'h00; + parameter PF3_MSI_CAP_PERVECMASKCAP = "FALSE"; + parameter [7:0] PF3_PCIE_CAP_NEXTPTR = 8'h00; + parameter [7:0] PF3_PM_CAP_NEXTPTR = 8'h00; + parameter [11:0] PF3_PRI_CAP_NEXTPTR = 12'h000; + parameter PF3_PRI_CAP_ON = "FALSE"; + parameter [31:0] PF3_PRI_OST_PR_CAPACITY = 32'h00000000; + parameter PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; + parameter [5:0] PF3_SRIOV_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF3_SRIOV_BAR1_CONTROL = 3'h0; + parameter [5:0] PF3_SRIOV_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_SRIOV_BAR3_CONTROL = 3'h0; + parameter [5:0] PF3_SRIOV_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF3_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF3_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF3_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF3_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF3_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF3_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF3_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [11:0] PF3_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF3_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter PL_CFG_STATE_ROBUSTNESS_ENABLE = "TRUE"; + parameter PL_CTRL_SKP_GEN_ENABLE = "FALSE"; + parameter PL_CTRL_SKP_PARITY_AND_CRC_CHECK_DISABLE = "TRUE"; + parameter PL_DEEMPH_SOURCE_SELECT = "TRUE"; + parameter PL_DESKEW_ON_SKIP_IN_GEN12 = "FALSE"; + parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 = "FALSE"; + parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4 = "FALSE"; + parameter PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 = "FALSE"; + parameter PL_DISABLE_DC_BALANCE = "FALSE"; + parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE"; + parameter PL_DISABLE_LANE_REVERSAL = "FALSE"; + parameter [1:0] PL_DISABLE_LFSR_UPDATE_ON_SKP = 2'h0; + parameter PL_DISABLE_RETRAIN_ON_EB_ERROR = "FALSE"; + parameter PL_DISABLE_RETRAIN_ON_FRAMING_ERROR = "FALSE"; + parameter [15:0] PL_DISABLE_RETRAIN_ON_SPECIFIC_FRAMING_ERROR = 16'h0000; + parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE"; + parameter [1:0] PL_EQ_ADAPT_DISABLE_COEFF_CHECK = 2'h0; + parameter [1:0] PL_EQ_ADAPT_DISABLE_PRESET_CHECK = 2'h0; + parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02; + parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1; + parameter [1:0] PL_EQ_BYPASS_PHASE23 = 2'h0; + parameter [5:0] PL_EQ_DEFAULT_RX_PRESET_HINT = 6'h33; + parameter [7:0] PL_EQ_DEFAULT_TX_PRESET = 8'h44; + parameter PL_EQ_DISABLE_MISMATCH_CHECK = "TRUE"; + parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE0 = 2'h0; + parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE1 = 2'h0; + parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE"; + parameter PL_EQ_TX_8G_EQ_TS2_ENABLE = "FALSE"; + parameter PL_EXIT_LOOPBACK_ON_EI_ENTRY = "TRUE"; + parameter PL_INFER_EI_DISABLE_LPBK_ACTIVE = "TRUE"; + parameter PL_INFER_EI_DISABLE_REC_RC = "FALSE"; + parameter PL_INFER_EI_DISABLE_REC_SPD = "FALSE"; + parameter [31:0] PL_LANE0_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE10_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE11_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE12_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE13_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE14_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE15_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE1_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE2_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE3_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE4_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE5_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE6_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE7_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE8_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE9_EQ_CONTROL = 32'h00003F00; + parameter [3:0] PL_LINK_CAP_MAX_LINK_SPEED = 4'h4; + parameter [4:0] PL_LINK_CAP_MAX_LINK_WIDTH = 5'h08; + parameter integer PL_N_FTS = 255; + parameter PL_QUIESCE_GUARANTEE_DISABLE = "FALSE"; + parameter PL_REDO_EQ_SOURCE_SELECT = "TRUE"; + parameter [7:0] PL_REPORT_ALL_PHY_ERRORS = 8'h00; + parameter [1:0] PL_RX_ADAPT_TIMER_CLWS_CLOBBER_TX_TS = 2'h0; + parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN3 = 4'h0; + parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN4 = 4'h0; + parameter [1:0] PL_RX_ADAPT_TIMER_RRL_CLOBBER_TX_TS = 2'h0; + parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN3 = 4'h0; + parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN4 = 4'h0; + parameter [1:0] PL_RX_L0S_EXIT_TO_RECOVERY = 2'h0; + parameter [1:0] PL_SIM_FAST_LINK_TRAINING = 2'h0; + parameter PL_SRIS_ENABLE = "FALSE"; + parameter [6:0] PL_SRIS_SKPOS_GEN_SPD_VEC = 7'h00; + parameter [6:0] PL_SRIS_SKPOS_REC_SPD_VEC = 7'h00; + parameter PL_UPSTREAM_FACING = "TRUE"; + parameter [15:0] PL_USER_SPARE = 16'h0000; + parameter [15:0] PL_USER_SPARE2 = 16'h0000; + parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h1500; + parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h003E8; + parameter PM_ENABLE_L23_ENTRY = "FALSE"; + parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE"; + parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000100; + parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h00000; + parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0100; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter [31:0] SIM_JTAG_IDCODE = 32'h00000000; + parameter SIM_VERSION = "1.0"; + parameter SPARE_BIT0 = "FALSE"; + parameter integer SPARE_BIT1 = 0; + parameter integer SPARE_BIT2 = 0; + parameter SPARE_BIT3 = "FALSE"; + parameter integer SPARE_BIT4 = 0; + parameter integer SPARE_BIT5 = 0; + parameter integer SPARE_BIT6 = 0; + parameter integer SPARE_BIT7 = 0; + parameter integer SPARE_BIT8 = 0; + parameter [7:0] SPARE_BYTE0 = 8'h00; + parameter [7:0] SPARE_BYTE1 = 8'h00; + parameter [7:0] SPARE_BYTE2 = 8'h00; + parameter [7:0] SPARE_BYTE3 = 8'h00; + parameter [31:0] SPARE_WORD0 = 32'h00000000; + parameter [31:0] SPARE_WORD1 = 32'h00000000; + parameter [31:0] SPARE_WORD2 = 32'h00000000; + parameter [31:0] SPARE_WORD3 = 32'h00000000; + parameter [3:0] SRIOV_CAP_ENABLE = 4'h0; + parameter TL2CFG_IF_PARITY_CHK = "TRUE"; + parameter [1:0] TL_COMPLETION_RAM_NUM_TLPS = 2'h0; + parameter [1:0] TL_COMPLETION_RAM_SIZE = 2'h1; + parameter [11:0] TL_CREDITS_CD = 12'h000; + parameter [11:0] TL_CREDITS_CD_VC1 = 12'h000; + parameter [7:0] TL_CREDITS_CH = 8'h00; + parameter [7:0] TL_CREDITS_CH_VC1 = 8'h00; + parameter [11:0] TL_CREDITS_NPD = 12'h004; + parameter [11:0] TL_CREDITS_NPD_VC1 = 12'h000; + parameter [7:0] TL_CREDITS_NPH = 8'h20; + parameter [7:0] TL_CREDITS_NPH_VC1 = 8'h01; + parameter [11:0] TL_CREDITS_PD = 12'h0E0; + parameter [11:0] TL_CREDITS_PD_VC1 = 12'h3E0; + parameter [7:0] TL_CREDITS_PH = 8'h20; + parameter [7:0] TL_CREDITS_PH_VC1 = 8'h20; + parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TIME = 5'h02; + parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TIME_VC1 = 5'h02; + parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT = 5'h08; + parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT_VC1 = 5'h08; + parameter TL_FEATURE_ENABLE_FC_SCALING = "FALSE"; + parameter [1:0] TL_PF_ENABLE_REG = 2'h0; + parameter [0:0] TL_POSTED_RAM_SIZE = 1'h0; + parameter TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE = "FALSE"; + parameter TL_RX_COMPLETION_TO_RAM_READ_PIPELINE = "FALSE"; + parameter TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE = "FALSE"; + parameter TL_RX_POSTED_FROM_RAM_READ_PIPELINE = "FALSE"; + parameter TL_RX_POSTED_TO_RAM_READ_PIPELINE = "FALSE"; + parameter TL_RX_POSTED_TO_RAM_WRITE_PIPELINE = "FALSE"; + parameter TL_TX_MUX_STRICT_PRIORITY = "TRUE"; + parameter TL_TX_TLP_STRADDLE_ENABLE = "FALSE"; + parameter TL_TX_TLP_TERMINATE_PARITY = "FALSE"; + parameter [15:0] TL_USER_SPARE = 16'h0000; + parameter TPH_FROM_RAM_PIPELINE = "FALSE"; + parameter TPH_TO_RAM_PIPELINE = "FALSE"; + parameter [7:0] VF0_CAPABILITY_POINTER = 8'h80; + parameter [11:0] VFG0_ARI_CAP_NEXTPTR = 12'h000; + parameter [4:0] VFG0_ATS_CAP_INV_QUEUE_DEPTH = 5'h00; + parameter [11:0] VFG0_ATS_CAP_NEXTPTR = 12'h000; + parameter VFG0_ATS_CAP_ON = "FALSE"; + parameter [7:0] VFG0_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer VFG0_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VFG0_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VFG0_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VFG0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VFG0_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [7:0] VFG0_PCIE_CAP_NEXTPTR = 8'h00; + parameter [11:0] VFG0_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VFG0_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [11:0] VFG1_ARI_CAP_NEXTPTR = 12'h000; + parameter [4:0] VFG1_ATS_CAP_INV_QUEUE_DEPTH = 5'h00; + parameter [11:0] VFG1_ATS_CAP_NEXTPTR = 12'h000; + parameter VFG1_ATS_CAP_ON = "FALSE"; + parameter [7:0] VFG1_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer VFG1_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VFG1_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VFG1_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VFG1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VFG1_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [7:0] VFG1_PCIE_CAP_NEXTPTR = 8'h00; + parameter [11:0] VFG1_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VFG1_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [11:0] VFG2_ARI_CAP_NEXTPTR = 12'h000; + parameter [4:0] VFG2_ATS_CAP_INV_QUEUE_DEPTH = 5'h00; + parameter [11:0] VFG2_ATS_CAP_NEXTPTR = 12'h000; + parameter VFG2_ATS_CAP_ON = "FALSE"; + parameter [7:0] VFG2_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer VFG2_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VFG2_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VFG2_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VFG2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VFG2_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [7:0] VFG2_PCIE_CAP_NEXTPTR = 8'h00; + parameter [11:0] VFG2_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VFG2_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [11:0] VFG3_ARI_CAP_NEXTPTR = 12'h000; + parameter [4:0] VFG3_ATS_CAP_INV_QUEUE_DEPTH = 5'h00; + parameter [11:0] VFG3_ATS_CAP_NEXTPTR = 12'h000; + parameter VFG3_ATS_CAP_ON = "FALSE"; + parameter [7:0] VFG3_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer VFG3_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VFG3_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VFG3_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VFG3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VFG3_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [7:0] VFG3_PCIE_CAP_NEXTPTR = 8'h00; + parameter [11:0] VFG3_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VFG3_TPHR_CAP_ST_MODE_SEL = 3'h0; + output [7:0] AXIUSEROUT; + output CCIXTXCREDIT; + output [7:0] CFGBUSNUMBER; + output [1:0] CFGCURRENTSPEED; + output CFGERRCOROUT; + output CFGERRFATALOUT; + output CFGERRNONFATALOUT; + output [7:0] CFGEXTFUNCTIONNUMBER; + output CFGEXTREADRECEIVED; + output [9:0] CFGEXTREGISTERNUMBER; + output [3:0] CFGEXTWRITEBYTEENABLE; + output [31:0] CFGEXTWRITEDATA; + output CFGEXTWRITERECEIVED; + output [11:0] CFGFCCPLD; + output [7:0] CFGFCCPLH; + output [11:0] CFGFCNPD; + output [7:0] CFGFCNPH; + output [11:0] CFGFCPD; + output [7:0] CFGFCPH; + output [3:0] CFGFLRINPROCESS; + output [11:0] CFGFUNCTIONPOWERSTATE; + output [15:0] CFGFUNCTIONSTATUS; + output CFGHOTRESETOUT; + output [31:0] CFGINTERRUPTMSIDATA; + output [3:0] CFGINTERRUPTMSIENABLE; + output CFGINTERRUPTMSIFAIL; + output CFGINTERRUPTMSIMASKUPDATE; + output [11:0] CFGINTERRUPTMSIMMENABLE; + output CFGINTERRUPTMSISENT; + output [3:0] CFGINTERRUPTMSIXENABLE; + output [3:0] CFGINTERRUPTMSIXMASK; + output CFGINTERRUPTMSIXVECPENDINGSTATUS; + output CFGINTERRUPTSENT; + output [1:0] CFGLINKPOWERSTATE; + output [4:0] CFGLOCALERROROUT; + output CFGLOCALERRORVALID; + output CFGLTRENABLE; + output [5:0] CFGLTSSMSTATE; + output [1:0] CFGMAXPAYLOAD; + output [2:0] CFGMAXREADREQ; + output [31:0] CFGMGMTREADDATA; + output CFGMGMTREADWRITEDONE; + output CFGMSGRECEIVED; + output [7:0] CFGMSGRECEIVEDDATA; + output [4:0] CFGMSGRECEIVEDTYPE; + output CFGMSGTRANSMITDONE; + output [12:0] CFGMSIXRAMADDRESS; + output CFGMSIXRAMREADENABLE; + output [3:0] CFGMSIXRAMWRITEBYTEENABLE; + output [35:0] CFGMSIXRAMWRITEDATA; + output [2:0] CFGNEGOTIATEDWIDTH; + output [1:0] CFGOBFFENABLE; + output CFGPHYLINKDOWN; + output [1:0] CFGPHYLINKSTATUS; + output CFGPLSTATUSCHANGE; + output CFGPOWERSTATECHANGEINTERRUPT; + output [3:0] CFGRCBSTATUS; + output [1:0] CFGRXPMSTATE; + output [11:0] CFGTPHRAMADDRESS; + output CFGTPHRAMREADENABLE; + output [3:0] CFGTPHRAMWRITEBYTEENABLE; + output [35:0] CFGTPHRAMWRITEDATA; + output [3:0] CFGTPHREQUESTERENABLE; + output [11:0] CFGTPHSTMODE; + output [1:0] CFGTXPMSTATE; + output CFGVC1ENABLE; + output CFGVC1NEGOTIATIONPENDING; + output CONFMCAPDESIGNSWITCH; + output CONFMCAPEOS; + output CONFMCAPINUSEBYPCIE; + output CONFREQREADY; + output [31:0] CONFRESPRDATA; + output CONFRESPVALID; + output [129:0] DBGCCIXOUT; + output [31:0] DBGCTRL0OUT; + output [31:0] DBGCTRL1OUT; + output [255:0] DBGDATA0OUT; + output [255:0] DBGDATA1OUT; + output [15:0] DRPDO; + output DRPRDY; + output [45:0] MAXISCCIXRXTUSER; + output MAXISCCIXRXTVALID; + output [255:0] MAXISCQTDATA; + output [7:0] MAXISCQTKEEP; + output MAXISCQTLAST; + output [87:0] MAXISCQTUSER; + output MAXISCQTVALID; + output [255:0] MAXISRCTDATA; + output [7:0] MAXISRCTKEEP; + output MAXISRCTLAST; + output [74:0] MAXISRCTUSER; + output MAXISRCTVALID; + output [8:0] MIREPLAYRAMADDRESS0; + output [8:0] MIREPLAYRAMADDRESS1; + output MIREPLAYRAMREADENABLE0; + output MIREPLAYRAMREADENABLE1; + output [127:0] MIREPLAYRAMWRITEDATA0; + output [127:0] MIREPLAYRAMWRITEDATA1; + output MIREPLAYRAMWRITEENABLE0; + output MIREPLAYRAMWRITEENABLE1; + output [8:0] MIRXCOMPLETIONRAMREADADDRESS0; + output [8:0] MIRXCOMPLETIONRAMREADADDRESS1; + output [1:0] MIRXCOMPLETIONRAMREADENABLE0; + output [1:0] MIRXCOMPLETIONRAMREADENABLE1; + output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS0; + output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS1; + output [143:0] MIRXCOMPLETIONRAMWRITEDATA0; + output [143:0] MIRXCOMPLETIONRAMWRITEDATA1; + output [1:0] MIRXCOMPLETIONRAMWRITEENABLE0; + output [1:0] MIRXCOMPLETIONRAMWRITEENABLE1; + output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS0; + output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS1; + output MIRXPOSTEDREQUESTRAMREADENABLE0; + output MIRXPOSTEDREQUESTRAMREADENABLE1; + output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS0; + output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS1; + output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA0; + output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA1; + output MIRXPOSTEDREQUESTRAMWRITEENABLE0; + output MIRXPOSTEDREQUESTRAMWRITEENABLE1; + output [5:0] PCIECQNPREQCOUNT; + output PCIEPERST0B; + output PCIEPERST1B; + output [5:0] PCIERQSEQNUM0; + output [5:0] PCIERQSEQNUM1; + output PCIERQSEQNUMVLD0; + output PCIERQSEQNUMVLD1; + output [7:0] PCIERQTAG0; + output [7:0] PCIERQTAG1; + output [3:0] PCIERQTAGAV; + output PCIERQTAGVLD0; + output PCIERQTAGVLD1; + output [3:0] PCIETFCNPDAV; + output [3:0] PCIETFCNPHAV; + output [1:0] PIPERX00EQCONTROL; + output PIPERX00POLARITY; + output [1:0] PIPERX01EQCONTROL; + output PIPERX01POLARITY; + output [1:0] PIPERX02EQCONTROL; + output PIPERX02POLARITY; + output [1:0] PIPERX03EQCONTROL; + output PIPERX03POLARITY; + output [1:0] PIPERX04EQCONTROL; + output PIPERX04POLARITY; + output [1:0] PIPERX05EQCONTROL; + output PIPERX05POLARITY; + output [1:0] PIPERX06EQCONTROL; + output PIPERX06POLARITY; + output [1:0] PIPERX07EQCONTROL; + output PIPERX07POLARITY; + output [1:0] PIPERX08EQCONTROL; + output PIPERX08POLARITY; + output [1:0] PIPERX09EQCONTROL; + output PIPERX09POLARITY; + output [1:0] PIPERX10EQCONTROL; + output PIPERX10POLARITY; + output [1:0] PIPERX11EQCONTROL; + output PIPERX11POLARITY; + output [1:0] PIPERX12EQCONTROL; + output PIPERX12POLARITY; + output [1:0] PIPERX13EQCONTROL; + output PIPERX13POLARITY; + output [1:0] PIPERX14EQCONTROL; + output PIPERX14POLARITY; + output [1:0] PIPERX15EQCONTROL; + output PIPERX15POLARITY; + output [5:0] PIPERXEQLPLFFS; + output [3:0] PIPERXEQLPTXPRESET; + output [1:0] PIPETX00CHARISK; + output PIPETX00COMPLIANCE; + output [31:0] PIPETX00DATA; + output PIPETX00DATAVALID; + output PIPETX00ELECIDLE; + output [1:0] PIPETX00EQCONTROL; + output [5:0] PIPETX00EQDEEMPH; + output [1:0] PIPETX00POWERDOWN; + output PIPETX00STARTBLOCK; + output [1:0] PIPETX00SYNCHEADER; + output [1:0] PIPETX01CHARISK; + output PIPETX01COMPLIANCE; + output [31:0] PIPETX01DATA; + output PIPETX01DATAVALID; + output PIPETX01ELECIDLE; + output [1:0] PIPETX01EQCONTROL; + output [5:0] PIPETX01EQDEEMPH; + output [1:0] PIPETX01POWERDOWN; + output PIPETX01STARTBLOCK; + output [1:0] PIPETX01SYNCHEADER; + output [1:0] PIPETX02CHARISK; + output PIPETX02COMPLIANCE; + output [31:0] PIPETX02DATA; + output PIPETX02DATAVALID; + output PIPETX02ELECIDLE; + output [1:0] PIPETX02EQCONTROL; + output [5:0] PIPETX02EQDEEMPH; + output [1:0] PIPETX02POWERDOWN; + output PIPETX02STARTBLOCK; + output [1:0] PIPETX02SYNCHEADER; + output [1:0] PIPETX03CHARISK; + output PIPETX03COMPLIANCE; + output [31:0] PIPETX03DATA; + output PIPETX03DATAVALID; + output PIPETX03ELECIDLE; + output [1:0] PIPETX03EQCONTROL; + output [5:0] PIPETX03EQDEEMPH; + output [1:0] PIPETX03POWERDOWN; + output PIPETX03STARTBLOCK; + output [1:0] PIPETX03SYNCHEADER; + output [1:0] PIPETX04CHARISK; + output PIPETX04COMPLIANCE; + output [31:0] PIPETX04DATA; + output PIPETX04DATAVALID; + output PIPETX04ELECIDLE; + output [1:0] PIPETX04EQCONTROL; + output [5:0] PIPETX04EQDEEMPH; + output [1:0] PIPETX04POWERDOWN; + output PIPETX04STARTBLOCK; + output [1:0] PIPETX04SYNCHEADER; + output [1:0] PIPETX05CHARISK; + output PIPETX05COMPLIANCE; + output [31:0] PIPETX05DATA; + output PIPETX05DATAVALID; + output PIPETX05ELECIDLE; + output [1:0] PIPETX05EQCONTROL; + output [5:0] PIPETX05EQDEEMPH; + output [1:0] PIPETX05POWERDOWN; + output PIPETX05STARTBLOCK; + output [1:0] PIPETX05SYNCHEADER; + output [1:0] PIPETX06CHARISK; + output PIPETX06COMPLIANCE; + output [31:0] PIPETX06DATA; + output PIPETX06DATAVALID; + output PIPETX06ELECIDLE; + output [1:0] PIPETX06EQCONTROL; + output [5:0] PIPETX06EQDEEMPH; + output [1:0] PIPETX06POWERDOWN; + output PIPETX06STARTBLOCK; + output [1:0] PIPETX06SYNCHEADER; + output [1:0] PIPETX07CHARISK; + output PIPETX07COMPLIANCE; + output [31:0] PIPETX07DATA; + output PIPETX07DATAVALID; + output PIPETX07ELECIDLE; + output [1:0] PIPETX07EQCONTROL; + output [5:0] PIPETX07EQDEEMPH; + output [1:0] PIPETX07POWERDOWN; + output PIPETX07STARTBLOCK; + output [1:0] PIPETX07SYNCHEADER; + output [1:0] PIPETX08CHARISK; + output PIPETX08COMPLIANCE; + output [31:0] PIPETX08DATA; + output PIPETX08DATAVALID; + output PIPETX08ELECIDLE; + output [1:0] PIPETX08EQCONTROL; + output [5:0] PIPETX08EQDEEMPH; + output [1:0] PIPETX08POWERDOWN; + output PIPETX08STARTBLOCK; + output [1:0] PIPETX08SYNCHEADER; + output [1:0] PIPETX09CHARISK; + output PIPETX09COMPLIANCE; + output [31:0] PIPETX09DATA; + output PIPETX09DATAVALID; + output PIPETX09ELECIDLE; + output [1:0] PIPETX09EQCONTROL; + output [5:0] PIPETX09EQDEEMPH; + output [1:0] PIPETX09POWERDOWN; + output PIPETX09STARTBLOCK; + output [1:0] PIPETX09SYNCHEADER; + output [1:0] PIPETX10CHARISK; + output PIPETX10COMPLIANCE; + output [31:0] PIPETX10DATA; + output PIPETX10DATAVALID; + output PIPETX10ELECIDLE; + output [1:0] PIPETX10EQCONTROL; + output [5:0] PIPETX10EQDEEMPH; + output [1:0] PIPETX10POWERDOWN; + output PIPETX10STARTBLOCK; + output [1:0] PIPETX10SYNCHEADER; + output [1:0] PIPETX11CHARISK; + output PIPETX11COMPLIANCE; + output [31:0] PIPETX11DATA; + output PIPETX11DATAVALID; + output PIPETX11ELECIDLE; + output [1:0] PIPETX11EQCONTROL; + output [5:0] PIPETX11EQDEEMPH; + output [1:0] PIPETX11POWERDOWN; + output PIPETX11STARTBLOCK; + output [1:0] PIPETX11SYNCHEADER; + output [1:0] PIPETX12CHARISK; + output PIPETX12COMPLIANCE; + output [31:0] PIPETX12DATA; + output PIPETX12DATAVALID; + output PIPETX12ELECIDLE; + output [1:0] PIPETX12EQCONTROL; + output [5:0] PIPETX12EQDEEMPH; + output [1:0] PIPETX12POWERDOWN; + output PIPETX12STARTBLOCK; + output [1:0] PIPETX12SYNCHEADER; + output [1:0] PIPETX13CHARISK; + output PIPETX13COMPLIANCE; + output [31:0] PIPETX13DATA; + output PIPETX13DATAVALID; + output PIPETX13ELECIDLE; + output [1:0] PIPETX13EQCONTROL; + output [5:0] PIPETX13EQDEEMPH; + output [1:0] PIPETX13POWERDOWN; + output PIPETX13STARTBLOCK; + output [1:0] PIPETX13SYNCHEADER; + output [1:0] PIPETX14CHARISK; + output PIPETX14COMPLIANCE; + output [31:0] PIPETX14DATA; + output PIPETX14DATAVALID; + output PIPETX14ELECIDLE; + output [1:0] PIPETX14EQCONTROL; + output [5:0] PIPETX14EQDEEMPH; + output [1:0] PIPETX14POWERDOWN; + output PIPETX14STARTBLOCK; + output [1:0] PIPETX14SYNCHEADER; + output [1:0] PIPETX15CHARISK; + output PIPETX15COMPLIANCE; + output [31:0] PIPETX15DATA; + output PIPETX15DATAVALID; + output PIPETX15ELECIDLE; + output [1:0] PIPETX15EQCONTROL; + output [5:0] PIPETX15EQDEEMPH; + output [1:0] PIPETX15POWERDOWN; + output PIPETX15STARTBLOCK; + output [1:0] PIPETX15SYNCHEADER; + output PIPETXDEEMPH; + output [2:0] PIPETXMARGIN; + output [1:0] PIPETXRATE; + output PIPETXRCVRDET; + output PIPETXRESET; + output PIPETXSWING; + output PLEQINPROGRESS; + output [1:0] PLEQPHASE; + output PLGEN34EQMISMATCH; + output [3:0] SAXISCCTREADY; + output [3:0] SAXISRQTREADY; + output [23:0] USERSPAREOUT; + input [7:0] AXIUSERIN; + input CCIXOPTIMIZEDTLPTXANDRXENABLE; + input CCIXRXCORRECTABLEERRORDETECTED; + input CCIXRXFIFOOVERFLOW; + input CCIXRXTLPFORWARDED0; + input CCIXRXTLPFORWARDED1; + input [5:0] CCIXRXTLPFORWARDEDLENGTH0; + input [5:0] CCIXRXTLPFORWARDEDLENGTH1; + input CCIXRXUNCORRECTABLEERRORDETECTED; + input CFGCONFIGSPACEENABLE; + input [15:0] CFGDEVIDPF0; + input [15:0] CFGDEVIDPF1; + input [15:0] CFGDEVIDPF2; + input [15:0] CFGDEVIDPF3; + input [7:0] CFGDSBUSNUMBER; + input [4:0] CFGDSDEVICENUMBER; + input [2:0] CFGDSFUNCTIONNUMBER; + input [63:0] CFGDSN; + input [7:0] CFGDSPORTNUMBER; + input CFGERRCORIN; + input CFGERRUNCORIN; + input [31:0] CFGEXTREADDATA; + input CFGEXTREADDATAVALID; + input [2:0] CFGFCSEL; + input CFGFCVCSEL; + input [3:0] CFGFLRDONE; + input CFGHOTRESETIN; + input [3:0] CFGINTERRUPTINT; + input [2:0] CFGINTERRUPTMSIATTR; + input [7:0] CFGINTERRUPTMSIFUNCTIONNUMBER; + input [31:0] CFGINTERRUPTMSIINT; + input [31:0] CFGINTERRUPTMSIPENDINGSTATUS; + input CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE; + input [1:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM; + input [1:0] CFGINTERRUPTMSISELECT; + input CFGINTERRUPTMSITPHPRESENT; + input [7:0] CFGINTERRUPTMSITPHSTTAG; + input [1:0] CFGINTERRUPTMSITPHTYPE; + input [63:0] CFGINTERRUPTMSIXADDRESS; + input [31:0] CFGINTERRUPTMSIXDATA; + input CFGINTERRUPTMSIXINT; + input [1:0] CFGINTERRUPTMSIXVECPENDING; + input [3:0] CFGINTERRUPTPENDING; + input CFGLINKTRAININGENABLE; + input [9:0] CFGMGMTADDR; + input [3:0] CFGMGMTBYTEENABLE; + input CFGMGMTDEBUGACCESS; + input [7:0] CFGMGMTFUNCTIONNUMBER; + input CFGMGMTREAD; + input CFGMGMTWRITE; + input [31:0] CFGMGMTWRITEDATA; + input CFGMSGTRANSMIT; + input [31:0] CFGMSGTRANSMITDATA; + input [2:0] CFGMSGTRANSMITTYPE; + input [35:0] CFGMSIXRAMREADDATA; + input CFGPMASPML1ENTRYREJECT; + input CFGPMASPMTXL0SENTRYDISABLE; + input CFGPOWERSTATECHANGEACK; + input CFGREQPMTRANSITIONL23READY; + input [7:0] CFGREVIDPF0; + input [7:0] CFGREVIDPF1; + input [7:0] CFGREVIDPF2; + input [7:0] CFGREVIDPF3; + input [15:0] CFGSUBSYSIDPF0; + input [15:0] CFGSUBSYSIDPF1; + input [15:0] CFGSUBSYSIDPF2; + input [15:0] CFGSUBSYSIDPF3; + input [15:0] CFGSUBSYSVENDID; + input [35:0] CFGTPHRAMREADDATA; + input [15:0] CFGVENDID; + input CFGVFFLRDONE; + input [7:0] CFGVFFLRFUNCNUM; + input CONFMCAPREQUESTBYCONF; + input [31:0] CONFREQDATA; + input [3:0] CONFREQREGNUM; + input [1:0] CONFREQTYPE; + input CONFREQVALID; + input CORECLK; + input CORECLKCCIX; + input CORECLKMIREPLAYRAM0; + input CORECLKMIREPLAYRAM1; + input CORECLKMIRXCOMPLETIONRAM0; + input CORECLKMIRXCOMPLETIONRAM1; + input CORECLKMIRXPOSTEDREQUESTRAM0; + input CORECLKMIRXPOSTEDREQUESTRAM1; + input [5:0] DBGSEL0; + input [5:0] DBGSEL1; + input [9:0] DRPADDR; + input DRPCLK; + input [15:0] DRPDI; + input DRPEN; + input DRPWE; + input [21:0] MAXISCQTREADY; + input [21:0] MAXISRCTREADY; + input MCAPCLK; + input MCAPPERST0B; + input MCAPPERST1B; + input MGMTRESETN; + input MGMTSTICKYRESETN; + input [5:0] MIREPLAYRAMERRCOR; + input [5:0] MIREPLAYRAMERRUNCOR; + input [127:0] MIREPLAYRAMREADDATA0; + input [127:0] MIREPLAYRAMREADDATA1; + input [11:0] MIRXCOMPLETIONRAMERRCOR; + input [11:0] MIRXCOMPLETIONRAMERRUNCOR; + input [143:0] MIRXCOMPLETIONRAMREADDATA0; + input [143:0] MIRXCOMPLETIONRAMREADDATA1; + input [5:0] MIRXPOSTEDREQUESTRAMERRCOR; + input [5:0] MIRXPOSTEDREQUESTRAMERRUNCOR; + input [143:0] MIRXPOSTEDREQUESTRAMREADDATA0; + input [143:0] MIRXPOSTEDREQUESTRAMREADDATA1; + input [1:0] PCIECOMPLDELIVERED; + input [7:0] PCIECOMPLDELIVEREDTAG0; + input [7:0] PCIECOMPLDELIVEREDTAG1; + input [1:0] PCIECQNPREQ; + input PCIECQNPUSERCREDITRCVD; + input PCIECQPIPELINEEMPTY; + input PCIEPOSTEDREQDELIVERED; + input PIPECLK; + input PIPECLKEN; + input [5:0] PIPEEQFS; + input [5:0] PIPEEQLF; + input PIPERESETN; + input [1:0] PIPERX00CHARISK; + input [31:0] PIPERX00DATA; + input PIPERX00DATAVALID; + input PIPERX00ELECIDLE; + input PIPERX00EQDONE; + input PIPERX00EQLPADAPTDONE; + input PIPERX00EQLPLFFSSEL; + input [17:0] PIPERX00EQLPNEWTXCOEFFORPRESET; + input PIPERX00PHYSTATUS; + input [1:0] PIPERX00STARTBLOCK; + input [2:0] PIPERX00STATUS; + input [1:0] PIPERX00SYNCHEADER; + input PIPERX00VALID; + input [1:0] PIPERX01CHARISK; + input [31:0] PIPERX01DATA; + input PIPERX01DATAVALID; + input PIPERX01ELECIDLE; + input PIPERX01EQDONE; + input PIPERX01EQLPADAPTDONE; + input PIPERX01EQLPLFFSSEL; + input [17:0] PIPERX01EQLPNEWTXCOEFFORPRESET; + input PIPERX01PHYSTATUS; + input [1:0] PIPERX01STARTBLOCK; + input [2:0] PIPERX01STATUS; + input [1:0] PIPERX01SYNCHEADER; + input PIPERX01VALID; + input [1:0] PIPERX02CHARISK; + input [31:0] PIPERX02DATA; + input PIPERX02DATAVALID; + input PIPERX02ELECIDLE; + input PIPERX02EQDONE; + input PIPERX02EQLPADAPTDONE; + input PIPERX02EQLPLFFSSEL; + input [17:0] PIPERX02EQLPNEWTXCOEFFORPRESET; + input PIPERX02PHYSTATUS; + input [1:0] PIPERX02STARTBLOCK; + input [2:0] PIPERX02STATUS; + input [1:0] PIPERX02SYNCHEADER; + input PIPERX02VALID; + input [1:0] PIPERX03CHARISK; + input [31:0] PIPERX03DATA; + input PIPERX03DATAVALID; + input PIPERX03ELECIDLE; + input PIPERX03EQDONE; + input PIPERX03EQLPADAPTDONE; + input PIPERX03EQLPLFFSSEL; + input [17:0] PIPERX03EQLPNEWTXCOEFFORPRESET; + input PIPERX03PHYSTATUS; + input [1:0] PIPERX03STARTBLOCK; + input [2:0] PIPERX03STATUS; + input [1:0] PIPERX03SYNCHEADER; + input PIPERX03VALID; + input [1:0] PIPERX04CHARISK; + input [31:0] PIPERX04DATA; + input PIPERX04DATAVALID; + input PIPERX04ELECIDLE; + input PIPERX04EQDONE; + input PIPERX04EQLPADAPTDONE; + input PIPERX04EQLPLFFSSEL; + input [17:0] PIPERX04EQLPNEWTXCOEFFORPRESET; + input PIPERX04PHYSTATUS; + input [1:0] PIPERX04STARTBLOCK; + input [2:0] PIPERX04STATUS; + input [1:0] PIPERX04SYNCHEADER; + input PIPERX04VALID; + input [1:0] PIPERX05CHARISK; + input [31:0] PIPERX05DATA; + input PIPERX05DATAVALID; + input PIPERX05ELECIDLE; + input PIPERX05EQDONE; + input PIPERX05EQLPADAPTDONE; + input PIPERX05EQLPLFFSSEL; + input [17:0] PIPERX05EQLPNEWTXCOEFFORPRESET; + input PIPERX05PHYSTATUS; + input [1:0] PIPERX05STARTBLOCK; + input [2:0] PIPERX05STATUS; + input [1:0] PIPERX05SYNCHEADER; + input PIPERX05VALID; + input [1:0] PIPERX06CHARISK; + input [31:0] PIPERX06DATA; + input PIPERX06DATAVALID; + input PIPERX06ELECIDLE; + input PIPERX06EQDONE; + input PIPERX06EQLPADAPTDONE; + input PIPERX06EQLPLFFSSEL; + input [17:0] PIPERX06EQLPNEWTXCOEFFORPRESET; + input PIPERX06PHYSTATUS; + input [1:0] PIPERX06STARTBLOCK; + input [2:0] PIPERX06STATUS; + input [1:0] PIPERX06SYNCHEADER; + input PIPERX06VALID; + input [1:0] PIPERX07CHARISK; + input [31:0] PIPERX07DATA; + input PIPERX07DATAVALID; + input PIPERX07ELECIDLE; + input PIPERX07EQDONE; + input PIPERX07EQLPADAPTDONE; + input PIPERX07EQLPLFFSSEL; + input [17:0] PIPERX07EQLPNEWTXCOEFFORPRESET; + input PIPERX07PHYSTATUS; + input [1:0] PIPERX07STARTBLOCK; + input [2:0] PIPERX07STATUS; + input [1:0] PIPERX07SYNCHEADER; + input PIPERX07VALID; + input [1:0] PIPERX08CHARISK; + input [31:0] PIPERX08DATA; + input PIPERX08DATAVALID; + input PIPERX08ELECIDLE; + input PIPERX08EQDONE; + input PIPERX08EQLPADAPTDONE; + input PIPERX08EQLPLFFSSEL; + input [17:0] PIPERX08EQLPNEWTXCOEFFORPRESET; + input PIPERX08PHYSTATUS; + input [1:0] PIPERX08STARTBLOCK; + input [2:0] PIPERX08STATUS; + input [1:0] PIPERX08SYNCHEADER; + input PIPERX08VALID; + input [1:0] PIPERX09CHARISK; + input [31:0] PIPERX09DATA; + input PIPERX09DATAVALID; + input PIPERX09ELECIDLE; + input PIPERX09EQDONE; + input PIPERX09EQLPADAPTDONE; + input PIPERX09EQLPLFFSSEL; + input [17:0] PIPERX09EQLPNEWTXCOEFFORPRESET; + input PIPERX09PHYSTATUS; + input [1:0] PIPERX09STARTBLOCK; + input [2:0] PIPERX09STATUS; + input [1:0] PIPERX09SYNCHEADER; + input PIPERX09VALID; + input [1:0] PIPERX10CHARISK; + input [31:0] PIPERX10DATA; + input PIPERX10DATAVALID; + input PIPERX10ELECIDLE; + input PIPERX10EQDONE; + input PIPERX10EQLPADAPTDONE; + input PIPERX10EQLPLFFSSEL; + input [17:0] PIPERX10EQLPNEWTXCOEFFORPRESET; + input PIPERX10PHYSTATUS; + input [1:0] PIPERX10STARTBLOCK; + input [2:0] PIPERX10STATUS; + input [1:0] PIPERX10SYNCHEADER; + input PIPERX10VALID; + input [1:0] PIPERX11CHARISK; + input [31:0] PIPERX11DATA; + input PIPERX11DATAVALID; + input PIPERX11ELECIDLE; + input PIPERX11EQDONE; + input PIPERX11EQLPADAPTDONE; + input PIPERX11EQLPLFFSSEL; + input [17:0] PIPERX11EQLPNEWTXCOEFFORPRESET; + input PIPERX11PHYSTATUS; + input [1:0] PIPERX11STARTBLOCK; + input [2:0] PIPERX11STATUS; + input [1:0] PIPERX11SYNCHEADER; + input PIPERX11VALID; + input [1:0] PIPERX12CHARISK; + input [31:0] PIPERX12DATA; + input PIPERX12DATAVALID; + input PIPERX12ELECIDLE; + input PIPERX12EQDONE; + input PIPERX12EQLPADAPTDONE; + input PIPERX12EQLPLFFSSEL; + input [17:0] PIPERX12EQLPNEWTXCOEFFORPRESET; + input PIPERX12PHYSTATUS; + input [1:0] PIPERX12STARTBLOCK; + input [2:0] PIPERX12STATUS; + input [1:0] PIPERX12SYNCHEADER; + input PIPERX12VALID; + input [1:0] PIPERX13CHARISK; + input [31:0] PIPERX13DATA; + input PIPERX13DATAVALID; + input PIPERX13ELECIDLE; + input PIPERX13EQDONE; + input PIPERX13EQLPADAPTDONE; + input PIPERX13EQLPLFFSSEL; + input [17:0] PIPERX13EQLPNEWTXCOEFFORPRESET; + input PIPERX13PHYSTATUS; + input [1:0] PIPERX13STARTBLOCK; + input [2:0] PIPERX13STATUS; + input [1:0] PIPERX13SYNCHEADER; + input PIPERX13VALID; + input [1:0] PIPERX14CHARISK; + input [31:0] PIPERX14DATA; + input PIPERX14DATAVALID; + input PIPERX14ELECIDLE; + input PIPERX14EQDONE; + input PIPERX14EQLPADAPTDONE; + input PIPERX14EQLPLFFSSEL; + input [17:0] PIPERX14EQLPNEWTXCOEFFORPRESET; + input PIPERX14PHYSTATUS; + input [1:0] PIPERX14STARTBLOCK; + input [2:0] PIPERX14STATUS; + input [1:0] PIPERX14SYNCHEADER; + input PIPERX14VALID; + input [1:0] PIPERX15CHARISK; + input [31:0] PIPERX15DATA; + input PIPERX15DATAVALID; + input PIPERX15ELECIDLE; + input PIPERX15EQDONE; + input PIPERX15EQLPADAPTDONE; + input PIPERX15EQLPLFFSSEL; + input [17:0] PIPERX15EQLPNEWTXCOEFFORPRESET; + input PIPERX15PHYSTATUS; + input [1:0] PIPERX15STARTBLOCK; + input [2:0] PIPERX15STATUS; + input [1:0] PIPERX15SYNCHEADER; + input PIPERX15VALID; + input [17:0] PIPETX00EQCOEFF; + input PIPETX00EQDONE; + input [17:0] PIPETX01EQCOEFF; + input PIPETX01EQDONE; + input [17:0] PIPETX02EQCOEFF; + input PIPETX02EQDONE; + input [17:0] PIPETX03EQCOEFF; + input PIPETX03EQDONE; + input [17:0] PIPETX04EQCOEFF; + input PIPETX04EQDONE; + input [17:0] PIPETX05EQCOEFF; + input PIPETX05EQDONE; + input [17:0] PIPETX06EQCOEFF; + input PIPETX06EQDONE; + input [17:0] PIPETX07EQCOEFF; + input PIPETX07EQDONE; + input [17:0] PIPETX08EQCOEFF; + input PIPETX08EQDONE; + input [17:0] PIPETX09EQCOEFF; + input PIPETX09EQDONE; + input [17:0] PIPETX10EQCOEFF; + input PIPETX10EQDONE; + input [17:0] PIPETX11EQCOEFF; + input PIPETX11EQDONE; + input [17:0] PIPETX12EQCOEFF; + input PIPETX12EQDONE; + input [17:0] PIPETX13EQCOEFF; + input PIPETX13EQDONE; + input [17:0] PIPETX14EQCOEFF; + input PIPETX14EQDONE; + input [17:0] PIPETX15EQCOEFF; + input PIPETX15EQDONE; + input PLEQRESETEIEOSCOUNT; + input PLGEN2UPSTREAMPREFERDEEMPH; + input PLGEN34REDOEQSPEED; + input PLGEN34REDOEQUALIZATION; + input RESETN; + input [255:0] SAXISCCIXTXTDATA; + input [45:0] SAXISCCIXTXTUSER; + input SAXISCCIXTXTVALID; + input [255:0] SAXISCCTDATA; + input [7:0] SAXISCCTKEEP; + input SAXISCCTLAST; + input [32:0] SAXISCCTUSER; + input SAXISCCTVALID; + input [255:0] SAXISRQTDATA; + input [7:0] SAXISRQTKEEP; + input SAXISRQTLAST; + input [61:0] SAXISRQTUSER; + input SAXISRQTVALID; + input USERCLK; + input USERCLK2; + input USERCLKEN; + input [31:0] USERSPAREIN; +endmodule + +module EMAC (...); + parameter EMAC0_MODE = "RGMII"; + parameter EMAC1_MODE = "RGMII"; + output DCRHOSTDONEIR; + output EMAC0CLIENTANINTERRUPT; + output EMAC0CLIENTRXBADFRAME; + output EMAC0CLIENTRXCLIENTCLKOUT; + output EMAC0CLIENTRXDVLD; + output EMAC0CLIENTRXDVLDMSW; + output EMAC0CLIENTRXDVREG6; + output EMAC0CLIENTRXFRAMEDROP; + output EMAC0CLIENTRXGOODFRAME; + output EMAC0CLIENTRXSTATSBYTEVLD; + output EMAC0CLIENTRXSTATSVLD; + output EMAC0CLIENTTXACK; + output EMAC0CLIENTTXCLIENTCLKOUT; + output EMAC0CLIENTTXCOLLISION; + output EMAC0CLIENTTXGMIIMIICLKOUT; + output EMAC0CLIENTTXRETRANSMIT; + output EMAC0CLIENTTXSTATS; + output EMAC0CLIENTTXSTATSBYTEVLD; + output EMAC0CLIENTTXSTATSVLD; + output EMAC0PHYENCOMMAALIGN; + output EMAC0PHYLOOPBACKMSB; + output EMAC0PHYMCLKOUT; + output EMAC0PHYMDOUT; + output EMAC0PHYMDTRI; + output EMAC0PHYMGTRXRESET; + output EMAC0PHYMGTTXRESET; + output EMAC0PHYPOWERDOWN; + output EMAC0PHYSYNCACQSTATUS; + output EMAC0PHYTXCHARDISPMODE; + output EMAC0PHYTXCHARDISPVAL; + output EMAC0PHYTXCHARISK; + output EMAC0PHYTXCLK; + output EMAC0PHYTXEN; + output EMAC0PHYTXER; + output EMAC1CLIENTANINTERRUPT; + output EMAC1CLIENTRXBADFRAME; + output EMAC1CLIENTRXCLIENTCLKOUT; + output EMAC1CLIENTRXDVLD; + output EMAC1CLIENTRXDVLDMSW; + output EMAC1CLIENTRXDVREG6; + output EMAC1CLIENTRXFRAMEDROP; + output EMAC1CLIENTRXGOODFRAME; + output EMAC1CLIENTRXSTATSBYTEVLD; + output EMAC1CLIENTRXSTATSVLD; + output EMAC1CLIENTTXACK; + output EMAC1CLIENTTXCLIENTCLKOUT; + output EMAC1CLIENTTXCOLLISION; + output EMAC1CLIENTTXGMIIMIICLKOUT; + output EMAC1CLIENTTXRETRANSMIT; + output EMAC1CLIENTTXSTATS; + output EMAC1CLIENTTXSTATSBYTEVLD; + output EMAC1CLIENTTXSTATSVLD; + output EMAC1PHYENCOMMAALIGN; + output EMAC1PHYLOOPBACKMSB; + output EMAC1PHYMCLKOUT; + output EMAC1PHYMDOUT; + output EMAC1PHYMDTRI; + output EMAC1PHYMGTRXRESET; + output EMAC1PHYMGTTXRESET; + output EMAC1PHYPOWERDOWN; + output EMAC1PHYSYNCACQSTATUS; + output EMAC1PHYTXCHARDISPMODE; + output EMAC1PHYTXCHARDISPVAL; + output EMAC1PHYTXCHARISK; + output EMAC1PHYTXCLK; + output EMAC1PHYTXEN; + output EMAC1PHYTXER; + output EMACDCRACK; + output HOSTMIIMRDY; + output [0:31] EMACDCRDBUS; + output [15:0] EMAC0CLIENTRXD; + output [15:0] EMAC1CLIENTRXD; + output [31:0] HOSTRDDATA; + output [6:0] EMAC0CLIENTRXSTATS; + output [6:0] EMAC1CLIENTRXSTATS; + output [7:0] EMAC0PHYTXD; + output [7:0] EMAC1PHYTXD; + input CLIENTEMAC0DCMLOCKED; + input CLIENTEMAC0PAUSEREQ; + input CLIENTEMAC0RXCLIENTCLKIN; + input CLIENTEMAC0TXCLIENTCLKIN; + input CLIENTEMAC0TXDVLD; + input CLIENTEMAC0TXDVLDMSW; + input CLIENTEMAC0TXFIRSTBYTE; + input CLIENTEMAC0TXGMIIMIICLKIN; + input CLIENTEMAC0TXUNDERRUN; + input CLIENTEMAC1DCMLOCKED; + input CLIENTEMAC1PAUSEREQ; + input CLIENTEMAC1RXCLIENTCLKIN; + input CLIENTEMAC1TXCLIENTCLKIN; + input CLIENTEMAC1TXDVLD; + input CLIENTEMAC1TXDVLDMSW; + input CLIENTEMAC1TXFIRSTBYTE; + input CLIENTEMAC1TXGMIIMIICLKIN; + input CLIENTEMAC1TXUNDERRUN; + input DCREMACCLK; + input DCREMACENABLE; + input DCREMACREAD; + input DCREMACWRITE; + input HOSTCLK; + input HOSTEMAC1SEL; + input HOSTMIIMSEL; + input HOSTREQ; + input PHYEMAC0COL; + input PHYEMAC0CRS; + input PHYEMAC0GTXCLK; + input PHYEMAC0MCLKIN; + input PHYEMAC0MDIN; + input PHYEMAC0MIITXCLK; + input PHYEMAC0RXBUFERR; + input PHYEMAC0RXCHARISCOMMA; + input PHYEMAC0RXCHARISK; + input PHYEMAC0RXCHECKINGCRC; + input PHYEMAC0RXCLK; + input PHYEMAC0RXCOMMADET; + input PHYEMAC0RXDISPERR; + input PHYEMAC0RXDV; + input PHYEMAC0RXER; + input PHYEMAC0RXNOTINTABLE; + input PHYEMAC0RXRUNDISP; + input PHYEMAC0SIGNALDET; + input PHYEMAC0TXBUFERR; + input PHYEMAC1COL; + input PHYEMAC1CRS; + input PHYEMAC1GTXCLK; + input PHYEMAC1MCLKIN; + input PHYEMAC1MDIN; + input PHYEMAC1MIITXCLK; + input PHYEMAC1RXBUFERR; + input PHYEMAC1RXCHARISCOMMA; + input PHYEMAC1RXCHARISK; + input PHYEMAC1RXCHECKINGCRC; + input PHYEMAC1RXCLK; + input PHYEMAC1RXCOMMADET; + input PHYEMAC1RXDISPERR; + input PHYEMAC1RXDV; + input PHYEMAC1RXER; + input PHYEMAC1RXNOTINTABLE; + input PHYEMAC1RXRUNDISP; + input PHYEMAC1SIGNALDET; + input PHYEMAC1TXBUFERR; + input RESET; + input [0:31] DCREMACDBUS; + input [15:0] CLIENTEMAC0PAUSEVAL; + input [15:0] CLIENTEMAC0TXD; + input [15:0] CLIENTEMAC1PAUSEVAL; + input [15:0] CLIENTEMAC1TXD; + input [1:0] HOSTOPCODE; + input [1:0] PHYEMAC0RXBUFSTATUS; + input [1:0] PHYEMAC0RXLOSSOFSYNC; + input [1:0] PHYEMAC1RXBUFSTATUS; + input [1:0] PHYEMAC1RXLOSSOFSYNC; + input [2:0] PHYEMAC0RXCLKCORCNT; + input [2:0] PHYEMAC1RXCLKCORCNT; + input [31:0] HOSTWRDATA; + input [47:0] TIEEMAC0UNICASTADDR; + input [47:0] TIEEMAC1UNICASTADDR; + input [4:0] PHYEMAC0PHYAD; + input [4:0] PHYEMAC1PHYAD; + input [79:0] TIEEMAC0CONFIGVEC; + input [79:0] TIEEMAC1CONFIGVEC; + input [7:0] CLIENTEMAC0TXIFGDELAY; + input [7:0] CLIENTEMAC1TXIFGDELAY; + input [7:0] PHYEMAC0RXD; + input [7:0] PHYEMAC1RXD; + input [8:9] DCREMACABUS; + input [9:0] HOSTADDR; +endmodule + +module TEMAC (...); + parameter EMAC0_1000BASEX_ENABLE = "FALSE"; + parameter EMAC0_ADDRFILTER_ENABLE = "FALSE"; + parameter EMAC0_BYTEPHY = "FALSE"; + parameter EMAC0_CONFIGVEC_79 = "FALSE"; + parameter EMAC0_GTLOOPBACK = "FALSE"; + parameter EMAC0_HOST_ENABLE = "FALSE"; + parameter EMAC0_LTCHECK_DISABLE = "FALSE"; + parameter EMAC0_MDIO_ENABLE = "FALSE"; + parameter EMAC0_PHYINITAUTONEG_ENABLE = "FALSE"; + parameter EMAC0_PHYISOLATE = "FALSE"; + parameter EMAC0_PHYLOOPBACKMSB = "FALSE"; + parameter EMAC0_PHYPOWERDOWN = "FALSE"; + parameter EMAC0_PHYRESET = "FALSE"; + parameter EMAC0_RGMII_ENABLE = "FALSE"; + parameter EMAC0_RX16BITCLIENT_ENABLE = "FALSE"; + parameter EMAC0_RXFLOWCTRL_ENABLE = "FALSE"; + parameter EMAC0_RXHALFDUPLEX = "FALSE"; + parameter EMAC0_RXINBANDFCS_ENABLE = "FALSE"; + parameter EMAC0_RXJUMBOFRAME_ENABLE = "FALSE"; + parameter EMAC0_RXRESET = "FALSE"; + parameter EMAC0_RXVLAN_ENABLE = "FALSE"; + parameter EMAC0_RX_ENABLE = "FALSE"; + parameter EMAC0_SGMII_ENABLE = "FALSE"; + parameter EMAC0_SPEED_LSB = "FALSE"; + parameter EMAC0_SPEED_MSB = "FALSE"; + parameter EMAC0_TX16BITCLIENT_ENABLE = "FALSE"; + parameter EMAC0_TXFLOWCTRL_ENABLE = "FALSE"; + parameter EMAC0_TXHALFDUPLEX = "FALSE"; + parameter EMAC0_TXIFGADJUST_ENABLE = "FALSE"; + parameter EMAC0_TXINBANDFCS_ENABLE = "FALSE"; + parameter EMAC0_TXJUMBOFRAME_ENABLE = "FALSE"; + parameter EMAC0_TXRESET = "FALSE"; + parameter EMAC0_TXVLAN_ENABLE = "FALSE"; + parameter EMAC0_TX_ENABLE = "FALSE"; + parameter EMAC0_UNIDIRECTION_ENABLE = "FALSE"; + parameter EMAC0_USECLKEN = "FALSE"; + parameter EMAC1_1000BASEX_ENABLE = "FALSE"; + parameter EMAC1_ADDRFILTER_ENABLE = "FALSE"; + parameter EMAC1_BYTEPHY = "FALSE"; + parameter EMAC1_CONFIGVEC_79 = "FALSE"; + parameter EMAC1_GTLOOPBACK = "FALSE"; + parameter EMAC1_HOST_ENABLE = "FALSE"; + parameter EMAC1_LTCHECK_DISABLE = "FALSE"; + parameter EMAC1_MDIO_ENABLE = "FALSE"; + parameter EMAC1_PHYINITAUTONEG_ENABLE = "FALSE"; + parameter EMAC1_PHYISOLATE = "FALSE"; + parameter EMAC1_PHYLOOPBACKMSB = "FALSE"; + parameter EMAC1_PHYPOWERDOWN = "FALSE"; + parameter EMAC1_PHYRESET = "FALSE"; + parameter EMAC1_RGMII_ENABLE = "FALSE"; + parameter EMAC1_RX16BITCLIENT_ENABLE = "FALSE"; + parameter EMAC1_RXFLOWCTRL_ENABLE = "FALSE"; + parameter EMAC1_RXHALFDUPLEX = "FALSE"; + parameter EMAC1_RXINBANDFCS_ENABLE = "FALSE"; + parameter EMAC1_RXJUMBOFRAME_ENABLE = "FALSE"; + parameter EMAC1_RXRESET = "FALSE"; + parameter EMAC1_RXVLAN_ENABLE = "FALSE"; + parameter EMAC1_RX_ENABLE = "FALSE"; + parameter EMAC1_SGMII_ENABLE = "FALSE"; + parameter EMAC1_SPEED_LSB = "FALSE"; + parameter EMAC1_SPEED_MSB = "FALSE"; + parameter EMAC1_TX16BITCLIENT_ENABLE = "FALSE"; + parameter EMAC1_TXFLOWCTRL_ENABLE = "FALSE"; + parameter EMAC1_TXHALFDUPLEX = "FALSE"; + parameter EMAC1_TXIFGADJUST_ENABLE = "FALSE"; + parameter EMAC1_TXINBANDFCS_ENABLE = "FALSE"; + parameter EMAC1_TXJUMBOFRAME_ENABLE = "FALSE"; + parameter EMAC1_TXRESET = "FALSE"; + parameter EMAC1_TXVLAN_ENABLE = "FALSE"; + parameter EMAC1_TX_ENABLE = "FALSE"; + parameter EMAC1_UNIDIRECTION_ENABLE = "FALSE"; + parameter EMAC1_USECLKEN = "FALSE"; + parameter [0:7] EMAC0_DCRBASEADDR = 8'h00; + parameter [0:7] EMAC1_DCRBASEADDR = 8'h00; + parameter [47:0] EMAC0_PAUSEADDR = 48'h000000000000; + parameter [47:0] EMAC0_UNICASTADDR = 48'h000000000000; + parameter [47:0] EMAC1_PAUSEADDR = 48'h000000000000; + parameter [47:0] EMAC1_UNICASTADDR = 48'h000000000000; + parameter [8:0] EMAC0_LINKTIMERVAL = 9'h000; + parameter [8:0] EMAC1_LINKTIMERVAL = 9'h000; + output DCRHOSTDONEIR; + output EMAC0CLIENTANINTERRUPT; + output EMAC0CLIENTRXBADFRAME; + output EMAC0CLIENTRXCLIENTCLKOUT; + output EMAC0CLIENTRXDVLD; + output EMAC0CLIENTRXDVLDMSW; + output EMAC0CLIENTRXFRAMEDROP; + output EMAC0CLIENTRXGOODFRAME; + output EMAC0CLIENTRXSTATSBYTEVLD; + output EMAC0CLIENTRXSTATSVLD; + output EMAC0CLIENTTXACK; + output EMAC0CLIENTTXCLIENTCLKOUT; + output EMAC0CLIENTTXCOLLISION; + output EMAC0CLIENTTXRETRANSMIT; + output EMAC0CLIENTTXSTATS; + output EMAC0CLIENTTXSTATSBYTEVLD; + output EMAC0CLIENTTXSTATSVLD; + output EMAC0PHYENCOMMAALIGN; + output EMAC0PHYLOOPBACKMSB; + output EMAC0PHYMCLKOUT; + output EMAC0PHYMDOUT; + output EMAC0PHYMDTRI; + output EMAC0PHYMGTRXRESET; + output EMAC0PHYMGTTXRESET; + output EMAC0PHYPOWERDOWN; + output EMAC0PHYSYNCACQSTATUS; + output EMAC0PHYTXCHARDISPMODE; + output EMAC0PHYTXCHARDISPVAL; + output EMAC0PHYTXCHARISK; + output EMAC0PHYTXCLK; + output EMAC0PHYTXEN; + output EMAC0PHYTXER; + output EMAC0PHYTXGMIIMIICLKOUT; + output EMAC0SPEEDIS10100; + output EMAC1CLIENTANINTERRUPT; + output EMAC1CLIENTRXBADFRAME; + output EMAC1CLIENTRXCLIENTCLKOUT; + output EMAC1CLIENTRXDVLD; + output EMAC1CLIENTRXDVLDMSW; + output EMAC1CLIENTRXFRAMEDROP; + output EMAC1CLIENTRXGOODFRAME; + output EMAC1CLIENTRXSTATSBYTEVLD; + output EMAC1CLIENTRXSTATSVLD; + output EMAC1CLIENTTXACK; + output EMAC1CLIENTTXCLIENTCLKOUT; + output EMAC1CLIENTTXCOLLISION; + output EMAC1CLIENTTXRETRANSMIT; + output EMAC1CLIENTTXSTATS; + output EMAC1CLIENTTXSTATSBYTEVLD; + output EMAC1CLIENTTXSTATSVLD; + output EMAC1PHYENCOMMAALIGN; + output EMAC1PHYLOOPBACKMSB; + output EMAC1PHYMCLKOUT; + output EMAC1PHYMDOUT; + output EMAC1PHYMDTRI; + output EMAC1PHYMGTRXRESET; + output EMAC1PHYMGTTXRESET; + output EMAC1PHYPOWERDOWN; + output EMAC1PHYSYNCACQSTATUS; + output EMAC1PHYTXCHARDISPMODE; + output EMAC1PHYTXCHARDISPVAL; + output EMAC1PHYTXCHARISK; + output EMAC1PHYTXCLK; + output EMAC1PHYTXEN; + output EMAC1PHYTXER; + output EMAC1PHYTXGMIIMIICLKOUT; + output EMAC1SPEEDIS10100; + output EMACDCRACK; + output HOSTMIIMRDY; + output [0:31] EMACDCRDBUS; + output [15:0] EMAC0CLIENTRXD; + output [15:0] EMAC1CLIENTRXD; + output [31:0] HOSTRDDATA; + output [6:0] EMAC0CLIENTRXSTATS; + output [6:0] EMAC1CLIENTRXSTATS; + output [7:0] EMAC0PHYTXD; + output [7:0] EMAC1PHYTXD; + input CLIENTEMAC0DCMLOCKED; + input CLIENTEMAC0PAUSEREQ; + input CLIENTEMAC0RXCLIENTCLKIN; + input CLIENTEMAC0TXCLIENTCLKIN; + input CLIENTEMAC0TXDVLD; + input CLIENTEMAC0TXDVLDMSW; + input CLIENTEMAC0TXFIRSTBYTE; + input CLIENTEMAC0TXUNDERRUN; + input CLIENTEMAC1DCMLOCKED; + input CLIENTEMAC1PAUSEREQ; + input CLIENTEMAC1RXCLIENTCLKIN; + input CLIENTEMAC1TXCLIENTCLKIN; + input CLIENTEMAC1TXDVLD; + input CLIENTEMAC1TXDVLDMSW; + input CLIENTEMAC1TXFIRSTBYTE; + input CLIENTEMAC1TXUNDERRUN; + input DCREMACCLK; + input DCREMACENABLE; + input DCREMACREAD; + input DCREMACWRITE; + input HOSTCLK; + input HOSTEMAC1SEL; + input HOSTMIIMSEL; + input HOSTREQ; + input PHYEMAC0COL; + input PHYEMAC0CRS; + input PHYEMAC0GTXCLK; + input PHYEMAC0MCLKIN; + input PHYEMAC0MDIN; + input PHYEMAC0MIITXCLK; + input PHYEMAC0RXBUFERR; + input PHYEMAC0RXCHARISCOMMA; + input PHYEMAC0RXCHARISK; + input PHYEMAC0RXCHECKINGCRC; + input PHYEMAC0RXCLK; + input PHYEMAC0RXCOMMADET; + input PHYEMAC0RXDISPERR; + input PHYEMAC0RXDV; + input PHYEMAC0RXER; + input PHYEMAC0RXNOTINTABLE; + input PHYEMAC0RXRUNDISP; + input PHYEMAC0SIGNALDET; + input PHYEMAC0TXBUFERR; + input PHYEMAC0TXGMIIMIICLKIN; + input PHYEMAC1COL; + input PHYEMAC1CRS; + input PHYEMAC1GTXCLK; + input PHYEMAC1MCLKIN; + input PHYEMAC1MDIN; + input PHYEMAC1MIITXCLK; + input PHYEMAC1RXBUFERR; + input PHYEMAC1RXCHARISCOMMA; + input PHYEMAC1RXCHARISK; + input PHYEMAC1RXCHECKINGCRC; + input PHYEMAC1RXCLK; + input PHYEMAC1RXCOMMADET; + input PHYEMAC1RXDISPERR; + input PHYEMAC1RXDV; + input PHYEMAC1RXER; + input PHYEMAC1RXNOTINTABLE; + input PHYEMAC1RXRUNDISP; + input PHYEMAC1SIGNALDET; + input PHYEMAC1TXBUFERR; + input PHYEMAC1TXGMIIMIICLKIN; + input RESET; + input [0:31] DCREMACDBUS; + input [0:9] DCREMACABUS; + input [15:0] CLIENTEMAC0PAUSEVAL; + input [15:0] CLIENTEMAC0TXD; + input [15:0] CLIENTEMAC1PAUSEVAL; + input [15:0] CLIENTEMAC1TXD; + input [1:0] HOSTOPCODE; + input [1:0] PHYEMAC0RXBUFSTATUS; + input [1:0] PHYEMAC0RXLOSSOFSYNC; + input [1:0] PHYEMAC1RXBUFSTATUS; + input [1:0] PHYEMAC1RXLOSSOFSYNC; + input [2:0] PHYEMAC0RXCLKCORCNT; + input [2:0] PHYEMAC1RXCLKCORCNT; + input [31:0] HOSTWRDATA; + input [4:0] PHYEMAC0PHYAD; + input [4:0] PHYEMAC1PHYAD; + input [7:0] CLIENTEMAC0TXIFGDELAY; + input [7:0] CLIENTEMAC1TXIFGDELAY; + input [7:0] PHYEMAC0RXD; + input [7:0] PHYEMAC1RXD; + input [9:0] HOSTADDR; +endmodule + +module TEMAC_SINGLE (...); + parameter EMAC_1000BASEX_ENABLE = "FALSE"; + parameter EMAC_ADDRFILTER_ENABLE = "FALSE"; + parameter EMAC_BYTEPHY = "FALSE"; + parameter EMAC_CTRLLENCHECK_DISABLE = "FALSE"; + parameter [0:7] EMAC_DCRBASEADDR = 8'h00; + parameter EMAC_GTLOOPBACK = "FALSE"; + parameter EMAC_HOST_ENABLE = "FALSE"; + parameter [8:0] EMAC_LINKTIMERVAL = 9'h000; + parameter EMAC_LTCHECK_DISABLE = "FALSE"; + parameter EMAC_MDIO_ENABLE = "FALSE"; + parameter EMAC_MDIO_IGNORE_PHYADZERO = "FALSE"; + parameter [47:0] EMAC_PAUSEADDR = 48'h000000000000; + parameter EMAC_PHYINITAUTONEG_ENABLE = "FALSE"; + parameter EMAC_PHYISOLATE = "FALSE"; + parameter EMAC_PHYLOOPBACKMSB = "FALSE"; + parameter EMAC_PHYPOWERDOWN = "FALSE"; + parameter EMAC_PHYRESET = "FALSE"; + parameter EMAC_RGMII_ENABLE = "FALSE"; + parameter EMAC_RX16BITCLIENT_ENABLE = "FALSE"; + parameter EMAC_RXFLOWCTRL_ENABLE = "FALSE"; + parameter EMAC_RXHALFDUPLEX = "FALSE"; + parameter EMAC_RXINBANDFCS_ENABLE = "FALSE"; + parameter EMAC_RXJUMBOFRAME_ENABLE = "FALSE"; + parameter EMAC_RXRESET = "FALSE"; + parameter EMAC_RXVLAN_ENABLE = "FALSE"; + parameter EMAC_RX_ENABLE = "TRUE"; + parameter EMAC_SGMII_ENABLE = "FALSE"; + parameter EMAC_SPEED_LSB = "FALSE"; + parameter EMAC_SPEED_MSB = "FALSE"; + parameter EMAC_TX16BITCLIENT_ENABLE = "FALSE"; + parameter EMAC_TXFLOWCTRL_ENABLE = "FALSE"; + parameter EMAC_TXHALFDUPLEX = "FALSE"; + parameter EMAC_TXIFGADJUST_ENABLE = "FALSE"; + parameter EMAC_TXINBANDFCS_ENABLE = "FALSE"; + parameter EMAC_TXJUMBOFRAME_ENABLE = "FALSE"; + parameter EMAC_TXRESET = "FALSE"; + parameter EMAC_TXVLAN_ENABLE = "FALSE"; + parameter EMAC_TX_ENABLE = "TRUE"; + parameter [47:0] EMAC_UNICASTADDR = 48'h000000000000; + parameter EMAC_UNIDIRECTION_ENABLE = "FALSE"; + parameter EMAC_USECLKEN = "FALSE"; + parameter SIM_VERSION = "1.0"; + output DCRHOSTDONEIR; + output EMACCLIENTANINTERRUPT; + output EMACCLIENTRXBADFRAME; + output EMACCLIENTRXCLIENTCLKOUT; + output EMACCLIENTRXDVLD; + output EMACCLIENTRXDVLDMSW; + output EMACCLIENTRXFRAMEDROP; + output EMACCLIENTRXGOODFRAME; + output EMACCLIENTRXSTATSBYTEVLD; + output EMACCLIENTRXSTATSVLD; + output EMACCLIENTTXACK; + output EMACCLIENTTXCLIENTCLKOUT; + output EMACCLIENTTXCOLLISION; + output EMACCLIENTTXRETRANSMIT; + output EMACCLIENTTXSTATS; + output EMACCLIENTTXSTATSBYTEVLD; + output EMACCLIENTTXSTATSVLD; + output EMACDCRACK; + output EMACPHYENCOMMAALIGN; + output EMACPHYLOOPBACKMSB; + output EMACPHYMCLKOUT; + output EMACPHYMDOUT; + output EMACPHYMDTRI; + output EMACPHYMGTRXRESET; + output EMACPHYMGTTXRESET; + output EMACPHYPOWERDOWN; + output EMACPHYSYNCACQSTATUS; + output EMACPHYTXCHARDISPMODE; + output EMACPHYTXCHARDISPVAL; + output EMACPHYTXCHARISK; + output EMACPHYTXCLK; + output EMACPHYTXEN; + output EMACPHYTXER; + output EMACPHYTXGMIIMIICLKOUT; + output EMACSPEEDIS10100; + output HOSTMIIMRDY; + output [0:31] EMACDCRDBUS; + output [15:0] EMACCLIENTRXD; + output [31:0] HOSTRDDATA; + output [6:0] EMACCLIENTRXSTATS; + output [7:0] EMACPHYTXD; + input CLIENTEMACDCMLOCKED; + input CLIENTEMACPAUSEREQ; + input CLIENTEMACRXCLIENTCLKIN; + input CLIENTEMACTXCLIENTCLKIN; + input CLIENTEMACTXDVLD; + input CLIENTEMACTXDVLDMSW; + input CLIENTEMACTXFIRSTBYTE; + input CLIENTEMACTXUNDERRUN; + input DCREMACCLK; + input DCREMACENABLE; + input DCREMACREAD; + input DCREMACWRITE; + input HOSTCLK; + input HOSTMIIMSEL; + input HOSTREQ; + input PHYEMACCOL; + input PHYEMACCRS; + input PHYEMACGTXCLK; + input PHYEMACMCLKIN; + input PHYEMACMDIN; + input PHYEMACMIITXCLK; + input PHYEMACRXCHARISCOMMA; + input PHYEMACRXCHARISK; + input PHYEMACRXCLK; + input PHYEMACRXDISPERR; + input PHYEMACRXDV; + input PHYEMACRXER; + input PHYEMACRXNOTINTABLE; + input PHYEMACRXRUNDISP; + input PHYEMACSIGNALDET; + input PHYEMACTXBUFERR; + input PHYEMACTXGMIIMIICLKIN; + input RESET; + input [0:31] DCREMACDBUS; + input [0:9] DCREMACABUS; + input [15:0] CLIENTEMACPAUSEVAL; + input [15:0] CLIENTEMACTXD; + input [1:0] HOSTOPCODE; + input [1:0] PHYEMACRXBUFSTATUS; + input [2:0] PHYEMACRXCLKCORCNT; + input [31:0] HOSTWRDATA; + input [4:0] PHYEMACPHYAD; + input [7:0] CLIENTEMACTXIFGDELAY; + input [7:0] PHYEMACRXD; + input [9:0] HOSTADDR; +endmodule + +module CMAC (...); + parameter CTL_PTP_TRANSPCLK_MODE = "FALSE"; + parameter CTL_RX_CHECK_ACK = "TRUE"; + parameter CTL_RX_CHECK_PREAMBLE = "FALSE"; + parameter CTL_RX_CHECK_SFD = "FALSE"; + parameter CTL_RX_DELETE_FCS = "TRUE"; + parameter [15:0] CTL_RX_ETYPE_GCP = 16'h8808; + parameter [15:0] CTL_RX_ETYPE_GPP = 16'h8808; + parameter [15:0] CTL_RX_ETYPE_PCP = 16'h8808; + parameter [15:0] CTL_RX_ETYPE_PPP = 16'h8808; + parameter CTL_RX_FORWARD_CONTROL = "FALSE"; + parameter CTL_RX_IGNORE_FCS = "FALSE"; + parameter [14:0] CTL_RX_MAX_PACKET_LEN = 15'h2580; + parameter [7:0] CTL_RX_MIN_PACKET_LEN = 8'h40; + parameter [15:0] CTL_RX_OPCODE_GPP = 16'h0001; + parameter [15:0] CTL_RX_OPCODE_MAX_GCP = 16'hFFFF; + parameter [15:0] CTL_RX_OPCODE_MAX_PCP = 16'hFFFF; + parameter [15:0] CTL_RX_OPCODE_MIN_GCP = 16'h0000; + parameter [15:0] CTL_RX_OPCODE_MIN_PCP = 16'h0000; + parameter [15:0] CTL_RX_OPCODE_PPP = 16'h0001; + parameter [47:0] CTL_RX_PAUSE_DA_MCAST = 48'h0180C2000001; + parameter [47:0] CTL_RX_PAUSE_DA_UCAST = 48'h000000000000; + parameter [47:0] CTL_RX_PAUSE_SA = 48'h000000000000; + parameter CTL_RX_PROCESS_LFI = "FALSE"; + parameter [15:0] CTL_RX_VL_LENGTH_MINUS1 = 16'h3FFF; + parameter [63:0] CTL_RX_VL_MARKER_ID0 = 64'hC16821003E97DE00; + parameter [63:0] CTL_RX_VL_MARKER_ID1 = 64'h9D718E00628E7100; + parameter [63:0] CTL_RX_VL_MARKER_ID10 = 64'hFD6C990002936600; + parameter [63:0] CTL_RX_VL_MARKER_ID11 = 64'hB9915500466EAA00; + parameter [63:0] CTL_RX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00; + parameter [63:0] CTL_RX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200; + parameter [63:0] CTL_RX_VL_MARKER_ID14 = 64'h83C7CA007C383500; + parameter [63:0] CTL_RX_VL_MARKER_ID15 = 64'h3536CD00CAC93200; + parameter [63:0] CTL_RX_VL_MARKER_ID16 = 64'hC4314C003BCEB300; + parameter [63:0] CTL_RX_VL_MARKER_ID17 = 64'hADD6B70052294800; + parameter [63:0] CTL_RX_VL_MARKER_ID18 = 64'h5F662A00A099D500; + parameter [63:0] CTL_RX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00; + parameter [63:0] CTL_RX_VL_MARKER_ID2 = 64'h594BE800A6B41700; + parameter [63:0] CTL_RX_VL_MARKER_ID3 = 64'h4D957B00B26A8400; + parameter [63:0] CTL_RX_VL_MARKER_ID4 = 64'hF50709000AF8F600; + parameter [63:0] CTL_RX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00; + parameter [63:0] CTL_RX_VL_MARKER_ID6 = 64'h9A4A260065B5D900; + parameter [63:0] CTL_RX_VL_MARKER_ID7 = 64'h7B45660084BA9900; + parameter [63:0] CTL_RX_VL_MARKER_ID8 = 64'hA02476005FDB8900; + parameter [63:0] CTL_RX_VL_MARKER_ID9 = 64'h68C9FB0097360400; + parameter CTL_TEST_MODE_PIN_CHAR = "FALSE"; + parameter [47:0] CTL_TX_DA_GPP = 48'h0180C2000001; + parameter [47:0] CTL_TX_DA_PPP = 48'h0180C2000001; + parameter [15:0] CTL_TX_ETHERTYPE_GPP = 16'h8808; + parameter [15:0] CTL_TX_ETHERTYPE_PPP = 16'h8808; + parameter CTL_TX_FCS_INS_ENABLE = "TRUE"; + parameter CTL_TX_IGNORE_FCS = "FALSE"; + parameter [15:0] CTL_TX_OPCODE_GPP = 16'h0001; + parameter [15:0] CTL_TX_OPCODE_PPP = 16'h0001; + parameter CTL_TX_PTP_1STEP_ENABLE = "FALSE"; + parameter [10:0] CTL_TX_PTP_LATENCY_ADJUST = 11'h2C1; + parameter [47:0] CTL_TX_SA_GPP = 48'h000000000000; + parameter [47:0] CTL_TX_SA_PPP = 48'h000000000000; + parameter [15:0] CTL_TX_VL_LENGTH_MINUS1 = 16'h3FFF; + parameter [63:0] CTL_TX_VL_MARKER_ID0 = 64'hC16821003E97DE00; + parameter [63:0] CTL_TX_VL_MARKER_ID1 = 64'h9D718E00628E7100; + parameter [63:0] CTL_TX_VL_MARKER_ID10 = 64'hFD6C990002936600; + parameter [63:0] CTL_TX_VL_MARKER_ID11 = 64'hB9915500466EAA00; + parameter [63:0] CTL_TX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00; + parameter [63:0] CTL_TX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200; + parameter [63:0] CTL_TX_VL_MARKER_ID14 = 64'h83C7CA007C383500; + parameter [63:0] CTL_TX_VL_MARKER_ID15 = 64'h3536CD00CAC93200; + parameter [63:0] CTL_TX_VL_MARKER_ID16 = 64'hC4314C003BCEB300; + parameter [63:0] CTL_TX_VL_MARKER_ID17 = 64'hADD6B70052294800; + parameter [63:0] CTL_TX_VL_MARKER_ID18 = 64'h5F662A00A099D500; + parameter [63:0] CTL_TX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00; + parameter [63:0] CTL_TX_VL_MARKER_ID2 = 64'h594BE800A6B41700; + parameter [63:0] CTL_TX_VL_MARKER_ID3 = 64'h4D957B00B26A8400; + parameter [63:0] CTL_TX_VL_MARKER_ID4 = 64'hF50709000AF8F600; + parameter [63:0] CTL_TX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00; + parameter [63:0] CTL_TX_VL_MARKER_ID6 = 64'h9A4A260065B5D900; + parameter [63:0] CTL_TX_VL_MARKER_ID7 = 64'h7B45660084BA9900; + parameter [63:0] CTL_TX_VL_MARKER_ID8 = 64'hA02476005FDB8900; + parameter [63:0] CTL_TX_VL_MARKER_ID9 = 64'h68C9FB0097360400; + parameter SIM_VERSION = "2.0"; + parameter TEST_MODE_PIN_CHAR = "FALSE"; + output [15:0] DRP_DO; + output DRP_RDY; + output [127:0] RX_DATAOUT0; + output [127:0] RX_DATAOUT1; + output [127:0] RX_DATAOUT2; + output [127:0] RX_DATAOUT3; + output RX_ENAOUT0; + output RX_ENAOUT1; + output RX_ENAOUT2; + output RX_ENAOUT3; + output RX_EOPOUT0; + output RX_EOPOUT1; + output RX_EOPOUT2; + output RX_EOPOUT3; + output RX_ERROUT0; + output RX_ERROUT1; + output RX_ERROUT2; + output RX_ERROUT3; + output [6:0] RX_LANE_ALIGNER_FILL_0; + output [6:0] RX_LANE_ALIGNER_FILL_1; + output [6:0] RX_LANE_ALIGNER_FILL_10; + output [6:0] RX_LANE_ALIGNER_FILL_11; + output [6:0] RX_LANE_ALIGNER_FILL_12; + output [6:0] RX_LANE_ALIGNER_FILL_13; + output [6:0] RX_LANE_ALIGNER_FILL_14; + output [6:0] RX_LANE_ALIGNER_FILL_15; + output [6:0] RX_LANE_ALIGNER_FILL_16; + output [6:0] RX_LANE_ALIGNER_FILL_17; + output [6:0] RX_LANE_ALIGNER_FILL_18; + output [6:0] RX_LANE_ALIGNER_FILL_19; + output [6:0] RX_LANE_ALIGNER_FILL_2; + output [6:0] RX_LANE_ALIGNER_FILL_3; + output [6:0] RX_LANE_ALIGNER_FILL_4; + output [6:0] RX_LANE_ALIGNER_FILL_5; + output [6:0] RX_LANE_ALIGNER_FILL_6; + output [6:0] RX_LANE_ALIGNER_FILL_7; + output [6:0] RX_LANE_ALIGNER_FILL_8; + output [6:0] RX_LANE_ALIGNER_FILL_9; + output [3:0] RX_MTYOUT0; + output [3:0] RX_MTYOUT1; + output [3:0] RX_MTYOUT2; + output [3:0] RX_MTYOUT3; + output [4:0] RX_PTP_PCSLANE_OUT; + output [79:0] RX_PTP_TSTAMP_OUT; + output RX_SOPOUT0; + output RX_SOPOUT1; + output RX_SOPOUT2; + output RX_SOPOUT3; + output STAT_RX_ALIGNED; + output STAT_RX_ALIGNED_ERR; + output [6:0] STAT_RX_BAD_CODE; + output [3:0] STAT_RX_BAD_FCS; + output STAT_RX_BAD_PREAMBLE; + output STAT_RX_BAD_SFD; + output STAT_RX_BIP_ERR_0; + output STAT_RX_BIP_ERR_1; + output STAT_RX_BIP_ERR_10; + output STAT_RX_BIP_ERR_11; + output STAT_RX_BIP_ERR_12; + output STAT_RX_BIP_ERR_13; + output STAT_RX_BIP_ERR_14; + output STAT_RX_BIP_ERR_15; + output STAT_RX_BIP_ERR_16; + output STAT_RX_BIP_ERR_17; + output STAT_RX_BIP_ERR_18; + output STAT_RX_BIP_ERR_19; + output STAT_RX_BIP_ERR_2; + output STAT_RX_BIP_ERR_3; + output STAT_RX_BIP_ERR_4; + output STAT_RX_BIP_ERR_5; + output STAT_RX_BIP_ERR_6; + output STAT_RX_BIP_ERR_7; + output STAT_RX_BIP_ERR_8; + output STAT_RX_BIP_ERR_9; + output [19:0] STAT_RX_BLOCK_LOCK; + output STAT_RX_BROADCAST; + output [3:0] STAT_RX_FRAGMENT; + output [3:0] STAT_RX_FRAMING_ERR_0; + output [3:0] STAT_RX_FRAMING_ERR_1; + output [3:0] STAT_RX_FRAMING_ERR_10; + output [3:0] STAT_RX_FRAMING_ERR_11; + output [3:0] STAT_RX_FRAMING_ERR_12; + output [3:0] STAT_RX_FRAMING_ERR_13; + output [3:0] STAT_RX_FRAMING_ERR_14; + output [3:0] STAT_RX_FRAMING_ERR_15; + output [3:0] STAT_RX_FRAMING_ERR_16; + output [3:0] STAT_RX_FRAMING_ERR_17; + output [3:0] STAT_RX_FRAMING_ERR_18; + output [3:0] STAT_RX_FRAMING_ERR_19; + output [3:0] STAT_RX_FRAMING_ERR_2; + output [3:0] STAT_RX_FRAMING_ERR_3; + output [3:0] STAT_RX_FRAMING_ERR_4; + output [3:0] STAT_RX_FRAMING_ERR_5; + output [3:0] STAT_RX_FRAMING_ERR_6; + output [3:0] STAT_RX_FRAMING_ERR_7; + output [3:0] STAT_RX_FRAMING_ERR_8; + output [3:0] STAT_RX_FRAMING_ERR_9; + output STAT_RX_FRAMING_ERR_VALID_0; + output STAT_RX_FRAMING_ERR_VALID_1; + output STAT_RX_FRAMING_ERR_VALID_10; + output STAT_RX_FRAMING_ERR_VALID_11; + output STAT_RX_FRAMING_ERR_VALID_12; + output STAT_RX_FRAMING_ERR_VALID_13; + output STAT_RX_FRAMING_ERR_VALID_14; + output STAT_RX_FRAMING_ERR_VALID_15; + output STAT_RX_FRAMING_ERR_VALID_16; + output STAT_RX_FRAMING_ERR_VALID_17; + output STAT_RX_FRAMING_ERR_VALID_18; + output STAT_RX_FRAMING_ERR_VALID_19; + output STAT_RX_FRAMING_ERR_VALID_2; + output STAT_RX_FRAMING_ERR_VALID_3; + output STAT_RX_FRAMING_ERR_VALID_4; + output STAT_RX_FRAMING_ERR_VALID_5; + output STAT_RX_FRAMING_ERR_VALID_6; + output STAT_RX_FRAMING_ERR_VALID_7; + output STAT_RX_FRAMING_ERR_VALID_8; + output STAT_RX_FRAMING_ERR_VALID_9; + output STAT_RX_GOT_SIGNAL_OS; + output STAT_RX_HI_BER; + output STAT_RX_INRANGEERR; + output STAT_RX_INTERNAL_LOCAL_FAULT; + output STAT_RX_JABBER; + output [7:0] STAT_RX_LANE0_VLM_BIP7; + output STAT_RX_LANE0_VLM_BIP7_VALID; + output STAT_RX_LOCAL_FAULT; + output [19:0] STAT_RX_MF_ERR; + output [19:0] STAT_RX_MF_LEN_ERR; + output [19:0] STAT_RX_MF_REPEAT_ERR; + output STAT_RX_MISALIGNED; + output STAT_RX_MULTICAST; + output STAT_RX_OVERSIZE; + output STAT_RX_PACKET_1024_1518_BYTES; + output STAT_RX_PACKET_128_255_BYTES; + output STAT_RX_PACKET_1519_1522_BYTES; + output STAT_RX_PACKET_1523_1548_BYTES; + output STAT_RX_PACKET_1549_2047_BYTES; + output STAT_RX_PACKET_2048_4095_BYTES; + output STAT_RX_PACKET_256_511_BYTES; + output STAT_RX_PACKET_4096_8191_BYTES; + output STAT_RX_PACKET_512_1023_BYTES; + output STAT_RX_PACKET_64_BYTES; + output STAT_RX_PACKET_65_127_BYTES; + output STAT_RX_PACKET_8192_9215_BYTES; + output STAT_RX_PACKET_BAD_FCS; + output STAT_RX_PACKET_LARGE; + output [3:0] STAT_RX_PACKET_SMALL; + output STAT_RX_PAUSE; + output [15:0] STAT_RX_PAUSE_QUANTA0; + output [15:0] STAT_RX_PAUSE_QUANTA1; + output [15:0] STAT_RX_PAUSE_QUANTA2; + output [15:0] STAT_RX_PAUSE_QUANTA3; + output [15:0] STAT_RX_PAUSE_QUANTA4; + output [15:0] STAT_RX_PAUSE_QUANTA5; + output [15:0] STAT_RX_PAUSE_QUANTA6; + output [15:0] STAT_RX_PAUSE_QUANTA7; + output [15:0] STAT_RX_PAUSE_QUANTA8; + output [8:0] STAT_RX_PAUSE_REQ; + output [8:0] STAT_RX_PAUSE_VALID; + output STAT_RX_RECEIVED_LOCAL_FAULT; + output STAT_RX_REMOTE_FAULT; + output STAT_RX_STATUS; + output [3:0] STAT_RX_STOMPED_FCS; + output [19:0] STAT_RX_SYNCED; + output [19:0] STAT_RX_SYNCED_ERR; + output [2:0] STAT_RX_TEST_PATTERN_MISMATCH; + output STAT_RX_TOOLONG; + output [7:0] STAT_RX_TOTAL_BYTES; + output [13:0] STAT_RX_TOTAL_GOOD_BYTES; + output STAT_RX_TOTAL_GOOD_PACKETS; + output [3:0] STAT_RX_TOTAL_PACKETS; + output STAT_RX_TRUNCATED; + output [3:0] STAT_RX_UNDERSIZE; + output STAT_RX_UNICAST; + output STAT_RX_USER_PAUSE; + output STAT_RX_VLAN; + output [19:0] STAT_RX_VL_DEMUXED; + output [4:0] STAT_RX_VL_NUMBER_0; + output [4:0] STAT_RX_VL_NUMBER_1; + output [4:0] STAT_RX_VL_NUMBER_10; + output [4:0] STAT_RX_VL_NUMBER_11; + output [4:0] STAT_RX_VL_NUMBER_12; + output [4:0] STAT_RX_VL_NUMBER_13; + output [4:0] STAT_RX_VL_NUMBER_14; + output [4:0] STAT_RX_VL_NUMBER_15; + output [4:0] STAT_RX_VL_NUMBER_16; + output [4:0] STAT_RX_VL_NUMBER_17; + output [4:0] STAT_RX_VL_NUMBER_18; + output [4:0] STAT_RX_VL_NUMBER_19; + output [4:0] STAT_RX_VL_NUMBER_2; + output [4:0] STAT_RX_VL_NUMBER_3; + output [4:0] STAT_RX_VL_NUMBER_4; + output [4:0] STAT_RX_VL_NUMBER_5; + output [4:0] STAT_RX_VL_NUMBER_6; + output [4:0] STAT_RX_VL_NUMBER_7; + output [4:0] STAT_RX_VL_NUMBER_8; + output [4:0] STAT_RX_VL_NUMBER_9; + output STAT_TX_BAD_FCS; + output STAT_TX_BROADCAST; + output STAT_TX_FRAME_ERROR; + output STAT_TX_LOCAL_FAULT; + output STAT_TX_MULTICAST; + output STAT_TX_PACKET_1024_1518_BYTES; + output STAT_TX_PACKET_128_255_BYTES; + output STAT_TX_PACKET_1519_1522_BYTES; + output STAT_TX_PACKET_1523_1548_BYTES; + output STAT_TX_PACKET_1549_2047_BYTES; + output STAT_TX_PACKET_2048_4095_BYTES; + output STAT_TX_PACKET_256_511_BYTES; + output STAT_TX_PACKET_4096_8191_BYTES; + output STAT_TX_PACKET_512_1023_BYTES; + output STAT_TX_PACKET_64_BYTES; + output STAT_TX_PACKET_65_127_BYTES; + output STAT_TX_PACKET_8192_9215_BYTES; + output STAT_TX_PACKET_LARGE; + output STAT_TX_PACKET_SMALL; + output STAT_TX_PAUSE; + output [8:0] STAT_TX_PAUSE_VALID; + output STAT_TX_PTP_FIFO_READ_ERROR; + output STAT_TX_PTP_FIFO_WRITE_ERROR; + output [6:0] STAT_TX_TOTAL_BYTES; + output [13:0] STAT_TX_TOTAL_GOOD_BYTES; + output STAT_TX_TOTAL_GOOD_PACKETS; + output STAT_TX_TOTAL_PACKETS; + output STAT_TX_UNICAST; + output STAT_TX_USER_PAUSE; + output STAT_TX_VLAN; + output TX_OVFOUT; + output [4:0] TX_PTP_PCSLANE_OUT; + output [79:0] TX_PTP_TSTAMP_OUT; + output [15:0] TX_PTP_TSTAMP_TAG_OUT; + output TX_PTP_TSTAMP_VALID_OUT; + output TX_RDYOUT; + output [15:0] TX_SERDES_ALT_DATA0; + output [15:0] TX_SERDES_ALT_DATA1; + output [15:0] TX_SERDES_ALT_DATA2; + output [15:0] TX_SERDES_ALT_DATA3; + output [63:0] TX_SERDES_DATA0; + output [63:0] TX_SERDES_DATA1; + output [63:0] TX_SERDES_DATA2; + output [63:0] TX_SERDES_DATA3; + output [31:0] TX_SERDES_DATA4; + output [31:0] TX_SERDES_DATA5; + output [31:0] TX_SERDES_DATA6; + output [31:0] TX_SERDES_DATA7; + output [31:0] TX_SERDES_DATA8; + output [31:0] TX_SERDES_DATA9; + output TX_UNFOUT; + input CTL_CAUI4_MODE; + input CTL_RX_CHECK_ETYPE_GCP; + input CTL_RX_CHECK_ETYPE_GPP; + input CTL_RX_CHECK_ETYPE_PCP; + input CTL_RX_CHECK_ETYPE_PPP; + input CTL_RX_CHECK_MCAST_GCP; + input CTL_RX_CHECK_MCAST_GPP; + input CTL_RX_CHECK_MCAST_PCP; + input CTL_RX_CHECK_MCAST_PPP; + input CTL_RX_CHECK_OPCODE_GCP; + input CTL_RX_CHECK_OPCODE_GPP; + input CTL_RX_CHECK_OPCODE_PCP; + input CTL_RX_CHECK_OPCODE_PPP; + input CTL_RX_CHECK_SA_GCP; + input CTL_RX_CHECK_SA_GPP; + input CTL_RX_CHECK_SA_PCP; + input CTL_RX_CHECK_SA_PPP; + input CTL_RX_CHECK_UCAST_GCP; + input CTL_RX_CHECK_UCAST_GPP; + input CTL_RX_CHECK_UCAST_PCP; + input CTL_RX_CHECK_UCAST_PPP; + input CTL_RX_ENABLE; + input CTL_RX_ENABLE_GCP; + input CTL_RX_ENABLE_GPP; + input CTL_RX_ENABLE_PCP; + input CTL_RX_ENABLE_PPP; + input CTL_RX_FORCE_RESYNC; + input [8:0] CTL_RX_PAUSE_ACK; + input [8:0] CTL_RX_PAUSE_ENABLE; + input [79:0] CTL_RX_SYSTEMTIMERIN; + input CTL_RX_TEST_PATTERN; + input CTL_TX_ENABLE; + input CTL_TX_LANE0_VLM_BIP7_OVERRIDE; + input [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE; + input [8:0] CTL_TX_PAUSE_ENABLE; + input [15:0] CTL_TX_PAUSE_QUANTA0; + input [15:0] CTL_TX_PAUSE_QUANTA1; + input [15:0] CTL_TX_PAUSE_QUANTA2; + input [15:0] CTL_TX_PAUSE_QUANTA3; + input [15:0] CTL_TX_PAUSE_QUANTA4; + input [15:0] CTL_TX_PAUSE_QUANTA5; + input [15:0] CTL_TX_PAUSE_QUANTA6; + input [15:0] CTL_TX_PAUSE_QUANTA7; + input [15:0] CTL_TX_PAUSE_QUANTA8; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER0; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER1; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER2; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER3; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER4; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER5; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER6; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER7; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER8; + input [8:0] CTL_TX_PAUSE_REQ; + input CTL_TX_PTP_VLANE_ADJUST_MODE; + input CTL_TX_RESEND_PAUSE; + input CTL_TX_SEND_IDLE; + input CTL_TX_SEND_RFI; + input [79:0] CTL_TX_SYSTEMTIMERIN; + input CTL_TX_TEST_PATTERN; + input [9:0] DRP_ADDR; + input DRP_CLK; + input [15:0] DRP_DI; + input DRP_EN; + input DRP_WE; + input RX_CLK; + input RX_RESET; + input [15:0] RX_SERDES_ALT_DATA0; + input [15:0] RX_SERDES_ALT_DATA1; + input [15:0] RX_SERDES_ALT_DATA2; + input [15:0] RX_SERDES_ALT_DATA3; + input [9:0] RX_SERDES_CLK; + input [63:0] RX_SERDES_DATA0; + input [63:0] RX_SERDES_DATA1; + input [63:0] RX_SERDES_DATA2; + input [63:0] RX_SERDES_DATA3; + input [31:0] RX_SERDES_DATA4; + input [31:0] RX_SERDES_DATA5; + input [31:0] RX_SERDES_DATA6; + input [31:0] RX_SERDES_DATA7; + input [31:0] RX_SERDES_DATA8; + input [31:0] RX_SERDES_DATA9; + input [9:0] RX_SERDES_RESET; + input TX_CLK; + input [127:0] TX_DATAIN0; + input [127:0] TX_DATAIN1; + input [127:0] TX_DATAIN2; + input [127:0] TX_DATAIN3; + input TX_ENAIN0; + input TX_ENAIN1; + input TX_ENAIN2; + input TX_ENAIN3; + input TX_EOPIN0; + input TX_EOPIN1; + input TX_EOPIN2; + input TX_EOPIN3; + input TX_ERRIN0; + input TX_ERRIN1; + input TX_ERRIN2; + input TX_ERRIN3; + input [3:0] TX_MTYIN0; + input [3:0] TX_MTYIN1; + input [3:0] TX_MTYIN2; + input [3:0] TX_MTYIN3; + input [1:0] TX_PTP_1588OP_IN; + input [15:0] TX_PTP_CHKSUM_OFFSET_IN; + input [63:0] TX_PTP_RXTSTAMP_IN; + input [15:0] TX_PTP_TAG_FIELD_IN; + input [15:0] TX_PTP_TSTAMP_OFFSET_IN; + input TX_PTP_UPD_CHKSUM_IN; + input TX_RESET; + input TX_SOPIN0; + input TX_SOPIN1; + input TX_SOPIN2; + input TX_SOPIN3; +endmodule + +module CMACE4 (...); + parameter CTL_PTP_TRANSPCLK_MODE = "FALSE"; + parameter CTL_RX_CHECK_ACK = "TRUE"; + parameter CTL_RX_CHECK_PREAMBLE = "FALSE"; + parameter CTL_RX_CHECK_SFD = "FALSE"; + parameter CTL_RX_DELETE_FCS = "TRUE"; + parameter [15:0] CTL_RX_ETYPE_GCP = 16'h8808; + parameter [15:0] CTL_RX_ETYPE_GPP = 16'h8808; + parameter [15:0] CTL_RX_ETYPE_PCP = 16'h8808; + parameter [15:0] CTL_RX_ETYPE_PPP = 16'h8808; + parameter CTL_RX_FORWARD_CONTROL = "FALSE"; + parameter CTL_RX_IGNORE_FCS = "FALSE"; + parameter [14:0] CTL_RX_MAX_PACKET_LEN = 15'h2580; + parameter [7:0] CTL_RX_MIN_PACKET_LEN = 8'h40; + parameter [15:0] CTL_RX_OPCODE_GPP = 16'h0001; + parameter [15:0] CTL_RX_OPCODE_MAX_GCP = 16'hFFFF; + parameter [15:0] CTL_RX_OPCODE_MAX_PCP = 16'hFFFF; + parameter [15:0] CTL_RX_OPCODE_MIN_GCP = 16'h0000; + parameter [15:0] CTL_RX_OPCODE_MIN_PCP = 16'h0000; + parameter [15:0] CTL_RX_OPCODE_PPP = 16'h0001; + parameter [47:0] CTL_RX_PAUSE_DA_MCAST = 48'h0180C2000001; + parameter [47:0] CTL_RX_PAUSE_DA_UCAST = 48'h000000000000; + parameter [47:0] CTL_RX_PAUSE_SA = 48'h000000000000; + parameter CTL_RX_PROCESS_LFI = "FALSE"; + parameter [8:0] CTL_RX_RSFEC_AM_THRESHOLD = 9'h046; + parameter [1:0] CTL_RX_RSFEC_FILL_ADJUST = 2'h0; + parameter [15:0] CTL_RX_VL_LENGTH_MINUS1 = 16'h3FFF; + parameter [63:0] CTL_RX_VL_MARKER_ID0 = 64'hC16821003E97DE00; + parameter [63:0] CTL_RX_VL_MARKER_ID1 = 64'h9D718E00628E7100; + parameter [63:0] CTL_RX_VL_MARKER_ID10 = 64'hFD6C990002936600; + parameter [63:0] CTL_RX_VL_MARKER_ID11 = 64'hB9915500466EAA00; + parameter [63:0] CTL_RX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00; + parameter [63:0] CTL_RX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200; + parameter [63:0] CTL_RX_VL_MARKER_ID14 = 64'h83C7CA007C383500; + parameter [63:0] CTL_RX_VL_MARKER_ID15 = 64'h3536CD00CAC93200; + parameter [63:0] CTL_RX_VL_MARKER_ID16 = 64'hC4314C003BCEB300; + parameter [63:0] CTL_RX_VL_MARKER_ID17 = 64'hADD6B70052294800; + parameter [63:0] CTL_RX_VL_MARKER_ID18 = 64'h5F662A00A099D500; + parameter [63:0] CTL_RX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00; + parameter [63:0] CTL_RX_VL_MARKER_ID2 = 64'h594BE800A6B41700; + parameter [63:0] CTL_RX_VL_MARKER_ID3 = 64'h4D957B00B26A8400; + parameter [63:0] CTL_RX_VL_MARKER_ID4 = 64'hF50709000AF8F600; + parameter [63:0] CTL_RX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00; + parameter [63:0] CTL_RX_VL_MARKER_ID6 = 64'h9A4A260065B5D900; + parameter [63:0] CTL_RX_VL_MARKER_ID7 = 64'h7B45660084BA9900; + parameter [63:0] CTL_RX_VL_MARKER_ID8 = 64'hA02476005FDB8900; + parameter [63:0] CTL_RX_VL_MARKER_ID9 = 64'h68C9FB0097360400; + parameter CTL_TEST_MODE_PIN_CHAR = "FALSE"; + parameter CTL_TX_CUSTOM_PREAMBLE_ENABLE = "FALSE"; + parameter [47:0] CTL_TX_DA_GPP = 48'h0180C2000001; + parameter [47:0] CTL_TX_DA_PPP = 48'h0180C2000001; + parameter [15:0] CTL_TX_ETHERTYPE_GPP = 16'h8808; + parameter [15:0] CTL_TX_ETHERTYPE_PPP = 16'h8808; + parameter CTL_TX_FCS_INS_ENABLE = "TRUE"; + parameter CTL_TX_IGNORE_FCS = "FALSE"; + parameter [3:0] CTL_TX_IPG_VALUE = 4'hC; + parameter [15:0] CTL_TX_OPCODE_GPP = 16'h0001; + parameter [15:0] CTL_TX_OPCODE_PPP = 16'h0001; + parameter CTL_TX_PTP_1STEP_ENABLE = "FALSE"; + parameter [10:0] CTL_TX_PTP_LATENCY_ADJUST = 11'h2C1; + parameter [47:0] CTL_TX_SA_GPP = 48'h000000000000; + parameter [47:0] CTL_TX_SA_PPP = 48'h000000000000; + parameter [15:0] CTL_TX_VL_LENGTH_MINUS1 = 16'h3FFF; + parameter [63:0] CTL_TX_VL_MARKER_ID0 = 64'hC16821003E97DE00; + parameter [63:0] CTL_TX_VL_MARKER_ID1 = 64'h9D718E00628E7100; + parameter [63:0] CTL_TX_VL_MARKER_ID10 = 64'hFD6C990002936600; + parameter [63:0] CTL_TX_VL_MARKER_ID11 = 64'hB9915500466EAA00; + parameter [63:0] CTL_TX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00; + parameter [63:0] CTL_TX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200; + parameter [63:0] CTL_TX_VL_MARKER_ID14 = 64'h83C7CA007C383500; + parameter [63:0] CTL_TX_VL_MARKER_ID15 = 64'h3536CD00CAC93200; + parameter [63:0] CTL_TX_VL_MARKER_ID16 = 64'hC4314C003BCEB300; + parameter [63:0] CTL_TX_VL_MARKER_ID17 = 64'hADD6B70052294800; + parameter [63:0] CTL_TX_VL_MARKER_ID18 = 64'h5F662A00A099D500; + parameter [63:0] CTL_TX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00; + parameter [63:0] CTL_TX_VL_MARKER_ID2 = 64'h594BE800A6B41700; + parameter [63:0] CTL_TX_VL_MARKER_ID3 = 64'h4D957B00B26A8400; + parameter [63:0] CTL_TX_VL_MARKER_ID4 = 64'hF50709000AF8F600; + parameter [63:0] CTL_TX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00; + parameter [63:0] CTL_TX_VL_MARKER_ID6 = 64'h9A4A260065B5D900; + parameter [63:0] CTL_TX_VL_MARKER_ID7 = 64'h7B45660084BA9900; + parameter [63:0] CTL_TX_VL_MARKER_ID8 = 64'hA02476005FDB8900; + parameter [63:0] CTL_TX_VL_MARKER_ID9 = 64'h68C9FB0097360400; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter TEST_MODE_PIN_CHAR = "FALSE"; + output [15:0] DRP_DO; + output DRP_RDY; + output [329:0] RSFEC_BYPASS_RX_DOUT; + output RSFEC_BYPASS_RX_DOUT_CW_START; + output RSFEC_BYPASS_RX_DOUT_VALID; + output [329:0] RSFEC_BYPASS_TX_DOUT; + output RSFEC_BYPASS_TX_DOUT_CW_START; + output RSFEC_BYPASS_TX_DOUT_VALID; + output [127:0] RX_DATAOUT0; + output [127:0] RX_DATAOUT1; + output [127:0] RX_DATAOUT2; + output [127:0] RX_DATAOUT3; + output RX_ENAOUT0; + output RX_ENAOUT1; + output RX_ENAOUT2; + output RX_ENAOUT3; + output RX_EOPOUT0; + output RX_EOPOUT1; + output RX_EOPOUT2; + output RX_EOPOUT3; + output RX_ERROUT0; + output RX_ERROUT1; + output RX_ERROUT2; + output RX_ERROUT3; + output [6:0] RX_LANE_ALIGNER_FILL_0; + output [6:0] RX_LANE_ALIGNER_FILL_1; + output [6:0] RX_LANE_ALIGNER_FILL_10; + output [6:0] RX_LANE_ALIGNER_FILL_11; + output [6:0] RX_LANE_ALIGNER_FILL_12; + output [6:0] RX_LANE_ALIGNER_FILL_13; + output [6:0] RX_LANE_ALIGNER_FILL_14; + output [6:0] RX_LANE_ALIGNER_FILL_15; + output [6:0] RX_LANE_ALIGNER_FILL_16; + output [6:0] RX_LANE_ALIGNER_FILL_17; + output [6:0] RX_LANE_ALIGNER_FILL_18; + output [6:0] RX_LANE_ALIGNER_FILL_19; + output [6:0] RX_LANE_ALIGNER_FILL_2; + output [6:0] RX_LANE_ALIGNER_FILL_3; + output [6:0] RX_LANE_ALIGNER_FILL_4; + output [6:0] RX_LANE_ALIGNER_FILL_5; + output [6:0] RX_LANE_ALIGNER_FILL_6; + output [6:0] RX_LANE_ALIGNER_FILL_7; + output [6:0] RX_LANE_ALIGNER_FILL_8; + output [6:0] RX_LANE_ALIGNER_FILL_9; + output [3:0] RX_MTYOUT0; + output [3:0] RX_MTYOUT1; + output [3:0] RX_MTYOUT2; + output [3:0] RX_MTYOUT3; + output [7:0] RX_OTN_BIP8_0; + output [7:0] RX_OTN_BIP8_1; + output [7:0] RX_OTN_BIP8_2; + output [7:0] RX_OTN_BIP8_3; + output [7:0] RX_OTN_BIP8_4; + output [65:0] RX_OTN_DATA_0; + output [65:0] RX_OTN_DATA_1; + output [65:0] RX_OTN_DATA_2; + output [65:0] RX_OTN_DATA_3; + output [65:0] RX_OTN_DATA_4; + output RX_OTN_ENA; + output RX_OTN_LANE0; + output RX_OTN_VLMARKER; + output [55:0] RX_PREOUT; + output [4:0] RX_PTP_PCSLANE_OUT; + output [79:0] RX_PTP_TSTAMP_OUT; + output RX_SOPOUT0; + output RX_SOPOUT1; + output RX_SOPOUT2; + output RX_SOPOUT3; + output STAT_RX_ALIGNED; + output STAT_RX_ALIGNED_ERR; + output [2:0] STAT_RX_BAD_CODE; + output [2:0] STAT_RX_BAD_FCS; + output STAT_RX_BAD_PREAMBLE; + output STAT_RX_BAD_SFD; + output STAT_RX_BIP_ERR_0; + output STAT_RX_BIP_ERR_1; + output STAT_RX_BIP_ERR_10; + output STAT_RX_BIP_ERR_11; + output STAT_RX_BIP_ERR_12; + output STAT_RX_BIP_ERR_13; + output STAT_RX_BIP_ERR_14; + output STAT_RX_BIP_ERR_15; + output STAT_RX_BIP_ERR_16; + output STAT_RX_BIP_ERR_17; + output STAT_RX_BIP_ERR_18; + output STAT_RX_BIP_ERR_19; + output STAT_RX_BIP_ERR_2; + output STAT_RX_BIP_ERR_3; + output STAT_RX_BIP_ERR_4; + output STAT_RX_BIP_ERR_5; + output STAT_RX_BIP_ERR_6; + output STAT_RX_BIP_ERR_7; + output STAT_RX_BIP_ERR_8; + output STAT_RX_BIP_ERR_9; + output [19:0] STAT_RX_BLOCK_LOCK; + output STAT_RX_BROADCAST; + output [2:0] STAT_RX_FRAGMENT; + output [1:0] STAT_RX_FRAMING_ERR_0; + output [1:0] STAT_RX_FRAMING_ERR_1; + output [1:0] STAT_RX_FRAMING_ERR_10; + output [1:0] STAT_RX_FRAMING_ERR_11; + output [1:0] STAT_RX_FRAMING_ERR_12; + output [1:0] STAT_RX_FRAMING_ERR_13; + output [1:0] STAT_RX_FRAMING_ERR_14; + output [1:0] STAT_RX_FRAMING_ERR_15; + output [1:0] STAT_RX_FRAMING_ERR_16; + output [1:0] STAT_RX_FRAMING_ERR_17; + output [1:0] STAT_RX_FRAMING_ERR_18; + output [1:0] STAT_RX_FRAMING_ERR_19; + output [1:0] STAT_RX_FRAMING_ERR_2; + output [1:0] STAT_RX_FRAMING_ERR_3; + output [1:0] STAT_RX_FRAMING_ERR_4; + output [1:0] STAT_RX_FRAMING_ERR_5; + output [1:0] STAT_RX_FRAMING_ERR_6; + output [1:0] STAT_RX_FRAMING_ERR_7; + output [1:0] STAT_RX_FRAMING_ERR_8; + output [1:0] STAT_RX_FRAMING_ERR_9; + output STAT_RX_FRAMING_ERR_VALID_0; + output STAT_RX_FRAMING_ERR_VALID_1; + output STAT_RX_FRAMING_ERR_VALID_10; + output STAT_RX_FRAMING_ERR_VALID_11; + output STAT_RX_FRAMING_ERR_VALID_12; + output STAT_RX_FRAMING_ERR_VALID_13; + output STAT_RX_FRAMING_ERR_VALID_14; + output STAT_RX_FRAMING_ERR_VALID_15; + output STAT_RX_FRAMING_ERR_VALID_16; + output STAT_RX_FRAMING_ERR_VALID_17; + output STAT_RX_FRAMING_ERR_VALID_18; + output STAT_RX_FRAMING_ERR_VALID_19; + output STAT_RX_FRAMING_ERR_VALID_2; + output STAT_RX_FRAMING_ERR_VALID_3; + output STAT_RX_FRAMING_ERR_VALID_4; + output STAT_RX_FRAMING_ERR_VALID_5; + output STAT_RX_FRAMING_ERR_VALID_6; + output STAT_RX_FRAMING_ERR_VALID_7; + output STAT_RX_FRAMING_ERR_VALID_8; + output STAT_RX_FRAMING_ERR_VALID_9; + output STAT_RX_GOT_SIGNAL_OS; + output STAT_RX_HI_BER; + output STAT_RX_INRANGEERR; + output STAT_RX_INTERNAL_LOCAL_FAULT; + output STAT_RX_JABBER; + output [7:0] STAT_RX_LANE0_VLM_BIP7; + output STAT_RX_LANE0_VLM_BIP7_VALID; + output STAT_RX_LOCAL_FAULT; + output [19:0] STAT_RX_MF_ERR; + output [19:0] STAT_RX_MF_LEN_ERR; + output [19:0] STAT_RX_MF_REPEAT_ERR; + output STAT_RX_MISALIGNED; + output STAT_RX_MULTICAST; + output STAT_RX_OVERSIZE; + output STAT_RX_PACKET_1024_1518_BYTES; + output STAT_RX_PACKET_128_255_BYTES; + output STAT_RX_PACKET_1519_1522_BYTES; + output STAT_RX_PACKET_1523_1548_BYTES; + output STAT_RX_PACKET_1549_2047_BYTES; + output STAT_RX_PACKET_2048_4095_BYTES; + output STAT_RX_PACKET_256_511_BYTES; + output STAT_RX_PACKET_4096_8191_BYTES; + output STAT_RX_PACKET_512_1023_BYTES; + output STAT_RX_PACKET_64_BYTES; + output STAT_RX_PACKET_65_127_BYTES; + output STAT_RX_PACKET_8192_9215_BYTES; + output STAT_RX_PACKET_BAD_FCS; + output STAT_RX_PACKET_LARGE; + output [2:0] STAT_RX_PACKET_SMALL; + output STAT_RX_PAUSE; + output [15:0] STAT_RX_PAUSE_QUANTA0; + output [15:0] STAT_RX_PAUSE_QUANTA1; + output [15:0] STAT_RX_PAUSE_QUANTA2; + output [15:0] STAT_RX_PAUSE_QUANTA3; + output [15:0] STAT_RX_PAUSE_QUANTA4; + output [15:0] STAT_RX_PAUSE_QUANTA5; + output [15:0] STAT_RX_PAUSE_QUANTA6; + output [15:0] STAT_RX_PAUSE_QUANTA7; + output [15:0] STAT_RX_PAUSE_QUANTA8; + output [8:0] STAT_RX_PAUSE_REQ; + output [8:0] STAT_RX_PAUSE_VALID; + output STAT_RX_RECEIVED_LOCAL_FAULT; + output STAT_RX_REMOTE_FAULT; + output STAT_RX_RSFEC_AM_LOCK0; + output STAT_RX_RSFEC_AM_LOCK1; + output STAT_RX_RSFEC_AM_LOCK2; + output STAT_RX_RSFEC_AM_LOCK3; + output STAT_RX_RSFEC_CORRECTED_CW_INC; + output STAT_RX_RSFEC_CW_INC; + output [2:0] STAT_RX_RSFEC_ERR_COUNT0_INC; + output [2:0] STAT_RX_RSFEC_ERR_COUNT1_INC; + output [2:0] STAT_RX_RSFEC_ERR_COUNT2_INC; + output [2:0] STAT_RX_RSFEC_ERR_COUNT3_INC; + output STAT_RX_RSFEC_HI_SER; + output STAT_RX_RSFEC_LANE_ALIGNMENT_STATUS; + output [13:0] STAT_RX_RSFEC_LANE_FILL_0; + output [13:0] STAT_RX_RSFEC_LANE_FILL_1; + output [13:0] STAT_RX_RSFEC_LANE_FILL_2; + output [13:0] STAT_RX_RSFEC_LANE_FILL_3; + output [7:0] STAT_RX_RSFEC_LANE_MAPPING; + output [31:0] STAT_RX_RSFEC_RSVD; + output STAT_RX_RSFEC_UNCORRECTED_CW_INC; + output STAT_RX_STATUS; + output [2:0] STAT_RX_STOMPED_FCS; + output [19:0] STAT_RX_SYNCED; + output [19:0] STAT_RX_SYNCED_ERR; + output [2:0] STAT_RX_TEST_PATTERN_MISMATCH; + output STAT_RX_TOOLONG; + output [6:0] STAT_RX_TOTAL_BYTES; + output [13:0] STAT_RX_TOTAL_GOOD_BYTES; + output STAT_RX_TOTAL_GOOD_PACKETS; + output [2:0] STAT_RX_TOTAL_PACKETS; + output STAT_RX_TRUNCATED; + output [2:0] STAT_RX_UNDERSIZE; + output STAT_RX_UNICAST; + output STAT_RX_USER_PAUSE; + output STAT_RX_VLAN; + output [19:0] STAT_RX_VL_DEMUXED; + output [4:0] STAT_RX_VL_NUMBER_0; + output [4:0] STAT_RX_VL_NUMBER_1; + output [4:0] STAT_RX_VL_NUMBER_10; + output [4:0] STAT_RX_VL_NUMBER_11; + output [4:0] STAT_RX_VL_NUMBER_12; + output [4:0] STAT_RX_VL_NUMBER_13; + output [4:0] STAT_RX_VL_NUMBER_14; + output [4:0] STAT_RX_VL_NUMBER_15; + output [4:0] STAT_RX_VL_NUMBER_16; + output [4:0] STAT_RX_VL_NUMBER_17; + output [4:0] STAT_RX_VL_NUMBER_18; + output [4:0] STAT_RX_VL_NUMBER_19; + output [4:0] STAT_RX_VL_NUMBER_2; + output [4:0] STAT_RX_VL_NUMBER_3; + output [4:0] STAT_RX_VL_NUMBER_4; + output [4:0] STAT_RX_VL_NUMBER_5; + output [4:0] STAT_RX_VL_NUMBER_6; + output [4:0] STAT_RX_VL_NUMBER_7; + output [4:0] STAT_RX_VL_NUMBER_8; + output [4:0] STAT_RX_VL_NUMBER_9; + output STAT_TX_BAD_FCS; + output STAT_TX_BROADCAST; + output STAT_TX_FRAME_ERROR; + output STAT_TX_LOCAL_FAULT; + output STAT_TX_MULTICAST; + output STAT_TX_PACKET_1024_1518_BYTES; + output STAT_TX_PACKET_128_255_BYTES; + output STAT_TX_PACKET_1519_1522_BYTES; + output STAT_TX_PACKET_1523_1548_BYTES; + output STAT_TX_PACKET_1549_2047_BYTES; + output STAT_TX_PACKET_2048_4095_BYTES; + output STAT_TX_PACKET_256_511_BYTES; + output STAT_TX_PACKET_4096_8191_BYTES; + output STAT_TX_PACKET_512_1023_BYTES; + output STAT_TX_PACKET_64_BYTES; + output STAT_TX_PACKET_65_127_BYTES; + output STAT_TX_PACKET_8192_9215_BYTES; + output STAT_TX_PACKET_LARGE; + output STAT_TX_PACKET_SMALL; + output STAT_TX_PAUSE; + output [8:0] STAT_TX_PAUSE_VALID; + output STAT_TX_PTP_FIFO_READ_ERROR; + output STAT_TX_PTP_FIFO_WRITE_ERROR; + output [5:0] STAT_TX_TOTAL_BYTES; + output [13:0] STAT_TX_TOTAL_GOOD_BYTES; + output STAT_TX_TOTAL_GOOD_PACKETS; + output STAT_TX_TOTAL_PACKETS; + output STAT_TX_UNICAST; + output STAT_TX_USER_PAUSE; + output STAT_TX_VLAN; + output TX_OVFOUT; + output [4:0] TX_PTP_PCSLANE_OUT; + output [79:0] TX_PTP_TSTAMP_OUT; + output [15:0] TX_PTP_TSTAMP_TAG_OUT; + output TX_PTP_TSTAMP_VALID_OUT; + output TX_RDYOUT; + output [15:0] TX_SERDES_ALT_DATA0; + output [15:0] TX_SERDES_ALT_DATA1; + output [15:0] TX_SERDES_ALT_DATA2; + output [15:0] TX_SERDES_ALT_DATA3; + output [63:0] TX_SERDES_DATA0; + output [63:0] TX_SERDES_DATA1; + output [63:0] TX_SERDES_DATA2; + output [63:0] TX_SERDES_DATA3; + output [31:0] TX_SERDES_DATA4; + output [31:0] TX_SERDES_DATA5; + output [31:0] TX_SERDES_DATA6; + output [31:0] TX_SERDES_DATA7; + output [31:0] TX_SERDES_DATA8; + output [31:0] TX_SERDES_DATA9; + output TX_UNFOUT; + input CTL_CAUI4_MODE; + input CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE; + input CTL_RSFEC_IEEE_ERROR_INDICATION_MODE; + input CTL_RX_CHECK_ETYPE_GCP; + input CTL_RX_CHECK_ETYPE_GPP; + input CTL_RX_CHECK_ETYPE_PCP; + input CTL_RX_CHECK_ETYPE_PPP; + input CTL_RX_CHECK_MCAST_GCP; + input CTL_RX_CHECK_MCAST_GPP; + input CTL_RX_CHECK_MCAST_PCP; + input CTL_RX_CHECK_MCAST_PPP; + input CTL_RX_CHECK_OPCODE_GCP; + input CTL_RX_CHECK_OPCODE_GPP; + input CTL_RX_CHECK_OPCODE_PCP; + input CTL_RX_CHECK_OPCODE_PPP; + input CTL_RX_CHECK_SA_GCP; + input CTL_RX_CHECK_SA_GPP; + input CTL_RX_CHECK_SA_PCP; + input CTL_RX_CHECK_SA_PPP; + input CTL_RX_CHECK_UCAST_GCP; + input CTL_RX_CHECK_UCAST_GPP; + input CTL_RX_CHECK_UCAST_PCP; + input CTL_RX_CHECK_UCAST_PPP; + input CTL_RX_ENABLE; + input CTL_RX_ENABLE_GCP; + input CTL_RX_ENABLE_GPP; + input CTL_RX_ENABLE_PCP; + input CTL_RX_ENABLE_PPP; + input CTL_RX_FORCE_RESYNC; + input [8:0] CTL_RX_PAUSE_ACK; + input [8:0] CTL_RX_PAUSE_ENABLE; + input CTL_RX_RSFEC_ENABLE; + input CTL_RX_RSFEC_ENABLE_CORRECTION; + input CTL_RX_RSFEC_ENABLE_INDICATION; + input [79:0] CTL_RX_SYSTEMTIMERIN; + input CTL_RX_TEST_PATTERN; + input CTL_TX_ENABLE; + input CTL_TX_LANE0_VLM_BIP7_OVERRIDE; + input [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE; + input [8:0] CTL_TX_PAUSE_ENABLE; + input [15:0] CTL_TX_PAUSE_QUANTA0; + input [15:0] CTL_TX_PAUSE_QUANTA1; + input [15:0] CTL_TX_PAUSE_QUANTA2; + input [15:0] CTL_TX_PAUSE_QUANTA3; + input [15:0] CTL_TX_PAUSE_QUANTA4; + input [15:0] CTL_TX_PAUSE_QUANTA5; + input [15:0] CTL_TX_PAUSE_QUANTA6; + input [15:0] CTL_TX_PAUSE_QUANTA7; + input [15:0] CTL_TX_PAUSE_QUANTA8; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER0; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER1; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER2; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER3; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER4; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER5; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER6; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER7; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER8; + input [8:0] CTL_TX_PAUSE_REQ; + input CTL_TX_PTP_VLANE_ADJUST_MODE; + input CTL_TX_RESEND_PAUSE; + input CTL_TX_RSFEC_ENABLE; + input CTL_TX_SEND_IDLE; + input CTL_TX_SEND_LFI; + input CTL_TX_SEND_RFI; + input [79:0] CTL_TX_SYSTEMTIMERIN; + input CTL_TX_TEST_PATTERN; + input [9:0] DRP_ADDR; + input DRP_CLK; + input [15:0] DRP_DI; + input DRP_EN; + input DRP_WE; + input [329:0] RSFEC_BYPASS_RX_DIN; + input RSFEC_BYPASS_RX_DIN_CW_START; + input [329:0] RSFEC_BYPASS_TX_DIN; + input RSFEC_BYPASS_TX_DIN_CW_START; + input RX_CLK; + input RX_RESET; + input [15:0] RX_SERDES_ALT_DATA0; + input [15:0] RX_SERDES_ALT_DATA1; + input [15:0] RX_SERDES_ALT_DATA2; + input [15:0] RX_SERDES_ALT_DATA3; + input [9:0] RX_SERDES_CLK; + input [63:0] RX_SERDES_DATA0; + input [63:0] RX_SERDES_DATA1; + input [63:0] RX_SERDES_DATA2; + input [63:0] RX_SERDES_DATA3; + input [31:0] RX_SERDES_DATA4; + input [31:0] RX_SERDES_DATA5; + input [31:0] RX_SERDES_DATA6; + input [31:0] RX_SERDES_DATA7; + input [31:0] RX_SERDES_DATA8; + input [31:0] RX_SERDES_DATA9; + input [9:0] RX_SERDES_RESET; + input TX_CLK; + input [127:0] TX_DATAIN0; + input [127:0] TX_DATAIN1; + input [127:0] TX_DATAIN2; + input [127:0] TX_DATAIN3; + input TX_ENAIN0; + input TX_ENAIN1; + input TX_ENAIN2; + input TX_ENAIN3; + input TX_EOPIN0; + input TX_EOPIN1; + input TX_EOPIN2; + input TX_EOPIN3; + input TX_ERRIN0; + input TX_ERRIN1; + input TX_ERRIN2; + input TX_ERRIN3; + input [3:0] TX_MTYIN0; + input [3:0] TX_MTYIN1; + input [3:0] TX_MTYIN2; + input [3:0] TX_MTYIN3; + input [55:0] TX_PREIN; + input [1:0] TX_PTP_1588OP_IN; + input [15:0] TX_PTP_CHKSUM_OFFSET_IN; + input [63:0] TX_PTP_RXTSTAMP_IN; + input [15:0] TX_PTP_TAG_FIELD_IN; + input [15:0] TX_PTP_TSTAMP_OFFSET_IN; + input TX_PTP_UPD_CHKSUM_IN; + input TX_RESET; + input TX_SOPIN0; + input TX_SOPIN1; + input TX_SOPIN2; + input TX_SOPIN3; +endmodule + +module MCB (...); + parameter integer ARB_NUM_TIME_SLOTS = 12; + parameter [17:0] ARB_TIME_SLOT_0 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_1 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_10 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_11 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_2 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_3 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_4 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_5 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_6 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_7 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_8 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_9 = 18'b111111111111111111; + parameter [2:0] CAL_BA = 3'h0; + parameter CAL_BYPASS = "YES"; + parameter [11:0] CAL_CA = 12'h000; + parameter CAL_CALIBRATION_MODE = "NOCALIBRATION"; + parameter integer CAL_CLK_DIV = 1; + parameter CAL_DELAY = "QUARTER"; + parameter [14:0] CAL_RA = 15'h0000; + parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN"; + parameter integer MEM_BA_SIZE = 3; + parameter integer MEM_BURST_LEN = 8; + parameter integer MEM_CAS_LATENCY = 4; + parameter integer MEM_CA_SIZE = 11; + parameter MEM_DDR1_2_ODS = "FULL"; + parameter MEM_DDR2_3_HIGH_TEMP_SR = "NORMAL"; + parameter MEM_DDR2_3_PA_SR = "FULL"; + parameter integer MEM_DDR2_ADD_LATENCY = 0; + parameter MEM_DDR2_DIFF_DQS_EN = "YES"; + parameter MEM_DDR2_RTT = "50OHMS"; + parameter integer MEM_DDR2_WRT_RECOVERY = 4; + parameter MEM_DDR3_ADD_LATENCY = "OFF"; + parameter MEM_DDR3_AUTO_SR = "ENABLED"; + parameter integer MEM_DDR3_CAS_LATENCY = 7; + parameter integer MEM_DDR3_CAS_WR_LATENCY = 5; + parameter MEM_DDR3_DYN_WRT_ODT = "OFF"; + parameter MEM_DDR3_ODS = "DIV7"; + parameter MEM_DDR3_RTT = "DIV2"; + parameter integer MEM_DDR3_WRT_RECOVERY = 7; + parameter MEM_MDDR_ODS = "FULL"; + parameter MEM_MOBILE_PA_SR = "FULL"; + parameter integer MEM_MOBILE_TC_SR = 0; + parameter integer MEM_RAS_VAL = 0; + parameter integer MEM_RA_SIZE = 13; + parameter integer MEM_RCD_VAL = 1; + parameter integer MEM_REFI_VAL = 0; + parameter integer MEM_RFC_VAL = 0; + parameter integer MEM_RP_VAL = 0; + parameter integer MEM_RTP_VAL = 0; + parameter MEM_TYPE = "DDR3"; + parameter integer MEM_WIDTH = 4; + parameter integer MEM_WR_VAL = 0; + parameter integer MEM_WTR_VAL = 3; + parameter PORT_CONFIG = "B32_B32_B32_B32"; + output CAS; + output CKE; + output DQIOWEN0; + output DQSIOWEN90N; + output DQSIOWEN90P; + output IOIDRPADD; + output IOIDRPBROADCAST; + output IOIDRPCLK; + output IOIDRPCS; + output IOIDRPSDO; + output IOIDRPTRAIN; + output IOIDRPUPDATE; + output LDMN; + output LDMP; + output ODT; + output P0CMDEMPTY; + output P0CMDFULL; + output P0RDEMPTY; + output P0RDERROR; + output P0RDFULL; + output P0RDOVERFLOW; + output P0WREMPTY; + output P0WRERROR; + output P0WRFULL; + output P0WRUNDERRUN; + output P1CMDEMPTY; + output P1CMDFULL; + output P1RDEMPTY; + output P1RDERROR; + output P1RDFULL; + output P1RDOVERFLOW; + output P1WREMPTY; + output P1WRERROR; + output P1WRFULL; + output P1WRUNDERRUN; + output P2CMDEMPTY; + output P2CMDFULL; + output P2EMPTY; + output P2ERROR; + output P2FULL; + output P2RDOVERFLOW; + output P2WRUNDERRUN; + output P3CMDEMPTY; + output P3CMDFULL; + output P3EMPTY; + output P3ERROR; + output P3FULL; + output P3RDOVERFLOW; + output P3WRUNDERRUN; + output P4CMDEMPTY; + output P4CMDFULL; + output P4EMPTY; + output P4ERROR; + output P4FULL; + output P4RDOVERFLOW; + output P4WRUNDERRUN; + output P5CMDEMPTY; + output P5CMDFULL; + output P5EMPTY; + output P5ERROR; + output P5FULL; + output P5RDOVERFLOW; + output P5WRUNDERRUN; + output RAS; + output RST; + output SELFREFRESHMODE; + output UDMN; + output UDMP; + output UOCALSTART; + output UOCMDREADYIN; + output UODATAVALID; + output UODONECAL; + output UOREFRSHFLAG; + output UOSDO; + output WE; + output [14:0] ADDR; + output [15:0] DQON; + output [15:0] DQOP; + output [2:0] BA; + output [31:0] P0RDDATA; + output [31:0] P1RDDATA; + output [31:0] P2RDDATA; + output [31:0] P3RDDATA; + output [31:0] P4RDDATA; + output [31:0] P5RDDATA; + output [31:0] STATUS; + output [4:0] IOIDRPADDR; + output [6:0] P0RDCOUNT; + output [6:0] P0WRCOUNT; + output [6:0] P1RDCOUNT; + output [6:0] P1WRCOUNT; + output [6:0] P2COUNT; + output [6:0] P3COUNT; + output [6:0] P4COUNT; + output [6:0] P5COUNT; + output [7:0] UODATA; + input DQSIOIN; + input DQSIOIP; + input IOIDRPSDI; + input P0ARBEN; + input P0CMDCLK; + input P0CMDEN; + input P0RDCLK; + input P0RDEN; + input P0WRCLK; + input P0WREN; + input P1ARBEN; + input P1CMDCLK; + input P1CMDEN; + input P1RDCLK; + input P1RDEN; + input P1WRCLK; + input P1WREN; + input P2ARBEN; + input P2CLK; + input P2CMDCLK; + input P2CMDEN; + input P2EN; + input P3ARBEN; + input P3CLK; + input P3CMDCLK; + input P3CMDEN; + input P3EN; + input P4ARBEN; + input P4CLK; + input P4CMDCLK; + input P4CMDEN; + input P4EN; + input P5ARBEN; + input P5CLK; + input P5CMDCLK; + input P5CMDEN; + input P5EN; + input PLLLOCK; + input RECAL; + input SELFREFRESHENTER; + input SYSRST; + input UDQSIOIN; + input UDQSIOIP; + input UIADD; + input UIBROADCAST; + input UICLK; + input UICMD; + input UICMDEN; + input UICMDIN; + input UICS; + input UIDONECAL; + input UIDQLOWERDEC; + input UIDQLOWERINC; + input UIDQUPPERDEC; + input UIDQUPPERINC; + input UIDRPUPDATE; + input UILDQSDEC; + input UILDQSINC; + input UIREAD; + input UISDI; + input UIUDQSDEC; + input UIUDQSINC; + input [11:0] P0CMDCA; + input [11:0] P1CMDCA; + input [11:0] P2CMDCA; + input [11:0] P3CMDCA; + input [11:0] P4CMDCA; + input [11:0] P5CMDCA; + input [14:0] P0CMDRA; + input [14:0] P1CMDRA; + input [14:0] P2CMDRA; + input [14:0] P3CMDRA; + input [14:0] P4CMDRA; + input [14:0] P5CMDRA; + input [15:0] DQI; + input [1:0] PLLCE; + input [1:0] PLLCLK; + input [2:0] P0CMDBA; + input [2:0] P0CMDINSTR; + input [2:0] P1CMDBA; + input [2:0] P1CMDINSTR; + input [2:0] P2CMDBA; + input [2:0] P2CMDINSTR; + input [2:0] P3CMDBA; + input [2:0] P3CMDINSTR; + input [2:0] P4CMDBA; + input [2:0] P4CMDINSTR; + input [2:0] P5CMDBA; + input [2:0] P5CMDINSTR; + input [31:0] P0WRDATA; + input [31:0] P1WRDATA; + input [31:0] P2WRDATA; + input [31:0] P3WRDATA; + input [31:0] P4WRDATA; + input [31:0] P5WRDATA; + input [3:0] P0RWRMASK; + input [3:0] P1RWRMASK; + input [3:0] P2WRMASK; + input [3:0] P3WRMASK; + input [3:0] P4WRMASK; + input [3:0] P5WRMASK; + input [3:0] UIDQCOUNT; + input [4:0] UIADDR; + input [5:0] P0CMDBL; + input [5:0] P1CMDBL; + input [5:0] P2CMDBL; + input [5:0] P3CMDBL; + input [5:0] P4CMDBL; + input [5:0] P5CMDBL; +endmodule + +(* keep *) +module HBM_REF_CLK (...); + input REF_CLK; +endmodule + +(* keep *) +module HBM_SNGLBLI_INTF_APB (...); + parameter CLK_SEL = "FALSE"; + parameter [0:0] IS_PCLK_INVERTED = 1'b0; + parameter [0:0] IS_PRESET_N_INVERTED = 1'b0; + parameter MC_ENABLE = "FALSE"; + parameter PHY_ENABLE = "FALSE"; + parameter PHY_PCLK_INVERT = "FALSE"; + parameter SWITCH_ENABLE = "FALSE"; + output CATTRIP_PIPE; + output [31:0] PRDATA_PIPE; + output PREADY_PIPE; + output PSLVERR_PIPE; + output [2:0] TEMP_PIPE; + input [21:0] PADDR; + (* invertible_pin = "IS_PCLK_INVERTED" *) + input PCLK; + input PENABLE; + (* invertible_pin = "IS_PRESET_N_INVERTED" *) + input PRESET_N; + input PSEL; + input [31:0] PWDATA; + input PWRITE; +endmodule + +(* keep *) +module HBM_SNGLBLI_INTF_AXI (...); + parameter CLK_SEL = "FALSE"; + parameter integer DATARATE = 1800; + parameter [0:0] IS_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_ARESET_N_INVERTED = 1'b0; + parameter MC_ENABLE = "FALSE"; + parameter integer PAGEHIT_PERCENT = 75; + parameter PHY_ENABLE = "FALSE"; + parameter integer READ_PERCENT = 50; + parameter SWITCH_ENABLE = "FALSE"; + parameter integer WRITE_PERCENT = 50; + output ARREADY_PIPE; + output AWREADY_PIPE; + output [5:0] BID_PIPE; + output [1:0] BRESP_PIPE; + output BVALID_PIPE; + output [1:0] DFI_AW_AERR_N_PIPE; + output DFI_CLK_BUF; + output DFI_CTRLUPD_ACK_PIPE; + output [7:0] DFI_DBI_BYTE_DISABLE_PIPE; + output [20:0] DFI_DW_RDDATA_DBI_PIPE; + output [7:0] DFI_DW_RDDATA_DERR_PIPE; + output [1:0] DFI_DW_RDDATA_PAR_VALID_PIPE; + output [1:0] DFI_DW_RDDATA_VALID_PIPE; + output DFI_INIT_COMPLETE_PIPE; + output DFI_PHYUPD_REQ_PIPE; + output DFI_PHYUPD_TYPE_PIPE; + output DFI_PHY_LP_STATE_PIPE; + output DFI_RST_N_BUF; + output [5:0] MC_STATUS; + output [7:0] PHY_STATUS; + output [31:0] RDATA_PARITY_PIPE; + output [255:0] RDATA_PIPE; + output [5:0] RID_PIPE; + output RLAST_PIPE; + output [1:0] RRESP_PIPE; + output RVALID_PIPE; + output [5:0] STATUS; + output WREADY_PIPE; + (* invertible_pin = "IS_ACLK_INVERTED" *) + input ACLK; + input [36:0] ARADDR; + input [1:0] ARBURST; + (* invertible_pin = "IS_ARESET_N_INVERTED" *) + input ARESET_N; + input [5:0] ARID; + input [3:0] ARLEN; + input [2:0] ARSIZE; + input ARVALID; + input [36:0] AWADDR; + input [1:0] AWBURST; + input [5:0] AWID; + input [3:0] AWLEN; + input [2:0] AWSIZE; + input AWVALID; + input BREADY; + input BSCAN_CK; + input DFI_LP_PWR_X_REQ; + input MBIST_EN; + input RREADY; + input [255:0] WDATA; + input [31:0] WDATA_PARITY; + input WLAST; + input [31:0] WSTRB; + input WVALID; +endmodule + +(* keep *) +module HBM_ONE_STACK_INTF (...); + parameter CLK_SEL_00 = "FALSE"; + parameter CLK_SEL_01 = "FALSE"; + parameter CLK_SEL_02 = "FALSE"; + parameter CLK_SEL_03 = "FALSE"; + parameter CLK_SEL_04 = "FALSE"; + parameter CLK_SEL_05 = "FALSE"; + parameter CLK_SEL_06 = "FALSE"; + parameter CLK_SEL_07 = "FALSE"; + parameter CLK_SEL_08 = "FALSE"; + parameter CLK_SEL_09 = "FALSE"; + parameter CLK_SEL_10 = "FALSE"; + parameter CLK_SEL_11 = "FALSE"; + parameter CLK_SEL_12 = "FALSE"; + parameter CLK_SEL_13 = "FALSE"; + parameter CLK_SEL_14 = "FALSE"; + parameter CLK_SEL_15 = "FALSE"; + parameter integer DATARATE_00 = 1800; + parameter integer DATARATE_01 = 1800; + parameter integer DATARATE_02 = 1800; + parameter integer DATARATE_03 = 1800; + parameter integer DATARATE_04 = 1800; + parameter integer DATARATE_05 = 1800; + parameter integer DATARATE_06 = 1800; + parameter integer DATARATE_07 = 1800; + parameter DA_LOCKOUT = "FALSE"; + parameter [0:0] IS_APB_0_PCLK_INVERTED = 1'b0; + parameter [0:0] IS_APB_0_PRESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_00_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_00_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_01_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_01_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_02_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_02_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_03_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_03_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_04_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_04_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_05_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_05_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_06_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_06_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_07_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_07_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_08_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_08_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_09_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_09_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_10_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_10_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_11_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_11_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_12_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_12_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_13_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_13_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_14_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_14_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_15_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_15_ARESET_N_INVERTED = 1'b0; + parameter MC_ENABLE_0 = "FALSE"; + parameter MC_ENABLE_1 = "FALSE"; + parameter MC_ENABLE_2 = "FALSE"; + parameter MC_ENABLE_3 = "FALSE"; + parameter MC_ENABLE_4 = "FALSE"; + parameter MC_ENABLE_5 = "FALSE"; + parameter MC_ENABLE_6 = "FALSE"; + parameter MC_ENABLE_7 = "FALSE"; + parameter MC_ENABLE_APB = "FALSE"; + parameter integer PAGEHIT_PERCENT_00 = 75; + parameter PHY_ENABLE_00 = "FALSE"; + parameter PHY_ENABLE_01 = "FALSE"; + parameter PHY_ENABLE_02 = "FALSE"; + parameter PHY_ENABLE_03 = "FALSE"; + parameter PHY_ENABLE_04 = "FALSE"; + parameter PHY_ENABLE_05 = "FALSE"; + parameter PHY_ENABLE_06 = "FALSE"; + parameter PHY_ENABLE_07 = "FALSE"; + parameter PHY_ENABLE_08 = "FALSE"; + parameter PHY_ENABLE_09 = "FALSE"; + parameter PHY_ENABLE_10 = "FALSE"; + parameter PHY_ENABLE_11 = "FALSE"; + parameter PHY_ENABLE_12 = "FALSE"; + parameter PHY_ENABLE_13 = "FALSE"; + parameter PHY_ENABLE_14 = "FALSE"; + parameter PHY_ENABLE_15 = "FALSE"; + parameter PHY_ENABLE_APB = "FALSE"; + parameter PHY_PCLK_INVERT_01 = "FALSE"; + parameter integer READ_PERCENT_00 = 50; + parameter integer READ_PERCENT_01 = 50; + parameter integer READ_PERCENT_02 = 50; + parameter integer READ_PERCENT_03 = 50; + parameter integer READ_PERCENT_04 = 50; + parameter integer READ_PERCENT_05 = 50; + parameter integer READ_PERCENT_06 = 50; + parameter integer READ_PERCENT_07 = 50; + parameter integer READ_PERCENT_08 = 50; + parameter integer READ_PERCENT_09 = 50; + parameter integer READ_PERCENT_10 = 50; + parameter integer READ_PERCENT_11 = 50; + parameter integer READ_PERCENT_12 = 50; + parameter integer READ_PERCENT_13 = 50; + parameter integer READ_PERCENT_14 = 50; + parameter integer READ_PERCENT_15 = 50; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter integer STACK_LOCATION = 0; + parameter SWITCH_ENABLE = "FALSE"; + parameter integer WRITE_PERCENT_00 = 50; + parameter integer WRITE_PERCENT_01 = 50; + parameter integer WRITE_PERCENT_02 = 50; + parameter integer WRITE_PERCENT_03 = 50; + parameter integer WRITE_PERCENT_04 = 50; + parameter integer WRITE_PERCENT_05 = 50; + parameter integer WRITE_PERCENT_06 = 50; + parameter integer WRITE_PERCENT_07 = 50; + parameter integer WRITE_PERCENT_08 = 50; + parameter integer WRITE_PERCENT_09 = 50; + parameter integer WRITE_PERCENT_10 = 50; + parameter integer WRITE_PERCENT_11 = 50; + parameter integer WRITE_PERCENT_12 = 50; + parameter integer WRITE_PERCENT_13 = 50; + parameter integer WRITE_PERCENT_14 = 50; + parameter integer WRITE_PERCENT_15 = 50; + output [31:0] APB_0_PRDATA; + output APB_0_PREADY; + output APB_0_PSLVERR; + output AXI_00_ARREADY; + output AXI_00_AWREADY; + output [5:0] AXI_00_BID; + output [1:0] AXI_00_BRESP; + output AXI_00_BVALID; + output [1:0] AXI_00_DFI_AW_AERR_N; + output AXI_00_DFI_CLK_BUF; + output [7:0] AXI_00_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_00_DFI_DW_RDDATA_DBI; + output [7:0] AXI_00_DFI_DW_RDDATA_DERR; + output [1:0] AXI_00_DFI_DW_RDDATA_VALID; + output AXI_00_DFI_INIT_COMPLETE; + output AXI_00_DFI_PHYUPD_REQ; + output AXI_00_DFI_PHY_LP_STATE; + output AXI_00_DFI_RST_N_BUF; + output [5:0] AXI_00_MC_STATUS; + output [7:0] AXI_00_PHY_STATUS; + output [255:0] AXI_00_RDATA; + output [31:0] AXI_00_RDATA_PARITY; + output [5:0] AXI_00_RID; + output AXI_00_RLAST; + output [1:0] AXI_00_RRESP; + output AXI_00_RVALID; + output AXI_00_WREADY; + output AXI_01_ARREADY; + output AXI_01_AWREADY; + output [5:0] AXI_01_BID; + output [1:0] AXI_01_BRESP; + output AXI_01_BVALID; + output [1:0] AXI_01_DFI_AW_AERR_N; + output AXI_01_DFI_CLK_BUF; + output [7:0] AXI_01_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_01_DFI_DW_RDDATA_DBI; + output [7:0] AXI_01_DFI_DW_RDDATA_DERR; + output [1:0] AXI_01_DFI_DW_RDDATA_VALID; + output AXI_01_DFI_INIT_COMPLETE; + output AXI_01_DFI_PHYUPD_REQ; + output AXI_01_DFI_PHY_LP_STATE; + output AXI_01_DFI_RST_N_BUF; + output [255:0] AXI_01_RDATA; + output [31:0] AXI_01_RDATA_PARITY; + output [5:0] AXI_01_RID; + output AXI_01_RLAST; + output [1:0] AXI_01_RRESP; + output AXI_01_RVALID; + output AXI_01_WREADY; + output AXI_02_ARREADY; + output AXI_02_AWREADY; + output [5:0] AXI_02_BID; + output [1:0] AXI_02_BRESP; + output AXI_02_BVALID; + output [1:0] AXI_02_DFI_AW_AERR_N; + output AXI_02_DFI_CLK_BUF; + output [7:0] AXI_02_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_02_DFI_DW_RDDATA_DBI; + output [7:0] AXI_02_DFI_DW_RDDATA_DERR; + output [1:0] AXI_02_DFI_DW_RDDATA_VALID; + output AXI_02_DFI_INIT_COMPLETE; + output AXI_02_DFI_PHYUPD_REQ; + output AXI_02_DFI_PHY_LP_STATE; + output AXI_02_DFI_RST_N_BUF; + output [5:0] AXI_02_MC_STATUS; + output [7:0] AXI_02_PHY_STATUS; + output [255:0] AXI_02_RDATA; + output [31:0] AXI_02_RDATA_PARITY; + output [5:0] AXI_02_RID; + output AXI_02_RLAST; + output [1:0] AXI_02_RRESP; + output AXI_02_RVALID; + output AXI_02_WREADY; + output AXI_03_ARREADY; + output AXI_03_AWREADY; + output [5:0] AXI_03_BID; + output [1:0] AXI_03_BRESP; + output AXI_03_BVALID; + output [1:0] AXI_03_DFI_AW_AERR_N; + output AXI_03_DFI_CLK_BUF; + output [7:0] AXI_03_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_03_DFI_DW_RDDATA_DBI; + output [7:0] AXI_03_DFI_DW_RDDATA_DERR; + output [1:0] AXI_03_DFI_DW_RDDATA_VALID; + output AXI_03_DFI_INIT_COMPLETE; + output AXI_03_DFI_PHYUPD_REQ; + output AXI_03_DFI_PHY_LP_STATE; + output AXI_03_DFI_RST_N_BUF; + output [255:0] AXI_03_RDATA; + output [31:0] AXI_03_RDATA_PARITY; + output [5:0] AXI_03_RID; + output AXI_03_RLAST; + output [1:0] AXI_03_RRESP; + output AXI_03_RVALID; + output AXI_03_WREADY; + output AXI_04_ARREADY; + output AXI_04_AWREADY; + output [5:0] AXI_04_BID; + output [1:0] AXI_04_BRESP; + output AXI_04_BVALID; + output [1:0] AXI_04_DFI_AW_AERR_N; + output AXI_04_DFI_CLK_BUF; + output [7:0] AXI_04_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_04_DFI_DW_RDDATA_DBI; + output [7:0] AXI_04_DFI_DW_RDDATA_DERR; + output [1:0] AXI_04_DFI_DW_RDDATA_VALID; + output AXI_04_DFI_INIT_COMPLETE; + output AXI_04_DFI_PHYUPD_REQ; + output AXI_04_DFI_PHY_LP_STATE; + output AXI_04_DFI_RST_N_BUF; + output [5:0] AXI_04_MC_STATUS; + output [7:0] AXI_04_PHY_STATUS; + output [255:0] AXI_04_RDATA; + output [31:0] AXI_04_RDATA_PARITY; + output [5:0] AXI_04_RID; + output AXI_04_RLAST; + output [1:0] AXI_04_RRESP; + output AXI_04_RVALID; + output AXI_04_WREADY; + output AXI_05_ARREADY; + output AXI_05_AWREADY; + output [5:0] AXI_05_BID; + output [1:0] AXI_05_BRESP; + output AXI_05_BVALID; + output [1:0] AXI_05_DFI_AW_AERR_N; + output AXI_05_DFI_CLK_BUF; + output [7:0] AXI_05_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_05_DFI_DW_RDDATA_DBI; + output [7:0] AXI_05_DFI_DW_RDDATA_DERR; + output [1:0] AXI_05_DFI_DW_RDDATA_VALID; + output AXI_05_DFI_INIT_COMPLETE; + output AXI_05_DFI_PHYUPD_REQ; + output AXI_05_DFI_PHY_LP_STATE; + output AXI_05_DFI_RST_N_BUF; + output [255:0] AXI_05_RDATA; + output [31:0] AXI_05_RDATA_PARITY; + output [5:0] AXI_05_RID; + output AXI_05_RLAST; + output [1:0] AXI_05_RRESP; + output AXI_05_RVALID; + output AXI_05_WREADY; + output AXI_06_ARREADY; + output AXI_06_AWREADY; + output [5:0] AXI_06_BID; + output [1:0] AXI_06_BRESP; + output AXI_06_BVALID; + output [1:0] AXI_06_DFI_AW_AERR_N; + output AXI_06_DFI_CLK_BUF; + output [7:0] AXI_06_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_06_DFI_DW_RDDATA_DBI; + output [7:0] AXI_06_DFI_DW_RDDATA_DERR; + output [1:0] AXI_06_DFI_DW_RDDATA_VALID; + output AXI_06_DFI_INIT_COMPLETE; + output AXI_06_DFI_PHYUPD_REQ; + output AXI_06_DFI_PHY_LP_STATE; + output AXI_06_DFI_RST_N_BUF; + output [5:0] AXI_06_MC_STATUS; + output [7:0] AXI_06_PHY_STATUS; + output [255:0] AXI_06_RDATA; + output [31:0] AXI_06_RDATA_PARITY; + output [5:0] AXI_06_RID; + output AXI_06_RLAST; + output [1:0] AXI_06_RRESP; + output AXI_06_RVALID; + output AXI_06_WREADY; + output AXI_07_ARREADY; + output AXI_07_AWREADY; + output [5:0] AXI_07_BID; + output [1:0] AXI_07_BRESP; + output AXI_07_BVALID; + output [1:0] AXI_07_DFI_AW_AERR_N; + output AXI_07_DFI_CLK_BUF; + output [7:0] AXI_07_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_07_DFI_DW_RDDATA_DBI; + output [7:0] AXI_07_DFI_DW_RDDATA_DERR; + output [1:0] AXI_07_DFI_DW_RDDATA_VALID; + output AXI_07_DFI_INIT_COMPLETE; + output AXI_07_DFI_PHYUPD_REQ; + output AXI_07_DFI_PHY_LP_STATE; + output AXI_07_DFI_RST_N_BUF; + output [255:0] AXI_07_RDATA; + output [31:0] AXI_07_RDATA_PARITY; + output [5:0] AXI_07_RID; + output AXI_07_RLAST; + output [1:0] AXI_07_RRESP; + output AXI_07_RVALID; + output AXI_07_WREADY; + output AXI_08_ARREADY; + output AXI_08_AWREADY; + output [5:0] AXI_08_BID; + output [1:0] AXI_08_BRESP; + output AXI_08_BVALID; + output [1:0] AXI_08_DFI_AW_AERR_N; + output AXI_08_DFI_CLK_BUF; + output [7:0] AXI_08_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_08_DFI_DW_RDDATA_DBI; + output [7:0] AXI_08_DFI_DW_RDDATA_DERR; + output [1:0] AXI_08_DFI_DW_RDDATA_VALID; + output AXI_08_DFI_INIT_COMPLETE; + output AXI_08_DFI_PHYUPD_REQ; + output AXI_08_DFI_PHY_LP_STATE; + output AXI_08_DFI_RST_N_BUF; + output [5:0] AXI_08_MC_STATUS; + output [7:0] AXI_08_PHY_STATUS; + output [255:0] AXI_08_RDATA; + output [31:0] AXI_08_RDATA_PARITY; + output [5:0] AXI_08_RID; + output AXI_08_RLAST; + output [1:0] AXI_08_RRESP; + output AXI_08_RVALID; + output AXI_08_WREADY; + output AXI_09_ARREADY; + output AXI_09_AWREADY; + output [5:0] AXI_09_BID; + output [1:0] AXI_09_BRESP; + output AXI_09_BVALID; + output [1:0] AXI_09_DFI_AW_AERR_N; + output AXI_09_DFI_CLK_BUF; + output [7:0] AXI_09_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_09_DFI_DW_RDDATA_DBI; + output [7:0] AXI_09_DFI_DW_RDDATA_DERR; + output [1:0] AXI_09_DFI_DW_RDDATA_VALID; + output AXI_09_DFI_INIT_COMPLETE; + output AXI_09_DFI_PHYUPD_REQ; + output AXI_09_DFI_PHY_LP_STATE; + output AXI_09_DFI_RST_N_BUF; + output [255:0] AXI_09_RDATA; + output [31:0] AXI_09_RDATA_PARITY; + output [5:0] AXI_09_RID; + output AXI_09_RLAST; + output [1:0] AXI_09_RRESP; + output AXI_09_RVALID; + output AXI_09_WREADY; + output AXI_10_ARREADY; + output AXI_10_AWREADY; + output [5:0] AXI_10_BID; + output [1:0] AXI_10_BRESP; + output AXI_10_BVALID; + output [1:0] AXI_10_DFI_AW_AERR_N; + output AXI_10_DFI_CLK_BUF; + output [7:0] AXI_10_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_10_DFI_DW_RDDATA_DBI; + output [7:0] AXI_10_DFI_DW_RDDATA_DERR; + output [1:0] AXI_10_DFI_DW_RDDATA_VALID; + output AXI_10_DFI_INIT_COMPLETE; + output AXI_10_DFI_PHYUPD_REQ; + output AXI_10_DFI_PHY_LP_STATE; + output AXI_10_DFI_RST_N_BUF; + output [5:0] AXI_10_MC_STATUS; + output [7:0] AXI_10_PHY_STATUS; + output [255:0] AXI_10_RDATA; + output [31:0] AXI_10_RDATA_PARITY; + output [5:0] AXI_10_RID; + output AXI_10_RLAST; + output [1:0] AXI_10_RRESP; + output AXI_10_RVALID; + output AXI_10_WREADY; + output AXI_11_ARREADY; + output AXI_11_AWREADY; + output [5:0] AXI_11_BID; + output [1:0] AXI_11_BRESP; + output AXI_11_BVALID; + output [1:0] AXI_11_DFI_AW_AERR_N; + output AXI_11_DFI_CLK_BUF; + output [7:0] AXI_11_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_11_DFI_DW_RDDATA_DBI; + output [7:0] AXI_11_DFI_DW_RDDATA_DERR; + output [1:0] AXI_11_DFI_DW_RDDATA_VALID; + output AXI_11_DFI_INIT_COMPLETE; + output AXI_11_DFI_PHYUPD_REQ; + output AXI_11_DFI_PHY_LP_STATE; + output AXI_11_DFI_RST_N_BUF; + output [255:0] AXI_11_RDATA; + output [31:0] AXI_11_RDATA_PARITY; + output [5:0] AXI_11_RID; + output AXI_11_RLAST; + output [1:0] AXI_11_RRESP; + output AXI_11_RVALID; + output AXI_11_WREADY; + output AXI_12_ARREADY; + output AXI_12_AWREADY; + output [5:0] AXI_12_BID; + output [1:0] AXI_12_BRESP; + output AXI_12_BVALID; + output [1:0] AXI_12_DFI_AW_AERR_N; + output AXI_12_DFI_CLK_BUF; + output [7:0] AXI_12_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_12_DFI_DW_RDDATA_DBI; + output [7:0] AXI_12_DFI_DW_RDDATA_DERR; + output [1:0] AXI_12_DFI_DW_RDDATA_VALID; + output AXI_12_DFI_INIT_COMPLETE; + output AXI_12_DFI_PHYUPD_REQ; + output AXI_12_DFI_PHY_LP_STATE; + output AXI_12_DFI_RST_N_BUF; + output [5:0] AXI_12_MC_STATUS; + output [7:0] AXI_12_PHY_STATUS; + output [255:0] AXI_12_RDATA; + output [31:0] AXI_12_RDATA_PARITY; + output [5:0] AXI_12_RID; + output AXI_12_RLAST; + output [1:0] AXI_12_RRESP; + output AXI_12_RVALID; + output AXI_12_WREADY; + output AXI_13_ARREADY; + output AXI_13_AWREADY; + output [5:0] AXI_13_BID; + output [1:0] AXI_13_BRESP; + output AXI_13_BVALID; + output [1:0] AXI_13_DFI_AW_AERR_N; + output AXI_13_DFI_CLK_BUF; + output [7:0] AXI_13_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_13_DFI_DW_RDDATA_DBI; + output [7:0] AXI_13_DFI_DW_RDDATA_DERR; + output [1:0] AXI_13_DFI_DW_RDDATA_VALID; + output AXI_13_DFI_INIT_COMPLETE; + output AXI_13_DFI_PHYUPD_REQ; + output AXI_13_DFI_PHY_LP_STATE; + output AXI_13_DFI_RST_N_BUF; + output [255:0] AXI_13_RDATA; + output [31:0] AXI_13_RDATA_PARITY; + output [5:0] AXI_13_RID; + output AXI_13_RLAST; + output [1:0] AXI_13_RRESP; + output AXI_13_RVALID; + output AXI_13_WREADY; + output AXI_14_ARREADY; + output AXI_14_AWREADY; + output [5:0] AXI_14_BID; + output [1:0] AXI_14_BRESP; + output AXI_14_BVALID; + output [1:0] AXI_14_DFI_AW_AERR_N; + output AXI_14_DFI_CLK_BUF; + output [7:0] AXI_14_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_14_DFI_DW_RDDATA_DBI; + output [7:0] AXI_14_DFI_DW_RDDATA_DERR; + output [1:0] AXI_14_DFI_DW_RDDATA_VALID; + output AXI_14_DFI_INIT_COMPLETE; + output AXI_14_DFI_PHYUPD_REQ; + output AXI_14_DFI_PHY_LP_STATE; + output AXI_14_DFI_RST_N_BUF; + output [5:0] AXI_14_MC_STATUS; + output [7:0] AXI_14_PHY_STATUS; + output [255:0] AXI_14_RDATA; + output [31:0] AXI_14_RDATA_PARITY; + output [5:0] AXI_14_RID; + output AXI_14_RLAST; + output [1:0] AXI_14_RRESP; + output AXI_14_RVALID; + output AXI_14_WREADY; + output AXI_15_ARREADY; + output AXI_15_AWREADY; + output [5:0] AXI_15_BID; + output [1:0] AXI_15_BRESP; + output AXI_15_BVALID; + output [1:0] AXI_15_DFI_AW_AERR_N; + output AXI_15_DFI_CLK_BUF; + output [7:0] AXI_15_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_15_DFI_DW_RDDATA_DBI; + output [7:0] AXI_15_DFI_DW_RDDATA_DERR; + output [1:0] AXI_15_DFI_DW_RDDATA_VALID; + output AXI_15_DFI_INIT_COMPLETE; + output AXI_15_DFI_PHYUPD_REQ; + output AXI_15_DFI_PHY_LP_STATE; + output AXI_15_DFI_RST_N_BUF; + output [255:0] AXI_15_RDATA; + output [31:0] AXI_15_RDATA_PARITY; + output [5:0] AXI_15_RID; + output AXI_15_RLAST; + output [1:0] AXI_15_RRESP; + output AXI_15_RVALID; + output AXI_15_WREADY; + output DRAM_0_STAT_CATTRIP; + output [2:0] DRAM_0_STAT_TEMP; + input [21:0] APB_0_PADDR; + (* invertible_pin = "IS_APB_0_PCLK_INVERTED" *) + input APB_0_PCLK; + input APB_0_PENABLE; + (* invertible_pin = "IS_APB_0_PRESET_N_INVERTED" *) + input APB_0_PRESET_N; + input APB_0_PSEL; + input [31:0] APB_0_PWDATA; + input APB_0_PWRITE; + (* invertible_pin = "IS_AXI_00_ACLK_INVERTED" *) + input AXI_00_ACLK; + input [36:0] AXI_00_ARADDR; + input [1:0] AXI_00_ARBURST; + (* invertible_pin = "IS_AXI_00_ARESET_N_INVERTED" *) + input AXI_00_ARESET_N; + input [5:0] AXI_00_ARID; + input [3:0] AXI_00_ARLEN; + input [2:0] AXI_00_ARSIZE; + input AXI_00_ARVALID; + input [36:0] AXI_00_AWADDR; + input [1:0] AXI_00_AWBURST; + input [5:0] AXI_00_AWID; + input [3:0] AXI_00_AWLEN; + input [2:0] AXI_00_AWSIZE; + input AXI_00_AWVALID; + input AXI_00_BREADY; + input AXI_00_DFI_LP_PWR_X_REQ; + input AXI_00_RREADY; + input [255:0] AXI_00_WDATA; + input [31:0] AXI_00_WDATA_PARITY; + input AXI_00_WLAST; + input [31:0] AXI_00_WSTRB; + input AXI_00_WVALID; + (* invertible_pin = "IS_AXI_01_ACLK_INVERTED" *) + input AXI_01_ACLK; + input [36:0] AXI_01_ARADDR; + input [1:0] AXI_01_ARBURST; + (* invertible_pin = "IS_AXI_01_ARESET_N_INVERTED" *) + input AXI_01_ARESET_N; + input [5:0] AXI_01_ARID; + input [3:0] AXI_01_ARLEN; + input [2:0] AXI_01_ARSIZE; + input AXI_01_ARVALID; + input [36:0] AXI_01_AWADDR; + input [1:0] AXI_01_AWBURST; + input [5:0] AXI_01_AWID; + input [3:0] AXI_01_AWLEN; + input [2:0] AXI_01_AWSIZE; + input AXI_01_AWVALID; + input AXI_01_BREADY; + input AXI_01_DFI_LP_PWR_X_REQ; + input AXI_01_RREADY; + input [255:0] AXI_01_WDATA; + input [31:0] AXI_01_WDATA_PARITY; + input AXI_01_WLAST; + input [31:0] AXI_01_WSTRB; + input AXI_01_WVALID; + (* invertible_pin = "IS_AXI_02_ACLK_INVERTED" *) + input AXI_02_ACLK; + input [36:0] AXI_02_ARADDR; + input [1:0] AXI_02_ARBURST; + (* invertible_pin = "IS_AXI_02_ARESET_N_INVERTED" *) + input AXI_02_ARESET_N; + input [5:0] AXI_02_ARID; + input [3:0] AXI_02_ARLEN; + input [2:0] AXI_02_ARSIZE; + input AXI_02_ARVALID; + input [36:0] AXI_02_AWADDR; + input [1:0] AXI_02_AWBURST; + input [5:0] AXI_02_AWID; + input [3:0] AXI_02_AWLEN; + input [2:0] AXI_02_AWSIZE; + input AXI_02_AWVALID; + input AXI_02_BREADY; + input AXI_02_DFI_LP_PWR_X_REQ; + input AXI_02_RREADY; + input [255:0] AXI_02_WDATA; + input [31:0] AXI_02_WDATA_PARITY; + input AXI_02_WLAST; + input [31:0] AXI_02_WSTRB; + input AXI_02_WVALID; + (* invertible_pin = "IS_AXI_03_ACLK_INVERTED" *) + input AXI_03_ACLK; + input [36:0] AXI_03_ARADDR; + input [1:0] AXI_03_ARBURST; + (* invertible_pin = "IS_AXI_03_ARESET_N_INVERTED" *) + input AXI_03_ARESET_N; + input [5:0] AXI_03_ARID; + input [3:0] AXI_03_ARLEN; + input [2:0] AXI_03_ARSIZE; + input AXI_03_ARVALID; + input [36:0] AXI_03_AWADDR; + input [1:0] AXI_03_AWBURST; + input [5:0] AXI_03_AWID; + input [3:0] AXI_03_AWLEN; + input [2:0] AXI_03_AWSIZE; + input AXI_03_AWVALID; + input AXI_03_BREADY; + input AXI_03_DFI_LP_PWR_X_REQ; + input AXI_03_RREADY; + input [255:0] AXI_03_WDATA; + input [31:0] AXI_03_WDATA_PARITY; + input AXI_03_WLAST; + input [31:0] AXI_03_WSTRB; + input AXI_03_WVALID; + (* invertible_pin = "IS_AXI_04_ACLK_INVERTED" *) + input AXI_04_ACLK; + input [36:0] AXI_04_ARADDR; + input [1:0] AXI_04_ARBURST; + (* invertible_pin = "IS_AXI_04_ARESET_N_INVERTED" *) + input AXI_04_ARESET_N; + input [5:0] AXI_04_ARID; + input [3:0] AXI_04_ARLEN; + input [2:0] AXI_04_ARSIZE; + input AXI_04_ARVALID; + input [36:0] AXI_04_AWADDR; + input [1:0] AXI_04_AWBURST; + input [5:0] AXI_04_AWID; + input [3:0] AXI_04_AWLEN; + input [2:0] AXI_04_AWSIZE; + input AXI_04_AWVALID; + input AXI_04_BREADY; + input AXI_04_DFI_LP_PWR_X_REQ; + input AXI_04_RREADY; + input [255:0] AXI_04_WDATA; + input [31:0] AXI_04_WDATA_PARITY; + input AXI_04_WLAST; + input [31:0] AXI_04_WSTRB; + input AXI_04_WVALID; + (* invertible_pin = "IS_AXI_05_ACLK_INVERTED" *) + input AXI_05_ACLK; + input [36:0] AXI_05_ARADDR; + input [1:0] AXI_05_ARBURST; + (* invertible_pin = "IS_AXI_05_ARESET_N_INVERTED" *) + input AXI_05_ARESET_N; + input [5:0] AXI_05_ARID; + input [3:0] AXI_05_ARLEN; + input [2:0] AXI_05_ARSIZE; + input AXI_05_ARVALID; + input [36:0] AXI_05_AWADDR; + input [1:0] AXI_05_AWBURST; + input [5:0] AXI_05_AWID; + input [3:0] AXI_05_AWLEN; + input [2:0] AXI_05_AWSIZE; + input AXI_05_AWVALID; + input AXI_05_BREADY; + input AXI_05_DFI_LP_PWR_X_REQ; + input AXI_05_RREADY; + input [255:0] AXI_05_WDATA; + input [31:0] AXI_05_WDATA_PARITY; + input AXI_05_WLAST; + input [31:0] AXI_05_WSTRB; + input AXI_05_WVALID; + (* invertible_pin = "IS_AXI_06_ACLK_INVERTED" *) + input AXI_06_ACLK; + input [36:0] AXI_06_ARADDR; + input [1:0] AXI_06_ARBURST; + (* invertible_pin = "IS_AXI_06_ARESET_N_INVERTED" *) + input AXI_06_ARESET_N; + input [5:0] AXI_06_ARID; + input [3:0] AXI_06_ARLEN; + input [2:0] AXI_06_ARSIZE; + input AXI_06_ARVALID; + input [36:0] AXI_06_AWADDR; + input [1:0] AXI_06_AWBURST; + input [5:0] AXI_06_AWID; + input [3:0] AXI_06_AWLEN; + input [2:0] AXI_06_AWSIZE; + input AXI_06_AWVALID; + input AXI_06_BREADY; + input AXI_06_DFI_LP_PWR_X_REQ; + input AXI_06_RREADY; + input [255:0] AXI_06_WDATA; + input [31:0] AXI_06_WDATA_PARITY; + input AXI_06_WLAST; + input [31:0] AXI_06_WSTRB; + input AXI_06_WVALID; + (* invertible_pin = "IS_AXI_07_ACLK_INVERTED" *) + input AXI_07_ACLK; + input [36:0] AXI_07_ARADDR; + input [1:0] AXI_07_ARBURST; + (* invertible_pin = "IS_AXI_07_ARESET_N_INVERTED" *) + input AXI_07_ARESET_N; + input [5:0] AXI_07_ARID; + input [3:0] AXI_07_ARLEN; + input [2:0] AXI_07_ARSIZE; + input AXI_07_ARVALID; + input [36:0] AXI_07_AWADDR; + input [1:0] AXI_07_AWBURST; + input [5:0] AXI_07_AWID; + input [3:0] AXI_07_AWLEN; + input [2:0] AXI_07_AWSIZE; + input AXI_07_AWVALID; + input AXI_07_BREADY; + input AXI_07_DFI_LP_PWR_X_REQ; + input AXI_07_RREADY; + input [255:0] AXI_07_WDATA; + input [31:0] AXI_07_WDATA_PARITY; + input AXI_07_WLAST; + input [31:0] AXI_07_WSTRB; + input AXI_07_WVALID; + (* invertible_pin = "IS_AXI_08_ACLK_INVERTED" *) + input AXI_08_ACLK; + input [36:0] AXI_08_ARADDR; + input [1:0] AXI_08_ARBURST; + (* invertible_pin = "IS_AXI_08_ARESET_N_INVERTED" *) + input AXI_08_ARESET_N; + input [5:0] AXI_08_ARID; + input [3:0] AXI_08_ARLEN; + input [2:0] AXI_08_ARSIZE; + input AXI_08_ARVALID; + input [36:0] AXI_08_AWADDR; + input [1:0] AXI_08_AWBURST; + input [5:0] AXI_08_AWID; + input [3:0] AXI_08_AWLEN; + input [2:0] AXI_08_AWSIZE; + input AXI_08_AWVALID; + input AXI_08_BREADY; + input AXI_08_DFI_LP_PWR_X_REQ; + input AXI_08_RREADY; + input [255:0] AXI_08_WDATA; + input [31:0] AXI_08_WDATA_PARITY; + input AXI_08_WLAST; + input [31:0] AXI_08_WSTRB; + input AXI_08_WVALID; + (* invertible_pin = "IS_AXI_09_ACLK_INVERTED" *) + input AXI_09_ACLK; + input [36:0] AXI_09_ARADDR; + input [1:0] AXI_09_ARBURST; + (* invertible_pin = "IS_AXI_09_ARESET_N_INVERTED" *) + input AXI_09_ARESET_N; + input [5:0] AXI_09_ARID; + input [3:0] AXI_09_ARLEN; + input [2:0] AXI_09_ARSIZE; + input AXI_09_ARVALID; + input [36:0] AXI_09_AWADDR; + input [1:0] AXI_09_AWBURST; + input [5:0] AXI_09_AWID; + input [3:0] AXI_09_AWLEN; + input [2:0] AXI_09_AWSIZE; + input AXI_09_AWVALID; + input AXI_09_BREADY; + input AXI_09_DFI_LP_PWR_X_REQ; + input AXI_09_RREADY; + input [255:0] AXI_09_WDATA; + input [31:0] AXI_09_WDATA_PARITY; + input AXI_09_WLAST; + input [31:0] AXI_09_WSTRB; + input AXI_09_WVALID; + (* invertible_pin = "IS_AXI_10_ACLK_INVERTED" *) + input AXI_10_ACLK; + input [36:0] AXI_10_ARADDR; + input [1:0] AXI_10_ARBURST; + (* invertible_pin = "IS_AXI_10_ARESET_N_INVERTED" *) + input AXI_10_ARESET_N; + input [5:0] AXI_10_ARID; + input [3:0] AXI_10_ARLEN; + input [2:0] AXI_10_ARSIZE; + input AXI_10_ARVALID; + input [36:0] AXI_10_AWADDR; + input [1:0] AXI_10_AWBURST; + input [5:0] AXI_10_AWID; + input [3:0] AXI_10_AWLEN; + input [2:0] AXI_10_AWSIZE; + input AXI_10_AWVALID; + input AXI_10_BREADY; + input AXI_10_DFI_LP_PWR_X_REQ; + input AXI_10_RREADY; + input [255:0] AXI_10_WDATA; + input [31:0] AXI_10_WDATA_PARITY; + input AXI_10_WLAST; + input [31:0] AXI_10_WSTRB; + input AXI_10_WVALID; + (* invertible_pin = "IS_AXI_11_ACLK_INVERTED" *) + input AXI_11_ACLK; + input [36:0] AXI_11_ARADDR; + input [1:0] AXI_11_ARBURST; + (* invertible_pin = "IS_AXI_11_ARESET_N_INVERTED" *) + input AXI_11_ARESET_N; + input [5:0] AXI_11_ARID; + input [3:0] AXI_11_ARLEN; + input [2:0] AXI_11_ARSIZE; + input AXI_11_ARVALID; + input [36:0] AXI_11_AWADDR; + input [1:0] AXI_11_AWBURST; + input [5:0] AXI_11_AWID; + input [3:0] AXI_11_AWLEN; + input [2:0] AXI_11_AWSIZE; + input AXI_11_AWVALID; + input AXI_11_BREADY; + input AXI_11_DFI_LP_PWR_X_REQ; + input AXI_11_RREADY; + input [255:0] AXI_11_WDATA; + input [31:0] AXI_11_WDATA_PARITY; + input AXI_11_WLAST; + input [31:0] AXI_11_WSTRB; + input AXI_11_WVALID; + (* invertible_pin = "IS_AXI_12_ACLK_INVERTED" *) + input AXI_12_ACLK; + input [36:0] AXI_12_ARADDR; + input [1:0] AXI_12_ARBURST; + (* invertible_pin = "IS_AXI_12_ARESET_N_INVERTED" *) + input AXI_12_ARESET_N; + input [5:0] AXI_12_ARID; + input [3:0] AXI_12_ARLEN; + input [2:0] AXI_12_ARSIZE; + input AXI_12_ARVALID; + input [36:0] AXI_12_AWADDR; + input [1:0] AXI_12_AWBURST; + input [5:0] AXI_12_AWID; + input [3:0] AXI_12_AWLEN; + input [2:0] AXI_12_AWSIZE; + input AXI_12_AWVALID; + input AXI_12_BREADY; + input AXI_12_DFI_LP_PWR_X_REQ; + input AXI_12_RREADY; + input [255:0] AXI_12_WDATA; + input [31:0] AXI_12_WDATA_PARITY; + input AXI_12_WLAST; + input [31:0] AXI_12_WSTRB; + input AXI_12_WVALID; + (* invertible_pin = "IS_AXI_13_ACLK_INVERTED" *) + input AXI_13_ACLK; + input [36:0] AXI_13_ARADDR; + input [1:0] AXI_13_ARBURST; + (* invertible_pin = "IS_AXI_13_ARESET_N_INVERTED" *) + input AXI_13_ARESET_N; + input [5:0] AXI_13_ARID; + input [3:0] AXI_13_ARLEN; + input [2:0] AXI_13_ARSIZE; + input AXI_13_ARVALID; + input [36:0] AXI_13_AWADDR; + input [1:0] AXI_13_AWBURST; + input [5:0] AXI_13_AWID; + input [3:0] AXI_13_AWLEN; + input [2:0] AXI_13_AWSIZE; + input AXI_13_AWVALID; + input AXI_13_BREADY; + input AXI_13_DFI_LP_PWR_X_REQ; + input AXI_13_RREADY; + input [255:0] AXI_13_WDATA; + input [31:0] AXI_13_WDATA_PARITY; + input AXI_13_WLAST; + input [31:0] AXI_13_WSTRB; + input AXI_13_WVALID; + (* invertible_pin = "IS_AXI_14_ACLK_INVERTED" *) + input AXI_14_ACLK; + input [36:0] AXI_14_ARADDR; + input [1:0] AXI_14_ARBURST; + (* invertible_pin = "IS_AXI_14_ARESET_N_INVERTED" *) + input AXI_14_ARESET_N; + input [5:0] AXI_14_ARID; + input [3:0] AXI_14_ARLEN; + input [2:0] AXI_14_ARSIZE; + input AXI_14_ARVALID; + input [36:0] AXI_14_AWADDR; + input [1:0] AXI_14_AWBURST; + input [5:0] AXI_14_AWID; + input [3:0] AXI_14_AWLEN; + input [2:0] AXI_14_AWSIZE; + input AXI_14_AWVALID; + input AXI_14_BREADY; + input AXI_14_DFI_LP_PWR_X_REQ; + input AXI_14_RREADY; + input [255:0] AXI_14_WDATA; + input [31:0] AXI_14_WDATA_PARITY; + input AXI_14_WLAST; + input [31:0] AXI_14_WSTRB; + input AXI_14_WVALID; + (* invertible_pin = "IS_AXI_15_ACLK_INVERTED" *) + input AXI_15_ACLK; + input [36:0] AXI_15_ARADDR; + input [1:0] AXI_15_ARBURST; + (* invertible_pin = "IS_AXI_15_ARESET_N_INVERTED" *) + input AXI_15_ARESET_N; + input [5:0] AXI_15_ARID; + input [3:0] AXI_15_ARLEN; + input [2:0] AXI_15_ARSIZE; + input AXI_15_ARVALID; + input [36:0] AXI_15_AWADDR; + input [1:0] AXI_15_AWBURST; + input [5:0] AXI_15_AWID; + input [3:0] AXI_15_AWLEN; + input [2:0] AXI_15_AWSIZE; + input AXI_15_AWVALID; + input AXI_15_BREADY; + input AXI_15_DFI_LP_PWR_X_REQ; + input AXI_15_RREADY; + input [255:0] AXI_15_WDATA; + input [31:0] AXI_15_WDATA_PARITY; + input AXI_15_WLAST; + input [31:0] AXI_15_WSTRB; + input AXI_15_WVALID; + input BSCAN_DRCK; + input BSCAN_TCK; + input HBM_REF_CLK; + input MBIST_EN_00; + input MBIST_EN_01; + input MBIST_EN_02; + input MBIST_EN_03; + input MBIST_EN_04; + input MBIST_EN_05; + input MBIST_EN_06; + input MBIST_EN_07; +endmodule + +(* keep *) +module HBM_TWO_STACK_INTF (...); + parameter CLK_SEL_00 = "FALSE"; + parameter CLK_SEL_01 = "FALSE"; + parameter CLK_SEL_02 = "FALSE"; + parameter CLK_SEL_03 = "FALSE"; + parameter CLK_SEL_04 = "FALSE"; + parameter CLK_SEL_05 = "FALSE"; + parameter CLK_SEL_06 = "FALSE"; + parameter CLK_SEL_07 = "FALSE"; + parameter CLK_SEL_08 = "FALSE"; + parameter CLK_SEL_09 = "FALSE"; + parameter CLK_SEL_10 = "FALSE"; + parameter CLK_SEL_11 = "FALSE"; + parameter CLK_SEL_12 = "FALSE"; + parameter CLK_SEL_13 = "FALSE"; + parameter CLK_SEL_14 = "FALSE"; + parameter CLK_SEL_15 = "FALSE"; + parameter CLK_SEL_16 = "FALSE"; + parameter CLK_SEL_17 = "FALSE"; + parameter CLK_SEL_18 = "FALSE"; + parameter CLK_SEL_19 = "FALSE"; + parameter CLK_SEL_20 = "FALSE"; + parameter CLK_SEL_21 = "FALSE"; + parameter CLK_SEL_22 = "FALSE"; + parameter CLK_SEL_23 = "FALSE"; + parameter CLK_SEL_24 = "FALSE"; + parameter CLK_SEL_25 = "FALSE"; + parameter CLK_SEL_26 = "FALSE"; + parameter CLK_SEL_27 = "FALSE"; + parameter CLK_SEL_28 = "FALSE"; + parameter CLK_SEL_29 = "FALSE"; + parameter CLK_SEL_30 = "FALSE"; + parameter CLK_SEL_31 = "FALSE"; + parameter integer DATARATE_00 = 1800; + parameter integer DATARATE_01 = 1800; + parameter integer DATARATE_02 = 1800; + parameter integer DATARATE_03 = 1800; + parameter integer DATARATE_04 = 1800; + parameter integer DATARATE_05 = 1800; + parameter integer DATARATE_06 = 1800; + parameter integer DATARATE_07 = 1800; + parameter integer DATARATE_08 = 1800; + parameter integer DATARATE_09 = 1800; + parameter integer DATARATE_10 = 1800; + parameter integer DATARATE_11 = 1800; + parameter integer DATARATE_12 = 1800; + parameter integer DATARATE_13 = 1800; + parameter integer DATARATE_14 = 1800; + parameter integer DATARATE_15 = 1800; + parameter DA_LOCKOUT_0 = "FALSE"; + parameter DA_LOCKOUT_1 = "FALSE"; + parameter [0:0] IS_APB_0_PCLK_INVERTED = 1'b0; + parameter [0:0] IS_APB_0_PRESET_N_INVERTED = 1'b0; + parameter [0:0] IS_APB_1_PCLK_INVERTED = 1'b0; + parameter [0:0] IS_APB_1_PRESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_00_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_00_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_01_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_01_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_02_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_02_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_03_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_03_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_04_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_04_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_05_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_05_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_06_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_06_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_07_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_07_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_08_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_08_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_09_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_09_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_10_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_10_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_11_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_11_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_12_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_12_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_13_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_13_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_14_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_14_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_15_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_15_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_16_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_16_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_17_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_17_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_18_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_18_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_19_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_19_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_20_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_20_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_21_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_21_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_22_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_22_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_23_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_23_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_24_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_24_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_25_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_25_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_26_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_26_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_27_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_27_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_28_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_28_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_29_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_29_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_30_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_30_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_31_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_31_ARESET_N_INVERTED = 1'b0; + parameter MC_ENABLE_00 = "FALSE"; + parameter MC_ENABLE_01 = "FALSE"; + parameter MC_ENABLE_02 = "FALSE"; + parameter MC_ENABLE_03 = "FALSE"; + parameter MC_ENABLE_04 = "FALSE"; + parameter MC_ENABLE_05 = "FALSE"; + parameter MC_ENABLE_06 = "FALSE"; + parameter MC_ENABLE_07 = "FALSE"; + parameter MC_ENABLE_08 = "FALSE"; + parameter MC_ENABLE_09 = "FALSE"; + parameter MC_ENABLE_10 = "FALSE"; + parameter MC_ENABLE_11 = "FALSE"; + parameter MC_ENABLE_12 = "FALSE"; + parameter MC_ENABLE_13 = "FALSE"; + parameter MC_ENABLE_14 = "FALSE"; + parameter MC_ENABLE_15 = "FALSE"; + parameter MC_ENABLE_APB_00 = "FALSE"; + parameter MC_ENABLE_APB_01 = "FALSE"; + parameter integer PAGEHIT_PERCENT_00 = 75; + parameter integer PAGEHIT_PERCENT_01 = 75; + parameter PHY_ENABLE_00 = "FALSE"; + parameter PHY_ENABLE_01 = "FALSE"; + parameter PHY_ENABLE_02 = "FALSE"; + parameter PHY_ENABLE_03 = "FALSE"; + parameter PHY_ENABLE_04 = "FALSE"; + parameter PHY_ENABLE_05 = "FALSE"; + parameter PHY_ENABLE_06 = "FALSE"; + parameter PHY_ENABLE_07 = "FALSE"; + parameter PHY_ENABLE_08 = "FALSE"; + parameter PHY_ENABLE_09 = "FALSE"; + parameter PHY_ENABLE_10 = "FALSE"; + parameter PHY_ENABLE_11 = "FALSE"; + parameter PHY_ENABLE_12 = "FALSE"; + parameter PHY_ENABLE_13 = "FALSE"; + parameter PHY_ENABLE_14 = "FALSE"; + parameter PHY_ENABLE_15 = "FALSE"; + parameter PHY_ENABLE_16 = "FALSE"; + parameter PHY_ENABLE_17 = "FALSE"; + parameter PHY_ENABLE_18 = "FALSE"; + parameter PHY_ENABLE_19 = "FALSE"; + parameter PHY_ENABLE_20 = "FALSE"; + parameter PHY_ENABLE_21 = "FALSE"; + parameter PHY_ENABLE_22 = "FALSE"; + parameter PHY_ENABLE_23 = "FALSE"; + parameter PHY_ENABLE_24 = "FALSE"; + parameter PHY_ENABLE_25 = "FALSE"; + parameter PHY_ENABLE_26 = "FALSE"; + parameter PHY_ENABLE_27 = "FALSE"; + parameter PHY_ENABLE_28 = "FALSE"; + parameter PHY_ENABLE_29 = "FALSE"; + parameter PHY_ENABLE_30 = "FALSE"; + parameter PHY_ENABLE_31 = "FALSE"; + parameter PHY_ENABLE_APB_00 = "FALSE"; + parameter PHY_ENABLE_APB_01 = "FALSE"; + parameter PHY_PCLK_INVERT_01 = "FALSE"; + parameter PHY_PCLK_INVERT_02 = "FALSE"; + parameter integer READ_PERCENT_00 = 50; + parameter integer READ_PERCENT_01 = 50; + parameter integer READ_PERCENT_02 = 50; + parameter integer READ_PERCENT_03 = 50; + parameter integer READ_PERCENT_04 = 50; + parameter integer READ_PERCENT_05 = 50; + parameter integer READ_PERCENT_06 = 50; + parameter integer READ_PERCENT_07 = 50; + parameter integer READ_PERCENT_08 = 50; + parameter integer READ_PERCENT_09 = 50; + parameter integer READ_PERCENT_10 = 50; + parameter integer READ_PERCENT_11 = 50; + parameter integer READ_PERCENT_12 = 50; + parameter integer READ_PERCENT_13 = 50; + parameter integer READ_PERCENT_14 = 50; + parameter integer READ_PERCENT_15 = 50; + parameter integer READ_PERCENT_16 = 50; + parameter integer READ_PERCENT_17 = 50; + parameter integer READ_PERCENT_18 = 50; + parameter integer READ_PERCENT_19 = 50; + parameter integer READ_PERCENT_20 = 50; + parameter integer READ_PERCENT_21 = 50; + parameter integer READ_PERCENT_22 = 50; + parameter integer READ_PERCENT_23 = 50; + parameter integer READ_PERCENT_24 = 50; + parameter integer READ_PERCENT_25 = 50; + parameter integer READ_PERCENT_26 = 50; + parameter integer READ_PERCENT_27 = 50; + parameter integer READ_PERCENT_28 = 50; + parameter integer READ_PERCENT_29 = 50; + parameter integer READ_PERCENT_30 = 50; + parameter integer READ_PERCENT_31 = 50; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter SWITCH_ENABLE_00 = "FALSE"; + parameter SWITCH_ENABLE_01 = "FALSE"; + parameter integer WRITE_PERCENT_00 = 50; + parameter integer WRITE_PERCENT_01 = 50; + parameter integer WRITE_PERCENT_02 = 50; + parameter integer WRITE_PERCENT_03 = 50; + parameter integer WRITE_PERCENT_04 = 50; + parameter integer WRITE_PERCENT_05 = 50; + parameter integer WRITE_PERCENT_06 = 50; + parameter integer WRITE_PERCENT_07 = 50; + parameter integer WRITE_PERCENT_08 = 50; + parameter integer WRITE_PERCENT_09 = 50; + parameter integer WRITE_PERCENT_10 = 50; + parameter integer WRITE_PERCENT_11 = 50; + parameter integer WRITE_PERCENT_12 = 50; + parameter integer WRITE_PERCENT_13 = 50; + parameter integer WRITE_PERCENT_14 = 50; + parameter integer WRITE_PERCENT_15 = 50; + parameter integer WRITE_PERCENT_16 = 50; + parameter integer WRITE_PERCENT_17 = 50; + parameter integer WRITE_PERCENT_18 = 50; + parameter integer WRITE_PERCENT_19 = 50; + parameter integer WRITE_PERCENT_20 = 50; + parameter integer WRITE_PERCENT_21 = 50; + parameter integer WRITE_PERCENT_22 = 50; + parameter integer WRITE_PERCENT_23 = 50; + parameter integer WRITE_PERCENT_24 = 50; + parameter integer WRITE_PERCENT_25 = 50; + parameter integer WRITE_PERCENT_26 = 50; + parameter integer WRITE_PERCENT_27 = 50; + parameter integer WRITE_PERCENT_28 = 50; + parameter integer WRITE_PERCENT_29 = 50; + parameter integer WRITE_PERCENT_30 = 50; + parameter integer WRITE_PERCENT_31 = 50; + output [31:0] APB_0_PRDATA; + output APB_0_PREADY; + output APB_0_PSLVERR; + output [31:0] APB_1_PRDATA; + output APB_1_PREADY; + output APB_1_PSLVERR; + output AXI_00_ARREADY; + output AXI_00_AWREADY; + output [5:0] AXI_00_BID; + output [1:0] AXI_00_BRESP; + output AXI_00_BVALID; + output [1:0] AXI_00_DFI_AW_AERR_N; + output AXI_00_DFI_CLK_BUF; + output [7:0] AXI_00_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_00_DFI_DW_RDDATA_DBI; + output [7:0] AXI_00_DFI_DW_RDDATA_DERR; + output [1:0] AXI_00_DFI_DW_RDDATA_VALID; + output AXI_00_DFI_INIT_COMPLETE; + output AXI_00_DFI_PHYUPD_REQ; + output AXI_00_DFI_PHY_LP_STATE; + output AXI_00_DFI_RST_N_BUF; + output [5:0] AXI_00_MC_STATUS; + output [7:0] AXI_00_PHY_STATUS; + output [255:0] AXI_00_RDATA; + output [31:0] AXI_00_RDATA_PARITY; + output [5:0] AXI_00_RID; + output AXI_00_RLAST; + output [1:0] AXI_00_RRESP; + output AXI_00_RVALID; + output AXI_00_WREADY; + output AXI_01_ARREADY; + output AXI_01_AWREADY; + output [5:0] AXI_01_BID; + output [1:0] AXI_01_BRESP; + output AXI_01_BVALID; + output [1:0] AXI_01_DFI_AW_AERR_N; + output AXI_01_DFI_CLK_BUF; + output [7:0] AXI_01_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_01_DFI_DW_RDDATA_DBI; + output [7:0] AXI_01_DFI_DW_RDDATA_DERR; + output [1:0] AXI_01_DFI_DW_RDDATA_VALID; + output AXI_01_DFI_INIT_COMPLETE; + output AXI_01_DFI_PHYUPD_REQ; + output AXI_01_DFI_PHY_LP_STATE; + output AXI_01_DFI_RST_N_BUF; + output [255:0] AXI_01_RDATA; + output [31:0] AXI_01_RDATA_PARITY; + output [5:0] AXI_01_RID; + output AXI_01_RLAST; + output [1:0] AXI_01_RRESP; + output AXI_01_RVALID; + output AXI_01_WREADY; + output AXI_02_ARREADY; + output AXI_02_AWREADY; + output [5:0] AXI_02_BID; + output [1:0] AXI_02_BRESP; + output AXI_02_BVALID; + output [1:0] AXI_02_DFI_AW_AERR_N; + output AXI_02_DFI_CLK_BUF; + output [7:0] AXI_02_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_02_DFI_DW_RDDATA_DBI; + output [7:0] AXI_02_DFI_DW_RDDATA_DERR; + output [1:0] AXI_02_DFI_DW_RDDATA_VALID; + output AXI_02_DFI_INIT_COMPLETE; + output AXI_02_DFI_PHYUPD_REQ; + output AXI_02_DFI_PHY_LP_STATE; + output AXI_02_DFI_RST_N_BUF; + output [5:0] AXI_02_MC_STATUS; + output [7:0] AXI_02_PHY_STATUS; + output [255:0] AXI_02_RDATA; + output [31:0] AXI_02_RDATA_PARITY; + output [5:0] AXI_02_RID; + output AXI_02_RLAST; + output [1:0] AXI_02_RRESP; + output AXI_02_RVALID; + output AXI_02_WREADY; + output AXI_03_ARREADY; + output AXI_03_AWREADY; + output [5:0] AXI_03_BID; + output [1:0] AXI_03_BRESP; + output AXI_03_BVALID; + output [1:0] AXI_03_DFI_AW_AERR_N; + output AXI_03_DFI_CLK_BUF; + output [7:0] AXI_03_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_03_DFI_DW_RDDATA_DBI; + output [7:0] AXI_03_DFI_DW_RDDATA_DERR; + output [1:0] AXI_03_DFI_DW_RDDATA_VALID; + output AXI_03_DFI_INIT_COMPLETE; + output AXI_03_DFI_PHYUPD_REQ; + output AXI_03_DFI_PHY_LP_STATE; + output AXI_03_DFI_RST_N_BUF; + output [255:0] AXI_03_RDATA; + output [31:0] AXI_03_RDATA_PARITY; + output [5:0] AXI_03_RID; + output AXI_03_RLAST; + output [1:0] AXI_03_RRESP; + output AXI_03_RVALID; + output AXI_03_WREADY; + output AXI_04_ARREADY; + output AXI_04_AWREADY; + output [5:0] AXI_04_BID; + output [1:0] AXI_04_BRESP; + output AXI_04_BVALID; + output [1:0] AXI_04_DFI_AW_AERR_N; + output AXI_04_DFI_CLK_BUF; + output [7:0] AXI_04_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_04_DFI_DW_RDDATA_DBI; + output [7:0] AXI_04_DFI_DW_RDDATA_DERR; + output [1:0] AXI_04_DFI_DW_RDDATA_VALID; + output AXI_04_DFI_INIT_COMPLETE; + output AXI_04_DFI_PHYUPD_REQ; + output AXI_04_DFI_PHY_LP_STATE; + output AXI_04_DFI_RST_N_BUF; + output [5:0] AXI_04_MC_STATUS; + output [7:0] AXI_04_PHY_STATUS; + output [255:0] AXI_04_RDATA; + output [31:0] AXI_04_RDATA_PARITY; + output [5:0] AXI_04_RID; + output AXI_04_RLAST; + output [1:0] AXI_04_RRESP; + output AXI_04_RVALID; + output AXI_04_WREADY; + output AXI_05_ARREADY; + output AXI_05_AWREADY; + output [5:0] AXI_05_BID; + output [1:0] AXI_05_BRESP; + output AXI_05_BVALID; + output [1:0] AXI_05_DFI_AW_AERR_N; + output AXI_05_DFI_CLK_BUF; + output [7:0] AXI_05_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_05_DFI_DW_RDDATA_DBI; + output [7:0] AXI_05_DFI_DW_RDDATA_DERR; + output [1:0] AXI_05_DFI_DW_RDDATA_VALID; + output AXI_05_DFI_INIT_COMPLETE; + output AXI_05_DFI_PHYUPD_REQ; + output AXI_05_DFI_PHY_LP_STATE; + output AXI_05_DFI_RST_N_BUF; + output [255:0] AXI_05_RDATA; + output [31:0] AXI_05_RDATA_PARITY; + output [5:0] AXI_05_RID; + output AXI_05_RLAST; + output [1:0] AXI_05_RRESP; + output AXI_05_RVALID; + output AXI_05_WREADY; + output AXI_06_ARREADY; + output AXI_06_AWREADY; + output [5:0] AXI_06_BID; + output [1:0] AXI_06_BRESP; + output AXI_06_BVALID; + output [1:0] AXI_06_DFI_AW_AERR_N; + output AXI_06_DFI_CLK_BUF; + output [7:0] AXI_06_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_06_DFI_DW_RDDATA_DBI; + output [7:0] AXI_06_DFI_DW_RDDATA_DERR; + output [1:0] AXI_06_DFI_DW_RDDATA_VALID; + output AXI_06_DFI_INIT_COMPLETE; + output AXI_06_DFI_PHYUPD_REQ; + output AXI_06_DFI_PHY_LP_STATE; + output AXI_06_DFI_RST_N_BUF; + output [5:0] AXI_06_MC_STATUS; + output [7:0] AXI_06_PHY_STATUS; + output [255:0] AXI_06_RDATA; + output [31:0] AXI_06_RDATA_PARITY; + output [5:0] AXI_06_RID; + output AXI_06_RLAST; + output [1:0] AXI_06_RRESP; + output AXI_06_RVALID; + output AXI_06_WREADY; + output AXI_07_ARREADY; + output AXI_07_AWREADY; + output [5:0] AXI_07_BID; + output [1:0] AXI_07_BRESP; + output AXI_07_BVALID; + output [1:0] AXI_07_DFI_AW_AERR_N; + output AXI_07_DFI_CLK_BUF; + output [7:0] AXI_07_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_07_DFI_DW_RDDATA_DBI; + output [7:0] AXI_07_DFI_DW_RDDATA_DERR; + output [1:0] AXI_07_DFI_DW_RDDATA_VALID; + output AXI_07_DFI_INIT_COMPLETE; + output AXI_07_DFI_PHYUPD_REQ; + output AXI_07_DFI_PHY_LP_STATE; + output AXI_07_DFI_RST_N_BUF; + output [255:0] AXI_07_RDATA; + output [31:0] AXI_07_RDATA_PARITY; + output [5:0] AXI_07_RID; + output AXI_07_RLAST; + output [1:0] AXI_07_RRESP; + output AXI_07_RVALID; + output AXI_07_WREADY; + output AXI_08_ARREADY; + output AXI_08_AWREADY; + output [5:0] AXI_08_BID; + output [1:0] AXI_08_BRESP; + output AXI_08_BVALID; + output [1:0] AXI_08_DFI_AW_AERR_N; + output AXI_08_DFI_CLK_BUF; + output [7:0] AXI_08_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_08_DFI_DW_RDDATA_DBI; + output [7:0] AXI_08_DFI_DW_RDDATA_DERR; + output [1:0] AXI_08_DFI_DW_RDDATA_VALID; + output AXI_08_DFI_INIT_COMPLETE; + output AXI_08_DFI_PHYUPD_REQ; + output AXI_08_DFI_PHY_LP_STATE; + output AXI_08_DFI_RST_N_BUF; + output [5:0] AXI_08_MC_STATUS; + output [7:0] AXI_08_PHY_STATUS; + output [255:0] AXI_08_RDATA; + output [31:0] AXI_08_RDATA_PARITY; + output [5:0] AXI_08_RID; + output AXI_08_RLAST; + output [1:0] AXI_08_RRESP; + output AXI_08_RVALID; + output AXI_08_WREADY; + output AXI_09_ARREADY; + output AXI_09_AWREADY; + output [5:0] AXI_09_BID; + output [1:0] AXI_09_BRESP; + output AXI_09_BVALID; + output [1:0] AXI_09_DFI_AW_AERR_N; + output AXI_09_DFI_CLK_BUF; + output [7:0] AXI_09_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_09_DFI_DW_RDDATA_DBI; + output [7:0] AXI_09_DFI_DW_RDDATA_DERR; + output [1:0] AXI_09_DFI_DW_RDDATA_VALID; + output AXI_09_DFI_INIT_COMPLETE; + output AXI_09_DFI_PHYUPD_REQ; + output AXI_09_DFI_PHY_LP_STATE; + output AXI_09_DFI_RST_N_BUF; + output [255:0] AXI_09_RDATA; + output [31:0] AXI_09_RDATA_PARITY; + output [5:0] AXI_09_RID; + output AXI_09_RLAST; + output [1:0] AXI_09_RRESP; + output AXI_09_RVALID; + output AXI_09_WREADY; + output AXI_10_ARREADY; + output AXI_10_AWREADY; + output [5:0] AXI_10_BID; + output [1:0] AXI_10_BRESP; + output AXI_10_BVALID; + output [1:0] AXI_10_DFI_AW_AERR_N; + output AXI_10_DFI_CLK_BUF; + output [7:0] AXI_10_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_10_DFI_DW_RDDATA_DBI; + output [7:0] AXI_10_DFI_DW_RDDATA_DERR; + output [1:0] AXI_10_DFI_DW_RDDATA_VALID; + output AXI_10_DFI_INIT_COMPLETE; + output AXI_10_DFI_PHYUPD_REQ; + output AXI_10_DFI_PHY_LP_STATE; + output AXI_10_DFI_RST_N_BUF; + output [5:0] AXI_10_MC_STATUS; + output [7:0] AXI_10_PHY_STATUS; + output [255:0] AXI_10_RDATA; + output [31:0] AXI_10_RDATA_PARITY; + output [5:0] AXI_10_RID; + output AXI_10_RLAST; + output [1:0] AXI_10_RRESP; + output AXI_10_RVALID; + output AXI_10_WREADY; + output AXI_11_ARREADY; + output AXI_11_AWREADY; + output [5:0] AXI_11_BID; + output [1:0] AXI_11_BRESP; + output AXI_11_BVALID; + output [1:0] AXI_11_DFI_AW_AERR_N; + output AXI_11_DFI_CLK_BUF; + output [7:0] AXI_11_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_11_DFI_DW_RDDATA_DBI; + output [7:0] AXI_11_DFI_DW_RDDATA_DERR; + output [1:0] AXI_11_DFI_DW_RDDATA_VALID; + output AXI_11_DFI_INIT_COMPLETE; + output AXI_11_DFI_PHYUPD_REQ; + output AXI_11_DFI_PHY_LP_STATE; + output AXI_11_DFI_RST_N_BUF; + output [255:0] AXI_11_RDATA; + output [31:0] AXI_11_RDATA_PARITY; + output [5:0] AXI_11_RID; + output AXI_11_RLAST; + output [1:0] AXI_11_RRESP; + output AXI_11_RVALID; + output AXI_11_WREADY; + output AXI_12_ARREADY; + output AXI_12_AWREADY; + output [5:0] AXI_12_BID; + output [1:0] AXI_12_BRESP; + output AXI_12_BVALID; + output [1:0] AXI_12_DFI_AW_AERR_N; + output AXI_12_DFI_CLK_BUF; + output [7:0] AXI_12_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_12_DFI_DW_RDDATA_DBI; + output [7:0] AXI_12_DFI_DW_RDDATA_DERR; + output [1:0] AXI_12_DFI_DW_RDDATA_VALID; + output AXI_12_DFI_INIT_COMPLETE; + output AXI_12_DFI_PHYUPD_REQ; + output AXI_12_DFI_PHY_LP_STATE; + output AXI_12_DFI_RST_N_BUF; + output [5:0] AXI_12_MC_STATUS; + output [7:0] AXI_12_PHY_STATUS; + output [255:0] AXI_12_RDATA; + output [31:0] AXI_12_RDATA_PARITY; + output [5:0] AXI_12_RID; + output AXI_12_RLAST; + output [1:0] AXI_12_RRESP; + output AXI_12_RVALID; + output AXI_12_WREADY; + output AXI_13_ARREADY; + output AXI_13_AWREADY; + output [5:0] AXI_13_BID; + output [1:0] AXI_13_BRESP; + output AXI_13_BVALID; + output [1:0] AXI_13_DFI_AW_AERR_N; + output AXI_13_DFI_CLK_BUF; + output [7:0] AXI_13_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_13_DFI_DW_RDDATA_DBI; + output [7:0] AXI_13_DFI_DW_RDDATA_DERR; + output [1:0] AXI_13_DFI_DW_RDDATA_VALID; + output AXI_13_DFI_INIT_COMPLETE; + output AXI_13_DFI_PHYUPD_REQ; + output AXI_13_DFI_PHY_LP_STATE; + output AXI_13_DFI_RST_N_BUF; + output [255:0] AXI_13_RDATA; + output [31:0] AXI_13_RDATA_PARITY; + output [5:0] AXI_13_RID; + output AXI_13_RLAST; + output [1:0] AXI_13_RRESP; + output AXI_13_RVALID; + output AXI_13_WREADY; + output AXI_14_ARREADY; + output AXI_14_AWREADY; + output [5:0] AXI_14_BID; + output [1:0] AXI_14_BRESP; + output AXI_14_BVALID; + output [1:0] AXI_14_DFI_AW_AERR_N; + output AXI_14_DFI_CLK_BUF; + output [7:0] AXI_14_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_14_DFI_DW_RDDATA_DBI; + output [7:0] AXI_14_DFI_DW_RDDATA_DERR; + output [1:0] AXI_14_DFI_DW_RDDATA_VALID; + output AXI_14_DFI_INIT_COMPLETE; + output AXI_14_DFI_PHYUPD_REQ; + output AXI_14_DFI_PHY_LP_STATE; + output AXI_14_DFI_RST_N_BUF; + output [5:0] AXI_14_MC_STATUS; + output [7:0] AXI_14_PHY_STATUS; + output [255:0] AXI_14_RDATA; + output [31:0] AXI_14_RDATA_PARITY; + output [5:0] AXI_14_RID; + output AXI_14_RLAST; + output [1:0] AXI_14_RRESP; + output AXI_14_RVALID; + output AXI_14_WREADY; + output AXI_15_ARREADY; + output AXI_15_AWREADY; + output [5:0] AXI_15_BID; + output [1:0] AXI_15_BRESP; + output AXI_15_BVALID; + output [1:0] AXI_15_DFI_AW_AERR_N; + output AXI_15_DFI_CLK_BUF; + output [7:0] AXI_15_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_15_DFI_DW_RDDATA_DBI; + output [7:0] AXI_15_DFI_DW_RDDATA_DERR; + output [1:0] AXI_15_DFI_DW_RDDATA_VALID; + output AXI_15_DFI_INIT_COMPLETE; + output AXI_15_DFI_PHYUPD_REQ; + output AXI_15_DFI_PHY_LP_STATE; + output AXI_15_DFI_RST_N_BUF; + output [255:0] AXI_15_RDATA; + output [31:0] AXI_15_RDATA_PARITY; + output [5:0] AXI_15_RID; + output AXI_15_RLAST; + output [1:0] AXI_15_RRESP; + output AXI_15_RVALID; + output AXI_15_WREADY; + output AXI_16_ARREADY; + output AXI_16_AWREADY; + output [5:0] AXI_16_BID; + output [1:0] AXI_16_BRESP; + output AXI_16_BVALID; + output [1:0] AXI_16_DFI_AW_AERR_N; + output AXI_16_DFI_CLK_BUF; + output [7:0] AXI_16_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_16_DFI_DW_RDDATA_DBI; + output [7:0] AXI_16_DFI_DW_RDDATA_DERR; + output [1:0] AXI_16_DFI_DW_RDDATA_VALID; + output AXI_16_DFI_INIT_COMPLETE; + output AXI_16_DFI_PHYUPD_REQ; + output AXI_16_DFI_PHY_LP_STATE; + output AXI_16_DFI_RST_N_BUF; + output [5:0] AXI_16_MC_STATUS; + output [7:0] AXI_16_PHY_STATUS; + output [255:0] AXI_16_RDATA; + output [31:0] AXI_16_RDATA_PARITY; + output [5:0] AXI_16_RID; + output AXI_16_RLAST; + output [1:0] AXI_16_RRESP; + output AXI_16_RVALID; + output AXI_16_WREADY; + output AXI_17_ARREADY; + output AXI_17_AWREADY; + output [5:0] AXI_17_BID; + output [1:0] AXI_17_BRESP; + output AXI_17_BVALID; + output [1:0] AXI_17_DFI_AW_AERR_N; + output AXI_17_DFI_CLK_BUF; + output [7:0] AXI_17_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_17_DFI_DW_RDDATA_DBI; + output [7:0] AXI_17_DFI_DW_RDDATA_DERR; + output [1:0] AXI_17_DFI_DW_RDDATA_VALID; + output AXI_17_DFI_INIT_COMPLETE; + output AXI_17_DFI_PHYUPD_REQ; + output AXI_17_DFI_PHY_LP_STATE; + output AXI_17_DFI_RST_N_BUF; + output [255:0] AXI_17_RDATA; + output [31:0] AXI_17_RDATA_PARITY; + output [5:0] AXI_17_RID; + output AXI_17_RLAST; + output [1:0] AXI_17_RRESP; + output AXI_17_RVALID; + output AXI_17_WREADY; + output AXI_18_ARREADY; + output AXI_18_AWREADY; + output [5:0] AXI_18_BID; + output [1:0] AXI_18_BRESP; + output AXI_18_BVALID; + output [1:0] AXI_18_DFI_AW_AERR_N; + output AXI_18_DFI_CLK_BUF; + output [7:0] AXI_18_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_18_DFI_DW_RDDATA_DBI; + output [7:0] AXI_18_DFI_DW_RDDATA_DERR; + output [1:0] AXI_18_DFI_DW_RDDATA_VALID; + output AXI_18_DFI_INIT_COMPLETE; + output AXI_18_DFI_PHYUPD_REQ; + output AXI_18_DFI_PHY_LP_STATE; + output AXI_18_DFI_RST_N_BUF; + output [5:0] AXI_18_MC_STATUS; + output [7:0] AXI_18_PHY_STATUS; + output [255:0] AXI_18_RDATA; + output [31:0] AXI_18_RDATA_PARITY; + output [5:0] AXI_18_RID; + output AXI_18_RLAST; + output [1:0] AXI_18_RRESP; + output AXI_18_RVALID; + output AXI_18_WREADY; + output AXI_19_ARREADY; + output AXI_19_AWREADY; + output [5:0] AXI_19_BID; + output [1:0] AXI_19_BRESP; + output AXI_19_BVALID; + output [1:0] AXI_19_DFI_AW_AERR_N; + output AXI_19_DFI_CLK_BUF; + output [7:0] AXI_19_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_19_DFI_DW_RDDATA_DBI; + output [7:0] AXI_19_DFI_DW_RDDATA_DERR; + output [1:0] AXI_19_DFI_DW_RDDATA_VALID; + output AXI_19_DFI_INIT_COMPLETE; + output AXI_19_DFI_PHYUPD_REQ; + output AXI_19_DFI_PHY_LP_STATE; + output AXI_19_DFI_RST_N_BUF; + output [255:0] AXI_19_RDATA; + output [31:0] AXI_19_RDATA_PARITY; + output [5:0] AXI_19_RID; + output AXI_19_RLAST; + output [1:0] AXI_19_RRESP; + output AXI_19_RVALID; + output AXI_19_WREADY; + output AXI_20_ARREADY; + output AXI_20_AWREADY; + output [5:0] AXI_20_BID; + output [1:0] AXI_20_BRESP; + output AXI_20_BVALID; + output [1:0] AXI_20_DFI_AW_AERR_N; + output AXI_20_DFI_CLK_BUF; + output [7:0] AXI_20_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_20_DFI_DW_RDDATA_DBI; + output [7:0] AXI_20_DFI_DW_RDDATA_DERR; + output [1:0] AXI_20_DFI_DW_RDDATA_VALID; + output AXI_20_DFI_INIT_COMPLETE; + output AXI_20_DFI_PHYUPD_REQ; + output AXI_20_DFI_PHY_LP_STATE; + output AXI_20_DFI_RST_N_BUF; + output [5:0] AXI_20_MC_STATUS; + output [7:0] AXI_20_PHY_STATUS; + output [255:0] AXI_20_RDATA; + output [31:0] AXI_20_RDATA_PARITY; + output [5:0] AXI_20_RID; + output AXI_20_RLAST; + output [1:0] AXI_20_RRESP; + output AXI_20_RVALID; + output AXI_20_WREADY; + output AXI_21_ARREADY; + output AXI_21_AWREADY; + output [5:0] AXI_21_BID; + output [1:0] AXI_21_BRESP; + output AXI_21_BVALID; + output [1:0] AXI_21_DFI_AW_AERR_N; + output AXI_21_DFI_CLK_BUF; + output [7:0] AXI_21_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_21_DFI_DW_RDDATA_DBI; + output [7:0] AXI_21_DFI_DW_RDDATA_DERR; + output [1:0] AXI_21_DFI_DW_RDDATA_VALID; + output AXI_21_DFI_INIT_COMPLETE; + output AXI_21_DFI_PHYUPD_REQ; + output AXI_21_DFI_PHY_LP_STATE; + output AXI_21_DFI_RST_N_BUF; + output [255:0] AXI_21_RDATA; + output [31:0] AXI_21_RDATA_PARITY; + output [5:0] AXI_21_RID; + output AXI_21_RLAST; + output [1:0] AXI_21_RRESP; + output AXI_21_RVALID; + output AXI_21_WREADY; + output AXI_22_ARREADY; + output AXI_22_AWREADY; + output [5:0] AXI_22_BID; + output [1:0] AXI_22_BRESP; + output AXI_22_BVALID; + output [1:0] AXI_22_DFI_AW_AERR_N; + output AXI_22_DFI_CLK_BUF; + output [7:0] AXI_22_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_22_DFI_DW_RDDATA_DBI; + output [7:0] AXI_22_DFI_DW_RDDATA_DERR; + output [1:0] AXI_22_DFI_DW_RDDATA_VALID; + output AXI_22_DFI_INIT_COMPLETE; + output AXI_22_DFI_PHYUPD_REQ; + output AXI_22_DFI_PHY_LP_STATE; + output AXI_22_DFI_RST_N_BUF; + output [5:0] AXI_22_MC_STATUS; + output [7:0] AXI_22_PHY_STATUS; + output [255:0] AXI_22_RDATA; + output [31:0] AXI_22_RDATA_PARITY; + output [5:0] AXI_22_RID; + output AXI_22_RLAST; + output [1:0] AXI_22_RRESP; + output AXI_22_RVALID; + output AXI_22_WREADY; + output AXI_23_ARREADY; + output AXI_23_AWREADY; + output [5:0] AXI_23_BID; + output [1:0] AXI_23_BRESP; + output AXI_23_BVALID; + output [1:0] AXI_23_DFI_AW_AERR_N; + output AXI_23_DFI_CLK_BUF; + output [7:0] AXI_23_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_23_DFI_DW_RDDATA_DBI; + output [7:0] AXI_23_DFI_DW_RDDATA_DERR; + output [1:0] AXI_23_DFI_DW_RDDATA_VALID; + output AXI_23_DFI_INIT_COMPLETE; + output AXI_23_DFI_PHYUPD_REQ; + output AXI_23_DFI_PHY_LP_STATE; + output AXI_23_DFI_RST_N_BUF; + output [255:0] AXI_23_RDATA; + output [31:0] AXI_23_RDATA_PARITY; + output [5:0] AXI_23_RID; + output AXI_23_RLAST; + output [1:0] AXI_23_RRESP; + output AXI_23_RVALID; + output AXI_23_WREADY; + output AXI_24_ARREADY; + output AXI_24_AWREADY; + output [5:0] AXI_24_BID; + output [1:0] AXI_24_BRESP; + output AXI_24_BVALID; + output [1:0] AXI_24_DFI_AW_AERR_N; + output AXI_24_DFI_CLK_BUF; + output [7:0] AXI_24_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_24_DFI_DW_RDDATA_DBI; + output [7:0] AXI_24_DFI_DW_RDDATA_DERR; + output [1:0] AXI_24_DFI_DW_RDDATA_VALID; + output AXI_24_DFI_INIT_COMPLETE; + output AXI_24_DFI_PHYUPD_REQ; + output AXI_24_DFI_PHY_LP_STATE; + output AXI_24_DFI_RST_N_BUF; + output [5:0] AXI_24_MC_STATUS; + output [7:0] AXI_24_PHY_STATUS; + output [255:0] AXI_24_RDATA; + output [31:0] AXI_24_RDATA_PARITY; + output [5:0] AXI_24_RID; + output AXI_24_RLAST; + output [1:0] AXI_24_RRESP; + output AXI_24_RVALID; + output AXI_24_WREADY; + output AXI_25_ARREADY; + output AXI_25_AWREADY; + output [5:0] AXI_25_BID; + output [1:0] AXI_25_BRESP; + output AXI_25_BVALID; + output [1:0] AXI_25_DFI_AW_AERR_N; + output AXI_25_DFI_CLK_BUF; + output [7:0] AXI_25_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_25_DFI_DW_RDDATA_DBI; + output [7:0] AXI_25_DFI_DW_RDDATA_DERR; + output [1:0] AXI_25_DFI_DW_RDDATA_VALID; + output AXI_25_DFI_INIT_COMPLETE; + output AXI_25_DFI_PHYUPD_REQ; + output AXI_25_DFI_PHY_LP_STATE; + output AXI_25_DFI_RST_N_BUF; + output [255:0] AXI_25_RDATA; + output [31:0] AXI_25_RDATA_PARITY; + output [5:0] AXI_25_RID; + output AXI_25_RLAST; + output [1:0] AXI_25_RRESP; + output AXI_25_RVALID; + output AXI_25_WREADY; + output AXI_26_ARREADY; + output AXI_26_AWREADY; + output [5:0] AXI_26_BID; + output [1:0] AXI_26_BRESP; + output AXI_26_BVALID; + output [1:0] AXI_26_DFI_AW_AERR_N; + output AXI_26_DFI_CLK_BUF; + output [7:0] AXI_26_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_26_DFI_DW_RDDATA_DBI; + output [7:0] AXI_26_DFI_DW_RDDATA_DERR; + output [1:0] AXI_26_DFI_DW_RDDATA_VALID; + output AXI_26_DFI_INIT_COMPLETE; + output AXI_26_DFI_PHYUPD_REQ; + output AXI_26_DFI_PHY_LP_STATE; + output AXI_26_DFI_RST_N_BUF; + output [5:0] AXI_26_MC_STATUS; + output [7:0] AXI_26_PHY_STATUS; + output [255:0] AXI_26_RDATA; + output [31:0] AXI_26_RDATA_PARITY; + output [5:0] AXI_26_RID; + output AXI_26_RLAST; + output [1:0] AXI_26_RRESP; + output AXI_26_RVALID; + output AXI_26_WREADY; + output AXI_27_ARREADY; + output AXI_27_AWREADY; + output [5:0] AXI_27_BID; + output [1:0] AXI_27_BRESP; + output AXI_27_BVALID; + output [1:0] AXI_27_DFI_AW_AERR_N; + output AXI_27_DFI_CLK_BUF; + output [7:0] AXI_27_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_27_DFI_DW_RDDATA_DBI; + output [7:0] AXI_27_DFI_DW_RDDATA_DERR; + output [1:0] AXI_27_DFI_DW_RDDATA_VALID; + output AXI_27_DFI_INIT_COMPLETE; + output AXI_27_DFI_PHYUPD_REQ; + output AXI_27_DFI_PHY_LP_STATE; + output AXI_27_DFI_RST_N_BUF; + output [255:0] AXI_27_RDATA; + output [31:0] AXI_27_RDATA_PARITY; + output [5:0] AXI_27_RID; + output AXI_27_RLAST; + output [1:0] AXI_27_RRESP; + output AXI_27_RVALID; + output AXI_27_WREADY; + output AXI_28_ARREADY; + output AXI_28_AWREADY; + output [5:0] AXI_28_BID; + output [1:0] AXI_28_BRESP; + output AXI_28_BVALID; + output [1:0] AXI_28_DFI_AW_AERR_N; + output AXI_28_DFI_CLK_BUF; + output [7:0] AXI_28_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_28_DFI_DW_RDDATA_DBI; + output [7:0] AXI_28_DFI_DW_RDDATA_DERR; + output [1:0] AXI_28_DFI_DW_RDDATA_VALID; + output AXI_28_DFI_INIT_COMPLETE; + output AXI_28_DFI_PHYUPD_REQ; + output AXI_28_DFI_PHY_LP_STATE; + output AXI_28_DFI_RST_N_BUF; + output [5:0] AXI_28_MC_STATUS; + output [7:0] AXI_28_PHY_STATUS; + output [255:0] AXI_28_RDATA; + output [31:0] AXI_28_RDATA_PARITY; + output [5:0] AXI_28_RID; + output AXI_28_RLAST; + output [1:0] AXI_28_RRESP; + output AXI_28_RVALID; + output AXI_28_WREADY; + output AXI_29_ARREADY; + output AXI_29_AWREADY; + output [5:0] AXI_29_BID; + output [1:0] AXI_29_BRESP; + output AXI_29_BVALID; + output [1:0] AXI_29_DFI_AW_AERR_N; + output AXI_29_DFI_CLK_BUF; + output [7:0] AXI_29_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_29_DFI_DW_RDDATA_DBI; + output [7:0] AXI_29_DFI_DW_RDDATA_DERR; + output [1:0] AXI_29_DFI_DW_RDDATA_VALID; + output AXI_29_DFI_INIT_COMPLETE; + output AXI_29_DFI_PHYUPD_REQ; + output AXI_29_DFI_PHY_LP_STATE; + output AXI_29_DFI_RST_N_BUF; + output [255:0] AXI_29_RDATA; + output [31:0] AXI_29_RDATA_PARITY; + output [5:0] AXI_29_RID; + output AXI_29_RLAST; + output [1:0] AXI_29_RRESP; + output AXI_29_RVALID; + output AXI_29_WREADY; + output AXI_30_ARREADY; + output AXI_30_AWREADY; + output [5:0] AXI_30_BID; + output [1:0] AXI_30_BRESP; + output AXI_30_BVALID; + output [1:0] AXI_30_DFI_AW_AERR_N; + output AXI_30_DFI_CLK_BUF; + output [7:0] AXI_30_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_30_DFI_DW_RDDATA_DBI; + output [7:0] AXI_30_DFI_DW_RDDATA_DERR; + output [1:0] AXI_30_DFI_DW_RDDATA_VALID; + output AXI_30_DFI_INIT_COMPLETE; + output AXI_30_DFI_PHYUPD_REQ; + output AXI_30_DFI_PHY_LP_STATE; + output AXI_30_DFI_RST_N_BUF; + output [5:0] AXI_30_MC_STATUS; + output [7:0] AXI_30_PHY_STATUS; + output [255:0] AXI_30_RDATA; + output [31:0] AXI_30_RDATA_PARITY; + output [5:0] AXI_30_RID; + output AXI_30_RLAST; + output [1:0] AXI_30_RRESP; + output AXI_30_RVALID; + output AXI_30_WREADY; + output AXI_31_ARREADY; + output AXI_31_AWREADY; + output [5:0] AXI_31_BID; + output [1:0] AXI_31_BRESP; + output AXI_31_BVALID; + output [1:0] AXI_31_DFI_AW_AERR_N; + output AXI_31_DFI_CLK_BUF; + output [7:0] AXI_31_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_31_DFI_DW_RDDATA_DBI; + output [7:0] AXI_31_DFI_DW_RDDATA_DERR; + output [1:0] AXI_31_DFI_DW_RDDATA_VALID; + output AXI_31_DFI_INIT_COMPLETE; + output AXI_31_DFI_PHYUPD_REQ; + output AXI_31_DFI_PHY_LP_STATE; + output AXI_31_DFI_RST_N_BUF; + output [255:0] AXI_31_RDATA; + output [31:0] AXI_31_RDATA_PARITY; + output [5:0] AXI_31_RID; + output AXI_31_RLAST; + output [1:0] AXI_31_RRESP; + output AXI_31_RVALID; + output AXI_31_WREADY; + output DRAM_0_STAT_CATTRIP; + output [2:0] DRAM_0_STAT_TEMP; + output DRAM_1_STAT_CATTRIP; + output [2:0] DRAM_1_STAT_TEMP; + input [21:0] APB_0_PADDR; + (* invertible_pin = "IS_APB_0_PCLK_INVERTED" *) + input APB_0_PCLK; + input APB_0_PENABLE; + (* invertible_pin = "IS_APB_0_PRESET_N_INVERTED" *) + input APB_0_PRESET_N; + input APB_0_PSEL; + input [31:0] APB_0_PWDATA; + input APB_0_PWRITE; + input [21:0] APB_1_PADDR; + (* invertible_pin = "IS_APB_1_PCLK_INVERTED" *) + input APB_1_PCLK; + input APB_1_PENABLE; + (* invertible_pin = "IS_APB_1_PRESET_N_INVERTED" *) + input APB_1_PRESET_N; + input APB_1_PSEL; + input [31:0] APB_1_PWDATA; + input APB_1_PWRITE; + (* invertible_pin = "IS_AXI_00_ACLK_INVERTED" *) + input AXI_00_ACLK; + input [36:0] AXI_00_ARADDR; + input [1:0] AXI_00_ARBURST; + (* invertible_pin = "IS_AXI_00_ARESET_N_INVERTED" *) + input AXI_00_ARESET_N; + input [5:0] AXI_00_ARID; + input [3:0] AXI_00_ARLEN; + input [2:0] AXI_00_ARSIZE; + input AXI_00_ARVALID; + input [36:0] AXI_00_AWADDR; + input [1:0] AXI_00_AWBURST; + input [5:0] AXI_00_AWID; + input [3:0] AXI_00_AWLEN; + input [2:0] AXI_00_AWSIZE; + input AXI_00_AWVALID; + input AXI_00_BREADY; + input AXI_00_DFI_LP_PWR_X_REQ; + input AXI_00_RREADY; + input [255:0] AXI_00_WDATA; + input [31:0] AXI_00_WDATA_PARITY; + input AXI_00_WLAST; + input [31:0] AXI_00_WSTRB; + input AXI_00_WVALID; + (* invertible_pin = "IS_AXI_01_ACLK_INVERTED" *) + input AXI_01_ACLK; + input [36:0] AXI_01_ARADDR; + input [1:0] AXI_01_ARBURST; + (* invertible_pin = "IS_AXI_01_ARESET_N_INVERTED" *) + input AXI_01_ARESET_N; + input [5:0] AXI_01_ARID; + input [3:0] AXI_01_ARLEN; + input [2:0] AXI_01_ARSIZE; + input AXI_01_ARVALID; + input [36:0] AXI_01_AWADDR; + input [1:0] AXI_01_AWBURST; + input [5:0] AXI_01_AWID; + input [3:0] AXI_01_AWLEN; + input [2:0] AXI_01_AWSIZE; + input AXI_01_AWVALID; + input AXI_01_BREADY; + input AXI_01_DFI_LP_PWR_X_REQ; + input AXI_01_RREADY; + input [255:0] AXI_01_WDATA; + input [31:0] AXI_01_WDATA_PARITY; + input AXI_01_WLAST; + input [31:0] AXI_01_WSTRB; + input AXI_01_WVALID; + (* invertible_pin = "IS_AXI_02_ACLK_INVERTED" *) + input AXI_02_ACLK; + input [36:0] AXI_02_ARADDR; + input [1:0] AXI_02_ARBURST; + (* invertible_pin = "IS_AXI_02_ARESET_N_INVERTED" *) + input AXI_02_ARESET_N; + input [5:0] AXI_02_ARID; + input [3:0] AXI_02_ARLEN; + input [2:0] AXI_02_ARSIZE; + input AXI_02_ARVALID; + input [36:0] AXI_02_AWADDR; + input [1:0] AXI_02_AWBURST; + input [5:0] AXI_02_AWID; + input [3:0] AXI_02_AWLEN; + input [2:0] AXI_02_AWSIZE; + input AXI_02_AWVALID; + input AXI_02_BREADY; + input AXI_02_DFI_LP_PWR_X_REQ; + input AXI_02_RREADY; + input [255:0] AXI_02_WDATA; + input [31:0] AXI_02_WDATA_PARITY; + input AXI_02_WLAST; + input [31:0] AXI_02_WSTRB; + input AXI_02_WVALID; + (* invertible_pin = "IS_AXI_03_ACLK_INVERTED" *) + input AXI_03_ACLK; + input [36:0] AXI_03_ARADDR; + input [1:0] AXI_03_ARBURST; + (* invertible_pin = "IS_AXI_03_ARESET_N_INVERTED" *) + input AXI_03_ARESET_N; + input [5:0] AXI_03_ARID; + input [3:0] AXI_03_ARLEN; + input [2:0] AXI_03_ARSIZE; + input AXI_03_ARVALID; + input [36:0] AXI_03_AWADDR; + input [1:0] AXI_03_AWBURST; + input [5:0] AXI_03_AWID; + input [3:0] AXI_03_AWLEN; + input [2:0] AXI_03_AWSIZE; + input AXI_03_AWVALID; + input AXI_03_BREADY; + input AXI_03_DFI_LP_PWR_X_REQ; + input AXI_03_RREADY; + input [255:0] AXI_03_WDATA; + input [31:0] AXI_03_WDATA_PARITY; + input AXI_03_WLAST; + input [31:0] AXI_03_WSTRB; + input AXI_03_WVALID; + (* invertible_pin = "IS_AXI_04_ACLK_INVERTED" *) + input AXI_04_ACLK; + input [36:0] AXI_04_ARADDR; + input [1:0] AXI_04_ARBURST; + (* invertible_pin = "IS_AXI_04_ARESET_N_INVERTED" *) + input AXI_04_ARESET_N; + input [5:0] AXI_04_ARID; + input [3:0] AXI_04_ARLEN; + input [2:0] AXI_04_ARSIZE; + input AXI_04_ARVALID; + input [36:0] AXI_04_AWADDR; + input [1:0] AXI_04_AWBURST; + input [5:0] AXI_04_AWID; + input [3:0] AXI_04_AWLEN; + input [2:0] AXI_04_AWSIZE; + input AXI_04_AWVALID; + input AXI_04_BREADY; + input AXI_04_DFI_LP_PWR_X_REQ; + input AXI_04_RREADY; + input [255:0] AXI_04_WDATA; + input [31:0] AXI_04_WDATA_PARITY; + input AXI_04_WLAST; + input [31:0] AXI_04_WSTRB; + input AXI_04_WVALID; + (* invertible_pin = "IS_AXI_05_ACLK_INVERTED" *) + input AXI_05_ACLK; + input [36:0] AXI_05_ARADDR; + input [1:0] AXI_05_ARBURST; + (* invertible_pin = "IS_AXI_05_ARESET_N_INVERTED" *) + input AXI_05_ARESET_N; + input [5:0] AXI_05_ARID; + input [3:0] AXI_05_ARLEN; + input [2:0] AXI_05_ARSIZE; + input AXI_05_ARVALID; + input [36:0] AXI_05_AWADDR; + input [1:0] AXI_05_AWBURST; + input [5:0] AXI_05_AWID; + input [3:0] AXI_05_AWLEN; + input [2:0] AXI_05_AWSIZE; + input AXI_05_AWVALID; + input AXI_05_BREADY; + input AXI_05_DFI_LP_PWR_X_REQ; + input AXI_05_RREADY; + input [255:0] AXI_05_WDATA; + input [31:0] AXI_05_WDATA_PARITY; + input AXI_05_WLAST; + input [31:0] AXI_05_WSTRB; + input AXI_05_WVALID; + (* invertible_pin = "IS_AXI_06_ACLK_INVERTED" *) + input AXI_06_ACLK; + input [36:0] AXI_06_ARADDR; + input [1:0] AXI_06_ARBURST; + (* invertible_pin = "IS_AXI_06_ARESET_N_INVERTED" *) + input AXI_06_ARESET_N; + input [5:0] AXI_06_ARID; + input [3:0] AXI_06_ARLEN; + input [2:0] AXI_06_ARSIZE; + input AXI_06_ARVALID; + input [36:0] AXI_06_AWADDR; + input [1:0] AXI_06_AWBURST; + input [5:0] AXI_06_AWID; + input [3:0] AXI_06_AWLEN; + input [2:0] AXI_06_AWSIZE; + input AXI_06_AWVALID; + input AXI_06_BREADY; + input AXI_06_DFI_LP_PWR_X_REQ; + input AXI_06_RREADY; + input [255:0] AXI_06_WDATA; + input [31:0] AXI_06_WDATA_PARITY; + input AXI_06_WLAST; + input [31:0] AXI_06_WSTRB; + input AXI_06_WVALID; + (* invertible_pin = "IS_AXI_07_ACLK_INVERTED" *) + input AXI_07_ACLK; + input [36:0] AXI_07_ARADDR; + input [1:0] AXI_07_ARBURST; + (* invertible_pin = "IS_AXI_07_ARESET_N_INVERTED" *) + input AXI_07_ARESET_N; + input [5:0] AXI_07_ARID; + input [3:0] AXI_07_ARLEN; + input [2:0] AXI_07_ARSIZE; + input AXI_07_ARVALID; + input [36:0] AXI_07_AWADDR; + input [1:0] AXI_07_AWBURST; + input [5:0] AXI_07_AWID; + input [3:0] AXI_07_AWLEN; + input [2:0] AXI_07_AWSIZE; + input AXI_07_AWVALID; + input AXI_07_BREADY; + input AXI_07_DFI_LP_PWR_X_REQ; + input AXI_07_RREADY; + input [255:0] AXI_07_WDATA; + input [31:0] AXI_07_WDATA_PARITY; + input AXI_07_WLAST; + input [31:0] AXI_07_WSTRB; + input AXI_07_WVALID; + (* invertible_pin = "IS_AXI_08_ACLK_INVERTED" *) + input AXI_08_ACLK; + input [36:0] AXI_08_ARADDR; + input [1:0] AXI_08_ARBURST; + (* invertible_pin = "IS_AXI_08_ARESET_N_INVERTED" *) + input AXI_08_ARESET_N; + input [5:0] AXI_08_ARID; + input [3:0] AXI_08_ARLEN; + input [2:0] AXI_08_ARSIZE; + input AXI_08_ARVALID; + input [36:0] AXI_08_AWADDR; + input [1:0] AXI_08_AWBURST; + input [5:0] AXI_08_AWID; + input [3:0] AXI_08_AWLEN; + input [2:0] AXI_08_AWSIZE; + input AXI_08_AWVALID; + input AXI_08_BREADY; + input AXI_08_DFI_LP_PWR_X_REQ; + input AXI_08_RREADY; + input [255:0] AXI_08_WDATA; + input [31:0] AXI_08_WDATA_PARITY; + input AXI_08_WLAST; + input [31:0] AXI_08_WSTRB; + input AXI_08_WVALID; + (* invertible_pin = "IS_AXI_09_ACLK_INVERTED" *) + input AXI_09_ACLK; + input [36:0] AXI_09_ARADDR; + input [1:0] AXI_09_ARBURST; + (* invertible_pin = "IS_AXI_09_ARESET_N_INVERTED" *) + input AXI_09_ARESET_N; + input [5:0] AXI_09_ARID; + input [3:0] AXI_09_ARLEN; + input [2:0] AXI_09_ARSIZE; + input AXI_09_ARVALID; + input [36:0] AXI_09_AWADDR; + input [1:0] AXI_09_AWBURST; + input [5:0] AXI_09_AWID; + input [3:0] AXI_09_AWLEN; + input [2:0] AXI_09_AWSIZE; + input AXI_09_AWVALID; + input AXI_09_BREADY; + input AXI_09_DFI_LP_PWR_X_REQ; + input AXI_09_RREADY; + input [255:0] AXI_09_WDATA; + input [31:0] AXI_09_WDATA_PARITY; + input AXI_09_WLAST; + input [31:0] AXI_09_WSTRB; + input AXI_09_WVALID; + (* invertible_pin = "IS_AXI_10_ACLK_INVERTED" *) + input AXI_10_ACLK; + input [36:0] AXI_10_ARADDR; + input [1:0] AXI_10_ARBURST; + (* invertible_pin = "IS_AXI_10_ARESET_N_INVERTED" *) + input AXI_10_ARESET_N; + input [5:0] AXI_10_ARID; + input [3:0] AXI_10_ARLEN; + input [2:0] AXI_10_ARSIZE; + input AXI_10_ARVALID; + input [36:0] AXI_10_AWADDR; + input [1:0] AXI_10_AWBURST; + input [5:0] AXI_10_AWID; + input [3:0] AXI_10_AWLEN; + input [2:0] AXI_10_AWSIZE; + input AXI_10_AWVALID; + input AXI_10_BREADY; + input AXI_10_DFI_LP_PWR_X_REQ; + input AXI_10_RREADY; + input [255:0] AXI_10_WDATA; + input [31:0] AXI_10_WDATA_PARITY; + input AXI_10_WLAST; + input [31:0] AXI_10_WSTRB; + input AXI_10_WVALID; + (* invertible_pin = "IS_AXI_11_ACLK_INVERTED" *) + input AXI_11_ACLK; + input [36:0] AXI_11_ARADDR; + input [1:0] AXI_11_ARBURST; + (* invertible_pin = "IS_AXI_11_ARESET_N_INVERTED" *) + input AXI_11_ARESET_N; + input [5:0] AXI_11_ARID; + input [3:0] AXI_11_ARLEN; + input [2:0] AXI_11_ARSIZE; + input AXI_11_ARVALID; + input [36:0] AXI_11_AWADDR; + input [1:0] AXI_11_AWBURST; + input [5:0] AXI_11_AWID; + input [3:0] AXI_11_AWLEN; + input [2:0] AXI_11_AWSIZE; + input AXI_11_AWVALID; + input AXI_11_BREADY; + input AXI_11_DFI_LP_PWR_X_REQ; + input AXI_11_RREADY; + input [255:0] AXI_11_WDATA; + input [31:0] AXI_11_WDATA_PARITY; + input AXI_11_WLAST; + input [31:0] AXI_11_WSTRB; + input AXI_11_WVALID; + (* invertible_pin = "IS_AXI_12_ACLK_INVERTED" *) + input AXI_12_ACLK; + input [36:0] AXI_12_ARADDR; + input [1:0] AXI_12_ARBURST; + (* invertible_pin = "IS_AXI_12_ARESET_N_INVERTED" *) + input AXI_12_ARESET_N; + input [5:0] AXI_12_ARID; + input [3:0] AXI_12_ARLEN; + input [2:0] AXI_12_ARSIZE; + input AXI_12_ARVALID; + input [36:0] AXI_12_AWADDR; + input [1:0] AXI_12_AWBURST; + input [5:0] AXI_12_AWID; + input [3:0] AXI_12_AWLEN; + input [2:0] AXI_12_AWSIZE; + input AXI_12_AWVALID; + input AXI_12_BREADY; + input AXI_12_DFI_LP_PWR_X_REQ; + input AXI_12_RREADY; + input [255:0] AXI_12_WDATA; + input [31:0] AXI_12_WDATA_PARITY; + input AXI_12_WLAST; + input [31:0] AXI_12_WSTRB; + input AXI_12_WVALID; + (* invertible_pin = "IS_AXI_13_ACLK_INVERTED" *) + input AXI_13_ACLK; + input [36:0] AXI_13_ARADDR; + input [1:0] AXI_13_ARBURST; + (* invertible_pin = "IS_AXI_13_ARESET_N_INVERTED" *) + input AXI_13_ARESET_N; + input [5:0] AXI_13_ARID; + input [3:0] AXI_13_ARLEN; + input [2:0] AXI_13_ARSIZE; + input AXI_13_ARVALID; + input [36:0] AXI_13_AWADDR; + input [1:0] AXI_13_AWBURST; + input [5:0] AXI_13_AWID; + input [3:0] AXI_13_AWLEN; + input [2:0] AXI_13_AWSIZE; + input AXI_13_AWVALID; + input AXI_13_BREADY; + input AXI_13_DFI_LP_PWR_X_REQ; + input AXI_13_RREADY; + input [255:0] AXI_13_WDATA; + input [31:0] AXI_13_WDATA_PARITY; + input AXI_13_WLAST; + input [31:0] AXI_13_WSTRB; + input AXI_13_WVALID; + (* invertible_pin = "IS_AXI_14_ACLK_INVERTED" *) + input AXI_14_ACLK; + input [36:0] AXI_14_ARADDR; + input [1:0] AXI_14_ARBURST; + (* invertible_pin = "IS_AXI_14_ARESET_N_INVERTED" *) + input AXI_14_ARESET_N; + input [5:0] AXI_14_ARID; + input [3:0] AXI_14_ARLEN; + input [2:0] AXI_14_ARSIZE; + input AXI_14_ARVALID; + input [36:0] AXI_14_AWADDR; + input [1:0] AXI_14_AWBURST; + input [5:0] AXI_14_AWID; + input [3:0] AXI_14_AWLEN; + input [2:0] AXI_14_AWSIZE; + input AXI_14_AWVALID; + input AXI_14_BREADY; + input AXI_14_DFI_LP_PWR_X_REQ; + input AXI_14_RREADY; + input [255:0] AXI_14_WDATA; + input [31:0] AXI_14_WDATA_PARITY; + input AXI_14_WLAST; + input [31:0] AXI_14_WSTRB; + input AXI_14_WVALID; + (* invertible_pin = "IS_AXI_15_ACLK_INVERTED" *) + input AXI_15_ACLK; + input [36:0] AXI_15_ARADDR; + input [1:0] AXI_15_ARBURST; + (* invertible_pin = "IS_AXI_15_ARESET_N_INVERTED" *) + input AXI_15_ARESET_N; + input [5:0] AXI_15_ARID; + input [3:0] AXI_15_ARLEN; + input [2:0] AXI_15_ARSIZE; + input AXI_15_ARVALID; + input [36:0] AXI_15_AWADDR; + input [1:0] AXI_15_AWBURST; + input [5:0] AXI_15_AWID; + input [3:0] AXI_15_AWLEN; + input [2:0] AXI_15_AWSIZE; + input AXI_15_AWVALID; + input AXI_15_BREADY; + input AXI_15_DFI_LP_PWR_X_REQ; + input AXI_15_RREADY; + input [255:0] AXI_15_WDATA; + input [31:0] AXI_15_WDATA_PARITY; + input AXI_15_WLAST; + input [31:0] AXI_15_WSTRB; + input AXI_15_WVALID; + (* invertible_pin = "IS_AXI_16_ACLK_INVERTED" *) + input AXI_16_ACLK; + input [36:0] AXI_16_ARADDR; + input [1:0] AXI_16_ARBURST; + (* invertible_pin = "IS_AXI_16_ARESET_N_INVERTED" *) + input AXI_16_ARESET_N; + input [5:0] AXI_16_ARID; + input [3:0] AXI_16_ARLEN; + input [2:0] AXI_16_ARSIZE; + input AXI_16_ARVALID; + input [36:0] AXI_16_AWADDR; + input [1:0] AXI_16_AWBURST; + input [5:0] AXI_16_AWID; + input [3:0] AXI_16_AWLEN; + input [2:0] AXI_16_AWSIZE; + input AXI_16_AWVALID; + input AXI_16_BREADY; + input AXI_16_DFI_LP_PWR_X_REQ; + input AXI_16_RREADY; + input [255:0] AXI_16_WDATA; + input [31:0] AXI_16_WDATA_PARITY; + input AXI_16_WLAST; + input [31:0] AXI_16_WSTRB; + input AXI_16_WVALID; + (* invertible_pin = "IS_AXI_17_ACLK_INVERTED" *) + input AXI_17_ACLK; + input [36:0] AXI_17_ARADDR; + input [1:0] AXI_17_ARBURST; + (* invertible_pin = "IS_AXI_17_ARESET_N_INVERTED" *) + input AXI_17_ARESET_N; + input [5:0] AXI_17_ARID; + input [3:0] AXI_17_ARLEN; + input [2:0] AXI_17_ARSIZE; + input AXI_17_ARVALID; + input [36:0] AXI_17_AWADDR; + input [1:0] AXI_17_AWBURST; + input [5:0] AXI_17_AWID; + input [3:0] AXI_17_AWLEN; + input [2:0] AXI_17_AWSIZE; + input AXI_17_AWVALID; + input AXI_17_BREADY; + input AXI_17_DFI_LP_PWR_X_REQ; + input AXI_17_RREADY; + input [255:0] AXI_17_WDATA; + input [31:0] AXI_17_WDATA_PARITY; + input AXI_17_WLAST; + input [31:0] AXI_17_WSTRB; + input AXI_17_WVALID; + (* invertible_pin = "IS_AXI_18_ACLK_INVERTED" *) + input AXI_18_ACLK; + input [36:0] AXI_18_ARADDR; + input [1:0] AXI_18_ARBURST; + (* invertible_pin = "IS_AXI_18_ARESET_N_INVERTED" *) + input AXI_18_ARESET_N; + input [5:0] AXI_18_ARID; + input [3:0] AXI_18_ARLEN; + input [2:0] AXI_18_ARSIZE; + input AXI_18_ARVALID; + input [36:0] AXI_18_AWADDR; + input [1:0] AXI_18_AWBURST; + input [5:0] AXI_18_AWID; + input [3:0] AXI_18_AWLEN; + input [2:0] AXI_18_AWSIZE; + input AXI_18_AWVALID; + input AXI_18_BREADY; + input AXI_18_DFI_LP_PWR_X_REQ; + input AXI_18_RREADY; + input [255:0] AXI_18_WDATA; + input [31:0] AXI_18_WDATA_PARITY; + input AXI_18_WLAST; + input [31:0] AXI_18_WSTRB; + input AXI_18_WVALID; + (* invertible_pin = "IS_AXI_19_ACLK_INVERTED" *) + input AXI_19_ACLK; + input [36:0] AXI_19_ARADDR; + input [1:0] AXI_19_ARBURST; + (* invertible_pin = "IS_AXI_19_ARESET_N_INVERTED" *) + input AXI_19_ARESET_N; + input [5:0] AXI_19_ARID; + input [3:0] AXI_19_ARLEN; + input [2:0] AXI_19_ARSIZE; + input AXI_19_ARVALID; + input [36:0] AXI_19_AWADDR; + input [1:0] AXI_19_AWBURST; + input [5:0] AXI_19_AWID; + input [3:0] AXI_19_AWLEN; + input [2:0] AXI_19_AWSIZE; + input AXI_19_AWVALID; + input AXI_19_BREADY; + input AXI_19_DFI_LP_PWR_X_REQ; + input AXI_19_RREADY; + input [255:0] AXI_19_WDATA; + input [31:0] AXI_19_WDATA_PARITY; + input AXI_19_WLAST; + input [31:0] AXI_19_WSTRB; + input AXI_19_WVALID; + (* invertible_pin = "IS_AXI_20_ACLK_INVERTED" *) + input AXI_20_ACLK; + input [36:0] AXI_20_ARADDR; + input [1:0] AXI_20_ARBURST; + (* invertible_pin = "IS_AXI_20_ARESET_N_INVERTED" *) + input AXI_20_ARESET_N; + input [5:0] AXI_20_ARID; + input [3:0] AXI_20_ARLEN; + input [2:0] AXI_20_ARSIZE; + input AXI_20_ARVALID; + input [36:0] AXI_20_AWADDR; + input [1:0] AXI_20_AWBURST; + input [5:0] AXI_20_AWID; + input [3:0] AXI_20_AWLEN; + input [2:0] AXI_20_AWSIZE; + input AXI_20_AWVALID; + input AXI_20_BREADY; + input AXI_20_DFI_LP_PWR_X_REQ; + input AXI_20_RREADY; + input [255:0] AXI_20_WDATA; + input [31:0] AXI_20_WDATA_PARITY; + input AXI_20_WLAST; + input [31:0] AXI_20_WSTRB; + input AXI_20_WVALID; + (* invertible_pin = "IS_AXI_21_ACLK_INVERTED" *) + input AXI_21_ACLK; + input [36:0] AXI_21_ARADDR; + input [1:0] AXI_21_ARBURST; + (* invertible_pin = "IS_AXI_21_ARESET_N_INVERTED" *) + input AXI_21_ARESET_N; + input [5:0] AXI_21_ARID; + input [3:0] AXI_21_ARLEN; + input [2:0] AXI_21_ARSIZE; + input AXI_21_ARVALID; + input [36:0] AXI_21_AWADDR; + input [1:0] AXI_21_AWBURST; + input [5:0] AXI_21_AWID; + input [3:0] AXI_21_AWLEN; + input [2:0] AXI_21_AWSIZE; + input AXI_21_AWVALID; + input AXI_21_BREADY; + input AXI_21_DFI_LP_PWR_X_REQ; + input AXI_21_RREADY; + input [255:0] AXI_21_WDATA; + input [31:0] AXI_21_WDATA_PARITY; + input AXI_21_WLAST; + input [31:0] AXI_21_WSTRB; + input AXI_21_WVALID; + (* invertible_pin = "IS_AXI_22_ACLK_INVERTED" *) + input AXI_22_ACLK; + input [36:0] AXI_22_ARADDR; + input [1:0] AXI_22_ARBURST; + (* invertible_pin = "IS_AXI_22_ARESET_N_INVERTED" *) + input AXI_22_ARESET_N; + input [5:0] AXI_22_ARID; + input [3:0] AXI_22_ARLEN; + input [2:0] AXI_22_ARSIZE; + input AXI_22_ARVALID; + input [36:0] AXI_22_AWADDR; + input [1:0] AXI_22_AWBURST; + input [5:0] AXI_22_AWID; + input [3:0] AXI_22_AWLEN; + input [2:0] AXI_22_AWSIZE; + input AXI_22_AWVALID; + input AXI_22_BREADY; + input AXI_22_DFI_LP_PWR_X_REQ; + input AXI_22_RREADY; + input [255:0] AXI_22_WDATA; + input [31:0] AXI_22_WDATA_PARITY; + input AXI_22_WLAST; + input [31:0] AXI_22_WSTRB; + input AXI_22_WVALID; + (* invertible_pin = "IS_AXI_23_ACLK_INVERTED" *) + input AXI_23_ACLK; + input [36:0] AXI_23_ARADDR; + input [1:0] AXI_23_ARBURST; + (* invertible_pin = "IS_AXI_23_ARESET_N_INVERTED" *) + input AXI_23_ARESET_N; + input [5:0] AXI_23_ARID; + input [3:0] AXI_23_ARLEN; + input [2:0] AXI_23_ARSIZE; + input AXI_23_ARVALID; + input [36:0] AXI_23_AWADDR; + input [1:0] AXI_23_AWBURST; + input [5:0] AXI_23_AWID; + input [3:0] AXI_23_AWLEN; + input [2:0] AXI_23_AWSIZE; + input AXI_23_AWVALID; + input AXI_23_BREADY; + input AXI_23_DFI_LP_PWR_X_REQ; + input AXI_23_RREADY; + input [255:0] AXI_23_WDATA; + input [31:0] AXI_23_WDATA_PARITY; + input AXI_23_WLAST; + input [31:0] AXI_23_WSTRB; + input AXI_23_WVALID; + (* invertible_pin = "IS_AXI_24_ACLK_INVERTED" *) + input AXI_24_ACLK; + input [36:0] AXI_24_ARADDR; + input [1:0] AXI_24_ARBURST; + (* invertible_pin = "IS_AXI_24_ARESET_N_INVERTED" *) + input AXI_24_ARESET_N; + input [5:0] AXI_24_ARID; + input [3:0] AXI_24_ARLEN; + input [2:0] AXI_24_ARSIZE; + input AXI_24_ARVALID; + input [36:0] AXI_24_AWADDR; + input [1:0] AXI_24_AWBURST; + input [5:0] AXI_24_AWID; + input [3:0] AXI_24_AWLEN; + input [2:0] AXI_24_AWSIZE; + input AXI_24_AWVALID; + input AXI_24_BREADY; + input AXI_24_DFI_LP_PWR_X_REQ; + input AXI_24_RREADY; + input [255:0] AXI_24_WDATA; + input [31:0] AXI_24_WDATA_PARITY; + input AXI_24_WLAST; + input [31:0] AXI_24_WSTRB; + input AXI_24_WVALID; + (* invertible_pin = "IS_AXI_25_ACLK_INVERTED" *) + input AXI_25_ACLK; + input [36:0] AXI_25_ARADDR; + input [1:0] AXI_25_ARBURST; + (* invertible_pin = "IS_AXI_25_ARESET_N_INVERTED" *) + input AXI_25_ARESET_N; + input [5:0] AXI_25_ARID; + input [3:0] AXI_25_ARLEN; + input [2:0] AXI_25_ARSIZE; + input AXI_25_ARVALID; + input [36:0] AXI_25_AWADDR; + input [1:0] AXI_25_AWBURST; + input [5:0] AXI_25_AWID; + input [3:0] AXI_25_AWLEN; + input [2:0] AXI_25_AWSIZE; + input AXI_25_AWVALID; + input AXI_25_BREADY; + input AXI_25_DFI_LP_PWR_X_REQ; + input AXI_25_RREADY; + input [255:0] AXI_25_WDATA; + input [31:0] AXI_25_WDATA_PARITY; + input AXI_25_WLAST; + input [31:0] AXI_25_WSTRB; + input AXI_25_WVALID; + (* invertible_pin = "IS_AXI_26_ACLK_INVERTED" *) + input AXI_26_ACLK; + input [36:0] AXI_26_ARADDR; + input [1:0] AXI_26_ARBURST; + (* invertible_pin = "IS_AXI_26_ARESET_N_INVERTED" *) + input AXI_26_ARESET_N; + input [5:0] AXI_26_ARID; + input [3:0] AXI_26_ARLEN; + input [2:0] AXI_26_ARSIZE; + input AXI_26_ARVALID; + input [36:0] AXI_26_AWADDR; + input [1:0] AXI_26_AWBURST; + input [5:0] AXI_26_AWID; + input [3:0] AXI_26_AWLEN; + input [2:0] AXI_26_AWSIZE; + input AXI_26_AWVALID; + input AXI_26_BREADY; + input AXI_26_DFI_LP_PWR_X_REQ; + input AXI_26_RREADY; + input [255:0] AXI_26_WDATA; + input [31:0] AXI_26_WDATA_PARITY; + input AXI_26_WLAST; + input [31:0] AXI_26_WSTRB; + input AXI_26_WVALID; + (* invertible_pin = "IS_AXI_27_ACLK_INVERTED" *) + input AXI_27_ACLK; + input [36:0] AXI_27_ARADDR; + input [1:0] AXI_27_ARBURST; + (* invertible_pin = "IS_AXI_27_ARESET_N_INVERTED" *) + input AXI_27_ARESET_N; + input [5:0] AXI_27_ARID; + input [3:0] AXI_27_ARLEN; + input [2:0] AXI_27_ARSIZE; + input AXI_27_ARVALID; + input [36:0] AXI_27_AWADDR; + input [1:0] AXI_27_AWBURST; + input [5:0] AXI_27_AWID; + input [3:0] AXI_27_AWLEN; + input [2:0] AXI_27_AWSIZE; + input AXI_27_AWVALID; + input AXI_27_BREADY; + input AXI_27_DFI_LP_PWR_X_REQ; + input AXI_27_RREADY; + input [255:0] AXI_27_WDATA; + input [31:0] AXI_27_WDATA_PARITY; + input AXI_27_WLAST; + input [31:0] AXI_27_WSTRB; + input AXI_27_WVALID; + (* invertible_pin = "IS_AXI_28_ACLK_INVERTED" *) + input AXI_28_ACLK; + input [36:0] AXI_28_ARADDR; + input [1:0] AXI_28_ARBURST; + (* invertible_pin = "IS_AXI_28_ARESET_N_INVERTED" *) + input AXI_28_ARESET_N; + input [5:0] AXI_28_ARID; + input [3:0] AXI_28_ARLEN; + input [2:0] AXI_28_ARSIZE; + input AXI_28_ARVALID; + input [36:0] AXI_28_AWADDR; + input [1:0] AXI_28_AWBURST; + input [5:0] AXI_28_AWID; + input [3:0] AXI_28_AWLEN; + input [2:0] AXI_28_AWSIZE; + input AXI_28_AWVALID; + input AXI_28_BREADY; + input AXI_28_DFI_LP_PWR_X_REQ; + input AXI_28_RREADY; + input [255:0] AXI_28_WDATA; + input [31:0] AXI_28_WDATA_PARITY; + input AXI_28_WLAST; + input [31:0] AXI_28_WSTRB; + input AXI_28_WVALID; + (* invertible_pin = "IS_AXI_29_ACLK_INVERTED" *) + input AXI_29_ACLK; + input [36:0] AXI_29_ARADDR; + input [1:0] AXI_29_ARBURST; + (* invertible_pin = "IS_AXI_29_ARESET_N_INVERTED" *) + input AXI_29_ARESET_N; + input [5:0] AXI_29_ARID; + input [3:0] AXI_29_ARLEN; + input [2:0] AXI_29_ARSIZE; + input AXI_29_ARVALID; + input [36:0] AXI_29_AWADDR; + input [1:0] AXI_29_AWBURST; + input [5:0] AXI_29_AWID; + input [3:0] AXI_29_AWLEN; + input [2:0] AXI_29_AWSIZE; + input AXI_29_AWVALID; + input AXI_29_BREADY; + input AXI_29_DFI_LP_PWR_X_REQ; + input AXI_29_RREADY; + input [255:0] AXI_29_WDATA; + input [31:0] AXI_29_WDATA_PARITY; + input AXI_29_WLAST; + input [31:0] AXI_29_WSTRB; + input AXI_29_WVALID; + (* invertible_pin = "IS_AXI_30_ACLK_INVERTED" *) + input AXI_30_ACLK; + input [36:0] AXI_30_ARADDR; + input [1:0] AXI_30_ARBURST; + (* invertible_pin = "IS_AXI_30_ARESET_N_INVERTED" *) + input AXI_30_ARESET_N; + input [5:0] AXI_30_ARID; + input [3:0] AXI_30_ARLEN; + input [2:0] AXI_30_ARSIZE; + input AXI_30_ARVALID; + input [36:0] AXI_30_AWADDR; + input [1:0] AXI_30_AWBURST; + input [5:0] AXI_30_AWID; + input [3:0] AXI_30_AWLEN; + input [2:0] AXI_30_AWSIZE; + input AXI_30_AWVALID; + input AXI_30_BREADY; + input AXI_30_DFI_LP_PWR_X_REQ; + input AXI_30_RREADY; + input [255:0] AXI_30_WDATA; + input [31:0] AXI_30_WDATA_PARITY; + input AXI_30_WLAST; + input [31:0] AXI_30_WSTRB; + input AXI_30_WVALID; + (* invertible_pin = "IS_AXI_31_ACLK_INVERTED" *) + input AXI_31_ACLK; + input [36:0] AXI_31_ARADDR; + input [1:0] AXI_31_ARBURST; + (* invertible_pin = "IS_AXI_31_ARESET_N_INVERTED" *) + input AXI_31_ARESET_N; + input [5:0] AXI_31_ARID; + input [3:0] AXI_31_ARLEN; + input [2:0] AXI_31_ARSIZE; + input AXI_31_ARVALID; + input [36:0] AXI_31_AWADDR; + input [1:0] AXI_31_AWBURST; + input [5:0] AXI_31_AWID; + input [3:0] AXI_31_AWLEN; + input [2:0] AXI_31_AWSIZE; + input AXI_31_AWVALID; + input AXI_31_BREADY; + input AXI_31_DFI_LP_PWR_X_REQ; + input AXI_31_RREADY; + input [255:0] AXI_31_WDATA; + input [31:0] AXI_31_WDATA_PARITY; + input AXI_31_WLAST; + input [31:0] AXI_31_WSTRB; + input AXI_31_WVALID; + input BSCAN_DRCK_0; + input BSCAN_DRCK_1; + input BSCAN_TCK_0; + input BSCAN_TCK_1; + input HBM_REF_CLK_0; + input HBM_REF_CLK_1; + input MBIST_EN_00; + input MBIST_EN_01; + input MBIST_EN_02; + input MBIST_EN_03; + input MBIST_EN_04; + input MBIST_EN_05; + input MBIST_EN_06; + input MBIST_EN_07; + input MBIST_EN_08; + input MBIST_EN_09; + input MBIST_EN_10; + input MBIST_EN_11; + input MBIST_EN_12; + input MBIST_EN_13; + input MBIST_EN_14; + input MBIST_EN_15; +endmodule + +module PPC405_ADV (...); + parameter in_delay=100; + parameter out_delay=100; + output APUFCMDECODED; + output APUFCMDECUDIVALID; + output APUFCMENDIAN; + output APUFCMFLUSH; + output APUFCMINSTRVALID; + output APUFCMLOADDVALID; + output APUFCMOPERANDVALID; + output APUFCMWRITEBACKOK; + output APUFCMXERCA; + output C405CPMCORESLEEPREQ; + output C405CPMMSRCE; + output C405CPMMSREE; + output C405CPMTIMERIRQ; + output C405CPMTIMERRESETREQ; + output C405DBGLOADDATAONAPUDBUS; + output C405DBGMSRWE; + output C405DBGSTOPACK; + output C405DBGWBCOMPLETE; + output C405DBGWBFULL; + output C405JTGCAPTUREDR; + output C405JTGEXTEST; + output C405JTGPGMOUT; + output C405JTGSHIFTDR; + output C405JTGTDO; + output C405JTGTDOEN; + output C405JTGUPDATEDR; + output C405PLBDCUABORT; + output C405PLBDCUCACHEABLE; + output C405PLBDCUGUARDED; + output C405PLBDCUREQUEST; + output C405PLBDCURNW; + output C405PLBDCUSIZE2; + output C405PLBDCUU0ATTR; + output C405PLBDCUWRITETHRU; + output C405PLBICUABORT; + output C405PLBICUCACHEABLE; + output C405PLBICUREQUEST; + output C405PLBICUU0ATTR; + output C405RSTCHIPRESETREQ; + output C405RSTCORERESETREQ; + output C405RSTSYSRESETREQ; + output C405TRCCYCLE; + output C405TRCTRIGGEREVENTOUT; + output C405XXXMACHINECHECK; + output DCREMACCLK; + output DCREMACENABLER; + output DCREMACREAD; + output DCREMACWRITE; + output DSOCMBRAMEN; + output DSOCMBUSY; + output DSOCMRDADDRVALID; + output DSOCMWRADDRVALID; + output EXTDCRREAD; + output EXTDCRWRITE; + output ISOCMBRAMEN; + output ISOCMBRAMEVENWRITEEN; + output ISOCMBRAMODDWRITEEN; + output ISOCMDCRBRAMEVENEN; + output ISOCMDCRBRAMODDEN; + output ISOCMDCRBRAMRDSELECT; + output [0:10] C405TRCTRIGGEREVENTTYPE; + output [0:1] C405PLBDCUPRIORITY; + output [0:1] C405PLBICUPRIORITY; + output [0:1] C405TRCEVENEXECUTIONSTATUS; + output [0:1] C405TRCODDEXECUTIONSTATUS; + output [0:29] C405DBGWBIAR; + output [0:29] C405PLBICUABUS; + output [0:2] APUFCMDECUDI; + output [0:31] APUFCMINSTRUCTION; + output [0:31] APUFCMLOADDATA; + output [0:31] APUFCMRADATA; + output [0:31] APUFCMRBDATA; + output [0:31] C405PLBDCUABUS; + output [0:31] DCREMACDBUS; + output [0:31] DSOCMBRAMWRDBUS; + output [0:31] EXTDCRDBUSOUT; + output [0:31] ISOCMBRAMWRDBUS; + output [0:3] APUFCMLOADBYTEEN; + output [0:3] C405TRCTRACESTATUS; + output [0:3] DSOCMBRAMBYTEWRITE; + output [0:63] C405PLBDCUWRDBUS; + output [0:7] C405PLBDCUBE; + output [0:9] EXTDCRABUS; + output [2:3] C405PLBICUSIZE; + output [8:28] ISOCMBRAMRDABUS; + output [8:28] ISOCMBRAMWRABUS; + output [8:29] DSOCMBRAMABUS; + output [8:9] DCREMACABUS; + input BRAMDSOCMCLK; + input BRAMISOCMCLK; + input CPMC405CLOCK; + input CPMC405CORECLKINACTIVE; + input CPMC405CPUCLKEN; + input CPMC405JTAGCLKEN; + input CPMC405SYNCBYPASS; + input CPMC405TIMERCLKEN; + input CPMC405TIMERTICK; + input CPMDCRCLK; + input CPMFCMCLK; + input DBGC405DEBUGHALT; + input DBGC405EXTBUSHOLDACK; + input DBGC405UNCONDDEBUGEVENT; + input DSOCMRWCOMPLETE; + input EICC405CRITINPUTIRQ; + input EICC405EXTINPUTIRQ; + input EMACDCRACK; + input EXTDCRACK; + input FCMAPUDCDCREN; + input FCMAPUDCDFORCEALIGN; + input FCMAPUDCDFORCEBESTEERING; + input FCMAPUDCDFPUOP; + input FCMAPUDCDGPRWRITE; + input FCMAPUDCDLDSTBYTE; + input FCMAPUDCDLDSTDW; + input FCMAPUDCDLDSTHW; + input FCMAPUDCDLDSTQW; + input FCMAPUDCDLDSTWD; + input FCMAPUDCDLOAD; + input FCMAPUDCDPRIVOP; + input FCMAPUDCDRAEN; + input FCMAPUDCDRBEN; + input FCMAPUDCDSTORE; + input FCMAPUDCDTRAPBE; + input FCMAPUDCDTRAPLE; + input FCMAPUDCDUPDATE; + input FCMAPUDCDXERCAEN; + input FCMAPUDCDXEROVEN; + input FCMAPUDECODEBUSY; + input FCMAPUDONE; + input FCMAPUEXCEPTION; + input FCMAPUEXEBLOCKINGMCO; + input FCMAPUEXENONBLOCKINGMCO; + input FCMAPUINSTRACK; + input FCMAPULOADWAIT; + input FCMAPURESULTVALID; + input FCMAPUSLEEPNOTREADY; + input FCMAPUXERCA; + input FCMAPUXEROV; + input JTGC405BNDSCANTDO; + input JTGC405TCK; + input JTGC405TDI; + input JTGC405TMS; + input JTGC405TRSTNEG; + input MCBCPUCLKEN; + input MCBJTAGEN; + input MCBTIMEREN; + input MCPPCRST; + input PLBC405DCUADDRACK; + input PLBC405DCUBUSY; + input PLBC405DCUERR; + input PLBC405DCURDDACK; + input PLBC405DCUSSIZE1; + input PLBC405DCUWRDACK; + input PLBC405ICUADDRACK; + input PLBC405ICUBUSY; + input PLBC405ICUERR; + input PLBC405ICURDDACK; + input PLBC405ICUSSIZE1; + input PLBCLK; + input RSTC405RESETCHIP; + input RSTC405RESETCORE; + input RSTC405RESETSYS; + input TIEC405DETERMINISTICMULT; + input TIEC405DISOPERANDFWD; + input TIEC405MMUEN; + input TIEPVRBIT10; + input TIEPVRBIT11; + input TIEPVRBIT28; + input TIEPVRBIT29; + input TIEPVRBIT30; + input TIEPVRBIT31; + input TIEPVRBIT8; + input TIEPVRBIT9; + input TRCC405TRACEDISABLE; + input TRCC405TRIGGEREVENTIN; + input [0:15] TIEAPUCONTROL; + input [0:23] TIEAPUUDI1; + input [0:23] TIEAPUUDI2; + input [0:23] TIEAPUUDI3; + input [0:23] TIEAPUUDI4; + input [0:23] TIEAPUUDI5; + input [0:23] TIEAPUUDI6; + input [0:23] TIEAPUUDI7; + input [0:23] TIEAPUUDI8; + input [0:2] FCMAPUEXECRFIELD; + input [0:31] BRAMDSOCMRDDBUS; + input [0:31] BRAMISOCMDCRRDDBUS; + input [0:31] EMACDCRDBUS; + input [0:31] EXTDCRDBUSIN; + input [0:31] FCMAPURESULT; + input [0:3] FCMAPUCR; + input [0:5] TIEDCRADDR; + input [0:63] BRAMISOCMRDDBUS; + input [0:63] PLBC405DCURDDBUS; + input [0:63] PLBC405ICURDDBUS; + input [0:7] DSARCVALUE; + input [0:7] DSCNTLVALUE; + input [0:7] ISARCVALUE; + input [0:7] ISCNTLVALUE; + input [1:3] PLBC405DCURDWDADDR; + input [1:3] PLBC405ICURDWDADDR; +endmodule + +module PPC440 (...); + parameter CLOCK_DELAY = "FALSE"; + parameter DCR_AUTOLOCK_ENABLE = "TRUE"; + parameter PPCDM_ASYNCMODE = "FALSE"; + parameter PPCDS_ASYNCMODE = "FALSE"; + parameter PPCS0_WIDTH_128N64 = "TRUE"; + parameter PPCS1_WIDTH_128N64 = "TRUE"; + parameter [0:16] APU_CONTROL = 17'h02000; + parameter [0:23] APU_UDI0 = 24'h000000; + parameter [0:23] APU_UDI1 = 24'h000000; + parameter [0:23] APU_UDI10 = 24'h000000; + parameter [0:23] APU_UDI11 = 24'h000000; + parameter [0:23] APU_UDI12 = 24'h000000; + parameter [0:23] APU_UDI13 = 24'h000000; + parameter [0:23] APU_UDI14 = 24'h000000; + parameter [0:23] APU_UDI15 = 24'h000000; + parameter [0:23] APU_UDI2 = 24'h000000; + parameter [0:23] APU_UDI3 = 24'h000000; + parameter [0:23] APU_UDI4 = 24'h000000; + parameter [0:23] APU_UDI5 = 24'h000000; + parameter [0:23] APU_UDI6 = 24'h000000; + parameter [0:23] APU_UDI7 = 24'h000000; + parameter [0:23] APU_UDI8 = 24'h000000; + parameter [0:23] APU_UDI9 = 24'h000000; + parameter [0:31] DMA0_RXCHANNELCTRL = 32'h01010000; + parameter [0:31] DMA0_TXCHANNELCTRL = 32'h01010000; + parameter [0:31] DMA1_RXCHANNELCTRL = 32'h01010000; + parameter [0:31] DMA1_TXCHANNELCTRL = 32'h01010000; + parameter [0:31] DMA2_RXCHANNELCTRL = 32'h01010000; + parameter [0:31] DMA2_TXCHANNELCTRL = 32'h01010000; + parameter [0:31] DMA3_RXCHANNELCTRL = 32'h01010000; + parameter [0:31] DMA3_TXCHANNELCTRL = 32'h01010000; + parameter [0:31] INTERCONNECT_IMASK = 32'hFFFFFFFF; + parameter [0:31] INTERCONNECT_TMPL_SEL = 32'h3FFFFFFF; + parameter [0:31] MI_ARBCONFIG = 32'h00432010; + parameter [0:31] MI_BANKCONFLICT_MASK = 32'h00000000; + parameter [0:31] MI_CONTROL = 32'h0000008F; + parameter [0:31] MI_ROWCONFLICT_MASK = 32'h00000000; + parameter [0:31] PPCM_ARBCONFIG = 32'h00432010; + parameter [0:31] PPCM_CONTROL = 32'h8000019F; + parameter [0:31] PPCM_COUNTER = 32'h00000500; + parameter [0:31] PPCS0_ADDRMAP_TMPL0 = 32'hFFFFFFFF; + parameter [0:31] PPCS0_ADDRMAP_TMPL1 = 32'hFFFFFFFF; + parameter [0:31] PPCS0_ADDRMAP_TMPL2 = 32'hFFFFFFFF; + parameter [0:31] PPCS0_ADDRMAP_TMPL3 = 32'hFFFFFFFF; + parameter [0:31] PPCS0_CONTROL = 32'h8033336C; + parameter [0:31] PPCS1_ADDRMAP_TMPL0 = 32'hFFFFFFFF; + parameter [0:31] PPCS1_ADDRMAP_TMPL1 = 32'hFFFFFFFF; + parameter [0:31] PPCS1_ADDRMAP_TMPL2 = 32'hFFFFFFFF; + parameter [0:31] PPCS1_ADDRMAP_TMPL3 = 32'hFFFFFFFF; + parameter [0:31] PPCS1_CONTROL = 32'h8033336C; + parameter [0:31] XBAR_ADDRMAP_TMPL0 = 32'hFFFF0000; + parameter [0:31] XBAR_ADDRMAP_TMPL1 = 32'h00000000; + parameter [0:31] XBAR_ADDRMAP_TMPL2 = 32'h00000000; + parameter [0:31] XBAR_ADDRMAP_TMPL3 = 32'h00000000; + parameter [0:7] DMA0_CONTROL = 8'h00; + parameter [0:7] DMA1_CONTROL = 8'h00; + parameter [0:7] DMA2_CONTROL = 8'h00; + parameter [0:7] DMA3_CONTROL = 8'h00; + parameter [0:9] DMA0_RXIRQTIMER = 10'h3FF; + parameter [0:9] DMA0_TXIRQTIMER = 10'h3FF; + parameter [0:9] DMA1_RXIRQTIMER = 10'h3FF; + parameter [0:9] DMA1_TXIRQTIMER = 10'h3FF; + parameter [0:9] DMA2_RXIRQTIMER = 10'h3FF; + parameter [0:9] DMA2_TXIRQTIMER = 10'h3FF; + parameter [0:9] DMA3_RXIRQTIMER = 10'h3FF; + parameter [0:9] DMA3_TXIRQTIMER = 10'h3FF; + output APUFCMDECFPUOP; + output APUFCMDECLOAD; + output APUFCMDECNONAUTON; + output APUFCMDECSTORE; + output APUFCMDECUDIVALID; + output APUFCMENDIAN; + output APUFCMFLUSH; + output APUFCMINSTRVALID; + output APUFCMLOADDVALID; + output APUFCMMSRFE0; + output APUFCMMSRFE1; + output APUFCMNEXTINSTRREADY; + output APUFCMOPERANDVALID; + output APUFCMWRITEBACKOK; + output C440CPMCORESLEEPREQ; + output C440CPMDECIRPTREQ; + output C440CPMFITIRPTREQ; + output C440CPMMSRCE; + output C440CPMMSREE; + output C440CPMTIMERRESETREQ; + output C440CPMWDIRPTREQ; + output C440JTGTDO; + output C440JTGTDOEN; + output C440MACHINECHECK; + output C440RSTCHIPRESETREQ; + output C440RSTCORERESETREQ; + output C440RSTSYSTEMRESETREQ; + output C440TRCCYCLE; + output C440TRCTRIGGEREVENTOUT; + output DMA0LLRSTENGINEACK; + output DMA0LLRXDSTRDYN; + output DMA0LLTXEOFN; + output DMA0LLTXEOPN; + output DMA0LLTXSOFN; + output DMA0LLTXSOPN; + output DMA0LLTXSRCRDYN; + output DMA0RXIRQ; + output DMA0TXIRQ; + output DMA1LLRSTENGINEACK; + output DMA1LLRXDSTRDYN; + output DMA1LLTXEOFN; + output DMA1LLTXEOPN; + output DMA1LLTXSOFN; + output DMA1LLTXSOPN; + output DMA1LLTXSRCRDYN; + output DMA1RXIRQ; + output DMA1TXIRQ; + output DMA2LLRSTENGINEACK; + output DMA2LLRXDSTRDYN; + output DMA2LLTXEOFN; + output DMA2LLTXEOPN; + output DMA2LLTXSOFN; + output DMA2LLTXSOPN; + output DMA2LLTXSRCRDYN; + output DMA2RXIRQ; + output DMA2TXIRQ; + output DMA3LLRSTENGINEACK; + output DMA3LLRXDSTRDYN; + output DMA3LLTXEOFN; + output DMA3LLTXEOPN; + output DMA3LLTXSOFN; + output DMA3LLTXSOPN; + output DMA3LLTXSRCRDYN; + output DMA3RXIRQ; + output DMA3TXIRQ; + output MIMCADDRESSVALID; + output MIMCBANKCONFLICT; + output MIMCREADNOTWRITE; + output MIMCROWCONFLICT; + output MIMCWRITEDATAVALID; + output PPCCPMINTERCONNECTBUSY; + output PPCDMDCRREAD; + output PPCDMDCRWRITE; + output PPCDSDCRACK; + output PPCDSDCRTIMEOUTWAIT; + output PPCEICINTERCONNECTIRQ; + output PPCMPLBABORT; + output PPCMPLBBUSLOCK; + output PPCMPLBLOCKERR; + output PPCMPLBRDBURST; + output PPCMPLBREQUEST; + output PPCMPLBRNW; + output PPCMPLBWRBURST; + output PPCS0PLBADDRACK; + output PPCS0PLBRDBTERM; + output PPCS0PLBRDCOMP; + output PPCS0PLBRDDACK; + output PPCS0PLBREARBITRATE; + output PPCS0PLBWAIT; + output PPCS0PLBWRBTERM; + output PPCS0PLBWRCOMP; + output PPCS0PLBWRDACK; + output PPCS1PLBADDRACK; + output PPCS1PLBRDBTERM; + output PPCS1PLBRDCOMP; + output PPCS1PLBRDDACK; + output PPCS1PLBREARBITRATE; + output PPCS1PLBWAIT; + output PPCS1PLBWRBTERM; + output PPCS1PLBWRCOMP; + output PPCS1PLBWRDACK; + output [0:127] APUFCMLOADDATA; + output [0:127] MIMCWRITEDATA; + output [0:127] PPCMPLBWRDBUS; + output [0:127] PPCS0PLBRDDBUS; + output [0:127] PPCS1PLBRDDBUS; + output [0:13] C440TRCTRIGGEREVENTTYPE; + output [0:15] MIMCBYTEENABLE; + output [0:15] PPCMPLBBE; + output [0:15] PPCMPLBTATTRIBUTE; + output [0:1] PPCMPLBPRIORITY; + output [0:1] PPCS0PLBSSIZE; + output [0:1] PPCS1PLBSSIZE; + output [0:2] APUFCMDECLDSTXFERSIZE; + output [0:2] C440TRCBRANCHSTATUS; + output [0:2] PPCMPLBTYPE; + output [0:31] APUFCMINSTRUCTION; + output [0:31] APUFCMRADATA; + output [0:31] APUFCMRBDATA; + output [0:31] DMA0LLTXD; + output [0:31] DMA1LLTXD; + output [0:31] DMA2LLTXD; + output [0:31] DMA3LLTXD; + output [0:31] PPCDMDCRDBUSOUT; + output [0:31] PPCDSDCRDBUSIN; + output [0:31] PPCMPLBABUS; + output [0:35] MIMCADDRESS; + output [0:3] APUFCMDECUDI; + output [0:3] APUFCMLOADBYTEADDR; + output [0:3] DMA0LLTXREM; + output [0:3] DMA1LLTXREM; + output [0:3] DMA2LLTXREM; + output [0:3] DMA3LLTXREM; + output [0:3] PPCMPLBSIZE; + output [0:3] PPCS0PLBMBUSY; + output [0:3] PPCS0PLBMIRQ; + output [0:3] PPCS0PLBMRDERR; + output [0:3] PPCS0PLBMWRERR; + output [0:3] PPCS0PLBRDWDADDR; + output [0:3] PPCS1PLBMBUSY; + output [0:3] PPCS1PLBMIRQ; + output [0:3] PPCS1PLBMRDERR; + output [0:3] PPCS1PLBMWRERR; + output [0:3] PPCS1PLBRDWDADDR; + output [0:4] C440TRCEXECUTIONSTATUS; + output [0:6] C440TRCTRACESTATUS; + output [0:7] C440DBGSYSTEMCONTROL; + output [0:9] PPCDMDCRABUS; + output [20:21] PPCDMDCRUABUS; + output [28:31] PPCMPLBUABUS; + input CPMC440CLK; + input CPMC440CLKEN; + input CPMC440CORECLOCKINACTIVE; + input CPMC440TIMERCLOCK; + input CPMDCRCLK; + input CPMDMA0LLCLK; + input CPMDMA1LLCLK; + input CPMDMA2LLCLK; + input CPMDMA3LLCLK; + input CPMFCMCLK; + input CPMINTERCONNECTCLK; + input CPMINTERCONNECTCLKEN; + input CPMINTERCONNECTCLKNTO1; + input CPMMCCLK; + input CPMPPCMPLBCLK; + input CPMPPCS0PLBCLK; + input CPMPPCS1PLBCLK; + input DBGC440DEBUGHALT; + input DBGC440UNCONDDEBUGEVENT; + input DCRPPCDMACK; + input DCRPPCDMTIMEOUTWAIT; + input DCRPPCDSREAD; + input DCRPPCDSWRITE; + input EICC440CRITIRQ; + input EICC440EXTIRQ; + input FCMAPUCONFIRMINSTR; + input FCMAPUDONE; + input FCMAPUEXCEPTION; + input FCMAPUFPSCRFEX; + input FCMAPURESULTVALID; + input FCMAPUSLEEPNOTREADY; + input JTGC440TCK; + input JTGC440TDI; + input JTGC440TMS; + input JTGC440TRSTNEG; + input LLDMA0RSTENGINEREQ; + input LLDMA0RXEOFN; + input LLDMA0RXEOPN; + input LLDMA0RXSOFN; + input LLDMA0RXSOPN; + input LLDMA0RXSRCRDYN; + input LLDMA0TXDSTRDYN; + input LLDMA1RSTENGINEREQ; + input LLDMA1RXEOFN; + input LLDMA1RXEOPN; + input LLDMA1RXSOFN; + input LLDMA1RXSOPN; + input LLDMA1RXSRCRDYN; + input LLDMA1TXDSTRDYN; + input LLDMA2RSTENGINEREQ; + input LLDMA2RXEOFN; + input LLDMA2RXEOPN; + input LLDMA2RXSOFN; + input LLDMA2RXSOPN; + input LLDMA2RXSRCRDYN; + input LLDMA2TXDSTRDYN; + input LLDMA3RSTENGINEREQ; + input LLDMA3RXEOFN; + input LLDMA3RXEOPN; + input LLDMA3RXSOFN; + input LLDMA3RXSOPN; + input LLDMA3RXSRCRDYN; + input LLDMA3TXDSTRDYN; + input MCMIADDRREADYTOACCEPT; + input MCMIREADDATAERR; + input MCMIREADDATAVALID; + input PLBPPCMADDRACK; + input PLBPPCMMBUSY; + input PLBPPCMMIRQ; + input PLBPPCMMRDERR; + input PLBPPCMMWRERR; + input PLBPPCMRDBTERM; + input PLBPPCMRDDACK; + input PLBPPCMRDPENDREQ; + input PLBPPCMREARBITRATE; + input PLBPPCMTIMEOUT; + input PLBPPCMWRBTERM; + input PLBPPCMWRDACK; + input PLBPPCMWRPENDREQ; + input PLBPPCS0ABORT; + input PLBPPCS0BUSLOCK; + input PLBPPCS0LOCKERR; + input PLBPPCS0PAVALID; + input PLBPPCS0RDBURST; + input PLBPPCS0RDPENDREQ; + input PLBPPCS0RDPRIM; + input PLBPPCS0RNW; + input PLBPPCS0SAVALID; + input PLBPPCS0WRBURST; + input PLBPPCS0WRPENDREQ; + input PLBPPCS0WRPRIM; + input PLBPPCS1ABORT; + input PLBPPCS1BUSLOCK; + input PLBPPCS1LOCKERR; + input PLBPPCS1PAVALID; + input PLBPPCS1RDBURST; + input PLBPPCS1RDPENDREQ; + input PLBPPCS1RDPRIM; + input PLBPPCS1RNW; + input PLBPPCS1SAVALID; + input PLBPPCS1WRBURST; + input PLBPPCS1WRPENDREQ; + input PLBPPCS1WRPRIM; + input RSTC440RESETCHIP; + input RSTC440RESETCORE; + input RSTC440RESETSYSTEM; + input TIEC440ENDIANRESET; + input TRCC440TRACEDISABLE; + input TRCC440TRIGGEREVENTIN; + input [0:127] FCMAPUSTOREDATA; + input [0:127] MCMIREADDATA; + input [0:127] PLBPPCMRDDBUS; + input [0:127] PLBPPCS0WRDBUS; + input [0:127] PLBPPCS1WRDBUS; + input [0:15] PLBPPCS0BE; + input [0:15] PLBPPCS0TATTRIBUTE; + input [0:15] PLBPPCS1BE; + input [0:15] PLBPPCS1TATTRIBUTE; + input [0:1] PLBPPCMRDPENDPRI; + input [0:1] PLBPPCMREQPRI; + input [0:1] PLBPPCMSSIZE; + input [0:1] PLBPPCMWRPENDPRI; + input [0:1] PLBPPCS0MASTERID; + input [0:1] PLBPPCS0MSIZE; + input [0:1] PLBPPCS0RDPENDPRI; + input [0:1] PLBPPCS0REQPRI; + input [0:1] PLBPPCS0WRPENDPRI; + input [0:1] PLBPPCS1MASTERID; + input [0:1] PLBPPCS1MSIZE; + input [0:1] PLBPPCS1RDPENDPRI; + input [0:1] PLBPPCS1REQPRI; + input [0:1] PLBPPCS1WRPENDPRI; + input [0:1] TIEC440DCURDLDCACHEPLBPRIO; + input [0:1] TIEC440DCURDNONCACHEPLBPRIO; + input [0:1] TIEC440DCURDTOUCHPLBPRIO; + input [0:1] TIEC440DCURDURGENTPLBPRIO; + input [0:1] TIEC440DCUWRFLUSHPLBPRIO; + input [0:1] TIEC440DCUWRSTOREPLBPRIO; + input [0:1] TIEC440DCUWRURGENTPLBPRIO; + input [0:1] TIEC440ICURDFETCHPLBPRIO; + input [0:1] TIEC440ICURDSPECPLBPRIO; + input [0:1] TIEC440ICURDTOUCHPLBPRIO; + input [0:1] TIEDCRBASEADDR; + input [0:2] PLBPPCS0TYPE; + input [0:2] PLBPPCS1TYPE; + input [0:31] DCRPPCDMDBUSIN; + input [0:31] DCRPPCDSDBUSOUT; + input [0:31] FCMAPURESULT; + input [0:31] LLDMA0RXD; + input [0:31] LLDMA1RXD; + input [0:31] LLDMA2RXD; + input [0:31] LLDMA3RXD; + input [0:31] PLBPPCS0ABUS; + input [0:31] PLBPPCS1ABUS; + input [0:3] FCMAPUCR; + input [0:3] LLDMA0RXREM; + input [0:3] LLDMA1RXREM; + input [0:3] LLDMA2RXREM; + input [0:3] LLDMA3RXREM; + input [0:3] PLBPPCMRDWDADDR; + input [0:3] PLBPPCS0SIZE; + input [0:3] PLBPPCS1SIZE; + input [0:3] TIEC440ERPNRESET; + input [0:3] TIEC440USERRESET; + input [0:4] DBGC440SYSTEMSTATUS; + input [0:9] DCRPPCDSABUS; + input [28:31] PLBPPCS0UABUS; + input [28:31] PLBPPCS1UABUS; + input [28:31] TIEC440PIR; + input [28:31] TIEC440PVR; +endmodule + +(* keep *) +module PS7 (...); + output DMA0DAVALID; + output DMA0DRREADY; + output DMA0RSTN; + output DMA1DAVALID; + output DMA1DRREADY; + output DMA1RSTN; + output DMA2DAVALID; + output DMA2DRREADY; + output DMA2RSTN; + output DMA3DAVALID; + output DMA3DRREADY; + output DMA3RSTN; + output EMIOCAN0PHYTX; + output EMIOCAN1PHYTX; + output EMIOENET0GMIITXEN; + output EMIOENET0GMIITXER; + output EMIOENET0MDIOMDC; + output EMIOENET0MDIOO; + output EMIOENET0MDIOTN; + output EMIOENET0PTPDELAYREQRX; + output EMIOENET0PTPDELAYREQTX; + output EMIOENET0PTPPDELAYREQRX; + output EMIOENET0PTPPDELAYREQTX; + output EMIOENET0PTPPDELAYRESPRX; + output EMIOENET0PTPPDELAYRESPTX; + output EMIOENET0PTPSYNCFRAMERX; + output EMIOENET0PTPSYNCFRAMETX; + output EMIOENET0SOFRX; + output EMIOENET0SOFTX; + output EMIOENET1GMIITXEN; + output EMIOENET1GMIITXER; + output EMIOENET1MDIOMDC; + output EMIOENET1MDIOO; + output EMIOENET1MDIOTN; + output EMIOENET1PTPDELAYREQRX; + output EMIOENET1PTPDELAYREQTX; + output EMIOENET1PTPPDELAYREQRX; + output EMIOENET1PTPPDELAYREQTX; + output EMIOENET1PTPPDELAYRESPRX; + output EMIOENET1PTPPDELAYRESPTX; + output EMIOENET1PTPSYNCFRAMERX; + output EMIOENET1PTPSYNCFRAMETX; + output EMIOENET1SOFRX; + output EMIOENET1SOFTX; + output EMIOI2C0SCLO; + output EMIOI2C0SCLTN; + output EMIOI2C0SDAO; + output EMIOI2C0SDATN; + output EMIOI2C1SCLO; + output EMIOI2C1SCLTN; + output EMIOI2C1SDAO; + output EMIOI2C1SDATN; + output EMIOPJTAGTDO; + output EMIOPJTAGTDTN; + output EMIOSDIO0BUSPOW; + output EMIOSDIO0CLK; + output EMIOSDIO0CMDO; + output EMIOSDIO0CMDTN; + output EMIOSDIO0LED; + output EMIOSDIO1BUSPOW; + output EMIOSDIO1CLK; + output EMIOSDIO1CMDO; + output EMIOSDIO1CMDTN; + output EMIOSDIO1LED; + output EMIOSPI0MO; + output EMIOSPI0MOTN; + output EMIOSPI0SCLKO; + output EMIOSPI0SCLKTN; + output EMIOSPI0SO; + output EMIOSPI0SSNTN; + output EMIOSPI0STN; + output EMIOSPI1MO; + output EMIOSPI1MOTN; + output EMIOSPI1SCLKO; + output EMIOSPI1SCLKTN; + output EMIOSPI1SO; + output EMIOSPI1SSNTN; + output EMIOSPI1STN; + output EMIOTRACECTL; + output EMIOUART0DTRN; + output EMIOUART0RTSN; + output EMIOUART0TX; + output EMIOUART1DTRN; + output EMIOUART1RTSN; + output EMIOUART1TX; + output EMIOUSB0VBUSPWRSELECT; + output EMIOUSB1VBUSPWRSELECT; + output EMIOWDTRSTO; + output EVENTEVENTO; + output MAXIGP0ARESETN; + output MAXIGP0ARVALID; + output MAXIGP0AWVALID; + output MAXIGP0BREADY; + output MAXIGP0RREADY; + output MAXIGP0WLAST; + output MAXIGP0WVALID; + output MAXIGP1ARESETN; + output MAXIGP1ARVALID; + output MAXIGP1AWVALID; + output MAXIGP1BREADY; + output MAXIGP1RREADY; + output MAXIGP1WLAST; + output MAXIGP1WVALID; + output SAXIACPARESETN; + output SAXIACPARREADY; + output SAXIACPAWREADY; + output SAXIACPBVALID; + output SAXIACPRLAST; + output SAXIACPRVALID; + output SAXIACPWREADY; + output SAXIGP0ARESETN; + output SAXIGP0ARREADY; + output SAXIGP0AWREADY; + output SAXIGP0BVALID; + output SAXIGP0RLAST; + output SAXIGP0RVALID; + output SAXIGP0WREADY; + output SAXIGP1ARESETN; + output SAXIGP1ARREADY; + output SAXIGP1AWREADY; + output SAXIGP1BVALID; + output SAXIGP1RLAST; + output SAXIGP1RVALID; + output SAXIGP1WREADY; + output SAXIHP0ARESETN; + output SAXIHP0ARREADY; + output SAXIHP0AWREADY; + output SAXIHP0BVALID; + output SAXIHP0RLAST; + output SAXIHP0RVALID; + output SAXIHP0WREADY; + output SAXIHP1ARESETN; + output SAXIHP1ARREADY; + output SAXIHP1AWREADY; + output SAXIHP1BVALID; + output SAXIHP1RLAST; + output SAXIHP1RVALID; + output SAXIHP1WREADY; + output SAXIHP2ARESETN; + output SAXIHP2ARREADY; + output SAXIHP2AWREADY; + output SAXIHP2BVALID; + output SAXIHP2RLAST; + output SAXIHP2RVALID; + output SAXIHP2WREADY; + output SAXIHP3ARESETN; + output SAXIHP3ARREADY; + output SAXIHP3AWREADY; + output SAXIHP3BVALID; + output SAXIHP3RLAST; + output SAXIHP3RVALID; + output SAXIHP3WREADY; + output [11:0] MAXIGP0ARID; + output [11:0] MAXIGP0AWID; + output [11:0] MAXIGP0WID; + output [11:0] MAXIGP1ARID; + output [11:0] MAXIGP1AWID; + output [11:0] MAXIGP1WID; + output [1:0] DMA0DATYPE; + output [1:0] DMA1DATYPE; + output [1:0] DMA2DATYPE; + output [1:0] DMA3DATYPE; + output [1:0] EMIOUSB0PORTINDCTL; + output [1:0] EMIOUSB1PORTINDCTL; + output [1:0] EVENTSTANDBYWFE; + output [1:0] EVENTSTANDBYWFI; + output [1:0] MAXIGP0ARBURST; + output [1:0] MAXIGP0ARLOCK; + output [1:0] MAXIGP0ARSIZE; + output [1:0] MAXIGP0AWBURST; + output [1:0] MAXIGP0AWLOCK; + output [1:0] MAXIGP0AWSIZE; + output [1:0] MAXIGP1ARBURST; + output [1:0] MAXIGP1ARLOCK; + output [1:0] MAXIGP1ARSIZE; + output [1:0] MAXIGP1AWBURST; + output [1:0] MAXIGP1AWLOCK; + output [1:0] MAXIGP1AWSIZE; + output [1:0] SAXIACPBRESP; + output [1:0] SAXIACPRRESP; + output [1:0] SAXIGP0BRESP; + output [1:0] SAXIGP0RRESP; + output [1:0] SAXIGP1BRESP; + output [1:0] SAXIGP1RRESP; + output [1:0] SAXIHP0BRESP; + output [1:0] SAXIHP0RRESP; + output [1:0] SAXIHP1BRESP; + output [1:0] SAXIHP1RRESP; + output [1:0] SAXIHP2BRESP; + output [1:0] SAXIHP2RRESP; + output [1:0] SAXIHP3BRESP; + output [1:0] SAXIHP3RRESP; + output [28:0] IRQP2F; + output [2:0] EMIOSDIO0BUSVOLT; + output [2:0] EMIOSDIO1BUSVOLT; + output [2:0] EMIOSPI0SSON; + output [2:0] EMIOSPI1SSON; + output [2:0] EMIOTTC0WAVEO; + output [2:0] EMIOTTC1WAVEO; + output [2:0] MAXIGP0ARPROT; + output [2:0] MAXIGP0AWPROT; + output [2:0] MAXIGP1ARPROT; + output [2:0] MAXIGP1AWPROT; + output [2:0] SAXIACPBID; + output [2:0] SAXIACPRID; + output [2:0] SAXIHP0RACOUNT; + output [2:0] SAXIHP1RACOUNT; + output [2:0] SAXIHP2RACOUNT; + output [2:0] SAXIHP3RACOUNT; + output [31:0] EMIOTRACEDATA; + output [31:0] FTMTP2FDEBUG; + output [31:0] MAXIGP0ARADDR; + output [31:0] MAXIGP0AWADDR; + output [31:0] MAXIGP0WDATA; + output [31:0] MAXIGP1ARADDR; + output [31:0] MAXIGP1AWADDR; + output [31:0] MAXIGP1WDATA; + output [31:0] SAXIGP0RDATA; + output [31:0] SAXIGP1RDATA; + output [3:0] EMIOSDIO0DATAO; + output [3:0] EMIOSDIO0DATATN; + output [3:0] EMIOSDIO1DATAO; + output [3:0] EMIOSDIO1DATATN; + output [3:0] FCLKCLK; + output [3:0] FCLKRESETN; + output [3:0] FTMTF2PTRIGACK; + output [3:0] FTMTP2FTRIG; + output [3:0] MAXIGP0ARCACHE; + output [3:0] MAXIGP0ARLEN; + output [3:0] MAXIGP0ARQOS; + output [3:0] MAXIGP0AWCACHE; + output [3:0] MAXIGP0AWLEN; + output [3:0] MAXIGP0AWQOS; + output [3:0] MAXIGP0WSTRB; + output [3:0] MAXIGP1ARCACHE; + output [3:0] MAXIGP1ARLEN; + output [3:0] MAXIGP1ARQOS; + output [3:0] MAXIGP1AWCACHE; + output [3:0] MAXIGP1AWLEN; + output [3:0] MAXIGP1AWQOS; + output [3:0] MAXIGP1WSTRB; + output [5:0] SAXIGP0BID; + output [5:0] SAXIGP0RID; + output [5:0] SAXIGP1BID; + output [5:0] SAXIGP1RID; + output [5:0] SAXIHP0BID; + output [5:0] SAXIHP0RID; + output [5:0] SAXIHP0WACOUNT; + output [5:0] SAXIHP1BID; + output [5:0] SAXIHP1RID; + output [5:0] SAXIHP1WACOUNT; + output [5:0] SAXIHP2BID; + output [5:0] SAXIHP2RID; + output [5:0] SAXIHP2WACOUNT; + output [5:0] SAXIHP3BID; + output [5:0] SAXIHP3RID; + output [5:0] SAXIHP3WACOUNT; + output [63:0] EMIOGPIOO; + output [63:0] EMIOGPIOTN; + output [63:0] SAXIACPRDATA; + output [63:0] SAXIHP0RDATA; + output [63:0] SAXIHP1RDATA; + output [63:0] SAXIHP2RDATA; + output [63:0] SAXIHP3RDATA; + output [7:0] EMIOENET0GMIITXD; + output [7:0] EMIOENET1GMIITXD; + output [7:0] SAXIHP0RCOUNT; + output [7:0] SAXIHP0WCOUNT; + output [7:0] SAXIHP1RCOUNT; + output [7:0] SAXIHP1WCOUNT; + output [7:0] SAXIHP2RCOUNT; + output [7:0] SAXIHP2WCOUNT; + output [7:0] SAXIHP3RCOUNT; + output [7:0] SAXIHP3WCOUNT; + inout DDRCASB; + inout DDRCKE; + inout DDRCKN; + inout DDRCKP; + inout DDRCSB; + inout DDRDRSTB; + inout DDRODT; + inout DDRRASB; + inout DDRVRN; + inout DDRVRP; + inout DDRWEB; + inout PSCLK; + inout PSPORB; + inout PSSRSTB; + inout [14:0] DDRA; + inout [2:0] DDRBA; + inout [31:0] DDRDQ; + inout [3:0] DDRDM; + inout [3:0] DDRDQSN; + inout [3:0] DDRDQSP; + inout [53:0] MIO; + input DMA0ACLK; + input DMA0DAREADY; + input DMA0DRLAST; + input DMA0DRVALID; + input DMA1ACLK; + input DMA1DAREADY; + input DMA1DRLAST; + input DMA1DRVALID; + input DMA2ACLK; + input DMA2DAREADY; + input DMA2DRLAST; + input DMA2DRVALID; + input DMA3ACLK; + input DMA3DAREADY; + input DMA3DRLAST; + input DMA3DRVALID; + input EMIOCAN0PHYRX; + input EMIOCAN1PHYRX; + input EMIOENET0EXTINTIN; + input EMIOENET0GMIICOL; + input EMIOENET0GMIICRS; + input EMIOENET0GMIIRXCLK; + input EMIOENET0GMIIRXDV; + input EMIOENET0GMIIRXER; + input EMIOENET0GMIITXCLK; + input EMIOENET0MDIOI; + input EMIOENET1EXTINTIN; + input EMIOENET1GMIICOL; + input EMIOENET1GMIICRS; + input EMIOENET1GMIIRXCLK; + input EMIOENET1GMIIRXDV; + input EMIOENET1GMIIRXER; + input EMIOENET1GMIITXCLK; + input EMIOENET1MDIOI; + input EMIOI2C0SCLI; + input EMIOI2C0SDAI; + input EMIOI2C1SCLI; + input EMIOI2C1SDAI; + input EMIOPJTAGTCK; + input EMIOPJTAGTDI; + input EMIOPJTAGTMS; + input EMIOSDIO0CDN; + input EMIOSDIO0CLKFB; + input EMIOSDIO0CMDI; + input EMIOSDIO0WP; + input EMIOSDIO1CDN; + input EMIOSDIO1CLKFB; + input EMIOSDIO1CMDI; + input EMIOSDIO1WP; + input EMIOSPI0MI; + input EMIOSPI0SCLKI; + input EMIOSPI0SI; + input EMIOSPI0SSIN; + input EMIOSPI1MI; + input EMIOSPI1SCLKI; + input EMIOSPI1SI; + input EMIOSPI1SSIN; + input EMIOSRAMINTIN; + input EMIOTRACECLK; + input EMIOUART0CTSN; + input EMIOUART0DCDN; + input EMIOUART0DSRN; + input EMIOUART0RIN; + input EMIOUART0RX; + input EMIOUART1CTSN; + input EMIOUART1DCDN; + input EMIOUART1DSRN; + input EMIOUART1RIN; + input EMIOUART1RX; + input EMIOUSB0VBUSPWRFAULT; + input EMIOUSB1VBUSPWRFAULT; + input EMIOWDTCLKI; + input EVENTEVENTI; + input FPGAIDLEN; + input FTMDTRACEINCLOCK; + input FTMDTRACEINVALID; + input MAXIGP0ACLK; + input MAXIGP0ARREADY; + input MAXIGP0AWREADY; + input MAXIGP0BVALID; + input MAXIGP0RLAST; + input MAXIGP0RVALID; + input MAXIGP0WREADY; + input MAXIGP1ACLK; + input MAXIGP1ARREADY; + input MAXIGP1AWREADY; + input MAXIGP1BVALID; + input MAXIGP1RLAST; + input MAXIGP1RVALID; + input MAXIGP1WREADY; + input SAXIACPACLK; + input SAXIACPARVALID; + input SAXIACPAWVALID; + input SAXIACPBREADY; + input SAXIACPRREADY; + input SAXIACPWLAST; + input SAXIACPWVALID; + input SAXIGP0ACLK; + input SAXIGP0ARVALID; + input SAXIGP0AWVALID; + input SAXIGP0BREADY; + input SAXIGP0RREADY; + input SAXIGP0WLAST; + input SAXIGP0WVALID; + input SAXIGP1ACLK; + input SAXIGP1ARVALID; + input SAXIGP1AWVALID; + input SAXIGP1BREADY; + input SAXIGP1RREADY; + input SAXIGP1WLAST; + input SAXIGP1WVALID; + input SAXIHP0ACLK; + input SAXIHP0ARVALID; + input SAXIHP0AWVALID; + input SAXIHP0BREADY; + input SAXIHP0RDISSUECAP1EN; + input SAXIHP0RREADY; + input SAXIHP0WLAST; + input SAXIHP0WRISSUECAP1EN; + input SAXIHP0WVALID; + input SAXIHP1ACLK; + input SAXIHP1ARVALID; + input SAXIHP1AWVALID; + input SAXIHP1BREADY; + input SAXIHP1RDISSUECAP1EN; + input SAXIHP1RREADY; + input SAXIHP1WLAST; + input SAXIHP1WRISSUECAP1EN; + input SAXIHP1WVALID; + input SAXIHP2ACLK; + input SAXIHP2ARVALID; + input SAXIHP2AWVALID; + input SAXIHP2BREADY; + input SAXIHP2RDISSUECAP1EN; + input SAXIHP2RREADY; + input SAXIHP2WLAST; + input SAXIHP2WRISSUECAP1EN; + input SAXIHP2WVALID; + input SAXIHP3ACLK; + input SAXIHP3ARVALID; + input SAXIHP3AWVALID; + input SAXIHP3BREADY; + input SAXIHP3RDISSUECAP1EN; + input SAXIHP3RREADY; + input SAXIHP3WLAST; + input SAXIHP3WRISSUECAP1EN; + input SAXIHP3WVALID; + input [11:0] MAXIGP0BID; + input [11:0] MAXIGP0RID; + input [11:0] MAXIGP1BID; + input [11:0] MAXIGP1RID; + input [19:0] IRQF2P; + input [1:0] DMA0DRTYPE; + input [1:0] DMA1DRTYPE; + input [1:0] DMA2DRTYPE; + input [1:0] DMA3DRTYPE; + input [1:0] MAXIGP0BRESP; + input [1:0] MAXIGP0RRESP; + input [1:0] MAXIGP1BRESP; + input [1:0] MAXIGP1RRESP; + input [1:0] SAXIACPARBURST; + input [1:0] SAXIACPARLOCK; + input [1:0] SAXIACPARSIZE; + input [1:0] SAXIACPAWBURST; + input [1:0] SAXIACPAWLOCK; + input [1:0] SAXIACPAWSIZE; + input [1:0] SAXIGP0ARBURST; + input [1:0] SAXIGP0ARLOCK; + input [1:0] SAXIGP0ARSIZE; + input [1:0] SAXIGP0AWBURST; + input [1:0] SAXIGP0AWLOCK; + input [1:0] SAXIGP0AWSIZE; + input [1:0] SAXIGP1ARBURST; + input [1:0] SAXIGP1ARLOCK; + input [1:0] SAXIGP1ARSIZE; + input [1:0] SAXIGP1AWBURST; + input [1:0] SAXIGP1AWLOCK; + input [1:0] SAXIGP1AWSIZE; + input [1:0] SAXIHP0ARBURST; + input [1:0] SAXIHP0ARLOCK; + input [1:0] SAXIHP0ARSIZE; + input [1:0] SAXIHP0AWBURST; + input [1:0] SAXIHP0AWLOCK; + input [1:0] SAXIHP0AWSIZE; + input [1:0] SAXIHP1ARBURST; + input [1:0] SAXIHP1ARLOCK; + input [1:0] SAXIHP1ARSIZE; + input [1:0] SAXIHP1AWBURST; + input [1:0] SAXIHP1AWLOCK; + input [1:0] SAXIHP1AWSIZE; + input [1:0] SAXIHP2ARBURST; + input [1:0] SAXIHP2ARLOCK; + input [1:0] SAXIHP2ARSIZE; + input [1:0] SAXIHP2AWBURST; + input [1:0] SAXIHP2AWLOCK; + input [1:0] SAXIHP2AWSIZE; + input [1:0] SAXIHP3ARBURST; + input [1:0] SAXIHP3ARLOCK; + input [1:0] SAXIHP3ARSIZE; + input [1:0] SAXIHP3AWBURST; + input [1:0] SAXIHP3AWLOCK; + input [1:0] SAXIHP3AWSIZE; + input [2:0] EMIOTTC0CLKI; + input [2:0] EMIOTTC1CLKI; + input [2:0] SAXIACPARID; + input [2:0] SAXIACPARPROT; + input [2:0] SAXIACPAWID; + input [2:0] SAXIACPAWPROT; + input [2:0] SAXIACPWID; + input [2:0] SAXIGP0ARPROT; + input [2:0] SAXIGP0AWPROT; + input [2:0] SAXIGP1ARPROT; + input [2:0] SAXIGP1AWPROT; + input [2:0] SAXIHP0ARPROT; + input [2:0] SAXIHP0AWPROT; + input [2:0] SAXIHP1ARPROT; + input [2:0] SAXIHP1AWPROT; + input [2:0] SAXIHP2ARPROT; + input [2:0] SAXIHP2AWPROT; + input [2:0] SAXIHP3ARPROT; + input [2:0] SAXIHP3AWPROT; + input [31:0] FTMDTRACEINDATA; + input [31:0] FTMTF2PDEBUG; + input [31:0] MAXIGP0RDATA; + input [31:0] MAXIGP1RDATA; + input [31:0] SAXIACPARADDR; + input [31:0] SAXIACPAWADDR; + input [31:0] SAXIGP0ARADDR; + input [31:0] SAXIGP0AWADDR; + input [31:0] SAXIGP0WDATA; + input [31:0] SAXIGP1ARADDR; + input [31:0] SAXIGP1AWADDR; + input [31:0] SAXIGP1WDATA; + input [31:0] SAXIHP0ARADDR; + input [31:0] SAXIHP0AWADDR; + input [31:0] SAXIHP1ARADDR; + input [31:0] SAXIHP1AWADDR; + input [31:0] SAXIHP2ARADDR; + input [31:0] SAXIHP2AWADDR; + input [31:0] SAXIHP3ARADDR; + input [31:0] SAXIHP3AWADDR; + input [3:0] DDRARB; + input [3:0] EMIOSDIO0DATAI; + input [3:0] EMIOSDIO1DATAI; + input [3:0] FCLKCLKTRIGN; + input [3:0] FTMDTRACEINATID; + input [3:0] FTMTF2PTRIG; + input [3:0] FTMTP2FTRIGACK; + input [3:0] SAXIACPARCACHE; + input [3:0] SAXIACPARLEN; + input [3:0] SAXIACPARQOS; + input [3:0] SAXIACPAWCACHE; + input [3:0] SAXIACPAWLEN; + input [3:0] SAXIACPAWQOS; + input [3:0] SAXIGP0ARCACHE; + input [3:0] SAXIGP0ARLEN; + input [3:0] SAXIGP0ARQOS; + input [3:0] SAXIGP0AWCACHE; + input [3:0] SAXIGP0AWLEN; + input [3:0] SAXIGP0AWQOS; + input [3:0] SAXIGP0WSTRB; + input [3:0] SAXIGP1ARCACHE; + input [3:0] SAXIGP1ARLEN; + input [3:0] SAXIGP1ARQOS; + input [3:0] SAXIGP1AWCACHE; + input [3:0] SAXIGP1AWLEN; + input [3:0] SAXIGP1AWQOS; + input [3:0] SAXIGP1WSTRB; + input [3:0] SAXIHP0ARCACHE; + input [3:0] SAXIHP0ARLEN; + input [3:0] SAXIHP0ARQOS; + input [3:0] SAXIHP0AWCACHE; + input [3:0] SAXIHP0AWLEN; + input [3:0] SAXIHP0AWQOS; + input [3:0] SAXIHP1ARCACHE; + input [3:0] SAXIHP1ARLEN; + input [3:0] SAXIHP1ARQOS; + input [3:0] SAXIHP1AWCACHE; + input [3:0] SAXIHP1AWLEN; + input [3:0] SAXIHP1AWQOS; + input [3:0] SAXIHP2ARCACHE; + input [3:0] SAXIHP2ARLEN; + input [3:0] SAXIHP2ARQOS; + input [3:0] SAXIHP2AWCACHE; + input [3:0] SAXIHP2AWLEN; + input [3:0] SAXIHP2AWQOS; + input [3:0] SAXIHP3ARCACHE; + input [3:0] SAXIHP3ARLEN; + input [3:0] SAXIHP3ARQOS; + input [3:0] SAXIHP3AWCACHE; + input [3:0] SAXIHP3AWLEN; + input [3:0] SAXIHP3AWQOS; + input [4:0] SAXIACPARUSER; + input [4:0] SAXIACPAWUSER; + input [5:0] SAXIGP0ARID; + input [5:0] SAXIGP0AWID; + input [5:0] SAXIGP0WID; + input [5:0] SAXIGP1ARID; + input [5:0] SAXIGP1AWID; + input [5:0] SAXIGP1WID; + input [5:0] SAXIHP0ARID; + input [5:0] SAXIHP0AWID; + input [5:0] SAXIHP0WID; + input [5:0] SAXIHP1ARID; + input [5:0] SAXIHP1AWID; + input [5:0] SAXIHP1WID; + input [5:0] SAXIHP2ARID; + input [5:0] SAXIHP2AWID; + input [5:0] SAXIHP2WID; + input [5:0] SAXIHP3ARID; + input [5:0] SAXIHP3AWID; + input [5:0] SAXIHP3WID; + input [63:0] EMIOGPIOI; + input [63:0] SAXIACPWDATA; + input [63:0] SAXIHP0WDATA; + input [63:0] SAXIHP1WDATA; + input [63:0] SAXIHP2WDATA; + input [63:0] SAXIHP3WDATA; + input [7:0] EMIOENET0GMIIRXD; + input [7:0] EMIOENET1GMIIRXD; + input [7:0] SAXIACPWSTRB; + input [7:0] SAXIHP0WSTRB; + input [7:0] SAXIHP1WSTRB; + input [7:0] SAXIHP2WSTRB; + input [7:0] SAXIHP3WSTRB; +endmodule + +(* keep *) +module PS8 (...); + output [7:0] ADMA2PLCACK; + output [7:0] ADMA2PLTVLD; + output DPAUDIOREFCLK; + output DPAUXDATAOEN; + output DPAUXDATAOUT; + output DPLIVEVIDEODEOUT; + output [31:0] DPMAXISMIXEDAUDIOTDATA; + output DPMAXISMIXEDAUDIOTID; + output DPMAXISMIXEDAUDIOTVALID; + output DPSAXISAUDIOTREADY; + output DPVIDEOOUTHSYNC; + output [35:0] DPVIDEOOUTPIXEL1; + output DPVIDEOOUTVSYNC; + output DPVIDEOREFCLK; + output EMIOCAN0PHYTX; + output EMIOCAN1PHYTX; + output [1:0] EMIOENET0DMABUSWIDTH; + output EMIOENET0DMATXENDTOG; + output [93:0] EMIOENET0GEMTSUTIMERCNT; + output [7:0] EMIOENET0GMIITXD; + output EMIOENET0GMIITXEN; + output EMIOENET0GMIITXER; + output EMIOENET0MDIOMDC; + output EMIOENET0MDIOO; + output EMIOENET0MDIOTN; + output [7:0] EMIOENET0RXWDATA; + output EMIOENET0RXWEOP; + output EMIOENET0RXWERR; + output EMIOENET0RXWFLUSH; + output EMIOENET0RXWSOP; + output [44:0] EMIOENET0RXWSTATUS; + output EMIOENET0RXWWR; + output [2:0] EMIOENET0SPEEDMODE; + output EMIOENET0TXRRD; + output [3:0] EMIOENET0TXRSTATUS; + output [1:0] EMIOENET1DMABUSWIDTH; + output EMIOENET1DMATXENDTOG; + output [7:0] EMIOENET1GMIITXD; + output EMIOENET1GMIITXEN; + output EMIOENET1GMIITXER; + output EMIOENET1MDIOMDC; + output EMIOENET1MDIOO; + output EMIOENET1MDIOTN; + output [7:0] EMIOENET1RXWDATA; + output EMIOENET1RXWEOP; + output EMIOENET1RXWERR; + output EMIOENET1RXWFLUSH; + output EMIOENET1RXWSOP; + output [44:0] EMIOENET1RXWSTATUS; + output EMIOENET1RXWWR; + output [2:0] EMIOENET1SPEEDMODE; + output EMIOENET1TXRRD; + output [3:0] EMIOENET1TXRSTATUS; + output [1:0] EMIOENET2DMABUSWIDTH; + output EMIOENET2DMATXENDTOG; + output [7:0] EMIOENET2GMIITXD; + output EMIOENET2GMIITXEN; + output EMIOENET2GMIITXER; + output EMIOENET2MDIOMDC; + output EMIOENET2MDIOO; + output EMIOENET2MDIOTN; + output [7:0] EMIOENET2RXWDATA; + output EMIOENET2RXWEOP; + output EMIOENET2RXWERR; + output EMIOENET2RXWFLUSH; + output EMIOENET2RXWSOP; + output [44:0] EMIOENET2RXWSTATUS; + output EMIOENET2RXWWR; + output [2:0] EMIOENET2SPEEDMODE; + output EMIOENET2TXRRD; + output [3:0] EMIOENET2TXRSTATUS; + output [1:0] EMIOENET3DMABUSWIDTH; + output EMIOENET3DMATXENDTOG; + output [7:0] EMIOENET3GMIITXD; + output EMIOENET3GMIITXEN; + output EMIOENET3GMIITXER; + output EMIOENET3MDIOMDC; + output EMIOENET3MDIOO; + output EMIOENET3MDIOTN; + output [7:0] EMIOENET3RXWDATA; + output EMIOENET3RXWEOP; + output EMIOENET3RXWERR; + output EMIOENET3RXWFLUSH; + output EMIOENET3RXWSOP; + output [44:0] EMIOENET3RXWSTATUS; + output EMIOENET3RXWWR; + output [2:0] EMIOENET3SPEEDMODE; + output EMIOENET3TXRRD; + output [3:0] EMIOENET3TXRSTATUS; + output EMIOGEM0DELAYREQRX; + output EMIOGEM0DELAYREQTX; + output EMIOGEM0PDELAYREQRX; + output EMIOGEM0PDELAYREQTX; + output EMIOGEM0PDELAYRESPRX; + output EMIOGEM0PDELAYRESPTX; + output EMIOGEM0RXSOF; + output EMIOGEM0SYNCFRAMERX; + output EMIOGEM0SYNCFRAMETX; + output EMIOGEM0TSUTIMERCMPVAL; + output EMIOGEM0TXRFIXEDLAT; + output EMIOGEM0TXSOF; + output EMIOGEM1DELAYREQRX; + output EMIOGEM1DELAYREQTX; + output EMIOGEM1PDELAYREQRX; + output EMIOGEM1PDELAYREQTX; + output EMIOGEM1PDELAYRESPRX; + output EMIOGEM1PDELAYRESPTX; + output EMIOGEM1RXSOF; + output EMIOGEM1SYNCFRAMERX; + output EMIOGEM1SYNCFRAMETX; + output EMIOGEM1TSUTIMERCMPVAL; + output EMIOGEM1TXRFIXEDLAT; + output EMIOGEM1TXSOF; + output EMIOGEM2DELAYREQRX; + output EMIOGEM2DELAYREQTX; + output EMIOGEM2PDELAYREQRX; + output EMIOGEM2PDELAYREQTX; + output EMIOGEM2PDELAYRESPRX; + output EMIOGEM2PDELAYRESPTX; + output EMIOGEM2RXSOF; + output EMIOGEM2SYNCFRAMERX; + output EMIOGEM2SYNCFRAMETX; + output EMIOGEM2TSUTIMERCMPVAL; + output EMIOGEM2TXRFIXEDLAT; + output EMIOGEM2TXSOF; + output EMIOGEM3DELAYREQRX; + output EMIOGEM3DELAYREQTX; + output EMIOGEM3PDELAYREQRX; + output EMIOGEM3PDELAYREQTX; + output EMIOGEM3PDELAYRESPRX; + output EMIOGEM3PDELAYRESPTX; + output EMIOGEM3RXSOF; + output EMIOGEM3SYNCFRAMERX; + output EMIOGEM3SYNCFRAMETX; + output EMIOGEM3TSUTIMERCMPVAL; + output EMIOGEM3TXRFIXEDLAT; + output EMIOGEM3TXSOF; + output [95:0] EMIOGPIOO; + output [95:0] EMIOGPIOTN; + output EMIOI2C0SCLO; + output EMIOI2C0SCLTN; + output EMIOI2C0SDAO; + output EMIOI2C0SDATN; + output EMIOI2C1SCLO; + output EMIOI2C1SCLTN; + output EMIOI2C1SDAO; + output EMIOI2C1SDATN; + output EMIOSDIO0BUSPOWER; + output [2:0] EMIOSDIO0BUSVOLT; + output EMIOSDIO0CLKOUT; + output EMIOSDIO0CMDENA; + output EMIOSDIO0CMDOUT; + output [7:0] EMIOSDIO0DATAENA; + output [7:0] EMIOSDIO0DATAOUT; + output EMIOSDIO0LEDCONTROL; + output EMIOSDIO1BUSPOWER; + output [2:0] EMIOSDIO1BUSVOLT; + output EMIOSDIO1CLKOUT; + output EMIOSDIO1CMDENA; + output EMIOSDIO1CMDOUT; + output [7:0] EMIOSDIO1DATAENA; + output [7:0] EMIOSDIO1DATAOUT; + output EMIOSDIO1LEDCONTROL; + output EMIOSPI0MO; + output EMIOSPI0MOTN; + output EMIOSPI0SCLKO; + output EMIOSPI0SCLKTN; + output EMIOSPI0SO; + output EMIOSPI0SSNTN; + output [2:0] EMIOSPI0SSON; + output EMIOSPI0STN; + output EMIOSPI1MO; + output EMIOSPI1MOTN; + output EMIOSPI1SCLKO; + output EMIOSPI1SCLKTN; + output EMIOSPI1SO; + output EMIOSPI1SSNTN; + output [2:0] EMIOSPI1SSON; + output EMIOSPI1STN; + output [2:0] EMIOTTC0WAVEO; + output [2:0] EMIOTTC1WAVEO; + output [2:0] EMIOTTC2WAVEO; + output [2:0] EMIOTTC3WAVEO; + output EMIOU2DSPORTVBUSCTRLUSB30; + output EMIOU2DSPORTVBUSCTRLUSB31; + output EMIOU3DSPORTVBUSCTRLUSB30; + output EMIOU3DSPORTVBUSCTRLUSB31; + output EMIOUART0DTRN; + output EMIOUART0RTSN; + output EMIOUART0TX; + output EMIOUART1DTRN; + output EMIOUART1RTSN; + output EMIOUART1TX; + output EMIOWDT0RSTO; + output EMIOWDT1RSTO; + output FMIOGEM0FIFORXCLKTOPLBUFG; + output FMIOGEM0FIFOTXCLKTOPLBUFG; + output FMIOGEM1FIFORXCLKTOPLBUFG; + output FMIOGEM1FIFOTXCLKTOPLBUFG; + output FMIOGEM2FIFORXCLKTOPLBUFG; + output FMIOGEM2FIFOTXCLKTOPLBUFG; + output FMIOGEM3FIFORXCLKTOPLBUFG; + output FMIOGEM3FIFOTXCLKTOPLBUFG; + output FMIOGEMTSUCLKTOPLBUFG; + output [31:0] FTMGPO; + output [7:0] GDMA2PLCACK; + output [7:0] GDMA2PLTVLD; + output [39:0] MAXIGP0ARADDR; + output [1:0] MAXIGP0ARBURST; + output [3:0] MAXIGP0ARCACHE; + output [15:0] MAXIGP0ARID; + output [7:0] MAXIGP0ARLEN; + output MAXIGP0ARLOCK; + output [2:0] MAXIGP0ARPROT; + output [3:0] MAXIGP0ARQOS; + output [2:0] MAXIGP0ARSIZE; + output [15:0] MAXIGP0ARUSER; + output MAXIGP0ARVALID; + output [39:0] MAXIGP0AWADDR; + output [1:0] MAXIGP0AWBURST; + output [3:0] MAXIGP0AWCACHE; + output [15:0] MAXIGP0AWID; + output [7:0] MAXIGP0AWLEN; + output MAXIGP0AWLOCK; + output [2:0] MAXIGP0AWPROT; + output [3:0] MAXIGP0AWQOS; + output [2:0] MAXIGP0AWSIZE; + output [15:0] MAXIGP0AWUSER; + output MAXIGP0AWVALID; + output MAXIGP0BREADY; + output MAXIGP0RREADY; + output [127:0] MAXIGP0WDATA; + output MAXIGP0WLAST; + output [15:0] MAXIGP0WSTRB; + output MAXIGP0WVALID; + output [39:0] MAXIGP1ARADDR; + output [1:0] MAXIGP1ARBURST; + output [3:0] MAXIGP1ARCACHE; + output [15:0] MAXIGP1ARID; + output [7:0] MAXIGP1ARLEN; + output MAXIGP1ARLOCK; + output [2:0] MAXIGP1ARPROT; + output [3:0] MAXIGP1ARQOS; + output [2:0] MAXIGP1ARSIZE; + output [15:0] MAXIGP1ARUSER; + output MAXIGP1ARVALID; + output [39:0] MAXIGP1AWADDR; + output [1:0] MAXIGP1AWBURST; + output [3:0] MAXIGP1AWCACHE; + output [15:0] MAXIGP1AWID; + output [7:0] MAXIGP1AWLEN; + output MAXIGP1AWLOCK; + output [2:0] MAXIGP1AWPROT; + output [3:0] MAXIGP1AWQOS; + output [2:0] MAXIGP1AWSIZE; + output [15:0] MAXIGP1AWUSER; + output MAXIGP1AWVALID; + output MAXIGP1BREADY; + output MAXIGP1RREADY; + output [127:0] MAXIGP1WDATA; + output MAXIGP1WLAST; + output [15:0] MAXIGP1WSTRB; + output MAXIGP1WVALID; + output [39:0] MAXIGP2ARADDR; + output [1:0] MAXIGP2ARBURST; + output [3:0] MAXIGP2ARCACHE; + output [15:0] MAXIGP2ARID; + output [7:0] MAXIGP2ARLEN; + output MAXIGP2ARLOCK; + output [2:0] MAXIGP2ARPROT; + output [3:0] MAXIGP2ARQOS; + output [2:0] MAXIGP2ARSIZE; + output [15:0] MAXIGP2ARUSER; + output MAXIGP2ARVALID; + output [39:0] MAXIGP2AWADDR; + output [1:0] MAXIGP2AWBURST; + output [3:0] MAXIGP2AWCACHE; + output [15:0] MAXIGP2AWID; + output [7:0] MAXIGP2AWLEN; + output MAXIGP2AWLOCK; + output [2:0] MAXIGP2AWPROT; + output [3:0] MAXIGP2AWQOS; + output [2:0] MAXIGP2AWSIZE; + output [15:0] MAXIGP2AWUSER; + output MAXIGP2AWVALID; + output MAXIGP2BREADY; + output MAXIGP2RREADY; + output [127:0] MAXIGP2WDATA; + output MAXIGP2WLAST; + output [15:0] MAXIGP2WSTRB; + output MAXIGP2WVALID; + output OSCRTCCLK; + output [3:0] PLCLK; + output PMUAIBAFIFMFPDREQ; + output PMUAIBAFIFMLPDREQ; + output [46:0] PMUERRORTOPL; + output [31:0] PMUPLGPO; + output PSPLEVENTO; + output [63:0] PSPLIRQFPD; + output [99:0] PSPLIRQLPD; + output [3:0] PSPLSTANDBYWFE; + output [3:0] PSPLSTANDBYWFI; + output PSPLTRACECTL; + output [31:0] PSPLTRACEDATA; + output [3:0] PSPLTRIGACK; + output [3:0] PSPLTRIGGER; + output PSS_ALTO_CORE_PAD_MGTTXN0OUT; + output PSS_ALTO_CORE_PAD_MGTTXN1OUT; + output PSS_ALTO_CORE_PAD_MGTTXN2OUT; + output PSS_ALTO_CORE_PAD_MGTTXN3OUT; + output PSS_ALTO_CORE_PAD_MGTTXP0OUT; + output PSS_ALTO_CORE_PAD_MGTTXP1OUT; + output PSS_ALTO_CORE_PAD_MGTTXP2OUT; + output PSS_ALTO_CORE_PAD_MGTTXP3OUT; + output PSS_ALTO_CORE_PAD_PADO; + output RPUEVENTO0; + output RPUEVENTO1; + output [43:0] SACEFPDACADDR; + output [2:0] SACEFPDACPROT; + output [3:0] SACEFPDACSNOOP; + output SACEFPDACVALID; + output SACEFPDARREADY; + output SACEFPDAWREADY; + output [5:0] SACEFPDBID; + output [1:0] SACEFPDBRESP; + output SACEFPDBUSER; + output SACEFPDBVALID; + output SACEFPDCDREADY; + output SACEFPDCRREADY; + output [127:0] SACEFPDRDATA; + output [5:0] SACEFPDRID; + output SACEFPDRLAST; + output [3:0] SACEFPDRRESP; + output SACEFPDRUSER; + output SACEFPDRVALID; + output SACEFPDWREADY; + output SAXIACPARREADY; + output SAXIACPAWREADY; + output [4:0] SAXIACPBID; + output [1:0] SAXIACPBRESP; + output SAXIACPBVALID; + output [127:0] SAXIACPRDATA; + output [4:0] SAXIACPRID; + output SAXIACPRLAST; + output [1:0] SAXIACPRRESP; + output SAXIACPRVALID; + output SAXIACPWREADY; + output SAXIGP0ARREADY; + output SAXIGP0AWREADY; + output [5:0] SAXIGP0BID; + output [1:0] SAXIGP0BRESP; + output SAXIGP0BVALID; + output [3:0] SAXIGP0RACOUNT; + output [7:0] SAXIGP0RCOUNT; + output [127:0] SAXIGP0RDATA; + output [5:0] SAXIGP0RID; + output SAXIGP0RLAST; + output [1:0] SAXIGP0RRESP; + output SAXIGP0RVALID; + output [3:0] SAXIGP0WACOUNT; + output [7:0] SAXIGP0WCOUNT; + output SAXIGP0WREADY; + output SAXIGP1ARREADY; + output SAXIGP1AWREADY; + output [5:0] SAXIGP1BID; + output [1:0] SAXIGP1BRESP; + output SAXIGP1BVALID; + output [3:0] SAXIGP1RACOUNT; + output [7:0] SAXIGP1RCOUNT; + output [127:0] SAXIGP1RDATA; + output [5:0] SAXIGP1RID; + output SAXIGP1RLAST; + output [1:0] SAXIGP1RRESP; + output SAXIGP1RVALID; + output [3:0] SAXIGP1WACOUNT; + output [7:0] SAXIGP1WCOUNT; + output SAXIGP1WREADY; + output SAXIGP2ARREADY; + output SAXIGP2AWREADY; + output [5:0] SAXIGP2BID; + output [1:0] SAXIGP2BRESP; + output SAXIGP2BVALID; + output [3:0] SAXIGP2RACOUNT; + output [7:0] SAXIGP2RCOUNT; + output [127:0] SAXIGP2RDATA; + output [5:0] SAXIGP2RID; + output SAXIGP2RLAST; + output [1:0] SAXIGP2RRESP; + output SAXIGP2RVALID; + output [3:0] SAXIGP2WACOUNT; + output [7:0] SAXIGP2WCOUNT; + output SAXIGP2WREADY; + output SAXIGP3ARREADY; + output SAXIGP3AWREADY; + output [5:0] SAXIGP3BID; + output [1:0] SAXIGP3BRESP; + output SAXIGP3BVALID; + output [3:0] SAXIGP3RACOUNT; + output [7:0] SAXIGP3RCOUNT; + output [127:0] SAXIGP3RDATA; + output [5:0] SAXIGP3RID; + output SAXIGP3RLAST; + output [1:0] SAXIGP3RRESP; + output SAXIGP3RVALID; + output [3:0] SAXIGP3WACOUNT; + output [7:0] SAXIGP3WCOUNT; + output SAXIGP3WREADY; + output SAXIGP4ARREADY; + output SAXIGP4AWREADY; + output [5:0] SAXIGP4BID; + output [1:0] SAXIGP4BRESP; + output SAXIGP4BVALID; + output [3:0] SAXIGP4RACOUNT; + output [7:0] SAXIGP4RCOUNT; + output [127:0] SAXIGP4RDATA; + output [5:0] SAXIGP4RID; + output SAXIGP4RLAST; + output [1:0] SAXIGP4RRESP; + output SAXIGP4RVALID; + output [3:0] SAXIGP4WACOUNT; + output [7:0] SAXIGP4WCOUNT; + output SAXIGP4WREADY; + output SAXIGP5ARREADY; + output SAXIGP5AWREADY; + output [5:0] SAXIGP5BID; + output [1:0] SAXIGP5BRESP; + output SAXIGP5BVALID; + output [3:0] SAXIGP5RACOUNT; + output [7:0] SAXIGP5RCOUNT; + output [127:0] SAXIGP5RDATA; + output [5:0] SAXIGP5RID; + output SAXIGP5RLAST; + output [1:0] SAXIGP5RRESP; + output SAXIGP5RVALID; + output [3:0] SAXIGP5WACOUNT; + output [7:0] SAXIGP5WCOUNT; + output SAXIGP5WREADY; + output SAXIGP6ARREADY; + output SAXIGP6AWREADY; + output [5:0] SAXIGP6BID; + output [1:0] SAXIGP6BRESP; + output SAXIGP6BVALID; + output [3:0] SAXIGP6RACOUNT; + output [7:0] SAXIGP6RCOUNT; + output [127:0] SAXIGP6RDATA; + output [5:0] SAXIGP6RID; + output SAXIGP6RLAST; + output [1:0] SAXIGP6RRESP; + output SAXIGP6RVALID; + output [3:0] SAXIGP6WACOUNT; + output [7:0] SAXIGP6WCOUNT; + output SAXIGP6WREADY; + inout [3:0] PSS_ALTO_CORE_PAD_BOOTMODE; + inout PSS_ALTO_CORE_PAD_CLK; + inout PSS_ALTO_CORE_PAD_DONEB; + inout [17:0] PSS_ALTO_CORE_PAD_DRAMA; + inout PSS_ALTO_CORE_PAD_DRAMACTN; + inout PSS_ALTO_CORE_PAD_DRAMALERTN; + inout [1:0] PSS_ALTO_CORE_PAD_DRAMBA; + inout [1:0] PSS_ALTO_CORE_PAD_DRAMBG; + inout [1:0] PSS_ALTO_CORE_PAD_DRAMCK; + inout [1:0] PSS_ALTO_CORE_PAD_DRAMCKE; + inout [1:0] PSS_ALTO_CORE_PAD_DRAMCKN; + inout [1:0] PSS_ALTO_CORE_PAD_DRAMCSN; + inout [8:0] PSS_ALTO_CORE_PAD_DRAMDM; + inout [71:0] PSS_ALTO_CORE_PAD_DRAMDQ; + inout [8:0] PSS_ALTO_CORE_PAD_DRAMDQS; + inout [8:0] PSS_ALTO_CORE_PAD_DRAMDQSN; + inout [1:0] PSS_ALTO_CORE_PAD_DRAMODT; + inout PSS_ALTO_CORE_PAD_DRAMPARITY; + inout PSS_ALTO_CORE_PAD_DRAMRAMRSTN; + inout PSS_ALTO_CORE_PAD_ERROROUT; + inout PSS_ALTO_CORE_PAD_ERRORSTATUS; + inout PSS_ALTO_CORE_PAD_INITB; + inout PSS_ALTO_CORE_PAD_JTAGTCK; + inout PSS_ALTO_CORE_PAD_JTAGTDI; + inout PSS_ALTO_CORE_PAD_JTAGTDO; + inout PSS_ALTO_CORE_PAD_JTAGTMS; + inout [77:0] PSS_ALTO_CORE_PAD_MIO; + inout PSS_ALTO_CORE_PAD_PORB; + inout PSS_ALTO_CORE_PAD_PROGB; + inout PSS_ALTO_CORE_PAD_RCALIBINOUT; + inout PSS_ALTO_CORE_PAD_SRSTB; + inout PSS_ALTO_CORE_PAD_ZQ; + input [7:0] ADMAFCICLK; + input AIBPMUAFIFMFPDACK; + input AIBPMUAFIFMLPDACK; + input DDRCEXTREFRESHRANK0REQ; + input DDRCEXTREFRESHRANK1REQ; + input DDRCREFRESHPLCLK; + input DPAUXDATAIN; + input DPEXTERNALCUSTOMEVENT1; + input DPEXTERNALCUSTOMEVENT2; + input DPEXTERNALVSYNCEVENT; + input DPHOTPLUGDETECT; + input [7:0] DPLIVEGFXALPHAIN; + input [35:0] DPLIVEGFXPIXEL1IN; + input DPLIVEVIDEOINDE; + input DPLIVEVIDEOINHSYNC; + input [35:0] DPLIVEVIDEOINPIXEL1; + input DPLIVEVIDEOINVSYNC; + input DPMAXISMIXEDAUDIOTREADY; + input DPSAXISAUDIOCLK; + input [31:0] DPSAXISAUDIOTDATA; + input DPSAXISAUDIOTID; + input DPSAXISAUDIOTVALID; + input DPVIDEOINCLK; + input EMIOCAN0PHYRX; + input EMIOCAN1PHYRX; + input EMIOENET0DMATXSTATUSTOG; + input EMIOENET0EXTINTIN; + input EMIOENET0GMIICOL; + input EMIOENET0GMIICRS; + input EMIOENET0GMIIRXCLK; + input [7:0] EMIOENET0GMIIRXD; + input EMIOENET0GMIIRXDV; + input EMIOENET0GMIIRXER; + input EMIOENET0GMIITXCLK; + input EMIOENET0MDIOI; + input EMIOENET0RXWOVERFLOW; + input EMIOENET0TXRCONTROL; + input [7:0] EMIOENET0TXRDATA; + input EMIOENET0TXRDATARDY; + input EMIOENET0TXREOP; + input EMIOENET0TXRERR; + input EMIOENET0TXRFLUSHED; + input EMIOENET0TXRSOP; + input EMIOENET0TXRUNDERFLOW; + input EMIOENET0TXRVALID; + input EMIOENET1DMATXSTATUSTOG; + input EMIOENET1EXTINTIN; + input EMIOENET1GMIICOL; + input EMIOENET1GMIICRS; + input EMIOENET1GMIIRXCLK; + input [7:0] EMIOENET1GMIIRXD; + input EMIOENET1GMIIRXDV; + input EMIOENET1GMIIRXER; + input EMIOENET1GMIITXCLK; + input EMIOENET1MDIOI; + input EMIOENET1RXWOVERFLOW; + input EMIOENET1TXRCONTROL; + input [7:0] EMIOENET1TXRDATA; + input EMIOENET1TXRDATARDY; + input EMIOENET1TXREOP; + input EMIOENET1TXRERR; + input EMIOENET1TXRFLUSHED; + input EMIOENET1TXRSOP; + input EMIOENET1TXRUNDERFLOW; + input EMIOENET1TXRVALID; + input EMIOENET2DMATXSTATUSTOG; + input EMIOENET2EXTINTIN; + input EMIOENET2GMIICOL; + input EMIOENET2GMIICRS; + input EMIOENET2GMIIRXCLK; + input [7:0] EMIOENET2GMIIRXD; + input EMIOENET2GMIIRXDV; + input EMIOENET2GMIIRXER; + input EMIOENET2GMIITXCLK; + input EMIOENET2MDIOI; + input EMIOENET2RXWOVERFLOW; + input EMIOENET2TXRCONTROL; + input [7:0] EMIOENET2TXRDATA; + input EMIOENET2TXRDATARDY; + input EMIOENET2TXREOP; + input EMIOENET2TXRERR; + input EMIOENET2TXRFLUSHED; + input EMIOENET2TXRSOP; + input EMIOENET2TXRUNDERFLOW; + input EMIOENET2TXRVALID; + input EMIOENET3DMATXSTATUSTOG; + input EMIOENET3EXTINTIN; + input EMIOENET3GMIICOL; + input EMIOENET3GMIICRS; + input EMIOENET3GMIIRXCLK; + input [7:0] EMIOENET3GMIIRXD; + input EMIOENET3GMIIRXDV; + input EMIOENET3GMIIRXER; + input EMIOENET3GMIITXCLK; + input EMIOENET3MDIOI; + input EMIOENET3RXWOVERFLOW; + input EMIOENET3TXRCONTROL; + input [7:0] EMIOENET3TXRDATA; + input EMIOENET3TXRDATARDY; + input EMIOENET3TXREOP; + input EMIOENET3TXRERR; + input EMIOENET3TXRFLUSHED; + input EMIOENET3TXRSOP; + input EMIOENET3TXRUNDERFLOW; + input EMIOENET3TXRVALID; + input EMIOENETTSUCLK; + input [1:0] EMIOGEM0TSUINCCTRL; + input [1:0] EMIOGEM1TSUINCCTRL; + input [1:0] EMIOGEM2TSUINCCTRL; + input [1:0] EMIOGEM3TSUINCCTRL; + input [95:0] EMIOGPIOI; + input EMIOHUBPORTOVERCRNTUSB20; + input EMIOHUBPORTOVERCRNTUSB21; + input EMIOHUBPORTOVERCRNTUSB30; + input EMIOHUBPORTOVERCRNTUSB31; + input EMIOI2C0SCLI; + input EMIOI2C0SDAI; + input EMIOI2C1SCLI; + input EMIOI2C1SDAI; + input EMIOSDIO0CDN; + input EMIOSDIO0CMDIN; + input [7:0] EMIOSDIO0DATAIN; + input EMIOSDIO0FBCLKIN; + input EMIOSDIO0WP; + input EMIOSDIO1CDN; + input EMIOSDIO1CMDIN; + input [7:0] EMIOSDIO1DATAIN; + input EMIOSDIO1FBCLKIN; + input EMIOSDIO1WP; + input EMIOSPI0MI; + input EMIOSPI0SCLKI; + input EMIOSPI0SI; + input EMIOSPI0SSIN; + input EMIOSPI1MI; + input EMIOSPI1SCLKI; + input EMIOSPI1SI; + input EMIOSPI1SSIN; + input [2:0] EMIOTTC0CLKI; + input [2:0] EMIOTTC1CLKI; + input [2:0] EMIOTTC2CLKI; + input [2:0] EMIOTTC3CLKI; + input EMIOUART0CTSN; + input EMIOUART0DCDN; + input EMIOUART0DSRN; + input EMIOUART0RIN; + input EMIOUART0RX; + input EMIOUART1CTSN; + input EMIOUART1DCDN; + input EMIOUART1DSRN; + input EMIOUART1RIN; + input EMIOUART1RX; + input EMIOWDT0CLKI; + input EMIOWDT1CLKI; + input FMIOGEM0FIFORXCLKFROMPL; + input FMIOGEM0FIFOTXCLKFROMPL; + input FMIOGEM0SIGNALDETECT; + input FMIOGEM1FIFORXCLKFROMPL; + input FMIOGEM1FIFOTXCLKFROMPL; + input FMIOGEM1SIGNALDETECT; + input FMIOGEM2FIFORXCLKFROMPL; + input FMIOGEM2FIFOTXCLKFROMPL; + input FMIOGEM2SIGNALDETECT; + input FMIOGEM3FIFORXCLKFROMPL; + input FMIOGEM3FIFOTXCLKFROMPL; + input FMIOGEM3SIGNALDETECT; + input FMIOGEMTSUCLKFROMPL; + input [31:0] FTMGPI; + input [7:0] GDMAFCICLK; + input MAXIGP0ACLK; + input MAXIGP0ARREADY; + input MAXIGP0AWREADY; + input [15:0] MAXIGP0BID; + input [1:0] MAXIGP0BRESP; + input MAXIGP0BVALID; + input [127:0] MAXIGP0RDATA; + input [15:0] MAXIGP0RID; + input MAXIGP0RLAST; + input [1:0] MAXIGP0RRESP; + input MAXIGP0RVALID; + input MAXIGP0WREADY; + input MAXIGP1ACLK; + input MAXIGP1ARREADY; + input MAXIGP1AWREADY; + input [15:0] MAXIGP1BID; + input [1:0] MAXIGP1BRESP; + input MAXIGP1BVALID; + input [127:0] MAXIGP1RDATA; + input [15:0] MAXIGP1RID; + input MAXIGP1RLAST; + input [1:0] MAXIGP1RRESP; + input MAXIGP1RVALID; + input MAXIGP1WREADY; + input MAXIGP2ACLK; + input MAXIGP2ARREADY; + input MAXIGP2AWREADY; + input [15:0] MAXIGP2BID; + input [1:0] MAXIGP2BRESP; + input MAXIGP2BVALID; + input [127:0] MAXIGP2RDATA; + input [15:0] MAXIGP2RID; + input MAXIGP2RLAST; + input [1:0] MAXIGP2RRESP; + input MAXIGP2RVALID; + input MAXIGP2WREADY; + input NFIQ0LPDRPU; + input NFIQ1LPDRPU; + input NIRQ0LPDRPU; + input NIRQ1LPDRPU; + input [7:0] PL2ADMACVLD; + input [7:0] PL2ADMATACK; + input [7:0] PL2GDMACVLD; + input [7:0] PL2GDMATACK; + input PLACECLK; + input PLACPINACT; + input [3:0] PLFPGASTOP; + input [2:0] PLLAUXREFCLKFPD; + input [1:0] PLLAUXREFCLKLPD; + input [31:0] PLPMUGPI; + input [3:0] PLPSAPUGICFIQ; + input [3:0] PLPSAPUGICIRQ; + input PLPSEVENTI; + input [7:0] PLPSIRQ0; + input [7:0] PLPSIRQ1; + input PLPSTRACECLK; + input [3:0] PLPSTRIGACK; + input [3:0] PLPSTRIGGER; + input [3:0] PMUERRORFROMPL; + input PSS_ALTO_CORE_PAD_MGTRXN0IN; + input PSS_ALTO_CORE_PAD_MGTRXN1IN; + input PSS_ALTO_CORE_PAD_MGTRXN2IN; + input PSS_ALTO_CORE_PAD_MGTRXN3IN; + input PSS_ALTO_CORE_PAD_MGTRXP0IN; + input PSS_ALTO_CORE_PAD_MGTRXP1IN; + input PSS_ALTO_CORE_PAD_MGTRXP2IN; + input PSS_ALTO_CORE_PAD_MGTRXP3IN; + input PSS_ALTO_CORE_PAD_PADI; + input PSS_ALTO_CORE_PAD_REFN0IN; + input PSS_ALTO_CORE_PAD_REFN1IN; + input PSS_ALTO_CORE_PAD_REFN2IN; + input PSS_ALTO_CORE_PAD_REFN3IN; + input PSS_ALTO_CORE_PAD_REFP0IN; + input PSS_ALTO_CORE_PAD_REFP1IN; + input PSS_ALTO_CORE_PAD_REFP2IN; + input PSS_ALTO_CORE_PAD_REFP3IN; + input RPUEVENTI0; + input RPUEVENTI1; + input SACEFPDACREADY; + input [43:0] SACEFPDARADDR; + input [1:0] SACEFPDARBAR; + input [1:0] SACEFPDARBURST; + input [3:0] SACEFPDARCACHE; + input [1:0] SACEFPDARDOMAIN; + input [5:0] SACEFPDARID; + input [7:0] SACEFPDARLEN; + input SACEFPDARLOCK; + input [2:0] SACEFPDARPROT; + input [3:0] SACEFPDARQOS; + input [3:0] SACEFPDARREGION; + input [2:0] SACEFPDARSIZE; + input [3:0] SACEFPDARSNOOP; + input [15:0] SACEFPDARUSER; + input SACEFPDARVALID; + input [43:0] SACEFPDAWADDR; + input [1:0] SACEFPDAWBAR; + input [1:0] SACEFPDAWBURST; + input [3:0] SACEFPDAWCACHE; + input [1:0] SACEFPDAWDOMAIN; + input [5:0] SACEFPDAWID; + input [7:0] SACEFPDAWLEN; + input SACEFPDAWLOCK; + input [2:0] SACEFPDAWPROT; + input [3:0] SACEFPDAWQOS; + input [3:0] SACEFPDAWREGION; + input [2:0] SACEFPDAWSIZE; + input [2:0] SACEFPDAWSNOOP; + input [15:0] SACEFPDAWUSER; + input SACEFPDAWVALID; + input SACEFPDBREADY; + input [127:0] SACEFPDCDDATA; + input SACEFPDCDLAST; + input SACEFPDCDVALID; + input [4:0] SACEFPDCRRESP; + input SACEFPDCRVALID; + input SACEFPDRACK; + input SACEFPDRREADY; + input SACEFPDWACK; + input [127:0] SACEFPDWDATA; + input SACEFPDWLAST; + input [15:0] SACEFPDWSTRB; + input SACEFPDWUSER; + input SACEFPDWVALID; + input SAXIACPACLK; + input [39:0] SAXIACPARADDR; + input [1:0] SAXIACPARBURST; + input [3:0] SAXIACPARCACHE; + input [4:0] SAXIACPARID; + input [7:0] SAXIACPARLEN; + input SAXIACPARLOCK; + input [2:0] SAXIACPARPROT; + input [3:0] SAXIACPARQOS; + input [2:0] SAXIACPARSIZE; + input [1:0] SAXIACPARUSER; + input SAXIACPARVALID; + input [39:0] SAXIACPAWADDR; + input [1:0] SAXIACPAWBURST; + input [3:0] SAXIACPAWCACHE; + input [4:0] SAXIACPAWID; + input [7:0] SAXIACPAWLEN; + input SAXIACPAWLOCK; + input [2:0] SAXIACPAWPROT; + input [3:0] SAXIACPAWQOS; + input [2:0] SAXIACPAWSIZE; + input [1:0] SAXIACPAWUSER; + input SAXIACPAWVALID; + input SAXIACPBREADY; + input SAXIACPRREADY; + input [127:0] SAXIACPWDATA; + input SAXIACPWLAST; + input [15:0] SAXIACPWSTRB; + input SAXIACPWVALID; + input [48:0] SAXIGP0ARADDR; + input [1:0] SAXIGP0ARBURST; + input [3:0] SAXIGP0ARCACHE; + input [5:0] SAXIGP0ARID; + input [7:0] SAXIGP0ARLEN; + input SAXIGP0ARLOCK; + input [2:0] SAXIGP0ARPROT; + input [3:0] SAXIGP0ARQOS; + input [2:0] SAXIGP0ARSIZE; + input SAXIGP0ARUSER; + input SAXIGP0ARVALID; + input [48:0] SAXIGP0AWADDR; + input [1:0] SAXIGP0AWBURST; + input [3:0] SAXIGP0AWCACHE; + input [5:0] SAXIGP0AWID; + input [7:0] SAXIGP0AWLEN; + input SAXIGP0AWLOCK; + input [2:0] SAXIGP0AWPROT; + input [3:0] SAXIGP0AWQOS; + input [2:0] SAXIGP0AWSIZE; + input SAXIGP0AWUSER; + input SAXIGP0AWVALID; + input SAXIGP0BREADY; + input SAXIGP0RCLK; + input SAXIGP0RREADY; + input SAXIGP0WCLK; + input [127:0] SAXIGP0WDATA; + input SAXIGP0WLAST; + input [15:0] SAXIGP0WSTRB; + input SAXIGP0WVALID; + input [48:0] SAXIGP1ARADDR; + input [1:0] SAXIGP1ARBURST; + input [3:0] SAXIGP1ARCACHE; + input [5:0] SAXIGP1ARID; + input [7:0] SAXIGP1ARLEN; + input SAXIGP1ARLOCK; + input [2:0] SAXIGP1ARPROT; + input [3:0] SAXIGP1ARQOS; + input [2:0] SAXIGP1ARSIZE; + input SAXIGP1ARUSER; + input SAXIGP1ARVALID; + input [48:0] SAXIGP1AWADDR; + input [1:0] SAXIGP1AWBURST; + input [3:0] SAXIGP1AWCACHE; + input [5:0] SAXIGP1AWID; + input [7:0] SAXIGP1AWLEN; + input SAXIGP1AWLOCK; + input [2:0] SAXIGP1AWPROT; + input [3:0] SAXIGP1AWQOS; + input [2:0] SAXIGP1AWSIZE; + input SAXIGP1AWUSER; + input SAXIGP1AWVALID; + input SAXIGP1BREADY; + input SAXIGP1RCLK; + input SAXIGP1RREADY; + input SAXIGP1WCLK; + input [127:0] SAXIGP1WDATA; + input SAXIGP1WLAST; + input [15:0] SAXIGP1WSTRB; + input SAXIGP1WVALID; + input [48:0] SAXIGP2ARADDR; + input [1:0] SAXIGP2ARBURST; + input [3:0] SAXIGP2ARCACHE; + input [5:0] SAXIGP2ARID; + input [7:0] SAXIGP2ARLEN; + input SAXIGP2ARLOCK; + input [2:0] SAXIGP2ARPROT; + input [3:0] SAXIGP2ARQOS; + input [2:0] SAXIGP2ARSIZE; + input SAXIGP2ARUSER; + input SAXIGP2ARVALID; + input [48:0] SAXIGP2AWADDR; + input [1:0] SAXIGP2AWBURST; + input [3:0] SAXIGP2AWCACHE; + input [5:0] SAXIGP2AWID; + input [7:0] SAXIGP2AWLEN; + input SAXIGP2AWLOCK; + input [2:0] SAXIGP2AWPROT; + input [3:0] SAXIGP2AWQOS; + input [2:0] SAXIGP2AWSIZE; + input SAXIGP2AWUSER; + input SAXIGP2AWVALID; + input SAXIGP2BREADY; + input SAXIGP2RCLK; + input SAXIGP2RREADY; + input SAXIGP2WCLK; + input [127:0] SAXIGP2WDATA; + input SAXIGP2WLAST; + input [15:0] SAXIGP2WSTRB; + input SAXIGP2WVALID; + input [48:0] SAXIGP3ARADDR; + input [1:0] SAXIGP3ARBURST; + input [3:0] SAXIGP3ARCACHE; + input [5:0] SAXIGP3ARID; + input [7:0] SAXIGP3ARLEN; + input SAXIGP3ARLOCK; + input [2:0] SAXIGP3ARPROT; + input [3:0] SAXIGP3ARQOS; + input [2:0] SAXIGP3ARSIZE; + input SAXIGP3ARUSER; + input SAXIGP3ARVALID; + input [48:0] SAXIGP3AWADDR; + input [1:0] SAXIGP3AWBURST; + input [3:0] SAXIGP3AWCACHE; + input [5:0] SAXIGP3AWID; + input [7:0] SAXIGP3AWLEN; + input SAXIGP3AWLOCK; + input [2:0] SAXIGP3AWPROT; + input [3:0] SAXIGP3AWQOS; + input [2:0] SAXIGP3AWSIZE; + input SAXIGP3AWUSER; + input SAXIGP3AWVALID; + input SAXIGP3BREADY; + input SAXIGP3RCLK; + input SAXIGP3RREADY; + input SAXIGP3WCLK; + input [127:0] SAXIGP3WDATA; + input SAXIGP3WLAST; + input [15:0] SAXIGP3WSTRB; + input SAXIGP3WVALID; + input [48:0] SAXIGP4ARADDR; + input [1:0] SAXIGP4ARBURST; + input [3:0] SAXIGP4ARCACHE; + input [5:0] SAXIGP4ARID; + input [7:0] SAXIGP4ARLEN; + input SAXIGP4ARLOCK; + input [2:0] SAXIGP4ARPROT; + input [3:0] SAXIGP4ARQOS; + input [2:0] SAXIGP4ARSIZE; + input SAXIGP4ARUSER; + input SAXIGP4ARVALID; + input [48:0] SAXIGP4AWADDR; + input [1:0] SAXIGP4AWBURST; + input [3:0] SAXIGP4AWCACHE; + input [5:0] SAXIGP4AWID; + input [7:0] SAXIGP4AWLEN; + input SAXIGP4AWLOCK; + input [2:0] SAXIGP4AWPROT; + input [3:0] SAXIGP4AWQOS; + input [2:0] SAXIGP4AWSIZE; + input SAXIGP4AWUSER; + input SAXIGP4AWVALID; + input SAXIGP4BREADY; + input SAXIGP4RCLK; + input SAXIGP4RREADY; + input SAXIGP4WCLK; + input [127:0] SAXIGP4WDATA; + input SAXIGP4WLAST; + input [15:0] SAXIGP4WSTRB; + input SAXIGP4WVALID; + input [48:0] SAXIGP5ARADDR; + input [1:0] SAXIGP5ARBURST; + input [3:0] SAXIGP5ARCACHE; + input [5:0] SAXIGP5ARID; + input [7:0] SAXIGP5ARLEN; + input SAXIGP5ARLOCK; + input [2:0] SAXIGP5ARPROT; + input [3:0] SAXIGP5ARQOS; + input [2:0] SAXIGP5ARSIZE; + input SAXIGP5ARUSER; + input SAXIGP5ARVALID; + input [48:0] SAXIGP5AWADDR; + input [1:0] SAXIGP5AWBURST; + input [3:0] SAXIGP5AWCACHE; + input [5:0] SAXIGP5AWID; + input [7:0] SAXIGP5AWLEN; + input SAXIGP5AWLOCK; + input [2:0] SAXIGP5AWPROT; + input [3:0] SAXIGP5AWQOS; + input [2:0] SAXIGP5AWSIZE; + input SAXIGP5AWUSER; + input SAXIGP5AWVALID; + input SAXIGP5BREADY; + input SAXIGP5RCLK; + input SAXIGP5RREADY; + input SAXIGP5WCLK; + input [127:0] SAXIGP5WDATA; + input SAXIGP5WLAST; + input [15:0] SAXIGP5WSTRB; + input SAXIGP5WVALID; + input [48:0] SAXIGP6ARADDR; + input [1:0] SAXIGP6ARBURST; + input [3:0] SAXIGP6ARCACHE; + input [5:0] SAXIGP6ARID; + input [7:0] SAXIGP6ARLEN; + input SAXIGP6ARLOCK; + input [2:0] SAXIGP6ARPROT; + input [3:0] SAXIGP6ARQOS; + input [2:0] SAXIGP6ARSIZE; + input SAXIGP6ARUSER; + input SAXIGP6ARVALID; + input [48:0] SAXIGP6AWADDR; + input [1:0] SAXIGP6AWBURST; + input [3:0] SAXIGP6AWCACHE; + input [5:0] SAXIGP6AWID; + input [7:0] SAXIGP6AWLEN; + input SAXIGP6AWLOCK; + input [2:0] SAXIGP6AWPROT; + input [3:0] SAXIGP6AWQOS; + input [2:0] SAXIGP6AWSIZE; + input SAXIGP6AWUSER; + input SAXIGP6AWVALID; + input SAXIGP6BREADY; + input SAXIGP6RCLK; + input SAXIGP6RREADY; + input SAXIGP6WCLK; + input [127:0] SAXIGP6WDATA; + input SAXIGP6WLAST; + input [15:0] SAXIGP6WSTRB; + input SAXIGP6WVALID; + input [59:0] STMEVENT; +endmodule + +module ILKN (...); + parameter BYPASS = "FALSE"; + parameter [1:0] CTL_RX_BURSTMAX = 2'h3; + parameter [1:0] CTL_RX_CHAN_EXT = 2'h0; + parameter [3:0] CTL_RX_LAST_LANE = 4'hB; + parameter [15:0] CTL_RX_MFRAMELEN_MINUS1 = 16'h07FF; + parameter CTL_RX_PACKET_MODE = "TRUE"; + parameter [2:0] CTL_RX_RETRANS_MULT = 3'h0; + parameter [3:0] CTL_RX_RETRANS_RETRY = 4'h2; + parameter [15:0] CTL_RX_RETRANS_TIMER1 = 16'h0000; + parameter [15:0] CTL_RX_RETRANS_TIMER2 = 16'h0008; + parameter [11:0] CTL_RX_RETRANS_WDOG = 12'h000; + parameter [7:0] CTL_RX_RETRANS_WRAP_TIMER = 8'h00; + parameter CTL_TEST_MODE_PIN_CHAR = "FALSE"; + parameter [1:0] CTL_TX_BURSTMAX = 2'h3; + parameter [2:0] CTL_TX_BURSTSHORT = 3'h1; + parameter [1:0] CTL_TX_CHAN_EXT = 2'h0; + parameter CTL_TX_DISABLE_SKIPWORD = "TRUE"; + parameter [6:0] CTL_TX_FC_CALLEN = 7'h00; + parameter [3:0] CTL_TX_LAST_LANE = 4'hB; + parameter [15:0] CTL_TX_MFRAMELEN_MINUS1 = 16'h07FF; + parameter [13:0] CTL_TX_RETRANS_DEPTH = 14'h0800; + parameter [2:0] CTL_TX_RETRANS_MULT = 3'h0; + parameter [1:0] CTL_TX_RETRANS_RAM_BANKS = 2'h3; + parameter MODE = "TRUE"; + parameter SIM_VERSION = "2.0"; + parameter TEST_MODE_PIN_CHAR = "FALSE"; + output [15:0] DRP_DO; + output DRP_RDY; + output [65:0] RX_BYPASS_DATAOUT00; + output [65:0] RX_BYPASS_DATAOUT01; + output [65:0] RX_BYPASS_DATAOUT02; + output [65:0] RX_BYPASS_DATAOUT03; + output [65:0] RX_BYPASS_DATAOUT04; + output [65:0] RX_BYPASS_DATAOUT05; + output [65:0] RX_BYPASS_DATAOUT06; + output [65:0] RX_BYPASS_DATAOUT07; + output [65:0] RX_BYPASS_DATAOUT08; + output [65:0] RX_BYPASS_DATAOUT09; + output [65:0] RX_BYPASS_DATAOUT10; + output [65:0] RX_BYPASS_DATAOUT11; + output [11:0] RX_BYPASS_ENAOUT; + output [11:0] RX_BYPASS_IS_AVAILOUT; + output [11:0] RX_BYPASS_IS_BADLYFRAMEDOUT; + output [11:0] RX_BYPASS_IS_OVERFLOWOUT; + output [11:0] RX_BYPASS_IS_SYNCEDOUT; + output [11:0] RX_BYPASS_IS_SYNCWORDOUT; + output [10:0] RX_CHANOUT0; + output [10:0] RX_CHANOUT1; + output [10:0] RX_CHANOUT2; + output [10:0] RX_CHANOUT3; + output [127:0] RX_DATAOUT0; + output [127:0] RX_DATAOUT1; + output [127:0] RX_DATAOUT2; + output [127:0] RX_DATAOUT3; + output RX_ENAOUT0; + output RX_ENAOUT1; + output RX_ENAOUT2; + output RX_ENAOUT3; + output RX_EOPOUT0; + output RX_EOPOUT1; + output RX_EOPOUT2; + output RX_EOPOUT3; + output RX_ERROUT0; + output RX_ERROUT1; + output RX_ERROUT2; + output RX_ERROUT3; + output [3:0] RX_MTYOUT0; + output [3:0] RX_MTYOUT1; + output [3:0] RX_MTYOUT2; + output [3:0] RX_MTYOUT3; + output RX_OVFOUT; + output RX_SOPOUT0; + output RX_SOPOUT1; + output RX_SOPOUT2; + output RX_SOPOUT3; + output STAT_RX_ALIGNED; + output STAT_RX_ALIGNED_ERR; + output [11:0] STAT_RX_BAD_TYPE_ERR; + output STAT_RX_BURSTMAX_ERR; + output STAT_RX_BURST_ERR; + output STAT_RX_CRC24_ERR; + output [11:0] STAT_RX_CRC32_ERR; + output [11:0] STAT_RX_CRC32_VALID; + output [11:0] STAT_RX_DESCRAM_ERR; + output [11:0] STAT_RX_DIAGWORD_INTFSTAT; + output [11:0] STAT_RX_DIAGWORD_LANESTAT; + output [255:0] STAT_RX_FC_STAT; + output [11:0] STAT_RX_FRAMING_ERR; + output STAT_RX_MEOP_ERR; + output [11:0] STAT_RX_MF_ERR; + output [11:0] STAT_RX_MF_LEN_ERR; + output [11:0] STAT_RX_MF_REPEAT_ERR; + output STAT_RX_MISALIGNED; + output STAT_RX_MSOP_ERR; + output [7:0] STAT_RX_MUBITS; + output STAT_RX_MUBITS_UPDATED; + output STAT_RX_OVERFLOW_ERR; + output STAT_RX_RETRANS_CRC24_ERR; + output STAT_RX_RETRANS_DISC; + output [15:0] STAT_RX_RETRANS_LATENCY; + output STAT_RX_RETRANS_REQ; + output STAT_RX_RETRANS_RETRY_ERR; + output [7:0] STAT_RX_RETRANS_SEQ; + output STAT_RX_RETRANS_SEQ_UPDATED; + output [2:0] STAT_RX_RETRANS_STATE; + output [4:0] STAT_RX_RETRANS_SUBSEQ; + output STAT_RX_RETRANS_WDOG_ERR; + output STAT_RX_RETRANS_WRAP_ERR; + output [11:0] STAT_RX_SYNCED; + output [11:0] STAT_RX_SYNCED_ERR; + output [11:0] STAT_RX_WORD_SYNC; + output STAT_TX_BURST_ERR; + output STAT_TX_ERRINJ_BITERR_DONE; + output STAT_TX_OVERFLOW_ERR; + output STAT_TX_RETRANS_BURST_ERR; + output STAT_TX_RETRANS_BUSY; + output STAT_TX_RETRANS_RAM_PERROUT; + output [8:0] STAT_TX_RETRANS_RAM_RADDR; + output STAT_TX_RETRANS_RAM_RD_B0; + output STAT_TX_RETRANS_RAM_RD_B1; + output STAT_TX_RETRANS_RAM_RD_B2; + output STAT_TX_RETRANS_RAM_RD_B3; + output [1:0] STAT_TX_RETRANS_RAM_RSEL; + output [8:0] STAT_TX_RETRANS_RAM_WADDR; + output [643:0] STAT_TX_RETRANS_RAM_WDATA; + output STAT_TX_RETRANS_RAM_WE_B0; + output STAT_TX_RETRANS_RAM_WE_B1; + output STAT_TX_RETRANS_RAM_WE_B2; + output STAT_TX_RETRANS_RAM_WE_B3; + output STAT_TX_UNDERFLOW_ERR; + output TX_OVFOUT; + output TX_RDYOUT; + output [63:0] TX_SERDES_DATA00; + output [63:0] TX_SERDES_DATA01; + output [63:0] TX_SERDES_DATA02; + output [63:0] TX_SERDES_DATA03; + output [63:0] TX_SERDES_DATA04; + output [63:0] TX_SERDES_DATA05; + output [63:0] TX_SERDES_DATA06; + output [63:0] TX_SERDES_DATA07; + output [63:0] TX_SERDES_DATA08; + output [63:0] TX_SERDES_DATA09; + output [63:0] TX_SERDES_DATA10; + output [63:0] TX_SERDES_DATA11; + input CORE_CLK; + input CTL_RX_FORCE_RESYNC; + input CTL_RX_RETRANS_ACK; + input CTL_RX_RETRANS_ENABLE; + input CTL_RX_RETRANS_ERRIN; + input CTL_RX_RETRANS_FORCE_REQ; + input CTL_RX_RETRANS_RESET; + input CTL_RX_RETRANS_RESET_MODE; + input CTL_TX_DIAGWORD_INTFSTAT; + input [11:0] CTL_TX_DIAGWORD_LANESTAT; + input CTL_TX_ENABLE; + input CTL_TX_ERRINJ_BITERR_GO; + input [3:0] CTL_TX_ERRINJ_BITERR_LANE; + input [255:0] CTL_TX_FC_STAT; + input [7:0] CTL_TX_MUBITS; + input CTL_TX_RETRANS_ENABLE; + input CTL_TX_RETRANS_RAM_PERRIN; + input [643:0] CTL_TX_RETRANS_RAM_RDATA; + input CTL_TX_RETRANS_REQ; + input CTL_TX_RETRANS_REQ_VALID; + input [11:0] CTL_TX_RLIM_DELTA; + input CTL_TX_RLIM_ENABLE; + input [7:0] CTL_TX_RLIM_INTV; + input [11:0] CTL_TX_RLIM_MAX; + input [9:0] DRP_ADDR; + input DRP_CLK; + input [15:0] DRP_DI; + input DRP_EN; + input DRP_WE; + input LBUS_CLK; + input RX_BYPASS_FORCE_REALIGNIN; + input RX_BYPASS_RDIN; + input RX_RESET; + input [11:0] RX_SERDES_CLK; + input [63:0] RX_SERDES_DATA00; + input [63:0] RX_SERDES_DATA01; + input [63:0] RX_SERDES_DATA02; + input [63:0] RX_SERDES_DATA03; + input [63:0] RX_SERDES_DATA04; + input [63:0] RX_SERDES_DATA05; + input [63:0] RX_SERDES_DATA06; + input [63:0] RX_SERDES_DATA07; + input [63:0] RX_SERDES_DATA08; + input [63:0] RX_SERDES_DATA09; + input [63:0] RX_SERDES_DATA10; + input [63:0] RX_SERDES_DATA11; + input [11:0] RX_SERDES_RESET; + input TX_BCTLIN0; + input TX_BCTLIN1; + input TX_BCTLIN2; + input TX_BCTLIN3; + input [11:0] TX_BYPASS_CTRLIN; + input [63:0] TX_BYPASS_DATAIN00; + input [63:0] TX_BYPASS_DATAIN01; + input [63:0] TX_BYPASS_DATAIN02; + input [63:0] TX_BYPASS_DATAIN03; + input [63:0] TX_BYPASS_DATAIN04; + input [63:0] TX_BYPASS_DATAIN05; + input [63:0] TX_BYPASS_DATAIN06; + input [63:0] TX_BYPASS_DATAIN07; + input [63:0] TX_BYPASS_DATAIN08; + input [63:0] TX_BYPASS_DATAIN09; + input [63:0] TX_BYPASS_DATAIN10; + input [63:0] TX_BYPASS_DATAIN11; + input TX_BYPASS_ENAIN; + input [7:0] TX_BYPASS_GEARBOX_SEQIN; + input [3:0] TX_BYPASS_MFRAMER_STATEIN; + input [10:0] TX_CHANIN0; + input [10:0] TX_CHANIN1; + input [10:0] TX_CHANIN2; + input [10:0] TX_CHANIN3; + input [127:0] TX_DATAIN0; + input [127:0] TX_DATAIN1; + input [127:0] TX_DATAIN2; + input [127:0] TX_DATAIN3; + input TX_ENAIN0; + input TX_ENAIN1; + input TX_ENAIN2; + input TX_ENAIN3; + input TX_EOPIN0; + input TX_EOPIN1; + input TX_EOPIN2; + input TX_EOPIN3; + input TX_ERRIN0; + input TX_ERRIN1; + input TX_ERRIN2; + input TX_ERRIN3; + input [3:0] TX_MTYIN0; + input [3:0] TX_MTYIN1; + input [3:0] TX_MTYIN2; + input [3:0] TX_MTYIN3; + input TX_RESET; + input TX_SERDES_REFCLK; + input TX_SERDES_REFCLK_RESET; + input TX_SOPIN0; + input TX_SOPIN1; + input TX_SOPIN2; + input TX_SOPIN3; +endmodule + +module ILKNE4 (...); + parameter BYPASS = "FALSE"; + parameter [1:0] CTL_RX_BURSTMAX = 2'h3; + parameter [1:0] CTL_RX_CHAN_EXT = 2'h0; + parameter [3:0] CTL_RX_LAST_LANE = 4'hB; + parameter [15:0] CTL_RX_MFRAMELEN_MINUS1 = 16'h07FF; + parameter CTL_RX_PACKET_MODE = "FALSE"; + parameter [2:0] CTL_RX_RETRANS_MULT = 3'h0; + parameter [3:0] CTL_RX_RETRANS_RETRY = 4'h2; + parameter [15:0] CTL_RX_RETRANS_TIMER1 = 16'h0009; + parameter [15:0] CTL_RX_RETRANS_TIMER2 = 16'h0000; + parameter [11:0] CTL_RX_RETRANS_WDOG = 12'h000; + parameter [7:0] CTL_RX_RETRANS_WRAP_TIMER = 8'h00; + parameter CTL_TEST_MODE_PIN_CHAR = "FALSE"; + parameter [1:0] CTL_TX_BURSTMAX = 2'h3; + parameter [2:0] CTL_TX_BURSTSHORT = 3'h1; + parameter [1:0] CTL_TX_CHAN_EXT = 2'h0; + parameter CTL_TX_DISABLE_SKIPWORD = "FALSE"; + parameter [3:0] CTL_TX_FC_CALLEN = 4'hF; + parameter [3:0] CTL_TX_LAST_LANE = 4'hB; + parameter [15:0] CTL_TX_MFRAMELEN_MINUS1 = 16'h07FF; + parameter [13:0] CTL_TX_RETRANS_DEPTH = 14'h0800; + parameter [2:0] CTL_TX_RETRANS_MULT = 3'h0; + parameter [1:0] CTL_TX_RETRANS_RAM_BANKS = 2'h3; + parameter MODE = "TRUE"; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter TEST_MODE_PIN_CHAR = "FALSE"; + output [15:0] DRP_DO; + output DRP_RDY; + output [65:0] RX_BYPASS_DATAOUT00; + output [65:0] RX_BYPASS_DATAOUT01; + output [65:0] RX_BYPASS_DATAOUT02; + output [65:0] RX_BYPASS_DATAOUT03; + output [65:0] RX_BYPASS_DATAOUT04; + output [65:0] RX_BYPASS_DATAOUT05; + output [65:0] RX_BYPASS_DATAOUT06; + output [65:0] RX_BYPASS_DATAOUT07; + output [65:0] RX_BYPASS_DATAOUT08; + output [65:0] RX_BYPASS_DATAOUT09; + output [65:0] RX_BYPASS_DATAOUT10; + output [65:0] RX_BYPASS_DATAOUT11; + output [11:0] RX_BYPASS_ENAOUT; + output [11:0] RX_BYPASS_IS_AVAILOUT; + output [11:0] RX_BYPASS_IS_BADLYFRAMEDOUT; + output [11:0] RX_BYPASS_IS_OVERFLOWOUT; + output [11:0] RX_BYPASS_IS_SYNCEDOUT; + output [11:0] RX_BYPASS_IS_SYNCWORDOUT; + output [10:0] RX_CHANOUT0; + output [10:0] RX_CHANOUT1; + output [10:0] RX_CHANOUT2; + output [10:0] RX_CHANOUT3; + output [127:0] RX_DATAOUT0; + output [127:0] RX_DATAOUT1; + output [127:0] RX_DATAOUT2; + output [127:0] RX_DATAOUT3; + output RX_ENAOUT0; + output RX_ENAOUT1; + output RX_ENAOUT2; + output RX_ENAOUT3; + output RX_EOPOUT0; + output RX_EOPOUT1; + output RX_EOPOUT2; + output RX_EOPOUT3; + output RX_ERROUT0; + output RX_ERROUT1; + output RX_ERROUT2; + output RX_ERROUT3; + output [3:0] RX_MTYOUT0; + output [3:0] RX_MTYOUT1; + output [3:0] RX_MTYOUT2; + output [3:0] RX_MTYOUT3; + output RX_OVFOUT; + output RX_SOPOUT0; + output RX_SOPOUT1; + output RX_SOPOUT2; + output RX_SOPOUT3; + output STAT_RX_ALIGNED; + output STAT_RX_ALIGNED_ERR; + output [11:0] STAT_RX_BAD_TYPE_ERR; + output STAT_RX_BURSTMAX_ERR; + output STAT_RX_BURST_ERR; + output STAT_RX_CRC24_ERR; + output [11:0] STAT_RX_CRC32_ERR; + output [11:0] STAT_RX_CRC32_VALID; + output [11:0] STAT_RX_DESCRAM_ERR; + output [11:0] STAT_RX_DIAGWORD_INTFSTAT; + output [11:0] STAT_RX_DIAGWORD_LANESTAT; + output [255:0] STAT_RX_FC_STAT; + output [11:0] STAT_RX_FRAMING_ERR; + output STAT_RX_MEOP_ERR; + output [11:0] STAT_RX_MF_ERR; + output [11:0] STAT_RX_MF_LEN_ERR; + output [11:0] STAT_RX_MF_REPEAT_ERR; + output STAT_RX_MISALIGNED; + output STAT_RX_MSOP_ERR; + output [7:0] STAT_RX_MUBITS; + output STAT_RX_MUBITS_UPDATED; + output STAT_RX_OVERFLOW_ERR; + output STAT_RX_RETRANS_CRC24_ERR; + output STAT_RX_RETRANS_DISC; + output [15:0] STAT_RX_RETRANS_LATENCY; + output STAT_RX_RETRANS_REQ; + output STAT_RX_RETRANS_RETRY_ERR; + output [7:0] STAT_RX_RETRANS_SEQ; + output STAT_RX_RETRANS_SEQ_UPDATED; + output [2:0] STAT_RX_RETRANS_STATE; + output [4:0] STAT_RX_RETRANS_SUBSEQ; + output STAT_RX_RETRANS_WDOG_ERR; + output STAT_RX_RETRANS_WRAP_ERR; + output [11:0] STAT_RX_SYNCED; + output [11:0] STAT_RX_SYNCED_ERR; + output [11:0] STAT_RX_WORD_SYNC; + output STAT_TX_BURST_ERR; + output STAT_TX_ERRINJ_BITERR_DONE; + output STAT_TX_OVERFLOW_ERR; + output STAT_TX_RETRANS_BURST_ERR; + output STAT_TX_RETRANS_BUSY; + output STAT_TX_RETRANS_RAM_PERROUT; + output [8:0] STAT_TX_RETRANS_RAM_RADDR; + output STAT_TX_RETRANS_RAM_RD_B0; + output STAT_TX_RETRANS_RAM_RD_B1; + output STAT_TX_RETRANS_RAM_RD_B2; + output STAT_TX_RETRANS_RAM_RD_B3; + output [1:0] STAT_TX_RETRANS_RAM_RSEL; + output [8:0] STAT_TX_RETRANS_RAM_WADDR; + output [643:0] STAT_TX_RETRANS_RAM_WDATA; + output STAT_TX_RETRANS_RAM_WE_B0; + output STAT_TX_RETRANS_RAM_WE_B1; + output STAT_TX_RETRANS_RAM_WE_B2; + output STAT_TX_RETRANS_RAM_WE_B3; + output STAT_TX_UNDERFLOW_ERR; + output TX_OVFOUT; + output TX_RDYOUT; + output [63:0] TX_SERDES_DATA00; + output [63:0] TX_SERDES_DATA01; + output [63:0] TX_SERDES_DATA02; + output [63:0] TX_SERDES_DATA03; + output [63:0] TX_SERDES_DATA04; + output [63:0] TX_SERDES_DATA05; + output [63:0] TX_SERDES_DATA06; + output [63:0] TX_SERDES_DATA07; + output [63:0] TX_SERDES_DATA08; + output [63:0] TX_SERDES_DATA09; + output [63:0] TX_SERDES_DATA10; + output [63:0] TX_SERDES_DATA11; + input CORE_CLK; + input CTL_RX_FORCE_RESYNC; + input CTL_RX_RETRANS_ACK; + input CTL_RX_RETRANS_ENABLE; + input CTL_RX_RETRANS_ERRIN; + input CTL_RX_RETRANS_FORCE_REQ; + input CTL_RX_RETRANS_RESET; + input CTL_RX_RETRANS_RESET_MODE; + input CTL_TX_DIAGWORD_INTFSTAT; + input [11:0] CTL_TX_DIAGWORD_LANESTAT; + input CTL_TX_ENABLE; + input CTL_TX_ERRINJ_BITERR_GO; + input [3:0] CTL_TX_ERRINJ_BITERR_LANE; + input [255:0] CTL_TX_FC_STAT; + input [7:0] CTL_TX_MUBITS; + input CTL_TX_RETRANS_ENABLE; + input CTL_TX_RETRANS_RAM_PERRIN; + input [643:0] CTL_TX_RETRANS_RAM_RDATA; + input CTL_TX_RETRANS_REQ; + input CTL_TX_RETRANS_REQ_VALID; + input [11:0] CTL_TX_RLIM_DELTA; + input CTL_TX_RLIM_ENABLE; + input [7:0] CTL_TX_RLIM_INTV; + input [11:0] CTL_TX_RLIM_MAX; + input [9:0] DRP_ADDR; + input DRP_CLK; + input [15:0] DRP_DI; + input DRP_EN; + input DRP_WE; + input LBUS_CLK; + input RX_BYPASS_FORCE_REALIGNIN; + input RX_BYPASS_RDIN; + input RX_RESET; + input [11:0] RX_SERDES_CLK; + input [63:0] RX_SERDES_DATA00; + input [63:0] RX_SERDES_DATA01; + input [63:0] RX_SERDES_DATA02; + input [63:0] RX_SERDES_DATA03; + input [63:0] RX_SERDES_DATA04; + input [63:0] RX_SERDES_DATA05; + input [63:0] RX_SERDES_DATA06; + input [63:0] RX_SERDES_DATA07; + input [63:0] RX_SERDES_DATA08; + input [63:0] RX_SERDES_DATA09; + input [63:0] RX_SERDES_DATA10; + input [63:0] RX_SERDES_DATA11; + input [11:0] RX_SERDES_RESET; + input TX_BCTLIN0; + input TX_BCTLIN1; + input TX_BCTLIN2; + input TX_BCTLIN3; + input [11:0] TX_BYPASS_CTRLIN; + input [63:0] TX_BYPASS_DATAIN00; + input [63:0] TX_BYPASS_DATAIN01; + input [63:0] TX_BYPASS_DATAIN02; + input [63:0] TX_BYPASS_DATAIN03; + input [63:0] TX_BYPASS_DATAIN04; + input [63:0] TX_BYPASS_DATAIN05; + input [63:0] TX_BYPASS_DATAIN06; + input [63:0] TX_BYPASS_DATAIN07; + input [63:0] TX_BYPASS_DATAIN08; + input [63:0] TX_BYPASS_DATAIN09; + input [63:0] TX_BYPASS_DATAIN10; + input [63:0] TX_BYPASS_DATAIN11; + input TX_BYPASS_ENAIN; + input [7:0] TX_BYPASS_GEARBOX_SEQIN; + input [3:0] TX_BYPASS_MFRAMER_STATEIN; + input [10:0] TX_CHANIN0; + input [10:0] TX_CHANIN1; + input [10:0] TX_CHANIN2; + input [10:0] TX_CHANIN3; + input [127:0] TX_DATAIN0; + input [127:0] TX_DATAIN1; + input [127:0] TX_DATAIN2; + input [127:0] TX_DATAIN3; + input TX_ENAIN0; + input TX_ENAIN1; + input TX_ENAIN2; + input TX_ENAIN3; + input TX_EOPIN0; + input TX_EOPIN1; + input TX_EOPIN2; + input TX_EOPIN3; + input TX_ERRIN0; + input TX_ERRIN1; + input TX_ERRIN2; + input TX_ERRIN3; + input [3:0] TX_MTYIN0; + input [3:0] TX_MTYIN1; + input [3:0] TX_MTYIN2; + input [3:0] TX_MTYIN3; + input TX_RESET; + input TX_SERDES_REFCLK; + input TX_SERDES_REFCLK_RESET; + input TX_SOPIN0; + input TX_SOPIN1; + input TX_SOPIN2; + input TX_SOPIN3; +endmodule + +(* keep *) +module VCU (...); + parameter integer CORECLKREQ = 667; + parameter integer DECHORRESOLUTION = 3840; + parameter DECODERCHROMAFORMAT = "4_2_2"; + parameter DECODERCODING = "H.265"; + parameter integer DECODERCOLORDEPTH = 10; + parameter integer DECODERNUMCORES = 2; + parameter integer DECVERTRESOLUTION = 2160; + parameter ENABLEDECODER = "TRUE"; + parameter ENABLEENCODER = "TRUE"; + parameter integer ENCHORRESOLUTION = 3840; + parameter ENCODERCHROMAFORMAT = "4_2_2"; + parameter ENCODERCODING = "H.265"; + parameter integer ENCODERCOLORDEPTH = 10; + parameter integer ENCODERNUMCORES = 4; + parameter integer ENCVERTRESOLUTION = 2160; + output VCUPLARREADYAXILITEAPB; + output VCUPLAWREADYAXILITEAPB; + output [1:0] VCUPLBRESPAXILITEAPB; + output VCUPLBVALIDAXILITEAPB; + output VCUPLCORESTATUSCLKPLL; + output [43:0] VCUPLDECARADDR0; + output [43:0] VCUPLDECARADDR1; + output [1:0] VCUPLDECARBURST0; + output [1:0] VCUPLDECARBURST1; + output [3:0] VCUPLDECARCACHE0; + output [3:0] VCUPLDECARCACHE1; + output [3:0] VCUPLDECARID0; + output [3:0] VCUPLDECARID1; + output [7:0] VCUPLDECARLEN0; + output [7:0] VCUPLDECARLEN1; + output VCUPLDECARPROT0; + output VCUPLDECARPROT1; + output [3:0] VCUPLDECARQOS0; + output [3:0] VCUPLDECARQOS1; + output [2:0] VCUPLDECARSIZE0; + output [2:0] VCUPLDECARSIZE1; + output VCUPLDECARVALID0; + output VCUPLDECARVALID1; + output [43:0] VCUPLDECAWADDR0; + output [43:0] VCUPLDECAWADDR1; + output [1:0] VCUPLDECAWBURST0; + output [1:0] VCUPLDECAWBURST1; + output [3:0] VCUPLDECAWCACHE0; + output [3:0] VCUPLDECAWCACHE1; + output [3:0] VCUPLDECAWID0; + output [3:0] VCUPLDECAWID1; + output [7:0] VCUPLDECAWLEN0; + output [7:0] VCUPLDECAWLEN1; + output VCUPLDECAWPROT0; + output VCUPLDECAWPROT1; + output [3:0] VCUPLDECAWQOS0; + output [3:0] VCUPLDECAWQOS1; + output [2:0] VCUPLDECAWSIZE0; + output [2:0] VCUPLDECAWSIZE1; + output VCUPLDECAWVALID0; + output VCUPLDECAWVALID1; + output VCUPLDECBREADY0; + output VCUPLDECBREADY1; + output VCUPLDECRREADY0; + output VCUPLDECRREADY1; + output [127:0] VCUPLDECWDATA0; + output [127:0] VCUPLDECWDATA1; + output VCUPLDECWLAST0; + output VCUPLDECWLAST1; + output VCUPLDECWVALID0; + output VCUPLDECWVALID1; + output [16:0] VCUPLENCALL2CADDR; + output VCUPLENCALL2CRVALID; + output [319:0] VCUPLENCALL2CWDATA; + output VCUPLENCALL2CWVALID; + output [43:0] VCUPLENCARADDR0; + output [43:0] VCUPLENCARADDR1; + output [1:0] VCUPLENCARBURST0; + output [1:0] VCUPLENCARBURST1; + output [3:0] VCUPLENCARCACHE0; + output [3:0] VCUPLENCARCACHE1; + output [3:0] VCUPLENCARID0; + output [3:0] VCUPLENCARID1; + output [7:0] VCUPLENCARLEN0; + output [7:0] VCUPLENCARLEN1; + output VCUPLENCARPROT0; + output VCUPLENCARPROT1; + output [3:0] VCUPLENCARQOS0; + output [3:0] VCUPLENCARQOS1; + output [2:0] VCUPLENCARSIZE0; + output [2:0] VCUPLENCARSIZE1; + output VCUPLENCARVALID0; + output VCUPLENCARVALID1; + output [43:0] VCUPLENCAWADDR0; + output [43:0] VCUPLENCAWADDR1; + output [1:0] VCUPLENCAWBURST0; + output [1:0] VCUPLENCAWBURST1; + output [3:0] VCUPLENCAWCACHE0; + output [3:0] VCUPLENCAWCACHE1; + output [3:0] VCUPLENCAWID0; + output [3:0] VCUPLENCAWID1; + output [7:0] VCUPLENCAWLEN0; + output [7:0] VCUPLENCAWLEN1; + output VCUPLENCAWPROT0; + output VCUPLENCAWPROT1; + output [3:0] VCUPLENCAWQOS0; + output [3:0] VCUPLENCAWQOS1; + output [2:0] VCUPLENCAWSIZE0; + output [2:0] VCUPLENCAWSIZE1; + output VCUPLENCAWVALID0; + output VCUPLENCAWVALID1; + output VCUPLENCBREADY0; + output VCUPLENCBREADY1; + output VCUPLENCRREADY0; + output VCUPLENCRREADY1; + output [127:0] VCUPLENCWDATA0; + output [127:0] VCUPLENCWDATA1; + output VCUPLENCWLAST0; + output VCUPLENCWLAST1; + output VCUPLENCWVALID0; + output VCUPLENCWVALID1; + output [43:0] VCUPLMCUMAXIICDCARADDR; + output [1:0] VCUPLMCUMAXIICDCARBURST; + output [3:0] VCUPLMCUMAXIICDCARCACHE; + output [2:0] VCUPLMCUMAXIICDCARID; + output [7:0] VCUPLMCUMAXIICDCARLEN; + output VCUPLMCUMAXIICDCARLOCK; + output [2:0] VCUPLMCUMAXIICDCARPROT; + output [3:0] VCUPLMCUMAXIICDCARQOS; + output [2:0] VCUPLMCUMAXIICDCARSIZE; + output VCUPLMCUMAXIICDCARVALID; + output [43:0] VCUPLMCUMAXIICDCAWADDR; + output [1:0] VCUPLMCUMAXIICDCAWBURST; + output [3:0] VCUPLMCUMAXIICDCAWCACHE; + output [2:0] VCUPLMCUMAXIICDCAWID; + output [7:0] VCUPLMCUMAXIICDCAWLEN; + output VCUPLMCUMAXIICDCAWLOCK; + output [2:0] VCUPLMCUMAXIICDCAWPROT; + output [3:0] VCUPLMCUMAXIICDCAWQOS; + output [2:0] VCUPLMCUMAXIICDCAWSIZE; + output VCUPLMCUMAXIICDCAWVALID; + output VCUPLMCUMAXIICDCBREADY; + output VCUPLMCUMAXIICDCRREADY; + output [31:0] VCUPLMCUMAXIICDCWDATA; + output VCUPLMCUMAXIICDCWLAST; + output [3:0] VCUPLMCUMAXIICDCWSTRB; + output VCUPLMCUMAXIICDCWVALID; + output VCUPLMCUSTATUSCLKPLL; + output VCUPLPINTREQ; + output VCUPLPLLSTATUSPLLLOCK; + output VCUPLPWRSUPPLYSTATUSVCCAUX; + output VCUPLPWRSUPPLYSTATUSVCUINT; + output [31:0] VCUPLRDATAAXILITEAPB; + output [1:0] VCUPLRRESPAXILITEAPB; + output VCUPLRVALIDAXILITEAPB; + output VCUPLWREADYAXILITEAPB; + input INITPLVCUGASKETCLAMPCONTROLLVLSHVCCINTD; + input [19:0] PLVCUARADDRAXILITEAPB; + input [2:0] PLVCUARPROTAXILITEAPB; + input PLVCUARVALIDAXILITEAPB; + input [19:0] PLVCUAWADDRAXILITEAPB; + input [2:0] PLVCUAWPROTAXILITEAPB; + input PLVCUAWVALIDAXILITEAPB; + input PLVCUAXIDECCLK; + input PLVCUAXIENCCLK; + input PLVCUAXILITECLK; + input PLVCUAXIMCUCLK; + input PLVCUBREADYAXILITEAPB; + input PLVCUCORECLK; + input PLVCUDECARREADY0; + input PLVCUDECARREADY1; + input PLVCUDECAWREADY0; + input PLVCUDECAWREADY1; + input [3:0] PLVCUDECBID0; + input [3:0] PLVCUDECBID1; + input [1:0] PLVCUDECBRESP0; + input [1:0] PLVCUDECBRESP1; + input PLVCUDECBVALID0; + input PLVCUDECBVALID1; + input [127:0] PLVCUDECRDATA0; + input [127:0] PLVCUDECRDATA1; + input [3:0] PLVCUDECRID0; + input [3:0] PLVCUDECRID1; + input PLVCUDECRLAST0; + input PLVCUDECRLAST1; + input [1:0] PLVCUDECRRESP0; + input [1:0] PLVCUDECRRESP1; + input PLVCUDECRVALID0; + input PLVCUDECRVALID1; + input PLVCUDECWREADY0; + input PLVCUDECWREADY1; + input [319:0] PLVCUENCALL2CRDATA; + input PLVCUENCALL2CRREADY; + input PLVCUENCARREADY0; + input PLVCUENCARREADY1; + input PLVCUENCAWREADY0; + input PLVCUENCAWREADY1; + input [3:0] PLVCUENCBID0; + input [3:0] PLVCUENCBID1; + input [1:0] PLVCUENCBRESP0; + input [1:0] PLVCUENCBRESP1; + input PLVCUENCBVALID0; + input PLVCUENCBVALID1; + input PLVCUENCL2CCLK; + input [127:0] PLVCUENCRDATA0; + input [127:0] PLVCUENCRDATA1; + input [3:0] PLVCUENCRID0; + input [3:0] PLVCUENCRID1; + input PLVCUENCRLAST0; + input PLVCUENCRLAST1; + input [1:0] PLVCUENCRRESP0; + input [1:0] PLVCUENCRRESP1; + input PLVCUENCRVALID0; + input PLVCUENCRVALID1; + input PLVCUENCWREADY0; + input PLVCUENCWREADY1; + input PLVCUMCUCLK; + input PLVCUMCUMAXIICDCARREADY; + input PLVCUMCUMAXIICDCAWREADY; + input [2:0] PLVCUMCUMAXIICDCBID; + input [1:0] PLVCUMCUMAXIICDCBRESP; + input PLVCUMCUMAXIICDCBVALID; + input [31:0] PLVCUMCUMAXIICDCRDATA; + input [2:0] PLVCUMCUMAXIICDCRID; + input PLVCUMCUMAXIICDCRLAST; + input [1:0] PLVCUMCUMAXIICDCRRESP; + input PLVCUMCUMAXIICDCRVALID; + input PLVCUMCUMAXIICDCWREADY; + input PLVCUPLLREFCLKPL; + input PLVCURAWRSTN; + input PLVCURREADYAXILITEAPB; + input [31:0] PLVCUWDATAAXILITEAPB; + input [3:0] PLVCUWSTRBAXILITEAPB; + input PLVCUWVALIDAXILITEAPB; +endmodule + +module FE (...); + parameter MODE = "TURBO_DECODE"; + parameter real PHYSICAL_UTILIZATION = 100.00; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter STANDARD = "LTE"; + parameter real THROUGHPUT_UTILIZATION = 100.00; + output [399:0] DEBUG_DOUT; + output DEBUG_PHASE; + output INTERRUPT; + output [511:0] M_AXIS_DOUT_TDATA; + output M_AXIS_DOUT_TLAST; + output M_AXIS_DOUT_TVALID; + output [31:0] M_AXIS_STATUS_TDATA; + output M_AXIS_STATUS_TVALID; + output [15:0] SPARE_OUT; + output S_AXIS_CTRL_TREADY; + output S_AXIS_DIN_TREADY; + output S_AXIS_DIN_WORDS_TREADY; + output S_AXIS_DOUT_WORDS_TREADY; + output S_AXI_ARREADY; + output S_AXI_AWREADY; + output S_AXI_BVALID; + output [31:0] S_AXI_RDATA; + output S_AXI_RVALID; + output S_AXI_WREADY; + input CORE_CLK; + input DEBUG_CLK_EN; + input DEBUG_EN; + input [3:0] DEBUG_SEL_IN; + input M_AXIS_DOUT_ACLK; + input M_AXIS_DOUT_TREADY; + input M_AXIS_STATUS_ACLK; + input M_AXIS_STATUS_TREADY; + input RESET_N; + input [15:0] SPARE_IN; + input S_AXIS_CTRL_ACLK; + input [31:0] S_AXIS_CTRL_TDATA; + input S_AXIS_CTRL_TVALID; + input S_AXIS_DIN_ACLK; + input [511:0] S_AXIS_DIN_TDATA; + input S_AXIS_DIN_TLAST; + input S_AXIS_DIN_TVALID; + input S_AXIS_DIN_WORDS_ACLK; + input [31:0] S_AXIS_DIN_WORDS_TDATA; + input S_AXIS_DIN_WORDS_TLAST; + input S_AXIS_DIN_WORDS_TVALID; + input S_AXIS_DOUT_WORDS_ACLK; + input [31:0] S_AXIS_DOUT_WORDS_TDATA; + input S_AXIS_DOUT_WORDS_TLAST; + input S_AXIS_DOUT_WORDS_TVALID; + input S_AXI_ACLK; + input [17:0] S_AXI_ARADDR; + input S_AXI_ARVALID; + input [17:0] S_AXI_AWADDR; + input S_AXI_AWVALID; + input S_AXI_BREADY; + input S_AXI_RREADY; + input [31:0] S_AXI_WDATA; + input S_AXI_WVALID; +endmodule + diff --git a/techlibs/analogdevices/dsp_map.v b/techlibs/analogdevices/dsp_map.v new file mode 100644 index 000000000..58df977ec --- /dev/null +++ b/techlibs/analogdevices/dsp_map.v @@ -0,0 +1,50 @@ +module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + wire [47:0] P_48; + DSP48E1 #( + // Disable all registers + .ACASCREG(0), + .ADREG(0), + .A_INPUT("DIRECT"), + .ALUMODEREG(0), + .AREG(0), + .BCASCREG(0), + .B_INPUT("DIRECT"), + .BREG(0), + .CARRYINREG(0), + .CARRYINSELREG(0), + .CREG(0), + .DREG(0), + .INMODEREG(0), + .MREG(0), + .OPMODEREG(0), + .PREG(0), + .USE_MULT("MULTIPLY"), + .USE_SIMD("ONE48"), + .USE_DPORT("FALSE") + ) _TECHMAP_REPLACE_ ( + //Data path + .A({{5{A[24]}}, A}), + .B(B), + .C(48'b0), + .D(25'b0), + .CARRYIN(1'b0), + .P(P_48), + + .INMODE(5'b00000), + .ALUMODE(4'b0000), + .OPMODE(7'b000101), + .CARRYINSEL(3'b000), + + .ACIN(30'b0), + .BCIN(18'b0), + .PCIN(48'b0), + .CARRYIN(1'b0) + ); + assign Y = P_48; +endmodule diff --git a/techlibs/analogdevices/ff_map.v b/techlibs/analogdevices/ff_map.v new file mode 100644 index 000000000..2079fd99a --- /dev/null +++ b/techlibs/analogdevices/ff_map.v @@ -0,0 +1,120 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +`ifndef _NO_FFS + +// Async reset, enable. + +module \$_DFFE_NP0P_ (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$_DFFE_PP0P_ (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +module \$_DFFE_NP1P_ (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE(R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$_DFFE_PP1P_ (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE(R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +// Async set and reset, enable. + +module \$_DFFSRE_NPPP_ (input D, C, E, S, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDCPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R), .PRE(S)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$_DFFSRE_PPPP_ (input D, C, E, S, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDCPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R), .PRE(S)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +// Sync reset, enable. + +module \$_SDFFE_NP0P_ (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$_SDFFE_PP0P_ (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +module \$_SDFFE_NP1P_ (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$_SDFFE_PP1P_ (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +// Latches with reset. + +module \$_DLATCH_NP0_ (input E, R, D, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + LDCE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$_DLATCH_PP0_ (input E, R, D, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + LDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$_DLATCH_NP1_ (input E, R, D, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + LDPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .PRE(R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$_DLATCH_PP1_ (input E, R, D, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + LDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .PRE(R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +// Latches with set and reset. + +module \$_DLATCH_NPP_ (input E, S, R, D, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + LDCPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R), .PRE(S)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$_DLATCH_PPP_ (input E, S, R, D, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + LDCPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R), .PRE(S)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +`endif + diff --git a/techlibs/analogdevices/lut_map.v b/techlibs/analogdevices/lut_map.v new file mode 100644 index 000000000..d63bd7edb --- /dev/null +++ b/techlibs/analogdevices/lut_map.v @@ -0,0 +1,83 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +// ============================================================================ +// LUT mapping + +`ifndef _NO_LUTS + +module \$lut (A, Y); + parameter WIDTH = 0; + parameter LUT = 0; + + (* force_downto *) + input [WIDTH-1:0] A; + output Y; + + generate + if (WIDTH == 1) begin + if (LUT == 2'b01) begin + INV _TECHMAP_REPLACE_ (.O(Y), .I(A[0])); + end else begin + LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), + .I0(A[0])); + end + end else + if (WIDTH == 2) begin + LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), + .I0(A[0]), .I1(A[1])); + end else + if (WIDTH == 3) begin + LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), + .I0(A[0]), .I1(A[1]), .I2(A[2])); + end else + if (WIDTH == 4) begin + LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), + .I0(A[0]), .I1(A[1]), .I2(A[2]), + .I3(A[3])); + end else + if (WIDTH == 5) begin + LUT5 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), + .I0(A[0]), .I1(A[1]), .I2(A[2]), + .I3(A[3]), .I4(A[4])); + end else + if (WIDTH == 6) begin + LUT6 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), + .I0(A[0]), .I1(A[1]), .I2(A[2]), + .I3(A[3]), .I4(A[4]), .I5(A[5])); + end else + if (WIDTH == 7) begin + wire f0, f1; + \$lut #(.LUT(LUT[ 63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0)); + \$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1)); + LUTMUX7 mux7(.I0(f0), .I1(f1), .S(A[6]), .O(Y)); + end else + if (WIDTH == 8) begin + wire f0, f1; + \$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0)); + \$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1)); + LUTMUX8 mux8(.I0(f0), .I1(f1), .S(A[7]), .O(Y)); + end else begin + wire _TECHMAP_FAIL_ = 1; + end + endgenerate +endmodule + +`endif + diff --git a/techlibs/analogdevices/lutrams.txt b/techlibs/analogdevices/lutrams.txt new file mode 100644 index 000000000..882cc5722 --- /dev/null +++ b/techlibs/analogdevices/lutrams.txt @@ -0,0 +1,78 @@ +# LUT RAMs for Virtex 5, Virtex 6, Spartan 6, Series 7. +# The corresponding mapping file is lutrams_xc5v_map.v + +# Single-port RAMs. + +ram distributed $__ANALOGDEVICES_LUTRAM_SP_ { + cost 8; + widthscale; + option "ABITS" 5 { + abits 5; + widths 8 global; + } + option "ABITS" 6 { + abits 6; + widths 4 global; + } + option "ABITS" 7 { + abits 7; + widths 2 global; + } + option "ABITS" 8 { + abits 8; + widths 1 global; + } + init no_undef; + prune_rom; + port arsw "RW" { + clock posedge; + } +} + +# Dual-port RAMs. + +ram distributed $__ANALOGDEVICES_LUTRAM_DP_ { + cost 8; + widthscale; + option "ABITS" 5 { + abits 5; + widths 4 global; + } + option "ABITS" 6 { + abits 6; + widths 2 global; + } + option "ABITS" 7 { + abits 7; + widths 1 global; + } + init no_undef; + prune_rom; + port arsw "RW" { + clock posedge; + } + port ar "R" { + } +} + +# Simple dual port RAMs. + +ram distributed $__ANALOGDEVICES_LUTRAM_SDP_ { + cost 8; + widthscale 7; + option "ABITS" 5 { + abits 5; + widths 6 global; + } + option "ABITS" 6 { + abits 6; + widths 3 global; + } + init no_undef; + prune_rom; + port sw "W" { + clock posedge; + } + port ar "R" { + } +} diff --git a/techlibs/analogdevices/lutrams_map.v b/techlibs/analogdevices/lutrams_map.v new file mode 100644 index 000000000..2142fdf7c --- /dev/null +++ b/techlibs/analogdevices/lutrams_map.v @@ -0,0 +1,459 @@ +// LUT RAMs for Virtex 5, Virtex 6, Spartan 6, Series 7, Ultrascale. +// The definitions are in lutrams_xc5v.txt. + + +module $__ANALOGDEVICES_LUTRAM_SP_ (...); + +parameter INIT = 0; +parameter OPTION_ABITS = 5; +parameter WIDTH = 8; +parameter BITS_USED = 0; + +output [WIDTH-1:0] PORT_RW_RD_DATA; +input [WIDTH-1:0] PORT_RW_WR_DATA; +input [OPTION_ABITS-1:0] PORT_RW_ADDR; +input PORT_RW_WR_EN; +input PORT_RW_CLK; + +function [(1 << OPTION_ABITS)-1:0] init_slice; + input integer idx; + integer i; + for (i = 0; i < (1 << OPTION_ABITS); i = i + 1) + init_slice[i] = INIT[i * WIDTH + idx]; +endfunction + +function [(2 << OPTION_ABITS)-1:0] init_slice2; + input integer idx; + integer i; + for (i = 0; i < (1 << OPTION_ABITS); i = i + 1) + init_slice2[2 * i +: 2] = INIT[i * WIDTH + idx * 2 +: 2]; +endfunction + +generate +case(OPTION_ABITS) +5: if (WIDTH == 8) + RAM32M + #( + .INIT_D(init_slice2(0)), + .INIT_C(init_slice2(1)), + .INIT_B(init_slice2(2)), + .INIT_A(init_slice2(3)), + ) + _TECHMAP_REPLACE_ + ( + .DOA(PORT_RW_RD_DATA[7:6]), + .DOB(PORT_RW_RD_DATA[5:4]), + .DOC(PORT_RW_RD_DATA[3:2]), + .DOD(PORT_RW_RD_DATA[1:0]), + .DIA(PORT_RW_WR_DATA[7:6]), + .DIB(PORT_RW_WR_DATA[5:4]), + .DIC(PORT_RW_WR_DATA[3:2]), + .DID(PORT_RW_WR_DATA[1:0]), + .ADDRA(PORT_RW_ADDR), + .ADDRB(PORT_RW_ADDR), + .ADDRC(PORT_RW_ADDR), + .ADDRD(PORT_RW_ADDR), + .WE(PORT_RW_WR_EN), + .WCLK(PORT_RW_CLK), + ); +else + RAM32M16 + #( + .INIT_H(init_slice2(0)), + .INIT_G(init_slice2(1)), + .INIT_F(init_slice2(2)), + .INIT_E(init_slice2(3)), + .INIT_D(init_slice2(4)), + .INIT_C(init_slice2(5)), + .INIT_B(init_slice2(6)), + .INIT_A(init_slice2(7)), + ) + _TECHMAP_REPLACE_ + ( + .DOA(PORT_RW_RD_DATA[15:14]), + .DOB(PORT_RW_RD_DATA[13:12]), + .DOC(PORT_RW_RD_DATA[11:10]), + .DOD(PORT_RW_RD_DATA[9:8]), + .DOE(PORT_RW_RD_DATA[7:6]), + .DOF(PORT_RW_RD_DATA[5:4]), + .DOG(PORT_RW_RD_DATA[3:2]), + .DOH(PORT_RW_RD_DATA[1:0]), + .DIA(PORT_RW_WR_DATA[15:14]), + .DIB(PORT_RW_WR_DATA[13:12]), + .DIC(PORT_RW_WR_DATA[11:10]), + .DID(PORT_RW_WR_DATA[9:8]), + .DIE(PORT_RW_WR_DATA[7:6]), + .DIF(PORT_RW_WR_DATA[5:4]), + .DIG(PORT_RW_WR_DATA[3:2]), + .DIH(PORT_RW_WR_DATA[1:0]), + .ADDRA(PORT_RW_ADDR), + .ADDRB(PORT_RW_ADDR), + .ADDRC(PORT_RW_ADDR), + .ADDRD(PORT_RW_ADDR), + .ADDRE(PORT_RW_ADDR), + .ADDRF(PORT_RW_ADDR), + .ADDRG(PORT_RW_ADDR), + .ADDRH(PORT_RW_ADDR), + .WE(PORT_RW_WR_EN), + .WCLK(PORT_RW_CLK), + ); +6: begin + genvar i; + for (i = 0; i < WIDTH; i = i + 1) + if (BITS_USED[i]) + RAM64X1S + #( + .INIT(init_slice(i)), + ) + slice + ( + .A0(PORT_RW_ADDR[0]), + .A1(PORT_RW_ADDR[1]), + .A2(PORT_RW_ADDR[2]), + .A3(PORT_RW_ADDR[3]), + .A4(PORT_RW_ADDR[4]), + .A5(PORT_RW_ADDR[5]), + .D(PORT_RW_WR_DATA[i]), + .O(PORT_RW_RD_DATA[i]), + .WE(PORT_RW_WR_EN), + .WCLK(PORT_RW_CLK), + ); +end +default: + $error("invalid OPTION_ABITS/WIDTH combination"); +endcase +endgenerate + +endmodule + + +module $__ANALOGDEVICES_LUTRAM_DP_ (...); + +parameter INIT = 0; +parameter OPTION_ABITS = 5; +parameter WIDTH = 4; +parameter BITS_USED = 0; + +output [WIDTH-1:0] PORT_RW_RD_DATA; +input [WIDTH-1:0] PORT_RW_WR_DATA; +input [OPTION_ABITS-1:0] PORT_RW_ADDR; +input PORT_RW_WR_EN; +input PORT_RW_CLK; + +output [WIDTH-1:0] PORT_R_RD_DATA; +input [OPTION_ABITS-1:0] PORT_R_ADDR; + +function [(1 << OPTION_ABITS)-1:0] init_slice; + input integer idx; + integer i; + for (i = 0; i < (1 << OPTION_ABITS); i = i + 1) + init_slice[i] = INIT[i * WIDTH + idx]; +endfunction + +function [(2 << OPTION_ABITS)-1:0] init_slice2; + input integer idx; + integer i; + for (i = 0; i < (1 << OPTION_ABITS); i = i + 1) + init_slice2[2 * i +: 2] = INIT[i * WIDTH + idx * 2 +: 2]; +endfunction + +generate +case (OPTION_ABITS) +5: if (WIDTH == 4) + RAM32M + #( + .INIT_D(init_slice2(0)), + .INIT_C(init_slice2(0)), + .INIT_B(init_slice2(1)), + .INIT_A(init_slice2(1)), + ) + _TECHMAP_REPLACE_ + ( + .DOA(PORT_R_RD_DATA[3:2]), + .DOB(PORT_RW_RD_DATA[3:2]), + .DOC(PORT_R_RD_DATA[1:0]), + .DOD(PORT_RW_RD_DATA[1:0]), + .DIA(PORT_RW_WR_DATA[3:2]), + .DIB(PORT_RW_WR_DATA[3:2]), + .DIC(PORT_RW_WR_DATA[1:0]), + .DID(PORT_RW_WR_DATA[1:0]), + .ADDRA(PORT_R_ADDR), + .ADDRB(PORT_RW_ADDR), + .ADDRC(PORT_R_ADDR), + .ADDRD(PORT_RW_ADDR), + .WE(PORT_RW_WR_EN), + .WCLK(PORT_RW_CLK), + ); +else + RAM32M16 + #( + .INIT_H(init_slice2(0)), + .INIT_G(init_slice2(0)), + .INIT_F(init_slice2(1)), + .INIT_E(init_slice2(1)), + .INIT_D(init_slice2(2)), + .INIT_C(init_slice2(2)), + .INIT_B(init_slice2(3)), + .INIT_A(init_slice2(3)), + ) + _TECHMAP_REPLACE_ + ( + .DOA(PORT_R_RD_DATA[7:6]), + .DOB(PORT_RW_RD_DATA[7:6]), + .DOC(PORT_R_RD_DATA[5:4]), + .DOD(PORT_RW_RD_DATA[5:4]), + .DOE(PORT_R_RD_DATA[3:2]), + .DOF(PORT_RW_RD_DATA[3:2]), + .DOG(PORT_R_RD_DATA[1:0]), + .DOH(PORT_RW_RD_DATA[1:0]), + .DIA(PORT_RW_WR_DATA[7:6]), + .DIB(PORT_RW_WR_DATA[7:6]), + .DIC(PORT_RW_WR_DATA[5:4]), + .DID(PORT_RW_WR_DATA[5:4]), + .DIE(PORT_RW_WR_DATA[3:2]), + .DIF(PORT_RW_WR_DATA[3:2]), + .DIG(PORT_RW_WR_DATA[1:0]), + .DIH(PORT_RW_WR_DATA[1:0]), + .ADDRA(PORT_R_ADDR), + .ADDRB(PORT_RW_ADDR), + .ADDRC(PORT_R_ADDR), + .ADDRD(PORT_RW_ADDR), + .ADDRE(PORT_R_ADDR), + .ADDRF(PORT_RW_ADDR), + .ADDRG(PORT_R_ADDR), + .ADDRH(PORT_RW_ADDR), + .WE(PORT_RW_WR_EN), + .WCLK(PORT_RW_CLK), + ); +6: begin + genvar i; + for (i = 0; i < WIDTH; i = i + 1) + if (BITS_USED[i]) + RAM64X1D + #( + .INIT(init_slice(i)), + ) + slice + ( + .A0(PORT_RW_ADDR[0]), + .A1(PORT_RW_ADDR[1]), + .A2(PORT_RW_ADDR[2]), + .A3(PORT_RW_ADDR[3]), + .A4(PORT_RW_ADDR[4]), + .A5(PORT_RW_ADDR[5]), + .D(PORT_RW_WR_DATA[i]), + .SPO(PORT_RW_RD_DATA[i]), + .WE(PORT_RW_WR_EN), + .WCLK(PORT_RW_CLK), + .DPRA0(PORT_R_ADDR[0]), + .DPRA1(PORT_R_ADDR[1]), + .DPRA2(PORT_R_ADDR[2]), + .DPRA3(PORT_R_ADDR[3]), + .DPRA4(PORT_R_ADDR[4]), + .DPRA5(PORT_R_ADDR[5]), + .DPO(PORT_R_RD_DATA[i]), + ); +end +7: begin + genvar i; + for (i = 0; i < WIDTH; i = i + 1) + if (BITS_USED[i]) + RAM128X1D + #( + .INIT(init_slice(i)), + ) + slice + ( + .A(PORT_RW_ADDR), + .D(PORT_RW_WR_DATA[i]), + .SPO(PORT_RW_RD_DATA[i]), + .WE(PORT_RW_WR_EN), + .WCLK(PORT_RW_CLK), + .DPRA(PORT_R_ADDR), + .DPO(PORT_R_RD_DATA[i]), + ); +end +8: begin + genvar i; + for (i = 0; i < WIDTH; i = i + 1) + if (BITS_USED[i]) + RAM256X1D + #( + .INIT(init_slice(i)), + ) + slice + ( + .A(PORT_RW_ADDR), + .D(PORT_RW_WR_DATA[i]), + .SPO(PORT_RW_RD_DATA[i]), + .WE(PORT_RW_WR_EN), + .WCLK(PORT_RW_CLK), + .DPRA(PORT_R_ADDR), + .DPO(PORT_R_RD_DATA[i]), + ); +end +default: + $error("invalid OPTION_ABITS/WIDTH combination"); +endcase +endgenerate + +endmodule + + +module $__ANALOGDEVICES_LUTRAM_SDP_ (...); + +parameter INIT = 0; +parameter OPTION_ABITS = 5; +parameter WIDTH = 6; +parameter BITS_USED = 0; + +input [WIDTH-1:0] PORT_W_WR_DATA; +input [OPTION_ABITS-1:0] PORT_W_ADDR; +input PORT_W_WR_EN; +input PORT_W_CLK; + +output [WIDTH-1:0] PORT_R_RD_DATA; +input [OPTION_ABITS-1:0] PORT_R_ADDR; + +function [(1 << OPTION_ABITS)-1:0] init_slice; + input integer idx; + integer i; + for (i = 0; i < (1 << OPTION_ABITS); i = i + 1) + init_slice[i] = INIT[i * WIDTH + idx]; +endfunction + +function [(2 << OPTION_ABITS)-1:0] init_slice2; + input integer idx; + integer i; + for (i = 0; i < (1 << OPTION_ABITS); i = i + 1) + init_slice2[2 * i +: 2] = INIT[i * WIDTH + idx * 2 +: 2]; +endfunction + +generate +case (OPTION_ABITS) +5: if (WIDTH == 6) + RAM32M + #( + .INIT_C(init_slice2(0)), + .INIT_B(init_slice2(1)), + .INIT_A(init_slice2(2)), + ) + _TECHMAP_REPLACE_ + ( + .DOA(PORT_R_RD_DATA[5:4]), + .DOB(PORT_R_RD_DATA[3:2]), + .DOC(PORT_R_RD_DATA[1:0]), + .DIA(PORT_W_WR_DATA[5:4]), + .DIB(PORT_W_WR_DATA[3:2]), + .DIC(PORT_W_WR_DATA[1:0]), + .ADDRA(PORT_R_ADDR), + .ADDRB(PORT_R_ADDR), + .ADDRC(PORT_R_ADDR), + .ADDRD(PORT_W_ADDR), + .WE(PORT_W_WR_EN), + .WCLK(PORT_W_CLK), + ); +else + RAM32M16 + #( + .INIT_G(init_slice2(0)), + .INIT_F(init_slice2(1)), + .INIT_E(init_slice2(2)), + .INIT_D(init_slice2(3)), + .INIT_C(init_slice2(4)), + .INIT_B(init_slice2(5)), + .INIT_A(init_slice2(6)), + ) + _TECHMAP_REPLACE_ + ( + .DOA(PORT_R_RD_DATA[13:12]), + .DOB(PORT_R_RD_DATA[11:10]), + .DOC(PORT_R_RD_DATA[9:8]), + .DOD(PORT_R_RD_DATA[7:6]), + .DOE(PORT_R_RD_DATA[5:4]), + .DOF(PORT_R_RD_DATA[3:2]), + .DOG(PORT_R_RD_DATA[1:0]), + .DIA(PORT_W_WR_DATA[13:12]), + .DIB(PORT_W_WR_DATA[11:10]), + .DIC(PORT_W_WR_DATA[9:8]), + .DID(PORT_W_WR_DATA[7:6]), + .DIE(PORT_W_WR_DATA[5:4]), + .DIF(PORT_W_WR_DATA[3:2]), + .DIG(PORT_W_WR_DATA[1:0]), + .ADDRA(PORT_R_ADDR), + .ADDRB(PORT_R_ADDR), + .ADDRC(PORT_R_ADDR), + .ADDRD(PORT_R_ADDR), + .ADDRE(PORT_R_ADDR), + .ADDRF(PORT_R_ADDR), + .ADDRG(PORT_R_ADDR), + .ADDRH(PORT_W_ADDR), + .WE(PORT_W_WR_EN), + .WCLK(PORT_W_CLK), + ); +6: if (WIDTH == 3) + RAM64M + #( + .INIT_C(init_slice(0)), + .INIT_B(init_slice(1)), + .INIT_A(init_slice(2)), + ) + _TECHMAP_REPLACE_ + ( + .DOA(PORT_R_RD_DATA[2]), + .DOB(PORT_R_RD_DATA[1]), + .DOC(PORT_R_RD_DATA[0]), + .DIA(PORT_W_WR_DATA[2]), + .DIB(PORT_W_WR_DATA[1]), + .DIC(PORT_W_WR_DATA[0]), + .ADDRA(PORT_R_ADDR), + .ADDRB(PORT_R_ADDR), + .ADDRC(PORT_R_ADDR), + .ADDRD(PORT_W_ADDR), + .WE(PORT_W_WR_EN), + .WCLK(PORT_W_CLK), + ); +else + RAM64M8 + #( + .INIT_G(init_slice(0)), + .INIT_F(init_slice(1)), + .INIT_E(init_slice(2)), + .INIT_D(init_slice(3)), + .INIT_C(init_slice(4)), + .INIT_B(init_slice(5)), + .INIT_A(init_slice(6)), + ) + _TECHMAP_REPLACE_ + ( + .DOA(PORT_R_RD_DATA[6]), + .DOB(PORT_R_RD_DATA[5]), + .DOC(PORT_R_RD_DATA[4]), + .DOD(PORT_R_RD_DATA[3]), + .DOE(PORT_R_RD_DATA[2]), + .DOF(PORT_R_RD_DATA[1]), + .DOG(PORT_R_RD_DATA[0]), + .DIA(PORT_W_WR_DATA[6]), + .DIB(PORT_W_WR_DATA[5]), + .DIC(PORT_W_WR_DATA[4]), + .DID(PORT_W_WR_DATA[3]), + .DIE(PORT_W_WR_DATA[2]), + .DIF(PORT_W_WR_DATA[1]), + .DIG(PORT_W_WR_DATA[0]), + .ADDRA(PORT_R_ADDR), + .ADDRB(PORT_R_ADDR), + .ADDRC(PORT_R_ADDR), + .ADDRD(PORT_R_ADDR), + .ADDRE(PORT_R_ADDR), + .ADDRF(PORT_R_ADDR), + .ADDRG(PORT_R_ADDR), + .ADDRH(PORT_W_ADDR), + .WE(PORT_W_WR_EN), + .WCLK(PORT_W_CLK), + ); +default: + $error("invalid OPTION_ABITS/WIDTH combination"); +endcase +endgenerate + +endmodule diff --git a/techlibs/analogdevices/mux_map.v b/techlibs/analogdevices/mux_map.v new file mode 100644 index 000000000..f49834491 --- /dev/null +++ b/techlibs/analogdevices/mux_map.v @@ -0,0 +1,74 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * 2019 Eddie Hung + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +// The purpose of these mapping rules is to allow preserve all (sufficiently +// wide) $shiftx cells during 'techmap' so that they can be mapped to hard +// resources, rather than being bit-blasted to gates during 'techmap' +// execution + +module \$shiftx (A, B, Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + (* force_downto *) + input [A_WIDTH-1:0] A; + (* force_downto *) + input [B_WIDTH-1:0] B; + (* force_downto *) + output [Y_WIDTH-1:0] Y; + + parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0; + parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0; + + generate + if (B_SIGNED) begin + if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && (_TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0 || _TECHMAP_CONSTVAL_B_[B_WIDTH-1] === 1'bx)) + // Optimisation to remove B_SIGNED if sign bit of B is constant-0 + \$shiftx #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(0), + .A_WIDTH(A_WIDTH), + .B_WIDTH(B_WIDTH-1'd1), + .Y_WIDTH(Y_WIDTH) + ) _TECHMAP_REPLACE_ ( + .A(A), .B(B[B_WIDTH-2:0]), .Y(Y) + ); + else + wire _TECHMAP_FAIL_ = 1; + end + else begin + if (((A_WIDTH + Y_WIDTH - 1) / Y_WIDTH) < `MIN_MUX_INPUTS) + wire _TECHMAP_FAIL_ = 1; + else + \$__XILINX_SHIFTX #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(Y_WIDTH) + ) _TECHMAP_REPLACE_ ( + .A(A), .B(B), .Y(Y) + ); + end + endgenerate +endmodule diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc new file mode 100644 index 000000000..2973bd619 --- /dev/null +++ b/techlibs/analogdevices/synth_analogdevices.cc @@ -0,0 +1,504 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * (C) 2019 Eddie Hung + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/celltypes.h" +#include "kernel/rtlil.h" +#include "kernel/log.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct SynthAnalogDevicesPass : public ScriptPass +{ + SynthAnalogDevicesPass() : ScriptPass("synth_analogdevices", "synthesis for Analog Devices FPGAs") { } + + void on_register() override + { + RTLIL::constpad["synth_analogdevices.abc9.W"] = "300"; // Number with which ABC will map a 6-input gate + // to one LUT6 (instead of a LUT5 + LUT2) + } + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" synth_analogdevices [options]\n"); + log("\n"); + log("This command runs synthesis for Analog Devices FPGAs. This command does not operate on\n"); + log("partly selected designs.\n"); + log("\n"); + log(" -top \n"); + log(" use the specified module as top module\n"); + log("\n"); + log(" -edif \n"); + log(" write the design to the specified edif file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -nobram\n"); + log(" do not use block RAM cells in output netlist\n"); + log("\n"); + log(" -nolutram\n"); + log(" do not use distributed RAM cells in output netlist\n"); + log("\n"); + log(" -nosrl\n"); + log(" do not use distributed SRL cells in output netlist\n"); + log("\n"); + log(" -nocarry\n"); + log(" do not use XORCY/MUXCY/CARRY4 cells in output netlist\n"); + log("\n"); + log(" -nowidelut\n"); + log(" do not use MUXF[7-8] resources to implement LUTs larger than native for\n"); + log(" the target\n"); + log("\n"); + log(" -nodsp\n"); + log(" do not use DSP48*s to implement multipliers and associated logic\n"); + log("\n"); + log(" -noiopad\n"); + log(" disable I/O buffer insertion (useful for hierarchical or \n"); + log(" out-of-context flows)\n"); + log("\n"); + log(" -noclkbuf\n"); + log(" disable automatic clock buffer insertion\n"); + log("\n"); + log(" -widemux \n"); + log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at\n"); + log(" or above this number of inputs (minimum value 2, recommended value >= 5)\n"); + log(" default: 0 (no inference)\n"); + log("\n"); + log(" -run :\n"); + log(" only run the commands between the labels (see below). an empty\n"); + log(" from label is synonymous to 'begin', and empty to label is\n"); + log(" synonymous to the end of the command list.\n"); + log("\n"); + log(" -noflatten\n"); + log(" do not flatten design before synthesis\n"); + log("\n"); + log(" -dff\n"); + log(" run 'abc'/'abc9' with -dff option\n"); + log("\n"); + log(" -retime\n"); + log(" run 'abc' with '-D 1' option to enable flip-flop retiming.\n"); + log(" implies -dff.\n"); + log("\n"); + log(" -noabc9\n"); + log(" disable use of new ABC9 flow\n"); + log("\n"); + log("\n"); + log("The following commands are executed by this synthesis command:\n"); + help_script(); + log("\n"); + } + + std::string top_opt, edif_file, json_file; + bool flatten, retime, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp; + bool abc9, dff; + bool flatten_before_abc; + int widemux; + int widelut_size; + + void clear_flags() override + { + top_opt = "-auto-top"; + edif_file.clear(); + flatten = true; + retime = false; + noiopad = false; + noclkbuf = false; + nocarry = false; + nobram = false; + nolutram = false; + nosrl = false; + nocarry = false; + nowidelut = false; + nodsp = false; + abc9 = true; + dff = false; + flatten_before_abc = false; + widemux = 0; + } + + void execute(std::vector args, RTLIL::Design *design) override + { + std::string run_from, run_to; + clear_flags(); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-top" && argidx+1 < args.size()) { + top_opt = "-top " + args[++argidx]; + continue; + } + if (args[argidx] == "-edif" && argidx+1 < args.size()) { + edif_file = args[++argidx]; + continue; + } + if (args[argidx] == "-run" && argidx+1 < args.size()) { + size_t pos = args[argidx+1].find(':'); + if (pos == std::string::npos) + break; + run_from = args[++argidx].substr(0, pos); + run_to = args[argidx].substr(pos+1); + continue; + } + if (args[argidx] == "-noflatten") { + flatten = false; + continue; + } + if (args[argidx] == "-flatten_before_abc") { + flatten_before_abc = true; + continue; + } + if (args[argidx] == "-retime") { + dff = true; + retime = true; + continue; + } + if (args[argidx] == "-nocarry") { + nocarry = true; + continue; + } + if (args[argidx] == "-nowidelut") { + nowidelut = true; + continue; + } + if (args[argidx] == "-iopad") { + continue; + } + if (args[argidx] == "-noiopad") { + noiopad = true; + continue; + } + if (args[argidx] == "-noclkbuf") { + noclkbuf = true; + continue; + } + if (args[argidx] == "-nocarry") { + nocarry = true; + continue; + } + if (args[argidx] == "-nobram") { + nobram = true; + continue; + } + if (args[argidx] == "-nolutram") { + nolutram = true; + continue; + } + if (args[argidx] == "-nosrl") { + nosrl = true; + continue; + } + if (args[argidx] == "-widemux" && argidx+1 < args.size()) { + widemux = atoi(args[++argidx].c_str()); + continue; + } + if (args[argidx] == "-noabc9") { + abc9 = false; + continue; + } + if (args[argidx] == "-nodsp") { + nodsp = true; + continue; + } + if (args[argidx] == "-dff") { + dff = true; + continue; + } + if (args[argidx] == "-json" && argidx+1 < args.size()) { + json_file = args[++argidx]; + continue; + } + break; + } + extra_args(args, argidx, design); + + if (widemux != 0 && widemux < 2) + log_cmd_error("-widemux value must be 0 or >= 2.\n"); + + if (!design->full_selection()) + log_cmd_error("This command only operates on fully selected designs!\n"); + + if (abc9 && retime) + log_cmd_error("-retime option not currently compatible with -abc9!\n"); + + log_header(design, "Executing SYNTH_ANALOGDEVICES pass.\n"); + log_push(); + + run_script(design, run_from, run_to); + + log_pop(); + } + + void script() override + { + if (check_label("begin")) { + std::string read_args; + read_args += " -lib -specify +/analogdevices/cells_sim.v"; + run("read_verilog" + read_args); + + run("read_verilog -lib +/analogdevices/cells_xtra.v"); + + run(stringf("hierarchy -check %s", top_opt.c_str())); + } + + if (check_label("prepare")) { + run("proc"); + if (flatten || help_mode) + run("flatten", "(with '-flatten')"); + if (active_design) + active_design->scratchpad_unset("tribuf.added_something"); + run("tribuf -logic"); + if (noiopad && active_design && active_design->scratchpad_get_bool("tribuf.added_something")) + log_error("Tristate buffers are unsupported without the '-iopad' option.\n"); + run("deminout"); + run("opt_expr"); + run("opt_clean"); + run("check"); + run("opt -nodffe -nosdff"); + run("fsm"); + run("opt"); + if (help_mode) + run("wreduce [-keepdc]", "(option for '-widemux')"); + else + run("wreduce" + std::string(widemux > 0 ? " -keepdc" : "")); + run("peepopt"); + run("opt_clean"); + + if (widemux > 0 || help_mode) + run("muxpack", " ('-widemux' only)"); + + // xilinx_srl looks for $shiftx cells for identifying variable-length + // shift registers, so attempt to convert $pmux-es to this + // Also: wide multiplexer inference benefits from this too + if (!(nosrl && widemux == 0) || help_mode) { + run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')"); + run("clean", " (skip if '-nosrl' and '-widemux=0')"); + } + } + + if (check_label("map_dsp", "(skip if '-nodsp')")) { + if (!nodsp || help_mode) { + run("memory_dff"); // xilinx_dsp will merge registers, reserve memory port registers first + // NB: Xilinx multipliers are signed only + if (help_mode) + run("techmap -map +/mul2dsp.v -map +/analogdevices/{family}_dsp_map.v {options}"); + run("techmap -map +/mul2dsp.v -map +/analogdevices/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 " + "-D DSP_A_MAXWIDTH_PARTIAL=18 " // Partial multipliers are intentionally + // limited to 18x18 in order to take + // advantage of the (PCOUT << 17) -> PCIN + // dedicated cascade chain capability + "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers + "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller + "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); + + run("select a:mul2dsp"); + run("setattr -unset mul2dsp"); + run("opt_expr -fine"); + run("wreduce"); + run("select -clear"); + if (help_mode) + run("xilinx_dsp -family "); + else + run("xilinx_dsp -family xc7"); + run("chtype -set $mul t:$__soft_mul"); + } + } + + if (check_label("coarse")) { + run("techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=6"); + run("alumacc"); + run("share"); + run("opt"); + run("memory -nomap"); + run("opt_clean"); + } + + if (check_label("map_memory")) { + std::string params = ""; + std::string lutrams_map = "+/analogdevices/lutrams__map.v"; + std::string brams_map = "+/analogdevices/brams__map.v"; + if (help_mode) { + params = " [...]"; + } else { + params += " -logic-cost-rom 0.015625"; + params += " -lib +/analogdevices/lutrams.txt"; + lutrams_map = "+/analogdevices/lutrams_map.v"; + params += " -lib +/analogdevices/brams.txt"; + params += " -D HAS_SIZE_36"; + params += " -D HAS_CASCADE"; + params += " -D HAS_CONFLICT_BUG"; + params += " -D HAS_MIXWIDTH_SDP"; + brams_map = "+/analogdevices/brams_map.v"; + if (nolutram) + params += " -no-auto-distributed"; + if (nobram) + params += " -no-auto-block"; + } + run("memory_libmap" + params); + run("techmap -map " + lutrams_map); + run("techmap -map " + brams_map); + } + + if (check_label("map_ffram")) { + if (widemux > 0) { + run("opt -fast -mux_bool -undriven -fine"); // Necessary to omit -mux_undef otherwise muxcover + // performs less efficiently + } else { + run("opt -fast -full"); + } + run("memory_map"); + } + + if (check_label("fine")) { + if (help_mode) { + run("simplemap t:$mux", "('-widemux' only)"); + run("muxcover ", "('-widemux' only)"); + } else if (widemux > 0) { + run("simplemap t:$mux"); + constexpr int cost_mux2 = 100; + std::string muxcover_args = stringf(" -nodecode -mux2=%d", cost_mux2); + switch (widemux) { + case 2: muxcover_args += stringf(" -mux4=%d -mux8=%d -mux16=%d", cost_mux2+1, cost_mux2+2, cost_mux2+3); break; + case 3: + case 4: muxcover_args += stringf(" -mux4=%d -mux8=%d -mux16=%d", cost_mux2*(widemux-1)-2, cost_mux2*(widemux-1)-1, cost_mux2*(widemux-1)); break; + case 5: + case 6: + case 7: + case 8: muxcover_args += stringf(" -mux8=%d -mux16=%d", cost_mux2*(widemux-1)-1, cost_mux2*(widemux-1)); break; + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + default: muxcover_args += stringf(" -mux16=%d", cost_mux2*(widemux-1)-1); break; + } + run("muxcover " + muxcover_args); + } + run("opt -full"); + + if (!nosrl || help_mode) + run("xilinx_srl -variable -minlen 3", "(skip if '-nosrl')"); + + std::string techmap_args = " -map +/techmap.v -D LUT_SIZE=6"; + if (help_mode) + techmap_args += " [-map +/analogdevices/mux_map.v]"; + else if (widemux > 0) + techmap_args += stringf(" -D MIN_MUX_INPUTS=%d -map +/analogdevices/mux_map.v", widemux); + if (!nocarry) { + techmap_args += " -map +/analogdevices/arith_map.v"; + } + run("techmap " + techmap_args); + run("opt -fast"); + } + + if (check_label("map_cells")) { + // Needs to be done before logic optimization, so that inverters (inserted + // here because of negative-polarity output enable) are handled. + if (help_mode || !noiopad) + run("iopadmap -bits -outpad OUTBUF I:O -inpad INBUF O:I -toutpad OBUFT ~T:I:O -tinoutpad IOBUF ~T:O:I:IO A:top", "(skip if '-noiopad')"); + std::string techmap_args = "-map +/techmap.v -map +/analogdevices/cells_map.v"; + if (widemux > 0) + techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux); + run("techmap " + techmap_args); + run("clean"); + } + + if (check_label("map_ffs")) { + run("dfflegalize -cell $_DFFE_?P?P_ 01 -cell $_SDFFE_?P?P_ 01"); + if (abc9 || help_mode) { + if (dff || help_mode) + run("zinit -all w:* t:$_SDFFE_*", "('-dff' only)"); + run("techmap -map +/analogdevices/ff_map.v", "('-abc9' only)"); + } + } + + if (check_label("map_luts")) { + run("opt_expr -mux_undef -noclkinv"); + if (flatten_before_abc) + run("flatten"); + if (help_mode) + run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for '-nowidelut', '-dff', '-retime')"); + else if (abc9) { + run("read_verilog -icells -lib -specify +/analogdevices/abc9_model.v"); + std::string abc9_opts; + std::string k = "synth_analogdevices.abc9.W"; + if (active_design && active_design->scratchpad.count(k)) + abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str()); + else { + abc9_opts += stringf(" -W %s", RTLIL::constpad.at("synth_analogdevices.abc9.W").c_str()); + } + if (nowidelut) + abc9_opts += stringf(" -maxlut 6"); + if (dff) + abc9_opts += " -dff"; + run("abc9" + abc9_opts); + } + else { + std::string abc_opts; + if (nowidelut) + abc_opts += " -luts 2:2,3,6:5"; + else + abc_opts += " -luts 2:2,3,6:5,10,20"; + if (dff) + abc_opts += " -dff"; + if (retime) + abc_opts += " -D 1"; + run("abc" + abc_opts); + } + run("clean"); + + if (help_mode || !abc9) + run("techmap -map +/analogdevices/ff_map.v", "(only if not '-abc9')"); + // This shregmap call infers fixed length shift registers after abc + // has performed any necessary retiming + if (!nosrl || help_mode) + run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')"); + std::string techmap_args = "-map +/analogdevices/lut_map.v -map +/analogdevices/cells_map.v"; + techmap_args += " -D LUT_WIDTH=6"; + run("techmap " + techmap_args); + run("xilinx_dffopt"); + run("opt_lut_ins -tech xilinx"); + } + + if (check_label("finalize")) { + if (help_mode || !noclkbuf) + run("clkbufmap -buf BUFG O:I", "(skip if '-noclkbuf')"); + run("clean"); + } + + if (check_label("check")) { + run("hierarchy -check"); + run("stat -tech xilinx"); + run("check -noinit"); + run("blackbox =A:whitebox"); + } + + if (check_label("edif")) { + if (!edif_file.empty() || help_mode) + run(stringf("write_edif -pvector bra %s", edif_file.c_str())); + } + } +} SynthAnalogDevicesPass; + +PRIVATE_NAMESPACE_END From 4f2f06426259dc2ead6f9c73be4c820f10eb9009 Mon Sep 17 00:00:00 2001 From: Lofty Date: Wed, 24 Sep 2025 16:29:38 +0100 Subject: [PATCH 252/291] synth_analogdevices: remove scopeinfo cells --- techlibs/analogdevices/synth_analogdevices.cc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc index 2973bd619..75fc59e99 100644 --- a/techlibs/analogdevices/synth_analogdevices.cc +++ b/techlibs/analogdevices/synth_analogdevices.cc @@ -495,8 +495,10 @@ struct SynthAnalogDevicesPass : public ScriptPass } if (check_label("edif")) { - if (!edif_file.empty() || help_mode) - run(stringf("write_edif -pvector bra %s", edif_file.c_str())); + if (!edif_file.empty() || help_mode) { + run("delete t:$scopeinfo"); + run(stringf("write_edif %s", edif_file.c_str())); + } } } } SynthAnalogDevicesPass; From 6f205b41f5ebd3d3d29abb4b973d1f69c40c2479 Mon Sep 17 00:00:00 2001 From: Lofty Date: Wed, 24 Sep 2025 20:56:27 +0100 Subject: [PATCH 253/291] test suite --- backends/edif/edif.cc | 1 + techlibs/analogdevices/cells_sim.v | 99 ++---------- techlibs/analogdevices/ff_map.v | 73 +-------- techlibs/analogdevices/lutrams.txt | 8 - techlibs/analogdevices/synth_analogdevices.cc | 2 +- tests/arch/analogdevices/abc9_dff.ys | 142 ++++++++++++++++++ tests/arch/analogdevices/add_sub.ys | 13 ++ tests/arch/analogdevices/adffs.ys | 51 +++++++ tests/arch/analogdevices/asym_ram_sdp.ys | 50 ++++++ .../analogdevices/asym_ram_sdp_read_wider.v | 72 +++++++++ .../analogdevices/asym_ram_sdp_write_wider.v | 71 +++++++++ tests/arch/analogdevices/attributes_test.ys | 37 +++++ tests/arch/analogdevices/blockram.ys | 73 +++++++++ tests/arch/analogdevices/bug1460.ys | 34 +++++ tests/arch/analogdevices/bug1462.ys | 11 ++ tests/arch/analogdevices/bug1480.ys | 18 +++ tests/arch/analogdevices/bug1598.ys | 16 ++ tests/arch/analogdevices/bug1605.ys | 19 +++ tests/arch/analogdevices/bug3670.v | 13 ++ tests/arch/analogdevices/bug3670.ys | 3 + tests/arch/analogdevices/counter.ys | 13 ++ tests/arch/analogdevices/dffs.ys | 45 ++++++ tests/arch/analogdevices/dsp_abc9.ys | 56 +++++++ tests/arch/analogdevices/fsm.ys | 21 +++ tests/arch/analogdevices/logic.ys | 11 ++ tests/arch/analogdevices/lutram.ys | 119 +++++++++++++++ tests/arch/analogdevices/macc.sh | 6 + tests/arch/analogdevices/macc.v | 84 +++++++++++ tests/arch/analogdevices/macc.ys | 32 ++++ tests/arch/analogdevices/macc_tb.v | 96 ++++++++++++ tests/arch/analogdevices/mul.ys | 9 ++ tests/arch/analogdevices/mul_unsigned.v | 30 ++++ tests/arch/analogdevices/mul_unsigned.ys | 11 ++ tests/arch/analogdevices/mux.ys | 50 ++++++ tests/arch/analogdevices/opt_lut_ins.ys | 26 ++++ tests/arch/analogdevices/run-test.sh | 4 + tests/arch/analogdevices/shifter.ys | 11 ++ tests/arch/analogdevices/tribuf.ys | 13 ++ 38 files changed, 1282 insertions(+), 161 deletions(-) create mode 100644 tests/arch/analogdevices/abc9_dff.ys create mode 100644 tests/arch/analogdevices/add_sub.ys create mode 100644 tests/arch/analogdevices/adffs.ys create mode 100644 tests/arch/analogdevices/asym_ram_sdp.ys create mode 100644 tests/arch/analogdevices/asym_ram_sdp_read_wider.v create mode 100644 tests/arch/analogdevices/asym_ram_sdp_write_wider.v create mode 100644 tests/arch/analogdevices/attributes_test.ys create mode 100644 tests/arch/analogdevices/blockram.ys create mode 100644 tests/arch/analogdevices/bug1460.ys create mode 100644 tests/arch/analogdevices/bug1462.ys create mode 100644 tests/arch/analogdevices/bug1480.ys create mode 100644 tests/arch/analogdevices/bug1598.ys create mode 100644 tests/arch/analogdevices/bug1605.ys create mode 100644 tests/arch/analogdevices/bug3670.v create mode 100644 tests/arch/analogdevices/bug3670.ys create mode 100644 tests/arch/analogdevices/counter.ys create mode 100644 tests/arch/analogdevices/dffs.ys create mode 100644 tests/arch/analogdevices/dsp_abc9.ys create mode 100644 tests/arch/analogdevices/fsm.ys create mode 100644 tests/arch/analogdevices/logic.ys create mode 100644 tests/arch/analogdevices/lutram.ys create mode 100644 tests/arch/analogdevices/macc.sh create mode 100644 tests/arch/analogdevices/macc.v create mode 100644 tests/arch/analogdevices/macc.ys create mode 100644 tests/arch/analogdevices/macc_tb.v create mode 100644 tests/arch/analogdevices/mul.ys create mode 100644 tests/arch/analogdevices/mul_unsigned.v create mode 100644 tests/arch/analogdevices/mul_unsigned.ys create mode 100644 tests/arch/analogdevices/mux.ys create mode 100644 tests/arch/analogdevices/opt_lut_ins.ys create mode 100755 tests/arch/analogdevices/run-test.sh create mode 100644 tests/arch/analogdevices/shifter.ys create mode 100644 tests/arch/analogdevices/tribuf.ys diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 145477b6b..12d035e49 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -82,6 +82,7 @@ struct EdifNames used_names.count(gen_name) == 0) break; } + log("renamed '%s' to '%s'\n", id, gen_name); generated_names.insert(gen_name); name_map[id] = gen_name; return gen_name; diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v index 05a320986..286619f71 100644 --- a/techlibs/analogdevices/cells_sim.v +++ b/techlibs/analogdevices/cells_sim.v @@ -453,7 +453,7 @@ endmodule // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250 (* abc9_flop, lib_whitebox *) -module FDRE ( +module FFRE ( output reg Q, (* clkbuf_sink *) (* invertible_pin = "IS_C_INVERTED" *) @@ -494,7 +494,7 @@ module FDRE ( endmodule (* abc9_flop, lib_whitebox *) -module FDRE_1 ( +module FFRE_N ( output reg Q, (* clkbuf_sink *) input C, @@ -518,7 +518,7 @@ module FDRE_1 ( endmodule (* abc9_flop, lib_whitebox *) -module FDSE ( +module FFSE ( output reg Q, (* clkbuf_sink *) (* invertible_pin = "IS_C_INVERTED" *) @@ -559,7 +559,7 @@ module FDSE ( endmodule (* abc9_flop, lib_whitebox *) -module FDSE_1 ( +module FFSE_N ( output reg Q, (* clkbuf_sink *) input C, @@ -583,7 +583,7 @@ module FDSE_1 ( endspecify endmodule -module FDRSE ( +module FFRSE ( output reg Q, (* clkbuf_sink *) (* invertible_pin = "IS_C_INVERTED" *) @@ -618,7 +618,7 @@ module FDRSE ( Q <= d; endmodule -module FDRSE_1 ( +module FFRSE_N ( output reg Q, (* clkbuf_sink *) (* invertible_pin = "IS_C_INVERTED" *) @@ -654,7 +654,7 @@ module FDRSE_1 ( endmodule (* abc9_box, lib_whitebox *) -module FDCE ( +module FFCE ( output reg Q, (* clkbuf_sink *) (* invertible_pin = "IS_C_INVERTED" *) @@ -703,7 +703,7 @@ module FDCE ( endmodule (* abc9_box, lib_whitebox *) -module FDCE_1 ( +module FFCE_N ( output reg Q, (* clkbuf_sink *) input C, @@ -734,7 +734,7 @@ module FDCE_1 ( endmodule (* abc9_box, lib_whitebox *) -module FDPE ( +module FFPE ( output reg Q, (* clkbuf_sink *) (* invertible_pin = "IS_C_INVERTED" *) @@ -782,7 +782,7 @@ module FDPE ( endmodule (* abc9_box, lib_whitebox *) -module FDPE_1 ( +module FFPE_N ( output reg Q, (* clkbuf_sink *) input C, @@ -812,7 +812,7 @@ module FDPE_1 ( endspecify endmodule -module FDCPE ( +module FFCPE ( output wire Q, (* clkbuf_sink *) (* invertible_pin = "IS_C_INVERTED" *) @@ -857,7 +857,7 @@ module FDCPE ( assign Q = qs ? qp : qc; endmodule -module FDCPE_1 ( +module FFCPE_N ( output wire Q, (* clkbuf_sink *) (* invertible_pin = "IS_C_INVERTED" *) @@ -902,81 +902,6 @@ module FDCPE_1 ( assign Q = qs ? qp : qc; endmodule -module LDCE ( - output reg Q, - (* invertible_pin = "IS_CLR_INVERTED" *) - input CLR, - input D, - (* invertible_pin = "IS_G_INVERTED" *) - input G, - input GE -); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_CLR_INVERTED = 1'b0; - parameter [0:0] IS_G_INVERTED = 1'b0; - parameter MSGON = "TRUE"; - parameter XON = "TRUE"; - initial Q = INIT; - wire clr = CLR ^ IS_CLR_INVERTED; - wire g = G ^ IS_G_INVERTED; - always @* - if (clr) Q <= 1'b0; - else if (GE && g) Q <= D; -endmodule - -module LDPE ( - output reg Q, - input D, - (* invertible_pin = "IS_G_INVERTED" *) - input G, - input GE, - (* invertible_pin = "IS_PRE_INVERTED" *) - input PRE -); - parameter [0:0] INIT = 1'b1; - parameter [0:0] IS_G_INVERTED = 1'b0; - parameter [0:0] IS_PRE_INVERTED = 1'b0; - parameter MSGON = "TRUE"; - parameter XON = "TRUE"; - initial Q = INIT; - wire g = G ^ IS_G_INVERTED; - wire pre = PRE ^ IS_PRE_INVERTED; - always @* - if (pre) Q <= 1'b1; - else if (GE && g) Q <= D; -endmodule - -module LDCPE ( - output reg Q, - (* invertible_pin = "IS_CLR_INVERTED" *) - input CLR, - (* invertible_pin = "IS_D_INVERTED" *) - input D, - (* invertible_pin = "IS_G_INVERTED" *) - input G, - (* invertible_pin = "IS_GE_INVERTED" *) - input GE, - (* invertible_pin = "IS_PRE_INVERTED" *) - input PRE -); - parameter [0:0] INIT = 1'b1; - parameter [0:0] IS_CLR_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_G_INVERTED = 1'b0; - parameter [0:0] IS_GE_INVERTED = 1'b0; - parameter [0:0] IS_PRE_INVERTED = 1'b0; - initial Q = INIT; - wire d = D ^ IS_D_INVERTED; - wire g = G ^ IS_G_INVERTED; - wire ge = GE ^ IS_GE_INVERTED; - wire clr = CLR ^ IS_CLR_INVERTED; - wire pre = PRE ^ IS_PRE_INVERTED; - always @* - if (clr) Q <= 1'b0; - else if (pre) Q <= 1'b1; - else if (ge && g) Q <= d; -endmodule - module AND2B1L ( output O, input DI, diff --git a/techlibs/analogdevices/ff_map.v b/techlibs/analogdevices/ff_map.v index 2079fd99a..0be742b49 100644 --- a/techlibs/analogdevices/ff_map.v +++ b/techlibs/analogdevices/ff_map.v @@ -22,97 +22,40 @@ // Async reset, enable. module \$_DFFE_NP0P_ (input D, C, E, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R)); + FFCE_N #(.INIT(1'b0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFFE_PP0P_ (input D, C, E, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R)); + FFCE #(.INIT(1'b0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFFE_NP1P_ (input D, C, E, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE(R)); + FFPE_N #(.INIT(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFFE_PP1P_ (input D, C, E, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE(R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -// Async set and reset, enable. - -module \$_DFFSRE_NPPP_ (input D, C, E, S, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDCPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R), .PRE(S)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$_DFFSRE_PPPP_ (input D, C, E, S, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDCPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R), .PRE(S)); + FFPE #(.INIT(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule // Sync reset, enable. module \$_SDFFE_NP0P_ (input D, C, E, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(R)); + FFRE_N #(.INIT(1'b0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_SDFFE_PP0P_ (input D, C, E, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(R)); + FFRE #(.INIT(1'b0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_SDFFE_NP1P_ (input D, C, E, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(R)); + FFSE_N #(.INIT(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_SDFFE_PP1P_ (input D, C, E, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -// Latches with reset. - -module \$_DLATCH_NP0_ (input E, R, D, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - LDCE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$_DLATCH_PP0_ (input E, R, D, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - LDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$_DLATCH_NP1_ (input E, R, D, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - LDPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .PRE(R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$_DLATCH_PP1_ (input E, R, D, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - LDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .PRE(R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -// Latches with set and reset. - -module \$_DLATCH_NPP_ (input E, S, R, D, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - LDCPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R), .PRE(S)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$_DLATCH_PPP_ (input E, S, R, D, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - LDCPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R), .PRE(S)); + FFSE #(.INIT(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule diff --git a/techlibs/analogdevices/lutrams.txt b/techlibs/analogdevices/lutrams.txt index 882cc5722..ae1c16ebb 100644 --- a/techlibs/analogdevices/lutrams.txt +++ b/techlibs/analogdevices/lutrams.txt @@ -14,14 +14,6 @@ ram distributed $__ANALOGDEVICES_LUTRAM_SP_ { abits 6; widths 4 global; } - option "ABITS" 7 { - abits 7; - widths 2 global; - } - option "ABITS" 8 { - abits 8; - widths 1 global; - } init no_undef; prune_rom; port arsw "RW" { diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc index 75fc59e99..33ba520fa 100644 --- a/techlibs/analogdevices/synth_analogdevices.cc +++ b/techlibs/analogdevices/synth_analogdevices.cc @@ -425,7 +425,7 @@ struct SynthAnalogDevicesPass : public ScriptPass } if (check_label("map_ffs")) { - run("dfflegalize -cell $_DFFE_?P?P_ 01 -cell $_SDFFE_?P?P_ 01"); + run("dfflegalize -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r"); if (abc9 || help_mode) { if (dff || help_mode) run("zinit -all w:* t:$_SDFFE_*", "('-dff' only)"); diff --git a/tests/arch/analogdevices/abc9_dff.ys b/tests/arch/analogdevices/abc9_dff.ys new file mode 100644 index 000000000..891330726 --- /dev/null +++ b/tests/arch/analogdevices/abc9_dff.ys @@ -0,0 +1,142 @@ +logger -nowarn "Yosys has only limited support for tri-state logic at the moment\. .*" +logger -nowarn "Ignoring boxed module .*\." + +read_verilog < RAMB18E1 + +# w4b | r16b +design -reset +read_verilog asym_ram_sdp_read_wider.v +synth_analogdevices -top asym_ram_sdp_read_wider -noiopad +select -assert-count 1 t:RAMB18E1 + +# w8b | r16b +design -reset +read_verilog asym_ram_sdp_read_wider.v +chparam -set WIDTHA 8 -set SIZEA 512 -set ADDRWIDTHA 9 asym_ram_sdp_read_wider +synth_analogdevices -top asym_ram_sdp_read_wider -noiopad +select -assert-count 1 t:RAMB18E1 + +# w4b | r32b +design -reset +read_verilog asym_ram_sdp_read_wider.v +chparam -set WIDTHB 32 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider +synth_analogdevices -top asym_ram_sdp_read_wider -noiopad +select -assert-count 1 t:RAMB18E1 + +# w16b | r4b +design -reset +read_verilog asym_ram_sdp_write_wider.v +synth_analogdevices -top asym_ram_sdp_write_wider -noiopad +select -assert-count 1 t:RAMB18E1 + +# w16b | r8b +design -reset +read_verilog asym_ram_sdp_write_wider.v +chparam -set WIDTHB 8 -set SIZEB 512 -set ADDRWIDTHB 9 asym_ram_sdp_read_wider +synth_analogdevices -top asym_ram_sdp_write_wider -noiopad +select -assert-count 1 t:RAMB18E1 + +# w32b | r4b +design -reset +read_verilog asym_ram_sdp_write_wider.v +chparam -set WIDTHA 32 -set SIZEA 128 -set ADDRWIDTHA 7 asym_ram_sdp_read_wider +synth_analogdevices -top asym_ram_sdp_write_wider -noiopad +select -assert-count 1 t:RAMB18E1 + +# w4b | r24b +design -reset +read_verilog asym_ram_sdp_read_wider.v +chparam -set SIZEA 768 +chparam -set WIDTHB 24 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider +synth_analogdevices -top asym_ram_sdp_read_wider -noiopad +select -assert-count 1 t:RAMB18E1 + diff --git a/tests/arch/analogdevices/asym_ram_sdp_read_wider.v b/tests/arch/analogdevices/asym_ram_sdp_read_wider.v new file mode 100644 index 000000000..8743209e3 --- /dev/null +++ b/tests/arch/analogdevices/asym_ram_sdp_read_wider.v @@ -0,0 +1,72 @@ +// Asymmetric port RAM +// Read Wider than Write. Read Statement in loop +//asym_ram_sdp_read_wider.v +module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA, doB); + parameter WIDTHA = 4; + parameter SIZEA = 1024; + parameter ADDRWIDTHA = 10; + + parameter WIDTHB = 16; + parameter SIZEB = 256; + parameter ADDRWIDTHB = 8; + + input clkA; + input clkB; + input weA; + input enaA, enaB; + input [ADDRWIDTHA-1:0] addrA; + input [ADDRWIDTHB-1:0] addrB; + input [WIDTHA-1:0] diA; + output [WIDTHB-1:0] doB; + + `define max(a,b) {(a) > (b) ? (a) : (b)} + `define min(a,b) {(a) < (b) ? (a) : (b)} + + function integer log2; + input integer value; + reg [31:0] shifted; + integer res; + begin + if (value < 2) + log2 = value; + else + begin + shifted = value-1; + for (res=0; shifted>0; res=res+1) + shifted = shifted>>1; + log2 = res; + end + end + endfunction + + localparam maxSIZE = `max(SIZEA, SIZEB); + localparam maxWIDTH = `max(WIDTHA, WIDTHB); + localparam minWIDTH = `min(WIDTHA, WIDTHB); + + localparam RATIO = maxWIDTH / minWIDTH; + localparam log2RATIO = log2(RATIO); + + reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; + reg [WIDTHB-1:0] readB; + + always @(posedge clkA) + begin + if (enaA) begin + if (weA) + RAM[addrA] <= diA; + end + end + + always @(posedge clkB) + begin : ramread + integer i; + reg [log2RATIO-1:0] lsbaddr; + if (enaB) begin + for (i = 0; i < RATIO; i = i+1) begin + lsbaddr = i; + readB[(i+1)*minWIDTH-1 -: minWIDTH] <= RAM[{addrB, lsbaddr}]; + end + end + end + assign doB = readB; +endmodule \ No newline at end of file diff --git a/tests/arch/analogdevices/asym_ram_sdp_write_wider.v b/tests/arch/analogdevices/asym_ram_sdp_write_wider.v new file mode 100644 index 000000000..cd61a3ccc --- /dev/null +++ b/tests/arch/analogdevices/asym_ram_sdp_write_wider.v @@ -0,0 +1,71 @@ +// Asymmetric port RAM +// Write wider than Read. Write Statement in a loop. +// asym_ram_sdp_write_wider.v +module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA, doB); + parameter WIDTHB = 4; + parameter SIZEB = 1024; + parameter ADDRWIDTHB = 10; + + parameter WIDTHA = 16; + parameter SIZEA = 256; + parameter ADDRWIDTHA = 8; + + input clkA; + input clkB; + input weA; + input enaA, enaB; + input [ADDRWIDTHA-1:0] addrA; + input [ADDRWIDTHB-1:0] addrB; + input [WIDTHA-1:0] diA; + output [WIDTHB-1:0] doB; + + `define max(a,b) {(a) > (b) ? (a) : (b)} + `define min(a,b) {(a) < (b) ? (a) : (b)} + + function integer log2; + input integer value; + reg [31:0] shifted; + integer res; + begin + if (value < 2) + log2 = value; + else + begin + shifted = value-1; + for (res=0; shifted>0; res=res+1) + shifted = shifted>>1; + log2 = res; + end + end + endfunction + + localparam maxSIZE = `max(SIZEA, SIZEB); + localparam maxWIDTH = `max(WIDTHA, WIDTHB); + localparam minWIDTH = `min(WIDTHA, WIDTHB); + + localparam RATIO = maxWIDTH / minWIDTH; + localparam log2RATIO = log2(RATIO); + + reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; + reg [WIDTHB-1:0] readB; + + always @(posedge clkB) begin + if (enaB) begin + readB <= RAM[addrB]; + end + end + assign doB = readB; + + always @(posedge clkA) + begin : ramwrite + integer i; + reg [log2RATIO-1:0] lsbaddr; + for (i=0; i< RATIO; i= i+ 1) begin : write1 + lsbaddr = i; + if (enaA) begin + if (weA) + RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH]; + end + end + end +endmodule \ No newline at end of file diff --git a/tests/arch/analogdevices/attributes_test.ys b/tests/arch/analogdevices/attributes_test.ys new file mode 100644 index 000000000..8d55d96fd --- /dev/null +++ b/tests/arch/analogdevices/attributes_test.ys @@ -0,0 +1,37 @@ +# Check that blockram memory without parameters is not modified +read_verilog ../common/memory_attributes/attributes_test.v +hierarchy -top block_ram +synth_analogdevices -top block_ram -noiopad +cd block_ram # Constrain all select calls below inside the top module +select -assert-count 1 t:RAMB18E1 + +# Check that distributed memory without parameters is not modified +design -reset +read_verilog ../common/memory_attributes/attributes_test.v +hierarchy -top distributed_ram +synth_analogdevices -top distributed_ram -noiopad +cd distributed_ram # Constrain all select calls below inside the top module +select -assert-count 1 t:RAM32M + +# Set ram_style distributed to blockram memory; will be implemented as distributed +design -reset +read_verilog ../common/memory_attributes/attributes_test.v +setattr -set ram_style "distributed" block_ram/m:* +synth_analogdevices -top block_ram -noiopad +cd block_ram # Constrain all select calls below inside the top module +select -assert-count 64 t:RAM64X1S + +# Set synthesis, logic_block to blockram memory; will be implemented as distributed +design -reset +read_verilog ../common/memory_attributes/attributes_test.v +setattr -set logic_block 1 block_ram/m:* +synth_analogdevices -top block_ram -noiopad +cd block_ram # Constrain all select calls below inside the top module +select -assert-count 0 t:RAMB18E1 + +# Set ram_style block to a distributed memory; will be implemented as blockram +design -reset +read_verilog ../common/memory_attributes/attributes_test.v +synth_analogdevices -top distributed_ram_manual -noiopad +cd distributed_ram_manual # Constrain all select calls below inside the top module +select -assert-count 1 t:RAMB18E1 diff --git a/tests/arch/analogdevices/blockram.ys b/tests/arch/analogdevices/blockram.ys new file mode 100644 index 000000000..26d5634ba --- /dev/null +++ b/tests/arch/analogdevices/blockram.ys @@ -0,0 +1,73 @@ +### TODO: Not running equivalence checking because BRAM models does not exists +### currently. Checking instance counts instead. +# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 12 -set DATA_WIDTH 1 sync_ram_sdp +synth_analogdevices -top sync_ram_sdp -noiopad +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp +synth_analogdevices -top sync_ram_sdp -noiopad +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp +synth_analogdevices -top sync_ram_sdp -noiopad +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp +synth_analogdevices -top sync_ram_sdp -noiopad +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +# Anything memory bits < 1024 -> LUTRAM +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp +synth_analogdevices -top sync_ram_sdp -noiopad +cd sync_ram_sdp +select -assert-count 0 t:RAMB18E1 +select -assert-count 4 t:RAM64M + +# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp +synth_analogdevices -top sync_ram_sdp -noiopad +cd sync_ram_sdp +select -assert-count 1 t:RAMB36E1 + + +### With parameters + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 +setattr -set ram_style "block" m:memory +synth_analogdevices -top sync_ram_sdp -noiopad +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 +setattr -set logic_block 1 m:memory +synth_analogdevices -top sync_ram_sdp -noiopad +cd sync_ram_sdp +select -assert-count 0 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1 +setattr -set ram_style "block" m:memory +synth_analogdevices -top sync_ram_sdp -noiopad +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 diff --git a/tests/arch/analogdevices/bug1460.ys b/tests/arch/analogdevices/bug1460.ys new file mode 100644 index 000000000..d00292c19 --- /dev/null +++ b/tests/arch/analogdevices/bug1460.ys @@ -0,0 +1,34 @@ +read_verilog <= 2**(SIZEOUT-1)) | overflow_reg; + +// Output accumulation result +assign accum_out = overflow ? 2**(SIZEOUT-1)-1 : adder_out; + +endmodule diff --git a/tests/arch/analogdevices/macc.ys b/tests/arch/analogdevices/macc.ys new file mode 100644 index 000000000..79b330016 --- /dev/null +++ b/tests/arch/analogdevices/macc.ys @@ -0,0 +1,32 @@ +read_verilog macc.v +design -save read + +hierarchy -top macc +proc +#equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad ### TODO +equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -show-inputs -show-outputs miter +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd macc # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:FFRE +select -assert-count 1 t:DSP48E1 +select -assert-none t:BUFG t:FFRE t:DSP48E1 %% t:* %D + +design -load read +hierarchy -top macc2 +proc +#equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad ### TODO +equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 4 -show-inputs -show-outputs miter +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd macc2 # Constrain all select calls below inside the top module + +select -assert-count 1 t:BUFG +select -assert-count 1 t:DSP48E1 +select -assert-count 1 t:FFRE +select -assert-count 1 t:LUT2 +select -assert-count 40 t:LUT3 +select -assert-none t:BUFG t:DSP48E1 t:FFRE t:LUT2 t:LUT3 %% t:* %D diff --git a/tests/arch/analogdevices/macc_tb.v b/tests/arch/analogdevices/macc_tb.v new file mode 100644 index 000000000..64aed05c4 --- /dev/null +++ b/tests/arch/analogdevices/macc_tb.v @@ -0,0 +1,96 @@ +`timescale 1ns / 1ps + +module testbench; + + parameter SIZEIN = 16, SIZEOUT = 40; + reg clk, ce, rst; + reg signed [SIZEIN-1:0] a, b; + output signed [SIZEOUT-1:0] REF_accum_out, accum_out; + output REF_overflow, overflow; + + integer errcount = 0; + + reg ERROR_FLAG = 0; + + task clkcycle; + begin + #5; + clk = ~clk; + #10; + clk = ~clk; + #2; + ERROR_FLAG = 0; + if (REF_accum_out !== accum_out) begin + $display("ERROR at %1t: REF_accum_out=%b UUT_accum_out=%b DIFF=%b", $time, REF_accum_out, accum_out, REF_accum_out ^ accum_out); + errcount = errcount + 1; + ERROR_FLAG = 1; + end + if (REF_overflow !== overflow) begin + $display("ERROR at %1t: REF_overflow=%b UUT_overflow=%b DIFF=%b", $time, REF_overflow, overflow, REF_overflow ^ overflow); + errcount = errcount + 1; + ERROR_FLAG = 1; + end + #3; + end + endtask + + initial begin + //$dumpfile("test_macc.vcd"); + //$dumpvars(0, testbench); + + #2; + clk = 1'b0; + ce = 1'b0; + a = 0; + b = 0; + + rst = 1'b1; + repeat (10) begin + #10; + clk = 1'b1; + #10; + clk = 1'b0; + #10; + clk = 1'b1; + #10; + clk = 1'b0; + end + rst = 1'b0; + + repeat (10000) begin + clkcycle; + ce = 1; //$urandom & $urandom; + //rst = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom; + a = $urandom & ~(1 << (SIZEIN-1)); + b = $urandom & ~(1 << (SIZEIN-1)); + end + + if (errcount == 0) begin + $display("All tests passed."); + $finish; + end else begin + $display("Caught %1d errors.", errcount); + $stop; + end + end + + macc2 ref ( + .clk(clk), + .ce(ce), + .rst(rst), + .a(a), + .b(b), + .accum_out(REF_accum_out), + .overflow(REF_overflow) + ); + + macc2_uut uut ( + .clk(clk), + .ce(ce), + .rst(rst), + .a(a), + .b(b), + .accum_out(accum_out), + .overflow(overflow) + ); +endmodule diff --git a/tests/arch/analogdevices/mul.ys b/tests/arch/analogdevices/mul.ys new file mode 100644 index 000000000..d20159a12 --- /dev/null +++ b/tests/arch/analogdevices/mul.ys @@ -0,0 +1,9 @@ +read_verilog ../common/mul.v +hierarchy -top top +proc +equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:DSP48E1 +select -assert-none t:DSP48E1 %% t:* %D diff --git a/tests/arch/analogdevices/mul_unsigned.v b/tests/arch/analogdevices/mul_unsigned.v new file mode 100644 index 000000000..e3713a642 --- /dev/null +++ b/tests/arch/analogdevices/mul_unsigned.v @@ -0,0 +1,30 @@ +/* +Example from: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf [p. 89]. +*/ + +// Unsigned 16x24-bit Multiplier +// 1 latency stage on operands +// 3 latency stage after the multiplication +// File: multipliers2.v +// +module mul_unsigned (clk, A, B, RES); +parameter WIDTHA = /*16*/ 6; +parameter WIDTHB = /*24*/ 9; +input clk; +input [WIDTHA-1:0] A; +input [WIDTHB-1:0] B; +output [WIDTHA+WIDTHB-1:0] RES; +reg [WIDTHA-1:0] rA; +reg [WIDTHB-1:0] rB; +reg [WIDTHA+WIDTHB-1:0] M [3:0]; +integer i; +always @(posedge clk) + begin + rA <= A; + rB <= B; + M[0] <= rA * rB; + for (i = 0; i < 3; i = i+1) + M[i+1] <= M[i]; + end +assign RES = M[3]; +endmodule diff --git a/tests/arch/analogdevices/mul_unsigned.ys b/tests/arch/analogdevices/mul_unsigned.ys new file mode 100644 index 000000000..99a0a3f0d --- /dev/null +++ b/tests/arch/analogdevices/mul_unsigned.ys @@ -0,0 +1,11 @@ +read_verilog mul_unsigned.v +hierarchy -top mul_unsigned +proc + +equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mul_unsigned # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:DSP48E1 +select -assert-count 30 t:FFRE +select -assert-none t:DSP48E1 t:FFRE t:BUFG %% t:* %D diff --git a/tests/arch/analogdevices/mux.ys b/tests/arch/analogdevices/mux.ys new file mode 100644 index 000000000..579519ce5 --- /dev/null +++ b/tests/arch/analogdevices/mux.ys @@ -0,0 +1,50 @@ +read_verilog ../common/mux.v +design -save read + +hierarchy -top mux2 +proc +equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT3 + +select -assert-none t:LUT3 %% t:* %D + + +design -load read +hierarchy -top mux4 +proc +equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT6 + +select -assert-none t:LUT6 %% t:* %D + + +design -load read +hierarchy -top mux8 +proc +equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT3 +select -assert-count 2 t:LUT6 + +select -assert-none t:LUT3 t:LUT6 %% t:* %D + + +design -load read +hierarchy -top mux16 +proc +equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-max 2 t:LUT3 +select -assert-max 2 t:LUT4 +select -assert-min 4 t:LUT6 +select -assert-max 7 t:LUT6 +select -assert-max 2 t:MUXF7 +dump + +select -assert-none t:LUT6 t:LUT4 t:LUT3 t:MUXF7 %% t:* %D diff --git a/tests/arch/analogdevices/opt_lut_ins.ys b/tests/arch/analogdevices/opt_lut_ins.ys new file mode 100644 index 000000000..0f312b4ca --- /dev/null +++ b/tests/arch/analogdevices/opt_lut_ins.ys @@ -0,0 +1,26 @@ +read_rtlil << EOF + +module \top + + wire width 4 input 1 \A + + wire output 2 \O + + cell \LUT4 $0 + parameter \INIT 16'1111110011000000 + connect \I0 \A [0] + connect \I1 \A [1] + connect \I2 \A [2] + connect \I3 \A [3] + connect \O \O + end +end + +EOF + +read_verilog -lib +/analogdevices/cells_sim.v +equiv_opt -assert -map +/analogdevices/cells_sim.v opt_lut_ins -tech xilinx + +design -load postopt + +select -assert-count 1 t:LUT3 diff --git a/tests/arch/analogdevices/run-test.sh b/tests/arch/analogdevices/run-test.sh new file mode 100755 index 000000000..691b70966 --- /dev/null +++ b/tests/arch/analogdevices/run-test.sh @@ -0,0 +1,4 @@ +#!/usr/bin/env bash +set -eu +source ../../gen-tests-makefile.sh +generate_mk --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'" diff --git a/tests/arch/analogdevices/shifter.ys b/tests/arch/analogdevices/shifter.ys new file mode 100644 index 000000000..6eab4bee5 --- /dev/null +++ b/tests/arch/analogdevices/shifter.ys @@ -0,0 +1,11 @@ +read_verilog ../common/shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:BUFG +select -assert-count 8 t:FFRE +select -assert-none t:BUFG t:FFRE %% t:* %D diff --git a/tests/arch/analogdevices/tribuf.ys b/tests/arch/analogdevices/tribuf.ys new file mode 100644 index 000000000..0be9f8d6f --- /dev/null +++ b/tests/arch/analogdevices/tribuf.ys @@ -0,0 +1,13 @@ +read_verilog ../common/tribuf.v +hierarchy -top tristate +proc +tribuf +flatten +synth +equiv_opt -assert -map +/analogdevices/cells_sim.v -map +/simcells.v synth_analogdevices # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristate # Constrain all select calls below inside the top module +select -assert-count 2 t:INBUF +select -assert-count 1 t:INV +select -assert-count 1 t:OBUFT +select -assert-none t:INBUF t:INV t:OBUFT %% t:* %D From f659cbd1596fb775ba3cd2de6060111626f1201d Mon Sep 17 00:00:00 2001 From: Lofty Date: Thu, 25 Sep 2025 15:09:16 +0100 Subject: [PATCH 254/291] analogdevices: remove some extra cells! --- techlibs/analogdevices/cells_sim.v | 42 ----------- techlibs/analogdevices/cells_xtra.v | 104 ---------------------------- 2 files changed, 146 deletions(-) diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v index 286619f71..e1e8aae8b 100644 --- a/techlibs/analogdevices/cells_sim.v +++ b/techlibs/analogdevices/cells_sim.v @@ -1347,48 +1347,6 @@ endmodule // Dual port. -module RAM16X1D ( - output DPO, SPO, - input D, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE, - input A0, A1, A2, A3, - input DPRA0, DPRA1, DPRA2, DPRA3 -); - parameter INIT = 16'h0; - parameter IS_WCLK_INVERTED = 1'b0; - wire [3:0] a = {A3, A2, A1, A0}; - wire [3:0] dpra = {DPRA3, DPRA2, DPRA1, DPRA0}; - reg [15:0] mem = INIT; - assign SPO = mem[a]; - assign DPO = mem[dpra]; - wire clk = WCLK ^ IS_WCLK_INVERTED; - always @(posedge clk) if (WE) mem[a] <= D; -endmodule - -module RAM16X1D_1 ( - output DPO, SPO, - input D, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE, - input A0, A1, A2, A3, - input DPRA0, DPRA1, DPRA2, DPRA3 -); - parameter INIT = 16'h0; - parameter IS_WCLK_INVERTED = 1'b0; - wire [3:0] a = {A3, A2, A1, A0}; - wire [3:0] dpra = {DPRA3, DPRA2, DPRA1, DPRA0}; - reg [15:0] mem = INIT; - assign SPO = mem[a]; - assign DPO = mem[dpra]; - wire clk = WCLK ^ IS_WCLK_INVERTED; - always @(negedge clk) if (WE) mem[a] <= D; -endmodule - (* abc9_box, lib_whitebox *) module RAM32X1D ( output DPO, SPO, diff --git a/techlibs/analogdevices/cells_xtra.v b/techlibs/analogdevices/cells_xtra.v index d12546aa7..d6e890751 100644 --- a/techlibs/analogdevices/cells_xtra.v +++ b/techlibs/analogdevices/cells_xtra.v @@ -6167,28 +6167,6 @@ module IDDR_2CLK (...); input S; endmodule -module ODDR (...); - parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; - parameter INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D1_INVERTED = 1'b0; - parameter [0:0] IS_D2_INVERTED = 1'b0; - parameter SRTYPE = "SYNC"; - parameter MSGON = "TRUE"; - parameter XON = "TRUE"; - output Q; - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C; - input CE; - (* invertible_pin = "IS_D1_INVERTED" *) - input D1; - (* invertible_pin = "IS_D2_INVERTED" *) - input D2; - input R; - input S; -endmodule - (* keep *) module IDELAYCTRL (...); parameter SIM_DEVICE = "7SERIES"; @@ -6598,77 +6576,6 @@ module ISERDESE2 (...); input SHIFTIN2; endmodule -module OSERDESE2 (...); - parameter DATA_RATE_OQ = "DDR"; - parameter DATA_RATE_TQ = "DDR"; - parameter integer DATA_WIDTH = 4; - parameter [0:0] INIT_OQ = 1'b0; - parameter [0:0] INIT_TQ = 1'b0; - parameter [0:0] IS_CLKDIV_INVERTED = 1'b0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [0:0] IS_D1_INVERTED = 1'b0; - parameter [0:0] IS_D2_INVERTED = 1'b0; - parameter [0:0] IS_D3_INVERTED = 1'b0; - parameter [0:0] IS_D4_INVERTED = 1'b0; - parameter [0:0] IS_D5_INVERTED = 1'b0; - parameter [0:0] IS_D6_INVERTED = 1'b0; - parameter [0:0] IS_D7_INVERTED = 1'b0; - parameter [0:0] IS_D8_INVERTED = 1'b0; - parameter [0:0] IS_T1_INVERTED = 1'b0; - parameter [0:0] IS_T2_INVERTED = 1'b0; - parameter [0:0] IS_T3_INVERTED = 1'b0; - parameter [0:0] IS_T4_INVERTED = 1'b0; - parameter SERDES_MODE = "MASTER"; - parameter [0:0] SRVAL_OQ = 1'b0; - parameter [0:0] SRVAL_TQ = 1'b0; - parameter TBYTE_CTL = "FALSE"; - parameter TBYTE_SRC = "FALSE"; - parameter integer TRISTATE_WIDTH = 4; - output OFB; - output OQ; - output SHIFTOUT1; - output SHIFTOUT2; - output TBYTEOUT; - output TFB; - output TQ; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKDIV_INVERTED" *) - input CLKDIV; - (* invertible_pin = "IS_D1_INVERTED" *) - input D1; - (* invertible_pin = "IS_D2_INVERTED" *) - input D2; - (* invertible_pin = "IS_D3_INVERTED" *) - input D3; - (* invertible_pin = "IS_D4_INVERTED" *) - input D4; - (* invertible_pin = "IS_D5_INVERTED" *) - input D5; - (* invertible_pin = "IS_D6_INVERTED" *) - input D6; - (* invertible_pin = "IS_D7_INVERTED" *) - input D7; - (* invertible_pin = "IS_D8_INVERTED" *) - input D8; - input OCE; - input RST; - input SHIFTIN1; - input SHIFTIN2; - (* invertible_pin = "IS_T1_INVERTED" *) - input T1; - (* invertible_pin = "IS_T2_INVERTED" *) - input T2; - (* invertible_pin = "IS_T3_INVERTED" *) - input T3; - (* invertible_pin = "IS_T4_INVERTED" *) - input T4; - input TBYTEIN; - input TCE; -endmodule - (* keep *) module PHASER_IN (...); parameter integer CLKOUT_DIV = 4; @@ -7906,17 +7813,6 @@ module IOBUFDSE3 (...); input T; endmodule -module OBUFDS (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - (* iopad_external_pin *) - output O; - (* iopad_external_pin *) - output OB; - input I; -endmodule - module OBUFDS_DPHY (...); parameter IOSTANDARD = "DEFAULT"; (* iopad_external_pin *) From c9f6d7b2d43cee271ebe6ec7a84294a89abfec17 Mon Sep 17 00:00:00 2001 From: Lofty Date: Tue, 30 Sep 2025 10:02:19 +0100 Subject: [PATCH 255/291] analogdevices: more housekeeping --- techlibs/analogdevices/cells_sim.v | 72 +----------------------------- 1 file changed, 1 insertion(+), 71 deletions(-) diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v index e1e8aae8b..019db5550 100644 --- a/techlibs/analogdevices/cells_sim.v +++ b/techlibs/analogdevices/cells_sim.v @@ -273,7 +273,7 @@ module LUT6(output O, input I0, I1, I2, I3, I4, I5); endspecify endmodule -module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5); +module LUT6_D(output O6, output O5, input I0, I1, I2, I3, I4, I5); parameter [63:0] INIT = 0; wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0]; wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0]; @@ -583,76 +583,6 @@ module FFSE_N ( endspecify endmodule -module FFRSE ( - output reg Q, - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C, - (* invertible_pin = "IS_CE_INVERTED" *) - input CE, - (* invertible_pin = "IS_D_INVERTED" *) - input D, - (* invertible_pin = "IS_R_INVERTED" *) - input R, - (* invertible_pin = "IS_S_INVERTED" *) - input S -); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_CE_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_R_INVERTED = 1'b0; - parameter [0:0] IS_S_INVERTED = 1'b0; - initial Q <= INIT; - wire c = C ^ IS_C_INVERTED; - wire ce = CE ^ IS_CE_INVERTED; - wire d = D ^ IS_D_INVERTED; - wire r = R ^ IS_R_INVERTED; - wire s = S ^ IS_S_INVERTED; - always @(posedge c) - if (r) - Q <= 0; - else if (s) - Q <= 1; - else if (ce) - Q <= d; -endmodule - -module FFRSE_N ( - output reg Q, - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C, - (* invertible_pin = "IS_CE_INVERTED" *) - input CE, - (* invertible_pin = "IS_D_INVERTED" *) - input D, - (* invertible_pin = "IS_R_INVERTED" *) - input R, - (* invertible_pin = "IS_S_INVERTED" *) - input S -); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_CE_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_R_INVERTED = 1'b0; - parameter [0:0] IS_S_INVERTED = 1'b0; - initial Q <= INIT; - wire c = C ^ IS_C_INVERTED; - wire ce = CE ^ IS_CE_INVERTED; - wire d = D ^ IS_D_INVERTED; - wire r = R ^ IS_R_INVERTED; - wire s = S ^ IS_S_INVERTED; - always @(negedge c) - if (r) - Q <= 0; - else if (s) - Q <= 1; - else if (ce) - Q <= d; -endmodule - (* abc9_box, lib_whitebox *) module FFCE ( output reg Q, From 85eb07d14da262df89d9250718d4379c5ca3285a Mon Sep 17 00:00:00 2001 From: Lofty Date: Tue, 30 Sep 2025 10:02:44 +0100 Subject: [PATCH 256/291] analogdevices: user retargeting --- techlibs/analogdevices/retarget_map.v | 49 +++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 techlibs/analogdevices/retarget_map.v diff --git a/techlibs/analogdevices/retarget_map.v b/techlibs/analogdevices/retarget_map.v new file mode 100644 index 000000000..a9712219f --- /dev/null +++ b/techlibs/analogdevices/retarget_map.v @@ -0,0 +1,49 @@ +module FF (input C, D, output Q); +parameter INIT = 1'b0; +if (INIT === 1'b1) begin +FFPE _TECHMAP_REPLACE_ (.C(C), .D(D), .PRE(1'b0), .CE(1'b1), .Q(Q)); +end else begin +FFCE _TECHMAP_REPLACE_ (.C(C), .D(D), .CLR(1'b0), .CE(1'b1), .Q(Q)); +end +endmodule + +module FF_N (input C, D, output Q); +parameter INIT = 1'b0; +if (INIT === 1'b1) begin +FFPE_N _TECHMAP_REPLACE_ (.C(C), .D(D), .PRE(1'b0), .CE(1'b1), .Q(Q)); +end else begin +FFCE_N _TECHMAP_REPLACE_ (.C(C), .D(D), .CLR(1'b0), .CE(1'b1), .Q(Q)); +end +endmodule + +module FFC (input C, D, CLR, output Q); +FFCE _TECHMAP_REPLACE_ (.C(C), .D(D), .CLR(CLR), .CE(1'b1), .Q(Q)); +endmodule + +module FFC_N (input C, D, CLR, output Q); +FFCE_N _TECHMAP_REPLACE_ (.C(C), .D(D), .CLR(CLR), .CE(1'b1), .Q(Q)); +endmodule + +module FFP (input C, D, PRE, output Q); +FFPE _TECHMAP_REPLACE_ (.C(C), .D(D), .PRE(PRE), .CE(1'b1), .Q(Q)); +endmodule + +module FFP_N (input C, D, CLR, output Q); +FFPE_N _TECHMAP_REPLACE_ (.C(C), .D(D), .PRE(PRE), .CE(1'b1), .Q(Q)); +endmodule + +module FFR (input C, D, R, output Q); +FFRE _TECHMAP_REPLACE_ (.C(C), .D(D), .R(R), .CE(1'b1), .Q(Q)); +endmodule + +module FFR_N (input C, D, R, output Q); +FFRE_N _TECHMAP_REPLACE_ (.C(C), .D(D), .R(R), .CE(1'b1), .Q(Q)); +endmodule + +module FFS (input C, D, S, output Q); +FFSE _TECHMAP_REPLACE_ (.C(C), .D(D), .S(S), .CE(1'b1), .Q(Q)); +endmodule + +module FFS_N (input C, D, S, output Q); +FFSE_N _TECHMAP_REPLACE_ (.C(C), .D(D), .S(S), .CE(1'b1), .Q(Q)); +endmodule From c4bec4e8b8cb27a8e8194a37f954680751b414eb Mon Sep 17 00:00:00 2001 From: Lofty Date: Wed, 1 Oct 2025 12:47:21 +0100 Subject: [PATCH 257/291] I thought I removed this... --- backends/edif/edif.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 12d035e49..145477b6b 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -82,7 +82,6 @@ struct EdifNames used_names.count(gen_name) == 0) break; } - log("renamed '%s' to '%s'\n", id, gen_name); generated_names.insert(gen_name); name_map[id] = gen_name; return gen_name; From ae5325fe53a0fcbfae159f4450d7f94edd11ae08 Mon Sep 17 00:00:00 2001 From: Lofty Date: Wed, 1 Oct 2025 20:13:29 +0100 Subject: [PATCH 258/291] analogdevices: update timing model --- techlibs/analogdevices/arith_map.v | 24 +- techlibs/analogdevices/cells_sim.v | 565 +++++------------- techlibs/analogdevices/lut_map.v | 2 +- techlibs/analogdevices/synth_analogdevices.cc | 2 +- 4 files changed, 168 insertions(+), 425 deletions(-) diff --git a/techlibs/analogdevices/arith_map.v b/techlibs/analogdevices/arith_map.v index 288e1eccf..394a5a957 100644 --- a/techlibs/analogdevices/arith_map.v +++ b/techlibs/analogdevices/arith_map.v @@ -50,10 +50,18 @@ generate generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice if (i == 0) begin - CRY4 carry4 + wire INITCO; + + CRY4INIT init ( .CYINIT(CI), - .CI (1'd0), + .CO (INITCO) + ); + + CRY4 carry4 + ( + .CYINIT(1'd0), + .CI (INITCO), .DI (GG[i*4 +: 4]), .S (S [i*4 +: 4]), .CO (C [i*4 +: 4]), @@ -130,10 +138,18 @@ module _80_analogdevices_alu (A, B, CI, BI, X, Y, CO); genvar i; generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice if (i == 0) begin - CRY4 carry4 + wire INITCO; + + CRY4INIT init ( .CYINIT(CI), - .CI (1'd0), + .CO (INITCO) + ); + + CRY4 carry4 + ( + .CYINIT(1'd0), + .CI (INITCO), .DI (DI[i*4 +: 4]), .S (S [i*4 +: 4]), .O (O [i*4 +: 4]), diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v index 019db5550..9a64f7454 100644 --- a/techlibs/analogdevices/cells_sim.v +++ b/techlibs/analogdevices/cells_sim.v @@ -17,10 +17,6 @@ * */ -// See Analog Devices UG953 and UG474 for a description of the cell types below. -// http://www.analogdevices.com/support/documentation/user_guides/ug474_7Series_CLB.pdf -// http://www.analogdevices.com/support/documentation/sw_manuals/analogdevices2014_4/ug953-vivado-7series-libraries.pdf - module VDD(output P); assign P = 1; endmodule @@ -41,7 +37,7 @@ module INBUF( parameter IOSTANDARD = "DEFAULT"; assign O = I; specify - (I => O) = 0; + (I => O) = 22; endspecify endmodule @@ -66,7 +62,7 @@ module OUTBUF( parameter SLEW = "SLOW"; assign O = I; specify - (I => O) = 0; + (I => O) = 22; endspecify endmodule @@ -182,7 +178,7 @@ module INV( ); assign O = !I; specify - (I => O) = 127; + (I => O) = 22; endspecify endmodule @@ -191,7 +187,7 @@ module LUT1(output O, input I0); parameter [1:0] INIT = 0; assign O = I0 ? INIT[1] : INIT[0]; specify - (I0 => O) = 127; + (I0 => O) = 22; endspecify endmodule @@ -201,8 +197,8 @@ module LUT2(output O, input I0, I1); wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0]; assign O = I0 ? s1[1] : s1[0]; specify - (I0 => O) = 238; - (I1 => O) = 127; + (I0 => O) = 22; + (I1 => O) = 22; endspecify endmodule @@ -213,13 +209,13 @@ module LUT3(output O, input I0, I1, I2); wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; assign O = I0 ? s1[1] : s1[0]; specify - (I0 => O) = 407; - (I1 => O) = 238; - (I2 => O) = 127; + (I0 => O) = 22; + (I1 => O) = 22; + (I2 => O) = 22; endspecify endmodule -(* abc9_lut=3 *) +(* abc9_lut=4 *) module LUT4(output O, input I0, I1, I2, I3); parameter [15:0] INIT = 0; wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0]; @@ -227,14 +223,14 @@ module LUT4(output O, input I0, I1, I2, I3); wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; assign O = I0 ? s1[1] : s1[0]; specify - (I0 => O) = 472; - (I1 => O) = 407; - (I2 => O) = 238; - (I3 => O) = 127; + (I0 => O) = 22; + (I1 => O) = 22; + (I2 => O) = 22; + (I3 => O) = 22; endspecify endmodule -(* abc9_lut=3 *) +(* abc9_lut=5 *) module LUT5(output O, input I0, I1, I2, I3, I4); parameter [31:0] INIT = 0; wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0]; @@ -243,18 +239,15 @@ module LUT5(output O, input I0, I1, I2, I3, I4); wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; assign O = I0 ? s1[1] : s1[0]; specify - (I0 => O) = 631; - (I1 => O) = 472; - (I2 => O) = 407; - (I3 => O) = 238; - (I4 => O) = 127; + (I0 => O) = 22; + (I1 => O) = 22; + (I2 => O) = 22; + (I3 => O) = 22; + (I4 => O) = 22; endspecify endmodule -// This is a placeholder for ABC9 to extract the area/delay -// cost of 3-input LUTs and is not intended to be instantiated - -(* abc9_lut=5 *) +(* abc9_lut=6 *) module LUT6(output O, input I0, I1, I2, I3, I4, I5); parameter [63:0] INIT = 0; wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0]; @@ -264,12 +257,12 @@ module LUT6(output O, input I0, I1, I2, I3, I4, I5); wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; assign O = I0 ? s1[1] : s1[0]; specify - (I0 => O) = 642; - (I1 => O) = 631; - (I2 => O) = 472; - (I3 => O) = 407; - (I4 => O) = 238; - (I5 => O) = 127; + (I0 => O) = 22; + (I1 => O) = 22; + (I2 => O) = 22; + (I3 => O) = 22; + (I4 => O) = 22; + (I5 => O) = 22; endspecify endmodule @@ -291,37 +284,35 @@ endmodule // This is a placeholder for ABC9 to extract the area/delay // cost of 3-input LUTs and is not intended to be instantiated -(* abc9_lut=10 *) +(* abc9_lut=12 *) module \$__ABC9_LUT7 (output O, input I0, I1, I2, I3, I4, I5, I6); `ifndef __ICARUS__ specify - // https://github.com/SymbiFlow/prjxray-db/blob/1c85daf1b115da4d27ca83c6b89f53a94de39748/artix7/timings/slicel.sdf#L867 - (I0 => O) = 642 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; - (I1 => O) = 631 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; - (I2 => O) = 472 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; - (I3 => O) = 407 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; - (I4 => O) = 238 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; - (I5 => O) = 127 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; - (I6 => O) = 0 + 296 /* to select F7BMUX */ + 174 /* CMUX */; + (I0 => O) = 22 + 63 /* LUTMUX7.I1 */; + (I1 => O) = 22 + 63 /* LUTMUX7.I1 */; + (I2 => O) = 22 + 63 /* LUTMUX7.I1 */; + (I3 => O) = 22 + 63 /* LUTMUX7.I1 */; + (I4 => O) = 22 + 63 /* LUTMUX7.I1 */; + (I5 => O) = 22 + 63 /* LUTMUX7.I1 */; + (I6 => O) = 0 + 51 /* LUTMUX7.S */; endspecify `endif endmodule // This is a placeholder for ABC9 to extract the area/delay // cost of 3-input LUTs and is not intended to be instantiated -(* abc9_lut=20 *) +(* abc9_lut=24 *) module \$__ABC9_LUT8 (output O, input I0, I1, I2, I3, I4, I5, I6, I7); `ifndef __ICARUS__ specify - // https://github.com/SymbiFlow/prjxray-db/blob/1c85daf1b115da4d27ca83c6b89f53a94de39748/artix7/timings/slicel.sdf#L716 - (I0 => O) = 642 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */; - (I1 => O) = 631 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */; - (I2 => O) = 472 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */; - (I3 => O) = 407 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */; - (I4 => O) = 238 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */; - (I5 => O) = 127 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */; - (I6 => O) = 0 + 296 /* to select F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */; - (I7 => O) = 0 + 0 + 273 /* to select F8MUX */ + 192 /* BMUX */; + (I0 => O) = 22 + 63 /* LUTMUX7.I1 */ + 48 /* LUTMUX8.I0 */; + (I1 => O) = 22 + 63 /* LUTMUX7.I1 */ + 48 /* LUTMUX8.I0 */; + (I2 => O) = 22 + 63 /* LUTMUX7.I1 */ + 48 /* LUTMUX8.I0 */; + (I3 => O) = 22 + 63 /* LUTMUX7.I1 */ + 48 /* LUTMUX8.I0 */; + (I4 => O) = 22 + 63 /* LUTMUX7.I1 */ + 48 /* LUTMUX8.I0 */; + (I5 => O) = 22 + 63 /* LUTMUX7.I1 */ + 48 /* LUTMUX8.I0 */; + (I6 => O) = 0 + 51 /* LUTMUX7.S */ + 48 /* LUTMUX8.I0 */; + (I7 => O) = 0 + 0 + 58 /* LUTMUX8.S */; endspecify `endif endmodule @@ -330,10 +321,9 @@ endmodule module LUTMUX7(output O, input I0, I1, S); assign O = S ? I1 : I0; specify - // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L451-L453 - (I0 => O) = 217; - (I1 => O) = 223; - (S => O) = 296; + (I0 => O) = 62; + (I1 => O) = 63; + (S => O) = 51; endspecify endmodule @@ -341,10 +331,9 @@ endmodule module LUTMUX8(output O, input I0, I1, S); assign O = S ? I1 : I0; specify - // Max delays from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L462-L464 - (I0 => O) = 104; - (I1 => O) = 94; - (S => O) = 273; + (I0 => O) = 48; + (I1 => O) = 46; + (S => O) = 58; endspecify endmodule @@ -365,79 +354,65 @@ module CRY4( assign CO[3] = S[3] ? CO[2] : DI[3]; specify // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L11-L46 - (CYINIT => O[0]) = 482; - (S[0] => O[0]) = 223; - (CI => O[0]) = 222; - (CYINIT => O[1]) = 598; - (DI[0] => O[1]) = 407; - (S[0] => O[1]) = 400; - (S[1] => O[1]) = 205; - (CI => O[1]) = 334; - (CYINIT => O[2]) = 584; - (DI[0] => O[2]) = 556; - (DI[1] => O[2]) = 537; - (S[0] => O[2]) = 523; - (S[1] => O[2]) = 558; - (S[2] => O[2]) = 226; - (CI => O[2]) = 239; - (CYINIT => O[3]) = 642; - (DI[0] => O[3]) = 615; - (DI[1] => O[3]) = 596; - (DI[2] => O[3]) = 438; - (S[0] => O[3]) = 582; - (S[1] => O[3]) = 618; - (S[2] => O[3]) = 330; - (S[3] => O[3]) = 227; - (CI => O[3]) = 313; - (CYINIT => CO[0]) = 536; - (DI[0] => CO[0]) = 379; - (S[0] => CO[0]) = 340; - (CI => CO[0]) = 271; - (CYINIT => CO[1]) = 494; - (DI[0] => CO[1]) = 465; - (DI[1] => CO[1]) = 445; - (S[0] => CO[1]) = 433; - (S[1] => CO[1]) = 469; - (CI => CO[1]) = 157; - (CYINIT => CO[2]) = 592; - (DI[0] => CO[2]) = 540; - (DI[1] => CO[2]) = 520; - (DI[2] => CO[2]) = 356; - (S[0] => CO[2]) = 512; - (S[1] => CO[2]) = 548; - (S[2] => CO[2]) = 292; - (CI => CO[2]) = 228; - (CYINIT => CO[3]) = 580; - (DI[0] => CO[3]) = 526; - (DI[1] => CO[3]) = 507; - (DI[2] => CO[3]) = 398; - (DI[3] => CO[3]) = 385; - (S[0] => CO[3]) = 508; - (S[1] => CO[3]) = 528; - (S[2] => CO[3]) = 378; - (S[3] => CO[3]) = 380; - (CI => CO[3]) = 114; + (S[0] => O[0]) = 39; + (CI => O[0]) = 43; + (DI[0] => O[1]) = 81; + (S[0] => O[1]) = 61; + (S[1] => O[1]) = 42; + (CI => O[1]) = 50; + (DI[0] => O[2]) = 98; + (DI[1] => O[2]) = 95; + (S[0] => O[2]) = 70; + (S[1] => O[2]) = 75; + (S[2] => O[2]) = 48; + (CI => O[2]) = 64; + (DI[0] => O[3]) = 101; + (DI[1] => O[3]) = 120; + (DI[2] => O[3]) = 65; + (S[0] => O[3]) = 69; + (S[1] => O[3]) = 91; + (S[2] => O[3]) = 42; + (S[3] => O[3]) = 39; + (CI => O[3]) = 84; + (DI[0] => CO[0]) = 59; + (S[0] => CO[0]) = 43; + (CI => CO[0]) = 50; + (DI[0] => CO[1]) = 87; + (DI[1] => CO[1]) = 64; + (S[0] => CO[1]) = 63; + (S[1] => CO[1]) = 51; + (CI => CO[1]) = 55; + (DI[0] => CO[2]) = 103; + (DI[1] => CO[2]) = 113; + (DI[2] => CO[2]) = 58; + (S[0] => CO[2]) = 68; + (S[1] => CO[2]) = 79; + (S[2] => CO[2]) = 37; + (CI => CO[2]) = 77; + (DI[0] => CO[3]) = 93; + (DI[1] => CO[3]) = 95; + (DI[2] => CO[3]) = 84; + (DI[3] => CO[3]) = 72; + (S[0] => CO[3]) = 91; + (S[1] => CO[3]) = 97; + (S[2] => CO[3]) = 82; + (S[3] => CO[3]) = 81; + (CI => CO[3]) = 20; endspecify endmodule -module CARRY8( - output [7:0] CO, - output [7:0] O, - input CI, - input CI_TOP, - input [7:0] DI, S +(* abc9_box, lib_whitebox *) +module CRY4INIT( + (* abc9_carry *) + output CO, + (* abc9_carry *) + input CYINIT ); - parameter CARRY_TYPE = "SINGLE_CY8"; - wire CI4 = (CARRY_TYPE == "DUAL_CY4" ? CI_TOP : CO[3]); - assign O = S ^ {CO[6:4], CI4, CO[2:0], CI}; - assign CO[0] = S[0] ? CI : DI[0]; - assign CO[1] = S[1] ? CO[0] : DI[1]; - assign CO[2] = S[2] ? CO[1] : DI[2]; - assign CO[3] = S[3] ? CO[2] : DI[3]; - assign CO[4] = S[4] ? CI4 : DI[4]; - assign CO[5] = S[5] ? CO[4] : DI[5]; - assign CO[6] = S[6] ? CO[5] : DI[6]; - assign CO[7] = S[7] ? CO[6] : DI[7]; + specify + (CYINIT => CO) = 72; + endspecify + + assign CO = CYINIT; endmodule module ORCY (output O, input CI, I); @@ -448,48 +423,26 @@ module MULT_AND (output LO, input I0, I1); assign LO = I0 & I1; endmodule -// Flip-flops and latches. - -// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250 +// Flip-flops. (* abc9_flop, lib_whitebox *) module FFRE ( output reg Q, (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) input C, input CE, - (* invertible_pin = "IS_D_INVERTED" *) input D, - (* invertible_pin = "IS_R_INVERTED" *) input R ); parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_R_INVERTED = 1'b0; initial Q <= INIT; - generate - case (|IS_C_INVERTED) - 1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; - 1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; - endcase - endgenerate + always @(posedge C) if (R) Q <= 1'b0; else if (CE) Q <= D; specify - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 - $setup(D , posedge C &&& CE && !IS_C_INVERTED , /*-46*/ 0); // Negative times not currently supported - $setup(D , negedge C &&& CE && IS_C_INVERTED , /*-46*/ 0); // Negative times not currently supported - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 - $setup(CE, posedge C &&& !IS_C_INVERTED, 109); - $setup(CE, negedge C &&& IS_C_INVERTED, 109); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 - $setup(R , posedge C &&& !IS_C_INVERTED, 404); - $setup(R , negedge C &&& IS_C_INVERTED, 404); - // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243 - if (!IS_C_INVERTED && R != IS_R_INVERTED) (posedge C => (Q : 1'b0)) = 303; - if ( IS_C_INVERTED && R != IS_R_INVERTED) (negedge C => (Q : 1'b0)) = 303; - if (!IS_C_INVERTED && R == IS_R_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303; - if ( IS_C_INVERTED && R == IS_R_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303; + $setup(D , posedge C, 31); + $setup(CE, posedge C, 122); + $setup(R , posedge C, 128); + if (R) (posedge C => (Q : 1'b0)) = 280; + if (!R && CE) (posedge C => (Q : D)) = 280; endspecify endmodule @@ -506,59 +459,34 @@ module FFRE_N ( initial Q <= INIT; always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D; specify - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 - $setup(D , negedge C &&& CE, /*-46*/ 0); // Negative times not currently supported - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 - $setup(CE, negedge C, 109); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 - $setup(R , negedge C, 404); // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243 - if (R) (negedge C => (Q : 1'b0)) = 303; - if (!R && CE) (negedge C => (Q : D)) = 303; + $setup(D , negedge C, 31); + $setup(CE, negedge C, 122); + $setup(R , negedge C, 128); + if (R) (negedge C => (Q : 1'b0)) = 280; + if (!R && CE) (negedge C => (Q : D)) = 280; endspecify endmodule -(* abc9_flop, lib_whitebox *) module FFSE ( output reg Q, (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) input C, input CE, - (* invertible_pin = "IS_D_INVERTED" *) input D, - (* invertible_pin = "IS_S_INVERTED" *) input S ); parameter [0:0] INIT = 1'b1; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_S_INVERTED = 1'b0; initial Q <= INIT; - generate - case (|IS_C_INVERTED) - 1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; - 1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; - endcase - endgenerate + always @(posedge C) if (S) Q <= 1'b1; else if (CE) Q <= D; specify - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 - $setup(D , posedge C &&& !IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported - $setup(D , negedge C &&& IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 - $setup(CE, posedge C &&& !IS_C_INVERTED, 109); - $setup(CE, negedge C &&& IS_C_INVERTED, 109); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 - $setup(S , posedge C &&& !IS_C_INVERTED, 404); - $setup(S , negedge C &&& IS_C_INVERTED, 404); - // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243 - if (!IS_C_INVERTED && S != IS_S_INVERTED) (posedge C => (Q : 1'b1)) = 303; - if ( IS_C_INVERTED && S != IS_S_INVERTED) (negedge C => (Q : 1'b1)) = 303; - if (!IS_C_INVERTED && S == IS_S_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303; - if ( IS_C_INVERTED && S == IS_S_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303; + $setup(D , posedge C, 31); + $setup(CE, posedge C, 122); + $setup(S , posedge C, 128); + if (S) (negedge C => (Q : 1'b1)) = 280; + if (!S && CE) (posedge C => (Q : D)) = 280; endspecify endmodule -(* abc9_flop, lib_whitebox *) module FFSE_N ( output reg Q, (* clkbuf_sink *) @@ -571,68 +499,32 @@ module FFSE_N ( initial Q <= INIT; always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D; specify - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 - $setup(D , negedge C &&& CE, /*-46*/ 0); // Negative times not currently supported - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 - $setup(CE, negedge C, 109); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 - $setup(S , negedge C, 404); - // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243 - if (S) (negedge C => (Q : 1'b1)) = 303; - if (!S && CE) (negedge C => (Q : D)) = 303; + $setup(D , negedge C, 31); + $setup(CE, negedge C, 122); + $setup(S , negedge C, 128); + if (S) (negedge C => (Q : 1'b1)) = 280; + if (!S && CE) (negedge C => (Q : D)) = 280; endspecify endmodule -(* abc9_box, lib_whitebox *) module FFCE ( output reg Q, (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) input C, input CE, - (* invertible_pin = "IS_CLR_INVERTED" *) input CLR, - (* invertible_pin = "IS_D_INVERTED" *) input D ); parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_CLR_INVERTED = 1'b0; initial Q <= INIT; - generate - case ({|IS_C_INVERTED, |IS_CLR_INVERTED}) - 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; - 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; - 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; - 2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; - endcase - endgenerate + always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D; specify - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 - $setup(D , posedge C &&& !IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported - $setup(D , negedge C &&& IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 - $setup(CE , posedge C &&& !IS_C_INVERTED, 109); - $setup(CE , negedge C &&& IS_C_INVERTED, 109); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 - $setup(CLR, posedge C &&& !IS_C_INVERTED, 404); - $setup(CLR, negedge C &&& IS_C_INVERTED, 404); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270 -`ifndef YOSYS - if (!IS_CLR_INVERTED) (posedge CLR => (Q : 1'b0)) = 764; - if ( IS_CLR_INVERTED) (negedge CLR => (Q : 1'b0)) = 764; -`else - if (IS_CLR_INVERTED != CLR) (CLR => Q) = 764; // Technically, this should be an edge sensitive path - // but for facilitating a bypass box, let's pretend it's - // a simple path -`endif - if (!IS_C_INVERTED && CLR == IS_CLR_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303; - if ( IS_C_INVERTED && CLR == IS_CLR_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303; + $setup(D , posedge C, 31); + $setup(CE , posedge C, 122); + if (!CLR && CE) (posedge C => (Q : D)) = 280; endspecify endmodule -(* abc9_box, lib_whitebox *) module FFCE_N ( output reg Q, (* clkbuf_sink *) @@ -645,213 +537,48 @@ module FFCE_N ( initial Q <= INIT; always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D; specify - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 - $setup(D , negedge C &&& CE, /*-46*/ 0); // Negative times not currently supported - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 - $setup(CE , negedge C, 109); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 - $setup(CLR, negedge C, 404); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270 -`ifndef YOSYS - (posedge CLR => (Q : 1'b0)) = 764; -`else - if (CLR) (CLR => Q) = 764; // Technically, this should be an edge sensitive path - // but for facilitating a bypass box, let's pretend it's - // a simple path -`endif - if (!CLR && CE) (negedge C => (Q : D)) = 303; + $setup(D , negedge C, 31); + $setup(CE , negedge C, 122); + if (!CLR && CE) (negedge C => (Q : D)) = 280; endspecify endmodule -(* abc9_box, lib_whitebox *) module FFPE ( output reg Q, (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) input C, input CE, - (* invertible_pin = "IS_D_INVERTED" *) - input D, - (* invertible_pin = "IS_PRE_INVERTED" *) - input PRE + input PRE, + input D ); parameter [0:0] INIT = 1'b1; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_PRE_INVERTED = 1'b0; initial Q <= INIT; - generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED}) - 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; - 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; - 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; - 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; - endcase - endgenerate + always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D; specify - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 - $setup(D , posedge C &&& !IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported - $setup(D , negedge C &&& IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 - $setup(CE , posedge C &&& !IS_C_INVERTED, 109); - $setup(CE , negedge C &&& IS_C_INVERTED, 109); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 - $setup(PRE, posedge C &&& !IS_C_INVERTED, 404); - $setup(PRE, negedge C &&& IS_C_INVERTED, 404); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270 -`ifndef YOSYS - if (!IS_PRE_INVERTED) (posedge PRE => (Q : 1'b1)) = 764; - if ( IS_PRE_INVERTED) (negedge PRE => (Q : 1'b1)) = 764; -`else - if (IS_PRE_INVERTED != PRE) (PRE => Q) = 764; // Technically, this should be an edge sensitive path - // but for facilitating a bypass box, let's pretend it's - // a simple path -`endif - if (!IS_C_INVERTED && PRE == IS_PRE_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303; - if ( IS_C_INVERTED && PRE == IS_PRE_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303; + $setup(D , posedge C, 31); + $setup(CE , posedge C, 122); + if (!PRE && CE) (posedge C => (Q : D)) = 291; endspecify endmodule -(* abc9_box, lib_whitebox *) module FFPE_N ( output reg Q, (* clkbuf_sink *) input C, input CE, - input D, - input PRE + input PRE, + input D ); parameter [0:0] INIT = 1'b1; initial Q <= INIT; always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; specify - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 - $setup(D , negedge C &&& CE, /*-46*/ 0); // Negative times not currently supported - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 - $setup(CE , negedge C, 109); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 - $setup(PRE, negedge C, 404); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270 -`ifndef YOSYS - (posedge PRE => (Q : 1'b1)) = 764; -`else - if (PRE) (PRE => Q) = 764; // Technically, this should be an edge sensitive path - // but for facilitating a bypass box, let's pretend it's - // a simple path -`endif - if (!PRE && CE) (negedge C => (Q : D)) = 303; + $setup(D , negedge C, 31); + $setup(CE , negedge C, 122); + if (!PRE && CE) (negedge C => (Q : D)) = 291; endspecify endmodule -module FFCPE ( - output wire Q, - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C, - input CE, - (* invertible_pin = "IS_CLR_INVERTED" *) - input CLR, - input D, - (* invertible_pin = "IS_PRE_INVERTED" *) - input PRE -); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_CLR_INVERTED = 1'b0; - parameter [0:0] IS_PRE_INVERTED = 1'b0; - wire c = C ^ IS_C_INVERTED; - wire clr = CLR ^ IS_CLR_INVERTED; - wire pre = PRE ^ IS_PRE_INVERTED; - // Hacky model to avoid simulation-synthesis mismatches. - reg qc, qp, qs; - initial qc = INIT; - initial qp = INIT; - initial qs = 0; - always @(posedge c, posedge clr) begin - if (clr) - qc <= 0; - else if (CE) - qc <= D; - end - always @(posedge c, posedge pre) begin - if (pre) - qp <= 1; - else if (CE) - qp <= D; - end - always @* begin - if (clr) - qs <= 0; - else if (pre) - qs <= 1; - end - assign Q = qs ? qp : qc; -endmodule - -module FFCPE_N ( - output wire Q, - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C, - input CE, - (* invertible_pin = "IS_CLR_INVERTED" *) - input CLR, - input D, - (* invertible_pin = "IS_PRE_INVERTED" *) - input PRE -); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_CLR_INVERTED = 1'b0; - parameter [0:0] IS_PRE_INVERTED = 1'b0; - wire c = C ^ IS_C_INVERTED; - wire clr = CLR ^ IS_CLR_INVERTED; - wire pre = PRE ^ IS_PRE_INVERTED; - // Hacky model to avoid simulation-synthesis mismatches. - reg qc, qp, qs; - initial qc = INIT; - initial qp = INIT; - initial qs = 0; - always @(negedge c, posedge clr) begin - if (clr) - qc <= 0; - else if (CE) - qc <= D; - end - always @(negedge c, posedge pre) begin - if (pre) - qp <= 1; - else if (CE) - qp <= D; - end - always @* begin - if (clr) - qs <= 0; - else if (pre) - qs <= 1; - end - assign Q = qs ? qp : qc; -endmodule - -module AND2B1L ( - output O, - input DI, - (* invertible_pin = "IS_SRI_INVERTED" *) - input SRI -); - parameter [0:0] IS_SRI_INVERTED = 1'b0; - assign O = DI & ~(SRI ^ IS_SRI_INVERTED); -endmodule - -module OR2L ( - output O, - input DI, - (* invertible_pin = "IS_SRI_INVERTED" *) - input SRI -); - parameter [0:0] IS_SRI_INVERTED = 1'b0; - assign O = DI | (SRI ^ IS_SRI_INVERTED); -endmodule - // LUTRAM. // Single port. diff --git a/techlibs/analogdevices/lut_map.v b/techlibs/analogdevices/lut_map.v index d63bd7edb..a0b617b10 100644 --- a/techlibs/analogdevices/lut_map.v +++ b/techlibs/analogdevices/lut_map.v @@ -72,7 +72,7 @@ module \$lut (A, Y); wire f0, f1; \$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0)); \$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1)); - LUTMUX8 mux8(.I0(f0), .I1(f1), .S(A[7]), .O(Y)); + LUTMUX8 mux8 (.I0(f0), .I1(f1), .S(A[7]), .O(Y)); end else begin wire _TECHMAP_FAIL_ = 1; end diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc index 33ba520fa..1c183476d 100644 --- a/techlibs/analogdevices/synth_analogdevices.cc +++ b/techlibs/analogdevices/synth_analogdevices.cc @@ -464,7 +464,7 @@ struct SynthAnalogDevicesPass : public ScriptPass abc_opts += " -dff"; if (retime) abc_opts += " -D 1"; - run("abc" + abc_opts); + run("abc -dress" + abc_opts); } run("clean"); From 30a03886a5b7d818e2047a74b3352174e01b6dd5 Mon Sep 17 00:00:00 2001 From: Lofty Date: Thu, 9 Oct 2025 04:38:49 +0100 Subject: [PATCH 259/291] analogdevices: LUTRAM config --- techlibs/analogdevices/cells_sim.v | 2218 +---------------- techlibs/analogdevices/lutrams.txt | 45 +- techlibs/analogdevices/lutrams_map.v | 470 +--- techlibs/analogdevices/synth_analogdevices.cc | 2 +- 4 files changed, 191 insertions(+), 2544 deletions(-) diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v index 9a64f7454..c49a54e79 100644 --- a/techlibs/analogdevices/cells_sim.v +++ b/techlibs/analogdevices/cells_sim.v @@ -66,41 +66,6 @@ module OUTBUF( endspecify endmodule -module IOBUF ( - (* iopad_external_pin *) - inout IO, - output O, - input I, - input T -); - parameter integer DRIVE = 12; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - assign IO = T ? 1'bz : I; - assign O = IO; - specify - (I => IO) = 0; - (IO => O) = 0; - endspecify -endmodule - -module OBUFT ( - (* iopad_external_pin *) - output O, - input I, - input T -); - parameter CAPACITANCE = "DONT_CARE"; - parameter integer DRIVE = 12; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - assign O = T ? 1'bz : I; - specify - (I => O) = 0; - endspecify -endmodule - module BUFG( (* clkbuf_driver *) output O, @@ -163,14 +128,6 @@ assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT); endmodule -// module OBUFT(output O, input I, T); -// assign O = T ? 1'bz : I; -// endmodule - -// module IOBUF(inout IO, output O, input I, T); -// assign O = IO, IO = T ? 1'bz : I; -// endmodule - module INV( (* clkbuf_inv = "I" *) output O, @@ -583,1281 +540,186 @@ endmodule // Single port. -module RAM16X1S ( - output O, - input A0, A1, A2, A3, - input D, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE -); - parameter [15:0] INIT = 16'h0000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - wire [3:0] a = {A3, A2, A1, A0}; - reg [15:0] mem = INIT; - assign O = mem[a]; - wire clk = WCLK ^ IS_WCLK_INVERTED; - always @(posedge clk) if (WE) mem[a] <= D; -endmodule - -module RAM16X1S_1 ( - output O, - input A0, A1, A2, A3, - input D, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE -); - parameter [15:0] INIT = 16'h0000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - wire [3:0] a = {A3, A2, A1, A0}; - reg [15:0] mem = INIT; - assign O = mem[a]; - wire clk = WCLK ^ IS_WCLK_INVERTED; - always @(negedge clk) if (WE) mem[a] <= D; -endmodule - -module RAM32X1S ( +(* abc9_box, lib_whitebox *) +module RAMS32X1 ( output O, input A0, A1, A2, A3, A4, input D, (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) input WCLK, input WE ); parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; wire [4:0] a = {A4, A3, A2, A1, A0}; reg [31:0] mem = INIT; assign O = mem[a]; - wire clk = WCLK ^ IS_WCLK_INVERTED; - always @(posedge clk) if (WE) mem[a] <= D; + always @(posedge WCLK) if (WE) mem[a] <= D; + specify + $setup(A0, posedge WCLK, 0); + $setup(A1, posedge WCLK, 0); + $setup(A2, posedge WCLK, 0); + $setup(A3, posedge WCLK, 0); + $setup(A4, posedge WCLK, 0); + $setup(D, posedge WCLK, 0); + $setup(WE, posedge WCLK, 0); + (A0 => O) = 63; + (A1 => O) = 63; + (A2 => O) = 63; + (A3 => O) = 63; + (A4 => O) = 63; + (posedge WCLK => (O : D)) = 813; + endspecify endmodule -module RAM32X1S_1 ( - output O, - input A0, A1, A2, A3, A4, - input D, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE -); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - wire [4:0] a = {A4, A3, A2, A1, A0}; - reg [31:0] mem = INIT; - assign O = mem[a]; - wire clk = WCLK ^ IS_WCLK_INVERTED; - always @(negedge clk) if (WE) mem[a] <= D; -endmodule - -module RAM64X1S ( - output O, - input A0, A1, A2, A3, A4, A5, - input D, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE -); - parameter [63:0] INIT = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - wire [5:0] a = {A5, A4, A3, A2, A1, A0}; - reg [63:0] mem = INIT; - assign O = mem[a]; - wire clk = WCLK ^ IS_WCLK_INVERTED; - always @(posedge clk) if (WE) mem[a] <= D; -endmodule - -module RAM64X1S_1 ( - output O, - input A0, A1, A2, A3, A4, A5, - input D, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE -); - parameter [63:0] INIT = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - wire [5:0] a = {A5, A4, A3, A2, A1, A0}; - reg [63:0] mem = INIT; - assign O = mem[a]; - wire clk = WCLK ^ IS_WCLK_INVERTED; - always @(negedge clk) if (WE) mem[a] <= D; -endmodule - -module RAM128X1S ( - output O, - input A0, A1, A2, A3, A4, A5, A6, - input D, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE -); - parameter [127:0] INIT = 128'h00000000000000000000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - wire [6:0] a = {A6, A5, A4, A3, A2, A1, A0}; - reg [127:0] mem = INIT; - assign O = mem[a]; - wire clk = WCLK ^ IS_WCLK_INVERTED; - always @(posedge clk) if (WE) mem[a] <= D; -endmodule - -module RAM128X1S_1 ( - output O, - input A0, A1, A2, A3, A4, A5, A6, - input D, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE -); - parameter [127:0] INIT = 128'h00000000000000000000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - wire [6:0] a = {A6, A5, A4, A3, A2, A1, A0}; - reg [127:0] mem = INIT; - assign O = mem[a]; - wire clk = WCLK ^ IS_WCLK_INVERTED; - always @(negedge clk) if (WE) mem[a] <= D; -endmodule - -module RAM256X1S ( - output O, - input [7:0] A, - input D, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE -); - parameter [255:0] INIT = 256'h0; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - reg [255:0] mem = INIT; - assign O = mem[A]; - wire clk = WCLK ^ IS_WCLK_INVERTED; - always @(posedge clk) if (WE) mem[A] <= D; -endmodule - -module RAM512X1S ( - output O, - input [8:0] A, - input D, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE -); - parameter [511:0] INIT = 512'h0; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - reg [511:0] mem = INIT; - assign O = mem[A]; - wire clk = WCLK ^ IS_WCLK_INVERTED; - always @(posedge clk) if (WE) mem[A] <= D; -endmodule - -// Single port, wide. - -module RAM16X2S ( - output O0, O1, - input A0, A1, A2, A3, - input D0, D1, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE -); - parameter [15:0] INIT_00 = 16'h0000; - parameter [15:0] INIT_01 = 16'h0000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - wire [3:0] a = {A3, A2, A1, A0}; - wire clk = WCLK ^ IS_WCLK_INVERTED; - reg [15:0] mem0 = INIT_00; - reg [15:0] mem1 = INIT_01; - assign O0 = mem0[a]; - assign O1 = mem1[a]; - always @(posedge clk) - if (WE) begin - mem0[a] <= D0; - mem1[a] <= D1; - end -endmodule - -module RAM32X2S ( - output O0, O1, - input A0, A1, A2, A3, A4, - input D0, D1, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE -); - parameter [31:0] INIT_00 = 32'h00000000; - parameter [31:0] INIT_01 = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - wire [4:0] a = {A4, A3, A2, A1, A0}; - wire clk = WCLK ^ IS_WCLK_INVERTED; - reg [31:0] mem0 = INIT_00; - reg [31:0] mem1 = INIT_01; - assign O0 = mem0[a]; - assign O1 = mem1[a]; - always @(posedge clk) - if (WE) begin - mem0[a] <= D0; - mem1[a] <= D1; - end -endmodule - -module RAM64X2S ( - output O0, O1, - input A0, A1, A2, A3, A4, A5, - input D0, D1, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE -); - parameter [63:0] INIT_00 = 64'h0000000000000000; - parameter [63:0] INIT_01 = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - wire [5:0] a = {A5, A3, A2, A1, A0}; - wire clk = WCLK ^ IS_WCLK_INVERTED; - reg [63:0] mem0 = INIT_00; - reg [63:0] mem1 = INIT_01; - assign O0 = mem0[a]; - assign O1 = mem1[a]; - always @(posedge clk) - if (WE) begin - mem0[a] <= D0; - mem1[a] <= D1; - end -endmodule - -module RAM16X4S ( - output O0, O1, O2, O3, - input A0, A1, A2, A3, - input D0, D1, D2, D3, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE -); - parameter [15:0] INIT_00 = 16'h0000; - parameter [15:0] INIT_01 = 16'h0000; - parameter [15:0] INIT_02 = 16'h0000; - parameter [15:0] INIT_03 = 16'h0000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - wire [3:0] a = {A3, A2, A1, A0}; - wire clk = WCLK ^ IS_WCLK_INVERTED; - reg [15:0] mem0 = INIT_00; - reg [15:0] mem1 = INIT_01; - reg [15:0] mem2 = INIT_02; - reg [15:0] mem3 = INIT_03; - assign O0 = mem0[a]; - assign O1 = mem1[a]; - assign O2 = mem2[a]; - assign O3 = mem3[a]; - always @(posedge clk) - if (WE) begin - mem0[a] <= D0; - mem1[a] <= D1; - mem2[a] <= D2; - mem3[a] <= D3; - end -endmodule - -module RAM32X4S ( - output O0, O1, O2, O3, - input A0, A1, A2, A3, A4, - input D0, D1, D2, D3, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE -); - parameter [31:0] INIT_00 = 32'h00000000; - parameter [31:0] INIT_01 = 32'h00000000; - parameter [31:0] INIT_02 = 32'h00000000; - parameter [31:0] INIT_03 = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - wire [4:0] a = {A4, A3, A2, A1, A0}; - wire clk = WCLK ^ IS_WCLK_INVERTED; - reg [31:0] mem0 = INIT_00; - reg [31:0] mem1 = INIT_01; - reg [31:0] mem2 = INIT_02; - reg [31:0] mem3 = INIT_03; - assign O0 = mem0[a]; - assign O1 = mem1[a]; - assign O2 = mem2[a]; - assign O3 = mem3[a]; - always @(posedge clk) - if (WE) begin - mem0[a] <= D0; - mem1[a] <= D1; - mem2[a] <= D2; - mem3[a] <= D3; - end -endmodule - -module RAM16X8S ( - output [7:0] O, - input A0, A1, A2, A3, - input [7:0] D, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE -); - parameter [15:0] INIT_00 = 16'h0000; - parameter [15:0] INIT_01 = 16'h0000; - parameter [15:0] INIT_02 = 16'h0000; - parameter [15:0] INIT_03 = 16'h0000; - parameter [15:0] INIT_04 = 16'h0000; - parameter [15:0] INIT_05 = 16'h0000; - parameter [15:0] INIT_06 = 16'h0000; - parameter [15:0] INIT_07 = 16'h0000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - wire [3:0] a = {A3, A2, A1, A0}; - wire clk = WCLK ^ IS_WCLK_INVERTED; - reg [15:0] mem0 = INIT_00; - reg [15:0] mem1 = INIT_01; - reg [15:0] mem2 = INIT_02; - reg [15:0] mem3 = INIT_03; - reg [15:0] mem4 = INIT_04; - reg [15:0] mem5 = INIT_05; - reg [15:0] mem6 = INIT_06; - reg [15:0] mem7 = INIT_07; - assign O[0] = mem0[a]; - assign O[1] = mem1[a]; - assign O[2] = mem2[a]; - assign O[3] = mem3[a]; - assign O[4] = mem4[a]; - assign O[5] = mem5[a]; - assign O[6] = mem6[a]; - assign O[7] = mem7[a]; - always @(posedge clk) - if (WE) begin - mem0[a] <= D[0]; - mem1[a] <= D[1]; - mem2[a] <= D[2]; - mem3[a] <= D[3]; - mem4[a] <= D[4]; - mem5[a] <= D[5]; - mem6[a] <= D[6]; - mem7[a] <= D[7]; - end -endmodule - -module RAM32X8S ( - output [7:0] O, - input A0, A1, A2, A3, A4, - input [7:0] D, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE -); - parameter [31:0] INIT_00 = 32'h00000000; - parameter [31:0] INIT_01 = 32'h00000000; - parameter [31:0] INIT_02 = 32'h00000000; - parameter [31:0] INIT_03 = 32'h00000000; - parameter [31:0] INIT_04 = 32'h00000000; - parameter [31:0] INIT_05 = 32'h00000000; - parameter [31:0] INIT_06 = 32'h00000000; - parameter [31:0] INIT_07 = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - wire [4:0] a = {A4, A3, A2, A1, A0}; - wire clk = WCLK ^ IS_WCLK_INVERTED; - reg [31:0] mem0 = INIT_00; - reg [31:0] mem1 = INIT_01; - reg [31:0] mem2 = INIT_02; - reg [31:0] mem3 = INIT_03; - reg [31:0] mem4 = INIT_04; - reg [31:0] mem5 = INIT_05; - reg [31:0] mem6 = INIT_06; - reg [31:0] mem7 = INIT_07; - assign O[0] = mem0[a]; - assign O[1] = mem1[a]; - assign O[2] = mem2[a]; - assign O[3] = mem3[a]; - assign O[4] = mem4[a]; - assign O[5] = mem5[a]; - assign O[6] = mem6[a]; - assign O[7] = mem7[a]; - always @(posedge clk) - if (WE) begin - mem0[a] <= D[0]; - mem1[a] <= D[1]; - mem2[a] <= D[2]; - mem3[a] <= D[3]; - mem4[a] <= D[4]; - mem5[a] <= D[5]; - mem6[a] <= D[6]; - mem7[a] <= D[7]; - end -endmodule - -// Dual port. - (* abc9_box, lib_whitebox *) -module RAM32X1D ( +module RAMS64X1 ( + output O, + input A0, A1, A2, A3, A4, A5, + input D, + (* clkbuf_sink *) + input WCLK, + input WE +); + parameter [63:0] INIT = 64'h0000000000000000; + wire [5:0] a = {A5, A4, A3, A2, A1, A0}; + reg [63:0] mem = INIT; + assign O = mem[a]; + always @(posedge WCLK) if (WE) mem[a] <= D; + specify + $setup(A0, posedge WCLK, 0); + $setup(A1, posedge WCLK, 0); + $setup(A2, posedge WCLK, 0); + $setup(A3, posedge WCLK, 0); + $setup(A4, posedge WCLK, 0); + $setup(A5, posedge WCLK, 0); + $setup(D, posedge WCLK, 0); + $setup(WE, posedge WCLK, 0); + (A0 => O) = 161; + (A1 => O) = 161; + (A2 => O) = 161; + (A3 => O) = 161; + (A4 => O) = 161; + (A5 => O) = 64; + (posedge WCLK => (O : D)) = 762; + endspecify +endmodule + +(* abc9_box, lib_whitebox *) +module RAMD32X1 ( output DPO, SPO, input D, (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) input WCLK, input WE, input A0, A1, A2, A3, A4, input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4 ); parameter INIT = 32'h0; - parameter IS_WCLK_INVERTED = 1'b0; wire [4:0] a = {A4, A3, A2, A1, A0}; - wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}; + wire [4:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}; reg [31:0] mem = INIT; assign SPO = mem[a]; assign DPO = mem[dpra]; - wire clk = WCLK ^ IS_WCLK_INVERTED; - always @(posedge clk) if (WE) mem[a] <= D; + always @(posedge WCLK) if (WE) mem[a] <= D; specify - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986 - $setup(D , posedge WCLK &&& !IS_WCLK_INVERTED && WE, 453); - $setup(D , negedge WCLK &&& IS_WCLK_INVERTED && WE, 453); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834 - $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED, 654); - $setup(WE, negedge WCLK &&& IS_WCLK_INVERTED, 654); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800 - $setup(A0, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245); - $setup(A0, negedge WCLK &&& IS_WCLK_INVERTED && WE, 245); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798 - $setup(A1, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208); - $setup(A1, negedge WCLK &&& IS_WCLK_INVERTED && WE, 208); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796 - $setup(A2, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147); - $setup(A2, negedge WCLK &&& IS_WCLK_INVERTED && WE, 147); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794 - $setup(A3, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68); - $setup(A3, negedge WCLK &&& IS_WCLK_INVERTED && WE, 68); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792 - $setup(A4, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66); - $setup(A4, posedge WCLK &&& IS_WCLK_INVERTED && WE, 66); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981 - if (!IS_WCLK_INVERTED) (posedge WCLK => (SPO : D)) = 1153; - if (!IS_WCLK_INVERTED) (posedge WCLK => (DPO : 1'bx)) = 1153; - if ( IS_WCLK_INVERTED) (posedge WCLK => (SPO : D)) = 1153; - if ( IS_WCLK_INVERTED) (negedge WCLK => (DPO : 1'bx)) = 1153; - (A0 => SPO) = 642; (DPRA0 => DPO) = 642; - (A1 => SPO) = 632; (DPRA1 => DPO) = 631; - (A2 => SPO) = 472; (DPRA2 => DPO) = 472; - (A3 => SPO) = 407; (DPRA3 => DPO) = 407; - (A4 => SPO) = 238; (DPRA4 => DPO) = 238; + $setup(A0, posedge WCLK, 0); + $setup(A1, posedge WCLK, 0); + $setup(A2, posedge WCLK, 0); + $setup(A3, posedge WCLK, 0); + $setup(A4, posedge WCLK, 0); + // HACK: No timing arcs for DPRAn; using ones for An + $setup(DPRA0, posedge WCLK, 0); + $setup(DPRA1, posedge WCLK, 0); + $setup(DPRA2, posedge WCLK, 0); + $setup(DPRA3, posedge WCLK, 0); + $setup(DPRA4, posedge WCLK, 0); + $setup(D, posedge WCLK, 0); + $setup(WE, posedge WCLK, 0); + // HACK: No timing arcs for SPO; using ones for DPO + (A0 => SPO) = 66; + (A1 => SPO) = 66; + (A2 => SPO) = 66; + (A3 => SPO) = 66; + (A4 => SPO) = 66; + (DPRA0 => DPO) = 66; + (DPRA1 => DPO) = 66; + (DPRA2 => DPO) = 66; + (DPRA3 => DPO) = 66; + (DPRA4 => DPO) = 66; + (posedge WCLK => (SPO : D)) = 813; + (posedge WCLK => (DPO : D)) = 813; endspecify endmodule (* abc9_box, lib_whitebox *) -module RAM32X1D_1 ( +module RAMD64X1 ( output DPO, SPO, input D, (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE, - input A0, - input A1, - input A2, - input A3, - input A4, - input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4 -); - parameter INIT = 32'h0; - parameter IS_WCLK_INVERTED = 1'b0; - wire [4:0] a = {A4, A3, A2, A1, A0}; - wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}; - reg [31:0] mem = INIT; - assign SPO = mem[a]; - assign DPO = mem[dpra]; - wire clk = WCLK ^ IS_WCLK_INVERTED; - always @(negedge clk) if (WE) mem[a] <= D; - specify - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986 - $setup(D , negedge WCLK &&& WE, 453); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834 - $setup(WE, negedge WCLK, 654); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800 - $setup(A0, negedge WCLK &&& WE, 245); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798 - $setup(A1, negedge WCLK &&& WE, 208); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796 - $setup(A2, negedge WCLK &&& WE, 147); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794 - $setup(A3, negedge WCLK &&& WE, 68); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792 - $setup(A4, negedge WCLK &&& WE, 66); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981 - if (WE) (negedge WCLK => (SPO : D)) = 1153; - if (WE) (negedge WCLK => (DPO : 1'bx)) = 1153; - (A0 => SPO) = 642; (DPRA0 => DPO) = 642; - (A1 => SPO) = 632; (DPRA1 => DPO) = 631; - (A2 => SPO) = 472; (DPRA2 => DPO) = 472; - (A3 => SPO) = 407; (DPRA3 => DPO) = 407; - (A4 => SPO) = 238; (DPRA4 => DPO) = 238; - endspecify -endmodule - -(* abc9_box, lib_whitebox *) -module RAM64X1D ( - output DPO, SPO, - input D, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) input WCLK, input WE, input A0, A1, A2, A3, A4, A5, input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 ); parameter INIT = 64'h0; - parameter IS_WCLK_INVERTED = 1'b0; wire [5:0] a = {A5, A4, A3, A2, A1, A0}; wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}; reg [63:0] mem = INIT; assign SPO = mem[a]; assign DPO = mem[dpra]; - wire clk = WCLK ^ IS_WCLK_INVERTED; - always @(posedge clk) if (WE) mem[a] <= D; + always @(posedge WCLK) if (WE) mem[a] <= D; specify - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986 - $setup(D , posedge WCLK &&& !IS_WCLK_INVERTED && WE, 453); - $setup(D , negedge WCLK &&& IS_WCLK_INVERTED && WE, 453); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834 - $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED, 654); - $setup(WE, negedge WCLK &&& IS_WCLK_INVERTED, 654); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828 - $setup(A0, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 362); - $setup(A0, negedge WCLK &&& IS_WCLK_INVERTED && WE, 362); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826 - $setup(A1, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245); - $setup(A1, negedge WCLK &&& IS_WCLK_INVERTED && WE, 245); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824 - $setup(A2, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208); - $setup(A2, negedge WCLK &&& IS_WCLK_INVERTED && WE, 208); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822 - $setup(A3, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147); - $setup(A3, negedge WCLK &&& IS_WCLK_INVERTED && WE, 147); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820 - $setup(A4, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68); - $setup(A4, negedge WCLK &&& IS_WCLK_INVERTED && WE, 68); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818 - $setup(A5, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66); - $setup(A5, negedge WCLK &&& IS_WCLK_INVERTED && WE, 66); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981 - if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (SPO : D)) = 1153; - if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DPO : 1'bx)) = 1153; - if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (SPO : D)) = 1153; - if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DPO : 1'bx)) = 1153; - (A0 => SPO) = 642; (DPRA0 => DPO) = 642; - (A1 => SPO) = 632; (DPRA1 => DPO) = 631; - (A2 => SPO) = 472; (DPRA2 => DPO) = 472; - (A3 => SPO) = 407; (DPRA3 => DPO) = 407; - (A4 => SPO) = 238; (DPRA4 => DPO) = 238; - (A5 => SPO) = 127; (DPRA5 => DPO) = 127; + $setup(A0, posedge WCLK, 0); + $setup(A1, posedge WCLK, 0); + $setup(A2, posedge WCLK, 0); + $setup(A3, posedge WCLK, 0); + $setup(A4, posedge WCLK, 0); + $setup(A5, posedge WCLK, 0); + // HACK: No timing arcs for DPRAn; using ones for An + $setup(DPRA0, posedge WCLK, 0); + $setup(DPRA1, posedge WCLK, 0); + $setup(DPRA2, posedge WCLK, 0); + $setup(DPRA3, posedge WCLK, 0); + $setup(DPRA4, posedge WCLK, 0); + $setup(DPRA5, posedge WCLK, 0); + $setup(D, posedge WCLK, 0); + $setup(WE, posedge WCLK, 0); + (A0 => SPO) = 161; + (A1 => SPO) = 161; + (A2 => SPO) = 161; + (A3 => SPO) = 161; + (A4 => SPO) = 161; + (A5 => SPO) = 64; + (DPRA0 => DPO) = 118; + (DPRA1 => DPO) = 118; + (DPRA2 => DPO) = 118; + (DPRA3 => DPO) = 118; + (DPRA4 => DPO) = 118; + (DPRA5 => DPO) = 63; + (posedge WCLK => (SPO : D)) = 762; + (posedge WCLK => (DPO : D)) = 737; endspecify endmodule -module RAM64X1D_1 ( - output DPO, SPO, - input D, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE, - input A0, A1, A2, A3, A4, A5, - input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 -); - parameter INIT = 64'h0; - parameter IS_WCLK_INVERTED = 1'b0; - wire [5:0] a = {A5, A4, A3, A2, A1, A0}; - wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}; - reg [63:0] mem = INIT; - assign SPO = mem[a]; - assign DPO = mem[dpra]; - wire clk = WCLK ^ IS_WCLK_INVERTED; - always @(negedge clk) if (WE) mem[a] <= D; - specify - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986 - $setup(D , negedge WCLK &&& WE, 453); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834 - $setup(WE, negedge WCLK, 654); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828 - $setup(A0, negedge WCLK &&& WE, 362); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826 - $setup(A1, negedge WCLK &&& WE, 245); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824 - $setup(A2, negedge WCLK &&& WE, 208); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822 - $setup(A3, negedge WCLK &&& WE, 147); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820 - $setup(A4, negedge WCLK &&& WE, 68); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818 - $setup(A5, negedge WCLK &&& WE, 66); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981 - if (WE) (negedge WCLK => (SPO : D)) = 1153; - if (WE) (negedge WCLK => (DPO : 1'bx)) = 1153; - (A0 => SPO) = 642; (DPRA0 => DPO) = 642; - (A1 => SPO) = 632; (DPRA1 => DPO) = 631; - (A2 => SPO) = 472; (DPRA2 => DPO) = 472; - (A3 => SPO) = 407; (DPRA3 => DPO) = 407; - (A4 => SPO) = 238; (DPRA4 => DPO) = 238; - (A5 => SPO) = 127; (DPRA5 => DPO) = 127; - endspecify -endmodule - -(* abc9_box, lib_whitebox *) -module RAM128X1D ( - output DPO, SPO, - input D, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE, - input [6:0] A, - input [6:0] DPRA -); - parameter INIT = 128'h0; - parameter IS_WCLK_INVERTED = 1'b0; - reg [127:0] mem = INIT; - assign SPO = mem[A]; - assign DPO = mem[DPRA]; - wire clk = WCLK ^ IS_WCLK_INVERTED; - always @(posedge clk) if (WE) mem[A] <= D; - specify - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986 - $setup(D , posedge WCLK &&& !IS_WCLK_INVERTED && WE, 453); - $setup(D , negedge WCLK &&& IS_WCLK_INVERTED && WE, 453); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834 - $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED, 654); - $setup(WE, negedge WCLK &&& IS_WCLK_INVERTED, 654); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-830 - $setup(A[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 616); - $setup(A[0], negedge WCLK &&& IS_WCLK_INVERTED && WE, 616); - $setup(A[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 362); - $setup(A[1], negedge WCLK &&& IS_WCLK_INVERTED && WE, 362); - $setup(A[2], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245); - $setup(A[2], negedge WCLK &&& IS_WCLK_INVERTED && WE, 245); - $setup(A[3], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208); - $setup(A[3], negedge WCLK &&& IS_WCLK_INVERTED && WE, 208); - $setup(A[4], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147); - $setup(A[4], negedge WCLK &&& IS_WCLK_INVERTED && WE, 147); - $setup(A[5], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68); - $setup(A[5], negedge WCLK &&& IS_WCLK_INVERTED && WE, 68); - $setup(A[6], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66); - $setup(A[6], negedge WCLK &&& IS_WCLK_INVERTED && WE, 66); -`ifndef __ICARUS__ - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981 - if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (SPO : D)) = 1153 + 217 /* to cross F7AMUX */ + 175 /* AMUX */; - if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DPO : 1'bx)) = 1153 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; - (A[0] => SPO) = 642 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; - (A[1] => SPO) = 631 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; - (A[2] => SPO) = 472 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; - (A[3] => SPO) = 407 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; - (A[4] => SPO) = 238 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; - (A[5] => SPO) = 127 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; - (A[6] => SPO) = 0 + 276 /* to select F7AMUX */ + 175 /* AMUX */; - (DPRA[0] => DPO) = 642 + 223 /* to cross LUTMUX7 */ + 174 /* CMUX */; - (DPRA[1] => DPO) = 631 + 223 /* to cross LUTMUX7 */ + 174 /* CMUX */; - (DPRA[2] => DPO) = 472 + 223 /* to cross LUTMUX7 */ + 174 /* CMUX */; - (DPRA[3] => DPO) = 407 + 223 /* to cross LUTMUX7 */ + 174 /* CMUX */; - (DPRA[4] => DPO) = 238 + 223 /* to cross LUTMUX7 */ + 174 /* CMUX */; - (DPRA[5] => DPO) = 127 + 223 /* to cross LUTMUX7 */ + 174 /* CMUX */; - (DPRA[6] => DPO) = 0 + 296 /* to select LUTMUX7 */ + 174 /* CMUX */; -`endif - endspecify -endmodule - -module RAM256X1D ( - output DPO, SPO, - input D, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE, - input [7:0] A, DPRA -); - parameter INIT = 256'h0; - parameter IS_WCLK_INVERTED = 1'b0; - reg [255:0] mem = INIT; - assign SPO = mem[A]; - assign DPO = mem[DPRA]; - wire clk = WCLK ^ IS_WCLK_INVERTED; - always @(posedge clk) if (WE) mem[A] <= D; -endmodule - -// Multi port. - -(* abc9_box, lib_whitebox *) -module RAM32M ( - output [1:0] DOA, - output [1:0] DOB, - output [1:0] DOC, - output [1:0] DOD, - input [4:0] ADDRA, ADDRB, ADDRC, - input [4:0] ADDRD, - input [1:0] DIA, - input [1:0] DIB, - input [1:0] DIC, - input [1:0] DID, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE -); - parameter [63:0] INIT_A = 64'h0000000000000000; - parameter [63:0] INIT_B = 64'h0000000000000000; - parameter [63:0] INIT_C = 64'h0000000000000000; - parameter [63:0] INIT_D = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - reg [63:0] mem_a = INIT_A; - reg [63:0] mem_b = INIT_B; - reg [63:0] mem_c = INIT_C; - reg [63:0] mem_d = INIT_D; - assign DOA = mem_a[2*ADDRA+:2]; - assign DOB = mem_b[2*ADDRB+:2]; - assign DOC = mem_c[2*ADDRC+:2]; - assign DOD = mem_d[2*ADDRD+:2]; - wire clk = WCLK ^ IS_WCLK_INVERTED; - always @(posedge clk) - if (WE) begin - mem_a[2*ADDRD+:2] <= DIA; - mem_b[2*ADDRD+:2] <= DIB; - mem_c[2*ADDRD+:2] <= DIC; - mem_d[2*ADDRD+:2] <= DID; - end - specify - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986 - $setup(ADDRD[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245); - $setup(ADDRD[0], negedge WCLK &&& IS_WCLK_INVERTED && WE, 245); - $setup(ADDRD[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208); - $setup(ADDRD[1], negedge WCLK &&& IS_WCLK_INVERTED && WE, 208); - $setup(ADDRD[2], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147); - $setup(ADDRD[2], negedge WCLK &&& IS_WCLK_INVERTED && WE, 147); - $setup(ADDRD[3], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68); - $setup(ADDRD[3], negedge WCLK &&& IS_WCLK_INVERTED && WE, 68); - $setup(ADDRD[4], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66); - $setup(ADDRD[4], negedge WCLK &&& IS_WCLK_INVERTED && WE, 66); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988 - $setup(DIA[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 453); - $setup(DIA[0], negedge WCLK &&& IS_WCLK_INVERTED && WE, 453); - $setup(DIA[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 384); - $setup(DIA[1], negedge WCLK &&& IS_WCLK_INVERTED && WE, 384); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056 - $setup(DIB[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 461); - $setup(DIB[0], negedge WCLK &&& IS_WCLK_INVERTED && WE, 461); - $setup(DIB[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 354); - $setup(DIB[1], negedge WCLK &&& IS_WCLK_INVERTED && WE, 354); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124 - $setup(DIC[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 457); - $setup(DIC[0], negedge WCLK &&& IS_WCLK_INVERTED && WE, 457); - $setup(DIC[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 375); - $setup(DIC[1], negedge WCLK &&& IS_WCLK_INVERTED && WE, 375); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192 - $setup(DID[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 310); - $setup(DID[0], negedge WCLK &&& IS_WCLK_INVERTED && WE, 310); - $setup(DID[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 334); - $setup(DID[1], negedge WCLK &&& IS_WCLK_INVERTED && WE, 334); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834 - $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED, 654); - $setup(WE, negedge WCLK &&& IS_WCLK_INVERTED, 654); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889 - if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOA[0] : DIA[0])) = 1153; - if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOA[0] : DIA[0])) = 1153; - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857 - if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOA[1] : DIA[1])) = 1188; - if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOA[1] : DIA[1])) = 1188; - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 - if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOB[0] : DIB[0])) = 1161; - if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOB[0] : DIB[0])) = 1161; - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L925 - if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOB[1] : DIB[1])) = 1187; - if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOB[1] : DIB[1])) = 1187; - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L993 - if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOC[0] : DIC[0])) = 1158; - if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOC[0] : DIC[0])) = 1158; - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025 - if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOC[1] : DIC[1])) = 1180; - if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOC[1] : DIC[1])) = 1180; - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093 - if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD[0] : DID[0])) = 1163; - if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD[0] : DID[0])) = 1163; - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061 - if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD[1] : DID[1])) = 1190; - if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD[1] : DID[1])) = 1190; - (ADDRA[0] *> DOA) = 642; (ADDRB[0] *> DOB) = 642; (ADDRC[0] *> DOC) = 642; (ADDRD[0] *> DOD) = 642; - (ADDRA[1] *> DOA) = 631; (ADDRB[1] *> DOB) = 631; (ADDRC[1] *> DOC) = 631; (ADDRD[1] *> DOD) = 631; - (ADDRA[2] *> DOA) = 472; (ADDRB[2] *> DOB) = 472; (ADDRC[2] *> DOC) = 472; (ADDRD[2] *> DOD) = 472; - (ADDRA[3] *> DOA) = 407; (ADDRB[3] *> DOB) = 407; (ADDRC[3] *> DOC) = 407; (ADDRD[3] *> DOD) = 407; - (ADDRA[4] *> DOA) = 238; (ADDRB[4] *> DOB) = 238; (ADDRC[4] *> DOC) = 238; (ADDRD[4] *> DOD) = 238; - endspecify -endmodule - -module RAM32M16 ( - output [1:0] DOA, - output [1:0] DOB, - output [1:0] DOC, - output [1:0] DOD, - output [1:0] DOE, - output [1:0] DOF, - output [1:0] DOG, - output [1:0] DOH, - input [4:0] ADDRA, - input [4:0] ADDRB, - input [4:0] ADDRC, - input [4:0] ADDRD, - input [4:0] ADDRE, - input [4:0] ADDRF, - input [4:0] ADDRG, - input [4:0] ADDRH, - input [1:0] DIA, - input [1:0] DIB, - input [1:0] DIC, - input [1:0] DID, - input [1:0] DIE, - input [1:0] DIF, - input [1:0] DIG, - input [1:0] DIH, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE -); - parameter [63:0] INIT_A = 64'h0000000000000000; - parameter [63:0] INIT_B = 64'h0000000000000000; - parameter [63:0] INIT_C = 64'h0000000000000000; - parameter [63:0] INIT_D = 64'h0000000000000000; - parameter [63:0] INIT_E = 64'h0000000000000000; - parameter [63:0] INIT_F = 64'h0000000000000000; - parameter [63:0] INIT_G = 64'h0000000000000000; - parameter [63:0] INIT_H = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - reg [63:0] mem_a = INIT_A; - reg [63:0] mem_b = INIT_B; - reg [63:0] mem_c = INIT_C; - reg [63:0] mem_d = INIT_D; - reg [63:0] mem_e = INIT_E; - reg [63:0] mem_f = INIT_F; - reg [63:0] mem_g = INIT_G; - reg [63:0] mem_h = INIT_H; - assign DOA = mem_a[2*ADDRA+:2]; - assign DOB = mem_b[2*ADDRB+:2]; - assign DOC = mem_c[2*ADDRC+:2]; - assign DOD = mem_d[2*ADDRD+:2]; - assign DOE = mem_e[2*ADDRE+:2]; - assign DOF = mem_f[2*ADDRF+:2]; - assign DOG = mem_g[2*ADDRG+:2]; - assign DOH = mem_h[2*ADDRH+:2]; - wire clk = WCLK ^ IS_WCLK_INVERTED; - always @(posedge clk) - if (WE) begin - mem_a[2*ADDRH+:2] <= DIA; - mem_b[2*ADDRH+:2] <= DIB; - mem_c[2*ADDRH+:2] <= DIC; - mem_d[2*ADDRH+:2] <= DID; - mem_e[2*ADDRH+:2] <= DIE; - mem_f[2*ADDRH+:2] <= DIF; - mem_g[2*ADDRH+:2] <= DIG; - mem_h[2*ADDRH+:2] <= DIH; - end -endmodule - -(* abc9_box, lib_whitebox *) -module RAM64M ( - output DOA, - output DOB, - output DOC, - output DOD, - input [5:0] ADDRA, ADDRB, ADDRC, - input [5:0] ADDRD, - input DIA, - input DIB, - input DIC, - input DID, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE -); - parameter [63:0] INIT_A = 64'h0000000000000000; - parameter [63:0] INIT_B = 64'h0000000000000000; - parameter [63:0] INIT_C = 64'h0000000000000000; - parameter [63:0] INIT_D = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - reg [63:0] mem_a = INIT_A; - reg [63:0] mem_b = INIT_B; - reg [63:0] mem_c = INIT_C; - reg [63:0] mem_d = INIT_D; - assign DOA = mem_a[ADDRA]; - assign DOB = mem_b[ADDRB]; - assign DOC = mem_c[ADDRC]; - assign DOD = mem_d[ADDRD]; - wire clk = WCLK ^ IS_WCLK_INVERTED; - always @(posedge clk) - if (WE) begin - mem_a[ADDRD] <= DIA; - mem_b[ADDRD] <= DIB; - mem_c[ADDRD] <= DIC; - mem_d[ADDRD] <= DID; - end - specify - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-L830 - $setup(ADDRD[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 362); - $setup(ADDRD[0], negedge WCLK &&& IS_WCLK_INVERTED && WE, 362); - $setup(ADDRD[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245); - $setup(ADDRD[1], negedge WCLK &&& IS_WCLK_INVERTED && WE, 245); - $setup(ADDRD[2], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208); - $setup(ADDRD[2], negedge WCLK &&& IS_WCLK_INVERTED && WE, 208); - $setup(ADDRD[3], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147); - $setup(ADDRD[3], negedge WCLK &&& IS_WCLK_INVERTED && WE, 147); - $setup(ADDRD[4], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68); - $setup(ADDRD[4], negedge WCLK &&& IS_WCLK_INVERTED && WE, 68); - $setup(ADDRD[5], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66); - $setup(ADDRD[5], negedge WCLK &&& IS_WCLK_INVERTED && WE, 66); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988 - $setup(DIA, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 384); - $setup(DIA, negedge WCLK &&& IS_WCLK_INVERTED && WE, 384); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056 - $setup(DIB, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 354); - $setup(DIB, negedge WCLK &&& IS_WCLK_INVERTED && WE, 354); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124 - $setup(DIC, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 375); - $setup(DIC, negedge WCLK &&& IS_WCLK_INVERTED && WE, 375); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192 - $setup(DID, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 310); - $setup(DID, negedge WCLK &&& IS_WCLK_INVERTED && WE, 310); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834 - $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 654); - $setup(WE, negedge WCLK &&& IS_WCLK_INVERTED && WE, 654); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889 - if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOA : DIA)) = 1153; - if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOA : DIA)) = 1153; - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 - if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOB : DIB)) = 1161; - if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOB : DIB)) = 1161; - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025 - if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOC : DIC)) = 1158; - if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOC : DIC)) = 1158; - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093 - if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD : DID)) = 1163; - if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD : DID)) = 1163; - (ADDRA[0] => DOA) = 642; (ADDRB[0] => DOB) = 642; (ADDRC[0] => DOC) = 642; (ADDRD[0] => DOD) = 642; - (ADDRA[1] => DOA) = 631; (ADDRB[1] => DOB) = 631; (ADDRC[1] => DOC) = 631; (ADDRD[1] => DOD) = 631; - (ADDRA[2] => DOA) = 472; (ADDRB[2] => DOB) = 472; (ADDRC[2] => DOC) = 472; (ADDRD[2] => DOD) = 472; - (ADDRA[3] => DOA) = 407; (ADDRB[3] => DOB) = 407; (ADDRC[3] => DOC) = 407; (ADDRD[3] => DOD) = 407; - (ADDRA[4] => DOA) = 238; (ADDRB[4] => DOB) = 238; (ADDRC[4] => DOC) = 238; (ADDRD[4] => DOD) = 238; - endspecify -endmodule - -module RAM64M8 ( - output DOA, - output DOB, - output DOC, - output DOD, - output DOE, - output DOF, - output DOG, - output DOH, - input [5:0] ADDRA, - input [5:0] ADDRB, - input [5:0] ADDRC, - input [5:0] ADDRD, - input [5:0] ADDRE, - input [5:0] ADDRF, - input [5:0] ADDRG, - input [5:0] ADDRH, - input DIA, - input DIB, - input DIC, - input DID, - input DIE, - input DIF, - input DIG, - input DIH, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE -); - parameter [63:0] INIT_A = 64'h0000000000000000; - parameter [63:0] INIT_B = 64'h0000000000000000; - parameter [63:0] INIT_C = 64'h0000000000000000; - parameter [63:0] INIT_D = 64'h0000000000000000; - parameter [63:0] INIT_E = 64'h0000000000000000; - parameter [63:0] INIT_F = 64'h0000000000000000; - parameter [63:0] INIT_G = 64'h0000000000000000; - parameter [63:0] INIT_H = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - reg [63:0] mem_a = INIT_A; - reg [63:0] mem_b = INIT_B; - reg [63:0] mem_c = INIT_C; - reg [63:0] mem_d = INIT_D; - reg [63:0] mem_e = INIT_E; - reg [63:0] mem_f = INIT_F; - reg [63:0] mem_g = INIT_G; - reg [63:0] mem_h = INIT_H; - assign DOA = mem_a[ADDRA]; - assign DOB = mem_b[ADDRB]; - assign DOC = mem_c[ADDRC]; - assign DOD = mem_d[ADDRD]; - assign DOE = mem_e[ADDRE]; - assign DOF = mem_f[ADDRF]; - assign DOG = mem_g[ADDRG]; - assign DOH = mem_h[ADDRH]; - wire clk = WCLK ^ IS_WCLK_INVERTED; - always @(posedge clk) - if (WE) begin - mem_a[ADDRH] <= DIA; - mem_b[ADDRH] <= DIB; - mem_c[ADDRH] <= DIC; - mem_d[ADDRH] <= DID; - mem_e[ADDRH] <= DIE; - mem_f[ADDRH] <= DIF; - mem_g[ADDRH] <= DIG; - mem_h[ADDRH] <= DIH; - end -endmodule - -module RAM32X16DR8 ( - output DOA, - output DOB, - output DOC, - output DOD, - output DOE, - output DOF, - output DOG, - output [1:0] DOH, - input [5:0] ADDRA, ADDRB, ADDRC, ADDRD, ADDRE, ADDRF, ADDRG, - input [4:0] ADDRH, - input [1:0] DIA, - input [1:0] DIB, - input [1:0] DIC, - input [1:0] DID, - input [1:0] DIE, - input [1:0] DIF, - input [1:0] DIG, - input [1:0] DIH, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE -); - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - reg [63:0] mem_a, mem_b, mem_c, mem_d, mem_e, mem_f, mem_g, mem_h; - assign DOA = mem_a[ADDRA]; - assign DOB = mem_b[ADDRB]; - assign DOC = mem_c[ADDRC]; - assign DOD = mem_d[ADDRD]; - assign DOE = mem_e[ADDRE]; - assign DOF = mem_f[ADDRF]; - assign DOG = mem_g[ADDRG]; - assign DOH = mem_h[2*ADDRH+:2]; - wire clk = WCLK ^ IS_WCLK_INVERTED; - always @(posedge clk) - if (WE) begin - mem_a[2*ADDRH+:2] <= DIA; - mem_b[2*ADDRH+:2] <= DIB; - mem_c[2*ADDRH+:2] <= DIC; - mem_d[2*ADDRH+:2] <= DID; - mem_e[2*ADDRH+:2] <= DIE; - mem_f[2*ADDRH+:2] <= DIF; - mem_g[2*ADDRH+:2] <= DIG; - mem_h[2*ADDRH+:2] <= DIH; - end -endmodule - -module RAM64X8SW ( - output [7:0] O, - input [5:0] A, - input D, - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK, - input WE, - input [2:0] WSEL -); - parameter [63:0] INIT_A = 64'h0000000000000000; - parameter [63:0] INIT_B = 64'h0000000000000000; - parameter [63:0] INIT_C = 64'h0000000000000000; - parameter [63:0] INIT_D = 64'h0000000000000000; - parameter [63:0] INIT_E = 64'h0000000000000000; - parameter [63:0] INIT_F = 64'h0000000000000000; - parameter [63:0] INIT_G = 64'h0000000000000000; - parameter [63:0] INIT_H = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - reg [63:0] mem_a = INIT_A; - reg [63:0] mem_b = INIT_B; - reg [63:0] mem_c = INIT_C; - reg [63:0] mem_d = INIT_D; - reg [63:0] mem_e = INIT_E; - reg [63:0] mem_f = INIT_F; - reg [63:0] mem_g = INIT_G; - reg [63:0] mem_h = INIT_H; - assign O[7] = mem_a[A]; - assign O[6] = mem_b[A]; - assign O[5] = mem_c[A]; - assign O[4] = mem_d[A]; - assign O[3] = mem_e[A]; - assign O[2] = mem_f[A]; - assign O[1] = mem_g[A]; - assign O[0] = mem_h[A]; - wire clk = WCLK ^ IS_WCLK_INVERTED; - always @(posedge clk) - if (WE) begin - case (WSEL) - 3'b111: mem_a[A] <= D; - 3'b110: mem_b[A] <= D; - 3'b101: mem_c[A] <= D; - 3'b100: mem_d[A] <= D; - 3'b011: mem_e[A] <= D; - 3'b010: mem_f[A] <= D; - 3'b001: mem_g[A] <= D; - 3'b000: mem_h[A] <= D; - endcase - end -endmodule - -// ROM. - -module ROM16X1 ( - output O, - input A0, A1, A2, A3 -); - parameter [15:0] INIT = 16'h0; - assign O = INIT[{A3, A2, A1, A0}]; -endmodule - -module ROM32X1 ( - output O, - input A0, A1, A2, A3, A4 -); - parameter [31:0] INIT = 32'h0; - assign O = INIT[{A4, A3, A2, A1, A0}]; -endmodule - -module ROM64X1 ( - output O, - input A0, A1, A2, A3, A4, A5 -); - parameter [63:0] INIT = 64'h0; - assign O = INIT[{A5, A4, A3, A2, A1, A0}]; -endmodule - -module ROM128X1 ( - output O, - input A0, A1, A2, A3, A4, A5, A6 -); - parameter [127:0] INIT = 128'h0; - assign O = INIT[{A6, A5, A4, A3, A2, A1, A0}]; -endmodule - -module ROM256X1 ( - output O, - input A0, A1, A2, A3, A4, A5, A6, A7 -); - parameter [255:0] INIT = 256'h0; - assign O = INIT[{A7, A6, A5, A4, A3, A2, A1, A0}]; -endmodule - // Shift registers. (* abc9_box, lib_whitebox *) -module SRL16 ( - output Q, - input A0, A1, A2, A3, - (* clkbuf_sink *) - input CLK, - input D -); - parameter [15:0] INIT = 16'h0000; - - reg [15:0] r = INIT; - assign Q = r[{A3,A2,A1,A0}]; - always @(posedge CLK) r <= { r[14:0], D }; - - specify - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905 - (posedge CLK => (Q : 1'bx)) = 1472; - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912 - $setup(D , posedge CLK, 173); - (A0 => Q) = 631; - (A1 => Q) = 472; - (A2 => Q) = 407; - (A3 => Q) = 238; - endspecify -endmodule - -(* abc9_box, lib_whitebox *) -module SRL16E ( +module SRG16E ( output Q, input A0, A1, A2, A3, CE, (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK, - input D -); - parameter [15:0] INIT = 16'h0000; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - - reg [15:0] r = INIT; - assign Q = r[{A3,A2,A1,A0}]; - generate - if (IS_CLK_INVERTED) begin - always @(negedge CLK) if (CE) r <= { r[14:0], D }; - end - else - always @(posedge CLK) if (CE) r <= { r[14:0], D }; - endgenerate - specify - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912 - $setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173); - $setup(D , negedge CLK &&& IS_CLK_INVERTED, 173); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905 - if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : D)) = 1472; - if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : D)) = 1472; - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905 - if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : 1'bx)) = 1472; - if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : 1'bx)) = 1472; - (A0 => Q) = 631; - (A1 => Q) = 472; - (A2 => Q) = 407; - (A3 => Q) = 238; - endspecify -endmodule - -(* abc9_box, lib_whitebox *) -module SRLC16 ( - output Q, - output Q15, - input A0, A1, A2, A3, - (* clkbuf_sink *) input CLK, input D ); parameter [15:0] INIT = 16'h0000; reg [15:0] r = INIT; - assign Q15 = r[15]; assign Q = r[{A3,A2,A1,A0}]; - always @(posedge CLK) r <= { r[14:0], D }; - + always @(posedge CLK) if (CE) r <= { r[14:0], D }; specify - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912 $setup(D , posedge CLK, 173); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905 - (posedge CLK => (Q : 1'bx)) = 1472; - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904 - (posedge CLK => (Q15 : 1'bx)) = 1114; + if (CE) (posedge CLK => (Q : D)) = 1472; + if (CE) (posedge CLK => (Q : 1'bx)) = 1472; (A0 => Q) = 631; (A1 => Q) = 472; (A2 => Q) = 407; @@ -1865,856 +727,8 @@ module SRLC16 ( endspecify endmodule -(* abc9_box, lib_whitebox *) -module SRLC16E ( - output Q, - output Q15, - input A0, A1, A2, A3, CE, - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK, - input D -); - parameter [15:0] INIT = 16'h0000; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - - reg [15:0] r = INIT; - assign Q15 = r[15]; - assign Q = r[{A3,A2,A1,A0}]; - generate - if (IS_CLK_INVERTED) begin - always @(negedge CLK) if (CE) r <= { r[14:0], D }; - end - else - always @(posedge CLK) if (CE) r <= { r[14:0], D }; - endgenerate - specify - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912 - $setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173); - $setup(D , negedge CLK &&& IS_CLK_INVERTED, 173); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 - $setup(CE, posedge CLK &&& !IS_CLK_INVERTED, 109); - $setup(CE, negedge CLK &&& IS_CLK_INVERTED, 109); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905 - if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : D)) = 1472; - if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : D)) = 1472; - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904 - if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q15 : 1'bx)) = 1114; - if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q15 : 1'bx)) = 1114; - (A0 => Q) = 631; - (A1 => Q) = 472; - (A2 => Q) = 407; - (A3 => Q) = 238; - endspecify -endmodule - -(* abc9_box, lib_whitebox *) -module SRLC32E ( - output Q, - output Q31, - input [4:0] A, - input CE, - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK, - input D -); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - - reg [31:0] r = INIT; - assign Q31 = r[31]; - assign Q = r[A]; - generate - if (IS_CLK_INVERTED) begin - always @(negedge CLK) if (CE) r <= { r[30:0], D }; - end - else - always @(posedge CLK) if (CE) r <= { r[30:0], D }; - endgenerate - specify - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912 - $setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173); - $setup(D , negedge CLK &&& IS_CLK_INVERTED, 173); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 - $setup(CE, posedge CLK &&& !IS_CLK_INVERTED, 109); - $setup(CE, negedge CLK &&& IS_CLK_INVERTED, 109); - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905 - if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : 1'bx)) = 1472; - if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : 1'bx)) = 1472; - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904 - if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q31 : 1'bx)) = 1114; - if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q31 : 1'bx)) = 1114; - (A[0] => Q) = 642; - (A[1] => Q) = 631; - (A[2] => Q) = 472; - (A[3] => Q) = 407; - (A[4] => Q) = 238; - endspecify -endmodule - -module CFGLUT5 ( - output CDO, - output O5, - output O6, - input I4, - input I3, - input I2, - input I1, - input I0, - input CDI, - input CE, - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK -); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - wire clk = CLK ^ IS_CLK_INVERTED; - reg [31:0] r = INIT; - assign CDO = r[31]; - assign O5 = r[{1'b0, I3, I2, I1, I0}]; - assign O6 = r[{I4, I3, I2, I1, I0}]; - always @(posedge clk) if (CE) r <= {r[30:0], CDI}; -endmodule - // DSP -// Virtex 2, Virtex 2 Pro, Spartan 3. - -// Asynchronous mode. - -module MULT18X18 ( - input signed [17:0] A, - input signed [17:0] B, - output signed [35:0] P -); - -assign P = A * B; - -endmodule - -// Synchronous mode. - -module MULT18X18S ( - input signed [17:0] A, - input signed [17:0] B, - output reg signed [35:0] P, - (* clkbuf_sink *) - input C, - input CE, - input R -); - -always @(posedge C) - if (R) - P <= 0; - else if (CE) - P <= A * B; - -endmodule - -// Spartan 3E, Spartan 3A. - -module MULT18X18SIO ( - input signed [17:0] A, - input signed [17:0] B, - output signed [35:0] P, - (* clkbuf_sink *) - input CLK, - input CEA, - input CEB, - input CEP, - input RSTA, - input RSTB, - input RSTP, - input signed [17:0] BCIN, - output signed [17:0] BCOUT -); - -parameter integer AREG = 1; -parameter integer BREG = 1; -parameter B_INPUT = "DIRECT"; -parameter integer PREG = 1; - -// The multiplier. -wire signed [35:0] P_MULT; -wire signed [17:0] A_MULT; -wire signed [17:0] B_MULT; -assign P_MULT = A_MULT * B_MULT; - -// The cascade output. -assign BCOUT = B_MULT; - -// The B input multiplexer. -wire signed [17:0] B_MUX; -assign B_MUX = (B_INPUT == "DIRECT") ? B : BCIN; - -// The registers. -reg signed [17:0] A_REG; -reg signed [17:0] B_REG; -reg signed [35:0] P_REG; - -initial begin - A_REG = 0; - B_REG = 0; - P_REG = 0; -end - -always @(posedge CLK) begin - if (RSTA) - A_REG <= 0; - else if (CEA) - A_REG <= A; - - if (RSTB) - B_REG <= 0; - else if (CEB) - B_REG <= B_MUX; - - if (RSTP) - P_REG <= 0; - else if (CEP) - P_REG <= P_MULT; -end - -// The register enables. -assign A_MULT = (AREG == 1) ? A_REG : A; -assign B_MULT = (BREG == 1) ? B_REG : B_MUX; -assign P = (PREG == 1) ? P_REG : P_MULT; - -endmodule - -// Spartan 3A DSP. - -module DSP48A ( - input signed [17:0] A, - input signed [17:0] B, - input signed [47:0] C, - input signed [17:0] D, - input signed [47:0] PCIN, - input CARRYIN, - input [7:0] OPMODE, - output signed [47:0] P, - output signed [17:0] BCOUT, - output signed [47:0] PCOUT, - output CARRYOUT, - (* clkbuf_sink *) - input CLK, - input CEA, - input CEB, - input CEC, - input CED, - input CEM, - input CECARRYIN, - input CEOPMODE, - input CEP, - input RSTA, - input RSTB, - input RSTC, - input RSTD, - input RSTM, - input RSTCARRYIN, - input RSTOPMODE, - input RSTP -); - -parameter integer A0REG = 0; -parameter integer A1REG = 1; -parameter integer B0REG = 0; -parameter integer B1REG = 1; -parameter integer CREG = 1; -parameter integer DREG = 1; -parameter integer MREG = 1; -parameter integer CARRYINREG = 1; -parameter integer OPMODEREG = 1; -parameter integer PREG = 1; -parameter CARRYINSEL = "CARRYIN"; -parameter RSTTYPE = "SYNC"; - -// This is a strict subset of Spartan 6 -- reuse its model. - -/* verilator lint_off PINMISSING */ -DSP48A1 #( - .A0REG(A0REG), - .A1REG(A1REG), - .B0REG(B0REG), - .B1REG(B1REG), - .CREG(CREG), - .DREG(DREG), - .MREG(MREG), - .CARRYINREG(CARRYINREG), - .CARRYOUTREG(0), - .OPMODEREG(OPMODEREG), - .PREG(PREG), - .CARRYINSEL(CARRYINSEL), - .RSTTYPE(RSTTYPE) -) upgrade ( - .A(A), - .B(B), - .C(C), - .D(D), - .PCIN(PCIN), - .CARRYIN(CARRYIN), - .OPMODE(OPMODE), - // M unconnected - .P(P), - .BCOUT(BCOUT), - .PCOUT(PCOUT), - .CARRYOUT(CARRYOUT), - // CARRYOUTF unconnected - .CLK(CLK), - .CEA(CEA), - .CEB(CEB), - .CEC(CEC), - .CED(CED), - .CEM(CEM), - .CECARRYIN(CECARRYIN), - .CEOPMODE(CEOPMODE), - .CEP(CEP), - .RSTA(RSTA), - .RSTB(RSTB), - .RSTC(RSTC), - .RSTD(RSTD), - .RSTM(RSTM), - .RSTCARRYIN(RSTCARRYIN), - .RSTOPMODE(RSTOPMODE), - .RSTP(RSTP) -); -/* verilator lint_on PINMISSING */ - -endmodule - -// Spartan 6. - -module DSP48A1 ( - input signed [17:0] A, - input signed [17:0] B, - input signed [47:0] C, - input signed [17:0] D, - input signed [47:0] PCIN, - input CARRYIN, - input [7:0] OPMODE, - output signed [35:0] M, - output signed [47:0] P, - output signed [17:0] BCOUT, - output signed [47:0] PCOUT, - output CARRYOUT, - output CARRYOUTF, - (* clkbuf_sink *) - input CLK, - input CEA, - input CEB, - input CEC, - input CED, - input CEM, - input CECARRYIN, - input CEOPMODE, - input CEP, - input RSTA, - input RSTB, - input RSTC, - input RSTD, - input RSTM, - input RSTCARRYIN, - input RSTOPMODE, - input RSTP -); - -parameter integer A0REG = 0; -parameter integer A1REG = 1; -parameter integer B0REG = 0; -parameter integer B1REG = 1; -parameter integer CREG = 1; -parameter integer DREG = 1; -parameter integer MREG = 1; -parameter integer CARRYINREG = 1; -parameter integer CARRYOUTREG = 1; -parameter integer OPMODEREG = 1; -parameter integer PREG = 1; -parameter CARRYINSEL = "OPMODE5"; -parameter RSTTYPE = "SYNC"; - -wire signed [35:0] M_MULT; -wire signed [47:0] P_IN; -wire signed [17:0] A0_OUT; -wire signed [17:0] B0_OUT; -wire signed [17:0] A1_OUT; -wire signed [17:0] B1_OUT; -wire signed [17:0] B1_IN; -wire signed [47:0] C_OUT; -wire signed [17:0] D_OUT; -wire signed [7:0] OPMODE_OUT; -wire CARRYIN_OUT; -wire CARRYOUT_IN; -wire CARRYIN_IN; -reg signed [47:0] XMUX; -reg signed [47:0] ZMUX; - -// The registers. -reg signed [17:0] A0_REG; -reg signed [17:0] A1_REG; -reg signed [17:0] B0_REG; -reg signed [17:0] B1_REG; -reg signed [47:0] C_REG; -reg signed [17:0] D_REG; -reg signed [35:0] M_REG; -reg signed [47:0] P_REG; -reg [7:0] OPMODE_REG; -reg CARRYIN_REG; -reg CARRYOUT_REG; - -initial begin - A0_REG = 0; - A1_REG = 0; - B0_REG = 0; - B1_REG = 0; - C_REG = 0; - D_REG = 0; - M_REG = 0; - P_REG = 0; - OPMODE_REG = 0; - CARRYIN_REG = 0; - CARRYOUT_REG = 0; -end - -generate - -if (RSTTYPE == "SYNC") begin - always @(posedge CLK) begin - if (RSTA) begin - A0_REG <= 0; - A1_REG <= 0; - end else if (CEA) begin - A0_REG <= A; - A1_REG <= A0_OUT; - end - end - - always @(posedge CLK) begin - if (RSTB) begin - B0_REG <= 0; - B1_REG <= 0; - end else if (CEB) begin - B0_REG <= B; - B1_REG <= B1_IN; - end - end - - always @(posedge CLK) begin - if (RSTC) begin - C_REG <= 0; - end else if (CEC) begin - C_REG <= C; - end - end - - always @(posedge CLK) begin - if (RSTD) begin - D_REG <= 0; - end else if (CED) begin - D_REG <= D; - end - end - - always @(posedge CLK) begin - if (RSTM) begin - M_REG <= 0; - end else if (CEM) begin - M_REG <= M_MULT; - end - end - - always @(posedge CLK) begin - if (RSTP) begin - P_REG <= 0; - end else if (CEP) begin - P_REG <= P_IN; - end - end - - always @(posedge CLK) begin - if (RSTOPMODE) begin - OPMODE_REG <= 0; - end else if (CEOPMODE) begin - OPMODE_REG <= OPMODE; - end - end - - always @(posedge CLK) begin - if (RSTCARRYIN) begin - CARRYIN_REG <= 0; - CARRYOUT_REG <= 0; - end else if (CECARRYIN) begin - CARRYIN_REG <= CARRYIN_IN; - CARRYOUT_REG <= CARRYOUT_IN; - end - end -end else begin - always @(posedge CLK, posedge RSTA) begin - if (RSTA) begin - A0_REG <= 0; - A1_REG <= 0; - end else if (CEA) begin - A0_REG <= A; - A1_REG <= A0_OUT; - end - end - - always @(posedge CLK, posedge RSTB) begin - if (RSTB) begin - B0_REG <= 0; - B1_REG <= 0; - end else if (CEB) begin - B0_REG <= B; - B1_REG <= B1_IN; - end - end - - always @(posedge CLK, posedge RSTC) begin - if (RSTC) begin - C_REG <= 0; - end else if (CEC) begin - C_REG <= C; - end - end - - always @(posedge CLK, posedge RSTD) begin - if (RSTD) begin - D_REG <= 0; - end else if (CED) begin - D_REG <= D; - end - end - - always @(posedge CLK, posedge RSTM) begin - if (RSTM) begin - M_REG <= 0; - end else if (CEM) begin - M_REG <= M_MULT; - end - end - - always @(posedge CLK, posedge RSTP) begin - if (RSTP) begin - P_REG <= 0; - end else if (CEP) begin - P_REG <= P_IN; - end - end - - always @(posedge CLK, posedge RSTOPMODE) begin - if (RSTOPMODE) begin - OPMODE_REG <= 0; - end else if (CEOPMODE) begin - OPMODE_REG <= OPMODE; - end - end - - always @(posedge CLK, posedge RSTCARRYIN) begin - if (RSTCARRYIN) begin - CARRYIN_REG <= 0; - CARRYOUT_REG <= 0; - end else if (CECARRYIN) begin - CARRYIN_REG <= CARRYIN_IN; - CARRYOUT_REG <= CARRYOUT_IN; - end - end -end - -endgenerate - -// The register enables. -assign A0_OUT = (A0REG == 1) ? A0_REG : A; -assign A1_OUT = (A1REG == 1) ? A1_REG : A0_OUT; -assign B0_OUT = (B0REG == 1) ? B0_REG : B; -assign B1_OUT = (B1REG == 1) ? B1_REG : B1_IN; -assign C_OUT = (CREG == 1) ? C_REG : C; -assign D_OUT = (DREG == 1) ? D_REG : D; -assign M = (MREG == 1) ? M_REG : M_MULT; -assign P = (PREG == 1) ? P_REG : P_IN; -assign OPMODE_OUT = (OPMODEREG == 1) ? OPMODE_REG : OPMODE; -assign CARRYIN_OUT = (CARRYINREG == 1) ? CARRYIN_REG : CARRYIN_IN; -assign CARRYOUT = (CARRYOUTREG == 1) ? CARRYOUT_REG : CARRYOUT_IN; -assign CARRYOUTF = CARRYOUT; - -// The pre-adder. -wire signed [17:0] PREADDER; -assign B1_IN = OPMODE_OUT[4] ? PREADDER : B0_OUT; -assign PREADDER = OPMODE_OUT[6] ? D_OUT - B0_OUT : D_OUT + B0_OUT; - -// The multiplier. -assign M_MULT = A1_OUT * B1_OUT; - -// The carry in selection. -assign CARRYIN_IN = (CARRYINSEL == "OPMODE5") ? OPMODE_OUT[5] : CARRYIN; - -// The post-adder inputs. -always @* begin - case (OPMODE_OUT[1:0]) - 2'b00: XMUX <= 0; - 2'b01: XMUX <= M; - 2'b10: XMUX <= P; - 2'b11: XMUX <= {D_OUT[11:0], A1_OUT, B1_OUT}; - default: XMUX <= 48'hxxxxxxxxxxxx; - endcase -end - -always @* begin - case (OPMODE_OUT[3:2]) - 2'b00: ZMUX <= 0; - 2'b01: ZMUX <= PCIN; - 2'b10: ZMUX <= P; - 2'b11: ZMUX <= C_OUT; - default: ZMUX <= 48'hxxxxxxxxxxxx; - endcase -end - -// The post-adder. -wire signed [48:0] X_EXT; -wire signed [48:0] Z_EXT; -assign X_EXT = {1'b0, XMUX}; -assign Z_EXT = {1'b0, ZMUX}; -assign {CARRYOUT_IN, P_IN} = OPMODE_OUT[7] ? (Z_EXT - (X_EXT + CARRYIN_OUT)) : (Z_EXT + X_EXT + CARRYIN_OUT); - -// Cascade outputs. -assign BCOUT = B1_OUT; -assign PCOUT = P; - -endmodule - -module DSP48 ( - input signed [17:0] A, - input signed [17:0] B, - input signed [47:0] C, - input signed [17:0] BCIN, - input signed [47:0] PCIN, - input CARRYIN, - input [6:0] OPMODE, - input SUBTRACT, - input [1:0] CARRYINSEL, - output signed [47:0] P, - output signed [17:0] BCOUT, - output signed [47:0] PCOUT, - (* clkbuf_sink *) - input CLK, - input CEA, - input CEB, - input CEC, - input CEM, - input CECARRYIN, - input CECINSUB, - input CECTRL, - input CEP, - input RSTA, - input RSTB, - input RSTC, - input RSTM, - input RSTCARRYIN, - input RSTCTRL, - input RSTP -); - -parameter integer AREG = 1; -parameter integer BREG = 1; -parameter integer CREG = 1; -parameter integer MREG = 1; -parameter integer PREG = 1; -parameter integer CARRYINREG = 1; -parameter integer CARRYINSELREG = 1; -parameter integer OPMODEREG = 1; -parameter integer SUBTRACTREG = 1; -parameter B_INPUT = "DIRECT"; -parameter LEGACY_MODE = "MULT18X18S"; - -wire signed [17:0] A_OUT; -wire signed [17:0] B_OUT; -wire signed [47:0] C_OUT; -wire signed [35:0] M_MULT; -wire signed [35:0] M_OUT; -wire signed [47:0] P_IN; -wire [6:0] OPMODE_OUT; -wire [1:0] CARRYINSEL_OUT; -wire CARRYIN_OUT; -wire SUBTRACT_OUT; -reg INT_CARRYIN_XY; -reg INT_CARRYIN_Z; -reg signed [47:0] XMUX; -reg signed [47:0] YMUX; -wire signed [47:0] XYMUX; -reg signed [47:0] ZMUX; -reg CIN; - -// The B input multiplexer. -wire signed [17:0] B_MUX; -assign B_MUX = (B_INPUT == "DIRECT") ? B : BCIN; - -// The cascade output. -assign BCOUT = B_OUT; -assign PCOUT = P; - -// The registers. -reg signed [17:0] A0_REG; -reg signed [17:0] A1_REG; -reg signed [17:0] B0_REG; -reg signed [17:0] B1_REG; -reg signed [47:0] C_REG; -reg signed [35:0] M_REG; -reg signed [47:0] P_REG; -reg [6:0] OPMODE_REG; -reg [1:0] CARRYINSEL_REG; -reg SUBTRACT_REG; -reg CARRYIN_REG; -reg INT_CARRYIN_XY_REG; - -initial begin - A0_REG = 0; - A1_REG = 0; - B0_REG = 0; - B1_REG = 0; - C_REG = 0; - M_REG = 0; - P_REG = 0; - OPMODE_REG = 0; - CARRYINSEL_REG = 0; - SUBTRACT_REG = 0; - CARRYIN_REG = 0; - INT_CARRYIN_XY_REG = 0; -end - -always @(posedge CLK) begin - if (RSTA) begin - A0_REG <= 0; - A1_REG <= 0; - end else if (CEA) begin - A0_REG <= A; - A1_REG <= A0_REG; - end - if (RSTB) begin - B0_REG <= 0; - B1_REG <= 0; - end else if (CEB) begin - B0_REG <= B_MUX; - B1_REG <= B0_REG; - end - if (RSTC) begin - C_REG <= 0; - end else if (CEC) begin - C_REG <= C; - end - if (RSTM) begin - M_REG <= 0; - end else if (CEM) begin - M_REG <= M_MULT; - end - if (RSTP) begin - P_REG <= 0; - end else if (CEP) begin - P_REG <= P_IN; - end - if (RSTCTRL) begin - OPMODE_REG <= 0; - CARRYINSEL_REG <= 0; - SUBTRACT_REG <= 0; - end else begin - if (CECTRL) begin - OPMODE_REG <= OPMODE; - CARRYINSEL_REG <= CARRYINSEL; - end - if (CECINSUB) - SUBTRACT_REG <= SUBTRACT; - end - if (RSTCARRYIN) begin - CARRYIN_REG <= 0; - INT_CARRYIN_XY_REG <= 0; - end else begin - if (CECINSUB) - CARRYIN_REG <= CARRYIN; - if (CECARRYIN) - INT_CARRYIN_XY_REG <= INT_CARRYIN_XY; - end -end - -// The register enables. -assign A_OUT = (AREG == 2) ? A1_REG : (AREG == 1) ? A0_REG : A; -assign B_OUT = (BREG == 2) ? B1_REG : (BREG == 1) ? B0_REG : B_MUX; -assign C_OUT = (CREG == 1) ? C_REG : C; -assign M_OUT = (MREG == 1) ? M_REG : M_MULT; -assign P = (PREG == 1) ? P_REG : P_IN; -assign OPMODE_OUT = (OPMODEREG == 1) ? OPMODE_REG : OPMODE; -assign SUBTRACT_OUT = (SUBTRACTREG == 1) ? SUBTRACT_REG : SUBTRACT; -assign CARRYINSEL_OUT = (CARRYINSELREG == 1) ? CARRYINSEL_REG : CARRYINSEL; -assign CARRYIN_OUT = (CARRYINREG == 1) ? CARRYIN_REG : CARRYIN; - -// The multiplier. -assign M_MULT = A_OUT * B_OUT; - -// The post-adder inputs. -always @* begin - case (OPMODE_OUT[1:0]) - 2'b00: XMUX <= 0; - 2'b10: XMUX <= P; - 2'b11: XMUX <= {{12{A_OUT[17]}}, A_OUT, B_OUT}; - default: XMUX <= 48'hxxxxxxxxxxxx; - endcase - case (OPMODE_OUT[1:0]) - 2'b01: INT_CARRYIN_XY <= A_OUT[17] ~^ B_OUT[17]; - 2'b11: INT_CARRYIN_XY <= ~A_OUT[17]; - // TODO: not tested in hardware. - default: INT_CARRYIN_XY <= A_OUT[17] ~^ B_OUT[17]; - endcase -end - -always @* begin - case (OPMODE_OUT[3:2]) - 2'b00: YMUX <= 0; - 2'b11: YMUX <= C_OUT; - default: YMUX <= 48'hxxxxxxxxxxxx; - endcase -end - -assign XYMUX = (OPMODE_OUT[3:0] == 4'b0101) ? M_OUT : (XMUX + YMUX); - -always @* begin - case (OPMODE_OUT[6:4]) - 3'b000: ZMUX <= 0; - 3'b001: ZMUX <= PCIN; - 3'b010: ZMUX <= P; - 3'b011: ZMUX <= C_OUT; - 3'b101: ZMUX <= {{17{PCIN[47]}}, PCIN[47:17]}; - 3'b110: ZMUX <= {{17{P[47]}}, P[47:17]}; - default: ZMUX <= 48'hxxxxxxxxxxxx; - endcase - // TODO: check how all this works on actual hw. - if (OPMODE_OUT[1:0] == 2'b10) - INT_CARRYIN_Z <= ~P[47]; - else - case (OPMODE_OUT[6:4]) - 3'b001: INT_CARRYIN_Z <= ~PCIN[47]; - 3'b010: INT_CARRYIN_Z <= ~P[47]; - 3'b101: INT_CARRYIN_Z <= ~PCIN[47]; - 3'b110: INT_CARRYIN_Z <= ~P[47]; - default: INT_CARRYIN_Z <= 1'bx; - endcase -end - -always @* begin - case (CARRYINSEL_OUT) - 2'b00: CIN <= CARRYIN_OUT; - 2'b01: CIN <= INT_CARRYIN_Z; - 2'b10: CIN <= INT_CARRYIN_XY; - 2'b11: CIN <= INT_CARRYIN_XY_REG; - default: CIN <= 1'bx; - endcase -end - -// The post-adder. -assign P_IN = SUBTRACT_OUT ? (ZMUX - (XYMUX + CIN)) : (ZMUX + XYMUX + CIN); - -endmodule - -// TODO: DSP48E (Virtex 5). - // Virtex 6, Series 7. `ifdef YOSYS @@ -3470,8 +1484,6 @@ module DSP48E1 ( endmodule -// TODO: DSP48E2 (Ultrascale). - // Block RAM module RAMB18E1 ( diff --git a/techlibs/analogdevices/lutrams.txt b/techlibs/analogdevices/lutrams.txt index ae1c16ebb..fbfd530c3 100644 --- a/techlibs/analogdevices/lutrams.txt +++ b/techlibs/analogdevices/lutrams.txt @@ -1,19 +1,14 @@ -# LUT RAMs for Virtex 5, Virtex 6, Spartan 6, Series 7. -# The corresponding mapping file is lutrams_xc5v_map.v - # Single-port RAMs. ram distributed $__ANALOGDEVICES_LUTRAM_SP_ { - cost 8; - widthscale; + cost 1; option "ABITS" 5 { abits 5; - widths 8 global; } option "ABITS" 6 { abits 6; - widths 4 global; } + width 1; init no_undef; prune_rom; port arsw "RW" { @@ -24,47 +19,19 @@ ram distributed $__ANALOGDEVICES_LUTRAM_SP_ { # Dual-port RAMs. ram distributed $__ANALOGDEVICES_LUTRAM_DP_ { - cost 8; - widthscale; + cost 1; option "ABITS" 5 { abits 5; - widths 4 global; } option "ABITS" 6 { abits 6; - widths 2 global; - } - option "ABITS" 7 { - abits 7; - widths 1 global; } + width 1; init no_undef; prune_rom; + port ar "R" { + } port arsw "RW" { clock posedge; } - port ar "R" { - } -} - -# Simple dual port RAMs. - -ram distributed $__ANALOGDEVICES_LUTRAM_SDP_ { - cost 8; - widthscale 7; - option "ABITS" 5 { - abits 5; - widths 6 global; - } - option "ABITS" 6 { - abits 6; - widths 3 global; - } - init no_undef; - prune_rom; - port sw "W" { - clock posedge; - } - port ar "R" { - } } diff --git a/techlibs/analogdevices/lutrams_map.v b/techlibs/analogdevices/lutrams_map.v index 2142fdf7c..cb148f56c 100644 --- a/techlibs/analogdevices/lutrams_map.v +++ b/techlibs/analogdevices/lutrams_map.v @@ -1,123 +1,51 @@ -// LUT RAMs for Virtex 5, Virtex 6, Spartan 6, Series 7, Ultrascale. -// The definitions are in lutrams_xc5v.txt. - - module $__ANALOGDEVICES_LUTRAM_SP_ (...); parameter INIT = 0; parameter OPTION_ABITS = 5; -parameter WIDTH = 8; -parameter BITS_USED = 0; -output [WIDTH-1:0] PORT_RW_RD_DATA; -input [WIDTH-1:0] PORT_RW_WR_DATA; +output PORT_RW_RD_DATA; +input PORT_RW_WR_DATA; input [OPTION_ABITS-1:0] PORT_RW_ADDR; input PORT_RW_WR_EN; input PORT_RW_CLK; -function [(1 << OPTION_ABITS)-1:0] init_slice; - input integer idx; - integer i; - for (i = 0; i < (1 << OPTION_ABITS); i = i + 1) - init_slice[i] = INIT[i * WIDTH + idx]; -endfunction - -function [(2 << OPTION_ABITS)-1:0] init_slice2; - input integer idx; - integer i; - for (i = 0; i < (1 << OPTION_ABITS); i = i + 1) - init_slice2[2 * i +: 2] = INIT[i * WIDTH + idx * 2 +: 2]; -endfunction - generate case(OPTION_ABITS) -5: if (WIDTH == 8) - RAM32M +5: + RAMS32X1 #( - .INIT_D(init_slice2(0)), - .INIT_C(init_slice2(1)), - .INIT_B(init_slice2(2)), - .INIT_A(init_slice2(3)), + .INIT(INIT) ) _TECHMAP_REPLACE_ ( - .DOA(PORT_RW_RD_DATA[7:6]), - .DOB(PORT_RW_RD_DATA[5:4]), - .DOC(PORT_RW_RD_DATA[3:2]), - .DOD(PORT_RW_RD_DATA[1:0]), - .DIA(PORT_RW_WR_DATA[7:6]), - .DIB(PORT_RW_WR_DATA[5:4]), - .DIC(PORT_RW_WR_DATA[3:2]), - .DID(PORT_RW_WR_DATA[1:0]), - .ADDRA(PORT_RW_ADDR), - .ADDRB(PORT_RW_ADDR), - .ADDRC(PORT_RW_ADDR), - .ADDRD(PORT_RW_ADDR), - .WE(PORT_RW_WR_EN), - .WCLK(PORT_RW_CLK), - ); -else - RAM32M16 - #( - .INIT_H(init_slice2(0)), - .INIT_G(init_slice2(1)), - .INIT_F(init_slice2(2)), - .INIT_E(init_slice2(3)), - .INIT_D(init_slice2(4)), - .INIT_C(init_slice2(5)), - .INIT_B(init_slice2(6)), - .INIT_A(init_slice2(7)), - ) - _TECHMAP_REPLACE_ - ( - .DOA(PORT_RW_RD_DATA[15:14]), - .DOB(PORT_RW_RD_DATA[13:12]), - .DOC(PORT_RW_RD_DATA[11:10]), - .DOD(PORT_RW_RD_DATA[9:8]), - .DOE(PORT_RW_RD_DATA[7:6]), - .DOF(PORT_RW_RD_DATA[5:4]), - .DOG(PORT_RW_RD_DATA[3:2]), - .DOH(PORT_RW_RD_DATA[1:0]), - .DIA(PORT_RW_WR_DATA[15:14]), - .DIB(PORT_RW_WR_DATA[13:12]), - .DIC(PORT_RW_WR_DATA[11:10]), - .DID(PORT_RW_WR_DATA[9:8]), - .DIE(PORT_RW_WR_DATA[7:6]), - .DIF(PORT_RW_WR_DATA[5:4]), - .DIG(PORT_RW_WR_DATA[3:2]), - .DIH(PORT_RW_WR_DATA[1:0]), - .ADDRA(PORT_RW_ADDR), - .ADDRB(PORT_RW_ADDR), - .ADDRC(PORT_RW_ADDR), - .ADDRD(PORT_RW_ADDR), - .ADDRE(PORT_RW_ADDR), - .ADDRF(PORT_RW_ADDR), - .ADDRG(PORT_RW_ADDR), - .ADDRH(PORT_RW_ADDR), - .WE(PORT_RW_WR_EN), + .O(PORT_RW_RD_DATA), + .A0(PORT_RW_ADDR[0]), + .A1(PORT_RW_ADDR[1]), + .A2(PORT_RW_ADDR[2]), + .A3(PORT_RW_ADDR[3]), + .A4(PORT_RW_ADDR[4]), + .D(PORT_RW_WR_DATA), .WCLK(PORT_RW_CLK), + .WE(PORT_RW_WR_EN) ); 6: begin - genvar i; - for (i = 0; i < WIDTH; i = i + 1) - if (BITS_USED[i]) - RAM64X1S - #( - .INIT(init_slice(i)), - ) - slice - ( - .A0(PORT_RW_ADDR[0]), - .A1(PORT_RW_ADDR[1]), - .A2(PORT_RW_ADDR[2]), - .A3(PORT_RW_ADDR[3]), - .A4(PORT_RW_ADDR[4]), - .A5(PORT_RW_ADDR[5]), - .D(PORT_RW_WR_DATA[i]), - .O(PORT_RW_RD_DATA[i]), - .WE(PORT_RW_WR_EN), - .WCLK(PORT_RW_CLK), - ); + RAMS64X1 + #( + .INIT(INIT) + ) + _TECHMAP_REPLACE_ + ( + .O(PORT_RW_RD_DATA), + .A0(PORT_RW_ADDR[0]), + .A1(PORT_RW_ADDR[1]), + .A2(PORT_RW_ADDR[2]), + .A3(PORT_RW_ADDR[3]), + .A4(PORT_RW_ADDR[4]), + .A5(PORT_RW_ADDR[5]), + .D(PORT_RW_WR_DATA), + .WCLK(PORT_RW_CLK), + .WE(PORT_RW_WR_EN) + ); end default: $error("invalid OPTION_ABITS/WIDTH combination"); @@ -131,325 +59,65 @@ module $__ANALOGDEVICES_LUTRAM_DP_ (...); parameter INIT = 0; parameter OPTION_ABITS = 5; -parameter WIDTH = 4; -parameter BITS_USED = 0; -output [WIDTH-1:0] PORT_RW_RD_DATA; -input [WIDTH-1:0] PORT_RW_WR_DATA; +output PORT_RW_RD_DATA; +input PORT_RW_WR_DATA; input [OPTION_ABITS-1:0] PORT_RW_ADDR; input PORT_RW_WR_EN; input PORT_RW_CLK; -output [WIDTH-1:0] PORT_R_RD_DATA; +output PORT_R_RD_DATA; input [OPTION_ABITS-1:0] PORT_R_ADDR; -function [(1 << OPTION_ABITS)-1:0] init_slice; - input integer idx; - integer i; - for (i = 0; i < (1 << OPTION_ABITS); i = i + 1) - init_slice[i] = INIT[i * WIDTH + idx]; -endfunction - -function [(2 << OPTION_ABITS)-1:0] init_slice2; - input integer idx; - integer i; - for (i = 0; i < (1 << OPTION_ABITS); i = i + 1) - init_slice2[2 * i +: 2] = INIT[i * WIDTH + idx * 2 +: 2]; -endfunction - generate case (OPTION_ABITS) -5: if (WIDTH == 4) - RAM32M +5: + RAMD32X1 #( - .INIT_D(init_slice2(0)), - .INIT_C(init_slice2(0)), - .INIT_B(init_slice2(1)), - .INIT_A(init_slice2(1)), + .INIT(INIT) ) _TECHMAP_REPLACE_ ( - .DOA(PORT_R_RD_DATA[3:2]), - .DOB(PORT_RW_RD_DATA[3:2]), - .DOC(PORT_R_RD_DATA[1:0]), - .DOD(PORT_RW_RD_DATA[1:0]), - .DIA(PORT_RW_WR_DATA[3:2]), - .DIB(PORT_RW_WR_DATA[3:2]), - .DIC(PORT_RW_WR_DATA[1:0]), - .DID(PORT_RW_WR_DATA[1:0]), - .ADDRA(PORT_R_ADDR), - .ADDRB(PORT_RW_ADDR), - .ADDRC(PORT_R_ADDR), - .ADDRD(PORT_RW_ADDR), - .WE(PORT_RW_WR_EN), + .SPO(PORT_RW_RD_DATA), + .DPO(PORT_R_RD_DATA), + .A0(PORT_RW_ADDR[0]), + .A1(PORT_RW_ADDR[1]), + .A2(PORT_RW_ADDR[2]), + .A3(PORT_RW_ADDR[3]), + .A4(PORT_RW_ADDR[4]), + .D(PORT_RW_WR_DATA), + .DPRA0(PORT_R_ADDR[0]), + .DPRA1(PORT_R_ADDR[1]), + .DPRA2(PORT_R_ADDR[2]), + .DPRA3(PORT_R_ADDR[3]), + .DPRA4(PORT_R_ADDR[4]), .WCLK(PORT_RW_CLK), + .WE(PORT_RW_WR_EN) ); -else - RAM32M16 +6: + RAMD64X1 #( - .INIT_H(init_slice2(0)), - .INIT_G(init_slice2(0)), - .INIT_F(init_slice2(1)), - .INIT_E(init_slice2(1)), - .INIT_D(init_slice2(2)), - .INIT_C(init_slice2(2)), - .INIT_B(init_slice2(3)), - .INIT_A(init_slice2(3)), + .INIT(INIT) ) _TECHMAP_REPLACE_ ( - .DOA(PORT_R_RD_DATA[7:6]), - .DOB(PORT_RW_RD_DATA[7:6]), - .DOC(PORT_R_RD_DATA[5:4]), - .DOD(PORT_RW_RD_DATA[5:4]), - .DOE(PORT_R_RD_DATA[3:2]), - .DOF(PORT_RW_RD_DATA[3:2]), - .DOG(PORT_R_RD_DATA[1:0]), - .DOH(PORT_RW_RD_DATA[1:0]), - .DIA(PORT_RW_WR_DATA[7:6]), - .DIB(PORT_RW_WR_DATA[7:6]), - .DIC(PORT_RW_WR_DATA[5:4]), - .DID(PORT_RW_WR_DATA[5:4]), - .DIE(PORT_RW_WR_DATA[3:2]), - .DIF(PORT_RW_WR_DATA[3:2]), - .DIG(PORT_RW_WR_DATA[1:0]), - .DIH(PORT_RW_WR_DATA[1:0]), - .ADDRA(PORT_R_ADDR), - .ADDRB(PORT_RW_ADDR), - .ADDRC(PORT_R_ADDR), - .ADDRD(PORT_RW_ADDR), - .ADDRE(PORT_R_ADDR), - .ADDRF(PORT_RW_ADDR), - .ADDRG(PORT_R_ADDR), - .ADDRH(PORT_RW_ADDR), - .WE(PORT_RW_WR_EN), + .SPO(PORT_RW_RD_DATA), + .DPO(PORT_R_RD_DATA), + .A0(PORT_RW_ADDR[0]), + .A1(PORT_RW_ADDR[1]), + .A2(PORT_RW_ADDR[2]), + .A3(PORT_RW_ADDR[3]), + .A4(PORT_RW_ADDR[4]), + .A5(PORT_RW_ADDR[5]), + .D(PORT_RW_WR_DATA), + .DPRA0(PORT_R_ADDR[0]), + .DPRA1(PORT_R_ADDR[1]), + .DPRA2(PORT_R_ADDR[2]), + .DPRA3(PORT_R_ADDR[3]), + .DPRA4(PORT_R_ADDR[4]), + .DPRA5(PORT_R_ADDR[5]), .WCLK(PORT_RW_CLK), - ); -6: begin - genvar i; - for (i = 0; i < WIDTH; i = i + 1) - if (BITS_USED[i]) - RAM64X1D - #( - .INIT(init_slice(i)), - ) - slice - ( - .A0(PORT_RW_ADDR[0]), - .A1(PORT_RW_ADDR[1]), - .A2(PORT_RW_ADDR[2]), - .A3(PORT_RW_ADDR[3]), - .A4(PORT_RW_ADDR[4]), - .A5(PORT_RW_ADDR[5]), - .D(PORT_RW_WR_DATA[i]), - .SPO(PORT_RW_RD_DATA[i]), - .WE(PORT_RW_WR_EN), - .WCLK(PORT_RW_CLK), - .DPRA0(PORT_R_ADDR[0]), - .DPRA1(PORT_R_ADDR[1]), - .DPRA2(PORT_R_ADDR[2]), - .DPRA3(PORT_R_ADDR[3]), - .DPRA4(PORT_R_ADDR[4]), - .DPRA5(PORT_R_ADDR[5]), - .DPO(PORT_R_RD_DATA[i]), - ); -end -7: begin - genvar i; - for (i = 0; i < WIDTH; i = i + 1) - if (BITS_USED[i]) - RAM128X1D - #( - .INIT(init_slice(i)), - ) - slice - ( - .A(PORT_RW_ADDR), - .D(PORT_RW_WR_DATA[i]), - .SPO(PORT_RW_RD_DATA[i]), - .WE(PORT_RW_WR_EN), - .WCLK(PORT_RW_CLK), - .DPRA(PORT_R_ADDR), - .DPO(PORT_R_RD_DATA[i]), - ); -end -8: begin - genvar i; - for (i = 0; i < WIDTH; i = i + 1) - if (BITS_USED[i]) - RAM256X1D - #( - .INIT(init_slice(i)), - ) - slice - ( - .A(PORT_RW_ADDR), - .D(PORT_RW_WR_DATA[i]), - .SPO(PORT_RW_RD_DATA[i]), - .WE(PORT_RW_WR_EN), - .WCLK(PORT_RW_CLK), - .DPRA(PORT_R_ADDR), - .DPO(PORT_R_RD_DATA[i]), - ); -end -default: - $error("invalid OPTION_ABITS/WIDTH combination"); -endcase -endgenerate - -endmodule - - -module $__ANALOGDEVICES_LUTRAM_SDP_ (...); - -parameter INIT = 0; -parameter OPTION_ABITS = 5; -parameter WIDTH = 6; -parameter BITS_USED = 0; - -input [WIDTH-1:0] PORT_W_WR_DATA; -input [OPTION_ABITS-1:0] PORT_W_ADDR; -input PORT_W_WR_EN; -input PORT_W_CLK; - -output [WIDTH-1:0] PORT_R_RD_DATA; -input [OPTION_ABITS-1:0] PORT_R_ADDR; - -function [(1 << OPTION_ABITS)-1:0] init_slice; - input integer idx; - integer i; - for (i = 0; i < (1 << OPTION_ABITS); i = i + 1) - init_slice[i] = INIT[i * WIDTH + idx]; -endfunction - -function [(2 << OPTION_ABITS)-1:0] init_slice2; - input integer idx; - integer i; - for (i = 0; i < (1 << OPTION_ABITS); i = i + 1) - init_slice2[2 * i +: 2] = INIT[i * WIDTH + idx * 2 +: 2]; -endfunction - -generate -case (OPTION_ABITS) -5: if (WIDTH == 6) - RAM32M - #( - .INIT_C(init_slice2(0)), - .INIT_B(init_slice2(1)), - .INIT_A(init_slice2(2)), - ) - _TECHMAP_REPLACE_ - ( - .DOA(PORT_R_RD_DATA[5:4]), - .DOB(PORT_R_RD_DATA[3:2]), - .DOC(PORT_R_RD_DATA[1:0]), - .DIA(PORT_W_WR_DATA[5:4]), - .DIB(PORT_W_WR_DATA[3:2]), - .DIC(PORT_W_WR_DATA[1:0]), - .ADDRA(PORT_R_ADDR), - .ADDRB(PORT_R_ADDR), - .ADDRC(PORT_R_ADDR), - .ADDRD(PORT_W_ADDR), - .WE(PORT_W_WR_EN), - .WCLK(PORT_W_CLK), - ); -else - RAM32M16 - #( - .INIT_G(init_slice2(0)), - .INIT_F(init_slice2(1)), - .INIT_E(init_slice2(2)), - .INIT_D(init_slice2(3)), - .INIT_C(init_slice2(4)), - .INIT_B(init_slice2(5)), - .INIT_A(init_slice2(6)), - ) - _TECHMAP_REPLACE_ - ( - .DOA(PORT_R_RD_DATA[13:12]), - .DOB(PORT_R_RD_DATA[11:10]), - .DOC(PORT_R_RD_DATA[9:8]), - .DOD(PORT_R_RD_DATA[7:6]), - .DOE(PORT_R_RD_DATA[5:4]), - .DOF(PORT_R_RD_DATA[3:2]), - .DOG(PORT_R_RD_DATA[1:0]), - .DIA(PORT_W_WR_DATA[13:12]), - .DIB(PORT_W_WR_DATA[11:10]), - .DIC(PORT_W_WR_DATA[9:8]), - .DID(PORT_W_WR_DATA[7:6]), - .DIE(PORT_W_WR_DATA[5:4]), - .DIF(PORT_W_WR_DATA[3:2]), - .DIG(PORT_W_WR_DATA[1:0]), - .ADDRA(PORT_R_ADDR), - .ADDRB(PORT_R_ADDR), - .ADDRC(PORT_R_ADDR), - .ADDRD(PORT_R_ADDR), - .ADDRE(PORT_R_ADDR), - .ADDRF(PORT_R_ADDR), - .ADDRG(PORT_R_ADDR), - .ADDRH(PORT_W_ADDR), - .WE(PORT_W_WR_EN), - .WCLK(PORT_W_CLK), - ); -6: if (WIDTH == 3) - RAM64M - #( - .INIT_C(init_slice(0)), - .INIT_B(init_slice(1)), - .INIT_A(init_slice(2)), - ) - _TECHMAP_REPLACE_ - ( - .DOA(PORT_R_RD_DATA[2]), - .DOB(PORT_R_RD_DATA[1]), - .DOC(PORT_R_RD_DATA[0]), - .DIA(PORT_W_WR_DATA[2]), - .DIB(PORT_W_WR_DATA[1]), - .DIC(PORT_W_WR_DATA[0]), - .ADDRA(PORT_R_ADDR), - .ADDRB(PORT_R_ADDR), - .ADDRC(PORT_R_ADDR), - .ADDRD(PORT_W_ADDR), - .WE(PORT_W_WR_EN), - .WCLK(PORT_W_CLK), - ); -else - RAM64M8 - #( - .INIT_G(init_slice(0)), - .INIT_F(init_slice(1)), - .INIT_E(init_slice(2)), - .INIT_D(init_slice(3)), - .INIT_C(init_slice(4)), - .INIT_B(init_slice(5)), - .INIT_A(init_slice(6)), - ) - _TECHMAP_REPLACE_ - ( - .DOA(PORT_R_RD_DATA[6]), - .DOB(PORT_R_RD_DATA[5]), - .DOC(PORT_R_RD_DATA[4]), - .DOD(PORT_R_RD_DATA[3]), - .DOE(PORT_R_RD_DATA[2]), - .DOF(PORT_R_RD_DATA[1]), - .DOG(PORT_R_RD_DATA[0]), - .DIA(PORT_W_WR_DATA[6]), - .DIB(PORT_W_WR_DATA[5]), - .DIC(PORT_W_WR_DATA[4]), - .DID(PORT_W_WR_DATA[3]), - .DIE(PORT_W_WR_DATA[2]), - .DIF(PORT_W_WR_DATA[1]), - .DIG(PORT_W_WR_DATA[0]), - .ADDRA(PORT_R_ADDR), - .ADDRB(PORT_R_ADDR), - .ADDRC(PORT_R_ADDR), - .ADDRD(PORT_R_ADDR), - .ADDRE(PORT_R_ADDR), - .ADDRF(PORT_R_ADDR), - .ADDRG(PORT_R_ADDR), - .ADDRH(PORT_W_ADDR), - .WE(PORT_W_WR_EN), - .WCLK(PORT_W_CLK), + .WE(PORT_RW_WR_EN) ); default: $error("invalid OPTION_ABITS/WIDTH combination"); diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc index 1c183476d..da7f226e7 100644 --- a/techlibs/analogdevices/synth_analogdevices.cc +++ b/techlibs/analogdevices/synth_analogdevices.cc @@ -416,7 +416,7 @@ struct SynthAnalogDevicesPass : public ScriptPass // Needs to be done before logic optimization, so that inverters (inserted // here because of negative-polarity output enable) are handled. if (help_mode || !noiopad) - run("iopadmap -bits -outpad OUTBUF I:O -inpad INBUF O:I -toutpad OBUFT ~T:I:O -tinoutpad IOBUF ~T:O:I:IO A:top", "(skip if '-noiopad')"); + run("iopadmap -bits -outpad OUTBUF I:O -inpad INBUF O:I A:top", "(skip if '-noiopad')"); std::string techmap_args = "-map +/techmap.v -map +/analogdevices/cells_map.v"; if (widemux > 0) techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux); From 376f746bc9b562bb391ca8978cb1cecee7a297e2 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Wed, 8 Oct 2025 14:08:41 +1300 Subject: [PATCH 260/291] analogdevices: Native LUTRAM primitives --- techlibs/analogdevices/cells_sim.v | 2 ++ techlibs/analogdevices/lutrams.txt | 12 +++++++----- techlibs/analogdevices/lutrams_map.v | 9 ++++----- 3 files changed, 13 insertions(+), 10 deletions(-) diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v index c49a54e79..4f9af79c5 100644 --- a/techlibs/analogdevices/cells_sim.v +++ b/techlibs/analogdevices/cells_sim.v @@ -604,6 +604,8 @@ module RAMS64X1 ( endspecify endmodule +// Dual port. + (* abc9_box, lib_whitebox *) module RAMD32X1 ( output DPO, SPO, diff --git a/techlibs/analogdevices/lutrams.txt b/techlibs/analogdevices/lutrams.txt index fbfd530c3..c342eaede 100644 --- a/techlibs/analogdevices/lutrams.txt +++ b/techlibs/analogdevices/lutrams.txt @@ -1,37 +1,39 @@ # Single-port RAMs. ram distributed $__ANALOGDEVICES_LUTRAM_SP_ { - cost 1; option "ABITS" 5 { + cost 1; abits 5; } option "ABITS" 6 { + cost 2; abits 6; } width 1; init no_undef; prune_rom; port arsw "RW" { - clock posedge; + clock anyedge; } } # Dual-port RAMs. ram distributed $__ANALOGDEVICES_LUTRAM_DP_ { - cost 1; option "ABITS" 5 { + cost 2; abits 5; } option "ABITS" 6 { + cost 4; abits 6; } width 1; init no_undef; prune_rom; - port ar "R" { - } port arsw "RW" { clock posedge; } + port ar "R" { + } } diff --git a/techlibs/analogdevices/lutrams_map.v b/techlibs/analogdevices/lutrams_map.v index cb148f56c..7962e616c 100644 --- a/techlibs/analogdevices/lutrams_map.v +++ b/techlibs/analogdevices/lutrams_map.v @@ -28,7 +28,7 @@ case(OPTION_ABITS) .WCLK(PORT_RW_CLK), .WE(PORT_RW_WR_EN) ); -6: begin +6: RAMS64X1 #( .INIT(INIT) @@ -46,9 +46,8 @@ case(OPTION_ABITS) .WCLK(PORT_RW_CLK), .WE(PORT_RW_WR_EN) ); -end default: - $error("invalid OPTION_ABITS/WIDTH combination"); + $error("invalid OPTION_ABITS"); endcase endgenerate @@ -78,8 +77,8 @@ case (OPTION_ABITS) ) _TECHMAP_REPLACE_ ( - .SPO(PORT_RW_RD_DATA), .DPO(PORT_R_RD_DATA), + .SPO(PORT_RW_RD_DATA), .A0(PORT_RW_ADDR[0]), .A1(PORT_RW_ADDR[1]), .A2(PORT_RW_ADDR[2]), @@ -101,8 +100,8 @@ case (OPTION_ABITS) ) _TECHMAP_REPLACE_ ( - .SPO(PORT_RW_RD_DATA), .DPO(PORT_R_RD_DATA), + .SPO(PORT_RW_RD_DATA), .A0(PORT_RW_ADDR[0]), .A1(PORT_RW_ADDR[1]), .A2(PORT_RW_ADDR[2]), From 9be3cfb3f9ff27220533484397b1a59852662921 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Wed, 8 Oct 2025 14:13:57 +1300 Subject: [PATCH 261/291] analogdevices: Update lutram.ys test --- tests/arch/analogdevices/lutram.ys | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/tests/arch/analogdevices/lutram.ys b/tests/arch/analogdevices/lutram.ys index b7ba3265b..d3a088bdb 100644 --- a/tests/arch/analogdevices/lutram.ys +++ b/tests/arch/analogdevices/lutram.ys @@ -14,8 +14,8 @@ design -load postopt cd lutram_1w1r select -assert-count 1 t:BUFG select -assert-count 8 t:FFRE -select -assert-count 1 t:RAM32M -select -assert-none t:BUFG t:FFRE t:RAM32M %% t:* %D +select -assert-count 8 t:RAMS32X1 +select -assert-none t:BUFG t:FFRE t:RAMS32X1 %% t:* %D design -reset @@ -35,8 +35,8 @@ cd lutram_1w1r dump select -assert-count 1 t:BUFG select -assert-count 8 t:FFRE -select -assert-count 8 t:RAM64X1S -select -assert-none t:BUFG t:FFRE t:RAM64X1S %% t:* %D +select -assert-count 8 t:RAMS64X1 +select -assert-none t:BUFG t:FFRE t:RAMS64X1 %% t:* %D design -reset @@ -55,8 +55,8 @@ design -load postopt cd lutram_1w3r select -assert-count 1 t:BUFG select -assert-count 24 t:FFRE -select -assert-count 4 t:RAM32M -select -assert-none t:BUFG t:FFRE t:RAM32M %% t:* %D +select -assert-count 16 t:RAMD32X1 +select -assert-none t:BUFG t:FFRE t:RAMD32X1 %% t:* %D design -reset @@ -75,8 +75,8 @@ design -load postopt cd lutram_1w3r select -assert-count 1 t:BUFG select -assert-count 24 t:FFRE -select -assert-count 16 t:RAM64X1D -select -assert-none t:BUFG t:FFRE t:RAM64X1D %% t:* %D +select -assert-count 16 t:RAMD64X1 +select -assert-none t:BUFG t:FFRE t:RAMD64X1 %% t:* %D design -reset @@ -95,8 +95,8 @@ design -load postopt cd lutram_1w1r select -assert-count 1 t:BUFG select -assert-count 6 t:FFRE -select -assert-count 1 t:RAM32M -select -assert-none t:BUFG t:FFRE t:RAM32M %% t:* %D +select -assert-count 6 t:RAMS32X1 +select -assert-none t:BUFG t:FFRE t:RAMS32X1 %% t:* %D design -reset @@ -115,5 +115,5 @@ design -load postopt cd lutram_1w1r select -assert-count 1 t:BUFG select -assert-count 6 t:FFRE -select -assert-count 6 t:RAM64X1S -select -assert-none t:BUFG t:FFRE t:RAM64X1S %% t:* %D +select -assert-count 6 t:RAMS64X1 +select -assert-none t:BUFG t:FFRE t:RAMS64X1 %% t:* %D From 99e26d80b047019b0e3bdf508af1820f7aa06946 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Wed, 8 Oct 2025 17:32:46 +1300 Subject: [PATCH 262/291] analogdevices: (some) Native BRAM Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy). Drop the unused defines from the synth pass. Remove comments from the lutram files referencing xilinx. --- techlibs/analogdevices/brams.txt | 192 ++----- techlibs/analogdevices/brams_map.v | 318 ++---------- techlibs/analogdevices/cells_sim.v | 470 ++---------------- techlibs/analogdevices/synth_analogdevices.cc | 4 - 4 files changed, 116 insertions(+), 868 deletions(-) diff --git a/techlibs/analogdevices/brams.txt b/techlibs/analogdevices/brams.txt index 7bcbeb0a8..209f232c7 100644 --- a/techlibs/analogdevices/brams.txt +++ b/techlibs/analogdevices/brams.txt @@ -1,165 +1,39 @@ -# Block RAMs for Virtex 4+. -# The corresponding mapping files are: -# - brams_xc6v_map.v: Virtex 6, Series 7 +# Simple Dual Port +# Supported: +# SDP_4096x05 +# SDP_2048x10 +# SDP_1024x40 +# Ignored: +# SDP_2048x09 -ram block $__ANALOGDEVICES_BLOCKRAM_TDP_ { - byte 9; - ifdef HAS_SIZE_36 { - option "MODE" "HALF" { - abits 14; - widths 1 2 4 9 18 per_port; - cost 129; - } - option "MODE" "FULL" { - abits 15; - widths 1 2 4 9 18 36 per_port; - cost 257; - } - ifdef HAS_CASCADE { - option "MODE" "CASCADE" { - abits 16; - # hack to enforce same INIT layout as in the other modes - widths 1 2 4 9 per_port; - cost 513; - } - } - } else { - option "MODE" "FULL" { - abits 14; - widths 1 2 4 9 18 36 per_port; - cost 129; - } - ifdef HAS_CASCADE { - option "MODE" "CASCADE" { - abits 15; - widths 1 2 4 9 per_port; - cost 257; - } - } +ram block $__ANALOGDEVICES_BLOCKRAM_SDP_ { + option "ENABLE_WIDTH" "BIT" { + abits 12; + widths 5 10 global; + byte 1; + cost 1; } - init any; - port srsw "A" "B" { - option "MODE" "HALF" { - width mix; - } - option "MODE" "FULL" { - width mix; - } - option "MODE" "CASCADE" { - width mix 1; - } - ifdef HAS_ADDRCE { - # TODO - # addrce; - } - # Spartan 6 and Virtex 6 have a bug where READ_FIRST is not usable with asynchronous clocks. - ifdef HAS_CONFLICT_BUG { - option "HAS_RDFIRST" 1 { - clock posedge "C"; - } - option "HAS_RDFIRST" 0 { - clock posedge; - } - } else { - clock posedge; - } + option "ENABLE_WIDTH" "BYTE" { + abits 10; + width 40; + byte 8; + cost 4; + } + # Unclear if/how RBRAM is initialized, default SIM_INIT_BEHAVIOUR is UNINITIALIZED + init none; + port sr "R" { + clock anyedge; + clken; + } + port sw "W" { + clock anyedge; clken; - rdsrst any gated_clken; - rdinit any; - portoption "WRITE_MODE" "NO_CHANGE" { - rdwr no_change; - option "MODE" "CASCADE" { - forbid; - } - } - portoption "WRITE_MODE" "WRITE_FIRST" { - ifdef HAS_SIZE_36 { - rdwr new; - } else { - rdwr new_only; - } - } - ifdef HAS_CONFLICT_BUG { - option "HAS_RDFIRST" 1 { - portoption "WRITE_MODE" "READ_FIRST" { - rdwr old; - wrtrans all old; - } - } - } else { - portoption "WRITE_MODE" "READ_FIRST" { - rdwr old; - wrtrans all old; - } - } - optional_rw; } } -ifdef HAS_SIZE_36 { - ram block $__ANALOGDEVICES_BLOCKRAM_SDP_ { - byte 9; - option "MODE" "HALF" { - abits 14; - widths 1 2 4 9 18 36 per_port; - cost 129; - } - option "MODE" "FULL" { - abits 15; - widths 1 2 4 9 18 36 72 per_port; - cost 257; - } - init any; - port sw "W" { - ifndef HAS_MIXWIDTH_SDP { - option "MODE" "HALF" width 36; - option "MODE" "FULL" width 72; - } - ifdef HAS_ADDRCE { - # TODO - # addrce; - } - # Spartan 6 and Virtex 6 have a bug where READ_FIRST is not usable with asynchronous clocks. - ifdef HAS_CONFLICT_BUG { - option "WRITE_MODE" "READ_FIRST" { - clock posedge "C"; - } - option "WRITE_MODE" "WRITE_FIRST" { - clock posedge; - } - } else { - clock posedge; - } - clken; - option "WRITE_MODE" "READ_FIRST" { - wrtrans all old; - } - optional; - } - port sr "R" { - ifndef HAS_MIXWIDTH_SDP { - option "MODE" "HALF" width 36; - option "MODE" "FULL" width 72; - } - ifdef HAS_ADDRCE { - # TODO - # addrce; - } - # Spartan 6 and Virtex 6 have a bug where READ_FIRST is not usable with asynchronous clocks. - ifdef HAS_CONFLICT_BUG { - option "WRITE_MODE" "READ_FIRST" { - clock posedge "C"; - } - option "WRITE_MODE" "WRITE_FIRST" { - clock posedge; - } - } else { - clock posedge; - } - clken; - rdsrst any gated_clken; - rdinit any; - optional; - } - } -} +# Single Port +# SP_1024x20 + +# Dual Single Port +# SP2_1024x09 +# SP2_2048x05 diff --git a/techlibs/analogdevices/brams_map.v b/techlibs/analogdevices/brams_map.v index f4655a220..6d590501e 100644 --- a/techlibs/analogdevices/brams_map.v +++ b/techlibs/analogdevices/brams_map.v @@ -1,284 +1,64 @@ -module $__ANALOGDEVICES_BLOCKRAM_TDP_ (...); - -parameter INIT = 0; -parameter OPTION_MODE = "FULL"; -parameter OPTION_HAS_RDFIRST = 0; - -parameter PORT_A_RD_WIDTH = 1; -parameter PORT_A_WR_WIDTH = 1; -parameter PORT_A_WR_EN_WIDTH = 1; -parameter PORT_A_RD_USED = 1; -parameter PORT_A_WR_USED = 1; -parameter PORT_A_OPTION_WRITE_MODE = "NO_CHANGE"; -parameter PORT_A_RD_INIT_VALUE = 0; -parameter PORT_A_RD_SRST_VALUE = 1; - -parameter PORT_B_RD_WIDTH = 1; -parameter PORT_B_WR_WIDTH = 1; -parameter PORT_B_WR_EN_WIDTH = 1; -parameter PORT_B_RD_USED = 0; -parameter PORT_B_WR_USED = 0; -parameter PORT_B_OPTION_WRITE_MODE = "NO_CHANGE"; -parameter PORT_B_RD_INIT_VALUE = 0; -parameter PORT_B_RD_SRST_VALUE = 0; - -input CLK_C; - -input PORT_A_CLK; -input PORT_A_CLK_EN; -input [15:0] PORT_A_ADDR; -input [PORT_A_WR_WIDTH-1:0] PORT_A_WR_DATA; -input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN; -output [PORT_A_RD_WIDTH-1:0] PORT_A_RD_DATA; -input PORT_A_RD_SRST; - -input PORT_B_CLK; -input PORT_B_CLK_EN; -input [15:0] PORT_B_ADDR; -input [PORT_B_WR_WIDTH-1:0] PORT_B_WR_DATA; -input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN; -output [PORT_B_RD_WIDTH-1:0] PORT_B_RD_DATA; -input PORT_B_RD_SRST; - -`include "brams_defs.vh" - -`define PARAMS_COMMON \ - .WRITE_MODE_A(PORT_A_OPTION_WRITE_MODE), \ - .WRITE_MODE_B(PORT_B_OPTION_WRITE_MODE), \ - .READ_WIDTH_A(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0), \ - .READ_WIDTH_B(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0), \ - .WRITE_WIDTH_A(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0), \ - .WRITE_WIDTH_B(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0), \ - .DOA_REG(0), \ - .DOB_REG(0), \ - .INIT_A(ival(PORT_A_RD_WIDTH, PORT_A_RD_INIT_VALUE)), \ - .INIT_B(ival(PORT_B_RD_WIDTH, PORT_B_RD_INIT_VALUE)), \ - .SRVAL_A(ival(PORT_A_RD_WIDTH, PORT_A_RD_SRST_VALUE)), \ - .SRVAL_B(ival(PORT_B_RD_WIDTH, PORT_B_RD_SRST_VALUE)), \ - .RAM_MODE("TDP"), - -`define PORTS_COMMON \ - .DOADO(DO_A), \ - .DOPADOP(DOP_A), \ - .DIADI(DI_A), \ - .DIPADIP(DIP_A), \ - .DOBDO(DO_B), \ - .DOPBDOP(DOP_B), \ - .DIBDI(DI_B), \ - .DIPBDIP(DIP_B), \ - .CLKARDCLK(PORT_A_CLK), \ - .CLKBWRCLK(PORT_B_CLK), \ - .ENARDEN(PORT_A_CLK_EN), \ - .ENBWREN(PORT_B_CLK_EN), \ - .REGCEAREGCE(1'b0), \ - .REGCEB(1'b0), \ - .RSTRAMARSTRAM(PORT_A_RD_SRST), \ - .RSTRAMB(PORT_B_RD_SRST), \ - .RSTREGARSTREG(1'b0), \ - .RSTREGB(1'b0), \ - .WEA(WE_A), \ - .WEBWE(WE_B), - -`MAKE_DI(DI_A, DIP_A, PORT_A_WR_DATA) -`MAKE_DI(DI_B, DIP_B, PORT_B_WR_DATA) -`MAKE_DO(DO_A, DOP_A, PORT_A_RD_DATA) -`MAKE_DO(DO_B, DOP_B, PORT_B_RD_DATA) - -wire [3:0] WE_A = {4{PORT_A_WR_EN}}; -wire [3:0] WE_B = {4{PORT_B_WR_EN}}; - -generate - -if (OPTION_MODE == "HALF") begin - RAMB18E1 #( - `PARAMS_INIT_18 - `PARAMS_INITP_18 - `PARAMS_COMMON - ) _TECHMAP_REPLACE_ ( - `PORTS_COMMON - .ADDRARDADDR(PORT_A_ADDR[13:0]), - .ADDRBWRADDR(PORT_B_ADDR[13:0]), - ); -end else if (OPTION_MODE == "FULL") begin - RAMB36E1 #( - `PARAMS_INIT_36 - `PARAMS_INITP_36 - `PARAMS_COMMON - .RAM_EXTENSION_A("NONE"), - .RAM_EXTENSION_B("NONE"), - ) _TECHMAP_REPLACE_ ( - `PORTS_COMMON - .ADDRARDADDR({1'b1, PORT_A_ADDR[14:0]}), - .ADDRBWRADDR({1'b1, PORT_B_ADDR[14:0]}), - ); -end else begin - wire CAS_A, CAS_B; - RAMB36E1 #( - `PARAMS_INIT_36 - `PARAMS_COMMON - .RAM_EXTENSION_A("LOWER"), - .RAM_EXTENSION_B("LOWER"), - ) lower ( - .DIADI(DI_A), - .DIBDI(DI_B), - .CLKARDCLK(PORT_A_CLK), - .CLKBWRCLK(PORT_B_CLK), - .ENARDEN(PORT_A_CLK_EN), - .ENBWREN(PORT_B_CLK_EN), - .REGCEAREGCE(1'b0), - .REGCEB(1'b0), - .RSTRAMARSTRAM(PORT_A_RD_SRST), - .RSTRAMB(PORT_B_RD_SRST), - .RSTREGARSTREG(1'b0), - .RSTREGB(1'b0), - .WEA(WE_A), - .WEBWE(WE_B), - .ADDRARDADDR(PORT_A_ADDR), - .ADDRBWRADDR(PORT_B_ADDR), - .CASCADEOUTA(CAS_A), - .CASCADEOUTB(CAS_B), - ); - RAMB36E1 #( - `PARAMS_INIT_36_U - `PARAMS_COMMON - .RAM_EXTENSION_A("UPPER"), - .RAM_EXTENSION_B("UPPER"), - ) upper ( - .DOADO(DO_A), - .DIADI(DI_A), - .DOBDO(DO_B), - .DIBDI(DI_B), - .CLKARDCLK(PORT_A_CLK), - .CLKBWRCLK(PORT_B_CLK), - .ENARDEN(PORT_A_CLK_EN), - .ENBWREN(PORT_B_CLK_EN), - .REGCEAREGCE(1'b0), - .REGCEB(1'b0), - .RSTRAMARSTRAM(PORT_A_RD_SRST), - .RSTRAMB(PORT_B_RD_SRST), - .RSTREGARSTREG(1'b0), - .RSTREGB(1'b0), - .WEA(WE_A), - .WEBWE(WE_B), - .ADDRARDADDR(PORT_A_ADDR), - .ADDRBWRADDR(PORT_B_ADDR), - .CASCADEINA(CAS_A), - .CASCADEINB(CAS_B), - ); -end - -endgenerate - -endmodule - - module $__ANALOGDEVICES_BLOCKRAM_SDP_ (...); parameter INIT = 0; -parameter OPTION_MODE = "FULL"; -parameter OPTION_WRITE_MODE = "READ_FIRST"; +parameter OPTION_ENABLE_WIDTH = "BIT"; +parameter WIDTH = 40; -parameter PORT_W_WIDTH = 1; -parameter PORT_W_WR_EN_WIDTH = 1; -parameter PORT_W_USED = 1; +parameter PORT_W_WR_EN_WIDTH = 5; +parameter PORT_W_CLK_POL = 1; -parameter PORT_R_WIDTH = 1; -parameter PORT_R_USED = 0; -parameter PORT_R_RD_INIT_VALUE = 0; -parameter PORT_R_RD_SRST_VALUE = 0; - -input CLK_C; +parameter PORT_R_CLK_POL = 1; input PORT_W_CLK; input PORT_W_CLK_EN; -input [15:0] PORT_W_ADDR; -input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA; +input [11:0] PORT_W_ADDR; +input [WIDTH-1:0] PORT_W_WR_DATA; input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN; input PORT_R_CLK; input PORT_R_CLK_EN; -input [15:0] PORT_R_ADDR; -output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA; -input PORT_R_RD_SRST; +input [11:0] PORT_R_ADDR; +output [WIDTH-1:0] PORT_R_RD_DATA; -`include "brams_defs.vh" - -`define PARAMS_COMMON \ - .WRITE_MODE_A(OPTION_WRITE_MODE), \ - .WRITE_MODE_B(OPTION_WRITE_MODE), \ - .READ_WIDTH_A(PORT_R_USED ? PORT_R_WIDTH : 0), \ - .READ_WIDTH_B(0), \ - .WRITE_WIDTH_A(0), \ - .WRITE_WIDTH_B(PORT_W_USED ? PORT_W_WIDTH : 0), \ - .DOA_REG(0), \ - .DOB_REG(0), \ - .RAM_MODE("SDP"), - -`define PORTS_COMMON \ - .CLKBWRCLK(PORT_W_CLK), \ - .CLKARDCLK(PORT_R_CLK), \ - .ENBWREN(PORT_W_CLK_EN), \ - .ENARDEN(PORT_R_CLK_EN), \ - .REGCEAREGCE(1'b0), \ - .REGCEB(1'b0), \ - .RSTRAMARSTRAM(PORT_R_RD_SRST), \ - .RSTRAMB(1'b0), \ - .RSTREGARSTREG(1'b0), \ - .RSTREGB(1'b0), \ - .WEA(0), \ - .WEBWE(PORT_W_WR_EN), - -`MAKE_DI(DI, DIP, PORT_W_WR_DATA) -`MAKE_DO(DO, DOP, PORT_R_RD_DATA) - -generate - -if (OPTION_MODE == "HALF") begin - RAMB18E1 #( - `PARAMS_INIT_18 - `PARAMS_INITP_18 - `PARAMS_COMMON - .INIT_A(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_INIT_VALUE[17:0]) : ival(PORT_R_WIDTH, PORT_R_RD_INIT_VALUE)), - .INIT_B(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_INIT_VALUE[35:18]) : 0), - .SRVAL_A(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_SRST_VALUE[17:0]) : ival(PORT_R_WIDTH, PORT_R_RD_SRST_VALUE)), - .SRVAL_B(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_SRST_VALUE[35:18]) : 0), - ) _TECHMAP_REPLACE_ ( - `PORTS_COMMON - .ADDRARDADDR(PORT_R_ADDR[13:0]), - .ADDRBWRADDR(PORT_W_ADDR[13:0]), - .DOADO(DO[15:0]), - .DOBDO(DO[31:16]), - .DOPADOP(DOP[1:0]), - .DOPBDOP(DOP[3:2]), - .DIADI(DI[15:0]), - .DIBDI(PORT_W_WIDTH == 36 ? DI[31:16] : DI[15:0]), - .DIPADIP(DIP[1:0]), - .DIPBDIP(PORT_W_WIDTH == 36 ? DIP[3:2] : DIP[1:0]), - ); -end else if (OPTION_MODE == "FULL") begin - RAMB36E1 #( - `PARAMS_INIT_36 - `PARAMS_INITP_36 - `PARAMS_COMMON - .INIT_A(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_INIT_VALUE[35:0]) : ival(PORT_R_WIDTH, PORT_R_RD_INIT_VALUE)), - .INIT_B(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_INIT_VALUE[71:36]) : 0), - .SRVAL_A(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_SRST_VALUE[35:0]) : ival(PORT_R_WIDTH, PORT_R_RD_SRST_VALUE)), - .SRVAL_B(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_SRST_VALUE[71:36]) : 0), - ) _TECHMAP_REPLACE_ ( - `PORTS_COMMON - .ADDRARDADDR({1'b1, PORT_R_ADDR}), - .ADDRBWRADDR({1'b1, PORT_W_ADDR}), - .DOADO(DO[31:0]), - .DOBDO(DO[63:32]), - .DOPADOP(DOP[3:0]), - .DOPBDOP(DOP[7:4]), - .DIADI(DI[31:0]), - .DIBDI(PORT_W_WIDTH == 72 ? DI[63:32] : DI[31:0]), - .DIPADIP(DIP[3:0]), - .DIPBDIP(PORT_W_WIDTH == 71 ? DIP[7:4] : DIP[3:0]), - ); -end - -endgenerate +RBRAM +#( + .TARGET_NODE("T40LP_Gen2.4"), + .BRAM_MODE( + WIDTH == 5 ? "SDP_4096x05" : + WIDTH == 10 ? "SDP_2048x10" : "SDP_1024x40" + ), + .QA_REG(0), + .QB_REG(0), + .CLKA_INV(!PORT_W_CLK_POL), + .CLKB_INV(!PORT_R_CLK_POL), + .DATA_WIDTH(WIDTH), + .ADDR_WIDTH( + WIDTH == 5 ? 12 : + WIDTH == 10 ? 11 : 10 + ), + .WE_WIDTH(OPTION_ENABLE_WIDTH == "BIT" ? WIDTH : PORT_W_WR_EN_WIDTH), + .PERR_WIDTH(1), +) +_TECHMAP_REPLACE_ +( + // .QA(0), + .DA(PORT_W_WR_DATA), + .CEA(PORT_W_CLK_EN), + .WEA(PORT_W_WR_EN), + .AA( + WIDTH == 5 ? PORT_W_ADDR : + WIDTH == 10 ? PORT_W_ADDR[11:1] : PORT_W_ADDR[11:2] + ), + .CLKA(PORT_W_CLK), + .QB(PORT_R_RD_DATA), + // .DB(0), + .CEB(PORT_R_CLK_EN), + // .WEB(0), + .AB( + WIDTH == 5 ? PORT_R_ADDR : + WIDTH == 10 ? PORT_R_ADDR[11:1] : PORT_R_ADDR[11:2] + ), + .CLKB(PORT_R_CLK), +); endmodule diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v index 4f9af79c5..69791cf03 100644 --- a/techlibs/analogdevices/cells_sim.v +++ b/techlibs/analogdevices/cells_sim.v @@ -1488,444 +1488,42 @@ endmodule // Block RAM -module RAMB18E1 ( +module RBRAM #( + parameter TARGET_NODE = "T40LP_Gen2.4", + parameter BRAM_MODE = "SDP_1024x40", + parameter QA_REG = 0, + parameter QB_REG = 0, + parameter CLKA_INV = 0, + parameter CLKB_INV = 0, + parameter DATA_WIDTH = 40, + parameter ADDR_WIDTH = 12, + parameter WE_WIDTH = 10, + parameter PERR_WIDTH = 4, +) ( + output [DATA_WIDTH-1:0] QA, + input [DATA_WIDTH-1:0] DA, + input CEA, + input [WE_WIDTH-1:0] WEA, + input [ADDR_WIDTH-1:0] AA, (* clkbuf_sink *) - (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) - input CLKARDCLK, + (* invertible_pin = "CLKA_INV" *) + input CLKA, + output [DATA_WIDTH-1:0] QB, + input [DATA_WIDTH-1:0] DB, + input CEB, + input [WE_WIDTH-1:0] WEB, + input [ADDR_WIDTH-1:0] AB, (* clkbuf_sink *) - (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) - input CLKBWRCLK, - (* invertible_pin = "IS_ENARDEN_INVERTED" *) - input ENARDEN, - (* invertible_pin = "IS_ENBWREN_INVERTED" *) - input ENBWREN, - input REGCEAREGCE, - input REGCEB, - (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) - input RSTRAMARSTRAM, - (* invertible_pin = "IS_RSTRAMB_INVERTED" *) - input RSTRAMB, - (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) - input RSTREGARSTREG, - (* invertible_pin = "IS_RSTREGB_INVERTED" *) - input RSTREGB, - input [13:0] ADDRARDADDR, - input [13:0] ADDRBWRADDR, - input [15:0] DIADI, - input [15:0] DIBDI, - input [1:0] DIPADIP, - input [1:0] DIPBDIP, - input [1:0] WEA, - input [3:0] WEBWE, - output [15:0] DOADO, - output [15:0] DOBDO, - output [1:0] DOPADOP, - output [1:0] DOPBDOP + (* invertible_pin = "CLKB_INV" *) + input CLKB, + output reg [PERR_WIDTH-1:0] PERRA, + output reg [PERR_WIDTH-1:0] PERRB, + output SBEA, + output SBEB, + output MBEA, + output MBEB, + input SLP, + input PD, ); - parameter integer DOA_REG = 0; - parameter integer DOB_REG = 0; - parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_A = 18'h0; - parameter INIT_B = 18'h0; - parameter INIT_FILE = "NONE"; - parameter RAM_MODE = "TDP"; - parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE"; - parameter integer READ_WIDTH_A = 0; - parameter integer READ_WIDTH_B = 0; - parameter RSTREG_PRIORITY_A = "RSTREG"; - parameter RSTREG_PRIORITY_B = "RSTREG"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter SIM_DEVICE = "VIRTEX6"; - parameter SRVAL_A = 18'h0; - parameter SRVAL_B = 18'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter integer WRITE_WIDTH_A = 0; - parameter integer WRITE_WIDTH_B = 0; - parameter IS_CLKARDCLK_INVERTED = 1'b0; - parameter IS_CLKBWRCLK_INVERTED = 1'b0; - parameter IS_ENARDEN_INVERTED = 1'b0; - parameter IS_ENBWREN_INVERTED = 1'b0; - parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0; - parameter IS_RSTRAMB_INVERTED = 1'b0; - parameter IS_RSTREGARSTREG_INVERTED = 1'b0; - parameter IS_RSTREGB_INVERTED = 1'b0; - specify - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L13 - $setup(ADDRARDADDR, posedge CLKARDCLK, 566); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L17 - $setup(ADDRBWRADDR, posedge CLKBWRCLK, 566); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L19 - $setup(WEA, posedge CLKARDCLK, 532); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L21 - $setup(WEBWE, posedge CLKBWRCLK, 532); - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L29 - $setup(REGCEAREGCE, posedge CLKARDCLK, 360); - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L31 - $setup(RSTREGARSTREG, posedge CLKARDCLK, 342); - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L49 - $setup(REGCEB, posedge CLKBWRCLK, 360); - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L59 - $setup(RSTREGB, posedge CLKBWRCLK, 342); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L123 - $setup(DIADI, posedge CLKARDCLK, 737); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L133 - $setup(DIBDI, posedge CLKBWRCLK, 737); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L125 - $setup(DIPADIP, posedge CLKARDCLK, 737); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L135 - $setup(DIPBDIP, posedge CLKBWRCLK, 737); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L143 - if (&DOA_REG) (posedge CLKARDCLK => (DOADO : 16'bx)) = 2454; - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L144 - if (&DOA_REG) (posedge CLKARDCLK => (DOPADOP : 2'bx)) = 2454; - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L153 - if (|DOA_REG) (posedge CLKARDCLK => (DOADO : 16'bx)) = 882; - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L154 - if (|DOA_REG) (posedge CLKARDCLK => (DOPADOP : 2'bx)) = 882; - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L163 - if (&DOB_REG) (posedge CLKBWRCLK => (DOBDO : 16'bx)) = 2454; - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L164 - if (&DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 2'bx)) = 2454; - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L173 - if (|DOB_REG) (posedge CLKBWRCLK => (DOBDO : 16'bx)) = 882; - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L174 - if (|DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 2'bx)) = 882; - endspecify -endmodule - -module RAMB36E1 ( - output CASCADEOUTA, - output CASCADEOUTB, - output [31:0] DOADO, - output [31:0] DOBDO, - output [3:0] DOPADOP, - output [3:0] DOPBDOP, - output [7:0] ECCPARITY, - output [8:0] RDADDRECC, - output SBITERR, - output DBITERR, - (* invertible_pin = "IS_ENARDEN_INVERTED" *) - input ENARDEN, - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) - input CLKARDCLK, - (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) - input RSTRAMARSTRAM, - (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) - input RSTREGARSTREG, - input CASCADEINA, - input REGCEAREGCE, - (* invertible_pin = "IS_ENBWREN_INVERTED" *) - input ENBWREN, - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) - input CLKBWRCLK, - (* invertible_pin = "IS_RSTRAMB_INVERTED" *) - input RSTRAMB, - (* invertible_pin = "IS_RSTREGB_INVERTED" *) - input RSTREGB, - input CASCADEINB, - input REGCEB, - input INJECTDBITERR, - input INJECTSBITERR, - input [15:0] ADDRARDADDR, - input [15:0] ADDRBWRADDR, - input [31:0] DIADI, - input [31:0] DIBDI, - input [3:0] DIPADIP, - input [3:0] DIPBDIP, - input [3:0] WEA, - input [7:0] WEBWE -); - parameter integer DOA_REG = 0; - parameter integer DOB_REG = 0; - parameter EN_ECC_READ = "FALSE"; - parameter EN_ECC_WRITE = "FALSE"; - parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_A = 36'h0; - parameter INIT_B = 36'h0; - parameter INIT_FILE = "NONE"; - parameter RAM_EXTENSION_A = "NONE"; - parameter RAM_EXTENSION_B = "NONE"; - parameter RAM_MODE = "TDP"; - parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE"; - parameter integer READ_WIDTH_A = 0; - parameter integer READ_WIDTH_B = 0; - parameter RSTREG_PRIORITY_A = "RSTREG"; - parameter RSTREG_PRIORITY_B = "RSTREG"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter SIM_DEVICE = "VIRTEX6"; - parameter SRVAL_A = 36'h0; - parameter SRVAL_B = 36'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter integer WRITE_WIDTH_A = 0; - parameter integer WRITE_WIDTH_B = 0; - parameter IS_CLKARDCLK_INVERTED = 1'b0; - parameter IS_CLKBWRCLK_INVERTED = 1'b0; - parameter IS_ENARDEN_INVERTED = 1'b0; - parameter IS_ENBWREN_INVERTED = 1'b0; - parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0; - parameter IS_RSTRAMB_INVERTED = 1'b0; - parameter IS_RSTREGARSTREG_INVERTED = 1'b0; - parameter IS_RSTREGB_INVERTED = 1'b0; - - specify - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L13 - $setup(ADDRARDADDR, posedge CLKARDCLK, 566); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L17 - $setup(ADDRBWRADDR, posedge CLKBWRCLK, 566); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L19 - $setup(WEA, posedge CLKARDCLK, 532); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L21 - $setup(WEBWE, posedge CLKBWRCLK, 532); - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L29 - $setup(REGCEAREGCE, posedge CLKARDCLK, 360); - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L31 - $setup(RSTREGARSTREG, posedge CLKARDCLK, 342); - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L49 - $setup(REGCEB, posedge CLKBWRCLK, 360); - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L59 - $setup(RSTREGB, posedge CLKBWRCLK, 342); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L123 - $setup(DIADI, posedge CLKARDCLK, 737); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L133 - $setup(DIBDI, posedge CLKBWRCLK, 737); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L125 - $setup(DIPADIP, posedge CLKARDCLK, 737); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L135 - $setup(DIPBDIP, posedge CLKBWRCLK, 737); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L143 - if (&DOA_REG) (posedge CLKARDCLK => (DOADO : 32'bx)) = 2454; - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L144 - if (&DOA_REG) (posedge CLKARDCLK => (DOPADOP : 4'bx)) = 2454; - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L153 - if (|DOA_REG) (posedge CLKARDCLK => (DOADO : 32'bx)) = 882; - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L154 - if (|DOA_REG) (posedge CLKARDCLK => (DOPADOP : 4'bx)) = 882; - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L163 - if (&DOB_REG) (posedge CLKBWRCLK => (DOBDO : 32'bx)) = 2454; - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L164 - if (&DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 4'bx)) = 2454; - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L173 - if (|DOB_REG) (posedge CLKBWRCLK => (DOBDO : 32'bx)) = 882; - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L174 - if (|DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 4'bx)) = 882; - endspecify endmodule diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc index da7f226e7..09406fbf1 100644 --- a/techlibs/analogdevices/synth_analogdevices.cc +++ b/techlibs/analogdevices/synth_analogdevices.cc @@ -343,10 +343,6 @@ struct SynthAnalogDevicesPass : public ScriptPass params += " -lib +/analogdevices/lutrams.txt"; lutrams_map = "+/analogdevices/lutrams_map.v"; params += " -lib +/analogdevices/brams.txt"; - params += " -D HAS_SIZE_36"; - params += " -D HAS_CASCADE"; - params += " -D HAS_CONFLICT_BUG"; - params += " -D HAS_MIXWIDTH_SDP"; brams_map = "+/analogdevices/brams_map.v"; if (nolutram) params += " -no-auto-distributed"; From 9dcffc3dbf6eec0495897afa22b445a6c3665db4 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Sat, 11 Oct 2025 12:06:35 +1300 Subject: [PATCH 263/291] analogdevices: Adding RBRAM2 and -tech --- techlibs/analogdevices/brams.txt | 39 ++++++++++++----- techlibs/analogdevices/brams_map.v | 36 +++++++++++----- techlibs/analogdevices/cells_sim.v | 42 ++++++++++++++++++- techlibs/analogdevices/synth_analogdevices.cc | 28 +++++++++++-- 4 files changed, 119 insertions(+), 26 deletions(-) diff --git a/techlibs/analogdevices/brams.txt b/techlibs/analogdevices/brams.txt index 209f232c7..9a5111490 100644 --- a/techlibs/analogdevices/brams.txt +++ b/techlibs/analogdevices/brams.txt @@ -1,20 +1,38 @@ +# family: T16FFC T40LP +# BRAM: RBRAM2 RBRAM +# Supported: SDP_8192x05 SDP_4096x05 +# SDP_4096x10 SDP_2048x10 +# SDP_2048x40 SDP_1024x40 +# Ignored: SDP_4096x09 SDP_2048x09 +# Unimplemented: SP_2048x20 SP_1024x20 +# TDP_4096x09 +# TDP_8192x05 +# TDP_2048x40 +# SP2_2048x09 SP2_1024x09 +# SP2_4096x05 SP2_2048x05 + + # Simple Dual Port -# Supported: -# SDP_4096x05 -# SDP_2048x10 -# SDP_1024x40 -# Ignored: -# SDP_2048x09 ram block $__ANALOGDEVICES_BLOCKRAM_SDP_ { option "ENABLE_WIDTH" "BIT" { - abits 12; + ifdef IS_T40LP { + abits 12; + } + ifdef IS_T16FFC { + abits 13; + } widths 5 10 global; byte 1; cost 1; } option "ENABLE_WIDTH" "BYTE" { - abits 10; + ifdef IS_T40LP { + abits 10; + } + ifdef IS_T16FFC { + abits 11; + } width 40; byte 8; cost 4; @@ -32,8 +50,7 @@ ram block $__ANALOGDEVICES_BLOCKRAM_SDP_ { } # Single Port -# SP_1024x20 + +# True Dual Port # Dual Single Port -# SP2_1024x09 -# SP2_2048x05 diff --git a/techlibs/analogdevices/brams_map.v b/techlibs/analogdevices/brams_map.v index 6d590501e..b2ba6b77d 100644 --- a/techlibs/analogdevices/brams_map.v +++ b/techlibs/analogdevices/brams_map.v @@ -4,6 +4,18 @@ parameter INIT = 0; parameter OPTION_ENABLE_WIDTH = "BIT"; parameter WIDTH = 40; +`ifdef IS_T40LP +parameter ABITS = 12; +localparam NODE = "T40LP_Gen2.4"; +localparam BRAM_MODE = WIDTH == 5 ? "SDP_4096x05" : + WIDTH == 10 ? "SDP_2048x10" : "SDP_1024x40"; +`elsif IS_T16FFC +parameter ABITS = 13; +localparam NODE = "T16FFC_Gen2.4"; +localparam BRAM_MODE = WIDTH == 5 ? "SDP_8192x05" : + WIDTH == 10 ? "SDP_4096x10" : "SDP_2048x40"; +`endif + parameter PORT_W_WR_EN_WIDTH = 5; parameter PORT_W_CLK_POL = 1; @@ -11,30 +23,32 @@ parameter PORT_R_CLK_POL = 1; input PORT_W_CLK; input PORT_W_CLK_EN; -input [11:0] PORT_W_ADDR; +input [ABITS-1:0] PORT_W_ADDR; input [WIDTH-1:0] PORT_W_WR_DATA; input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN; input PORT_R_CLK; input PORT_R_CLK_EN; -input [11:0] PORT_R_ADDR; +input [ABITS-1:0] PORT_R_ADDR; output [WIDTH-1:0] PORT_R_RD_DATA; +`ifdef IS_T40LP RBRAM +`endif +`ifdef IS_T16FFC +RBRAM2 +`endif #( - .TARGET_NODE("T40LP_Gen2.4"), - .BRAM_MODE( - WIDTH == 5 ? "SDP_4096x05" : - WIDTH == 10 ? "SDP_2048x10" : "SDP_1024x40" - ), + .TARGET_NODE(NODE), + .BRAM_MODE(BRAM_MODE), .QA_REG(0), .QB_REG(0), .CLKA_INV(!PORT_W_CLK_POL), .CLKB_INV(!PORT_R_CLK_POL), .DATA_WIDTH(WIDTH), .ADDR_WIDTH( - WIDTH == 5 ? 12 : - WIDTH == 10 ? 11 : 10 + WIDTH == 5 ? ABITS : + WIDTH == 10 ? ABITS-1 : ABITS-2 ), .WE_WIDTH(OPTION_ENABLE_WIDTH == "BIT" ? WIDTH : PORT_W_WR_EN_WIDTH), .PERR_WIDTH(1), @@ -47,7 +61,7 @@ _TECHMAP_REPLACE_ .WEA(PORT_W_WR_EN), .AA( WIDTH == 5 ? PORT_W_ADDR : - WIDTH == 10 ? PORT_W_ADDR[11:1] : PORT_W_ADDR[11:2] + WIDTH == 10 ? PORT_W_ADDR[ABITS-1:1] : PORT_W_ADDR[ABITS-1:2] ), .CLKA(PORT_W_CLK), .QB(PORT_R_RD_DATA), @@ -56,7 +70,7 @@ _TECHMAP_REPLACE_ // .WEB(0), .AB( WIDTH == 5 ? PORT_R_ADDR : - WIDTH == 10 ? PORT_R_ADDR[11:1] : PORT_R_ADDR[11:2] + WIDTH == 10 ? PORT_R_ADDR[ABITS-1:1] : PORT_R_ADDR[ABITS-1:2] ), .CLKB(PORT_R_CLK), ); diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v index 69791cf03..0a2fadc7d 100644 --- a/techlibs/analogdevices/cells_sim.v +++ b/techlibs/analogdevices/cells_sim.v @@ -1497,7 +1497,47 @@ module RBRAM #( parameter CLKB_INV = 0, parameter DATA_WIDTH = 40, parameter ADDR_WIDTH = 12, - parameter WE_WIDTH = 10, + parameter WE_WIDTH = 20, + parameter PERR_WIDTH = 4, +) ( + output [DATA_WIDTH-1:0] QA, + input [DATA_WIDTH-1:0] DA, + input CEA, + input [WE_WIDTH-1:0] WEA, + input [ADDR_WIDTH-1:0] AA, + (* clkbuf_sink *) + (* invertible_pin = "CLKA_INV" *) + input CLKA, + output [DATA_WIDTH-1:0] QB, + input [DATA_WIDTH-1:0] DB, + input CEB, + input [WE_WIDTH-1:0] WEB, + input [ADDR_WIDTH-1:0] AB, + (* clkbuf_sink *) + (* invertible_pin = "CLKB_INV" *) + input CLKB, + output reg [PERR_WIDTH-1:0] PERRA, + output reg [PERR_WIDTH-1:0] PERRB, + output SBEA, + output SBEB, + output MBEA, + output MBEB, + input SLP, + input PD, +); + +endmodule + +module RBRAM2 #( + parameter TARGET_NODE = "T16FFC_Gen2.4", + parameter BRAM_MODE = "SDP_2048x40", + parameter QA_REG = 0, + parameter QB_REG = 0, + parameter CLKA_INV = 0, + parameter CLKB_INV = 0, + parameter DATA_WIDTH = 40, + parameter ADDR_WIDTH = 13, + parameter WE_WIDTH = 20, parameter PERR_WIDTH = 4, ) ( output [DATA_WIDTH-1:0] QA, diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc index 09406fbf1..6a1d471b6 100644 --- a/techlibs/analogdevices/synth_analogdevices.cc +++ b/techlibs/analogdevices/synth_analogdevices.cc @@ -48,6 +48,13 @@ struct SynthAnalogDevicesPass : public ScriptPass log(" -top \n"); log(" use the specified module as top module\n"); log("\n"); + log(" -tech \n"); + log(" run synthesis for the specified ADI technology process\n"); + log(" currently only affects the type of BRAM used.\n"); + log(" supported values:\n"); + log(" - t40lp (RBRAM)\n"); + log(" - t16ffc (RBRAM2, default)\n"); + log("\n"); log(" -edif \n"); log(" write the design to the specified edif file. writing of an output file\n"); log(" is omitted if this parameter is not specified.\n"); @@ -107,7 +114,7 @@ struct SynthAnalogDevicesPass : public ScriptPass log("\n"); } - std::string top_opt, edif_file, json_file; + std::string top_opt, edif_file, json_file, tech; bool flatten, retime, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp; bool abc9, dff; bool flatten_before_abc; @@ -118,6 +125,7 @@ struct SynthAnalogDevicesPass : public ScriptPass { top_opt = "-auto-top"; edif_file.clear(); + tech = "t16ffc"; flatten = true; retime = false; noiopad = false; @@ -147,6 +155,10 @@ struct SynthAnalogDevicesPass : public ScriptPass top_opt = "-top " + args[++argidx]; continue; } + if (args[argidx] == "-tech" && argidx+1 < args.size()) { + tech = args[++argidx]; + continue; + } if (args[argidx] == "-edif" && argidx+1 < args.size()) { edif_file = args[++argidx]; continue; @@ -231,6 +243,9 @@ struct SynthAnalogDevicesPass : public ScriptPass } extra_args(args, argidx, design); + if (!(tech == "t16ffc" || tech == "t40lp")) + log_cmd_error("Invalid ADI -tech setting: '%s'.\n", tech); + if (widemux != 0 && widemux < 2) log_cmd_error("-widemux value must be 0 or >= 2.\n"); @@ -334,8 +349,8 @@ struct SynthAnalogDevicesPass : public ScriptPass if (check_label("map_memory")) { std::string params = ""; - std::string lutrams_map = "+/analogdevices/lutrams__map.v"; - std::string brams_map = "+/analogdevices/brams__map.v"; + std::string lutrams_map = "+/analogdevices/lutrams_map.v"; + std::string brams_map = "+/analogdevices/brams_map.v"; if (help_mode) { params = " [...]"; } else { @@ -344,6 +359,13 @@ struct SynthAnalogDevicesPass : public ScriptPass lutrams_map = "+/analogdevices/lutrams_map.v"; params += " -lib +/analogdevices/brams.txt"; brams_map = "+/analogdevices/brams_map.v"; + if (tech == "t16ffc") { + params += " -D IS_T16FFC"; + brams_map += " -D IS_T16FFC"; + } else if (tech == "t40lp") { + params += " -D IS_T40LP"; + brams_map += " -D IS_T40LP"; + } if (nolutram) params += " -no-auto-distributed"; if (nobram) From 6ee0bfa913bdf7df3b2b458c4350ad093ecaa1a3 Mon Sep 17 00:00:00 2001 From: Lofty Date: Sun, 12 Oct 2025 11:17:50 +0100 Subject: [PATCH 264/291] analogdevices: prepare for t40lp timings --- techlibs/analogdevices/cells_sim.v | 64 +++++++++++++++---- techlibs/analogdevices/synth_analogdevices.cc | 6 +- 2 files changed, 53 insertions(+), 17 deletions(-) diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v index 0a2fadc7d..df6f1be50 100644 --- a/techlibs/analogdevices/cells_sim.v +++ b/techlibs/analogdevices/cells_sim.v @@ -41,17 +41,6 @@ module INBUF( endspecify endmodule -module IBUFG( - output O, - (* iopad_external_pin *) - input I); - parameter CAPACITANCE = "DONT_CARE"; - parameter IBUF_DELAY_VALUE = "0"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - assign O = I; -endmodule - module OUTBUF( (* iopad_external_pin *) output O, @@ -134,18 +123,22 @@ module INV( input I ); assign O = !I; +`ifdef t16ffc specify (I => O) = 22; endspecify +`endif endmodule (* abc9_lut=1 *) module LUT1(output O, input I0); parameter [1:0] INIT = 0; assign O = I0 ? INIT[1] : INIT[0]; +`ifdef t16ffc specify (I0 => O) = 22; endspecify +`endif endmodule (* abc9_lut=2 *) @@ -153,10 +146,12 @@ module LUT2(output O, input I0, I1); parameter [3:0] INIT = 0; wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0]; assign O = I0 ? s1[1] : s1[0]; +`ifdef t16ffc specify (I0 => O) = 22; (I1 => O) = 22; endspecify +`endif endmodule (* abc9_lut=3 *) @@ -165,11 +160,13 @@ module LUT3(output O, input I0, I1, I2); wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0]; wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; assign O = I0 ? s1[1] : s1[0]; +`ifdef t16ffc specify (I0 => O) = 22; (I1 => O) = 22; (I2 => O) = 22; endspecify +`endif endmodule (* abc9_lut=4 *) @@ -179,12 +176,14 @@ module LUT4(output O, input I0, I1, I2, I3); wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; assign O = I0 ? s1[1] : s1[0]; +`ifdef t16ffc specify (I0 => O) = 22; (I1 => O) = 22; (I2 => O) = 22; (I3 => O) = 22; endspecify +`endif endmodule (* abc9_lut=5 *) @@ -195,6 +194,7 @@ module LUT5(output O, input I0, I1, I2, I3, I4); wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; assign O = I0 ? s1[1] : s1[0]; +`ifdef t16ffc specify (I0 => O) = 22; (I1 => O) = 22; @@ -202,6 +202,7 @@ module LUT5(output O, input I0, I1, I2, I3, I4); (I3 => O) = 22; (I4 => O) = 22; endspecify +`endif endmodule (* abc9_lut=6 *) @@ -213,6 +214,7 @@ module LUT6(output O, input I0, I1, I2, I3, I4, I5); wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; assign O = I0 ? s1[1] : s1[0]; +`ifdef t16ffc specify (I0 => O) = 22; (I1 => O) = 22; @@ -221,6 +223,7 @@ module LUT6(output O, input I0, I1, I2, I3, I4, I5); (I4 => O) = 22; (I5 => O) = 22; endspecify +`endif endmodule module LUT6_D(output O6, output O5, input I0, I1, I2, I3, I4, I5); @@ -244,6 +247,7 @@ endmodule (* abc9_lut=12 *) module \$__ABC9_LUT7 (output O, input I0, I1, I2, I3, I4, I5, I6); `ifndef __ICARUS__ +`ifdef t16ffc specify (I0 => O) = 22 + 63 /* LUTMUX7.I1 */; (I1 => O) = 22 + 63 /* LUTMUX7.I1 */; @@ -254,6 +258,7 @@ module \$__ABC9_LUT7 (output O, input I0, I1, I2, I3, I4, I5, I6); (I6 => O) = 0 + 51 /* LUTMUX7.S */; endspecify `endif +`endif endmodule // This is a placeholder for ABC9 to extract the area/delay @@ -261,6 +266,7 @@ endmodule (* abc9_lut=24 *) module \$__ABC9_LUT8 (output O, input I0, I1, I2, I3, I4, I5, I6, I7); `ifndef __ICARUS__ +`ifdef t16ffc specify (I0 => O) = 22 + 63 /* LUTMUX7.I1 */ + 48 /* LUTMUX8.I0 */; (I1 => O) = 22 + 63 /* LUTMUX7.I1 */ + 48 /* LUTMUX8.I0 */; @@ -272,26 +278,31 @@ module \$__ABC9_LUT8 (output O, input I0, I1, I2, I3, I4, I5, I6, I7); (I7 => O) = 0 + 0 + 58 /* LUTMUX8.S */; endspecify `endif +`endif endmodule (* abc9_box, lib_whitebox *) module LUTMUX7(output O, input I0, I1, S); assign O = S ? I1 : I0; +`ifdef t16ffc specify (I0 => O) = 62; (I1 => O) = 63; (S => O) = 51; endspecify +`endif endmodule (* abc9_box, lib_whitebox *) module LUTMUX8(output O, input I0, I1, S); assign O = S ? I1 : I0; +`ifdef t16ffc specify (I0 => O) = 48; (I1 => O) = 46; (S => O) = 58; endspecify +`endif endmodule (* abc9_box, lib_whitebox *) @@ -309,8 +320,8 @@ module CRY4( assign CO[1] = S[1] ? CO[0] : DI[1]; assign CO[2] = S[2] ? CO[1] : DI[2]; assign CO[3] = S[3] ? CO[2] : DI[3]; +`ifdef t16ffc specify - // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L11-L46 (S[0] => O[0]) = 39; (CI => O[0]) = 43; (DI[0] => O[1]) = 81; @@ -356,6 +367,7 @@ module CRY4( (S[3] => CO[3]) = 81; (CI => CO[3]) = 20; endspecify +`endif endmodule (* abc9_box, lib_whitebox *) @@ -365,9 +377,11 @@ module CRY4INIT( (* abc9_carry *) input CYINIT ); +`ifdef t16ffc specify (CYINIT => CO) = 72; endspecify +`endif assign CO = CYINIT; endmodule @@ -394,6 +408,7 @@ module FFRE ( parameter [0:0] INIT = 1'b0; initial Q <= INIT; always @(posedge C) if (R) Q <= 1'b0; else if (CE) Q <= D; +`ifdef t16ffc specify $setup(D , posedge C, 31); $setup(CE, posedge C, 122); @@ -401,6 +416,7 @@ module FFRE ( if (R) (posedge C => (Q : 1'b0)) = 280; if (!R && CE) (posedge C => (Q : D)) = 280; endspecify +`endif endmodule (* abc9_flop, lib_whitebox *) @@ -415,6 +431,7 @@ module FFRE_N ( parameter [0:0] INIT = 1'b0; initial Q <= INIT; always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D; +`ifdef t16ffc specify $setup(D , negedge C, 31); $setup(CE, negedge C, 122); @@ -422,6 +439,7 @@ module FFRE_N ( if (R) (negedge C => (Q : 1'b0)) = 280; if (!R && CE) (negedge C => (Q : D)) = 280; endspecify +`endif endmodule module FFSE ( @@ -435,6 +453,7 @@ module FFSE ( parameter [0:0] INIT = 1'b1; initial Q <= INIT; always @(posedge C) if (S) Q <= 1'b1; else if (CE) Q <= D; +`ifdef t16ffc specify $setup(D , posedge C, 31); $setup(CE, posedge C, 122); @@ -442,6 +461,7 @@ module FFSE ( if (S) (negedge C => (Q : 1'b1)) = 280; if (!S && CE) (posedge C => (Q : D)) = 280; endspecify +`endif endmodule module FFSE_N ( @@ -455,6 +475,7 @@ module FFSE_N ( parameter [0:0] INIT = 1'b1; initial Q <= INIT; always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D; +`ifdef t16ffc specify $setup(D , negedge C, 31); $setup(CE, negedge C, 122); @@ -462,6 +483,7 @@ module FFSE_N ( if (S) (negedge C => (Q : 1'b1)) = 280; if (!S && CE) (negedge C => (Q : D)) = 280; endspecify +`endif endmodule module FFCE ( @@ -475,11 +497,13 @@ module FFCE ( parameter [0:0] INIT = 1'b0; initial Q <= INIT; always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D; +`ifdef t16ffc specify $setup(D , posedge C, 31); $setup(CE , posedge C, 122); if (!CLR && CE) (posedge C => (Q : D)) = 280; endspecify +`endif endmodule module FFCE_N ( @@ -493,11 +517,13 @@ module FFCE_N ( parameter [0:0] INIT = 1'b0; initial Q <= INIT; always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D; +`ifdef t16ffc specify $setup(D , negedge C, 31); $setup(CE , negedge C, 122); if (!CLR && CE) (negedge C => (Q : D)) = 280; endspecify +`endif endmodule module FFPE ( @@ -511,11 +537,13 @@ module FFPE ( parameter [0:0] INIT = 1'b1; initial Q <= INIT; always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D; +`ifdef t16ffc specify $setup(D , posedge C, 31); $setup(CE , posedge C, 122); if (!PRE && CE) (posedge C => (Q : D)) = 291; endspecify +`endif endmodule module FFPE_N ( @@ -529,11 +557,13 @@ module FFPE_N ( parameter [0:0] INIT = 1'b1; initial Q <= INIT; always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; +`ifdef t16ffc specify $setup(D , negedge C, 31); $setup(CE , negedge C, 122); if (!PRE && CE) (negedge C => (Q : D)) = 291; endspecify +`endif endmodule // LUTRAM. @@ -554,6 +584,7 @@ module RAMS32X1 ( reg [31:0] mem = INIT; assign O = mem[a]; always @(posedge WCLK) if (WE) mem[a] <= D; +`ifdef t16ffc specify $setup(A0, posedge WCLK, 0); $setup(A1, posedge WCLK, 0); @@ -569,6 +600,7 @@ module RAMS32X1 ( (A4 => O) = 63; (posedge WCLK => (O : D)) = 813; endspecify +`endif endmodule (* abc9_box, lib_whitebox *) @@ -585,6 +617,7 @@ module RAMS64X1 ( reg [63:0] mem = INIT; assign O = mem[a]; always @(posedge WCLK) if (WE) mem[a] <= D; +`ifdef t16ffc specify $setup(A0, posedge WCLK, 0); $setup(A1, posedge WCLK, 0); @@ -602,6 +635,7 @@ module RAMS64X1 ( (A5 => O) = 64; (posedge WCLK => (O : D)) = 762; endspecify +`endif endmodule // Dual port. @@ -623,6 +657,7 @@ module RAMD32X1 ( assign SPO = mem[a]; assign DPO = mem[dpra]; always @(posedge WCLK) if (WE) mem[a] <= D; +`ifdef t16ffc specify $setup(A0, posedge WCLK, 0); $setup(A1, posedge WCLK, 0); @@ -651,6 +686,7 @@ module RAMD32X1 ( (posedge WCLK => (SPO : D)) = 813; (posedge WCLK => (DPO : D)) = 813; endspecify +`endif endmodule (* abc9_box, lib_whitebox *) @@ -670,6 +706,7 @@ module RAMD64X1 ( assign SPO = mem[a]; assign DPO = mem[dpra]; always @(posedge WCLK) if (WE) mem[a] <= D; +`ifdef t16ffc specify $setup(A0, posedge WCLK, 0); $setup(A1, posedge WCLK, 0); @@ -701,6 +738,7 @@ module RAMD64X1 ( (posedge WCLK => (SPO : D)) = 762; (posedge WCLK => (DPO : D)) = 737; endspecify +`endif endmodule // Shift registers. @@ -718,6 +756,7 @@ module SRG16E ( reg [15:0] r = INIT; assign Q = r[{A3,A2,A1,A0}]; always @(posedge CLK) if (CE) r <= { r[14:0], D }; +`ifdef t16ffc specify $setup(D , posedge CLK, 173); if (CE) (posedge CLK => (Q : D)) = 1472; @@ -727,6 +766,7 @@ module SRG16E ( (A2 => Q) = 407; (A3 => Q) = 238; endspecify +`endif endmodule // DSP diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc index 6a1d471b6..d301a997e 100644 --- a/techlibs/analogdevices/synth_analogdevices.cc +++ b/techlibs/analogdevices/synth_analogdevices.cc @@ -266,12 +266,8 @@ struct SynthAnalogDevicesPass : public ScriptPass void script() override { if (check_label("begin")) { - std::string read_args; - read_args += " -lib -specify +/analogdevices/cells_sim.v"; - run("read_verilog" + read_args); - + run(stringf("read_verilog -lib -specify -D %s +/analogdevices/cells_sim.v", tech)); run("read_verilog -lib +/analogdevices/cells_xtra.v"); - run(stringf("hierarchy -check %s", top_opt.c_str())); } From 0a2b6a4f21bf37a2e86360e729dc71c88f07841c Mon Sep 17 00:00:00 2001 From: Lofty Date: Sun, 12 Oct 2025 11:22:46 +0100 Subject: [PATCH 265/291] analogdevices: expreso does not care about clock buffers --- techlibs/analogdevices/cells_sim.v | 70 ------------------- techlibs/analogdevices/synth_analogdevices.cc | 2 - 2 files changed, 72 deletions(-) diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v index df6f1be50..d0cab8418 100644 --- a/techlibs/analogdevices/cells_sim.v +++ b/techlibs/analogdevices/cells_sim.v @@ -55,68 +55,6 @@ module OUTBUF( endspecify endmodule -module BUFG( - (* clkbuf_driver *) - output O, - input I); - assign O = I; - specify - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/CLK_BUFG_TOP_R.sdf#L11 - (I => O) = 96; - endspecify -endmodule - -module BUFGCTRL( - (* clkbuf_driver *) - output O, - input I0, input I1, - (* invertible_pin = "IS_S0_INVERTED" *) - input S0, - (* invertible_pin = "IS_S1_INVERTED" *) - input S1, - (* invertible_pin = "IS_CE0_INVERTED" *) - input CE0, - (* invertible_pin = "IS_CE1_INVERTED" *) - input CE1, - (* invertible_pin = "IS_IGNORE0_INVERTED" *) - input IGNORE0, - (* invertible_pin = "IS_IGNORE1_INVERTED" *) - input IGNORE1); - -parameter [0:0] INIT_OUT = 1'b0; -parameter PRESELECT_I0 = "FALSE"; -parameter PRESELECT_I1 = "FALSE"; -parameter [0:0] IS_CE0_INVERTED = 1'b0; -parameter [0:0] IS_CE1_INVERTED = 1'b0; -parameter [0:0] IS_S0_INVERTED = 1'b0; -parameter [0:0] IS_S1_INVERTED = 1'b0; -parameter [0:0] IS_IGNORE0_INVERTED = 1'b0; -parameter [0:0] IS_IGNORE1_INVERTED = 1'b0; - -wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT); -wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT); -wire S0_true = (S0 ^ IS_S0_INVERTED); -wire S1_true = (S1 ^ IS_S1_INVERTED); - -assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT); - -endmodule - -module BUFHCE( - (* clkbuf_driver *) - output O, - input I, - (* invertible_pin = "IS_CE_INVERTED" *) - input CE); - -parameter [0:0] INIT_OUT = 1'b0; -parameter CE_TYPE = "SYNC"; -parameter [0:0] IS_CE_INVERTED = 1'b0; - -assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT); - -endmodule - module INV( (* clkbuf_inv = "I" *) output O, @@ -386,14 +324,6 @@ module CRY4INIT( assign CO = CYINIT; endmodule -module ORCY (output O, input CI, I); - assign O = CI | I; -endmodule - -module MULT_AND (output LO, input I0, I1); - assign LO = I0 & I1; -endmodule - // Flip-flops. (* abc9_flop, lib_whitebox *) diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc index d301a997e..c51bf6c45 100644 --- a/techlibs/analogdevices/synth_analogdevices.cc +++ b/techlibs/analogdevices/synth_analogdevices.cc @@ -496,8 +496,6 @@ struct SynthAnalogDevicesPass : public ScriptPass } if (check_label("finalize")) { - if (help_mode || !noclkbuf) - run("clkbufmap -buf BUFG O:I", "(skip if '-noclkbuf')"); run("clean"); } From 2c3876671b0f215976313de18247726dc5fa61e0 Mon Sep 17 00:00:00 2001 From: Lofty Date: Sun, 12 Oct 2025 11:31:23 +0100 Subject: [PATCH 266/291] analogdevices: use single tech param --- techlibs/analogdevices/cells_sim.v | 65 ++++++++----------- techlibs/analogdevices/lut_map.v | 8 +-- techlibs/analogdevices/synth_analogdevices.cc | 18 ++--- 3 files changed, 39 insertions(+), 52 deletions(-) diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v index d0cab8418..4e606aef4 100644 --- a/techlibs/analogdevices/cells_sim.v +++ b/techlibs/analogdevices/cells_sim.v @@ -36,9 +36,11 @@ module INBUF( parameter IFD_DELAY_VALUE = "AUTO"; parameter IOSTANDARD = "DEFAULT"; assign O = I; +`ifdef IS_T16FFC specify (I => O) = 22; endspecify +`endif endmodule module OUTBUF( @@ -50,18 +52,7 @@ module OUTBUF( parameter DRIVE = 12; parameter SLEW = "SLOW"; assign O = I; - specify - (I => O) = 22; - endspecify -endmodule - -module INV( - (* clkbuf_inv = "I" *) - output O, - input I -); - assign O = !I; -`ifdef t16ffc +`ifdef IS_T16FFC specify (I => O) = 22; endspecify @@ -72,7 +63,7 @@ endmodule module LUT1(output O, input I0); parameter [1:0] INIT = 0; assign O = I0 ? INIT[1] : INIT[0]; -`ifdef t16ffc +`ifdef IS_T16FFC specify (I0 => O) = 22; endspecify @@ -84,7 +75,7 @@ module LUT2(output O, input I0, I1); parameter [3:0] INIT = 0; wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0]; assign O = I0 ? s1[1] : s1[0]; -`ifdef t16ffc +`ifdef IS_T16FFC specify (I0 => O) = 22; (I1 => O) = 22; @@ -98,7 +89,7 @@ module LUT3(output O, input I0, I1, I2); wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0]; wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; assign O = I0 ? s1[1] : s1[0]; -`ifdef t16ffc +`ifdef IS_T16FFC specify (I0 => O) = 22; (I1 => O) = 22; @@ -114,7 +105,7 @@ module LUT4(output O, input I0, I1, I2, I3); wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; assign O = I0 ? s1[1] : s1[0]; -`ifdef t16ffc +`ifdef IS_T16FFC specify (I0 => O) = 22; (I1 => O) = 22; @@ -132,7 +123,7 @@ module LUT5(output O, input I0, I1, I2, I3, I4); wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; assign O = I0 ? s1[1] : s1[0]; -`ifdef t16ffc +`ifdef IS_T16FFC specify (I0 => O) = 22; (I1 => O) = 22; @@ -152,7 +143,7 @@ module LUT6(output O, input I0, I1, I2, I3, I4, I5); wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; assign O = I0 ? s1[1] : s1[0]; -`ifdef t16ffc +`ifdef IS_T16FFC specify (I0 => O) = 22; (I1 => O) = 22; @@ -185,7 +176,7 @@ endmodule (* abc9_lut=12 *) module \$__ABC9_LUT7 (output O, input I0, I1, I2, I3, I4, I5, I6); `ifndef __ICARUS__ -`ifdef t16ffc +`ifdef IS_T16FFC specify (I0 => O) = 22 + 63 /* LUTMUX7.I1 */; (I1 => O) = 22 + 63 /* LUTMUX7.I1 */; @@ -204,7 +195,7 @@ endmodule (* abc9_lut=24 *) module \$__ABC9_LUT8 (output O, input I0, I1, I2, I3, I4, I5, I6, I7); `ifndef __ICARUS__ -`ifdef t16ffc +`ifdef IS_T16FFC specify (I0 => O) = 22 + 63 /* LUTMUX7.I1 */ + 48 /* LUTMUX8.I0 */; (I1 => O) = 22 + 63 /* LUTMUX7.I1 */ + 48 /* LUTMUX8.I0 */; @@ -222,7 +213,7 @@ endmodule (* abc9_box, lib_whitebox *) module LUTMUX7(output O, input I0, I1, S); assign O = S ? I1 : I0; -`ifdef t16ffc +`ifdef IS_T16FFC specify (I0 => O) = 62; (I1 => O) = 63; @@ -234,7 +225,7 @@ endmodule (* abc9_box, lib_whitebox *) module LUTMUX8(output O, input I0, I1, S); assign O = S ? I1 : I0; -`ifdef t16ffc +`ifdef IS_T16FFC specify (I0 => O) = 48; (I1 => O) = 46; @@ -258,7 +249,7 @@ module CRY4( assign CO[1] = S[1] ? CO[0] : DI[1]; assign CO[2] = S[2] ? CO[1] : DI[2]; assign CO[3] = S[3] ? CO[2] : DI[3]; -`ifdef t16ffc +`ifdef IS_T16FFC specify (S[0] => O[0]) = 39; (CI => O[0]) = 43; @@ -315,7 +306,7 @@ module CRY4INIT( (* abc9_carry *) input CYINIT ); -`ifdef t16ffc +`ifdef IS_T16FFC specify (CYINIT => CO) = 72; endspecify @@ -338,7 +329,7 @@ module FFRE ( parameter [0:0] INIT = 1'b0; initial Q <= INIT; always @(posedge C) if (R) Q <= 1'b0; else if (CE) Q <= D; -`ifdef t16ffc +`ifdef IS_T16FFC specify $setup(D , posedge C, 31); $setup(CE, posedge C, 122); @@ -361,7 +352,7 @@ module FFRE_N ( parameter [0:0] INIT = 1'b0; initial Q <= INIT; always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D; -`ifdef t16ffc +`ifdef IS_T16FFC specify $setup(D , negedge C, 31); $setup(CE, negedge C, 122); @@ -383,7 +374,7 @@ module FFSE ( parameter [0:0] INIT = 1'b1; initial Q <= INIT; always @(posedge C) if (S) Q <= 1'b1; else if (CE) Q <= D; -`ifdef t16ffc +`ifdef IS_T16FFC specify $setup(D , posedge C, 31); $setup(CE, posedge C, 122); @@ -405,7 +396,7 @@ module FFSE_N ( parameter [0:0] INIT = 1'b1; initial Q <= INIT; always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D; -`ifdef t16ffc +`ifdef IS_T16FFC specify $setup(D , negedge C, 31); $setup(CE, negedge C, 122); @@ -427,7 +418,7 @@ module FFCE ( parameter [0:0] INIT = 1'b0; initial Q <= INIT; always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D; -`ifdef t16ffc +`ifdef IS_T16FFC specify $setup(D , posedge C, 31); $setup(CE , posedge C, 122); @@ -447,7 +438,7 @@ module FFCE_N ( parameter [0:0] INIT = 1'b0; initial Q <= INIT; always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D; -`ifdef t16ffc +`ifdef IS_T16FFC specify $setup(D , negedge C, 31); $setup(CE , negedge C, 122); @@ -467,7 +458,7 @@ module FFPE ( parameter [0:0] INIT = 1'b1; initial Q <= INIT; always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D; -`ifdef t16ffc +`ifdef IS_T16FFC specify $setup(D , posedge C, 31); $setup(CE , posedge C, 122); @@ -487,7 +478,7 @@ module FFPE_N ( parameter [0:0] INIT = 1'b1; initial Q <= INIT; always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; -`ifdef t16ffc +`ifdef IS_T16FFC specify $setup(D , negedge C, 31); $setup(CE , negedge C, 122); @@ -514,7 +505,7 @@ module RAMS32X1 ( reg [31:0] mem = INIT; assign O = mem[a]; always @(posedge WCLK) if (WE) mem[a] <= D; -`ifdef t16ffc +`ifdef IS_T16FFC specify $setup(A0, posedge WCLK, 0); $setup(A1, posedge WCLK, 0); @@ -547,7 +538,7 @@ module RAMS64X1 ( reg [63:0] mem = INIT; assign O = mem[a]; always @(posedge WCLK) if (WE) mem[a] <= D; -`ifdef t16ffc +`ifdef IS_T16FFC specify $setup(A0, posedge WCLK, 0); $setup(A1, posedge WCLK, 0); @@ -587,7 +578,7 @@ module RAMD32X1 ( assign SPO = mem[a]; assign DPO = mem[dpra]; always @(posedge WCLK) if (WE) mem[a] <= D; -`ifdef t16ffc +`ifdef IS_T16FFC specify $setup(A0, posedge WCLK, 0); $setup(A1, posedge WCLK, 0); @@ -636,7 +627,7 @@ module RAMD64X1 ( assign SPO = mem[a]; assign DPO = mem[dpra]; always @(posedge WCLK) if (WE) mem[a] <= D; -`ifdef t16ffc +`ifdef IS_T16FFC specify $setup(A0, posedge WCLK, 0); $setup(A1, posedge WCLK, 0); @@ -686,7 +677,7 @@ module SRG16E ( reg [15:0] r = INIT; assign Q = r[{A3,A2,A1,A0}]; always @(posedge CLK) if (CE) r <= { r[14:0], D }; -`ifdef t16ffc +`ifdef IS_T16FFC specify $setup(D , posedge CLK, 173); if (CE) (posedge CLK => (Q : D)) = 1472; diff --git a/techlibs/analogdevices/lut_map.v b/techlibs/analogdevices/lut_map.v index a0b617b10..832b5cbfb 100644 --- a/techlibs/analogdevices/lut_map.v +++ b/techlibs/analogdevices/lut_map.v @@ -32,12 +32,8 @@ module \$lut (A, Y); generate if (WIDTH == 1) begin - if (LUT == 2'b01) begin - INV _TECHMAP_REPLACE_ (.O(Y), .I(A[0])); - end else begin - LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), - .I0(A[0])); - end + LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), + .I0(A[0])); end else if (WIDTH == 2) begin LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc index c51bf6c45..7b18ced35 100644 --- a/techlibs/analogdevices/synth_analogdevices.cc +++ b/techlibs/analogdevices/synth_analogdevices.cc @@ -114,7 +114,7 @@ struct SynthAnalogDevicesPass : public ScriptPass log("\n"); } - std::string top_opt, edif_file, json_file, tech; + std::string top_opt, edif_file, json_file, tech, tech_param; bool flatten, retime, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp; bool abc9, dff; bool flatten_before_abc; @@ -126,6 +126,7 @@ struct SynthAnalogDevicesPass : public ScriptPass top_opt = "-auto-top"; edif_file.clear(); tech = "t16ffc"; + tech_param = " -D IS_T16FFC"; flatten = true; retime = false; noiopad = false; @@ -157,6 +158,10 @@ struct SynthAnalogDevicesPass : public ScriptPass } if (args[argidx] == "-tech" && argidx+1 < args.size()) { tech = args[++argidx]; + if (tech == "t16ffc") + tech_param = " -D IS_T16FFC"; + else if (tech == "t40lp") + tech_param = " -D IS_T40LP"; continue; } if (args[argidx] == "-edif" && argidx+1 < args.size()) { @@ -266,7 +271,7 @@ struct SynthAnalogDevicesPass : public ScriptPass void script() override { if (check_label("begin")) { - run(stringf("read_verilog -lib -specify -D %s +/analogdevices/cells_sim.v", tech)); + run(stringf("read_verilog -lib -specify %s +/analogdevices/cells_sim.v", tech_param)); run("read_verilog -lib +/analogdevices/cells_xtra.v"); run(stringf("hierarchy -check %s", top_opt.c_str())); } @@ -355,13 +360,8 @@ struct SynthAnalogDevicesPass : public ScriptPass lutrams_map = "+/analogdevices/lutrams_map.v"; params += " -lib +/analogdevices/brams.txt"; brams_map = "+/analogdevices/brams_map.v"; - if (tech == "t16ffc") { - params += " -D IS_T16FFC"; - brams_map += " -D IS_T16FFC"; - } else if (tech == "t40lp") { - params += " -D IS_T40LP"; - brams_map += " -D IS_T40LP"; - } + params += tech_param; + brams_map += tech_param; if (nolutram) params += " -no-auto-distributed"; if (nobram) From 4954fc980f66b943323ccac3b7307598f79462f2 Mon Sep 17 00:00:00 2001 From: Lofty Date: Sun, 12 Oct 2025 12:55:09 +0100 Subject: [PATCH 267/291] analogdevices: timings for t40lp --- techlibs/analogdevices/cells_sim.v | 340 ++++++++++++++++++++++++++++- 1 file changed, 331 insertions(+), 9 deletions(-) diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v index 4e606aef4..39a2d1025 100644 --- a/techlibs/analogdevices/cells_sim.v +++ b/techlibs/analogdevices/cells_sim.v @@ -41,6 +41,11 @@ module INBUF( (I => O) = 22; endspecify `endif +`ifdef IS_T40LP + specify + (I => O) = 121; + endspecify +`endif endmodule module OUTBUF( @@ -57,6 +62,11 @@ module OUTBUF( (I => O) = 22; endspecify `endif +`ifdef IS_T40LP + specify + (I => O) = 121; + endspecify +`endif endmodule (* abc9_lut=1 *) @@ -68,6 +78,11 @@ module LUT1(output O, input I0); (I0 => O) = 22; endspecify `endif +`ifdef IS_T40LP + specify + (I0 => O) = 121; + endspecify +`endif endmodule (* abc9_lut=2 *) @@ -81,6 +96,12 @@ module LUT2(output O, input I0, I1); (I1 => O) = 22; endspecify `endif +`ifdef IS_T40LP + specify + (I0 => O) = 121; + (I1 => O) = 121; + endspecify +`endif endmodule (* abc9_lut=3 *) @@ -96,6 +117,13 @@ module LUT3(output O, input I0, I1, I2); (I2 => O) = 22; endspecify `endif +`ifdef IS_T40LP + specify + (I0 => O) = 121; + (I1 => O) = 121; + (I2 => O) = 121; + endspecify +`endif endmodule (* abc9_lut=4 *) @@ -113,6 +141,14 @@ module LUT4(output O, input I0, I1, I2, I3); (I3 => O) = 22; endspecify `endif +`ifdef IS_T40LP + specify + (I0 => O) = 121; + (I1 => O) = 121; + (I2 => O) = 121; + (I3 => O) = 121; + endspecify +`endif endmodule (* abc9_lut=5 *) @@ -132,6 +168,15 @@ module LUT5(output O, input I0, I1, I2, I3, I4); (I4 => O) = 22; endspecify `endif +`ifdef IS_T40LP + specify + (I0 => O) = 121; + (I1 => O) = 121; + (I2 => O) = 121; + (I3 => O) = 121; + (I4 => O) = 121; + endspecify +`endif endmodule (* abc9_lut=6 *) @@ -153,6 +198,16 @@ module LUT6(output O, input I0, I1, I2, I3, I4, I5); (I5 => O) = 22; endspecify `endif +`ifdef IS_T40LP + specify + (I0 => O) = 121; + (I1 => O) = 121; + (I2 => O) = 121; + (I3 => O) = 121; + (I4 => O) = 121; + (I5 => O) = 121; + endspecify +`endif endmodule module LUT6_D(output O6, output O5, input I0, I1, I2, I3, I4, I5); @@ -187,6 +242,17 @@ module \$__ABC9_LUT7 (output O, input I0, I1, I2, I3, I4, I5, I6); (I6 => O) = 0 + 51 /* LUTMUX7.S */; endspecify `endif +`ifdef IS_T40LP + specify + (I0 => O) = 121 + 140 /* LUTMUX7.I0 */; + (I1 => O) = 121 + 140 /* LUTMUX7.I0 */; + (I2 => O) = 121 + 140 /* LUTMUX7.I0 */; + (I3 => O) = 121 + 140 /* LUTMUX7.I0 */; + (I4 => O) = 121 + 140 /* LUTMUX7.I0 */; + (I5 => O) = 121 + 140 /* LUTMUX7.I0 */; + (I6 => O) = 0 + 162 /* LUTMUX7.S */; + endspecify +`endif `endif endmodule @@ -207,6 +273,18 @@ module \$__ABC9_LUT8 (output O, input I0, I1, I2, I3, I4, I5, I6, I7); (I7 => O) = 0 + 0 + 58 /* LUTMUX8.S */; endspecify `endif +`ifdef IS_T40LP + specify + (I0 => O) = 121 + 140 /* LUTMUX7.I0 */ + 146 /* LUTMUX8.I1 */; + (I1 => O) = 121 + 140 /* LUTMUX7.I0 */ + 146 /* LUTMUX8.I1 */; + (I2 => O) = 121 + 140 /* LUTMUX7.I0 */ + 146 /* LUTMUX8.I1 */; + (I3 => O) = 121 + 140 /* LUTMUX7.I0 */ + 146 /* LUTMUX8.I1 */; + (I4 => O) = 121 + 140 /* LUTMUX7.I0 */ + 146 /* LUTMUX8.I1 */; + (I5 => O) = 121 + 140 /* LUTMUX7.I0 */ + 146 /* LUTMUX8.I1 */; + (I6 => O) = 0 + 162 /* LUTMUX7.S */ + 146 /* LUTMUX8.I1 */; + (I7 => O) = 0 + 0 + 181 /* LUTMUX8.S */; + endspecify +`endif `endif endmodule @@ -220,6 +298,13 @@ module LUTMUX7(output O, input I0, I1, S); (S => O) = 51; endspecify `endif +`ifdef IS_T40LP + specify + (I0 => O) = 140; + (I1 => O) = 140; + (S => O) = 162; + endspecify +`endif endmodule (* abc9_box, lib_whitebox *) @@ -232,6 +317,13 @@ module LUTMUX8(output O, input I0, I1, S); (S => O) = 58; endspecify `endif +`ifdef IS_T40LP + specify + (I0 => O) = 140; + (I1 => O) = 146; + (S => O) = 181; + endspecify +`endif endmodule (* abc9_box, lib_whitebox *) @@ -297,6 +389,54 @@ module CRY4( (CI => CO[3]) = 20; endspecify `endif +`ifdef IS_T40LP + specify + (S[0] => O[0]) = 128; + (CI => O[0]) = 122; + (DI[0] => O[1]) = 268; + (S[0] => O[1]) = 256; + (S[1] => O[1]) = 141; + (CI => O[1]) = 173; + (DI[0] => O[2]) = 344; + (DI[1] => O[2]) = 320; + (S[0] => O[2]) = 271; + (S[1] => O[2]) = 225; + (S[2] => O[2]) = 129; + (CI => O[2]) = 223; + (DI[0] => O[3]) = 371; + (DI[1] => O[3]) = 383; + (DI[2] => O[3]) = 327; + (S[0] => O[3]) = 342; + (S[1] => O[3]) = 327; + (S[2] => O[3]) = 273; + (S[3] => O[3]) = 145; + (CI => O[3]) = 301; + (DI[0] => CO[0]) = 243; + (S[0] => CO[0]) = 136; + (CI => CO[0]) = 119; + (DI[0] => CO[1]) = 242; + (DI[1] => CO[1]) = 251; + (S[0] => CO[1]) = 220; + (S[1] => CO[1]) = 159; + (CI => CO[1]) = 155; + (DI[0] => CO[2]) = 275; + (DI[1] => CO[2]) = 241; + (DI[2] => CO[2]) = 231; + (S[0] => CO[2]) = 238; + (S[1] => CO[2]) = 197; + (S[2] => CO[2]) = 167; + (CI => CO[2]) = 197; + (DI[0] => CO[3]) = 294; + (DI[1] => CO[3]) = 303; + (DI[2] => CO[3]) = 317; + (DI[3] => CO[3]) = 205; + (S[0] => CO[3]) = 250; + (S[1] => CO[3]) = 292; + (S[2] => CO[3]) = 231; + (S[3] => CO[3]) = 178; + (CI => CO[3]) = 229; + endspecify +`endif endmodule (* abc9_box, lib_whitebox *) @@ -306,13 +446,17 @@ module CRY4INIT( (* abc9_carry *) input CYINIT ); + assign CO = CYINIT; `ifdef IS_T16FFC specify (CYINIT => CO) = 72; endspecify `endif - - assign CO = CYINIT; +`ifdef IS_T40LP + specify + (CYINIT => CO) = 205; + endspecify +`endif endmodule // Flip-flops. @@ -338,6 +482,17 @@ module FFRE ( if (!R && CE) (posedge C => (Q : D)) = 280; endspecify `endif +`ifdef IS_T40LP + specify + $setup(D , posedge C, 119); + $setup(CE, posedge C, 385); + $setup(R , posedge C, 565); + // HACK: no clock-to-Q timings; using FFCE timing + if (R) (posedge C => (Q : 1'b0)) = 689; + // HACK: no clock-to-Q timings; using FFCE timing + if (!R && CE) (posedge C => (Q : D)) = 689; + endspecify +`endif endmodule (* abc9_flop, lib_whitebox *) @@ -361,6 +516,17 @@ module FFRE_N ( if (!R && CE) (negedge C => (Q : D)) = 280; endspecify `endif +`ifdef IS_T40LP + specify + $setup(D , negedge C, 119); + $setup(CE, negedge C, 385); + $setup(R , negedge C, 565); + // HACK: no clock-to-Q timings; using FFCE timing + if (R) (negedge C => (Q : 1'b0)) = 689; + // HACK: no clock-to-Q timings; using FFCE timing + if (!R && CE) (negedge C => (Q : D)) = 689; + endspecify +`endif endmodule module FFSE ( @@ -383,6 +549,17 @@ module FFSE ( if (!S && CE) (posedge C => (Q : D)) = 280; endspecify `endif +`ifdef IS_T40LP + specify + $setup(D , posedge C, 119); + $setup(CE, posedge C, 385); + $setup(S , posedge C, 584); + // HACK: no clock-to-Q timings; using FFCE timing + if (S) (negedge C => (Q : 1'b1)) = 689; + // HACK: no clock-to-Q timings; using FFCE timing + if (!S && CE) (posedge C => (Q : D)) = 689; + endspecify +`endif endmodule module FFSE_N ( @@ -405,6 +582,17 @@ module FFSE_N ( if (!S && CE) (negedge C => (Q : D)) = 280; endspecify `endif +`ifdef IS_T40LP + specify + $setup(D , negedge C, 119); + $setup(CE, negedge C, 385); + $setup(S , negedge C, 584); + // HACK: no clock-to-Q timings; using FFCE timing + if (S) (negedge C => (Q : 1'b1)) = 689; + // HACK: no clock-to-Q timings; using FFCE timing + if (!S && CE) (negedge C => (Q : D)) = 689; + endspecify +`endif endmodule module FFCE ( @@ -421,10 +609,17 @@ module FFCE ( `ifdef IS_T16FFC specify $setup(D , posedge C, 31); - $setup(CE , posedge C, 122); + $setup(CE, posedge C, 122); if (!CLR && CE) (posedge C => (Q : D)) = 280; endspecify `endif +`ifdef IS_T40LP + specify + $setup(D , posedge C, 119); + $setup(CE, posedge C, 385); + if (!CLR && CE) (posedge C => (Q : D)) = 689; + endspecify +`endif endmodule module FFCE_N ( @@ -441,10 +636,17 @@ module FFCE_N ( `ifdef IS_T16FFC specify $setup(D , negedge C, 31); - $setup(CE , negedge C, 122); + $setup(CE, negedge C, 122); if (!CLR && CE) (negedge C => (Q : D)) = 280; endspecify `endif +`ifdef IS_T40LP + specify + $setup(D , negedge C, 119); + $setup(CE, negedge C, 385); + if (!CLR && CE) (negedge C => (Q : D)) = 689; + endspecify +`endif endmodule module FFPE ( @@ -461,10 +663,18 @@ module FFPE ( `ifdef IS_T16FFC specify $setup(D , posedge C, 31); - $setup(CE , posedge C, 122); + $setup(CE, posedge C, 122); if (!PRE && CE) (posedge C => (Q : D)) = 291; endspecify `endif +`ifdef IS_T40LP + specify + $setup(D , posedge C, 119); + $setup(CE, posedge C, 385); + // HACK: no clock-to-Q timings; using FFPE_N timing + if (!PRE && CE) (posedge C => (Q : D)) = 712; + endspecify +`endif endmodule module FFPE_N ( @@ -485,6 +695,15 @@ module FFPE_N ( if (!PRE && CE) (negedge C => (Q : D)) = 291; endspecify `endif +`ifdef IS_T40LP + specify + // HACK: no D setup time; using FFPE timing + $setup(D , negedge C, 119); + // HACK: no CE setup time; using FFPE timing + $setup(CE, negedge C, 385); + if (!PRE && CE) (negedge C => (Q : D)) = 712; + endspecify +`endif endmodule // LUTRAM. @@ -507,6 +726,7 @@ module RAMS32X1 ( always @(posedge WCLK) if (WE) mem[a] <= D; `ifdef IS_T16FFC specify + // HACK: no setup timing $setup(A0, posedge WCLK, 0); $setup(A1, posedge WCLK, 0); $setup(A2, posedge WCLK, 0); @@ -522,6 +742,24 @@ module RAMS32X1 ( (posedge WCLK => (O : D)) = 813; endspecify `endif +`ifdef IS_T40LP + specify + // HACK: no setup timing + $setup(A0, posedge WCLK, 0); + $setup(A1, posedge WCLK, 0); + $setup(A2, posedge WCLK, 0); + $setup(A3, posedge WCLK, 0); + $setup(A4, posedge WCLK, 0); + $setup(D, posedge WCLK, 0); + $setup(WE, posedge WCLK, 0); + (A0 => O) = 168; + (A1 => O) = 168; + (A2 => O) = 168; + (A3 => O) = 168; + (A4 => O) = 168; + (posedge WCLK => (O : D)) = 1586; + endspecify +`endif endmodule (* abc9_box, lib_whitebox *) @@ -540,6 +778,7 @@ module RAMS64X1 ( always @(posedge WCLK) if (WE) mem[a] <= D; `ifdef IS_T16FFC specify + // HACK: no setup timing $setup(A0, posedge WCLK, 0); $setup(A1, posedge WCLK, 0); $setup(A2, posedge WCLK, 0); @@ -557,6 +796,26 @@ module RAMS64X1 ( (posedge WCLK => (O : D)) = 762; endspecify `endif +`ifdef IS_T40LP + specify + // HACK: no setup timing + $setup(A0, posedge WCLK, 0); + $setup(A1, posedge WCLK, 0); + $setup(A2, posedge WCLK, 0); + $setup(A3, posedge WCLK, 0); + $setup(A4, posedge WCLK, 0); + $setup(A5, posedge WCLK, 0); + $setup(D, posedge WCLK, 0); + $setup(WE, posedge WCLK, 0); + (A0 => O) = 466; + (A1 => O) = 466; + (A2 => O) = 466; + (A3 => O) = 466; + (A4 => O) = 466; + (A5 => O) = 187; + (posedge WCLK => (O : D)) = 1730; + endspecify +`endif endmodule // Dual port. @@ -580,12 +839,12 @@ module RAMD32X1 ( always @(posedge WCLK) if (WE) mem[a] <= D; `ifdef IS_T16FFC specify + // HACK: no setup timing $setup(A0, posedge WCLK, 0); $setup(A1, posedge WCLK, 0); $setup(A2, posedge WCLK, 0); $setup(A3, posedge WCLK, 0); $setup(A4, posedge WCLK, 0); - // HACK: No timing arcs for DPRAn; using ones for An $setup(DPRA0, posedge WCLK, 0); $setup(DPRA1, posedge WCLK, 0); $setup(DPRA2, posedge WCLK, 0); @@ -594,6 +853,7 @@ module RAMD32X1 ( $setup(D, posedge WCLK, 0); $setup(WE, posedge WCLK, 0); // HACK: No timing arcs for SPO; using ones for DPO + // (are we meant to use the single-port timings here?) (A0 => SPO) = 66; (A1 => SPO) = 66; (A2 => SPO) = 66; @@ -608,6 +868,37 @@ module RAMD32X1 ( (posedge WCLK => (DPO : D)) = 813; endspecify `endif +`ifdef IS_T40LP + specify + // HACK: no setup timing + $setup(A0, posedge WCLK, 0); + $setup(A1, posedge WCLK, 0); + $setup(A2, posedge WCLK, 0); + $setup(A3, posedge WCLK, 0); + $setup(A4, posedge WCLK, 0); + $setup(DPRA0, posedge WCLK, 0); + $setup(DPRA1, posedge WCLK, 0); + $setup(DPRA2, posedge WCLK, 0); + $setup(DPRA3, posedge WCLK, 0); + $setup(DPRA4, posedge WCLK, 0); + $setup(D, posedge WCLK, 0); + $setup(WE, posedge WCLK, 0); + // HACK: No timing arcs for SPO; using ones for DPO + // (are we meant to use the single-port timings here?) + (A0 => SPO) = 142; + (A1 => SPO) = 142; + (A2 => SPO) = 142; + (A3 => SPO) = 142; + (A4 => SPO) = 142; + (DPRA0 => DPO) = 142; + (DPRA1 => DPO) = 142; + (DPRA2 => DPO) = 142; + (DPRA3 => DPO) = 142; + (DPRA4 => DPO) = 142; + (posedge WCLK => (SPO : D)) = 1586; + (posedge WCLK => (DPO : D)) = 1586; + endspecify +`endif endmodule (* abc9_box, lib_whitebox *) @@ -629,13 +920,13 @@ module RAMD64X1 ( always @(posedge WCLK) if (WE) mem[a] <= D; `ifdef IS_T16FFC specify + // HACK: no setup timing $setup(A0, posedge WCLK, 0); $setup(A1, posedge WCLK, 0); $setup(A2, posedge WCLK, 0); $setup(A3, posedge WCLK, 0); $setup(A4, posedge WCLK, 0); $setup(A5, posedge WCLK, 0); - // HACK: No timing arcs for DPRAn; using ones for An $setup(DPRA0, posedge WCLK, 0); $setup(DPRA1, posedge WCLK, 0); $setup(DPRA2, posedge WCLK, 0); @@ -660,6 +951,39 @@ module RAMD64X1 ( (posedge WCLK => (DPO : D)) = 737; endspecify `endif +`ifdef IS_T40LP + specify + // HACK: no setup timing + $setup(A0, posedge WCLK, 0); + $setup(A1, posedge WCLK, 0); + $setup(A2, posedge WCLK, 0); + $setup(A3, posedge WCLK, 0); + $setup(A4, posedge WCLK, 0); + $setup(A5, posedge WCLK, 0); + $setup(DPRA0, posedge WCLK, 0); + $setup(DPRA1, posedge WCLK, 0); + $setup(DPRA2, posedge WCLK, 0); + $setup(DPRA3, posedge WCLK, 0); + $setup(DPRA4, posedge WCLK, 0); + $setup(DPRA5, posedge WCLK, 0); + $setup(D, posedge WCLK, 0); + $setup(WE, posedge WCLK, 0); + (A0 => SPO) = 466; + (A1 => SPO) = 466; + (A2 => SPO) = 466; + (A3 => SPO) = 466; + (A4 => SPO) = 466; + (A5 => SPO) = 187; + (DPRA0 => DPO) = 380; + (DPRA1 => DPO) = 380; + (DPRA2 => DPO) = 380; + (DPRA3 => DPO) = 380; + (DPRA4 => DPO) = 380; + (DPRA5 => DPO) = 195; + (posedge WCLK => (SPO : D)) = 1730; + (posedge WCLK => (DPO : D)) = 1799; + endspecify +`endif endmodule // Shift registers. @@ -677,7 +1001,6 @@ module SRG16E ( reg [15:0] r = INIT; assign Q = r[{A3,A2,A1,A0}]; always @(posedge CLK) if (CE) r <= { r[14:0], D }; -`ifdef IS_T16FFC specify $setup(D , posedge CLK, 173); if (CE) (posedge CLK => (Q : D)) = 1472; @@ -687,7 +1010,6 @@ module SRG16E ( (A2 => Q) = 407; (A3 => Q) = 238; endspecify -`endif endmodule // DSP From 891b89f60d7a4cc343ec1f44c88cea79b53e1554 Mon Sep 17 00:00:00 2001 From: Lofty Date: Wed, 15 Oct 2025 04:55:12 +0100 Subject: [PATCH 268/291] analogdevices: remove cells_xtra --- techlibs/analogdevices/Makefile.inc | 1 - techlibs/analogdevices/cells_xtra.py | 730 - techlibs/analogdevices/cells_xtra.v | 34016 ---------------- techlibs/analogdevices/synth_analogdevices.cc | 1 - 4 files changed, 34748 deletions(-) delete mode 100644 techlibs/analogdevices/cells_xtra.py delete mode 100644 techlibs/analogdevices/cells_xtra.v diff --git a/techlibs/analogdevices/Makefile.inc b/techlibs/analogdevices/Makefile.inc index 52a48f8b4..5c2d6f05d 100644 --- a/techlibs/analogdevices/Makefile.inc +++ b/techlibs/analogdevices/Makefile.inc @@ -3,7 +3,6 @@ OBJS += techlibs/analogdevices/synth_analogdevices.o $(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/cells_map.v)) $(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/cells_sim.v)) -$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/cells_xtra.v)) $(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/lutrams.txt)) $(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/lutrams_map.v)) diff --git a/techlibs/analogdevices/cells_xtra.py b/techlibs/analogdevices/cells_xtra.py deleted file mode 100644 index 645f1497d..000000000 --- a/techlibs/analogdevices/cells_xtra.py +++ /dev/null @@ -1,730 +0,0 @@ -#!/usr/bin/env python3 - -from argparse import ArgumentParser -from io import StringIO -from enum import Enum, auto -import os.path -import sys -import re - - -class Cell: - def __init__(self, name, keep=False, port_attrs={}): - self.name = name - self.keep = keep - self.port_attrs = port_attrs - - -CELLS = [ - # Design element types listed in: - # - UG607 (Spartan 3) - # - UG613 (Spartan 3A) - # - UG617 (Spartan 3E) - # - UG615 (Spartan 6) - # - UG619 (Virtex 4) - # - UG621 (Virtex 5) - # - UG623 (Virtex 6) - # - UG953 (Series 7) - # - UG974 (Ultrascale) - - # CLB -- RAM/ROM. - # Cell('RAM16X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM16X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM128X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM512X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM16X2S', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM16X4S', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM32X4S', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM16X8S', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM32X8S', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM16X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM16X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM32X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM64X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM256X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM32M16', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM64M8', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM32X16DR8', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAM64X8SW', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('ROM16X1'), - # Cell('ROM32X1'), - # Cell('ROM64X1'), - # Cell('ROM128X1'), - # Cell('ROM256X1'), - - # CLB -- registers/latches. - # Virtex 1/2/4/5, Spartan 3. - # Cell('FDCPE', port_attrs={'C': ['clkbuf_sink']}), - # Cell('FDRSE', port_attrs={'C': ['clkbuf_sink']}), - # Cell('LDCPE', port_attrs={'C': ['clkbuf_sink']}), - # Virtex 6, Spartan 6, Series 7, Ultrascale. - # Cell('FDCE'), - # Cell('FDPE'), - # Cell('FDRE'), - # Cell('FDSE'), - # Cell('LDCE'), - # Cell('LDPE'), - # Cell('AND2B1L'), - # Cell('OR2L'), - - # CLB -- other. - # Cell('LUT1'), - # Cell('LUT2'), - # Cell('LUT3'), - # Cell('LUT4'), - # Cell('LUT5'), - # Cell('LUT6'), - # Cell('LUT6_2'), - # Cell('MUXF5'), - # Cell('MUXF6'), - # Cell('MUXF7'), - # Cell('MUXF8'), - # Cell('MUXF9'), - # Cell('CARRY4'), - # Cell('CARRY8'), - # Cell('MUXCY'), - # Cell('XORCY'), - # Cell('ORCY'), - # Cell('MULT_AND'), - # Cell('SRL16', port_attrs={'CLK': ['clkbuf_sink']}), - # Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}), - # Cell('SRLC16', port_attrs={'CLK': ['clkbuf_sink']}), - # Cell('SRLC16E', port_attrs={'CLK': ['clkbuf_sink']}), - # Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}), - # Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}), - - # Block RAM. - # Virtex. - Cell('RAMB4_S1', port_attrs={'CLK': ['clkbuf_sink']}), - Cell('RAMB4_S2', port_attrs={'CLK': ['clkbuf_sink']}), - Cell('RAMB4_S4', port_attrs={'CLK': ['clkbuf_sink']}), - Cell('RAMB4_S8', port_attrs={'CLK': ['clkbuf_sink']}), - Cell('RAMB4_S16', port_attrs={'CLK': ['clkbuf_sink']}), - Cell('RAMB4_S1_S1', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB4_S1_S2', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB4_S1_S4', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB4_S1_S8', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB4_S1_S16', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB4_S2_S2', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB4_S2_S4', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB4_S2_S8', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB4_S2_S16', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB4_S4_S4', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB4_S4_S8', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB4_S4_S16', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB4_S8_S8', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB4_S8_S16', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB4_S16_S16', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - # Virtex 2, Spartan 3. - Cell('RAMB16_S1', port_attrs={'CLK': ['clkbuf_sink']}), - Cell('RAMB16_S2', port_attrs={'CLK': ['clkbuf_sink']}), - Cell('RAMB16_S4', port_attrs={'CLK': ['clkbuf_sink']}), - Cell('RAMB16_S9', port_attrs={'CLK': ['clkbuf_sink']}), - Cell('RAMB16_S18', port_attrs={'CLK': ['clkbuf_sink']}), - Cell('RAMB16_S36', port_attrs={'CLK': ['clkbuf_sink']}), - Cell('RAMB16_S1_S1', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB16_S1_S2', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB16_S1_S4', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB16_S1_S9', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB16_S1_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB16_S1_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB16_S2_S2', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB16_S2_S4', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB16_S2_S9', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB16_S2_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB16_S2_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB16_S4_S4', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB16_S4_S9', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB16_S4_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB16_S4_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB16_S9_S9', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB16_S9_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB16_S9_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB16_S18_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB16_S18_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB16_S36_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - # Spartan 3A (in addition to above). - Cell('RAMB16BWE_S18', port_attrs={'CLK': ['clkbuf_sink']}), - Cell('RAMB16BWE_S36', port_attrs={'CLK': ['clkbuf_sink']}), - Cell('RAMB16BWE_S18_S9', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB16BWE_S18_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB16BWE_S36_S9', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB16BWE_S36_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB16BWE_S36_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - # Spartan 3A DSP. - Cell('RAMB16BWER', port_attrs={ 'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - # Spartan 6 (in addition to above). - Cell('RAMB8BWER', port_attrs={ 'CLKAWRCLK': ['clkbuf_sink'], 'CLKBRDCLK': ['clkbuf_sink']}), - # Virtex 4. - Cell('FIFO16', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - Cell('RAMB16', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB32_S64_ECC', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - # Virtex 5. - Cell('FIFO18', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - Cell('FIFO18_36', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - Cell('FIFO36', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - Cell('FIFO36_72', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - Cell('RAMB18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('RAMB18SDP', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - Cell('RAMB36SDP', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - # Virtex 6 / Series 7. - Cell('FIFO18E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - Cell('FIFO36E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - #Cell('RAMB18E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']]}), - #Cell('RAMB36E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']]}), - # Ultrascale. - Cell('FIFO18E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - Cell('FIFO36E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - Cell('RAMB18E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}), - Cell('RAMB36E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}), - - # Ultra RAM. - Cell('URAM288', port_attrs={'CLK': ['clkbuf_sink']}), - Cell('URAM288_BASE', port_attrs={'CLK': ['clkbuf_sink']}), - - # Multipliers and DSP. - # Cell('MULT18X18'), # Virtex 2, Spartan 3 - # Cell('MULT18X18S', port_attrs={'C': ['clkbuf_sink']}), # Spartan 3 - # Cell('MULT18X18SIO', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3E - # Cell('DSP48A', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3A DSP - # Cell('DSP48A1', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 6 - # Cell('DSP48', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 4 - Cell('DSP48E', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 5 - #Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 6 / Series 7 - Cell('DSP48E2', port_attrs={'CLK': ['clkbuf_sink']}), # Ultrascale - - # I/O logic. - # Virtex 2, Spartan 3. - # Note: these two are not officially listed in the HDL library guide, but - # they are more fundamental than OFDDR* and are necessary to construct - # differential DDR outputs (OFDDR* can only do single-ended). - Cell('FDDRCPE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}), - Cell('FDDRRSE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}), - Cell('IFDDRCPE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'D': ['iopad_external_pin']}), - Cell('IFDDRRSE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'D': ['iopad_external_pin']}), - Cell('OFDDRCPE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'Q': ['iopad_external_pin']}), - Cell('OFDDRRSE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'Q': ['iopad_external_pin']}), - Cell('OFDDRTCPE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'O': ['iopad_external_pin']}), - Cell('OFDDRTRSE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'O': ['iopad_external_pin']}), - # Spartan 3E. - Cell('IDDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}), - Cell('ODDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}), - # Virtex 4. - Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}), - Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}), - Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}), - Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}), - Cell('IDELAY', port_attrs={'C': ['clkbuf_sink']}), - Cell('ISERDES', port_attrs={ - 'CLK': ['clkbuf_sink'], - 'OCLK': ['clkbuf_sink'], - 'CLKDIV': ['clkbuf_sink'], - }), - Cell('OSERDES', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}), - # Virtex 5. - Cell('IODELAY', port_attrs={'C': ['clkbuf_sink']}), - Cell('ISERDES_NODELAY', port_attrs={ - 'CLK': ['clkbuf_sink'], - 'CLKB': ['clkbuf_sink'], - 'OCLK': ['clkbuf_sink'], - 'CLKDIV': ['clkbuf_sink'], - }), - # Virtex 6. - Cell('IODELAYE1', port_attrs={'C': ['clkbuf_sink']}), - Cell('ISERDESE1', port_attrs={ - 'CLK': ['clkbuf_sink'], - 'CLKB': ['clkbuf_sink'], - 'OCLK': ['clkbuf_sink'], - 'CLKDIV': ['clkbuf_sink'], - }), - Cell('OSERDESE1', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}), - # Series 7. - Cell('IDELAYE2', port_attrs={'C': ['clkbuf_sink']}), - Cell('ODELAYE2', port_attrs={'C': ['clkbuf_sink']}), - Cell('ISERDESE2', port_attrs={ - 'CLK': ['clkbuf_sink'], - 'CLKB': ['clkbuf_sink'], - 'OCLK': ['clkbuf_sink'], - 'OCLKB': ['clkbuf_sink'], - 'CLKDIV': ['clkbuf_sink'], - 'CLKDIVP': ['clkbuf_sink'], - }), - Cell('OSERDESE2', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}), - Cell('PHASER_IN', keep=True), - Cell('PHASER_IN_PHY', keep=True), - Cell('PHASER_OUT', keep=True), - Cell('PHASER_OUT_PHY', keep=True), - Cell('PHASER_REF', keep=True), - Cell('PHY_CONTROL', keep=True), - # Ultrascale. - Cell('IDDRE1', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}), - Cell('ODDRE1', port_attrs={'C': ['clkbuf_sink']}), - Cell('IDELAYE3', port_attrs={'CLK': ['clkbuf_sink']}), - Cell('ODELAYE3', port_attrs={'CLK': ['clkbuf_sink']}), - Cell('ISERDESE3', port_attrs={ - 'CLK': ['clkbuf_sink'], - 'CLK_B': ['clkbuf_sink'], - 'FIFO_RD_CLK': ['clkbuf_sink'], - 'CLKDIV': ['clkbuf_sink'], - }), - Cell('OSERDESE3', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}), - Cell('BITSLICE_CONTROL', keep=True), - Cell('RIU_OR', keep=True), - Cell('RX_BITSLICE'), - Cell('RXTX_BITSLICE'), - Cell('TX_BITSLICE'), - Cell('TX_BITSLICE_TRI'), - # Spartan 6. - Cell('IODELAY2', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}), - Cell('IODRP2', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}), - Cell('IODRP2_MCB', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}), - Cell('ISERDES2', port_attrs={ - 'CLK0': ['clkbuf_sink'], - 'CLK1': ['clkbuf_sink'], - 'CLKDIV': ['clkbuf_sink'], - }), - Cell('OSERDES2', port_attrs={ - 'CLK0': ['clkbuf_sink'], - 'CLK1': ['clkbuf_sink'], - 'CLKDIV': ['clkbuf_sink'], - }), - - # I/O buffers. - # Input. - # Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}), - Cell('IBUF_DLY_ADJ', port_attrs={'I': ['iopad_external_pin']}), - Cell('IBUF_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin']}), - Cell('IBUF_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin']}), - Cell('IBUF_ANALOG', port_attrs={'I': ['iopad_external_pin']}), - Cell('IBUFE3', port_attrs={'I': ['iopad_external_pin']}), - Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFDS_DLY_ADJ', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFDS_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFDS_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFDS_DIFF_OUT_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFDSE3', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFDS_DPHY', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - # Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}), - Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - # I/O. - # Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}), - Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}), - Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}), - Cell('IOBUFE3', port_attrs={'IO': ['iopad_external_pin']}), - Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), - Cell('IOBUFDS_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), - Cell('IOBUFDS_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), - Cell('IOBUFDS_DIFF_OUT', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), - Cell('IOBUFDS_DIFF_OUT_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), - Cell('IOBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), - Cell('IOBUFDSE3', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), - # Output. - # Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}), - Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), - Cell('OBUFDS_DPHY', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), - # Output + tristate. - # Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}), - Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), - # Pulls. - Cell('KEEPER'), - Cell('PULLDOWN'), - Cell('PULLUP'), - # Misc. - Cell('DCIRESET', keep=True), - Cell('HPIO_VREF', keep=True), # Ultrascale - - # Clock buffers (global). - # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}), - #Cell('BUFGCTRL', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGMUX_CTRL', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGMUX_VIRTEX4', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFG_GT', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFG_GT_SYNC'), - Cell('BUFG_PS', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGCE_DIV', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFH', port_attrs={'O': ['clkbuf_driver']}), - #Cell('BUFHCE', port_attrs={'O': ['clkbuf_driver']}), - - # Clock buffers (IO) -- Spartan 6. - Cell('BUFIO2', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}), - Cell('BUFIO2_2CLK', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}), - Cell('BUFIO2FB', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFPLL', port_attrs={'IOCLK': ['clkbuf_driver']}), - Cell('BUFPLL_MCB', port_attrs={'IOCLK0': ['clkbuf_driver'], 'IOCLK1': ['clkbuf_driver']}), - - # Clock buffers (IO and regional) -- Virtex. - Cell('BUFIO', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFIODQS', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFR', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFMR', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFMRCE', port_attrs={'O': ['clkbuf_driver']}), - - # Clock components. - # VIrtex. - # TODO: CLKDLL - # TODO: CLKDLLE - # TODO: CLKDLLHF - # Virtex 2, Spartan 3. - Cell('DCM'), - # Spartan 3E. - Cell('DCM_SP'), - # Spartan 6 (also uses DCM_SP and PLL_BASE). - Cell('DCM_CLKGEN'), - # Virtex 4/5. - Cell('DCM_ADV'), - Cell('DCM_BASE'), - Cell('DCM_PS'), - # Virtex 4. - Cell('PMCD'), - # Virtex 5. - Cell('PLL_ADV'), - Cell('PLL_BASE'), - # Virtex 6. - Cell('MMCM_ADV'), - Cell('MMCM_BASE'), - # Series 7. - Cell('MMCME2_ADV'), - Cell('MMCME2_BASE'), - Cell('PLLE2_ADV'), - Cell('PLLE2_BASE'), - # Ultrascale. - Cell('MMCME3_ADV'), - Cell('MMCME3_BASE'), - Cell('PLLE3_ADV'), - Cell('PLLE3_BASE'), - # Ultrascale+. - Cell('MMCME4_ADV'), - Cell('MMCME4_BASE'), - Cell('PLLE4_ADV'), - Cell('PLLE4_BASE'), - - # Misc stuff. - Cell('BUFT'), - # Series 7 I/O FIFOs. - Cell('IN_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - Cell('OUT_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - # Ultrascale special synchronizer register. - Cell('HARD_SYNC', port_attrs={'CLK': ['clkbuf_sink']}), - - # Singletons. - # Startup. - # TODO: STARTUP_VIRTEX - # TODO: STARTUP_VIRTEX2 - Cell('STARTUP_SPARTAN3', keep=True), - Cell('STARTUP_SPARTAN3E', keep=True), - Cell('STARTUP_SPARTAN3A', keep=True), - Cell('STARTUP_SPARTAN6', keep=True), - Cell('STARTUP_VIRTEX4', keep=True), - Cell('STARTUP_VIRTEX5', keep=True), - Cell('STARTUP_VIRTEX6', keep=True), - Cell('STARTUPE2', keep=True), # Series 7 - Cell('STARTUPE3', keep=True), # Ultrascale - # Capture trigger. - # TODO: CAPTURE_VIRTEX - # TODO: CAPTURE_VIRTEX2 - Cell('CAPTURE_SPARTAN3', keep=True), - Cell('CAPTURE_SPARTAN3A', keep=True), - Cell('CAPTURE_VIRTEX4', keep=True), - Cell('CAPTURE_VIRTEX5', keep=True), - Cell('CAPTURE_VIRTEX6', keep=True), - Cell('CAPTUREE2', keep=True), # Series 7 - # Internal Configuration Access Port. - # TODO: ICAP_VIRTEX2 - Cell('ICAP_SPARTAN3A', keep=True), - Cell('ICAP_SPARTAN6', keep=True), - Cell('ICAP_VIRTEX4', keep=True), - Cell('ICAP_VIRTEX5', keep=True), - Cell('ICAP_VIRTEX6', keep=True), - Cell('ICAPE2', keep=True), # Series 7 - Cell('ICAPE3', keep=True), # Ultrascale - # JTAG. - # TODO: BSCAN_VIRTEX - # TODO: BSCAN_VIRTEX2 - Cell('BSCAN_SPARTAN3', keep=True), - Cell('BSCAN_SPARTAN3A', keep=True), - Cell('BSCAN_SPARTAN6', keep=True), - Cell('BSCAN_VIRTEX4', keep=True), - Cell('BSCAN_VIRTEX5', keep=True), - Cell('BSCAN_VIRTEX6', keep=True), - Cell('BSCANE2', keep=True), # Series 7, Ultrascale - # DNA port. - Cell('DNA_PORT'), # Virtex 5/6, Series 7, Spartan 3A/6 - Cell('DNA_PORTE2'), # Ultrascale - # Frame ECC. - Cell('FRAME_ECC_VIRTEX4'), - Cell('FRAME_ECC_VIRTEX5'), - Cell('FRAME_ECC_VIRTEX6'), - Cell('FRAME_ECCE2'), # Series 7 - Cell('FRAME_ECCE3'), # Ultrascale - Cell('FRAME_ECCE4'), # Ultrascale+ - # AXSS command access. - Cell('USR_ACCESS_VIRTEX4'), - Cell('USR_ACCESS_VIRTEX5'), - Cell('USR_ACCESS_VIRTEX6'), - Cell('USR_ACCESSE2'), # Series 7, Ultrascale - # Misc. - Cell('POST_CRC_INTERNAL'), # Spartan 6 - Cell('SUSPEND_SYNC', keep=True), # Spartan 6 - Cell('KEY_CLEAR', keep=True), # Virtex 5 - Cell('MASTER_JTAG', keep=True), # Ultrascale - Cell('SPI_ACCESS', keep=True), # Spartan 3AN - Cell('EFUSE_USR'), - - # ADC. - Cell('SYSMON', keep=True), # Virtex 5/6 - Cell('XADC', keep=True), # Series 7 - Cell('SYSMONE1', keep=True), # Ultrascale - Cell('SYSMONE4', keep=True), # Ultrascale+ - - # Gigabit transceivers. - # Spartan 6. - Cell('GTPA1_DUAL'), - # Virtex 2 Pro. - # TODO: GT_* - # TODO: GT10_* - # Virtex 4. - Cell('GT11_CUSTOM'), - Cell('GT11_DUAL'), - Cell('GT11CLK'), - Cell('GT11CLK_MGT'), - # Virtex 5. - Cell('GTP_DUAL'), - Cell('GTX_DUAL'), - Cell('CRC32', port_attrs={'CRCCLK': ['clkbuf_sink']}), - Cell('CRC64', port_attrs={'CRCCLK': ['clkbuf_sink']}), - # Virtex 6. - Cell('GTHE1_QUAD'), - Cell('GTXE1'), - Cell('IBUFDS_GTXE1', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFDS_GTHE1', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - # Series 7. - Cell('GTHE2_CHANNEL'), - Cell('GTHE2_COMMON'), - Cell('GTPE2_CHANNEL'), - Cell('GTPE2_COMMON'), - Cell('GTXE2_CHANNEL'), - Cell('GTXE2_COMMON'), - Cell('IBUFDS_GTE2', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - # Ultrascale. - Cell('GTHE3_CHANNEL'), - Cell('GTHE3_COMMON'), - Cell('GTYE3_CHANNEL'), - Cell('GTYE3_COMMON'), - Cell('IBUFDS_GTE3', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('OBUFDS_GTE3', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), - Cell('OBUFDS_GTE3_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), - # Ultrascale+. - Cell('GTHE4_CHANNEL'), - Cell('GTHE4_COMMON'), - Cell('GTYE4_CHANNEL'), - Cell('GTYE4_COMMON'), - Cell('IBUFDS_GTE4', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('OBUFDS_GTE4', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), - Cell('OBUFDS_GTE4_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), - # Ultrascale+ GTM. - Cell('GTM_DUAL'), # not in the libraries guide - Cell('IBUFDS_GTM', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('OBUFDS_GTM', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), - Cell('OBUFDS_GTM_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), - - # High-speed ADC/DAC. - Cell('HSDAC'), # not in libraries guide - Cell('HSADC'), # not in libraries guide - Cell('RFDAC'), # not in libraries guide - Cell('RFADC'), # not in libraries guide - - # PCIE IP. - Cell('PCIE_A1'), # Spartan 6 - Cell('PCIE_EP'), # Virtex 5 - Cell('PCIE_2_0'), # Virtex 6 - Cell('PCIE_2_1'), # Series 7 - Cell('PCIE_3_0'), # Series 7 - Cell('PCIE_3_1'), # Ultrascale - Cell('PCIE40E4'), # Ultrascale+ - Cell('PCIE4CE4'), # Ultrascale+ v2 (not in the libraries guide) - - # Ethernet IP. - Cell('EMAC'), # Virtex 4 - Cell('TEMAC'), # Virtex 5 - Cell('TEMAC_SINGLE'), # Virtex 6 - Cell('CMAC'), # Ultrascale - Cell('CMACE4'), # Ultrsacale+ - - # Hard memory controllers. - Cell('MCB'), # Spartan 6 Memory Controller Block - Cell('HBM_REF_CLK', keep=True), # not in liraries guide - # not sure how the following relate to the hw - Cell('HBM_SNGLBLI_INTF_APB', keep=True), # not in liraries guide - Cell('HBM_SNGLBLI_INTF_AXI', keep=True), # not in liraries guide - Cell('HBM_ONE_STACK_INTF', keep=True), # not in liraries guide - Cell('HBM_TWO_STACK_INTF', keep=True), # not in liraries guide - - # PowerPC. - # TODO PPC405 (Virtex 2) - Cell('PPC405_ADV'), # Virtex 4 - Cell('PPC440'), # Virtex 5 - - # ARM. - Cell('PS7', keep=True), # The Zynq 7000 ARM Processor System (not in libraries guide). - Cell('PS8', keep=True), # The Zynq Ultrascale+ ARM Processor System (not in libraries guide). - - # Misc hard IP. - Cell('ILKN'), # Ultrascale Interlaken - Cell('ILKNE4'), # Ultrascale+ Interlaken - Cell('VCU', keep=True), # Zynq MPSoC Video Codec Unit (not in libraries guide). - Cell('FE'), # Zynq RFSoC Forward Error Correction (not in libraries guide). -] - - -class State(Enum): - OUTSIDE = auto() - IN_MODULE = auto() - IN_OTHER_MODULE = auto() - IN_FUNCTION = auto() - IN_TASK = auto() - -def xtract_cell_decl(cell, dirs, outf): - for dir in dirs: - for ext in ['.v', '.sv']: - fname = os.path.join(dir, cell.name + ext) - try: - with open(fname) as f: - state = State.OUTSIDE - found = False - # Probably the most horrible Verilog "parser" ever written. - module_ports = [] - invertible_ports = set() - for l in f: - l = l.partition('//')[0] - l = l.strip() - if l == 'module {}'.format(cell.name) or l.startswith('module {} '.format(cell.name)): - if found: - print('Multiple modules in {}.'.format(fname)) - sys.exit(1) - elif state != State.OUTSIDE: - print('Nested modules in {}.'.format(fname)) - sys.exit(1) - found = True - state = State.IN_MODULE - if cell.keep: - outf.write('(* keep *)\n') - outf.write('module {} (...);\n'.format(cell.name)) - elif l.startswith('module '): - if state != State.OUTSIDE: - print('Nested modules in {}.'.format(fname)) - sys.exit(1) - state = State.IN_OTHER_MODULE - elif l.startswith('task '): - if state == State.IN_MODULE: - state = State.IN_TASK - elif l.startswith('function '): - if state == State.IN_MODULE: - state = State.IN_FUNCTION - elif l == 'endtask': - if state == State.IN_TASK: - state = State.IN_MODULE - elif l == 'endfunction': - if state == State.IN_FUNCTION: - state = State.IN_MODULE - elif l == 'endmodule': - if state == State.IN_MODULE: - for kind, rng, port in module_ports: - for attr in cell.port_attrs.get(port, []): - outf.write(' (* {} *)\n'.format(attr)) - if port in invertible_ports: - outf.write(' (* invertible_pin = "IS_{}_INVERTED" *)\n'.format(port)) - if rng is None: - outf.write(' {} {};\n'.format(kind, port)) - else: - outf.write(' {} {} {};\n'.format(kind, rng, port)) - outf.write(l + '\n') - outf.write('\n') - elif state != State.IN_OTHER_MODULE: - print('endmodule in weird place in {}.'.format(cell.name, fname)) - sys.exit(1) - state = State.OUTSIDE - elif l.startswith(('input ', 'output ', 'inout ')) and state == State.IN_MODULE: - if l.endswith((';', ',')): - l = l[:-1] - if ';' in l: - print('Weird port line in {} [{}].'.format(fname, l)) - sys.exit(1) - kind, _, ports = l.partition(' ') - for port in ports.split(','): - port = port.strip() - if port.startswith('['): - rng, port = port.split() - else: - rng = None - module_ports.append((kind, rng, port)) - elif l.startswith('parameter ') and state == State.IN_MODULE: - if 'UNPLACED' in l: - continue - if l.endswith((';', ',')): - l = l[:-1] - while ' ' in l: - l = l.replace(' ', ' ') - if ';' in l: - print('Weird parameter line in {} [{}].'.format(fname, l)) - sys.exit(1) - outf.write(' {};\n'.format(l)) - match = re.search('IS_([a-zA-Z0-9_]+)_INVERTED', l) - if match: - invertible_ports.add(match[1]) - if state != State.OUTSIDE: - print('endmodule not found in {}.'.format(fname)) - sys.exit(1) - if not found: - print('Cannot find module {} in {}.'.format(cell.name, fname)) - sys.exit(1) - return - except FileNotFoundError: - continue - print('Cannot find {}.'.format(cell.name)) - sys.exit(1) - -if __name__ == '__main__': - parser = ArgumentParser(description='Extract Analog Devices blackbox cell definitions from ISE and Vivado.') - parser.add_argument('vivado_dir', nargs='?', default='/opt/Analog Devices/Vivado/2022.2') - parser.add_argument('ise_dir', nargs='?', default='/opt/Analog Devices/ISE/14.7') - args = parser.parse_args() - - dirs = [ - os.path.join(args.vivado_dir, 'data/verilog/src/xeclib'), - os.path.join(args.vivado_dir, 'data/verilog/src/unisims'), - os.path.join(args.vivado_dir, 'data/verilog/src/retarget'), - os.path.join(args.ise_dir, 'ISE_DS/ISE/verilog/xeclib/unisims'), - ] - for dir in dirs: - if not os.path.isdir(dir): - print('{} is not a directory'.format(dir)) - - out = StringIO() - for cell in CELLS: - xtract_cell_decl(cell, dirs, out) - - with open('cells_xtra.v', 'w') as f: - f.write('// Created by cells_xtra.py from Analog Devices models\n') - f.write('\n') - f.write(out.getvalue()) diff --git a/techlibs/analogdevices/cells_xtra.v b/techlibs/analogdevices/cells_xtra.v deleted file mode 100644 index d6e890751..000000000 --- a/techlibs/analogdevices/cells_xtra.v +++ /dev/null @@ -1,34016 +0,0 @@ -// Created by cells_xtra.py from Analog Devices models - -module RAMB4_S1 (...); - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [0:0] DO; - input [11:0] ADDR; - input [0:0] DI; - input EN; - (* clkbuf_sink *) - input CLK; - input WE; - input RST; -endmodule - -module RAMB4_S2 (...); - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [1:0] DO; - input [10:0] ADDR; - input [1:0] DI; - input EN; - (* clkbuf_sink *) - input CLK; - input WE; - input RST; -endmodule - -module RAMB4_S4 (...); - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [3:0] DO; - input [9:0] ADDR; - input [3:0] DI; - input EN; - (* clkbuf_sink *) - input CLK; - input WE; - input RST; -endmodule - -module RAMB4_S8 (...); - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [7:0] DO; - input [8:0] ADDR; - input [7:0] DI; - input EN; - (* clkbuf_sink *) - input CLK; - input WE; - input RST; -endmodule - -module RAMB4_S16 (...); - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [15:0] DO; - input [7:0] ADDR; - input [15:0] DI; - input EN; - (* clkbuf_sink *) - input CLK; - input WE; - input RST; -endmodule - -module RAMB4_S1_S1 (...); - parameter SIM_COLLISION_CHECK = "ALL"; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [0:0] DOA; - input [11:0] ADDRA; - input [0:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input RSTA; - output [0:0] DOB; - input [11:0] ADDRB; - input [0:0] DIB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input RSTB; -endmodule - -module RAMB4_S1_S2 (...); - parameter SIM_COLLISION_CHECK = "ALL"; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [0:0] DOA; - input [11:0] ADDRA; - input [0:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input RSTA; - output [1:0] DOB; - input [10:0] ADDRB; - input [1:0] DIB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input RSTB; -endmodule - -module RAMB4_S1_S4 (...); - parameter SIM_COLLISION_CHECK = "ALL"; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [0:0] DOA; - input [11:0] ADDRA; - input [0:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input RSTA; - output [3:0] DOB; - input [9:0] ADDRB; - input [3:0] DIB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input RSTB; -endmodule - -module RAMB4_S1_S8 (...); - parameter SIM_COLLISION_CHECK = "ALL"; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [0:0] DOA; - input [11:0] ADDRA; - input [0:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input RSTA; - output [7:0] DOB; - input [8:0] ADDRB; - input [7:0] DIB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input RSTB; -endmodule - -module RAMB4_S1_S16 (...); - parameter SIM_COLLISION_CHECK = "ALL"; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [0:0] DOA; - input [11:0] ADDRA; - input [0:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input RSTA; - output [15:0] DOB; - input [7:0] ADDRB; - input [15:0] DIB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input RSTB; -endmodule - -module RAMB4_S2_S2 (...); - parameter SIM_COLLISION_CHECK = "ALL"; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [1:0] DOA; - input [10:0] ADDRA; - input [1:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input RSTA; - output [1:0] DOB; - input [10:0] ADDRB; - input [1:0] DIB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input RSTB; -endmodule - -module RAMB4_S2_S4 (...); - parameter SIM_COLLISION_CHECK = "ALL"; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [1:0] DOA; - input [10:0] ADDRA; - input [1:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input RSTA; - output [3:0] DOB; - input [9:0] ADDRB; - input [3:0] DIB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input RSTB; -endmodule - -module RAMB4_S2_S8 (...); - parameter SIM_COLLISION_CHECK = "ALL"; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [1:0] DOA; - input [10:0] ADDRA; - input [1:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input RSTA; - output [7:0] DOB; - input [8:0] ADDRB; - input [7:0] DIB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input RSTB; -endmodule - -module RAMB4_S2_S16 (...); - parameter SIM_COLLISION_CHECK = "ALL"; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [1:0] DOA; - input [10:0] ADDRA; - input [1:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input RSTA; - output [15:0] DOB; - input [7:0] ADDRB; - input [15:0] DIB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input RSTB; -endmodule - -module RAMB4_S4_S4 (...); - parameter SIM_COLLISION_CHECK = "ALL"; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [3:0] DOA; - input [9:0] ADDRA; - input [3:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input RSTA; - output [3:0] DOB; - input [9:0] ADDRB; - input [3:0] DIB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input RSTB; -endmodule - -module RAMB4_S4_S8 (...); - parameter SIM_COLLISION_CHECK = "ALL"; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [3:0] DOA; - input [9:0] ADDRA; - input [3:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input RSTA; - output [7:0] DOB; - input [8:0] ADDRB; - input [7:0] DIB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input RSTB; -endmodule - -module RAMB4_S4_S16 (...); - parameter SIM_COLLISION_CHECK = "ALL"; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [3:0] DOA; - input [9:0] ADDRA; - input [3:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input RSTA; - output [15:0] DOB; - input [7:0] ADDRB; - input [15:0] DIB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input RSTB; -endmodule - -module RAMB4_S8_S8 (...); - parameter SIM_COLLISION_CHECK = "ALL"; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [7:0] DOA; - input [8:0] ADDRA; - input [7:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input RSTA; - output [7:0] DOB; - input [8:0] ADDRB; - input [7:0] DIB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input RSTB; -endmodule - -module RAMB4_S8_S16 (...); - parameter SIM_COLLISION_CHECK = "ALL"; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [7:0] DOA; - input [8:0] ADDRA; - input [7:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input RSTA; - output [15:0] DOB; - input [7:0] ADDRB; - input [15:0] DIB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input RSTB; -endmodule - -module RAMB4_S16_S16 (...); - parameter SIM_COLLISION_CHECK = "ALL"; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [15:0] DOA; - input [7:0] ADDRA; - input [15:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input RSTA; - output [15:0] DOB; - input [7:0] ADDRB; - input [15:0] DIB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input RSTB; -endmodule - -module RAMB16_S1 (...); - parameter [0:0] INIT = 1'h0; - parameter [0:0] SRVAL = 1'h0; - parameter WRITE_MODE = "WRITE_FIRST"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [0:0] DO; - input [13:0] ADDR; - input [0:0] DI; - input EN; - (* clkbuf_sink *) - input CLK; - input WE; - input SSR; -endmodule - -module RAMB16_S2 (...); - parameter [1:0] INIT = 2'h0; - parameter [1:0] SRVAL = 2'h0; - parameter WRITE_MODE = "WRITE_FIRST"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [1:0] DO; - input [12:0] ADDR; - input [1:0] DI; - input EN; - (* clkbuf_sink *) - input CLK; - input WE; - input SSR; -endmodule - -module RAMB16_S4 (...); - parameter [3:0] INIT = 4'h0; - parameter [3:0] SRVAL = 4'h0; - parameter WRITE_MODE = "WRITE_FIRST"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [3:0] DO; - input [11:0] ADDR; - input [3:0] DI; - input EN; - (* clkbuf_sink *) - input CLK; - input WE; - input SSR; -endmodule - -module RAMB16_S9 (...); - parameter [8:0] INIT = 9'h0; - parameter [8:0] SRVAL = 9'h0; - parameter WRITE_MODE = "WRITE_FIRST"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [7:0] DO; - output [0:0] DOP; - input [10:0] ADDR; - input [7:0] DI; - input [0:0] DIP; - input EN; - (* clkbuf_sink *) - input CLK; - input WE; - input SSR; -endmodule - -module RAMB16_S18 (...); - parameter [17:0] INIT = 18'h0; - parameter [17:0] SRVAL = 18'h0; - parameter WRITE_MODE = "WRITE_FIRST"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [15:0] DO; - output [1:0] DOP; - input [9:0] ADDR; - input [15:0] DI; - input [1:0] DIP; - input EN; - (* clkbuf_sink *) - input CLK; - input WE; - input SSR; -endmodule - -module RAMB16_S36 (...); - parameter [35:0] INIT = 36'h0; - parameter [35:0] SRVAL = 36'h0; - parameter WRITE_MODE = "WRITE_FIRST"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [31:0] DO; - output [3:0] DOP; - input [8:0] ADDR; - input [31:0] DI; - input [3:0] DIP; - input EN; - (* clkbuf_sink *) - input CLK; - input WE; - input SSR; -endmodule - -module RAMB16_S1_S1 (...); - parameter [0:0] INIT_A = 1'h0; - parameter [0:0] INIT_B = 1'h0; - parameter [0:0] SRVAL_A = 1'h0; - parameter [0:0] SRVAL_B = 1'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [0:0] DOA; - input [13:0] ADDRA; - input [0:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input SSRA; - output [0:0] DOB; - input [13:0] ADDRB; - input [0:0] DIB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input SSRB; -endmodule - -module RAMB16_S1_S2 (...); - parameter [0:0] INIT_A = 1'h0; - parameter [1:0] INIT_B = 2'h0; - parameter [0:0] SRVAL_A = 1'h0; - parameter [1:0] SRVAL_B = 2'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [0:0] DOA; - input [13:0] ADDRA; - input [0:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input SSRA; - output [1:0] DOB; - input [12:0] ADDRB; - input [1:0] DIB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input SSRB; -endmodule - -module RAMB16_S1_S4 (...); - parameter [0:0] INIT_A = 1'h0; - parameter [3:0] INIT_B = 4'h0; - parameter [0:0] SRVAL_A = 1'h0; - parameter [3:0] SRVAL_B = 4'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [0:0] DOA; - input [13:0] ADDRA; - input [0:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input SSRA; - output [3:0] DOB; - input [11:0] ADDRB; - input [3:0] DIB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input SSRB; -endmodule - -module RAMB16_S1_S9 (...); - parameter [0:0] INIT_A = 1'h0; - parameter [8:0] INIT_B = 9'h0; - parameter [0:0] SRVAL_A = 1'h0; - parameter [8:0] SRVAL_B = 9'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [0:0] DOA; - input [13:0] ADDRA; - input [0:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input SSRA; - output [7:0] DOB; - output [0:0] DOPB; - input [10:0] ADDRB; - input [7:0] DIB; - input [0:0] DIPB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input SSRB; -endmodule - -module RAMB16_S1_S18 (...); - parameter [0:0] INIT_A = 1'h0; - parameter [17:0] INIT_B = 18'h0; - parameter [0:0] SRVAL_A = 1'h0; - parameter [17:0] SRVAL_B = 18'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [0:0] DOA; - input [13:0] ADDRA; - input [0:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input SSRA; - output [15:0] DOB; - output [1:0] DOPB; - input [9:0] ADDRB; - input [15:0] DIB; - input [1:0] DIPB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input SSRB; -endmodule - -module RAMB16_S1_S36 (...); - parameter [0:0] INIT_A = 1'h0; - parameter [35:0] INIT_B = 36'h0; - parameter [0:0] SRVAL_A = 1'h0; - parameter [35:0] SRVAL_B = 36'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [0:0] DOA; - input [13:0] ADDRA; - input [0:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input SSRA; - output [31:0] DOB; - output [3:0] DOPB; - input [8:0] ADDRB; - input [31:0] DIB; - input [3:0] DIPB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input SSRB; -endmodule - -module RAMB16_S2_S2 (...); - parameter [1:0] INIT_A = 2'h0; - parameter [1:0] INIT_B = 2'h0; - parameter [1:0] SRVAL_A = 2'h0; - parameter [1:0] SRVAL_B = 2'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [1:0] DOA; - input [12:0] ADDRA; - input [1:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input SSRA; - output [1:0] DOB; - input [12:0] ADDRB; - input [1:0] DIB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input SSRB; -endmodule - -module RAMB16_S2_S4 (...); - parameter [1:0] INIT_A = 2'h0; - parameter [3:0] INIT_B = 4'h0; - parameter [1:0] SRVAL_A = 2'h0; - parameter [3:0] SRVAL_B = 4'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [1:0] DOA; - input [12:0] ADDRA; - input [1:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input SSRA; - output [3:0] DOB; - input [11:0] ADDRB; - input [3:0] DIB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input SSRB; -endmodule - -module RAMB16_S2_S9 (...); - parameter [1:0] INIT_A = 2'h0; - parameter [8:0] INIT_B = 9'h0; - parameter [1:0] SRVAL_A = 2'h0; - parameter [8:0] SRVAL_B = 9'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [1:0] DOA; - input [12:0] ADDRA; - input [1:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input SSRA; - output [7:0] DOB; - output [0:0] DOPB; - input [10:0] ADDRB; - input [7:0] DIB; - input [0:0] DIPB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input SSRB; -endmodule - -module RAMB16_S2_S18 (...); - parameter [1:0] INIT_A = 2'h0; - parameter [17:0] INIT_B = 18'h0; - parameter [1:0] SRVAL_A = 2'h0; - parameter [17:0] SRVAL_B = 18'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [1:0] DOA; - input [12:0] ADDRA; - input [1:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input SSRA; - output [15:0] DOB; - output [1:0] DOPB; - input [9:0] ADDRB; - input [15:0] DIB; - input [1:0] DIPB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input SSRB; -endmodule - -module RAMB16_S2_S36 (...); - parameter [1:0] INIT_A = 2'h0; - parameter [35:0] INIT_B = 36'h0; - parameter [1:0] SRVAL_A = 2'h0; - parameter [35:0] SRVAL_B = 36'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [1:0] DOA; - input [12:0] ADDRA; - input [1:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input SSRA; - output [31:0] DOB; - output [3:0] DOPB; - input [8:0] ADDRB; - input [31:0] DIB; - input [3:0] DIPB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input SSRB; -endmodule - -module RAMB16_S4_S4 (...); - parameter [3:0] INIT_A = 4'h0; - parameter [3:0] INIT_B = 4'h0; - parameter [3:0] SRVAL_A = 4'h0; - parameter [3:0] SRVAL_B = 4'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [3:0] DOA; - input [11:0] ADDRA; - input [3:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input SSRA; - output [3:0] DOB; - input [11:0] ADDRB; - input [3:0] DIB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input SSRB; -endmodule - -module RAMB16_S4_S9 (...); - parameter [3:0] INIT_A = 4'h0; - parameter [8:0] INIT_B = 9'h0; - parameter [3:0] SRVAL_A = 4'h0; - parameter [8:0] SRVAL_B = 9'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [3:0] DOA; - input [11:0] ADDRA; - input [3:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input SSRA; - output [7:0] DOB; - output [0:0] DOPB; - input [10:0] ADDRB; - input [7:0] DIB; - input [0:0] DIPB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input SSRB; -endmodule - -module RAMB16_S4_S18 (...); - parameter [3:0] INIT_A = 4'h0; - parameter [17:0] INIT_B = 18'h0; - parameter [3:0] SRVAL_A = 4'h0; - parameter [17:0] SRVAL_B = 18'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [3:0] DOA; - input [11:0] ADDRA; - input [3:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input SSRA; - output [15:0] DOB; - output [1:0] DOPB; - input [9:0] ADDRB; - input [15:0] DIB; - input [1:0] DIPB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input SSRB; -endmodule - -module RAMB16_S4_S36 (...); - parameter [3:0] INIT_A = 4'h0; - parameter [35:0] INIT_B = 36'h0; - parameter [3:0] SRVAL_A = 4'h0; - parameter [35:0] SRVAL_B = 36'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [3:0] DOA; - input [11:0] ADDRA; - input [3:0] DIA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input SSRA; - output [31:0] DOB; - output [3:0] DOPB; - input [8:0] ADDRB; - input [31:0] DIB; - input [3:0] DIPB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input SSRB; -endmodule - -module RAMB16_S9_S9 (...); - parameter [8:0] INIT_A = 9'h0; - parameter [8:0] INIT_B = 9'h0; - parameter [8:0] SRVAL_A = 9'h0; - parameter [8:0] SRVAL_B = 9'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [7:0] DOA; - output [0:0] DOPA; - input [10:0] ADDRA; - input [7:0] DIA; - input [0:0] DIPA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input SSRA; - output [7:0] DOB; - output [0:0] DOPB; - input [10:0] ADDRB; - input [7:0] DIB; - input [0:0] DIPB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input SSRB; -endmodule - -module RAMB16_S9_S18 (...); - parameter [8:0] INIT_A = 9'h0; - parameter [17:0] INIT_B = 18'h0; - parameter [8:0] SRVAL_A = 9'h0; - parameter [17:0] SRVAL_B = 18'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [7:0] DOA; - output [0:0] DOPA; - input [10:0] ADDRA; - input [7:0] DIA; - input [0:0] DIPA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input SSRA; - output [15:0] DOB; - output [1:0] DOPB; - input [9:0] ADDRB; - input [15:0] DIB; - input [1:0] DIPB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input SSRB; -endmodule - -module RAMB16_S9_S36 (...); - parameter [8:0] INIT_A = 9'h0; - parameter [35:0] INIT_B = 36'h0; - parameter [8:0] SRVAL_A = 9'h0; - parameter [35:0] SRVAL_B = 36'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [7:0] DOA; - output [0:0] DOPA; - input [10:0] ADDRA; - input [7:0] DIA; - input [0:0] DIPA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input SSRA; - output [31:0] DOB; - output [3:0] DOPB; - input [8:0] ADDRB; - input [31:0] DIB; - input [3:0] DIPB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input SSRB; -endmodule - -module RAMB16_S18_S18 (...); - parameter [17:0] INIT_A = 18'h0; - parameter [17:0] INIT_B = 18'h0; - parameter [17:0] SRVAL_A = 18'h0; - parameter [17:0] SRVAL_B = 18'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [15:0] DOA; - output [1:0] DOPA; - input [9:0] ADDRA; - input [15:0] DIA; - input [1:0] DIPA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input SSRA; - output [15:0] DOB; - output [1:0] DOPB; - input [9:0] ADDRB; - input [15:0] DIB; - input [1:0] DIPB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input SSRB; -endmodule - -module RAMB16_S18_S36 (...); - parameter [17:0] INIT_A = 18'h0; - parameter [35:0] INIT_B = 36'h0; - parameter [17:0] SRVAL_A = 18'h0; - parameter [35:0] SRVAL_B = 36'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [15:0] DOA; - output [1:0] DOPA; - input [9:0] ADDRA; - input [15:0] DIA; - input [1:0] DIPA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input SSRA; - output [31:0] DOB; - output [3:0] DOPB; - input [8:0] ADDRB; - input [31:0] DIB; - input [3:0] DIPB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input SSRB; -endmodule - -module RAMB16_S36_S36 (...); - parameter [35:0] INIT_A = 36'h0; - parameter [35:0] INIT_B = 36'h0; - parameter [35:0] SRVAL_A = 36'h0; - parameter [35:0] SRVAL_B = 36'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output [31:0] DOA; - output [3:0] DOPA; - input [8:0] ADDRA; - input [31:0] DIA; - input [3:0] DIPA; - input ENA; - (* clkbuf_sink *) - input CLKA; - input WEA; - input SSRA; - output [31:0] DOB; - output [3:0] DOPB; - input [8:0] ADDRB; - input [31:0] DIB; - input [3:0] DIPB; - input ENB; - (* clkbuf_sink *) - input CLKB; - input WEB; - input SSRB; -endmodule - -module RAMB16BWE_S18 (...); - parameter [17:0] INIT = 18'h0; - parameter [255:0] INITP_00 = 256'h0; - parameter [255:0] INITP_01 = 256'h0; - parameter [255:0] INITP_02 = 256'h0; - parameter [255:0] INITP_03 = 256'h0; - parameter [255:0] INITP_04 = 256'h0; - parameter [255:0] INITP_05 = 256'h0; - parameter [255:0] INITP_06 = 256'h0; - parameter [255:0] INITP_07 = 256'h0; - parameter [255:0] INIT_00 = 256'h0; - parameter [255:0] INIT_01 = 256'h0; - parameter [255:0] INIT_02 = 256'h0; - parameter [255:0] INIT_03 = 256'h0; - parameter [255:0] INIT_04 = 256'h0; - parameter [255:0] INIT_05 = 256'h0; - parameter [255:0] INIT_06 = 256'h0; - parameter [255:0] INIT_07 = 256'h0; - parameter [255:0] INIT_08 = 256'h0; - parameter [255:0] INIT_09 = 256'h0; - parameter [255:0] INIT_0A = 256'h0; - parameter [255:0] INIT_0B = 256'h0; - parameter [255:0] INIT_0C = 256'h0; - parameter [255:0] INIT_0D = 256'h0; - parameter [255:0] INIT_0E = 256'h0; - parameter [255:0] INIT_0F = 256'h0; - parameter [255:0] INIT_10 = 256'h0; - parameter [255:0] INIT_11 = 256'h0; - parameter [255:0] INIT_12 = 256'h0; - parameter [255:0] INIT_13 = 256'h0; - parameter [255:0] INIT_14 = 256'h0; - parameter [255:0] INIT_15 = 256'h0; - parameter [255:0] INIT_16 = 256'h0; - parameter [255:0] INIT_17 = 256'h0; - parameter [255:0] INIT_18 = 256'h0; - parameter [255:0] INIT_19 = 256'h0; - parameter [255:0] INIT_1A = 256'h0; - parameter [255:0] INIT_1B = 256'h0; - parameter [255:0] INIT_1C = 256'h0; - parameter [255:0] INIT_1D = 256'h0; - parameter [255:0] INIT_1E = 256'h0; - parameter [255:0] INIT_1F = 256'h0; - parameter [255:0] INIT_20 = 256'h0; - parameter [255:0] INIT_21 = 256'h0; - parameter [255:0] INIT_22 = 256'h0; - parameter [255:0] INIT_23 = 256'h0; - parameter [255:0] INIT_24 = 256'h0; - parameter [255:0] INIT_25 = 256'h0; - parameter [255:0] INIT_26 = 256'h0; - parameter [255:0] INIT_27 = 256'h0; - parameter [255:0] INIT_28 = 256'h0; - parameter [255:0] INIT_29 = 256'h0; - parameter [255:0] INIT_2A = 256'h0; - parameter [255:0] INIT_2B = 256'h0; - parameter [255:0] INIT_2C = 256'h0; - parameter [255:0] INIT_2D = 256'h0; - parameter [255:0] INIT_2E = 256'h0; - parameter [255:0] INIT_2F = 256'h0; - parameter [255:0] INIT_30 = 256'h0; - parameter [255:0] INIT_31 = 256'h0; - parameter [255:0] INIT_32 = 256'h0; - parameter [255:0] INIT_33 = 256'h0; - parameter [255:0] INIT_34 = 256'h0; - parameter [255:0] INIT_35 = 256'h0; - parameter [255:0] INIT_36 = 256'h0; - parameter [255:0] INIT_37 = 256'h0; - parameter [255:0] INIT_38 = 256'h0; - parameter [255:0] INIT_39 = 256'h0; - parameter [255:0] INIT_3A = 256'h0; - parameter [255:0] INIT_3B = 256'h0; - parameter [255:0] INIT_3C = 256'h0; - parameter [255:0] INIT_3D = 256'h0; - parameter [255:0] INIT_3E = 256'h0; - parameter [255:0] INIT_3F = 256'h0; - parameter [17:0] SRVAL = 18'h0; - parameter WRITE_MODE = "WRITE_FIRST"; - output [15:0] DO; - output [1:0] DOP; - (* clkbuf_sink *) - input CLK; - input EN; - input SSR; - input [1:0] WE; - input [15:0] DI; - input [1:0] DIP; - input [9:0] ADDR; -endmodule - -module RAMB16BWE_S36 (...); - parameter [35:0] INIT = 36'h0; - parameter [255:0] INITP_00 = 256'h0; - parameter [255:0] INITP_01 = 256'h0; - parameter [255:0] INITP_02 = 256'h0; - parameter [255:0] INITP_03 = 256'h0; - parameter [255:0] INITP_04 = 256'h0; - parameter [255:0] INITP_05 = 256'h0; - parameter [255:0] INITP_06 = 256'h0; - parameter [255:0] INITP_07 = 256'h0; - parameter [255:0] INIT_00 = 256'h0; - parameter [255:0] INIT_01 = 256'h0; - parameter [255:0] INIT_02 = 256'h0; - parameter [255:0] INIT_03 = 256'h0; - parameter [255:0] INIT_04 = 256'h0; - parameter [255:0] INIT_05 = 256'h0; - parameter [255:0] INIT_06 = 256'h0; - parameter [255:0] INIT_07 = 256'h0; - parameter [255:0] INIT_08 = 256'h0; - parameter [255:0] INIT_09 = 256'h0; - parameter [255:0] INIT_0A = 256'h0; - parameter [255:0] INIT_0B = 256'h0; - parameter [255:0] INIT_0C = 256'h0; - parameter [255:0] INIT_0D = 256'h0; - parameter [255:0] INIT_0E = 256'h0; - parameter [255:0] INIT_0F = 256'h0; - parameter [255:0] INIT_10 = 256'h0; - parameter [255:0] INIT_11 = 256'h0; - parameter [255:0] INIT_12 = 256'h0; - parameter [255:0] INIT_13 = 256'h0; - parameter [255:0] INIT_14 = 256'h0; - parameter [255:0] INIT_15 = 256'h0; - parameter [255:0] INIT_16 = 256'h0; - parameter [255:0] INIT_17 = 256'h0; - parameter [255:0] INIT_18 = 256'h0; - parameter [255:0] INIT_19 = 256'h0; - parameter [255:0] INIT_1A = 256'h0; - parameter [255:0] INIT_1B = 256'h0; - parameter [255:0] INIT_1C = 256'h0; - parameter [255:0] INIT_1D = 256'h0; - parameter [255:0] INIT_1E = 256'h0; - parameter [255:0] INIT_1F = 256'h0; - parameter [255:0] INIT_20 = 256'h0; - parameter [255:0] INIT_21 = 256'h0; - parameter [255:0] INIT_22 = 256'h0; - parameter [255:0] INIT_23 = 256'h0; - parameter [255:0] INIT_24 = 256'h0; - parameter [255:0] INIT_25 = 256'h0; - parameter [255:0] INIT_26 = 256'h0; - parameter [255:0] INIT_27 = 256'h0; - parameter [255:0] INIT_28 = 256'h0; - parameter [255:0] INIT_29 = 256'h0; - parameter [255:0] INIT_2A = 256'h0; - parameter [255:0] INIT_2B = 256'h0; - parameter [255:0] INIT_2C = 256'h0; - parameter [255:0] INIT_2D = 256'h0; - parameter [255:0] INIT_2E = 256'h0; - parameter [255:0] INIT_2F = 256'h0; - parameter [255:0] INIT_30 = 256'h0; - parameter [255:0] INIT_31 = 256'h0; - parameter [255:0] INIT_32 = 256'h0; - parameter [255:0] INIT_33 = 256'h0; - parameter [255:0] INIT_34 = 256'h0; - parameter [255:0] INIT_35 = 256'h0; - parameter [255:0] INIT_36 = 256'h0; - parameter [255:0] INIT_37 = 256'h0; - parameter [255:0] INIT_38 = 256'h0; - parameter [255:0] INIT_39 = 256'h0; - parameter [255:0] INIT_3A = 256'h0; - parameter [255:0] INIT_3B = 256'h0; - parameter [255:0] INIT_3C = 256'h0; - parameter [255:0] INIT_3D = 256'h0; - parameter [255:0] INIT_3E = 256'h0; - parameter [255:0] INIT_3F = 256'h0; - parameter [35:0] SRVAL = 36'h0; - parameter WRITE_MODE = "WRITE_FIRST"; - output [31:0] DO; - output [3:0] DOP; - (* clkbuf_sink *) - input CLK; - input EN; - input SSR; - input [3:0] WE; - input [31:0] DI; - input [3:0] DIP; - input [8:0] ADDR; -endmodule - -module RAMB16BWE_S18_S9 (...); - parameter [255:0] INITP_00 = 256'h0; - parameter [255:0] INITP_01 = 256'h0; - parameter [255:0] INITP_02 = 256'h0; - parameter [255:0] INITP_03 = 256'h0; - parameter [255:0] INITP_04 = 256'h0; - parameter [255:0] INITP_05 = 256'h0; - parameter [255:0] INITP_06 = 256'h0; - parameter [255:0] INITP_07 = 256'h0; - parameter [255:0] INIT_00 = 256'h0; - parameter [255:0] INIT_01 = 256'h0; - parameter [255:0] INIT_02 = 256'h0; - parameter [255:0] INIT_03 = 256'h0; - parameter [255:0] INIT_04 = 256'h0; - parameter [255:0] INIT_05 = 256'h0; - parameter [255:0] INIT_06 = 256'h0; - parameter [255:0] INIT_07 = 256'h0; - parameter [255:0] INIT_08 = 256'h0; - parameter [255:0] INIT_09 = 256'h0; - parameter [255:0] INIT_0A = 256'h0; - parameter [255:0] INIT_0B = 256'h0; - parameter [255:0] INIT_0C = 256'h0; - parameter [255:0] INIT_0D = 256'h0; - parameter [255:0] INIT_0E = 256'h0; - parameter [255:0] INIT_0F = 256'h0; - parameter [255:0] INIT_10 = 256'h0; - parameter [255:0] INIT_11 = 256'h0; - parameter [255:0] INIT_12 = 256'h0; - parameter [255:0] INIT_13 = 256'h0; - parameter [255:0] INIT_14 = 256'h0; - parameter [255:0] INIT_15 = 256'h0; - parameter [255:0] INIT_16 = 256'h0; - parameter [255:0] INIT_17 = 256'h0; - parameter [255:0] INIT_18 = 256'h0; - parameter [255:0] INIT_19 = 256'h0; - parameter [255:0] INIT_1A = 256'h0; - parameter [255:0] INIT_1B = 256'h0; - parameter [255:0] INIT_1C = 256'h0; - parameter [255:0] INIT_1D = 256'h0; - parameter [255:0] INIT_1E = 256'h0; - parameter [255:0] INIT_1F = 256'h0; - parameter [255:0] INIT_20 = 256'h0; - parameter [255:0] INIT_21 = 256'h0; - parameter [255:0] INIT_22 = 256'h0; - parameter [255:0] INIT_23 = 256'h0; - parameter [255:0] INIT_24 = 256'h0; - parameter [255:0] INIT_25 = 256'h0; - parameter [255:0] INIT_26 = 256'h0; - parameter [255:0] INIT_27 = 256'h0; - parameter [255:0] INIT_28 = 256'h0; - parameter [255:0] INIT_29 = 256'h0; - parameter [255:0] INIT_2A = 256'h0; - parameter [255:0] INIT_2B = 256'h0; - parameter [255:0] INIT_2C = 256'h0; - parameter [255:0] INIT_2D = 256'h0; - parameter [255:0] INIT_2E = 256'h0; - parameter [255:0] INIT_2F = 256'h0; - parameter [255:0] INIT_30 = 256'h0; - parameter [255:0] INIT_31 = 256'h0; - parameter [255:0] INIT_32 = 256'h0; - parameter [255:0] INIT_33 = 256'h0; - parameter [255:0] INIT_34 = 256'h0; - parameter [255:0] INIT_35 = 256'h0; - parameter [255:0] INIT_36 = 256'h0; - parameter [255:0] INIT_37 = 256'h0; - parameter [255:0] INIT_38 = 256'h0; - parameter [255:0] INIT_39 = 256'h0; - parameter [255:0] INIT_3A = 256'h0; - parameter [255:0] INIT_3B = 256'h0; - parameter [255:0] INIT_3C = 256'h0; - parameter [255:0] INIT_3D = 256'h0; - parameter [255:0] INIT_3E = 256'h0; - parameter [255:0] INIT_3F = 256'h0; - parameter [17:0] INIT_A = 18'h0; - parameter [8:0] INIT_B = 9'h0; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [17:0] SRVAL_A = 18'h0; - parameter [8:0] SRVAL_B = 9'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - output [15:0] DOA; - output [7:0] DOB; - output [1:0] DOPA; - output [0:0] DOPB; - (* clkbuf_sink *) - input CLKA; - (* clkbuf_sink *) - input CLKB; - input ENA; - input ENB; - input SSRA; - input SSRB; - input WEB; - input [1:0] WEA; - input [15:0] DIA; - input [7:0] DIB; - input [1:0] DIPA; - input [0:0] DIPB; - input [9:0] ADDRA; - input [10:0] ADDRB; -endmodule - -module RAMB16BWE_S18_S18 (...); - parameter [255:0] INITP_00 = 256'h0; - parameter [255:0] INITP_01 = 256'h0; - parameter [255:0] INITP_02 = 256'h0; - parameter [255:0] INITP_03 = 256'h0; - parameter [255:0] INITP_04 = 256'h0; - parameter [255:0] INITP_05 = 256'h0; - parameter [255:0] INITP_06 = 256'h0; - parameter [255:0] INITP_07 = 256'h0; - parameter [255:0] INIT_00 = 256'h0; - parameter [255:0] INIT_01 = 256'h0; - parameter [255:0] INIT_02 = 256'h0; - parameter [255:0] INIT_03 = 256'h0; - parameter [255:0] INIT_04 = 256'h0; - parameter [255:0] INIT_05 = 256'h0; - parameter [255:0] INIT_06 = 256'h0; - parameter [255:0] INIT_07 = 256'h0; - parameter [255:0] INIT_08 = 256'h0; - parameter [255:0] INIT_09 = 256'h0; - parameter [255:0] INIT_0A = 256'h0; - parameter [255:0] INIT_0B = 256'h0; - parameter [255:0] INIT_0C = 256'h0; - parameter [255:0] INIT_0D = 256'h0; - parameter [255:0] INIT_0E = 256'h0; - parameter [255:0] INIT_0F = 256'h0; - parameter [255:0] INIT_10 = 256'h0; - parameter [255:0] INIT_11 = 256'h0; - parameter [255:0] INIT_12 = 256'h0; - parameter [255:0] INIT_13 = 256'h0; - parameter [255:0] INIT_14 = 256'h0; - parameter [255:0] INIT_15 = 256'h0; - parameter [255:0] INIT_16 = 256'h0; - parameter [255:0] INIT_17 = 256'h0; - parameter [255:0] INIT_18 = 256'h0; - parameter [255:0] INIT_19 = 256'h0; - parameter [255:0] INIT_1A = 256'h0; - parameter [255:0] INIT_1B = 256'h0; - parameter [255:0] INIT_1C = 256'h0; - parameter [255:0] INIT_1D = 256'h0; - parameter [255:0] INIT_1E = 256'h0; - parameter [255:0] INIT_1F = 256'h0; - parameter [255:0] INIT_20 = 256'h0; - parameter [255:0] INIT_21 = 256'h0; - parameter [255:0] INIT_22 = 256'h0; - parameter [255:0] INIT_23 = 256'h0; - parameter [255:0] INIT_24 = 256'h0; - parameter [255:0] INIT_25 = 256'h0; - parameter [255:0] INIT_26 = 256'h0; - parameter [255:0] INIT_27 = 256'h0; - parameter [255:0] INIT_28 = 256'h0; - parameter [255:0] INIT_29 = 256'h0; - parameter [255:0] INIT_2A = 256'h0; - parameter [255:0] INIT_2B = 256'h0; - parameter [255:0] INIT_2C = 256'h0; - parameter [255:0] INIT_2D = 256'h0; - parameter [255:0] INIT_2E = 256'h0; - parameter [255:0] INIT_2F = 256'h0; - parameter [255:0] INIT_30 = 256'h0; - parameter [255:0] INIT_31 = 256'h0; - parameter [255:0] INIT_32 = 256'h0; - parameter [255:0] INIT_33 = 256'h0; - parameter [255:0] INIT_34 = 256'h0; - parameter [255:0] INIT_35 = 256'h0; - parameter [255:0] INIT_36 = 256'h0; - parameter [255:0] INIT_37 = 256'h0; - parameter [255:0] INIT_38 = 256'h0; - parameter [255:0] INIT_39 = 256'h0; - parameter [255:0] INIT_3A = 256'h0; - parameter [255:0] INIT_3B = 256'h0; - parameter [255:0] INIT_3C = 256'h0; - parameter [255:0] INIT_3D = 256'h0; - parameter [255:0] INIT_3E = 256'h0; - parameter [255:0] INIT_3F = 256'h0; - parameter [17:0] INIT_A = 18'h0; - parameter [17:0] INIT_B = 18'h0; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [17:0] SRVAL_A = 18'h0; - parameter [17:0] SRVAL_B = 18'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - output [15:0] DOA; - output [15:0] DOB; - output [1:0] DOPA; - output [1:0] DOPB; - (* clkbuf_sink *) - input CLKA; - (* clkbuf_sink *) - input CLKB; - input ENA; - input ENB; - input SSRA; - input SSRB; - input [1:0] WEB; - input [1:0] WEA; - input [15:0] DIA; - input [15:0] DIB; - input [1:0] DIPA; - input [1:0] DIPB; - input [9:0] ADDRA; - input [9:0] ADDRB; -endmodule - -module RAMB16BWE_S36_S9 (...); - parameter [255:0] INITP_00 = 256'h0; - parameter [255:0] INITP_01 = 256'h0; - parameter [255:0] INITP_02 = 256'h0; - parameter [255:0] INITP_03 = 256'h0; - parameter [255:0] INITP_04 = 256'h0; - parameter [255:0] INITP_05 = 256'h0; - parameter [255:0] INITP_06 = 256'h0; - parameter [255:0] INITP_07 = 256'h0; - parameter [255:0] INIT_00 = 256'h0; - parameter [255:0] INIT_01 = 256'h0; - parameter [255:0] INIT_02 = 256'h0; - parameter [255:0] INIT_03 = 256'h0; - parameter [255:0] INIT_04 = 256'h0; - parameter [255:0] INIT_05 = 256'h0; - parameter [255:0] INIT_06 = 256'h0; - parameter [255:0] INIT_07 = 256'h0; - parameter [255:0] INIT_08 = 256'h0; - parameter [255:0] INIT_09 = 256'h0; - parameter [255:0] INIT_0A = 256'h0; - parameter [255:0] INIT_0B = 256'h0; - parameter [255:0] INIT_0C = 256'h0; - parameter [255:0] INIT_0D = 256'h0; - parameter [255:0] INIT_0E = 256'h0; - parameter [255:0] INIT_0F = 256'h0; - parameter [255:0] INIT_10 = 256'h0; - parameter [255:0] INIT_11 = 256'h0; - parameter [255:0] INIT_12 = 256'h0; - parameter [255:0] INIT_13 = 256'h0; - parameter [255:0] INIT_14 = 256'h0; - parameter [255:0] INIT_15 = 256'h0; - parameter [255:0] INIT_16 = 256'h0; - parameter [255:0] INIT_17 = 256'h0; - parameter [255:0] INIT_18 = 256'h0; - parameter [255:0] INIT_19 = 256'h0; - parameter [255:0] INIT_1A = 256'h0; - parameter [255:0] INIT_1B = 256'h0; - parameter [255:0] INIT_1C = 256'h0; - parameter [255:0] INIT_1D = 256'h0; - parameter [255:0] INIT_1E = 256'h0; - parameter [255:0] INIT_1F = 256'h0; - parameter [255:0] INIT_20 = 256'h0; - parameter [255:0] INIT_21 = 256'h0; - parameter [255:0] INIT_22 = 256'h0; - parameter [255:0] INIT_23 = 256'h0; - parameter [255:0] INIT_24 = 256'h0; - parameter [255:0] INIT_25 = 256'h0; - parameter [255:0] INIT_26 = 256'h0; - parameter [255:0] INIT_27 = 256'h0; - parameter [255:0] INIT_28 = 256'h0; - parameter [255:0] INIT_29 = 256'h0; - parameter [255:0] INIT_2A = 256'h0; - parameter [255:0] INIT_2B = 256'h0; - parameter [255:0] INIT_2C = 256'h0; - parameter [255:0] INIT_2D = 256'h0; - parameter [255:0] INIT_2E = 256'h0; - parameter [255:0] INIT_2F = 256'h0; - parameter [255:0] INIT_30 = 256'h0; - parameter [255:0] INIT_31 = 256'h0; - parameter [255:0] INIT_32 = 256'h0; - parameter [255:0] INIT_33 = 256'h0; - parameter [255:0] INIT_34 = 256'h0; - parameter [255:0] INIT_35 = 256'h0; - parameter [255:0] INIT_36 = 256'h0; - parameter [255:0] INIT_37 = 256'h0; - parameter [255:0] INIT_38 = 256'h0; - parameter [255:0] INIT_39 = 256'h0; - parameter [255:0] INIT_3A = 256'h0; - parameter [255:0] INIT_3B = 256'h0; - parameter [255:0] INIT_3C = 256'h0; - parameter [255:0] INIT_3D = 256'h0; - parameter [255:0] INIT_3E = 256'h0; - parameter [255:0] INIT_3F = 256'h0; - parameter [35:0] INIT_A = 36'h0; - parameter [8:0] INIT_B = 9'h0; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [35:0] SRVAL_A = 36'h0; - parameter [8:0] SRVAL_B = 9'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - output [31:0] DOA; - output [3:0] DOPA; - output [7:0] DOB; - output [0:0] DOPB; - (* clkbuf_sink *) - input CLKA; - (* clkbuf_sink *) - input CLKB; - input ENA; - input ENB; - input SSRA; - input SSRB; - input [3:0] WEA; - input WEB; - input [31:0] DIA; - input [3:0] DIPA; - input [7:0] DIB; - input [0:0] DIPB; - input [8:0] ADDRA; - input [10:0] ADDRB; -endmodule - -module RAMB16BWE_S36_S18 (...); - parameter [255:0] INITP_00 = 256'h0; - parameter [255:0] INITP_01 = 256'h0; - parameter [255:0] INITP_02 = 256'h0; - parameter [255:0] INITP_03 = 256'h0; - parameter [255:0] INITP_04 = 256'h0; - parameter [255:0] INITP_05 = 256'h0; - parameter [255:0] INITP_06 = 256'h0; - parameter [255:0] INITP_07 = 256'h0; - parameter [255:0] INIT_00 = 256'h0; - parameter [255:0] INIT_01 = 256'h0; - parameter [255:0] INIT_02 = 256'h0; - parameter [255:0] INIT_03 = 256'h0; - parameter [255:0] INIT_04 = 256'h0; - parameter [255:0] INIT_05 = 256'h0; - parameter [255:0] INIT_06 = 256'h0; - parameter [255:0] INIT_07 = 256'h0; - parameter [255:0] INIT_08 = 256'h0; - parameter [255:0] INIT_09 = 256'h0; - parameter [255:0] INIT_0A = 256'h0; - parameter [255:0] INIT_0B = 256'h0; - parameter [255:0] INIT_0C = 256'h0; - parameter [255:0] INIT_0D = 256'h0; - parameter [255:0] INIT_0E = 256'h0; - parameter [255:0] INIT_0F = 256'h0; - parameter [255:0] INIT_10 = 256'h0; - parameter [255:0] INIT_11 = 256'h0; - parameter [255:0] INIT_12 = 256'h0; - parameter [255:0] INIT_13 = 256'h0; - parameter [255:0] INIT_14 = 256'h0; - parameter [255:0] INIT_15 = 256'h0; - parameter [255:0] INIT_16 = 256'h0; - parameter [255:0] INIT_17 = 256'h0; - parameter [255:0] INIT_18 = 256'h0; - parameter [255:0] INIT_19 = 256'h0; - parameter [255:0] INIT_1A = 256'h0; - parameter [255:0] INIT_1B = 256'h0; - parameter [255:0] INIT_1C = 256'h0; - parameter [255:0] INIT_1D = 256'h0; - parameter [255:0] INIT_1E = 256'h0; - parameter [255:0] INIT_1F = 256'h0; - parameter [255:0] INIT_20 = 256'h0; - parameter [255:0] INIT_21 = 256'h0; - parameter [255:0] INIT_22 = 256'h0; - parameter [255:0] INIT_23 = 256'h0; - parameter [255:0] INIT_24 = 256'h0; - parameter [255:0] INIT_25 = 256'h0; - parameter [255:0] INIT_26 = 256'h0; - parameter [255:0] INIT_27 = 256'h0; - parameter [255:0] INIT_28 = 256'h0; - parameter [255:0] INIT_29 = 256'h0; - parameter [255:0] INIT_2A = 256'h0; - parameter [255:0] INIT_2B = 256'h0; - parameter [255:0] INIT_2C = 256'h0; - parameter [255:0] INIT_2D = 256'h0; - parameter [255:0] INIT_2E = 256'h0; - parameter [255:0] INIT_2F = 256'h0; - parameter [255:0] INIT_30 = 256'h0; - parameter [255:0] INIT_31 = 256'h0; - parameter [255:0] INIT_32 = 256'h0; - parameter [255:0] INIT_33 = 256'h0; - parameter [255:0] INIT_34 = 256'h0; - parameter [255:0] INIT_35 = 256'h0; - parameter [255:0] INIT_36 = 256'h0; - parameter [255:0] INIT_37 = 256'h0; - parameter [255:0] INIT_38 = 256'h0; - parameter [255:0] INIT_39 = 256'h0; - parameter [255:0] INIT_3A = 256'h0; - parameter [255:0] INIT_3B = 256'h0; - parameter [255:0] INIT_3C = 256'h0; - parameter [255:0] INIT_3D = 256'h0; - parameter [255:0] INIT_3E = 256'h0; - parameter [255:0] INIT_3F = 256'h0; - parameter [35:0] INIT_A = 36'h0; - parameter [17:0] INIT_B = 18'h0; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [35:0] SRVAL_A = 36'h0; - parameter [17:0] SRVAL_B = 18'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - output [31:0] DOA; - output [3:0] DOPA; - output [15:0] DOB; - output [1:0] DOPB; - (* clkbuf_sink *) - input CLKA; - (* clkbuf_sink *) - input CLKB; - input ENA; - input ENB; - input SSRA; - input SSRB; - input [3:0] WEA; - input [1:0] WEB; - input [31:0] DIA; - input [3:0] DIPA; - input [15:0] DIB; - input [1:0] DIPB; - input [8:0] ADDRA; - input [9:0] ADDRB; -endmodule - -module RAMB16BWE_S36_S36 (...); - parameter [255:0] INITP_00 = 256'h0; - parameter [255:0] INITP_01 = 256'h0; - parameter [255:0] INITP_02 = 256'h0; - parameter [255:0] INITP_03 = 256'h0; - parameter [255:0] INITP_04 = 256'h0; - parameter [255:0] INITP_05 = 256'h0; - parameter [255:0] INITP_06 = 256'h0; - parameter [255:0] INITP_07 = 256'h0; - parameter [255:0] INIT_00 = 256'h0; - parameter [255:0] INIT_01 = 256'h0; - parameter [255:0] INIT_02 = 256'h0; - parameter [255:0] INIT_03 = 256'h0; - parameter [255:0] INIT_04 = 256'h0; - parameter [255:0] INIT_05 = 256'h0; - parameter [255:0] INIT_06 = 256'h0; - parameter [255:0] INIT_07 = 256'h0; - parameter [255:0] INIT_08 = 256'h0; - parameter [255:0] INIT_09 = 256'h0; - parameter [255:0] INIT_0A = 256'h0; - parameter [255:0] INIT_0B = 256'h0; - parameter [255:0] INIT_0C = 256'h0; - parameter [255:0] INIT_0D = 256'h0; - parameter [255:0] INIT_0E = 256'h0; - parameter [255:0] INIT_0F = 256'h0; - parameter [255:0] INIT_10 = 256'h0; - parameter [255:0] INIT_11 = 256'h0; - parameter [255:0] INIT_12 = 256'h0; - parameter [255:0] INIT_13 = 256'h0; - parameter [255:0] INIT_14 = 256'h0; - parameter [255:0] INIT_15 = 256'h0; - parameter [255:0] INIT_16 = 256'h0; - parameter [255:0] INIT_17 = 256'h0; - parameter [255:0] INIT_18 = 256'h0; - parameter [255:0] INIT_19 = 256'h0; - parameter [255:0] INIT_1A = 256'h0; - parameter [255:0] INIT_1B = 256'h0; - parameter [255:0] INIT_1C = 256'h0; - parameter [255:0] INIT_1D = 256'h0; - parameter [255:0] INIT_1E = 256'h0; - parameter [255:0] INIT_1F = 256'h0; - parameter [255:0] INIT_20 = 256'h0; - parameter [255:0] INIT_21 = 256'h0; - parameter [255:0] INIT_22 = 256'h0; - parameter [255:0] INIT_23 = 256'h0; - parameter [255:0] INIT_24 = 256'h0; - parameter [255:0] INIT_25 = 256'h0; - parameter [255:0] INIT_26 = 256'h0; - parameter [255:0] INIT_27 = 256'h0; - parameter [255:0] INIT_28 = 256'h0; - parameter [255:0] INIT_29 = 256'h0; - parameter [255:0] INIT_2A = 256'h0; - parameter [255:0] INIT_2B = 256'h0; - parameter [255:0] INIT_2C = 256'h0; - parameter [255:0] INIT_2D = 256'h0; - parameter [255:0] INIT_2E = 256'h0; - parameter [255:0] INIT_2F = 256'h0; - parameter [255:0] INIT_30 = 256'h0; - parameter [255:0] INIT_31 = 256'h0; - parameter [255:0] INIT_32 = 256'h0; - parameter [255:0] INIT_33 = 256'h0; - parameter [255:0] INIT_34 = 256'h0; - parameter [255:0] INIT_35 = 256'h0; - parameter [255:0] INIT_36 = 256'h0; - parameter [255:0] INIT_37 = 256'h0; - parameter [255:0] INIT_38 = 256'h0; - parameter [255:0] INIT_39 = 256'h0; - parameter [255:0] INIT_3A = 256'h0; - parameter [255:0] INIT_3B = 256'h0; - parameter [255:0] INIT_3C = 256'h0; - parameter [255:0] INIT_3D = 256'h0; - parameter [255:0] INIT_3E = 256'h0; - parameter [255:0] INIT_3F = 256'h0; - parameter [35:0] INIT_A = 36'h0; - parameter [35:0] INIT_B = 36'h0; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [35:0] SRVAL_A = 36'h0; - parameter [35:0] SRVAL_B = 36'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - output [31:0] DOA; - output [3:0] DOPA; - output [31:0] DOB; - output [3:0] DOPB; - (* clkbuf_sink *) - input CLKA; - (* clkbuf_sink *) - input CLKB; - input ENA; - input ENB; - input SSRA; - input SSRB; - input [3:0] WEA; - input [3:0] WEB; - input [31:0] DIA; - input [3:0] DIPA; - input [31:0] DIB; - input [3:0] DIPB; - input [8:0] ADDRA; - input [8:0] ADDRB; -endmodule - -module RAMB16BWER (...); - parameter integer DATA_WIDTH_A = 0; - parameter integer DATA_WIDTH_B = 0; - parameter integer DOA_REG = 0; - parameter integer DOB_REG = 0; - parameter EN_RSTRAM_A = "TRUE"; - parameter EN_RSTRAM_B = "TRUE"; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [35:0] INIT_A = 36'h0; - parameter [35:0] INIT_B = 36'h0; - parameter INIT_FILE = "NONE"; - parameter RSTTYPE = "SYNC"; - parameter RST_PRIORITY_A = "CE"; - parameter RST_PRIORITY_B = "CE"; - parameter SETUP_ALL = 1000; - parameter SETUP_READ_FIRST = 3000; - parameter SIM_DEVICE = "SPARTAN3ADSP"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [35:0] SRVAL_A = 36'h0; - parameter [35:0] SRVAL_B = 36'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - output [31:0] DOA; - output [31:0] DOB; - output [3:0] DOPA; - output [3:0] DOPB; - input [13:0] ADDRA; - input [13:0] ADDRB; - (* clkbuf_sink *) - input CLKA; - (* clkbuf_sink *) - input CLKB; - input [31:0] DIA; - input [31:0] DIB; - input [3:0] DIPA; - input [3:0] DIPB; - input ENA; - input ENB; - input REGCEA; - input REGCEB; - input RSTA; - input RSTB; - input [3:0] WEA; - input [3:0] WEB; -endmodule - -module RAMB8BWER (...); - parameter integer DATA_WIDTH_A = 0; - parameter integer DATA_WIDTH_B = 0; - parameter integer DOA_REG = 0; - parameter integer DOB_REG = 0; - parameter EN_RSTRAM_A = "TRUE"; - parameter EN_RSTRAM_B = "TRUE"; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [17:0] INIT_A = 18'h0; - parameter [17:0] INIT_B = 18'h0; - parameter INIT_FILE = "NONE"; - parameter RAM_MODE = "TDP"; - parameter RSTTYPE = "SYNC"; - parameter RST_PRIORITY_A = "CE"; - parameter RST_PRIORITY_B = "CE"; - parameter SETUP_ALL = 1000; - parameter SETUP_READ_FIRST = 3000; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [17:0] SRVAL_A = 18'h0; - parameter [17:0] SRVAL_B = 18'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - output [15:0] DOADO; - output [15:0] DOBDO; - output [1:0] DOPADOP; - output [1:0] DOPBDOP; - input [12:0] ADDRAWRADDR; - input [12:0] ADDRBRDADDR; - (* clkbuf_sink *) - input CLKAWRCLK; - (* clkbuf_sink *) - input CLKBRDCLK; - input [15:0] DIADI; - input [15:0] DIBDI; - input [1:0] DIPADIP; - input [1:0] DIPBDIP; - input ENAWREN; - input ENBRDEN; - input REGCEA; - input REGCEBREGCE; - input RSTA; - input RSTBRST; - input [1:0] WEAWEL; - input [1:0] WEBWEU; -endmodule - -module FIFO16 (...); - parameter [11:0] ALMOST_FULL_OFFSET = 12'h080; - parameter [11:0] ALMOST_EMPTY_OFFSET = 12'h080; - parameter integer DATA_WIDTH = 36; - parameter FIRST_WORD_FALL_THROUGH = "FALSE"; - output ALMOSTEMPTY; - output ALMOSTFULL; - output [31:0] DO; - output [3:0] DOP; - output EMPTY; - output FULL; - output [11:0] RDCOUNT; - output RDERR; - output [11:0] WRCOUNT; - output WRERR; - input [31:0] DI; - input [3:0] DIP; - (* clkbuf_sink *) - input RDCLK; - input RDEN; - input RST; - (* clkbuf_sink *) - input WRCLK; - input WREN; -endmodule - -module RAMB16 (...); - parameter integer DOA_REG = 0; - parameter integer DOB_REG = 0; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [35:0] INIT_A = 36'h0; - parameter [35:0] INIT_B = 36'h0; - parameter INIT_FILE = "NONE"; - parameter INVERT_CLK_DOA_REG = "FALSE"; - parameter INVERT_CLK_DOB_REG = "FALSE"; - parameter RAM_EXTENSION_A = "NONE"; - parameter RAM_EXTENSION_B = "NONE"; - parameter integer READ_WIDTH_A = 0; - parameter integer READ_WIDTH_B = 0; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter [35:0] SRVAL_A = 36'h0; - parameter [35:0] SRVAL_B = 36'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter integer WRITE_WIDTH_A = 0; - parameter integer WRITE_WIDTH_B = 0; - output CASCADEOUTA; - output CASCADEOUTB; - output [31:0] DOA; - output [31:0] DOB; - output [3:0] DOPA; - output [3:0] DOPB; - input ENA; - (* clkbuf_sink *) - input CLKA; - input SSRA; - input CASCADEINA; - input REGCEA; - input ENB; - (* clkbuf_sink *) - input CLKB; - input SSRB; - input CASCADEINB; - input REGCEB; - input [14:0] ADDRA; - input [14:0] ADDRB; - input [31:0] DIA; - input [31:0] DIB; - input [3:0] DIPA; - input [3:0] DIPB; - input [3:0] WEA; - input [3:0] WEB; -endmodule - -module RAMB32_S64_ECC (...); - parameter DO_REG = 0; - parameter SIM_COLLISION_CHECK = "ALL"; - output [1:0] STATUS; - output [63:0] DO; - (* clkbuf_sink *) - input RDCLK; - input RDEN; - input SSR; - (* clkbuf_sink *) - input WRCLK; - input WREN; - input [63:0] DI; - input [8:0] RDADDR; - input [8:0] WRADDR; -endmodule - -module FIFO18 (...); - parameter [11:0] ALMOST_EMPTY_OFFSET = 12'h080; - parameter [11:0] ALMOST_FULL_OFFSET = 12'h080; - parameter integer DATA_WIDTH = 4; - parameter integer DO_REG = 1; - parameter EN_SYN = "FALSE"; - parameter FIRST_WORD_FALL_THROUGH = "FALSE"; - parameter SIM_MODE = "SAFE"; - output ALMOSTEMPTY; - output ALMOSTFULL; - output [15:0] DO; - output [1:0] DOP; - output EMPTY; - output FULL; - output [11:0] RDCOUNT; - output RDERR; - output [11:0] WRCOUNT; - output WRERR; - input [15:0] DI; - input [1:0] DIP; - (* clkbuf_sink *) - input RDCLK; - input RDEN; - input RST; - (* clkbuf_sink *) - input WRCLK; - input WREN; -endmodule - -module FIFO18_36 (...); - parameter [8:0] ALMOST_EMPTY_OFFSET = 9'h080; - parameter [8:0] ALMOST_FULL_OFFSET = 9'h080; - parameter integer DO_REG = 1; - parameter EN_SYN = "FALSE"; - parameter FIRST_WORD_FALL_THROUGH = "FALSE"; - parameter SIM_MODE = "SAFE"; - output ALMOSTEMPTY; - output ALMOSTFULL; - output [31:0] DO; - output [3:0] DOP; - output EMPTY; - output FULL; - output [8:0] RDCOUNT; - output RDERR; - output [8:0] WRCOUNT; - output WRERR; - input [31:0] DI; - input [3:0] DIP; - (* clkbuf_sink *) - input RDCLK; - input RDEN; - input RST; - (* clkbuf_sink *) - input WRCLK; - input WREN; -endmodule - -module FIFO36 (...); - parameter [12:0] ALMOST_EMPTY_OFFSET = 13'h080; - parameter [12:0] ALMOST_FULL_OFFSET = 13'h080; - parameter integer DATA_WIDTH = 4; - parameter integer DO_REG = 1; - parameter EN_SYN = "FALSE"; - parameter FIRST_WORD_FALL_THROUGH = "FALSE"; - parameter SIM_MODE = "SAFE"; - output ALMOSTEMPTY; - output ALMOSTFULL; - output [31:0] DO; - output [3:0] DOP; - output EMPTY; - output FULL; - output [12:0] RDCOUNT; - output RDERR; - output [12:0] WRCOUNT; - output WRERR; - input [31:0] DI; - input [3:0] DIP; - (* clkbuf_sink *) - input RDCLK; - input RDEN; - input RST; - (* clkbuf_sink *) - input WRCLK; - input WREN; -endmodule - -module FIFO36_72 (...); - parameter [8:0] ALMOST_EMPTY_OFFSET = 9'h080; - parameter [8:0] ALMOST_FULL_OFFSET = 9'h080; - parameter integer DO_REG = 1; - parameter EN_ECC_WRITE = "FALSE"; - parameter EN_ECC_READ = "FALSE"; - parameter EN_SYN = "FALSE"; - parameter FIRST_WORD_FALL_THROUGH = "FALSE"; - parameter SIM_MODE = "SAFE"; - output ALMOSTEMPTY; - output ALMOSTFULL; - output DBITERR; - output [63:0] DO; - output [7:0] DOP; - output [7:0] ECCPARITY; - output EMPTY; - output FULL; - output [8:0] RDCOUNT; - output RDERR; - output SBITERR; - output [8:0] WRCOUNT; - output WRERR; - input [63:0] DI; - input [7:0] DIP; - (* clkbuf_sink *) - input RDCLK; - input RDEN; - input RST; - (* clkbuf_sink *) - input WRCLK; - input WREN; -endmodule - -module RAMB18 (...); - parameter integer DOA_REG = 0; - parameter integer DOB_REG = 0; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [17:0] INIT_A = 18'h0; - parameter [17:0] INIT_B = 18'h0; - parameter INIT_FILE = "NONE"; - parameter integer READ_WIDTH_A = 0; - parameter integer READ_WIDTH_B = 0; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter SIM_MODE = "SAFE"; - parameter [17:0] SRVAL_A = 18'h0; - parameter [17:0] SRVAL_B = 18'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter integer WRITE_WIDTH_A = 0; - parameter integer WRITE_WIDTH_B = 0; - output [15:0] DOA; - output [15:0] DOB; - output [1:0] DOPA; - output [1:0] DOPB; - input ENA; - (* clkbuf_sink *) - input CLKA; - input SSRA; - input REGCEA; - input ENB; - (* clkbuf_sink *) - input CLKB; - input SSRB; - input REGCEB; - input [13:0] ADDRA; - input [13:0] ADDRB; - input [15:0] DIA; - input [15:0] DIB; - input [1:0] DIPA; - input [1:0] DIPB; - input [1:0] WEA; - input [1:0] WEB; -endmodule - -module RAMB36 (...); - parameter integer DOA_REG = 0; - parameter integer DOB_REG = 0; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [35:0] INIT_A = 36'h0; - parameter [35:0] INIT_B = 36'h0; - parameter INIT_FILE = "NONE"; - parameter RAM_EXTENSION_A = "NONE"; - parameter RAM_EXTENSION_B = "NONE"; - parameter integer READ_WIDTH_A = 0; - parameter integer READ_WIDTH_B = 0; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter SIM_MODE = "SAFE"; - parameter [35:0] SRVAL_A = 36'h0; - parameter [35:0] SRVAL_B = 36'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter integer WRITE_WIDTH_A = 0; - parameter integer WRITE_WIDTH_B = 0; - output CASCADEOUTLATA; - output CASCADEOUTREGA; - output CASCADEOUTLATB; - output CASCADEOUTREGB; - output [31:0] DOA; - output [31:0] DOB; - output [3:0] DOPA; - output [3:0] DOPB; - input ENA; - (* clkbuf_sink *) - input CLKA; - input SSRA; - input CASCADEINLATA; - input CASCADEINREGA; - input REGCEA; - input ENB; - (* clkbuf_sink *) - input CLKB; - input SSRB; - input CASCADEINLATB; - input CASCADEINREGB; - input REGCEB; - input [15:0] ADDRA; - input [15:0] ADDRB; - input [31:0] DIA; - input [31:0] DIB; - input [3:0] DIPA; - input [3:0] DIPB; - input [3:0] WEA; - input [3:0] WEB; -endmodule - -module RAMB18SDP (...); - parameter integer DO_REG = 0; - parameter [35:0] INIT = 36'h0; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_FILE = "NONE"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter SIM_MODE = "SAFE"; - parameter [35:0] SRVAL = 36'h0; - output [31:0] DO; - output [3:0] DOP; - (* clkbuf_sink *) - input RDCLK; - input RDEN; - input REGCE; - input SSR; - (* clkbuf_sink *) - input WRCLK; - input WREN; - input [8:0] WRADDR; - input [8:0] RDADDR; - input [31:0] DI; - input [3:0] DIP; - input [3:0] WE; -endmodule - -module RAMB36SDP (...); - parameter integer DO_REG = 0; - parameter EN_ECC_READ = "FALSE"; - parameter EN_ECC_SCRUB = "FALSE"; - parameter EN_ECC_WRITE = "FALSE"; - parameter [71:0] INIT = 72'h0; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_FILE = "NONE"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter SIM_MODE = "SAFE"; - parameter [71:0] SRVAL = 72'h0; - output DBITERR; - output SBITERR; - output [63:0] DO; - output [7:0] DOP; - output [7:0] ECCPARITY; - (* clkbuf_sink *) - input RDCLK; - input RDEN; - input REGCE; - input SSR; - (* clkbuf_sink *) - input WRCLK; - input WREN; - input [8:0] WRADDR; - input [8:0] RDADDR; - input [63:0] DI; - input [7:0] DIP; - input [7:0] WE; -endmodule - -module FIFO18E1 (...); - parameter ALMOST_EMPTY_OFFSET = 13'h0080; - parameter ALMOST_FULL_OFFSET = 13'h0080; - parameter integer DATA_WIDTH = 4; - parameter integer DO_REG = 1; - parameter EN_SYN = "FALSE"; - parameter FIFO_MODE = "FIFO18"; - parameter FIRST_WORD_FALL_THROUGH = "FALSE"; - parameter INIT = 36'h0; - parameter SIM_DEVICE = "VIRTEX6"; - parameter SRVAL = 36'h0; - parameter IS_RDCLK_INVERTED = 1'b0; - parameter IS_RDEN_INVERTED = 1'b0; - parameter IS_RSTREG_INVERTED = 1'b0; - parameter IS_RST_INVERTED = 1'b0; - parameter IS_WRCLK_INVERTED = 1'b0; - parameter IS_WREN_INVERTED = 1'b0; - output ALMOSTEMPTY; - output ALMOSTFULL; - output [31:0] DO; - output [3:0] DOP; - output EMPTY; - output FULL; - output [11:0] RDCOUNT; - output RDERR; - output [11:0] WRCOUNT; - output WRERR; - input [31:0] DI; - input [3:0] DIP; - (* clkbuf_sink *) - (* invertible_pin = "IS_RDCLK_INVERTED" *) - input RDCLK; - (* invertible_pin = "IS_RDEN_INVERTED" *) - input RDEN; - input REGCE; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - (* invertible_pin = "IS_RSTREG_INVERTED" *) - input RSTREG; - (* clkbuf_sink *) - (* invertible_pin = "IS_WRCLK_INVERTED" *) - input WRCLK; - (* invertible_pin = "IS_WREN_INVERTED" *) - input WREN; -endmodule - -module FIFO36E1 (...); - parameter ALMOST_EMPTY_OFFSET = 13'h0080; - parameter ALMOST_FULL_OFFSET = 13'h0080; - parameter integer DATA_WIDTH = 4; - parameter integer DO_REG = 1; - parameter EN_ECC_READ = "FALSE"; - parameter EN_ECC_WRITE = "FALSE"; - parameter EN_SYN = "FALSE"; - parameter FIFO_MODE = "FIFO36"; - parameter FIRST_WORD_FALL_THROUGH = "FALSE"; - parameter INIT = 72'h0; - parameter SIM_DEVICE = "VIRTEX6"; - parameter SRVAL = 72'h0; - parameter IS_RDCLK_INVERTED = 1'b0; - parameter IS_RDEN_INVERTED = 1'b0; - parameter IS_RSTREG_INVERTED = 1'b0; - parameter IS_RST_INVERTED = 1'b0; - parameter IS_WRCLK_INVERTED = 1'b0; - parameter IS_WREN_INVERTED = 1'b0; - output ALMOSTEMPTY; - output ALMOSTFULL; - output DBITERR; - output [63:0] DO; - output [7:0] DOP; - output [7:0] ECCPARITY; - output EMPTY; - output FULL; - output [12:0] RDCOUNT; - output RDERR; - output SBITERR; - output [12:0] WRCOUNT; - output WRERR; - input [63:0] DI; - input [7:0] DIP; - input INJECTDBITERR; - input INJECTSBITERR; - (* clkbuf_sink *) - (* invertible_pin = "IS_RDCLK_INVERTED" *) - input RDCLK; - (* invertible_pin = "IS_RDEN_INVERTED" *) - input RDEN; - input REGCE; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - (* invertible_pin = "IS_RSTREG_INVERTED" *) - input RSTREG; - (* clkbuf_sink *) - (* invertible_pin = "IS_WRCLK_INVERTED" *) - input WRCLK; - (* invertible_pin = "IS_WREN_INVERTED" *) - input WREN; -endmodule - -module FIFO18E2 (...); - parameter CASCADE_ORDER = "NONE"; - parameter CLOCK_DOMAINS = "INDEPENDENT"; - parameter FIRST_WORD_FALL_THROUGH = "FALSE"; - parameter [35:0] INIT = 36'h000000000; - parameter [0:0] IS_RDCLK_INVERTED = 1'b0; - parameter [0:0] IS_RDEN_INVERTED = 1'b0; - parameter [0:0] IS_RSTREG_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter [0:0] IS_WRCLK_INVERTED = 1'b0; - parameter [0:0] IS_WREN_INVERTED = 1'b0; - parameter integer PROG_EMPTY_THRESH = 256; - parameter integer PROG_FULL_THRESH = 256; - parameter RDCOUNT_TYPE = "RAW_PNTR"; - parameter integer READ_WIDTH = 4; - parameter REGISTER_MODE = "UNREGISTERED"; - parameter RSTREG_PRIORITY = "RSTREG"; - parameter SLEEP_ASYNC = "FALSE"; - parameter [35:0] SRVAL = 36'h000000000; - parameter WRCOUNT_TYPE = "RAW_PNTR"; - parameter integer WRITE_WIDTH = 4; - output [31:0] CASDOUT; - output [3:0] CASDOUTP; - output CASNXTEMPTY; - output CASPRVRDEN; - output [31:0] DOUT; - output [3:0] DOUTP; - output EMPTY; - output FULL; - output PROGEMPTY; - output PROGFULL; - output [12:0] RDCOUNT; - output RDERR; - output RDRSTBUSY; - output [12:0] WRCOUNT; - output WRERR; - output WRRSTBUSY; - input [31:0] CASDIN; - input [3:0] CASDINP; - input CASDOMUX; - input CASDOMUXEN; - input CASNXTRDEN; - input CASOREGIMUX; - input CASOREGIMUXEN; - input CASPRVEMPTY; - input [31:0] DIN; - input [3:0] DINP; - (* clkbuf_sink *) - (* invertible_pin = "IS_RDCLK_INVERTED" *) - input RDCLK; - (* invertible_pin = "IS_RDEN_INVERTED" *) - input RDEN; - input REGCE; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - (* invertible_pin = "IS_RSTREG_INVERTED" *) - input RSTREG; - input SLEEP; - (* clkbuf_sink *) - (* invertible_pin = "IS_WRCLK_INVERTED" *) - input WRCLK; - (* invertible_pin = "IS_WREN_INVERTED" *) - input WREN; -endmodule - -module FIFO36E2 (...); - parameter CASCADE_ORDER = "NONE"; - parameter CLOCK_DOMAINS = "INDEPENDENT"; - parameter EN_ECC_PIPE = "FALSE"; - parameter EN_ECC_READ = "FALSE"; - parameter EN_ECC_WRITE = "FALSE"; - parameter FIRST_WORD_FALL_THROUGH = "FALSE"; - parameter [71:0] INIT = 72'h000000000000000000; - parameter [0:0] IS_RDCLK_INVERTED = 1'b0; - parameter [0:0] IS_RDEN_INVERTED = 1'b0; - parameter [0:0] IS_RSTREG_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter [0:0] IS_WRCLK_INVERTED = 1'b0; - parameter [0:0] IS_WREN_INVERTED = 1'b0; - parameter integer PROG_EMPTY_THRESH = 256; - parameter integer PROG_FULL_THRESH = 256; - parameter RDCOUNT_TYPE = "RAW_PNTR"; - parameter integer READ_WIDTH = 4; - parameter REGISTER_MODE = "UNREGISTERED"; - parameter RSTREG_PRIORITY = "RSTREG"; - parameter SLEEP_ASYNC = "FALSE"; - parameter [71:0] SRVAL = 72'h000000000000000000; - parameter WRCOUNT_TYPE = "RAW_PNTR"; - parameter integer WRITE_WIDTH = 4; - output [63:0] CASDOUT; - output [7:0] CASDOUTP; - output CASNXTEMPTY; - output CASPRVRDEN; - output DBITERR; - output [63:0] DOUT; - output [7:0] DOUTP; - output [7:0] ECCPARITY; - output EMPTY; - output FULL; - output PROGEMPTY; - output PROGFULL; - output [13:0] RDCOUNT; - output RDERR; - output RDRSTBUSY; - output SBITERR; - output [13:0] WRCOUNT; - output WRERR; - output WRRSTBUSY; - input [63:0] CASDIN; - input [7:0] CASDINP; - input CASDOMUX; - input CASDOMUXEN; - input CASNXTRDEN; - input CASOREGIMUX; - input CASOREGIMUXEN; - input CASPRVEMPTY; - input [63:0] DIN; - input [7:0] DINP; - input INJECTDBITERR; - input INJECTSBITERR; - (* clkbuf_sink *) - (* invertible_pin = "IS_RDCLK_INVERTED" *) - input RDCLK; - (* invertible_pin = "IS_RDEN_INVERTED" *) - input RDEN; - input REGCE; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - (* invertible_pin = "IS_RSTREG_INVERTED" *) - input RSTREG; - input SLEEP; - (* clkbuf_sink *) - (* invertible_pin = "IS_WRCLK_INVERTED" *) - input WRCLK; - (* invertible_pin = "IS_WREN_INVERTED" *) - input WREN; -endmodule - -module RAMB18E2 (...); - parameter CASCADE_ORDER_A = "NONE"; - parameter CASCADE_ORDER_B = "NONE"; - parameter CLOCK_DOMAINS = "INDEPENDENT"; - parameter integer DOA_REG = 1; - parameter integer DOB_REG = 1; - parameter ENADDRENA = "FALSE"; - parameter ENADDRENB = "FALSE"; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [17:0] INIT_A = 18'h00000; - parameter [17:0] INIT_B = 18'h00000; - parameter INIT_FILE = "NONE"; - parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0; - parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0; - parameter [0:0] IS_ENARDEN_INVERTED = 1'b0; - parameter [0:0] IS_ENBWREN_INVERTED = 1'b0; - parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0; - parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0; - parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0; - parameter [0:0] IS_RSTREGB_INVERTED = 1'b0; - parameter RDADDRCHANGEA = "FALSE"; - parameter RDADDRCHANGEB = "FALSE"; - parameter integer READ_WIDTH_A = 0; - parameter integer READ_WIDTH_B = 0; - parameter RSTREG_PRIORITY_A = "RSTREG"; - parameter RSTREG_PRIORITY_B = "RSTREG"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter SLEEP_ASYNC = "FALSE"; - parameter [17:0] SRVAL_A = 18'h00000; - parameter [17:0] SRVAL_B = 18'h00000; - parameter WRITE_MODE_A = "NO_CHANGE"; - parameter WRITE_MODE_B = "NO_CHANGE"; - parameter integer WRITE_WIDTH_A = 0; - parameter integer WRITE_WIDTH_B = 0; - output [15:0] CASDOUTA; - output [15:0] CASDOUTB; - output [1:0] CASDOUTPA; - output [1:0] CASDOUTPB; - output [15:0] DOUTADOUT; - output [15:0] DOUTBDOUT; - output [1:0] DOUTPADOUTP; - output [1:0] DOUTPBDOUTP; - input [13:0] ADDRARDADDR; - input [13:0] ADDRBWRADDR; - input ADDRENA; - input ADDRENB; - input CASDIMUXA; - input CASDIMUXB; - input [15:0] CASDINA; - input [15:0] CASDINB; - input [1:0] CASDINPA; - input [1:0] CASDINPB; - input CASDOMUXA; - input CASDOMUXB; - input CASDOMUXEN_A; - input CASDOMUXEN_B; - input CASOREGIMUXA; - input CASOREGIMUXB; - input CASOREGIMUXEN_A; - input CASOREGIMUXEN_B; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) - input CLKARDCLK; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) - input CLKBWRCLK; - input [15:0] DINADIN; - input [15:0] DINBDIN; - input [1:0] DINPADINP; - input [1:0] DINPBDINP; - (* invertible_pin = "IS_ENARDEN_INVERTED" *) - input ENARDEN; - (* invertible_pin = "IS_ENBWREN_INVERTED" *) - input ENBWREN; - input REGCEAREGCE; - input REGCEB; - (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) - input RSTRAMARSTRAM; - (* invertible_pin = "IS_RSTRAMB_INVERTED" *) - input RSTRAMB; - (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) - input RSTREGARSTREG; - (* invertible_pin = "IS_RSTREGB_INVERTED" *) - input RSTREGB; - input SLEEP; - input [1:0] WEA; - input [3:0] WEBWE; -endmodule - -module RAMB36E2 (...); - parameter CASCADE_ORDER_A = "NONE"; - parameter CASCADE_ORDER_B = "NONE"; - parameter CLOCK_DOMAINS = "INDEPENDENT"; - parameter integer DOA_REG = 1; - parameter integer DOB_REG = 1; - parameter ENADDRENA = "FALSE"; - parameter ENADDRENB = "FALSE"; - parameter EN_ECC_PIPE = "FALSE"; - parameter EN_ECC_READ = "FALSE"; - parameter EN_ECC_WRITE = "FALSE"; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [35:0] INIT_A = 36'h000000000; - parameter [35:0] INIT_B = 36'h000000000; - parameter INIT_FILE = "NONE"; - parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0; - parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0; - parameter [0:0] IS_ENARDEN_INVERTED = 1'b0; - parameter [0:0] IS_ENBWREN_INVERTED = 1'b0; - parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0; - parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0; - parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0; - parameter [0:0] IS_RSTREGB_INVERTED = 1'b0; - parameter RDADDRCHANGEA = "FALSE"; - parameter RDADDRCHANGEB = "FALSE"; - parameter integer READ_WIDTH_A = 0; - parameter integer READ_WIDTH_B = 0; - parameter RSTREG_PRIORITY_A = "RSTREG"; - parameter RSTREG_PRIORITY_B = "RSTREG"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter SLEEP_ASYNC = "FALSE"; - parameter [35:0] SRVAL_A = 36'h000000000; - parameter [35:0] SRVAL_B = 36'h000000000; - parameter WRITE_MODE_A = "NO_CHANGE"; - parameter WRITE_MODE_B = "NO_CHANGE"; - parameter integer WRITE_WIDTH_A = 0; - parameter integer WRITE_WIDTH_B = 0; - output [31:0] CASDOUTA; - output [31:0] CASDOUTB; - output [3:0] CASDOUTPA; - output [3:0] CASDOUTPB; - output CASOUTDBITERR; - output CASOUTSBITERR; - output DBITERR; - output [31:0] DOUTADOUT; - output [31:0] DOUTBDOUT; - output [3:0] DOUTPADOUTP; - output [3:0] DOUTPBDOUTP; - output [7:0] ECCPARITY; - output [8:0] RDADDRECC; - output SBITERR; - input [14:0] ADDRARDADDR; - input [14:0] ADDRBWRADDR; - input ADDRENA; - input ADDRENB; - input CASDIMUXA; - input CASDIMUXB; - input [31:0] CASDINA; - input [31:0] CASDINB; - input [3:0] CASDINPA; - input [3:0] CASDINPB; - input CASDOMUXA; - input CASDOMUXB; - input CASDOMUXEN_A; - input CASDOMUXEN_B; - input CASINDBITERR; - input CASINSBITERR; - input CASOREGIMUXA; - input CASOREGIMUXB; - input CASOREGIMUXEN_A; - input CASOREGIMUXEN_B; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) - input CLKARDCLK; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) - input CLKBWRCLK; - input [31:0] DINADIN; - input [31:0] DINBDIN; - input [3:0] DINPADINP; - input [3:0] DINPBDINP; - input ECCPIPECE; - (* invertible_pin = "IS_ENARDEN_INVERTED" *) - input ENARDEN; - (* invertible_pin = "IS_ENBWREN_INVERTED" *) - input ENBWREN; - input INJECTDBITERR; - input INJECTSBITERR; - input REGCEAREGCE; - input REGCEB; - (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) - input RSTRAMARSTRAM; - (* invertible_pin = "IS_RSTRAMB_INVERTED" *) - input RSTRAMB; - (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) - input RSTREGARSTREG; - (* invertible_pin = "IS_RSTREGB_INVERTED" *) - input RSTREGB; - input SLEEP; - input [3:0] WEA; - input [7:0] WEBWE; -endmodule - -module URAM288 (...); - parameter integer AUTO_SLEEP_LATENCY = 8; - parameter integer AVG_CONS_INACTIVE_CYCLES = 10; - parameter BWE_MODE_A = "PARITY_INTERLEAVED"; - parameter BWE_MODE_B = "PARITY_INTERLEAVED"; - parameter CASCADE_ORDER_A = "NONE"; - parameter CASCADE_ORDER_B = "NONE"; - parameter EN_AUTO_SLEEP_MODE = "FALSE"; - parameter EN_ECC_RD_A = "FALSE"; - parameter EN_ECC_RD_B = "FALSE"; - parameter EN_ECC_WR_A = "FALSE"; - parameter EN_ECC_WR_B = "FALSE"; - parameter IREG_PRE_A = "FALSE"; - parameter IREG_PRE_B = "FALSE"; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [0:0] IS_EN_A_INVERTED = 1'b0; - parameter [0:0] IS_EN_B_INVERTED = 1'b0; - parameter [0:0] IS_RDB_WR_A_INVERTED = 1'b0; - parameter [0:0] IS_RDB_WR_B_INVERTED = 1'b0; - parameter [0:0] IS_RST_A_INVERTED = 1'b0; - parameter [0:0] IS_RST_B_INVERTED = 1'b0; - parameter MATRIX_ID = "NONE"; - parameter integer NUM_UNIQUE_SELF_ADDR_A = 1; - parameter integer NUM_UNIQUE_SELF_ADDR_B = 1; - parameter integer NUM_URAM_IN_MATRIX = 1; - parameter OREG_A = "FALSE"; - parameter OREG_B = "FALSE"; - parameter OREG_ECC_A = "FALSE"; - parameter OREG_ECC_B = "FALSE"; - parameter REG_CAS_A = "FALSE"; - parameter REG_CAS_B = "FALSE"; - parameter RST_MODE_A = "SYNC"; - parameter RST_MODE_B = "SYNC"; - parameter [10:0] SELF_ADDR_A = 11'h000; - parameter [10:0] SELF_ADDR_B = 11'h000; - parameter [10:0] SELF_MASK_A = 11'h7FF; - parameter [10:0] SELF_MASK_B = 11'h7FF; - parameter USE_EXT_CE_A = "FALSE"; - parameter USE_EXT_CE_B = "FALSE"; - output [22:0] CAS_OUT_ADDR_A; - output [22:0] CAS_OUT_ADDR_B; - output [8:0] CAS_OUT_BWE_A; - output [8:0] CAS_OUT_BWE_B; - output CAS_OUT_DBITERR_A; - output CAS_OUT_DBITERR_B; - output [71:0] CAS_OUT_DIN_A; - output [71:0] CAS_OUT_DIN_B; - output [71:0] CAS_OUT_DOUT_A; - output [71:0] CAS_OUT_DOUT_B; - output CAS_OUT_EN_A; - output CAS_OUT_EN_B; - output CAS_OUT_RDACCESS_A; - output CAS_OUT_RDACCESS_B; - output CAS_OUT_RDB_WR_A; - output CAS_OUT_RDB_WR_B; - output CAS_OUT_SBITERR_A; - output CAS_OUT_SBITERR_B; - output DBITERR_A; - output DBITERR_B; - output [71:0] DOUT_A; - output [71:0] DOUT_B; - output RDACCESS_A; - output RDACCESS_B; - output SBITERR_A; - output SBITERR_B; - input [22:0] ADDR_A; - input [22:0] ADDR_B; - input [8:0] BWE_A; - input [8:0] BWE_B; - input [22:0] CAS_IN_ADDR_A; - input [22:0] CAS_IN_ADDR_B; - input [8:0] CAS_IN_BWE_A; - input [8:0] CAS_IN_BWE_B; - input CAS_IN_DBITERR_A; - input CAS_IN_DBITERR_B; - input [71:0] CAS_IN_DIN_A; - input [71:0] CAS_IN_DIN_B; - input [71:0] CAS_IN_DOUT_A; - input [71:0] CAS_IN_DOUT_B; - input CAS_IN_EN_A; - input CAS_IN_EN_B; - input CAS_IN_RDACCESS_A; - input CAS_IN_RDACCESS_B; - input CAS_IN_RDB_WR_A; - input CAS_IN_RDB_WR_B; - input CAS_IN_SBITERR_A; - input CAS_IN_SBITERR_B; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - input [71:0] DIN_A; - input [71:0] DIN_B; - (* invertible_pin = "IS_EN_A_INVERTED" *) - input EN_A; - (* invertible_pin = "IS_EN_B_INVERTED" *) - input EN_B; - input INJECT_DBITERR_A; - input INJECT_DBITERR_B; - input INJECT_SBITERR_A; - input INJECT_SBITERR_B; - input OREG_CE_A; - input OREG_CE_B; - input OREG_ECC_CE_A; - input OREG_ECC_CE_B; - (* invertible_pin = "IS_RDB_WR_A_INVERTED" *) - input RDB_WR_A; - (* invertible_pin = "IS_RDB_WR_B_INVERTED" *) - input RDB_WR_B; - (* invertible_pin = "IS_RST_A_INVERTED" *) - input RST_A; - (* invertible_pin = "IS_RST_B_INVERTED" *) - input RST_B; - input SLEEP; -endmodule - -module URAM288_BASE (...); - parameter integer AUTO_SLEEP_LATENCY = 8; - parameter integer AVG_CONS_INACTIVE_CYCLES = 10; - parameter BWE_MODE_A = "PARITY_INTERLEAVED"; - parameter BWE_MODE_B = "PARITY_INTERLEAVED"; - parameter EN_AUTO_SLEEP_MODE = "FALSE"; - parameter EN_ECC_RD_A = "FALSE"; - parameter EN_ECC_RD_B = "FALSE"; - parameter EN_ECC_WR_A = "FALSE"; - parameter EN_ECC_WR_B = "FALSE"; - parameter IREG_PRE_A = "FALSE"; - parameter IREG_PRE_B = "FALSE"; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [0:0] IS_EN_A_INVERTED = 1'b0; - parameter [0:0] IS_EN_B_INVERTED = 1'b0; - parameter [0:0] IS_RDB_WR_A_INVERTED = 1'b0; - parameter [0:0] IS_RDB_WR_B_INVERTED = 1'b0; - parameter [0:0] IS_RST_A_INVERTED = 1'b0; - parameter [0:0] IS_RST_B_INVERTED = 1'b0; - parameter OREG_A = "FALSE"; - parameter OREG_B = "FALSE"; - parameter OREG_ECC_A = "FALSE"; - parameter OREG_ECC_B = "FALSE"; - parameter RST_MODE_A = "SYNC"; - parameter RST_MODE_B = "SYNC"; - parameter USE_EXT_CE_A = "FALSE"; - parameter USE_EXT_CE_B = "FALSE"; - output DBITERR_A; - output DBITERR_B; - output [71:0] DOUT_A; - output [71:0] DOUT_B; - output SBITERR_A; - output SBITERR_B; - input [22:0] ADDR_A; - input [22:0] ADDR_B; - input [8:0] BWE_A; - input [8:0] BWE_B; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - input [71:0] DIN_A; - input [71:0] DIN_B; - (* invertible_pin = "IS_EN_A_INVERTED" *) - input EN_A; - (* invertible_pin = "IS_EN_B_INVERTED" *) - input EN_B; - input INJECT_DBITERR_A; - input INJECT_DBITERR_B; - input INJECT_SBITERR_A; - input INJECT_SBITERR_B; - input OREG_CE_A; - input OREG_CE_B; - input OREG_ECC_CE_A; - input OREG_ECC_CE_B; - (* invertible_pin = "IS_RDB_WR_A_INVERTED" *) - input RDB_WR_A; - (* invertible_pin = "IS_RDB_WR_B_INVERTED" *) - input RDB_WR_B; - (* invertible_pin = "IS_RST_A_INVERTED" *) - input RST_A; - (* invertible_pin = "IS_RST_B_INVERTED" *) - input RST_B; - input SLEEP; -endmodule - -module DSP48E (...); - parameter SIM_MODE = "SAFE"; - parameter integer ACASCREG = 1; - parameter integer ALUMODEREG = 1; - parameter integer AREG = 1; - parameter AUTORESET_PATTERN_DETECT = "FALSE"; - parameter AUTORESET_PATTERN_DETECT_OPTINV = "MATCH"; - parameter A_INPUT = "DIRECT"; - parameter integer BCASCREG = 1; - parameter integer BREG = 1; - parameter B_INPUT = "DIRECT"; - parameter integer CARRYINREG = 1; - parameter integer CARRYINSELREG = 1; - parameter integer CREG = 1; - parameter [47:0] MASK = 48'h3FFFFFFFFFFF; - parameter integer MREG = 1; - parameter integer MULTCARRYINREG = 1; - parameter integer OPMODEREG = 1; - parameter [47:0] PATTERN = 48'h000000000000; - parameter integer PREG = 1; - parameter SEL_MASK = "MASK"; - parameter SEL_PATTERN = "PATTERN"; - parameter SEL_ROUNDING_MASK = "SEL_MASK"; - parameter USE_MULT = "MULT_S"; - parameter USE_PATTERN_DETECT = "NO_PATDET"; - parameter USE_SIMD = "ONE48"; - output [29:0] ACOUT; - output [17:0] BCOUT; - output CARRYCASCOUT; - output [3:0] CARRYOUT; - output MULTSIGNOUT; - output OVERFLOW; - output [47:0] P; - output PATTERNBDETECT; - output PATTERNDETECT; - output [47:0] PCOUT; - output UNDERFLOW; - input [29:0] A; - input [29:0] ACIN; - input [3:0] ALUMODE; - input [17:0] B; - input [17:0] BCIN; - input [47:0] C; - input CARRYCASCIN; - input CARRYIN; - input [2:0] CARRYINSEL; - input CEA1; - input CEA2; - input CEALUMODE; - input CEB1; - input CEB2; - input CEC; - input CECARRYIN; - input CECTRL; - input CEM; - input CEMULTCARRYIN; - input CEP; - (* clkbuf_sink *) - input CLK; - input MULTSIGNIN; - input [6:0] OPMODE; - input [47:0] PCIN; - input RSTA; - input RSTALLCARRYIN; - input RSTALUMODE; - input RSTB; - input RSTC; - input RSTCTRL; - input RSTM; - input RSTP; -endmodule - -module DSP48E2 (...); - parameter integer ACASCREG = 1; - parameter integer ADREG = 1; - parameter integer ALUMODEREG = 1; - parameter AMULTSEL = "A"; - parameter integer AREG = 1; - parameter AUTORESET_PATDET = "NO_RESET"; - parameter AUTORESET_PRIORITY = "RESET"; - parameter A_INPUT = "DIRECT"; - parameter integer BCASCREG = 1; - parameter BMULTSEL = "B"; - parameter integer BREG = 1; - parameter B_INPUT = "DIRECT"; - parameter integer CARRYINREG = 1; - parameter integer CARRYINSELREG = 1; - parameter integer CREG = 1; - parameter integer DREG = 1; - parameter integer INMODEREG = 1; - parameter [3:0] IS_ALUMODE_INVERTED = 4'b0000; - parameter [0:0] IS_CARRYIN_INVERTED = 1'b0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [4:0] IS_INMODE_INVERTED = 5'b00000; - parameter [8:0] IS_OPMODE_INVERTED = 9'b000000000; - parameter [0:0] IS_RSTALLCARRYIN_INVERTED = 1'b0; - parameter [0:0] IS_RSTALUMODE_INVERTED = 1'b0; - parameter [0:0] IS_RSTA_INVERTED = 1'b0; - parameter [0:0] IS_RSTB_INVERTED = 1'b0; - parameter [0:0] IS_RSTCTRL_INVERTED = 1'b0; - parameter [0:0] IS_RSTC_INVERTED = 1'b0; - parameter [0:0] IS_RSTD_INVERTED = 1'b0; - parameter [0:0] IS_RSTINMODE_INVERTED = 1'b0; - parameter [0:0] IS_RSTM_INVERTED = 1'b0; - parameter [0:0] IS_RSTP_INVERTED = 1'b0; - parameter [47:0] MASK = 48'h3FFFFFFFFFFF; - parameter integer MREG = 1; - parameter integer OPMODEREG = 1; - parameter [47:0] PATTERN = 48'h000000000000; - parameter PREADDINSEL = "A"; - parameter integer PREG = 1; - parameter [47:0] RND = 48'h000000000000; - parameter SEL_MASK = "MASK"; - parameter SEL_PATTERN = "PATTERN"; - parameter USE_MULT = "MULTIPLY"; - parameter USE_PATTERN_DETECT = "NO_PATDET"; - parameter USE_SIMD = "ONE48"; - parameter USE_WIDEXOR = "FALSE"; - parameter XORSIMD = "XOR24_48_96"; - output [29:0] ACOUT; - output [17:0] BCOUT; - output CARRYCASCOUT; - output [3:0] CARRYOUT; - output MULTSIGNOUT; - output OVERFLOW; - output [47:0] P; - output PATTERNBDETECT; - output PATTERNDETECT; - output [47:0] PCOUT; - output UNDERFLOW; - output [7:0] XOROUT; - input [29:0] A; - input [29:0] ACIN; - (* invertible_pin = "IS_ALUMODE_INVERTED" *) - input [3:0] ALUMODE; - input [17:0] B; - input [17:0] BCIN; - input [47:0] C; - input CARRYCASCIN; - (* invertible_pin = "IS_CARRYIN_INVERTED" *) - input CARRYIN; - input [2:0] CARRYINSEL; - input CEA1; - input CEA2; - input CEAD; - input CEALUMODE; - input CEB1; - input CEB2; - input CEC; - input CECARRYIN; - input CECTRL; - input CED; - input CEINMODE; - input CEM; - input CEP; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - input [26:0] D; - (* invertible_pin = "IS_INMODE_INVERTED" *) - input [4:0] INMODE; - input MULTSIGNIN; - (* invertible_pin = "IS_OPMODE_INVERTED" *) - input [8:0] OPMODE; - input [47:0] PCIN; - (* invertible_pin = "IS_RSTA_INVERTED" *) - input RSTA; - (* invertible_pin = "IS_RSTALLCARRYIN_INVERTED" *) - input RSTALLCARRYIN; - (* invertible_pin = "IS_RSTALUMODE_INVERTED" *) - input RSTALUMODE; - (* invertible_pin = "IS_RSTB_INVERTED" *) - input RSTB; - (* invertible_pin = "IS_RSTC_INVERTED" *) - input RSTC; - (* invertible_pin = "IS_RSTCTRL_INVERTED" *) - input RSTCTRL; - (* invertible_pin = "IS_RSTD_INVERTED" *) - input RSTD; - (* invertible_pin = "IS_RSTINMODE_INVERTED" *) - input RSTINMODE; - (* invertible_pin = "IS_RSTM_INVERTED" *) - input RSTM; - (* invertible_pin = "IS_RSTP_INVERTED" *) - input RSTP; -endmodule - -module FDDRCPE (...); - parameter INIT = 1'b0; - (* clkbuf_sink *) - input C0; - (* clkbuf_sink *) - input C1; - input CE; - input D0; - input D1; - input CLR; - input PRE; - output Q; -endmodule - -module FDDRRSE (...); - parameter INIT = 1'b0; - output Q; - (* clkbuf_sink *) - input C0; - (* clkbuf_sink *) - input C1; - input CE; - input D0; - input D1; - input R; - input S; -endmodule - -module IFDDRCPE (...); - output Q0; - output Q1; - (* clkbuf_sink *) - input C0; - (* clkbuf_sink *) - input C1; - input CE; - input CLR; - (* iopad_external_pin *) - input D; - input PRE; -endmodule - -module IFDDRRSE (...); - output Q0; - output Q1; - (* clkbuf_sink *) - input C0; - (* clkbuf_sink *) - input C1; - input CE; - (* iopad_external_pin *) - input D; - input R; - input S; -endmodule - -module OFDDRCPE (...); - (* iopad_external_pin *) - output Q; - (* clkbuf_sink *) - input C0; - (* clkbuf_sink *) - input C1; - input CE; - input CLR; - input D0; - input D1; - input PRE; -endmodule - -module OFDDRRSE (...); - (* iopad_external_pin *) - output Q; - (* clkbuf_sink *) - input C0; - (* clkbuf_sink *) - input C1; - input CE; - input D0; - input D1; - input R; - input S; -endmodule - -module OFDDRTCPE (...); - (* iopad_external_pin *) - output O; - (* clkbuf_sink *) - input C0; - (* clkbuf_sink *) - input C1; - input CE; - input CLR; - input D0; - input D1; - input PRE; - input T; -endmodule - -module OFDDRTRSE (...); - (* iopad_external_pin *) - output O; - (* clkbuf_sink *) - input C0; - (* clkbuf_sink *) - input C1; - input CE; - input D0; - input D1; - input R; - input S; - input T; -endmodule - -module IDDR2 (...); - parameter DDR_ALIGNMENT = "NONE"; - parameter [0:0] INIT_Q0 = 1'b0; - parameter [0:0] INIT_Q1 = 1'b0; - parameter SRTYPE = "SYNC"; - output Q0; - output Q1; - (* clkbuf_sink *) - input C0; - (* clkbuf_sink *) - input C1; - input CE; - input D; - input R; - input S; -endmodule - -module ODDR2 (...); - parameter DDR_ALIGNMENT = "NONE"; - parameter [0:0] INIT = 1'b0; - parameter SRTYPE = "SYNC"; - output Q; - (* clkbuf_sink *) - input C0; - (* clkbuf_sink *) - input C1; - input CE; - input D0; - input D1; - input R; - input S; -endmodule - -module IDDR (...); - parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; - parameter INIT_Q1 = 1'b0; - parameter INIT_Q2 = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter SRTYPE = "SYNC"; - parameter MSGON = "TRUE"; - parameter XON = "TRUE"; - output Q1; - output Q2; - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C; - input CE; - (* invertible_pin = "IS_D_INVERTED" *) - input D; - input R; - input S; -endmodule - -module IDDR_2CLK (...); - parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; - parameter INIT_Q1 = 1'b0; - parameter INIT_Q2 = 1'b0; - parameter [0:0] IS_CB_INVERTED = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter SRTYPE = "SYNC"; - output Q1; - output Q2; - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C; - (* clkbuf_sink *) - (* invertible_pin = "IS_CB_INVERTED" *) - input CB; - input CE; - (* invertible_pin = "IS_D_INVERTED" *) - input D; - input R; - input S; -endmodule - -(* keep *) -module IDELAYCTRL (...); - parameter SIM_DEVICE = "7SERIES"; - output RDY; - (* clkbuf_sink *) - input REFCLK; - input RST; -endmodule - -module IDELAY (...); - parameter IOBDELAY_TYPE = "DEFAULT"; - parameter integer IOBDELAY_VALUE = 0; - output O; - (* clkbuf_sink *) - input C; - input CE; - input I; - input INC; - input RST; -endmodule - -module ISERDES (...); - parameter BITSLIP_ENABLE = "FALSE"; - parameter DATA_RATE = "DDR"; - parameter integer DATA_WIDTH = 4; - parameter [0:0] INIT_Q1 = 1'b0; - parameter [0:0] INIT_Q2 = 1'b0; - parameter [0:0] INIT_Q3 = 1'b0; - parameter [0:0] INIT_Q4 = 1'b0; - parameter INTERFACE_TYPE = "MEMORY"; - parameter IOBDELAY = "NONE"; - parameter IOBDELAY_TYPE = "DEFAULT"; - parameter integer IOBDELAY_VALUE = 0; - parameter integer NUM_CE = 2; - parameter SERDES_MODE = "MASTER"; - parameter integer SIM_DELAY_D = 0; - parameter integer SIM_SETUP_D_CLK = 0; - parameter integer SIM_HOLD_D_CLK = 0; - parameter [0:0] SRVAL_Q1 = 1'b0; - parameter [0:0] SRVAL_Q2 = 1'b0; - parameter [0:0] SRVAL_Q3 = 1'b0; - parameter [0:0] SRVAL_Q4 = 1'b0; - output O; - output Q1; - output Q2; - output Q3; - output Q4; - output Q5; - output Q6; - output SHIFTOUT1; - output SHIFTOUT2; - input BITSLIP; - input CE1; - input CE2; - (* clkbuf_sink *) - input CLK; - (* clkbuf_sink *) - input CLKDIV; - input D; - input DLYCE; - input DLYINC; - input DLYRST; - (* clkbuf_sink *) - input OCLK; - input REV; - input SHIFTIN1; - input SHIFTIN2; - input SR; -endmodule - -module OSERDES (...); - parameter DATA_RATE_OQ = "DDR"; - parameter DATA_RATE_TQ = "DDR"; - parameter integer DATA_WIDTH = 4; - parameter [0:0] INIT_OQ = 1'b0; - parameter [0:0] INIT_TQ = 1'b0; - parameter SERDES_MODE = "MASTER"; - parameter [0:0] SRVAL_OQ = 1'b0; - parameter [0:0] SRVAL_TQ = 1'b0; - parameter integer TRISTATE_WIDTH = 4; - output OQ; - output SHIFTOUT1; - output SHIFTOUT2; - output TQ; - (* clkbuf_sink *) - input CLK; - (* clkbuf_sink *) - input CLKDIV; - input D1; - input D2; - input D3; - input D4; - input D5; - input D6; - input OCE; - input REV; - input SHIFTIN1; - input SHIFTIN2; - input SR; - input T1; - input T2; - input T3; - input T4; - input TCE; -endmodule - -module IODELAY (...); - parameter DELAY_SRC = "I"; - parameter HIGH_PERFORMANCE_MODE = "TRUE"; - parameter IDELAY_TYPE = "DEFAULT"; - parameter integer IDELAY_VALUE = 0; - parameter integer ODELAY_VALUE = 0; - parameter real REFCLK_FREQUENCY = 200.0; - parameter SIGNAL_PATTERN = "DATA"; - output DATAOUT; - (* clkbuf_sink *) - input C; - input CE; - input DATAIN; - input IDATAIN; - input INC; - input ODATAIN; - input RST; - input T; -endmodule - -module ISERDES_NODELAY (...); - parameter BITSLIP_ENABLE = "FALSE"; - parameter DATA_RATE = "DDR"; - parameter integer DATA_WIDTH = 4; - parameter INIT_Q1 = 1'b0; - parameter INIT_Q2 = 1'b0; - parameter INIT_Q3 = 1'b0; - parameter INIT_Q4 = 1'b0; - parameter INTERFACE_TYPE = "MEMORY"; - parameter integer NUM_CE = 2; - parameter SERDES_MODE = "MASTER"; - output Q1; - output Q2; - output Q3; - output Q4; - output Q5; - output Q6; - output SHIFTOUT1; - output SHIFTOUT2; - input BITSLIP; - input CE1; - input CE2; - (* clkbuf_sink *) - input CLK; - (* clkbuf_sink *) - input CLKB; - (* clkbuf_sink *) - input CLKDIV; - input D; - (* clkbuf_sink *) - input OCLK; - input RST; - input SHIFTIN1; - input SHIFTIN2; -endmodule - -module IODELAYE1 (...); - parameter CINVCTRL_SEL = "FALSE"; - parameter DELAY_SRC = "I"; - parameter HIGH_PERFORMANCE_MODE = "FALSE"; - parameter IDELAY_TYPE = "DEFAULT"; - parameter integer IDELAY_VALUE = 0; - parameter ODELAY_TYPE = "FIXED"; - parameter integer ODELAY_VALUE = 0; - parameter real REFCLK_FREQUENCY = 200.0; - parameter SIGNAL_PATTERN = "DATA"; - output [4:0] CNTVALUEOUT; - output DATAOUT; - (* clkbuf_sink *) - input C; - input CE; - input CINVCTRL; - input CLKIN; - input [4:0] CNTVALUEIN; - input DATAIN; - input IDATAIN; - input INC; - input ODATAIN; - input RST; - input T; -endmodule - -module ISERDESE1 (...); - parameter DATA_RATE = "DDR"; - parameter integer DATA_WIDTH = 4; - parameter DYN_CLKDIV_INV_EN = "FALSE"; - parameter DYN_CLK_INV_EN = "FALSE"; - parameter [0:0] INIT_Q1 = 1'b0; - parameter [0:0] INIT_Q2 = 1'b0; - parameter [0:0] INIT_Q3 = 1'b0; - parameter [0:0] INIT_Q4 = 1'b0; - parameter INTERFACE_TYPE = "MEMORY"; - parameter integer NUM_CE = 2; - parameter IOBDELAY = "NONE"; - parameter OFB_USED = "FALSE"; - parameter SERDES_MODE = "MASTER"; - parameter [0:0] SRVAL_Q1 = 1'b0; - parameter [0:0] SRVAL_Q2 = 1'b0; - parameter [0:0] SRVAL_Q3 = 1'b0; - parameter [0:0] SRVAL_Q4 = 1'b0; - output O; - output Q1; - output Q2; - output Q3; - output Q4; - output Q5; - output Q6; - output SHIFTOUT1; - output SHIFTOUT2; - input BITSLIP; - input CE1; - input CE2; - (* clkbuf_sink *) - input CLK; - (* clkbuf_sink *) - input CLKB; - (* clkbuf_sink *) - input CLKDIV; - input D; - input DDLY; - input DYNCLKDIVSEL; - input DYNCLKSEL; - (* clkbuf_sink *) - input OCLK; - input OFB; - input RST; - input SHIFTIN1; - input SHIFTIN2; -endmodule - -module OSERDESE1 (...); - parameter DATA_RATE_OQ = "DDR"; - parameter DATA_RATE_TQ = "DDR"; - parameter integer DATA_WIDTH = 4; - parameter integer DDR3_DATA = 1; - parameter [0:0] INIT_OQ = 1'b0; - parameter [0:0] INIT_TQ = 1'b0; - parameter INTERFACE_TYPE = "DEFAULT"; - parameter integer ODELAY_USED = 0; - parameter SERDES_MODE = "MASTER"; - parameter [0:0] SRVAL_OQ = 1'b0; - parameter [0:0] SRVAL_TQ = 1'b0; - parameter integer TRISTATE_WIDTH = 4; - output OCBEXTEND; - output OFB; - output OQ; - output SHIFTOUT1; - output SHIFTOUT2; - output TFB; - output TQ; - (* clkbuf_sink *) - input CLK; - (* clkbuf_sink *) - input CLKDIV; - input CLKPERF; - input CLKPERFDELAY; - input D1; - input D2; - input D3; - input D4; - input D5; - input D6; - input OCE; - input ODV; - input RST; - input SHIFTIN1; - input SHIFTIN2; - input T1; - input T2; - input T3; - input T4; - input TCE; - input WC; -endmodule - -module IDELAYE2 (...); - parameter CINVCTRL_SEL = "FALSE"; - parameter DELAY_SRC = "IDATAIN"; - parameter HIGH_PERFORMANCE_MODE = "FALSE"; - parameter IDELAY_TYPE = "FIXED"; - parameter integer IDELAY_VALUE = 0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_DATAIN_INVERTED = 1'b0; - parameter [0:0] IS_IDATAIN_INVERTED = 1'b0; - parameter PIPE_SEL = "FALSE"; - parameter real REFCLK_FREQUENCY = 200.0; - parameter SIGNAL_PATTERN = "DATA"; - parameter integer SIM_DELAY_D = 0; - output [4:0] CNTVALUEOUT; - output DATAOUT; - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C; - input CE; - input CINVCTRL; - input [4:0] CNTVALUEIN; - (* invertible_pin = "IS_DATAIN_INVERTED" *) - input DATAIN; - (* invertible_pin = "IS_IDATAIN_INVERTED" *) - input IDATAIN; - input INC; - input LD; - input LDPIPEEN; - input REGRST; -endmodule - -module ODELAYE2 (...); - parameter CINVCTRL_SEL = "FALSE"; - parameter DELAY_SRC = "ODATAIN"; - parameter HIGH_PERFORMANCE_MODE = "FALSE"; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_ODATAIN_INVERTED = 1'b0; - parameter ODELAY_TYPE = "FIXED"; - parameter integer ODELAY_VALUE = 0; - parameter PIPE_SEL = "FALSE"; - parameter real REFCLK_FREQUENCY = 200.0; - parameter SIGNAL_PATTERN = "DATA"; - parameter integer SIM_DELAY_D = 0; - output [4:0] CNTVALUEOUT; - output DATAOUT; - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C; - input CE; - input CINVCTRL; - input CLKIN; - input [4:0] CNTVALUEIN; - input INC; - input LD; - input LDPIPEEN; - (* invertible_pin = "IS_ODATAIN_INVERTED" *) - input ODATAIN; - input REGRST; -endmodule - -module ISERDESE2 (...); - parameter DATA_RATE = "DDR"; - parameter integer DATA_WIDTH = 4; - parameter DYN_CLKDIV_INV_EN = "FALSE"; - parameter DYN_CLK_INV_EN = "FALSE"; - parameter [0:0] INIT_Q1 = 1'b0; - parameter [0:0] INIT_Q2 = 1'b0; - parameter [0:0] INIT_Q3 = 1'b0; - parameter [0:0] INIT_Q4 = 1'b0; - parameter INTERFACE_TYPE = "MEMORY"; - parameter IOBDELAY = "NONE"; - parameter [0:0] IS_CLKB_INVERTED = 1'b0; - parameter [0:0] IS_CLKDIVP_INVERTED = 1'b0; - parameter [0:0] IS_CLKDIV_INVERTED = 1'b0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_OCLKB_INVERTED = 1'b0; - parameter [0:0] IS_OCLK_INVERTED = 1'b0; - parameter integer NUM_CE = 2; - parameter OFB_USED = "FALSE"; - parameter SERDES_MODE = "MASTER"; - parameter [0:0] SRVAL_Q1 = 1'b0; - parameter [0:0] SRVAL_Q2 = 1'b0; - parameter [0:0] SRVAL_Q3 = 1'b0; - parameter [0:0] SRVAL_Q4 = 1'b0; - output O; - output Q1; - output Q2; - output Q3; - output Q4; - output Q5; - output Q6; - output Q7; - output Q8; - output SHIFTOUT1; - output SHIFTOUT2; - input BITSLIP; - input CE1; - input CE2; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKB_INVERTED" *) - input CLKB; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKDIV_INVERTED" *) - input CLKDIV; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKDIVP_INVERTED" *) - input CLKDIVP; - (* invertible_pin = "IS_D_INVERTED" *) - input D; - input DDLY; - input DYNCLKDIVSEL; - input DYNCLKSEL; - (* clkbuf_sink *) - (* invertible_pin = "IS_OCLK_INVERTED" *) - input OCLK; - (* clkbuf_sink *) - (* invertible_pin = "IS_OCLKB_INVERTED" *) - input OCLKB; - input OFB; - input RST; - input SHIFTIN1; - input SHIFTIN2; -endmodule - -(* keep *) -module PHASER_IN (...); - parameter integer CLKOUT_DIV = 4; - parameter DQS_BIAS_MODE = "FALSE"; - parameter EN_ISERDES_RST = "FALSE"; - parameter integer FINE_DELAY = 0; - parameter FREQ_REF_DIV = "NONE"; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real MEMREFCLK_PERIOD = 0.000; - parameter OUTPUT_CLK_SRC = "PHASE_REF"; - parameter real PHASEREFCLK_PERIOD = 0.000; - parameter real REFCLK_PERIOD = 0.000; - parameter integer SEL_CLK_OFFSET = 5; - parameter SYNC_IN_DIV_RST = "FALSE"; - output FINEOVERFLOW; - output ICLK; - output ICLKDIV; - output ISERDESRST; - output RCLK; - output [5:0] COUNTERREADVAL; - input COUNTERLOADEN; - input COUNTERREADEN; - input DIVIDERST; - input EDGEADV; - input FINEENABLE; - input FINEINC; - input FREQREFCLK; - input MEMREFCLK; - input PHASEREFCLK; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - input SYNCIN; - input SYSCLK; - input [1:0] RANKSEL; - input [5:0] COUNTERLOADVAL; -endmodule - -(* keep *) -module PHASER_IN_PHY (...); - parameter BURST_MODE = "FALSE"; - parameter integer CLKOUT_DIV = 4; - parameter [0:0] DQS_AUTO_RECAL = 1'b1; - parameter DQS_BIAS_MODE = "FALSE"; - parameter [2:0] DQS_FIND_PATTERN = 3'b001; - parameter integer FINE_DELAY = 0; - parameter FREQ_REF_DIV = "NONE"; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real MEMREFCLK_PERIOD = 0.000; - parameter OUTPUT_CLK_SRC = "PHASE_REF"; - parameter real PHASEREFCLK_PERIOD = 0.000; - parameter real REFCLK_PERIOD = 0.000; - parameter integer SEL_CLK_OFFSET = 5; - parameter SYNC_IN_DIV_RST = "FALSE"; - parameter WR_CYCLES = "FALSE"; - output DQSFOUND; - output DQSOUTOFRANGE; - output FINEOVERFLOW; - output ICLK; - output ICLKDIV; - output ISERDESRST; - output PHASELOCKED; - output RCLK; - output WRENABLE; - output [5:0] COUNTERREADVAL; - input BURSTPENDINGPHY; - input COUNTERLOADEN; - input COUNTERREADEN; - input FINEENABLE; - input FINEINC; - input FREQREFCLK; - input MEMREFCLK; - input PHASEREFCLK; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - input RSTDQSFIND; - input SYNCIN; - input SYSCLK; - input [1:0] ENCALIBPHY; - input [1:0] RANKSELPHY; - input [5:0] COUNTERLOADVAL; -endmodule - -(* keep *) -module PHASER_OUT (...); - parameter integer CLKOUT_DIV = 4; - parameter COARSE_BYPASS = "FALSE"; - parameter integer COARSE_DELAY = 0; - parameter EN_OSERDES_RST = "FALSE"; - parameter integer FINE_DELAY = 0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real MEMREFCLK_PERIOD = 0.000; - parameter OCLKDELAY_INV = "FALSE"; - parameter integer OCLK_DELAY = 0; - parameter OUTPUT_CLK_SRC = "PHASE_REF"; - parameter real PHASEREFCLK_PERIOD = 0.000; - parameter [2:0] PO = 3'b000; - parameter real REFCLK_PERIOD = 0.000; - parameter SYNC_IN_DIV_RST = "FALSE"; - output COARSEOVERFLOW; - output FINEOVERFLOW; - output OCLK; - output OCLKDELAYED; - output OCLKDIV; - output OSERDESRST; - output [8:0] COUNTERREADVAL; - input COARSEENABLE; - input COARSEINC; - input COUNTERLOADEN; - input COUNTERREADEN; - input DIVIDERST; - input EDGEADV; - input FINEENABLE; - input FINEINC; - input FREQREFCLK; - input MEMREFCLK; - input PHASEREFCLK; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - input SELFINEOCLKDELAY; - input SYNCIN; - input SYSCLK; - input [8:0] COUNTERLOADVAL; -endmodule - -(* keep *) -module PHASER_OUT_PHY (...); - parameter integer CLKOUT_DIV = 4; - parameter COARSE_BYPASS = "FALSE"; - parameter integer COARSE_DELAY = 0; - parameter DATA_CTL_N = "FALSE"; - parameter DATA_RD_CYCLES = "FALSE"; - parameter integer FINE_DELAY = 0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real MEMREFCLK_PERIOD = 0.000; - parameter OCLKDELAY_INV = "FALSE"; - parameter integer OCLK_DELAY = 0; - parameter OUTPUT_CLK_SRC = "PHASE_REF"; - parameter real PHASEREFCLK_PERIOD = 0.000; - parameter [2:0] PO = 3'b000; - parameter real REFCLK_PERIOD = 0.000; - parameter SYNC_IN_DIV_RST = "FALSE"; - output COARSEOVERFLOW; - output FINEOVERFLOW; - output OCLK; - output OCLKDELAYED; - output OCLKDIV; - output OSERDESRST; - output RDENABLE; - output [1:0] CTSBUS; - output [1:0] DQSBUS; - output [1:0] DTSBUS; - output [8:0] COUNTERREADVAL; - input BURSTPENDINGPHY; - input COARSEENABLE; - input COARSEINC; - input COUNTERLOADEN; - input COUNTERREADEN; - input FINEENABLE; - input FINEINC; - input FREQREFCLK; - input MEMREFCLK; - input PHASEREFCLK; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - input SELFINEOCLKDELAY; - input SYNCIN; - input SYSCLK; - input [1:0] ENCALIBPHY; - input [8:0] COUNTERLOADVAL; -endmodule - -(* keep *) -module PHASER_REF (...); - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; - output LOCKED; - input CLKIN; - (* invertible_pin = "IS_PWRDWN_INVERTED" *) - input PWRDWN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -(* keep *) -module PHY_CONTROL (...); - parameter integer AO_TOGGLE = 0; - parameter [3:0] AO_WRLVL_EN = 4'b0000; - parameter BURST_MODE = "FALSE"; - parameter integer CLK_RATIO = 1; - parameter integer CMD_OFFSET = 0; - parameter integer CO_DURATION = 0; - parameter DATA_CTL_A_N = "FALSE"; - parameter DATA_CTL_B_N = "FALSE"; - parameter DATA_CTL_C_N = "FALSE"; - parameter DATA_CTL_D_N = "FALSE"; - parameter DISABLE_SEQ_MATCH = "TRUE"; - parameter integer DI_DURATION = 0; - parameter integer DO_DURATION = 0; - parameter integer EVENTS_DELAY = 63; - parameter integer FOUR_WINDOW_CLOCKS = 63; - parameter MULTI_REGION = "FALSE"; - parameter PHY_COUNT_ENABLE = "FALSE"; - parameter integer RD_CMD_OFFSET_0 = 0; - parameter integer RD_CMD_OFFSET_1 = 00; - parameter integer RD_CMD_OFFSET_2 = 0; - parameter integer RD_CMD_OFFSET_3 = 0; - parameter integer RD_DURATION_0 = 0; - parameter integer RD_DURATION_1 = 0; - parameter integer RD_DURATION_2 = 0; - parameter integer RD_DURATION_3 = 0; - parameter SYNC_MODE = "FALSE"; - parameter integer WR_CMD_OFFSET_0 = 0; - parameter integer WR_CMD_OFFSET_1 = 0; - parameter integer WR_CMD_OFFSET_2 = 0; - parameter integer WR_CMD_OFFSET_3 = 0; - parameter integer WR_DURATION_0 = 0; - parameter integer WR_DURATION_1 = 0; - parameter integer WR_DURATION_2 = 0; - parameter integer WR_DURATION_3 = 0; - output PHYCTLALMOSTFULL; - output PHYCTLEMPTY; - output PHYCTLFULL; - output PHYCTLREADY; - output [1:0] INRANKA; - output [1:0] INRANKB; - output [1:0] INRANKC; - output [1:0] INRANKD; - output [1:0] PCENABLECALIB; - output [3:0] AUXOUTPUT; - output [3:0] INBURSTPENDING; - output [3:0] OUTBURSTPENDING; - input MEMREFCLK; - input PHYCLK; - input PHYCTLMSTREMPTY; - input PHYCTLWRENABLE; - input PLLLOCK; - input READCALIBENABLE; - input REFDLLLOCK; - input RESET; - input SYNCIN; - input WRITECALIBENABLE; - input [31:0] PHYCTLWD; -endmodule - -module IDDRE1 (...); - parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; - parameter [0:0] IS_CB_INVERTED = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - output Q1; - output Q2; - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C; - (* clkbuf_sink *) - (* invertible_pin = "IS_CB_INVERTED" *) - input CB; - input D; - input R; -endmodule - -module ODDRE1 (...); - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D1_INVERTED = 1'b0; - parameter [0:0] IS_D2_INVERTED = 1'b0; - parameter SIM_DEVICE = "ULTRASCALE"; - parameter [0:0] SRVAL = 1'b0; - output Q; - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C; - (* invertible_pin = "IS_D1_INVERTED" *) - input D1; - (* invertible_pin = "IS_D2_INVERTED" *) - input D2; - input SR; -endmodule - -module IDELAYE3 (...); - parameter CASCADE = "NONE"; - parameter DELAY_FORMAT = "TIME"; - parameter DELAY_SRC = "IDATAIN"; - parameter DELAY_TYPE = "FIXED"; - parameter integer DELAY_VALUE = 0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter LOOPBACK = "FALSE"; - parameter real REFCLK_FREQUENCY = 300.0; - parameter SIM_DEVICE = "ULTRASCALE"; - parameter real SIM_VERSION = 2.0; - parameter UPDATE_MODE = "ASYNC"; - output CASC_OUT; - output [8:0] CNTVALUEOUT; - output DATAOUT; - input CASC_IN; - input CASC_RETURN; - input CE; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - input [8:0] CNTVALUEIN; - input DATAIN; - input EN_VTC; - input IDATAIN; - input INC; - input LOAD; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module ODELAYE3 (...); - parameter CASCADE = "NONE"; - parameter DELAY_FORMAT = "TIME"; - parameter DELAY_TYPE = "FIXED"; - parameter integer DELAY_VALUE = 0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REFCLK_FREQUENCY = 300.0; - parameter SIM_DEVICE = "ULTRASCALE"; - parameter real SIM_VERSION = 2.0; - parameter UPDATE_MODE = "ASYNC"; - output CASC_OUT; - output [8:0] CNTVALUEOUT; - output DATAOUT; - input CASC_IN; - input CASC_RETURN; - input CE; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - input [8:0] CNTVALUEIN; - input EN_VTC; - input INC; - input LOAD; - input ODATAIN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module ISERDESE3 (...); - parameter integer DATA_WIDTH = 8; - parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; - parameter FIFO_ENABLE = "FALSE"; - parameter FIFO_SYNC_MODE = "FALSE"; - parameter IDDR_MODE = "FALSE"; - parameter [0:0] IS_CLK_B_INVERTED = 1'b0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter SIM_DEVICE = "ULTRASCALE"; - parameter real SIM_VERSION = 2.0; - output FIFO_EMPTY; - output INTERNAL_DIVCLK; - output [7:0] Q; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - (* clkbuf_sink *) - input CLKDIV; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_B_INVERTED" *) - input CLK_B; - input D; - (* clkbuf_sink *) - input FIFO_RD_CLK; - input FIFO_RD_EN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module OSERDESE3 (...); - parameter integer DATA_WIDTH = 8; - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_CLKDIV_INVERTED = 1'b0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter ODDR_MODE = "FALSE"; - parameter OSERDES_D_BYPASS = "FALSE"; - parameter OSERDES_T_BYPASS = "FALSE"; - parameter SIM_DEVICE = "ULTRASCALE"; - parameter real SIM_VERSION = 2.0; - output OQ; - output T_OUT; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKDIV_INVERTED" *) - input CLKDIV; - input [7:0] D; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - input T; -endmodule - -(* keep *) -module BITSLICE_CONTROL (...); - parameter CTRL_CLK = "EXTERNAL"; - parameter DIV_MODE = "DIV2"; - parameter EN_CLK_TO_EXT_NORTH = "DISABLE"; - parameter EN_CLK_TO_EXT_SOUTH = "DISABLE"; - parameter EN_DYN_ODLY_MODE = "FALSE"; - parameter EN_OTHER_NCLK = "FALSE"; - parameter EN_OTHER_PCLK = "FALSE"; - parameter IDLY_VT_TRACK = "TRUE"; - parameter INV_RXCLK = "FALSE"; - parameter ODLY_VT_TRACK = "TRUE"; - parameter QDLY_VT_TRACK = "TRUE"; - parameter [5:0] READ_IDLE_COUNT = 6'h00; - parameter REFCLK_SRC = "PLLCLK"; - parameter integer ROUNDING_FACTOR = 16; - parameter RXGATE_EXTEND = "FALSE"; - parameter RX_CLK_PHASE_N = "SHIFT_0"; - parameter RX_CLK_PHASE_P = "SHIFT_0"; - parameter RX_GATING = "DISABLE"; - parameter SELF_CALIBRATE = "ENABLE"; - parameter SERIAL_MODE = "FALSE"; - parameter SIM_DEVICE = "ULTRASCALE"; - parameter SIM_SPEEDUP = "FAST"; - parameter real SIM_VERSION = 2.0; - parameter TX_GATING = "DISABLE"; - output CLK_TO_EXT_NORTH; - output CLK_TO_EXT_SOUTH; - output DLY_RDY; - output [6:0] DYN_DCI; - output NCLK_NIBBLE_OUT; - output PCLK_NIBBLE_OUT; - output [15:0] RIU_RD_DATA; - output RIU_VALID; - output [39:0] RX_BIT_CTRL_OUT0; - output [39:0] RX_BIT_CTRL_OUT1; - output [39:0] RX_BIT_CTRL_OUT2; - output [39:0] RX_BIT_CTRL_OUT3; - output [39:0] RX_BIT_CTRL_OUT4; - output [39:0] RX_BIT_CTRL_OUT5; - output [39:0] RX_BIT_CTRL_OUT6; - output [39:0] TX_BIT_CTRL_OUT0; - output [39:0] TX_BIT_CTRL_OUT1; - output [39:0] TX_BIT_CTRL_OUT2; - output [39:0] TX_BIT_CTRL_OUT3; - output [39:0] TX_BIT_CTRL_OUT4; - output [39:0] TX_BIT_CTRL_OUT5; - output [39:0] TX_BIT_CTRL_OUT6; - output [39:0] TX_BIT_CTRL_OUT_TRI; - output VTC_RDY; - input CLK_FROM_EXT; - input EN_VTC; - input NCLK_NIBBLE_IN; - input PCLK_NIBBLE_IN; - input [3:0] PHY_RDCS0; - input [3:0] PHY_RDCS1; - input [3:0] PHY_RDEN; - input [3:0] PHY_WRCS0; - input [3:0] PHY_WRCS1; - input PLL_CLK; - input REFCLK; - input [5:0] RIU_ADDR; - input RIU_CLK; - input RIU_NIBBLE_SEL; - input [15:0] RIU_WR_DATA; - input RIU_WR_EN; - input RST; - input [39:0] RX_BIT_CTRL_IN0; - input [39:0] RX_BIT_CTRL_IN1; - input [39:0] RX_BIT_CTRL_IN2; - input [39:0] RX_BIT_CTRL_IN3; - input [39:0] RX_BIT_CTRL_IN4; - input [39:0] RX_BIT_CTRL_IN5; - input [39:0] RX_BIT_CTRL_IN6; - input [3:0] TBYTE_IN; - input [39:0] TX_BIT_CTRL_IN0; - input [39:0] TX_BIT_CTRL_IN1; - input [39:0] TX_BIT_CTRL_IN2; - input [39:0] TX_BIT_CTRL_IN3; - input [39:0] TX_BIT_CTRL_IN4; - input [39:0] TX_BIT_CTRL_IN5; - input [39:0] TX_BIT_CTRL_IN6; - input [39:0] TX_BIT_CTRL_IN_TRI; -endmodule - -(* keep *) -module RIU_OR (...); - parameter SIM_DEVICE = "ULTRASCALE"; - parameter real SIM_VERSION = 2.0; - output [15:0] RIU_RD_DATA; - output RIU_RD_VALID; - input [15:0] RIU_RD_DATA_LOW; - input [15:0] RIU_RD_DATA_UPP; - input RIU_RD_VALID_LOW; - input RIU_RD_VALID_UPP; -endmodule - -module RX_BITSLICE (...); - parameter CASCADE = "TRUE"; - parameter DATA_TYPE = "NONE"; - parameter integer DATA_WIDTH = 8; - parameter DELAY_FORMAT = "TIME"; - parameter DELAY_TYPE = "FIXED"; - parameter integer DELAY_VALUE = 0; - parameter integer DELAY_VALUE_EXT = 0; - parameter FIFO_SYNC_MODE = "FALSE"; - parameter [0:0] IS_CLK_EXT_INVERTED = 1'b0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [0:0] IS_RST_DLY_EXT_INVERTED = 1'b0; - parameter [0:0] IS_RST_DLY_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REFCLK_FREQUENCY = 300.0; - parameter SIM_DEVICE = "ULTRASCALE"; - parameter real SIM_VERSION = 2.0; - parameter UPDATE_MODE = "ASYNC"; - parameter UPDATE_MODE_EXT = "ASYNC"; - output [8:0] CNTVALUEOUT; - output [8:0] CNTVALUEOUT_EXT; - output FIFO_EMPTY; - output FIFO_WRCLK_OUT; - output [7:0] Q; - output [39:0] RX_BIT_CTRL_OUT; - output [39:0] TX_BIT_CTRL_OUT; - input CE; - input CE_EXT; - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - (* invertible_pin = "IS_CLK_EXT_INVERTED" *) - input CLK_EXT; - input [8:0] CNTVALUEIN; - input [8:0] CNTVALUEIN_EXT; - input DATAIN; - input EN_VTC; - input EN_VTC_EXT; - input FIFO_RD_CLK; - input FIFO_RD_EN; - input INC; - input INC_EXT; - input LOAD; - input LOAD_EXT; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - (* invertible_pin = "IS_RST_DLY_INVERTED" *) - input RST_DLY; - (* invertible_pin = "IS_RST_DLY_EXT_INVERTED" *) - input RST_DLY_EXT; - input [39:0] RX_BIT_CTRL_IN; - input [39:0] TX_BIT_CTRL_IN; -endmodule - -module RXTX_BITSLICE (...); - parameter FIFO_SYNC_MODE = "FALSE"; - parameter [0:0] INIT = 1'b1; - parameter [0:0] IS_RX_CLK_INVERTED = 1'b0; - parameter [0:0] IS_RX_RST_DLY_INVERTED = 1'b0; - parameter [0:0] IS_RX_RST_INVERTED = 1'b0; - parameter [0:0] IS_TX_CLK_INVERTED = 1'b0; - parameter [0:0] IS_TX_RST_DLY_INVERTED = 1'b0; - parameter [0:0] IS_TX_RST_INVERTED = 1'b0; - parameter LOOPBACK = "FALSE"; - parameter NATIVE_ODELAY_BYPASS = "FALSE"; - parameter ENABLE_PRE_EMPHASIS = "FALSE"; - parameter RX_DATA_TYPE = "NONE"; - parameter integer RX_DATA_WIDTH = 8; - parameter RX_DELAY_FORMAT = "TIME"; - parameter RX_DELAY_TYPE = "FIXED"; - parameter integer RX_DELAY_VALUE = 0; - parameter real RX_REFCLK_FREQUENCY = 300.0; - parameter RX_UPDATE_MODE = "ASYNC"; - parameter SIM_DEVICE = "ULTRASCALE"; - parameter real SIM_VERSION = 2.0; - parameter TBYTE_CTL = "TBYTE_IN"; - parameter integer TX_DATA_WIDTH = 8; - parameter TX_DELAY_FORMAT = "TIME"; - parameter TX_DELAY_TYPE = "FIXED"; - parameter integer TX_DELAY_VALUE = 0; - parameter TX_OUTPUT_PHASE_90 = "FALSE"; - parameter real TX_REFCLK_FREQUENCY = 300.0; - parameter TX_UPDATE_MODE = "ASYNC"; - output FIFO_EMPTY; - output FIFO_WRCLK_OUT; - output O; - output [7:0] Q; - output [39:0] RX_BIT_CTRL_OUT; - output [8:0] RX_CNTVALUEOUT; - output [39:0] TX_BIT_CTRL_OUT; - output [8:0] TX_CNTVALUEOUT; - output T_OUT; - input [7:0] D; - input DATAIN; - input FIFO_RD_CLK; - input FIFO_RD_EN; - input [39:0] RX_BIT_CTRL_IN; - input RX_CE; - (* invertible_pin = "IS_RX_CLK_INVERTED" *) - input RX_CLK; - input [8:0] RX_CNTVALUEIN; - input RX_EN_VTC; - input RX_INC; - input RX_LOAD; - (* invertible_pin = "IS_RX_RST_INVERTED" *) - input RX_RST; - (* invertible_pin = "IS_RX_RST_DLY_INVERTED" *) - input RX_RST_DLY; - input T; - input TBYTE_IN; - input [39:0] TX_BIT_CTRL_IN; - input TX_CE; - (* invertible_pin = "IS_TX_CLK_INVERTED" *) - input TX_CLK; - input [8:0] TX_CNTVALUEIN; - input TX_EN_VTC; - input TX_INC; - input TX_LOAD; - (* invertible_pin = "IS_TX_RST_INVERTED" *) - input TX_RST; - (* invertible_pin = "IS_TX_RST_DLY_INVERTED" *) - input TX_RST_DLY; -endmodule - -module TX_BITSLICE (...); - parameter integer DATA_WIDTH = 8; - parameter DELAY_FORMAT = "TIME"; - parameter DELAY_TYPE = "FIXED"; - parameter integer DELAY_VALUE = 0; - parameter ENABLE_PRE_EMPHASIS = "FALSE"; - parameter [0:0] INIT = 1'b1; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [0:0] IS_RST_DLY_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter NATIVE_ODELAY_BYPASS = "FALSE"; - parameter OUTPUT_PHASE_90 = "FALSE"; - parameter real REFCLK_FREQUENCY = 300.0; - parameter SIM_DEVICE = "ULTRASCALE"; - parameter real SIM_VERSION = 2.0; - parameter TBYTE_CTL = "TBYTE_IN"; - parameter UPDATE_MODE = "ASYNC"; - output [8:0] CNTVALUEOUT; - output O; - output [39:0] RX_BIT_CTRL_OUT; - output [39:0] TX_BIT_CTRL_OUT; - output T_OUT; - input CE; - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - input [8:0] CNTVALUEIN; - input [7:0] D; - input EN_VTC; - input INC; - input LOAD; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - (* invertible_pin = "IS_RST_DLY_INVERTED" *) - input RST_DLY; - input [39:0] RX_BIT_CTRL_IN; - input T; - input TBYTE_IN; - input [39:0] TX_BIT_CTRL_IN; -endmodule - -module TX_BITSLICE_TRI (...); - parameter integer DATA_WIDTH = 8; - parameter DELAY_FORMAT = "TIME"; - parameter DELAY_TYPE = "FIXED"; - parameter integer DELAY_VALUE = 0; - parameter [0:0] INIT = 1'b1; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [0:0] IS_RST_DLY_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter NATIVE_ODELAY_BYPASS = "FALSE"; - parameter OUTPUT_PHASE_90 = "FALSE"; - parameter real REFCLK_FREQUENCY = 300.0; - parameter SIM_DEVICE = "ULTRASCALE"; - parameter real SIM_VERSION = 2.0; - parameter UPDATE_MODE = "ASYNC"; - output [39:0] BIT_CTRL_OUT; - output [8:0] CNTVALUEOUT; - output TRI_OUT; - input [39:0] BIT_CTRL_IN; - input CE; - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - input [8:0] CNTVALUEIN; - input EN_VTC; - input INC; - input LOAD; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - (* invertible_pin = "IS_RST_DLY_INVERTED" *) - input RST_DLY; -endmodule - -module IODELAY2 (...); - parameter COUNTER_WRAPAROUND = "WRAPAROUND"; - parameter DATA_RATE = "SDR"; - parameter DELAY_SRC = "IO"; - parameter integer IDELAY2_VALUE = 0; - parameter IDELAY_MODE = "NORMAL"; - parameter IDELAY_TYPE = "DEFAULT"; - parameter integer IDELAY_VALUE = 0; - parameter integer ODELAY_VALUE = 0; - parameter SERDES_MODE = "NONE"; - parameter integer SIM_TAPDELAY_VALUE = 75; - output BUSY; - output DATAOUT2; - output DATAOUT; - output DOUT; - output TOUT; - input CAL; - input CE; - (* clkbuf_sink *) - input CLK; - input IDATAIN; - input INC; - (* clkbuf_sink *) - input IOCLK0; - (* clkbuf_sink *) - input IOCLK1; - input ODATAIN; - input RST; - input T; -endmodule - -module IODRP2 (...); - parameter DATA_RATE = "SDR"; - parameter integer SIM_TAPDELAY_VALUE = 75; - output DATAOUT2; - output DATAOUT; - output DOUT; - output SDO; - output TOUT; - input ADD; - input BKST; - (* clkbuf_sink *) - input CLK; - input CS; - input IDATAIN; - (* clkbuf_sink *) - input IOCLK0; - (* clkbuf_sink *) - input IOCLK1; - input ODATAIN; - input SDI; - input T; -endmodule - -module IODRP2_MCB (...); - parameter DATA_RATE = "SDR"; - parameter integer IDELAY_VALUE = 0; - parameter integer MCB_ADDRESS = 0; - parameter integer ODELAY_VALUE = 0; - parameter SERDES_MODE = "NONE"; - parameter integer SIM_TAPDELAY_VALUE = 75; - output AUXSDO; - output DATAOUT2; - output DATAOUT; - output DOUT; - output DQSOUTN; - output DQSOUTP; - output SDO; - output TOUT; - input ADD; - input AUXSDOIN; - input BKST; - (* clkbuf_sink *) - input CLK; - input CS; - input IDATAIN; - (* clkbuf_sink *) - input IOCLK0; - (* clkbuf_sink *) - input IOCLK1; - input MEMUPDATE; - input ODATAIN; - input SDI; - input T; - input [4:0] AUXADDR; -endmodule - -module ISERDES2 (...); - parameter BITSLIP_ENABLE = "FALSE"; - parameter DATA_RATE = "SDR"; - parameter integer DATA_WIDTH = 1; - parameter INTERFACE_TYPE = "NETWORKING"; - parameter SERDES_MODE = "NONE"; - output CFB0; - output CFB1; - output DFB; - output FABRICOUT; - output INCDEC; - output Q1; - output Q2; - output Q3; - output Q4; - output SHIFTOUT; - output VALID; - input BITSLIP; - input CE0; - (* clkbuf_sink *) - input CLK0; - (* clkbuf_sink *) - input CLK1; - (* clkbuf_sink *) - input CLKDIV; - input D; - input IOCE; - input RST; - input SHIFTIN; -endmodule - -module OSERDES2 (...); - parameter BYPASS_GCLK_FF = "FALSE"; - parameter DATA_RATE_OQ = "DDR"; - parameter DATA_RATE_OT = "DDR"; - parameter integer DATA_WIDTH = 2; - parameter OUTPUT_MODE = "SINGLE_ENDED"; - parameter SERDES_MODE = "NONE"; - parameter integer TRAIN_PATTERN = 0; - output OQ; - output SHIFTOUT1; - output SHIFTOUT2; - output SHIFTOUT3; - output SHIFTOUT4; - output TQ; - (* clkbuf_sink *) - input CLK0; - (* clkbuf_sink *) - input CLK1; - (* clkbuf_sink *) - input CLKDIV; - input D1; - input D2; - input D3; - input D4; - input IOCE; - input OCE; - input RST; - input SHIFTIN1; - input SHIFTIN2; - input SHIFTIN3; - input SHIFTIN4; - input T1; - input T2; - input T3; - input T4; - input TCE; - input TRAIN; -endmodule - -module IBUF_DLY_ADJ (...); - parameter DELAY_OFFSET = "OFF"; - parameter IOSTANDARD = "DEFAULT"; - output O; - (* iopad_external_pin *) - input I; - input [2:0] S; -endmodule - -module IBUF_IBUFDISABLE (...); - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - (* iopad_external_pin *) - input I; - input IBUFDISABLE; -endmodule - -module IBUF_INTERMDISABLE (...); - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - (* iopad_external_pin *) - input I; - input IBUFDISABLE; - input INTERMDISABLE; -endmodule - -module IBUF_ANALOG (...); - output O; - (* iopad_external_pin *) - input I; -endmodule - -module IBUFE3 (...); - parameter CCIO_EN = "TRUE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "ULTRASCALE"; - parameter integer SIM_INPUT_BUFFER_OFFSET = 0; - parameter USE_IBUFDISABLE = "FALSE"; - output O; - (* iopad_external_pin *) - input I; - input IBUFDISABLE; - input [3:0] OSC; - input OSC_EN; - input VREF; -endmodule - -module IBUFDS (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_DELAY_VALUE = "0"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IFD_DELAY_VALUE = "AUTO"; - parameter IOSTANDARD = "DEFAULT"; - output O; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module IBUFDS_DLY_ADJ (...); - parameter DELAY_OFFSET = "OFF"; - parameter DIFF_TERM = "FALSE"; - parameter IOSTANDARD = "DEFAULT"; - output O; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; - input [2:0] S; -endmodule - -module IBUFDS_IBUFDISABLE (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; - input IBUFDISABLE; -endmodule - -module IBUFDS_INTERMDISABLE (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; - input IBUFDISABLE; - input INTERMDISABLE; -endmodule - -module IBUFDS_DIFF_OUT (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - output O; - output OB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module IBUFDS_DIFF_OUT_IBUFDISABLE (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - output OB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; - input IBUFDISABLE; -endmodule - -module IBUFDS_DIFF_OUT_INTERMDISABLE (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - output OB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; - input IBUFDISABLE; - input INTERMDISABLE; -endmodule - -module IBUFDSE3 (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter USE_IBUFDISABLE = "FALSE"; - parameter integer SIM_INPUT_BUFFER_OFFSET = 0; - output O; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; - input IBUFDISABLE; - input [3:0] OSC; - input [1:0] OSC_EN; -endmodule - -module IBUFDS_DPHY (...); - parameter DIFF_TERM = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - output HSRX_O; - output LPRX_O_N; - output LPRX_O_P; - input HSRX_DISABLE; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; - input LPRX_DISABLE; -endmodule - -module IBUFGDS (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter DIFF_TERM = "FALSE"; - parameter IBUF_DELAY_VALUE = "0"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - output O; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module IBUFGDS_DIFF_OUT (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - output O; - output OB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module IOBUF_DCIEN (...); - parameter integer DRIVE = 12; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter SLEW = "SLOW"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - (* iopad_external_pin *) - inout IO; - input DCITERMDISABLE; - input I; - input IBUFDISABLE; - input T; -endmodule - -module IOBUF_INTERMDISABLE (...); - parameter integer DRIVE = 12; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter SLEW = "SLOW"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - (* iopad_external_pin *) - inout IO; - input I; - input IBUFDISABLE; - input INTERMDISABLE; - input T; -endmodule - -module IOBUFE3 (...); - parameter integer DRIVE = 12; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "ULTRASCALE"; - parameter integer SIM_INPUT_BUFFER_OFFSET = 0; - parameter USE_IBUFDISABLE = "FALSE"; - output O; - (* iopad_external_pin *) - inout IO; - input DCITERMDISABLE; - input I; - input IBUFDISABLE; - input [3:0] OSC; - input OSC_EN; - input T; - input VREF; -endmodule - -module IOBUFDS (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - output O; - (* iopad_external_pin *) - inout IO; - (* iopad_external_pin *) - inout IOB; - input I; - input T; -endmodule - -module IOBUFDS_DCIEN (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter SLEW = "SLOW"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - (* iopad_external_pin *) - inout IO; - (* iopad_external_pin *) - inout IOB; - input DCITERMDISABLE; - input I; - input IBUFDISABLE; - input T; -endmodule - -module IOBUFDS_INTERMDISABLE (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter SLEW = "SLOW"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - (* iopad_external_pin *) - inout IO; - (* iopad_external_pin *) - inout IOB; - input I; - input IBUFDISABLE; - input INTERMDISABLE; - input T; -endmodule - -module IOBUFDS_DIFF_OUT (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - output O; - output OB; - (* iopad_external_pin *) - inout IO; - (* iopad_external_pin *) - inout IOB; - input I; - input TM; - input TS; -endmodule - -module IOBUFDS_DIFF_OUT_DCIEN (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - output OB; - (* iopad_external_pin *) - inout IO; - (* iopad_external_pin *) - inout IOB; - input DCITERMDISABLE; - input I; - input IBUFDISABLE; - input TM; - input TS; -endmodule - -module IOBUFDS_DIFF_OUT_INTERMDISABLE (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - output OB; - (* iopad_external_pin *) - inout IO; - (* iopad_external_pin *) - inout IOB; - input I; - input IBUFDISABLE; - input INTERMDISABLE; - input TM; - input TS; -endmodule - -module IOBUFDSE3 (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter integer SIM_INPUT_BUFFER_OFFSET = 0; - parameter USE_IBUFDISABLE = "FALSE"; - output O; - (* iopad_external_pin *) - inout IO; - (* iopad_external_pin *) - inout IOB; - input DCITERMDISABLE; - input I; - input IBUFDISABLE; - input [3:0] OSC; - input [1:0] OSC_EN; - input T; -endmodule - -module OBUFDS_DPHY (...); - parameter IOSTANDARD = "DEFAULT"; - (* iopad_external_pin *) - output O; - (* iopad_external_pin *) - output OB; - input HSTX_I; - input HSTX_T; - input LPTX_I_N; - input LPTX_I_P; - input LPTX_T; -endmodule - -module OBUFTDS (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - (* iopad_external_pin *) - output O; - (* iopad_external_pin *) - output OB; - input I; - input T; -endmodule - -module KEEPER (...); - inout O; -endmodule - -module PULLDOWN (...); - output O; -endmodule - -module PULLUP (...); - output O; -endmodule - -(* keep *) -module DCIRESET (...); - output LOCKED; - input RST; -endmodule - -(* keep *) -module HPIO_VREF (...); - parameter VREF_CNTR = "OFF"; - output VREF; - input [6:0] FABRIC_VREF_TUNE; -endmodule - -module BUFGCE (...); - parameter CE_TYPE = "SYNC"; - parameter [0:0] IS_CE_INVERTED = 1'b0; - parameter [0:0] IS_I_INVERTED = 1'b0; - parameter SIM_DEVICE = "ULTRASCALE"; - parameter STARTUP_SYNC = "FALSE"; - (* clkbuf_driver *) - output O; - (* invertible_pin = "IS_CE_INVERTED" *) - input CE; - (* invertible_pin = "IS_I_INVERTED" *) - input I; -endmodule - -module BUFGCE_1 (...); - (* clkbuf_driver *) - output O; - input CE; - input I; -endmodule - -module BUFGMUX (...); - parameter CLK_SEL_TYPE = "SYNC"; - (* clkbuf_driver *) - output O; - input I0; - input I1; - input S; -endmodule - -module BUFGMUX_1 (...); - parameter CLK_SEL_TYPE = "SYNC"; - (* clkbuf_driver *) - output O; - input I0; - input I1; - input S; -endmodule - -module BUFGMUX_CTRL (...); - (* clkbuf_driver *) - output O; - input I0; - input I1; - input S; -endmodule - -module BUFGMUX_VIRTEX4 (...); - (* clkbuf_driver *) - output O; - input I0; - input I1; - input S; -endmodule - -module BUFG_GT (...); - parameter SIM_DEVICE = "ULTRASCALE"; - parameter STARTUP_SYNC = "FALSE"; - (* clkbuf_driver *) - output O; - input CE; - input CEMASK; - input CLR; - input CLRMASK; - input [2:0] DIV; - input I; -endmodule - -module BUFG_GT_SYNC (...); - output CESYNC; - output CLRSYNC; - input CE; - input CLK; - input CLR; -endmodule - -module BUFG_PS (...); - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter STARTUP_SYNC = "FALSE"; - (* clkbuf_driver *) - output O; - input I; -endmodule - -module BUFGCE_DIV (...); - parameter integer BUFGCE_DIVIDE = 1; - parameter CE_TYPE = "SYNC"; - parameter HARDSYNC_CLR = "FALSE"; - parameter [0:0] IS_CE_INVERTED = 1'b0; - parameter [0:0] IS_CLR_INVERTED = 1'b0; - parameter [0:0] IS_I_INVERTED = 1'b0; - parameter SIM_DEVICE = "ULTRASCALE"; - parameter STARTUP_SYNC = "FALSE"; - (* clkbuf_driver *) - output O; - (* invertible_pin = "IS_CE_INVERTED" *) - input CE; - (* invertible_pin = "IS_CLR_INVERTED" *) - input CLR; - (* invertible_pin = "IS_I_INVERTED" *) - input I; -endmodule - -module BUFH (...); - (* clkbuf_driver *) - output O; - input I; -endmodule - -module BUFIO2 (...); - parameter DIVIDE_BYPASS = "TRUE"; - parameter integer DIVIDE = 1; - parameter I_INVERT = "FALSE"; - parameter USE_DOUBLER = "FALSE"; - (* clkbuf_driver *) - output DIVCLK; - (* clkbuf_driver *) - output IOCLK; - output SERDESSTROBE; - input I; -endmodule - -module BUFIO2_2CLK (...); - parameter integer DIVIDE = 2; - (* clkbuf_driver *) - output DIVCLK; - (* clkbuf_driver *) - output IOCLK; - output SERDESSTROBE; - input I; - input IB; -endmodule - -module BUFIO2FB (...); - parameter DIVIDE_BYPASS = "TRUE"; - (* clkbuf_driver *) - output O; - input I; -endmodule - -module BUFPLL (...); - parameter integer DIVIDE = 1; - parameter ENABLE_SYNC = "TRUE"; - (* clkbuf_driver *) - output IOCLK; - output LOCK; - output SERDESSTROBE; - input GCLK; - input LOCKED; - input PLLIN; -endmodule - -module BUFPLL_MCB (...); - parameter integer DIVIDE = 2; - parameter LOCK_SRC = "LOCK_TO_0"; - (* clkbuf_driver *) - output IOCLK0; - (* clkbuf_driver *) - output IOCLK1; - output LOCK; - output SERDESSTROBE0; - output SERDESSTROBE1; - input GCLK; - input LOCKED; - input PLLIN0; - input PLLIN1; -endmodule - -module BUFIO (...); - (* clkbuf_driver *) - output O; - input I; -endmodule - -module BUFIODQS (...); - parameter DQSMASK_ENABLE = "FALSE"; - (* clkbuf_driver *) - output O; - input DQSMASK; - input I; -endmodule - -module BUFR (...); - parameter BUFR_DIVIDE = "BYPASS"; - parameter SIM_DEVICE = "7SERIES"; - (* clkbuf_driver *) - output O; - input CE; - input CLR; - input I; -endmodule - -module BUFMR (...); - (* clkbuf_driver *) - output O; - input I; -endmodule - -module BUFMRCE (...); - parameter CE_TYPE = "SYNC"; - parameter integer INIT_OUT = 0; - parameter [0:0] IS_CE_INVERTED = 1'b0; - (* clkbuf_driver *) - output O; - (* invertible_pin = "IS_CE_INVERTED" *) - input CE; - input I; -endmodule - -module DCM (...); - parameter real CLKDV_DIVIDE = 2.0; - parameter integer CLKFX_DIVIDE = 1; - parameter integer CLKFX_MULTIPLY = 4; - parameter CLKIN_DIVIDE_BY_2 = "FALSE"; - parameter real CLKIN_PERIOD = 10.0; - parameter CLKOUT_PHASE_SHIFT = "NONE"; - parameter CLK_FEEDBACK = "1X"; - parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - parameter DFS_FREQUENCY_MODE = "LOW"; - parameter DLL_FREQUENCY_MODE = "LOW"; - parameter DSS_MODE = "NONE"; - parameter DUTY_CYCLE_CORRECTION = "TRUE"; - parameter [15:0] FACTORY_JF = 16'hC080; - parameter integer PHASE_SHIFT = 0; - parameter SIM_MODE = "SAFE"; - parameter STARTUP_WAIT = "FALSE"; - input CLKFB; - input CLKIN; - input DSSEN; - input PSCLK; - input PSEN; - input PSINCDEC; - input RST; - output CLK0; - output CLK180; - output CLK270; - output CLK2X; - output CLK2X180; - output CLK90; - output CLKDV; - output CLKFX; - output CLKFX180; - output LOCKED; - output PSDONE; - output [7:0] STATUS; -endmodule - -module DCM_SP (...); - parameter real CLKDV_DIVIDE = 2.0; - parameter integer CLKFX_DIVIDE = 1; - parameter integer CLKFX_MULTIPLY = 4; - parameter CLKIN_DIVIDE_BY_2 = "FALSE"; - parameter real CLKIN_PERIOD = 10.0; - parameter CLKOUT_PHASE_SHIFT = "NONE"; - parameter CLK_FEEDBACK = "1X"; - parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - parameter DFS_FREQUENCY_MODE = "LOW"; - parameter DLL_FREQUENCY_MODE = "LOW"; - parameter DSS_MODE = "NONE"; - parameter DUTY_CYCLE_CORRECTION = "TRUE"; - parameter FACTORY_JF = 16'hC080; - parameter integer PHASE_SHIFT = 0; - parameter STARTUP_WAIT = "FALSE"; - input CLKFB; - input CLKIN; - input DSSEN; - input PSCLK; - input PSEN; - input PSINCDEC; - input RST; - output CLK0; - output CLK180; - output CLK270; - output CLK2X; - output CLK2X180; - output CLK90; - output CLKDV; - output CLKFX; - output CLKFX180; - output LOCKED; - output PSDONE; - output [7:0] STATUS; -endmodule - -module DCM_CLKGEN (...); - parameter SPREAD_SPECTRUM = "NONE"; - parameter STARTUP_WAIT = "FALSE"; - parameter integer CLKFXDV_DIVIDE = 2; - parameter integer CLKFX_DIVIDE = 1; - parameter integer CLKFX_MULTIPLY = 4; - parameter real CLKFX_MD_MAX = 0.0; - parameter real CLKIN_PERIOD = 0.0; - output CLKFX180; - output CLKFX; - output CLKFXDV; - output LOCKED; - output PROGDONE; - output [2:1] STATUS; - input CLKIN; - input FREEZEDCM; - input PROGCLK; - input PROGDATA; - input PROGEN; - input RST; -endmodule - -module DCM_ADV (...); - parameter real CLKDV_DIVIDE = 2.0; - parameter integer CLKFX_DIVIDE = 1; - parameter integer CLKFX_MULTIPLY = 4; - parameter CLKIN_DIVIDE_BY_2 = "FALSE"; - parameter real CLKIN_PERIOD = 10.0; - parameter CLKOUT_PHASE_SHIFT = "NONE"; - parameter CLK_FEEDBACK = "1X"; - parameter DCM_AUTOCALIBRATION = "TRUE"; - parameter DCM_PERFORMANCE_MODE = "MAX_SPEED"; - parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - parameter DFS_FREQUENCY_MODE = "LOW"; - parameter DLL_FREQUENCY_MODE = "LOW"; - parameter DUTY_CYCLE_CORRECTION = "TRUE"; - parameter FACTORY_JF = 16'hF0F0; - parameter integer PHASE_SHIFT = 0; - parameter SIM_DEVICE ="VIRTEX4"; - parameter STARTUP_WAIT = "FALSE"; - output CLK0; - output CLK180; - output CLK270; - output CLK2X180; - output CLK2X; - output CLK90; - output CLKDV; - output CLKFX180; - output CLKFX; - output DRDY; - output LOCKED; - output PSDONE; - output [15:0] DO; - input CLKFB; - input CLKIN; - input DCLK; - input DEN; - input DWE; - input PSCLK; - input PSEN; - input PSINCDEC; - input RST; - input [15:0] DI; - input [6:0] DADDR; -endmodule - -module DCM_BASE (...); - parameter real CLKDV_DIVIDE = 2.0; - parameter integer CLKFX_DIVIDE = 1; - parameter integer CLKFX_MULTIPLY = 4; - parameter CLKIN_DIVIDE_BY_2 = "FALSE"; - parameter real CLKIN_PERIOD = 10.0; - parameter CLKOUT_PHASE_SHIFT = "NONE"; - parameter CLK_FEEDBACK = "1X"; - parameter DCM_AUTOCALIBRATION = "TRUE"; - parameter DCM_PERFORMANCE_MODE = "MAX_SPEED"; - parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - parameter DFS_FREQUENCY_MODE = "LOW"; - parameter DLL_FREQUENCY_MODE = "LOW"; - parameter DUTY_CYCLE_CORRECTION = "TRUE"; - parameter [15:0] FACTORY_JF = 16'hF0F0; - parameter integer PHASE_SHIFT = 0; - parameter STARTUP_WAIT = "FALSE"; - output CLK0; - output CLK180; - output CLK270; - output CLK2X180; - output CLK2X; - output CLK90; - output CLKDV; - output CLKFX180; - output CLKFX; - output LOCKED; - input CLKFB; - input CLKIN; - input RST; -endmodule - -module DCM_PS (...); - parameter real CLKDV_DIVIDE = 2.0; - parameter integer CLKFX_DIVIDE = 1; - parameter integer CLKFX_MULTIPLY = 4; - parameter CLKIN_DIVIDE_BY_2 = "FALSE"; - parameter real CLKIN_PERIOD = 10.0; - parameter CLKOUT_PHASE_SHIFT = "NONE"; - parameter CLK_FEEDBACK = "1X"; - parameter DCM_AUTOCALIBRATION = "TRUE"; - parameter DCM_PERFORMANCE_MODE = "MAX_SPEED"; - parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - parameter DFS_FREQUENCY_MODE = "LOW"; - parameter DLL_FREQUENCY_MODE = "LOW"; - parameter DUTY_CYCLE_CORRECTION = "TRUE"; - parameter [15:0] FACTORY_JF = 16'hF0F0; - parameter integer PHASE_SHIFT = 0; - parameter STARTUP_WAIT = "FALSE"; - output CLK0; - output CLK180; - output CLK270; - output CLK2X180; - output CLK2X; - output CLK90; - output CLKDV; - output CLKFX180; - output CLKFX; - output LOCKED; - output PSDONE; - output [15:0] DO; - input CLKFB; - input CLKIN; - input PSCLK; - input PSEN; - input PSINCDEC; - input RST; -endmodule - -module PMCD (...); - parameter EN_REL = "FALSE"; - parameter RST_DEASSERT_CLK = "CLKA"; - output CLKA1; - output CLKA1D2; - output CLKA1D4; - output CLKA1D8; - output CLKB1; - output CLKC1; - output CLKD1; - input CLKA; - input CLKB; - input CLKC; - input CLKD; - input REL; - input RST; -endmodule - -module PLL_ADV (...); - parameter BANDWIDTH = "OPTIMIZED"; - parameter CLK_FEEDBACK = "CLKFBOUT"; - parameter CLKFBOUT_DESKEW_ADJUST = "NONE"; - parameter CLKOUT0_DESKEW_ADJUST = "NONE"; - parameter CLKOUT1_DESKEW_ADJUST = "NONE"; - parameter CLKOUT2_DESKEW_ADJUST = "NONE"; - parameter CLKOUT3_DESKEW_ADJUST = "NONE"; - parameter CLKOUT4_DESKEW_ADJUST = "NONE"; - parameter CLKOUT5_DESKEW_ADJUST = "NONE"; - parameter integer CLKFBOUT_MULT = 1; - parameter real CLKFBOUT_PHASE = 0.0; - parameter real CLKIN1_PERIOD = 0.000; - parameter real CLKIN2_PERIOD = 0.000; - parameter integer CLKOUT0_DIVIDE = 1; - parameter real CLKOUT0_DUTY_CYCLE = 0.5; - parameter real CLKOUT0_PHASE = 0.0; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.5; - parameter real CLKOUT1_PHASE = 0.0; - parameter integer CLKOUT2_DIVIDE = 1; - parameter real CLKOUT2_DUTY_CYCLE = 0.5; - parameter real CLKOUT2_PHASE = 0.0; - parameter integer CLKOUT3_DIVIDE = 1; - parameter real CLKOUT3_DUTY_CYCLE = 0.5; - parameter real CLKOUT3_PHASE = 0.0; - parameter integer CLKOUT4_DIVIDE = 1; - parameter real CLKOUT4_DUTY_CYCLE = 0.5; - parameter real CLKOUT4_PHASE = 0.0; - parameter integer CLKOUT5_DIVIDE = 1; - parameter real CLKOUT5_DUTY_CYCLE = 0.5; - parameter real CLKOUT5_PHASE = 0.0; - parameter COMPENSATION = "SYSTEM_SYNCHRONOUS"; - parameter integer DIVCLK_DIVIDE = 1; - parameter EN_REL = "FALSE"; - parameter PLL_PMCD_MODE = "FALSE"; - parameter real REF_JITTER = 0.100; - parameter RESET_ON_LOSS_OF_LOCK = "FALSE"; - parameter RST_DEASSERT_CLK = "CLKIN1"; - parameter SIM_DEVICE = "VIRTEX5"; - parameter real VCOCLK_FREQ_MAX = 1440.0; - parameter real VCOCLK_FREQ_MIN = 400.0; - parameter real CLKIN_FREQ_MAX = 710.0; - parameter real CLKIN_FREQ_MIN = 19.0; - parameter real CLKPFD_FREQ_MAX = 550.0; - parameter real CLKPFD_FREQ_MIN = 19.0; - output CLKFBDCM; - output CLKFBOUT; - output CLKOUT0; - output CLKOUT1; - output CLKOUT2; - output CLKOUT3; - output CLKOUT4; - output CLKOUT5; - output CLKOUTDCM0; - output CLKOUTDCM1; - output CLKOUTDCM2; - output CLKOUTDCM3; - output CLKOUTDCM4; - output CLKOUTDCM5; - output DRDY; - output LOCKED; - output [15:0] DO; - input CLKFBIN; - input CLKIN1; - input CLKIN2; - input CLKINSEL; - input DCLK; - input DEN; - input DWE; - input REL; - input RST; - input [15:0] DI; - input [4:0] DADDR; -endmodule - -module PLL_BASE (...); - parameter BANDWIDTH = "OPTIMIZED"; - parameter integer CLKFBOUT_MULT = 1; - parameter real CLKFBOUT_PHASE = 0.0; - parameter real CLKIN_PERIOD = 0.000; - parameter integer CLKOUT0_DIVIDE = 1; - parameter real CLKOUT0_DUTY_CYCLE = 0.5; - parameter real CLKOUT0_PHASE = 0.0; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.5; - parameter real CLKOUT1_PHASE = 0.0; - parameter integer CLKOUT2_DIVIDE = 1; - parameter real CLKOUT2_DUTY_CYCLE = 0.5; - parameter real CLKOUT2_PHASE = 0.0; - parameter integer CLKOUT3_DIVIDE = 1; - parameter real CLKOUT3_DUTY_CYCLE = 0.5; - parameter real CLKOUT3_PHASE = 0.0; - parameter integer CLKOUT4_DIVIDE = 1; - parameter real CLKOUT4_DUTY_CYCLE = 0.5; - parameter real CLKOUT4_PHASE = 0.0; - parameter integer CLKOUT5_DIVIDE = 1; - parameter real CLKOUT5_DUTY_CYCLE = 0.5; - parameter real CLKOUT5_PHASE = 0.0; - parameter CLK_FEEDBACK = "CLKFBOUT"; - parameter COMPENSATION = "SYSTEM_SYNCHRONOUS"; - parameter integer DIVCLK_DIVIDE = 1; - parameter real REF_JITTER = 0.100; - parameter RESET_ON_LOSS_OF_LOCK = "FALSE"; - output CLKFBOUT; - output CLKOUT0; - output CLKOUT1; - output CLKOUT2; - output CLKOUT3; - output CLKOUT4; - output CLKOUT5; - output LOCKED; - input CLKFBIN; - input CLKIN; - input RST; -endmodule - -module MMCM_ADV (...); - parameter BANDWIDTH = "OPTIMIZED"; - parameter CLKFBOUT_USE_FINE_PS = "FALSE"; - parameter CLKOUT0_USE_FINE_PS = "FALSE"; - parameter CLKOUT1_USE_FINE_PS = "FALSE"; - parameter CLKOUT2_USE_FINE_PS = "FALSE"; - parameter CLKOUT3_USE_FINE_PS = "FALSE"; - parameter CLKOUT4_CASCADE = "FALSE"; - parameter CLKOUT4_USE_FINE_PS = "FALSE"; - parameter CLKOUT5_USE_FINE_PS = "FALSE"; - parameter CLKOUT6_USE_FINE_PS = "FALSE"; - parameter CLOCK_HOLD = "FALSE"; - parameter COMPENSATION = "ZHOLD"; - parameter STARTUP_WAIT = "FALSE"; - parameter integer CLKOUT1_DIVIDE = 1; - parameter integer CLKOUT2_DIVIDE = 1; - parameter integer CLKOUT3_DIVIDE = 1; - parameter integer CLKOUT4_DIVIDE = 1; - parameter integer CLKOUT5_DIVIDE = 1; - parameter integer CLKOUT6_DIVIDE = 1; - parameter integer DIVCLK_DIVIDE = 1; - parameter real CLKFBOUT_MULT_F = 5.000; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN1_PERIOD = 0.000; - parameter real CLKIN2_PERIOD = 0.000; - parameter real CLKOUT0_DIVIDE_F = 1.000; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter real CLKOUT2_DUTY_CYCLE = 0.500; - parameter real CLKOUT2_PHASE = 0.000; - parameter real CLKOUT3_DUTY_CYCLE = 0.500; - parameter real CLKOUT3_PHASE = 0.000; - parameter real CLKOUT4_DUTY_CYCLE = 0.500; - parameter real CLKOUT4_PHASE = 0.000; - parameter real CLKOUT5_DUTY_CYCLE = 0.500; - parameter real CLKOUT5_PHASE = 0.000; - parameter real CLKOUT6_DUTY_CYCLE = 0.500; - parameter real CLKOUT6_PHASE = 0.000; - parameter real REF_JITTER1 = 0.010; - parameter real REF_JITTER2 = 0.010; - parameter real VCOCLK_FREQ_MAX = 1600.0; - parameter real VCOCLK_FREQ_MIN = 600.0; - parameter real CLKIN_FREQ_MAX = 800.0; - parameter real CLKIN_FREQ_MIN = 10.0; - parameter real CLKPFD_FREQ_MAX = 550.0; - parameter real CLKPFD_FREQ_MIN = 10.0; - output CLKFBOUT; - output CLKFBOUTB; - output CLKFBSTOPPED; - output CLKINSTOPPED; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUT2; - output CLKOUT2B; - output CLKOUT3; - output CLKOUT3B; - output CLKOUT4; - output CLKOUT5; - output CLKOUT6; - output DRDY; - output LOCKED; - output PSDONE; - output [15:0] DO; - input CLKFBIN; - input CLKIN1; - input CLKIN2; - input CLKINSEL; - input DCLK; - input DEN; - input DWE; - input PSCLK; - input PSEN; - input PSINCDEC; - input PWRDWN; - input RST; - input [15:0] DI; - input [6:0] DADDR; -endmodule - -module MMCM_BASE (...); - parameter BANDWIDTH = "OPTIMIZED"; - parameter real CLKFBOUT_MULT_F = 5.000; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN1_PERIOD = 0.000; - parameter real CLKOUT0_DIVIDE_F = 1.000; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter integer CLKOUT2_DIVIDE = 1; - parameter real CLKOUT2_DUTY_CYCLE = 0.500; - parameter real CLKOUT2_PHASE = 0.000; - parameter integer CLKOUT3_DIVIDE = 1; - parameter real CLKOUT3_DUTY_CYCLE = 0.500; - parameter real CLKOUT3_PHASE = 0.000; - parameter CLKOUT4_CASCADE = "FALSE"; - parameter integer CLKOUT4_DIVIDE = 1; - parameter real CLKOUT4_DUTY_CYCLE = 0.500; - parameter real CLKOUT4_PHASE = 0.000; - parameter integer CLKOUT5_DIVIDE = 1; - parameter real CLKOUT5_DUTY_CYCLE = 0.500; - parameter real CLKOUT5_PHASE = 0.000; - parameter integer CLKOUT6_DIVIDE = 1; - parameter real CLKOUT6_DUTY_CYCLE = 0.500; - parameter real CLKOUT6_PHASE = 0.000; - parameter CLOCK_HOLD = "FALSE"; - parameter integer DIVCLK_DIVIDE = 1; - parameter real REF_JITTER1 = 0.010; - parameter STARTUP_WAIT = "FALSE"; - output CLKFBOUT; - output CLKFBOUTB; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUT2; - output CLKOUT2B; - output CLKOUT3; - output CLKOUT3B; - output CLKOUT4; - output CLKOUT5; - output CLKOUT6; - output LOCKED; - input CLKFBIN; - input CLKIN1; - input PWRDWN; - input RST; -endmodule - -module MMCME2_ADV (...); - parameter real CLKIN_FREQ_MAX = 1066.000; - parameter real CLKIN_FREQ_MIN = 10.000; - parameter real CLKPFD_FREQ_MAX = 550.000; - parameter real CLKPFD_FREQ_MIN = 10.000; - parameter real VCOCLK_FREQ_MAX = 1600.000; - parameter real VCOCLK_FREQ_MIN = 600.000; - parameter BANDWIDTH = "OPTIMIZED"; - parameter real CLKFBOUT_MULT_F = 5.000; - parameter real CLKFBOUT_PHASE = 0.000; - parameter CLKFBOUT_USE_FINE_PS = "FALSE"; - parameter real CLKIN1_PERIOD = 0.000; - parameter real CLKIN2_PERIOD = 0.000; - parameter real CLKOUT0_DIVIDE_F = 1.000; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter CLKOUT0_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter CLKOUT1_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT2_DIVIDE = 1; - parameter real CLKOUT2_DUTY_CYCLE = 0.500; - parameter real CLKOUT2_PHASE = 0.000; - parameter CLKOUT2_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT3_DIVIDE = 1; - parameter real CLKOUT3_DUTY_CYCLE = 0.500; - parameter real CLKOUT3_PHASE = 0.000; - parameter CLKOUT3_USE_FINE_PS = "FALSE"; - parameter CLKOUT4_CASCADE = "FALSE"; - parameter integer CLKOUT4_DIVIDE = 1; - parameter real CLKOUT4_DUTY_CYCLE = 0.500; - parameter real CLKOUT4_PHASE = 0.000; - parameter CLKOUT4_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT5_DIVIDE = 1; - parameter real CLKOUT5_DUTY_CYCLE = 0.500; - parameter real CLKOUT5_PHASE = 0.000; - parameter CLKOUT5_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT6_DIVIDE = 1; - parameter real CLKOUT6_DUTY_CYCLE = 0.500; - parameter real CLKOUT6_PHASE = 0.000; - parameter CLKOUT6_USE_FINE_PS = "FALSE"; - parameter COMPENSATION = "ZHOLD"; - parameter integer DIVCLK_DIVIDE = 1; - parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0; - parameter [0:0] IS_PSEN_INVERTED = 1'b0; - parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0; - parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REF_JITTER1 = 0.010; - parameter real REF_JITTER2 = 0.010; - parameter SS_EN = "FALSE"; - parameter SS_MODE = "CENTER_HIGH"; - parameter integer SS_MOD_PERIOD = 10000; - parameter STARTUP_WAIT = "FALSE"; - output CLKFBOUT; - output CLKFBOUTB; - output CLKFBSTOPPED; - output CLKINSTOPPED; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUT2; - output CLKOUT2B; - output CLKOUT3; - output CLKOUT3B; - output CLKOUT4; - output CLKOUT5; - output CLKOUT6; - output [15:0] DO; - output DRDY; - output LOCKED; - output PSDONE; - input CLKFBIN; - input CLKIN1; - input CLKIN2; - (* invertible_pin = "IS_CLKINSEL_INVERTED" *) - input CLKINSEL; - input [6:0] DADDR; - input DCLK; - input DEN; - input [15:0] DI; - input DWE; - input PSCLK; - (* invertible_pin = "IS_PSEN_INVERTED" *) - input PSEN; - (* invertible_pin = "IS_PSINCDEC_INVERTED" *) - input PSINCDEC; - (* invertible_pin = "IS_PWRDWN_INVERTED" *) - input PWRDWN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module MMCME2_BASE (...); - parameter BANDWIDTH = "OPTIMIZED"; - parameter real CLKFBOUT_MULT_F = 5.000; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN1_PERIOD = 0.000; - parameter real CLKOUT0_DIVIDE_F = 1.000; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter integer CLKOUT2_DIVIDE = 1; - parameter real CLKOUT2_DUTY_CYCLE = 0.500; - parameter real CLKOUT2_PHASE = 0.000; - parameter integer CLKOUT3_DIVIDE = 1; - parameter real CLKOUT3_DUTY_CYCLE = 0.500; - parameter real CLKOUT3_PHASE = 0.000; - parameter CLKOUT4_CASCADE = "FALSE"; - parameter integer CLKOUT4_DIVIDE = 1; - parameter real CLKOUT4_DUTY_CYCLE = 0.500; - parameter real CLKOUT4_PHASE = 0.000; - parameter integer CLKOUT5_DIVIDE = 1; - parameter real CLKOUT5_DUTY_CYCLE = 0.500; - parameter real CLKOUT5_PHASE = 0.000; - parameter integer CLKOUT6_DIVIDE = 1; - parameter real CLKOUT6_DUTY_CYCLE = 0.500; - parameter real CLKOUT6_PHASE = 0.000; - parameter integer DIVCLK_DIVIDE = 1; - parameter real REF_JITTER1 = 0.010; - parameter STARTUP_WAIT = "FALSE"; - output CLKFBOUT; - output CLKFBOUTB; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUT2; - output CLKOUT2B; - output CLKOUT3; - output CLKOUT3B; - output CLKOUT4; - output CLKOUT5; - output CLKOUT6; - output LOCKED; - input CLKFBIN; - input CLKIN1; - input PWRDWN; - input RST; -endmodule - -module PLLE2_ADV (...); - parameter BANDWIDTH = "OPTIMIZED"; - parameter COMPENSATION = "ZHOLD"; - parameter STARTUP_WAIT = "FALSE"; - parameter integer CLKOUT0_DIVIDE = 1; - parameter integer CLKOUT1_DIVIDE = 1; - parameter integer CLKOUT2_DIVIDE = 1; - parameter integer CLKOUT3_DIVIDE = 1; - parameter integer CLKOUT4_DIVIDE = 1; - parameter integer CLKOUT5_DIVIDE = 1; - parameter integer DIVCLK_DIVIDE = 1; - parameter integer CLKFBOUT_MULT = 5; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN1_PERIOD = 0.000; - parameter real CLKIN2_PERIOD = 0.000; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter real CLKOUT2_DUTY_CYCLE = 0.500; - parameter real CLKOUT2_PHASE = 0.000; - parameter real CLKOUT3_DUTY_CYCLE = 0.500; - parameter real CLKOUT3_PHASE = 0.000; - parameter real CLKOUT4_DUTY_CYCLE = 0.500; - parameter real CLKOUT4_PHASE = 0.000; - parameter real CLKOUT5_DUTY_CYCLE = 0.500; - parameter real CLKOUT5_PHASE = 0.000; - parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0; - parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REF_JITTER1 = 0.010; - parameter real REF_JITTER2 = 0.010; - parameter real VCOCLK_FREQ_MAX = 2133.000; - parameter real VCOCLK_FREQ_MIN = 800.000; - parameter real CLKIN_FREQ_MAX = 1066.000; - parameter real CLKIN_FREQ_MIN = 19.000; - parameter real CLKPFD_FREQ_MAX = 550.0; - parameter real CLKPFD_FREQ_MIN = 19.0; - output CLKFBOUT; - output CLKOUT0; - output CLKOUT1; - output CLKOUT2; - output CLKOUT3; - output CLKOUT4; - output CLKOUT5; - output DRDY; - output LOCKED; - output [15:0] DO; - input CLKFBIN; - input CLKIN1; - input CLKIN2; - (* invertible_pin = "IS_CLKINSEL_INVERTED" *) - input CLKINSEL; - input DCLK; - input DEN; - input DWE; - (* invertible_pin = "IS_PWRDWN_INVERTED" *) - input PWRDWN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - input [15:0] DI; - input [6:0] DADDR; -endmodule - -module PLLE2_BASE (...); - parameter BANDWIDTH = "OPTIMIZED"; - parameter integer CLKFBOUT_MULT = 5; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN1_PERIOD = 0.000; - parameter integer CLKOUT0_DIVIDE = 1; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter integer CLKOUT2_DIVIDE = 1; - parameter real CLKOUT2_DUTY_CYCLE = 0.500; - parameter real CLKOUT2_PHASE = 0.000; - parameter integer CLKOUT3_DIVIDE = 1; - parameter real CLKOUT3_DUTY_CYCLE = 0.500; - parameter real CLKOUT3_PHASE = 0.000; - parameter integer CLKOUT4_DIVIDE = 1; - parameter real CLKOUT4_DUTY_CYCLE = 0.500; - parameter real CLKOUT4_PHASE = 0.000; - parameter integer CLKOUT5_DIVIDE = 1; - parameter real CLKOUT5_DUTY_CYCLE = 0.500; - parameter real CLKOUT5_PHASE = 0.000; - parameter integer DIVCLK_DIVIDE = 1; - parameter real REF_JITTER1 = 0.010; - parameter STARTUP_WAIT = "FALSE"; - output CLKFBOUT; - output CLKOUT0; - output CLKOUT1; - output CLKOUT2; - output CLKOUT3; - output CLKOUT4; - output CLKOUT5; - output LOCKED; - input CLKFBIN; - input CLKIN1; - input PWRDWN; - input RST; -endmodule - -module MMCME3_ADV (...); - parameter real CLKIN_FREQ_MAX = 1066.000; - parameter real CLKIN_FREQ_MIN = 10.000; - parameter real CLKPFD_FREQ_MAX = 550.000; - parameter real CLKPFD_FREQ_MIN = 10.000; - parameter real VCOCLK_FREQ_MAX = 1600.000; - parameter real VCOCLK_FREQ_MIN = 600.000; - parameter BANDWIDTH = "OPTIMIZED"; - parameter real CLKFBOUT_MULT_F = 5.000; - parameter real CLKFBOUT_PHASE = 0.000; - parameter CLKFBOUT_USE_FINE_PS = "FALSE"; - parameter real CLKIN1_PERIOD = 0.000; - parameter real CLKIN2_PERIOD = 0.000; - parameter real CLKOUT0_DIVIDE_F = 1.000; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter CLKOUT0_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter CLKOUT1_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT2_DIVIDE = 1; - parameter real CLKOUT2_DUTY_CYCLE = 0.500; - parameter real CLKOUT2_PHASE = 0.000; - parameter CLKOUT2_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT3_DIVIDE = 1; - parameter real CLKOUT3_DUTY_CYCLE = 0.500; - parameter real CLKOUT3_PHASE = 0.000; - parameter CLKOUT3_USE_FINE_PS = "FALSE"; - parameter CLKOUT4_CASCADE = "FALSE"; - parameter integer CLKOUT4_DIVIDE = 1; - parameter real CLKOUT4_DUTY_CYCLE = 0.500; - parameter real CLKOUT4_PHASE = 0.000; - parameter CLKOUT4_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT5_DIVIDE = 1; - parameter real CLKOUT5_DUTY_CYCLE = 0.500; - parameter real CLKOUT5_PHASE = 0.000; - parameter CLKOUT5_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT6_DIVIDE = 1; - parameter real CLKOUT6_DUTY_CYCLE = 0.500; - parameter real CLKOUT6_PHASE = 0.000; - parameter CLKOUT6_USE_FINE_PS = "FALSE"; - parameter COMPENSATION = "AUTO"; - parameter integer DIVCLK_DIVIDE = 1; - parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; - parameter [0:0] IS_CLKIN1_INVERTED = 1'b0; - parameter [0:0] IS_CLKIN2_INVERTED = 1'b0; - parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0; - parameter [0:0] IS_PSEN_INVERTED = 1'b0; - parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0; - parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REF_JITTER1 = 0.010; - parameter real REF_JITTER2 = 0.010; - parameter SS_EN = "FALSE"; - parameter SS_MODE = "CENTER_HIGH"; - parameter integer SS_MOD_PERIOD = 10000; - parameter STARTUP_WAIT = "FALSE"; - output CDDCDONE; - output CLKFBOUT; - output CLKFBOUTB; - output CLKFBSTOPPED; - output CLKINSTOPPED; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUT2; - output CLKOUT2B; - output CLKOUT3; - output CLKOUT3B; - output CLKOUT4; - output CLKOUT5; - output CLKOUT6; - output [15:0] DO; - output DRDY; - output LOCKED; - output PSDONE; - input CDDCREQ; - (* invertible_pin = "IS_CLKFBIN_INVERTED" *) - input CLKFBIN; - (* invertible_pin = "IS_CLKIN1_INVERTED" *) - input CLKIN1; - (* invertible_pin = "IS_CLKIN2_INVERTED" *) - input CLKIN2; - (* invertible_pin = "IS_CLKINSEL_INVERTED" *) - input CLKINSEL; - input [6:0] DADDR; - input DCLK; - input DEN; - input [15:0] DI; - input DWE; - input PSCLK; - (* invertible_pin = "IS_PSEN_INVERTED" *) - input PSEN; - (* invertible_pin = "IS_PSINCDEC_INVERTED" *) - input PSINCDEC; - (* invertible_pin = "IS_PWRDWN_INVERTED" *) - input PWRDWN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module MMCME3_BASE (...); - parameter BANDWIDTH = "OPTIMIZED"; - parameter real CLKFBOUT_MULT_F = 5.000; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN1_PERIOD = 0.000; - parameter real CLKOUT0_DIVIDE_F = 1.000; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter integer CLKOUT2_DIVIDE = 1; - parameter real CLKOUT2_DUTY_CYCLE = 0.500; - parameter real CLKOUT2_PHASE = 0.000; - parameter integer CLKOUT3_DIVIDE = 1; - parameter real CLKOUT3_DUTY_CYCLE = 0.500; - parameter real CLKOUT3_PHASE = 0.000; - parameter CLKOUT4_CASCADE = "FALSE"; - parameter integer CLKOUT4_DIVIDE = 1; - parameter real CLKOUT4_DUTY_CYCLE = 0.500; - parameter real CLKOUT4_PHASE = 0.000; - parameter integer CLKOUT5_DIVIDE = 1; - parameter real CLKOUT5_DUTY_CYCLE = 0.500; - parameter real CLKOUT5_PHASE = 0.000; - parameter integer CLKOUT6_DIVIDE = 1; - parameter real CLKOUT6_DUTY_CYCLE = 0.500; - parameter real CLKOUT6_PHASE = 0.000; - parameter integer DIVCLK_DIVIDE = 1; - parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; - parameter [0:0] IS_CLKIN1_INVERTED = 1'b0; - parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REF_JITTER1 = 0.010; - parameter STARTUP_WAIT = "FALSE"; - output CLKFBOUT; - output CLKFBOUTB; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUT2; - output CLKOUT2B; - output CLKOUT3; - output CLKOUT3B; - output CLKOUT4; - output CLKOUT5; - output CLKOUT6; - output LOCKED; - (* invertible_pin = "IS_CLKFBIN_INVERTED" *) - input CLKFBIN; - (* invertible_pin = "IS_CLKIN1_INVERTED" *) - input CLKIN1; - (* invertible_pin = "IS_PWRDWN_INVERTED" *) - input PWRDWN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module PLLE3_ADV (...); - parameter real CLKIN_FREQ_MAX = 1066.000; - parameter real CLKIN_FREQ_MIN = 70.000; - parameter real CLKPFD_FREQ_MAX = 667.500; - parameter real CLKPFD_FREQ_MIN = 70.000; - parameter real VCOCLK_FREQ_MAX = 1335.000; - parameter real VCOCLK_FREQ_MIN = 600.000; - parameter integer CLKFBOUT_MULT = 5; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN_PERIOD = 0.000; - parameter integer CLKOUT0_DIVIDE = 1; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter CLKOUTPHY_MODE = "VCO_2X"; - parameter COMPENSATION = "AUTO"; - parameter integer DIVCLK_DIVIDE = 1; - parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; - parameter [0:0] IS_CLKIN_INVERTED = 1'b0; - parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REF_JITTER = 0.010; - parameter STARTUP_WAIT = "FALSE"; - output CLKFBOUT; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUTPHY; - output [15:0] DO; - output DRDY; - output LOCKED; - (* invertible_pin = "IS_CLKFBIN_INVERTED" *) - input CLKFBIN; - (* invertible_pin = "IS_CLKIN_INVERTED" *) - input CLKIN; - input CLKOUTPHYEN; - input [6:0] DADDR; - input DCLK; - input DEN; - input [15:0] DI; - input DWE; - (* invertible_pin = "IS_PWRDWN_INVERTED" *) - input PWRDWN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module PLLE3_BASE (...); - parameter integer CLKFBOUT_MULT = 5; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN_PERIOD = 0.000; - parameter integer CLKOUT0_DIVIDE = 1; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter CLKOUTPHY_MODE = "VCO_2X"; - parameter integer DIVCLK_DIVIDE = 1; - parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; - parameter [0:0] IS_CLKIN_INVERTED = 1'b0; - parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REF_JITTER = 0.010; - parameter STARTUP_WAIT = "FALSE"; - output CLKFBOUT; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUTPHY; - output LOCKED; - (* invertible_pin = "IS_CLKFBIN_INVERTED" *) - input CLKFBIN; - (* invertible_pin = "IS_CLKIN_INVERTED" *) - input CLKIN; - input CLKOUTPHYEN; - (* invertible_pin = "IS_PWRDWN_INVERTED" *) - input PWRDWN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module MMCME4_ADV (...); - parameter real CLKIN_FREQ_MAX = 1066.000; - parameter real CLKIN_FREQ_MIN = 10.000; - parameter real CLKPFD_FREQ_MAX = 550.000; - parameter real CLKPFD_FREQ_MIN = 10.000; - parameter real VCOCLK_FREQ_MAX = 1600.000; - parameter real VCOCLK_FREQ_MIN = 800.000; - parameter BANDWIDTH = "OPTIMIZED"; - parameter real CLKFBOUT_MULT_F = 5.000; - parameter real CLKFBOUT_PHASE = 0.000; - parameter CLKFBOUT_USE_FINE_PS = "FALSE"; - parameter real CLKIN1_PERIOD = 0.000; - parameter real CLKIN2_PERIOD = 0.000; - parameter real CLKOUT0_DIVIDE_F = 1.000; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter CLKOUT0_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter CLKOUT1_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT2_DIVIDE = 1; - parameter real CLKOUT2_DUTY_CYCLE = 0.500; - parameter real CLKOUT2_PHASE = 0.000; - parameter CLKOUT2_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT3_DIVIDE = 1; - parameter real CLKOUT3_DUTY_CYCLE = 0.500; - parameter real CLKOUT3_PHASE = 0.000; - parameter CLKOUT3_USE_FINE_PS = "FALSE"; - parameter CLKOUT4_CASCADE = "FALSE"; - parameter integer CLKOUT4_DIVIDE = 1; - parameter real CLKOUT4_DUTY_CYCLE = 0.500; - parameter real CLKOUT4_PHASE = 0.000; - parameter CLKOUT4_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT5_DIVIDE = 1; - parameter real CLKOUT5_DUTY_CYCLE = 0.500; - parameter real CLKOUT5_PHASE = 0.000; - parameter CLKOUT5_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT6_DIVIDE = 1; - parameter real CLKOUT6_DUTY_CYCLE = 0.500; - parameter real CLKOUT6_PHASE = 0.000; - parameter CLKOUT6_USE_FINE_PS = "FALSE"; - parameter COMPENSATION = "AUTO"; - parameter integer DIVCLK_DIVIDE = 1; - parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; - parameter [0:0] IS_CLKIN1_INVERTED = 1'b0; - parameter [0:0] IS_CLKIN2_INVERTED = 1'b0; - parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0; - parameter [0:0] IS_PSEN_INVERTED = 1'b0; - parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0; - parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REF_JITTER1 = 0.010; - parameter real REF_JITTER2 = 0.010; - parameter SS_EN = "FALSE"; - parameter SS_MODE = "CENTER_HIGH"; - parameter integer SS_MOD_PERIOD = 10000; - parameter STARTUP_WAIT = "FALSE"; - output CDDCDONE; - output CLKFBOUT; - output CLKFBOUTB; - output CLKFBSTOPPED; - output CLKINSTOPPED; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUT2; - output CLKOUT2B; - output CLKOUT3; - output CLKOUT3B; - output CLKOUT4; - output CLKOUT5; - output CLKOUT6; - output [15:0] DO; - output DRDY; - output LOCKED; - output PSDONE; - input CDDCREQ; - (* invertible_pin = "IS_CLKFBIN_INVERTED" *) - input CLKFBIN; - (* invertible_pin = "IS_CLKIN1_INVERTED" *) - input CLKIN1; - (* invertible_pin = "IS_CLKIN2_INVERTED" *) - input CLKIN2; - (* invertible_pin = "IS_CLKINSEL_INVERTED" *) - input CLKINSEL; - input [6:0] DADDR; - input DCLK; - input DEN; - input [15:0] DI; - input DWE; - input PSCLK; - (* invertible_pin = "IS_PSEN_INVERTED" *) - input PSEN; - (* invertible_pin = "IS_PSINCDEC_INVERTED" *) - input PSINCDEC; - (* invertible_pin = "IS_PWRDWN_INVERTED" *) - input PWRDWN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module MMCME4_BASE (...); - parameter BANDWIDTH = "OPTIMIZED"; - parameter real CLKFBOUT_MULT_F = 5.000; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN1_PERIOD = 0.000; - parameter real CLKOUT0_DIVIDE_F = 1.000; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter integer CLKOUT2_DIVIDE = 1; - parameter real CLKOUT2_DUTY_CYCLE = 0.500; - parameter real CLKOUT2_PHASE = 0.000; - parameter integer CLKOUT3_DIVIDE = 1; - parameter real CLKOUT3_DUTY_CYCLE = 0.500; - parameter real CLKOUT3_PHASE = 0.000; - parameter CLKOUT4_CASCADE = "FALSE"; - parameter integer CLKOUT4_DIVIDE = 1; - parameter real CLKOUT4_DUTY_CYCLE = 0.500; - parameter real CLKOUT4_PHASE = 0.000; - parameter integer CLKOUT5_DIVIDE = 1; - parameter real CLKOUT5_DUTY_CYCLE = 0.500; - parameter real CLKOUT5_PHASE = 0.000; - parameter integer CLKOUT6_DIVIDE = 1; - parameter real CLKOUT6_DUTY_CYCLE = 0.500; - parameter real CLKOUT6_PHASE = 0.000; - parameter integer DIVCLK_DIVIDE = 1; - parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; - parameter [0:0] IS_CLKIN1_INVERTED = 1'b0; - parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REF_JITTER1 = 0.010; - parameter STARTUP_WAIT = "FALSE"; - output CLKFBOUT; - output CLKFBOUTB; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUT2; - output CLKOUT2B; - output CLKOUT3; - output CLKOUT3B; - output CLKOUT4; - output CLKOUT5; - output CLKOUT6; - output LOCKED; - (* invertible_pin = "IS_CLKFBIN_INVERTED" *) - input CLKFBIN; - (* invertible_pin = "IS_CLKIN1_INVERTED" *) - input CLKIN1; - (* invertible_pin = "IS_PWRDWN_INVERTED" *) - input PWRDWN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module PLLE4_ADV (...); - parameter real CLKIN_FREQ_MAX = 1066.000; - parameter real CLKIN_FREQ_MIN = 70.000; - parameter real CLKPFD_FREQ_MAX = 667.500; - parameter real CLKPFD_FREQ_MIN = 70.000; - parameter real VCOCLK_FREQ_MAX = 1500.000; - parameter real VCOCLK_FREQ_MIN = 750.000; - parameter integer CLKFBOUT_MULT = 5; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN_PERIOD = 0.000; - parameter integer CLKOUT0_DIVIDE = 1; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter CLKOUTPHY_MODE = "VCO_2X"; - parameter COMPENSATION = "AUTO"; - parameter integer DIVCLK_DIVIDE = 1; - parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; - parameter [0:0] IS_CLKIN_INVERTED = 1'b0; - parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REF_JITTER = 0.010; - parameter STARTUP_WAIT = "FALSE"; - output CLKFBOUT; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUTPHY; - output [15:0] DO; - output DRDY; - output LOCKED; - (* invertible_pin = "IS_CLKFBIN_INVERTED" *) - input CLKFBIN; - (* invertible_pin = "IS_CLKIN_INVERTED" *) - input CLKIN; - input CLKOUTPHYEN; - input [6:0] DADDR; - input DCLK; - input DEN; - input [15:0] DI; - input DWE; - (* invertible_pin = "IS_PWRDWN_INVERTED" *) - input PWRDWN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module PLLE4_BASE (...); - parameter integer CLKFBOUT_MULT = 5; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN_PERIOD = 0.000; - parameter integer CLKOUT0_DIVIDE = 1; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter CLKOUTPHY_MODE = "VCO_2X"; - parameter integer DIVCLK_DIVIDE = 1; - parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; - parameter [0:0] IS_CLKIN_INVERTED = 1'b0; - parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REF_JITTER = 0.010; - parameter STARTUP_WAIT = "FALSE"; - output CLKFBOUT; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUTPHY; - output LOCKED; - (* invertible_pin = "IS_CLKFBIN_INVERTED" *) - input CLKFBIN; - (* invertible_pin = "IS_CLKIN_INVERTED" *) - input CLKIN; - input CLKOUTPHYEN; - (* invertible_pin = "IS_PWRDWN_INVERTED" *) - input PWRDWN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module BUFT (...); - output O; - input I; - input T; -endmodule - -module IN_FIFO (...); - parameter integer ALMOST_EMPTY_VALUE = 1; - parameter integer ALMOST_FULL_VALUE = 1; - parameter ARRAY_MODE = "ARRAY_MODE_4_X_8"; - parameter SYNCHRONOUS_MODE = "FALSE"; - output ALMOSTEMPTY; - output ALMOSTFULL; - output EMPTY; - output FULL; - output [7:0] Q0; - output [7:0] Q1; - output [7:0] Q2; - output [7:0] Q3; - output [7:0] Q4; - output [7:0] Q5; - output [7:0] Q6; - output [7:0] Q7; - output [7:0] Q8; - output [7:0] Q9; - (* clkbuf_sink *) - input RDCLK; - input RDEN; - input RESET; - (* clkbuf_sink *) - input WRCLK; - input WREN; - input [3:0] D0; - input [3:0] D1; - input [3:0] D2; - input [3:0] D3; - input [3:0] D4; - input [3:0] D7; - input [3:0] D8; - input [3:0] D9; - input [7:0] D5; - input [7:0] D6; -endmodule - -module OUT_FIFO (...); - parameter integer ALMOST_EMPTY_VALUE = 1; - parameter integer ALMOST_FULL_VALUE = 1; - parameter ARRAY_MODE = "ARRAY_MODE_8_X_4"; - parameter OUTPUT_DISABLE = "FALSE"; - parameter SYNCHRONOUS_MODE = "FALSE"; - output ALMOSTEMPTY; - output ALMOSTFULL; - output EMPTY; - output FULL; - output [3:0] Q0; - output [3:0] Q1; - output [3:0] Q2; - output [3:0] Q3; - output [3:0] Q4; - output [3:0] Q7; - output [3:0] Q8; - output [3:0] Q9; - output [7:0] Q5; - output [7:0] Q6; - (* clkbuf_sink *) - input RDCLK; - input RDEN; - input RESET; - (* clkbuf_sink *) - input WRCLK; - input WREN; - input [7:0] D0; - input [7:0] D1; - input [7:0] D2; - input [7:0] D3; - input [7:0] D4; - input [7:0] D5; - input [7:0] D6; - input [7:0] D7; - input [7:0] D8; - input [7:0] D9; -endmodule - -module HARD_SYNC (...); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter integer LATENCY = 2; - output DOUT; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - input DIN; -endmodule - -(* keep *) -module STARTUP_SPARTAN3 (...); - input CLK; - input GSR; - input GTS; -endmodule - -(* keep *) -module STARTUP_SPARTAN3E (...); - input CLK; - input GSR; - input GTS; - input MBT; -endmodule - -(* keep *) -module STARTUP_SPARTAN3A (...); - input CLK; - input GSR; - input GTS; -endmodule - -(* keep *) -module STARTUP_SPARTAN6 (...); - output CFGCLK; - output CFGMCLK; - output EOS; - input CLK; - input GSR; - input GTS; - input KEYCLEARB; -endmodule - -(* keep *) -module STARTUP_VIRTEX4 (...); - output EOS; - input CLK; - input GSR; - input GTS; - input USRCCLKO; - input USRCCLKTS; - input USRDONEO; - input USRDONETS; -endmodule - -(* keep *) -module STARTUP_VIRTEX5 (...); - output CFGCLK; - output CFGMCLK; - output DINSPI; - output EOS; - output TCKSPI; - input CLK; - input GSR; - input GTS; - input USRCCLKO; - input USRCCLKTS; - input USRDONEO; - input USRDONETS; -endmodule - -(* keep *) -module STARTUP_VIRTEX6 (...); - parameter PROG_USR = "FALSE"; - output CFGCLK; - output CFGMCLK; - output DINSPI; - output EOS; - output PREQ; - output TCKSPI; - input CLK; - input GSR; - input GTS; - input KEYCLEARB; - input PACK; - input USRCCLKO; - input USRCCLKTS; - input USRDONEO; - input USRDONETS; -endmodule - -(* keep *) -module STARTUPE2 (...); - parameter PROG_USR = "FALSE"; - parameter real SIM_CCLK_FREQ = 0.0; - output CFGCLK; - output CFGMCLK; - output EOS; - output PREQ; - input CLK; - input GSR; - input GTS; - input KEYCLEARB; - input PACK; - input USRCCLKO; - input USRCCLKTS; - input USRDONEO; - input USRDONETS; -endmodule - -(* keep *) -module STARTUPE3 (...); - parameter PROG_USR = "FALSE"; - parameter real SIM_CCLK_FREQ = 0.0; - output CFGCLK; - output CFGMCLK; - output [3:0] DI; - output EOS; - output PREQ; - input [3:0] DO; - input [3:0] DTS; - input FCSBO; - input FCSBTS; - input GSR; - input GTS; - input KEYCLEARB; - input PACK; - input USRCCLKO; - input USRCCLKTS; - input USRDONEO; - input USRDONETS; -endmodule - -(* keep *) -module CAPTURE_SPARTAN3 (...); - parameter ONESHOT = "FALSE"; - input CAP; - input CLK; -endmodule - -(* keep *) -module CAPTURE_SPARTAN3A (...); - parameter ONESHOT = "TRUE"; - input CAP; - input CLK; -endmodule - -(* keep *) -module CAPTURE_VIRTEX4 (...); - parameter ONESHOT = "TRUE"; - input CAP; - input CLK; -endmodule - -(* keep *) -module CAPTURE_VIRTEX5 (...); - parameter ONESHOT = "TRUE"; - input CAP; - input CLK; -endmodule - -(* keep *) -module CAPTURE_VIRTEX6 (...); - parameter ONESHOT = "TRUE"; - input CAP; - input CLK; -endmodule - -(* keep *) -module CAPTUREE2 (...); - parameter ONESHOT = "TRUE"; - input CAP; - input CLK; -endmodule - -(* keep *) -module ICAP_SPARTAN3A (...); - output BUSY; - output [7:0] O; - input CE; - input CLK; - input WRITE; - input [7:0] I; -endmodule - -(* keep *) -module ICAP_SPARTAN6 (...); - parameter DEVICE_ID = 32'h04000093; - parameter SIM_CFG_FILE_NAME = "NONE"; - output BUSY; - output [15:0] O; - input CLK; - input CE; - input WRITE; - input [15:0] I; -endmodule - -(* keep *) -module ICAP_VIRTEX4 (...); - parameter ICAP_WIDTH = "X8"; - output BUSY; - output [31:0] O; - input CE; - input CLK; - input WRITE; - input [31:0] I; -endmodule - -(* keep *) -module ICAP_VIRTEX5 (...); - parameter ICAP_WIDTH = "X8"; - output BUSY; - output [31:0] O; - input CE; - input CLK; - input WRITE; - input [31:0] I; -endmodule - -(* keep *) -module ICAP_VIRTEX6 (...); - parameter [31:0] DEVICE_ID = 32'h04244093; - parameter ICAP_WIDTH = "X8"; - parameter SIM_CFG_FILE_NAME = "NONE"; - output BUSY; - output [31:0] O; - input CLK; - input CSB; - input RDWRB; - input [31:0] I; -endmodule - -(* keep *) -module ICAPE2 (...); - parameter [31:0] DEVICE_ID = 32'h04244093; - parameter ICAP_WIDTH = "X32"; - parameter SIM_CFG_FILE_NAME = "NONE"; - output [31:0] O; - input CLK; - input CSIB; - input RDWRB; - input [31:0] I; -endmodule - -(* keep *) -module ICAPE3 (...); - parameter [31:0] DEVICE_ID = 32'h03628093; - parameter ICAP_AUTO_SWITCH = "DISABLE"; - parameter SIM_CFG_FILE_NAME = "NONE"; - output AVAIL; - output [31:0] O; - output PRDONE; - output PRERROR; - input CLK; - input CSIB; - input RDWRB; - input [31:0] I; -endmodule - -(* keep *) -module BSCAN_SPARTAN3 (...); - output CAPTURE; - output DRCK1; - output DRCK2; - output RESET; - output SEL1; - output SEL2; - output SHIFT; - output TDI; - output UPDATE; - input TDO1; - input TDO2; -endmodule - -(* keep *) -module BSCAN_SPARTAN3A (...); - output CAPTURE; - output DRCK1; - output DRCK2; - output RESET; - output SEL1; - output SEL2; - output SHIFT; - output TCK; - output TDI; - output TMS; - output UPDATE; - input TDO1; - input TDO2; -endmodule - -(* keep *) -module BSCAN_SPARTAN6 (...); - parameter integer JTAG_CHAIN = 1; - output CAPTURE; - output DRCK; - output RESET; - output RUNTEST; - output SEL; - output SHIFT; - output TCK; - output TDI; - output TMS; - output UPDATE; - input TDO; -endmodule - -(* keep *) -module BSCAN_VIRTEX4 (...); - parameter integer JTAG_CHAIN = 1; - output CAPTURE; - output DRCK; - output RESET; - output SEL; - output SHIFT; - output TDI; - output UPDATE; - input TDO; -endmodule - -(* keep *) -module BSCAN_VIRTEX5 (...); - parameter integer JTAG_CHAIN = 1; - output CAPTURE; - output DRCK; - output RESET; - output SEL; - output SHIFT; - output TDI; - output UPDATE; - input TDO; -endmodule - -(* keep *) -module BSCAN_VIRTEX6 (...); - parameter DISABLE_JTAG = "FALSE"; - parameter integer JTAG_CHAIN = 1; - output CAPTURE; - output DRCK; - output RESET; - output RUNTEST; - output SEL; - output SHIFT; - output TCK; - output TDI; - output TMS; - output UPDATE; - input TDO; -endmodule - -(* keep *) -module BSCANE2 (...); - parameter DISABLE_JTAG = "FALSE"; - parameter integer JTAG_CHAIN = 1; - output CAPTURE; - output DRCK; - output RESET; - output RUNTEST; - output SEL; - output SHIFT; - output TCK; - output TDI; - output TMS; - output UPDATE; - input TDO; -endmodule - -module DNA_PORT (...); - parameter [56:0] SIM_DNA_VALUE = 57'h0; - output DOUT; - input CLK; - input DIN; - input READ; - input SHIFT; -endmodule - -module DNA_PORTE2 (...); - parameter [95:0] SIM_DNA_VALUE = 96'h000000000000000000000000; - output DOUT; - input CLK; - input DIN; - input READ; - input SHIFT; -endmodule - -module FRAME_ECC_VIRTEX4 (...); - output ERROR; - output [11:0] SYNDROME; - output SYNDROMEVALID; -endmodule - -module FRAME_ECC_VIRTEX5 (...); - output CRCERROR; - output ECCERROR; - output SYNDROMEVALID; - output [11:0] SYNDROME; -endmodule - -module FRAME_ECC_VIRTEX6 (...); - parameter FARSRC = "EFAR"; - parameter FRAME_RBT_IN_FILENAME = "NONE"; - output CRCERROR; - output ECCERROR; - output ECCERRORSINGLE; - output SYNDROMEVALID; - output [12:0] SYNDROME; - output [23:0] FAR; - output [4:0] SYNBIT; - output [6:0] SYNWORD; -endmodule - -module FRAME_ECCE2 (...); - parameter FARSRC = "EFAR"; - parameter FRAME_RBT_IN_FILENAME = "NONE"; - output CRCERROR; - output ECCERROR; - output ECCERRORSINGLE; - output SYNDROMEVALID; - output [12:0] SYNDROME; - output [25:0] FAR; - output [4:0] SYNBIT; - output [6:0] SYNWORD; -endmodule - -module FRAME_ECCE3 (...); - output CRCERROR; - output ECCERRORNOTSINGLE; - output ECCERRORSINGLE; - output ENDOFFRAME; - output ENDOFSCAN; - output [25:0] FAR; - input [1:0] FARSEL; - input ICAPBOTCLK; - input ICAPTOPCLK; -endmodule - -module FRAME_ECCE4 (...); - output CRCERROR; - output ECCERRORNOTSINGLE; - output ECCERRORSINGLE; - output ENDOFFRAME; - output ENDOFSCAN; - output [26:0] FAR; - input [1:0] FARSEL; - input ICAPBOTCLK; - input ICAPTOPCLK; -endmodule - -module USR_ACCESS_VIRTEX4 (...); - output [31:0] DATA; - output DATAVALID; -endmodule - -module USR_ACCESS_VIRTEX5 (...); - output CFGCLK; - output [31:0] DATA; - output DATAVALID; -endmodule - -module USR_ACCESS_VIRTEX6 (...); - output CFGCLK; - output [31:0] DATA; - output DATAVALID; -endmodule - -module USR_ACCESSE2 (...); - output CFGCLK; - output DATAVALID; - output [31:0] DATA; -endmodule - -module POST_CRC_INTERNAL (...); - output CRCERROR; -endmodule - -(* keep *) -module SUSPEND_SYNC (...); - output SREQ; - input CLK; - input SACK; -endmodule - -(* keep *) -module KEY_CLEAR (...); - input KEYCLEARB; -endmodule - -(* keep *) -module MASTER_JTAG (...); - output TDO; - input TCK; - input TDI; - input TMS; -endmodule - -(* keep *) -module SPI_ACCESS (...); - parameter SIM_DELAY_TYPE = "SCALED"; - parameter SIM_DEVICE = "3S1400AN"; - parameter SIM_FACTORY_ID = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter SIM_MEM_FILE = "NONE"; - parameter SIM_USER_ID = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; - output MISO; - input CLK; - input CSB; - input MOSI; -endmodule - -module EFUSE_USR (...); - parameter [31:0] SIM_EFUSE_VALUE = 32'h00000000; - output [31:0] EFUSEUSR; -endmodule - -(* keep *) -module SYSMON (...); - parameter [15:0] INIT_40 = 16'h0; - parameter [15:0] INIT_41 = 16'h0; - parameter [15:0] INIT_42 = 16'h0800; - parameter [15:0] INIT_43 = 16'h0; - parameter [15:0] INIT_44 = 16'h0; - parameter [15:0] INIT_45 = 16'h0; - parameter [15:0] INIT_46 = 16'h0; - parameter [15:0] INIT_47 = 16'h0; - parameter [15:0] INIT_48 = 16'h0; - parameter [15:0] INIT_49 = 16'h0; - parameter [15:0] INIT_4A = 16'h0; - parameter [15:0] INIT_4B = 16'h0; - parameter [15:0] INIT_4C = 16'h0; - parameter [15:0] INIT_4D = 16'h0; - parameter [15:0] INIT_4E = 16'h0; - parameter [15:0] INIT_4F = 16'h0; - parameter [15:0] INIT_50 = 16'h0; - parameter [15:0] INIT_51 = 16'h0; - parameter [15:0] INIT_52 = 16'h0; - parameter [15:0] INIT_53 = 16'h0; - parameter [15:0] INIT_54 = 16'h0; - parameter [15:0] INIT_55 = 16'h0; - parameter [15:0] INIT_56 = 16'h0; - parameter [15:0] INIT_57 = 16'h0; - parameter SIM_DEVICE = "VIRTEX5"; - parameter SIM_MONITOR_FILE = "design.txt"; - output BUSY; - output DRDY; - output EOC; - output EOS; - output JTAGBUSY; - output JTAGLOCKED; - output JTAGMODIFIED; - output OT; - output [15:0] DO; - output [2:0] ALM; - output [4:0] CHANNEL; - input CONVST; - input CONVSTCLK; - input DCLK; - input DEN; - input DWE; - input RESET; - input VN; - input VP; - input [15:0] DI; - input [15:0] VAUXN; - input [15:0] VAUXP; - input [6:0] DADDR; -endmodule - -(* keep *) -module XADC (...); - parameter [15:0] INIT_40 = 16'h0; - parameter [15:0] INIT_41 = 16'h0; - parameter [15:0] INIT_42 = 16'h0800; - parameter [15:0] INIT_43 = 16'h0; - parameter [15:0] INIT_44 = 16'h0; - parameter [15:0] INIT_45 = 16'h0; - parameter [15:0] INIT_46 = 16'h0; - parameter [15:0] INIT_47 = 16'h0; - parameter [15:0] INIT_48 = 16'h0; - parameter [15:0] INIT_49 = 16'h0; - parameter [15:0] INIT_4A = 16'h0; - parameter [15:0] INIT_4B = 16'h0; - parameter [15:0] INIT_4C = 16'h0; - parameter [15:0] INIT_4D = 16'h0; - parameter [15:0] INIT_4E = 16'h0; - parameter [15:0] INIT_4F = 16'h0; - parameter [15:0] INIT_50 = 16'h0; - parameter [15:0] INIT_51 = 16'h0; - parameter [15:0] INIT_52 = 16'h0; - parameter [15:0] INIT_53 = 16'h0; - parameter [15:0] INIT_54 = 16'h0; - parameter [15:0] INIT_55 = 16'h0; - parameter [15:0] INIT_56 = 16'h0; - parameter [15:0] INIT_57 = 16'h0; - parameter [15:0] INIT_58 = 16'h0; - parameter [15:0] INIT_59 = 16'h0; - parameter [15:0] INIT_5A = 16'h0; - parameter [15:0] INIT_5B = 16'h0; - parameter [15:0] INIT_5C = 16'h0; - parameter [15:0] INIT_5D = 16'h0; - parameter [15:0] INIT_5E = 16'h0; - parameter [15:0] INIT_5F = 16'h0; - parameter IS_CONVSTCLK_INVERTED = 1'b0; - parameter IS_DCLK_INVERTED = 1'b0; - parameter SIM_DEVICE = "7SERIES"; - parameter SIM_MONITOR_FILE = "design.txt"; - output BUSY; - output DRDY; - output EOC; - output EOS; - output JTAGBUSY; - output JTAGLOCKED; - output JTAGMODIFIED; - output OT; - output [15:0] DO; - output [7:0] ALM; - output [4:0] CHANNEL; - output [4:0] MUXADDR; - input CONVST; - (* invertible_pin = "IS_CONVSTCLK_INVERTED" *) - input CONVSTCLK; - (* invertible_pin = "IS_DCLK_INVERTED" *) - input DCLK; - input DEN; - input DWE; - input RESET; - input VN; - input VP; - input [15:0] DI; - input [15:0] VAUXN; - input [15:0] VAUXP; - input [6:0] DADDR; -endmodule - -(* keep *) -module SYSMONE1 (...); - parameter [15:0] INIT_40 = 16'h0; - parameter [15:0] INIT_41 = 16'h0; - parameter [15:0] INIT_42 = 16'h0; - parameter [15:0] INIT_43 = 16'h0; - parameter [15:0] INIT_44 = 16'h0; - parameter [15:0] INIT_45 = 16'h0; - parameter [15:0] INIT_46 = 16'h0; - parameter [15:0] INIT_47 = 16'h0; - parameter [15:0] INIT_48 = 16'h0; - parameter [15:0] INIT_49 = 16'h0; - parameter [15:0] INIT_4A = 16'h0; - parameter [15:0] INIT_4B = 16'h0; - parameter [15:0] INIT_4C = 16'h0; - parameter [15:0] INIT_4D = 16'h0; - parameter [15:0] INIT_4E = 16'h0; - parameter [15:0] INIT_4F = 16'h0; - parameter [15:0] INIT_50 = 16'h0; - parameter [15:0] INIT_51 = 16'h0; - parameter [15:0] INIT_52 = 16'h0; - parameter [15:0] INIT_53 = 16'h0; - parameter [15:0] INIT_54 = 16'h0; - parameter [15:0] INIT_55 = 16'h0; - parameter [15:0] INIT_56 = 16'h0; - parameter [15:0] INIT_57 = 16'h0; - parameter [15:0] INIT_58 = 16'h0; - parameter [15:0] INIT_59 = 16'h0; - parameter [15:0] INIT_5A = 16'h0; - parameter [15:0] INIT_5B = 16'h0; - parameter [15:0] INIT_5C = 16'h0; - parameter [15:0] INIT_5D = 16'h0; - parameter [15:0] INIT_5E = 16'h0; - parameter [15:0] INIT_5F = 16'h0; - parameter [15:0] INIT_60 = 16'h0; - parameter [15:0] INIT_61 = 16'h0; - parameter [15:0] INIT_62 = 16'h0; - parameter [15:0] INIT_63 = 16'h0; - parameter [15:0] INIT_64 = 16'h0; - parameter [15:0] INIT_65 = 16'h0; - parameter [15:0] INIT_66 = 16'h0; - parameter [15:0] INIT_67 = 16'h0; - parameter [15:0] INIT_68 = 16'h0; - parameter [15:0] INIT_69 = 16'h0; - parameter [15:0] INIT_6A = 16'h0; - parameter [15:0] INIT_6B = 16'h0; - parameter [15:0] INIT_6C = 16'h0; - parameter [15:0] INIT_6D = 16'h0; - parameter [15:0] INIT_6E = 16'h0; - parameter [15:0] INIT_6F = 16'h0; - parameter [15:0] INIT_70 = 16'h0; - parameter [15:0] INIT_71 = 16'h0; - parameter [15:0] INIT_72 = 16'h0; - parameter [15:0] INIT_73 = 16'h0; - parameter [15:0] INIT_74 = 16'h0; - parameter [15:0] INIT_75 = 16'h0; - parameter [15:0] INIT_76 = 16'h0; - parameter [15:0] INIT_77 = 16'h0; - parameter [15:0] INIT_78 = 16'h0; - parameter [15:0] INIT_79 = 16'h0; - parameter [15:0] INIT_7A = 16'h0; - parameter [15:0] INIT_7B = 16'h0; - parameter [15:0] INIT_7C = 16'h0; - parameter [15:0] INIT_7D = 16'h0; - parameter [15:0] INIT_7E = 16'h0; - parameter [15:0] INIT_7F = 16'h0; - parameter [0:0] IS_CONVSTCLK_INVERTED = 1'b0; - parameter [0:0] IS_DCLK_INVERTED = 1'b0; - parameter SIM_MONITOR_FILE = "design.txt"; - parameter integer SYSMON_VUSER0_BANK = 0; - parameter SYSMON_VUSER0_MONITOR = "NONE"; - parameter integer SYSMON_VUSER1_BANK = 0; - parameter SYSMON_VUSER1_MONITOR = "NONE"; - parameter integer SYSMON_VUSER2_BANK = 0; - parameter SYSMON_VUSER2_MONITOR = "NONE"; - parameter integer SYSMON_VUSER3_BANK = 0; - parameter SYSMON_VUSER3_MONITOR = "NONE"; - output [15:0] ALM; - output BUSY; - output [5:0] CHANNEL; - output [15:0] DO; - output DRDY; - output EOC; - output EOS; - output I2C_SCLK_TS; - output I2C_SDA_TS; - output JTAGBUSY; - output JTAGLOCKED; - output JTAGMODIFIED; - output [4:0] MUXADDR; - output OT; - input CONVST; - (* invertible_pin = "IS_CONVSTCLK_INVERTED" *) - input CONVSTCLK; - input [7:0] DADDR; - (* invertible_pin = "IS_DCLK_INVERTED" *) - input DCLK; - input DEN; - input [15:0] DI; - input DWE; - input I2C_SCLK; - input I2C_SDA; - input RESET; - input [15:0] VAUXN; - input [15:0] VAUXP; - input VN; - input VP; -endmodule - -(* keep *) -module SYSMONE4 (...); - parameter [15:0] COMMON_N_SOURCE = 16'hFFFF; - parameter [15:0] INIT_40 = 16'h0000; - parameter [15:0] INIT_41 = 16'h0000; - parameter [15:0] INIT_42 = 16'h0000; - parameter [15:0] INIT_43 = 16'h0000; - parameter [15:0] INIT_44 = 16'h0000; - parameter [15:0] INIT_45 = 16'h0000; - parameter [15:0] INIT_46 = 16'h0000; - parameter [15:0] INIT_47 = 16'h0000; - parameter [15:0] INIT_48 = 16'h0000; - parameter [15:0] INIT_49 = 16'h0000; - parameter [15:0] INIT_4A = 16'h0000; - parameter [15:0] INIT_4B = 16'h0000; - parameter [15:0] INIT_4C = 16'h0000; - parameter [15:0] INIT_4D = 16'h0000; - parameter [15:0] INIT_4E = 16'h0000; - parameter [15:0] INIT_4F = 16'h0000; - parameter [15:0] INIT_50 = 16'h0000; - parameter [15:0] INIT_51 = 16'h0000; - parameter [15:0] INIT_52 = 16'h0000; - parameter [15:0] INIT_53 = 16'h0000; - parameter [15:0] INIT_54 = 16'h0000; - parameter [15:0] INIT_55 = 16'h0000; - parameter [15:0] INIT_56 = 16'h0000; - parameter [15:0] INIT_57 = 16'h0000; - parameter [15:0] INIT_58 = 16'h0000; - parameter [15:0] INIT_59 = 16'h0000; - parameter [15:0] INIT_5A = 16'h0000; - parameter [15:0] INIT_5B = 16'h0000; - parameter [15:0] INIT_5C = 16'h0000; - parameter [15:0] INIT_5D = 16'h0000; - parameter [15:0] INIT_5E = 16'h0000; - parameter [15:0] INIT_5F = 16'h0000; - parameter [15:0] INIT_60 = 16'h0000; - parameter [15:0] INIT_61 = 16'h0000; - parameter [15:0] INIT_62 = 16'h0000; - parameter [15:0] INIT_63 = 16'h0000; - parameter [15:0] INIT_64 = 16'h0000; - parameter [15:0] INIT_65 = 16'h0000; - parameter [15:0] INIT_66 = 16'h0000; - parameter [15:0] INIT_67 = 16'h0000; - parameter [15:0] INIT_68 = 16'h0000; - parameter [15:0] INIT_69 = 16'h0000; - parameter [15:0] INIT_6A = 16'h0000; - parameter [15:0] INIT_6B = 16'h0000; - parameter [15:0] INIT_6C = 16'h0000; - parameter [15:0] INIT_6D = 16'h0000; - parameter [15:0] INIT_6E = 16'h0000; - parameter [15:0] INIT_6F = 16'h0000; - parameter [15:0] INIT_70 = 16'h0000; - parameter [15:0] INIT_71 = 16'h0000; - parameter [15:0] INIT_72 = 16'h0000; - parameter [15:0] INIT_73 = 16'h0000; - parameter [15:0] INIT_74 = 16'h0000; - parameter [15:0] INIT_75 = 16'h0000; - parameter [15:0] INIT_76 = 16'h0000; - parameter [15:0] INIT_77 = 16'h0000; - parameter [15:0] INIT_78 = 16'h0000; - parameter [15:0] INIT_79 = 16'h0000; - parameter [15:0] INIT_7A = 16'h0000; - parameter [15:0] INIT_7B = 16'h0000; - parameter [15:0] INIT_7C = 16'h0000; - parameter [15:0] INIT_7D = 16'h0000; - parameter [15:0] INIT_7E = 16'h0000; - parameter [15:0] INIT_7F = 16'h0000; - parameter [0:0] IS_CONVSTCLK_INVERTED = 1'b0; - parameter [0:0] IS_DCLK_INVERTED = 1'b0; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter SIM_MONITOR_FILE = "design.txt"; - parameter integer SYSMON_VUSER0_BANK = 0; - parameter SYSMON_VUSER0_MONITOR = "NONE"; - parameter integer SYSMON_VUSER1_BANK = 0; - parameter SYSMON_VUSER1_MONITOR = "NONE"; - parameter integer SYSMON_VUSER2_BANK = 0; - parameter SYSMON_VUSER2_MONITOR = "NONE"; - parameter integer SYSMON_VUSER3_BANK = 0; - parameter SYSMON_VUSER3_MONITOR = "NONE"; - output [15:0] ADC_DATA; - output [15:0] ALM; - output BUSY; - output [5:0] CHANNEL; - output [15:0] DO; - output DRDY; - output EOC; - output EOS; - output I2C_SCLK_TS; - output I2C_SDA_TS; - output JTAGBUSY; - output JTAGLOCKED; - output JTAGMODIFIED; - output [4:0] MUXADDR; - output OT; - output SMBALERT_TS; - input CONVST; - (* invertible_pin = "IS_CONVSTCLK_INVERTED" *) - input CONVSTCLK; - input [7:0] DADDR; - (* invertible_pin = "IS_DCLK_INVERTED" *) - input DCLK; - input DEN; - input [15:0] DI; - input DWE; - input I2C_SCLK; - input I2C_SDA; - input RESET; - input [15:0] VAUXN; - input [15:0] VAUXP; - input VN; - input VP; -endmodule - -module GTPA1_DUAL (...); - parameter AC_CAP_DIS_0 = "TRUE"; - parameter AC_CAP_DIS_1 = "TRUE"; - parameter integer ALIGN_COMMA_WORD_0 = 1; - parameter integer ALIGN_COMMA_WORD_1 = 1; - parameter integer CB2_INH_CC_PERIOD_0 = 8; - parameter integer CB2_INH_CC_PERIOD_1 = 8; - parameter [4:0] CDR_PH_ADJ_TIME_0 = 5'b01010; - parameter [4:0] CDR_PH_ADJ_TIME_1 = 5'b01010; - parameter integer CHAN_BOND_1_MAX_SKEW_0 = 7; - parameter integer CHAN_BOND_1_MAX_SKEW_1 = 7; - parameter integer CHAN_BOND_2_MAX_SKEW_0 = 1; - parameter integer CHAN_BOND_2_MAX_SKEW_1 = 1; - parameter CHAN_BOND_KEEP_ALIGN_0 = "FALSE"; - parameter CHAN_BOND_KEEP_ALIGN_1 = "FALSE"; - parameter [9:0] CHAN_BOND_SEQ_1_1_0 = 10'b0101111100; - parameter [9:0] CHAN_BOND_SEQ_1_1_1 = 10'b0101111100; - parameter [9:0] CHAN_BOND_SEQ_1_2_0 = 10'b0001001010; - parameter [9:0] CHAN_BOND_SEQ_1_2_1 = 10'b0001001010; - parameter [9:0] CHAN_BOND_SEQ_1_3_0 = 10'b0001001010; - parameter [9:0] CHAN_BOND_SEQ_1_3_1 = 10'b0001001010; - parameter [9:0] CHAN_BOND_SEQ_1_4_0 = 10'b0110111100; - parameter [9:0] CHAN_BOND_SEQ_1_4_1 = 10'b0110111100; - parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_0 = 4'b1111; - parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_1 = 4'b1111; - parameter [9:0] CHAN_BOND_SEQ_2_1_0 = 10'b0110111100; - parameter [9:0] CHAN_BOND_SEQ_2_1_1 = 10'b0110111100; - parameter [9:0] CHAN_BOND_SEQ_2_2_0 = 10'b0100111100; - parameter [9:0] CHAN_BOND_SEQ_2_2_1 = 10'b0100111100; - parameter [9:0] CHAN_BOND_SEQ_2_3_0 = 10'b0100111100; - parameter [9:0] CHAN_BOND_SEQ_2_3_1 = 10'b0100111100; - parameter [9:0] CHAN_BOND_SEQ_2_4_0 = 10'b0100111100; - parameter [9:0] CHAN_BOND_SEQ_2_4_1 = 10'b0100111100; - parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_0 = 4'b1111; - parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_1 = 4'b1111; - parameter CHAN_BOND_SEQ_2_USE_0 = "FALSE"; - parameter CHAN_BOND_SEQ_2_USE_1 = "FALSE"; - parameter integer CHAN_BOND_SEQ_LEN_0 = 1; - parameter integer CHAN_BOND_SEQ_LEN_1 = 1; - parameter integer CLK25_DIVIDER_0 = 4; - parameter integer CLK25_DIVIDER_1 = 4; - parameter CLKINDC_B_0 = "TRUE"; - parameter CLKINDC_B_1 = "TRUE"; - parameter CLKRCV_TRST_0 = "TRUE"; - parameter CLKRCV_TRST_1 = "TRUE"; - parameter CLK_CORRECT_USE_0 = "TRUE"; - parameter CLK_CORRECT_USE_1 = "TRUE"; - parameter integer CLK_COR_ADJ_LEN_0 = 1; - parameter integer CLK_COR_ADJ_LEN_1 = 1; - parameter integer CLK_COR_DET_LEN_0 = 1; - parameter integer CLK_COR_DET_LEN_1 = 1; - parameter CLK_COR_INSERT_IDLE_FLAG_0 = "FALSE"; - parameter CLK_COR_INSERT_IDLE_FLAG_1 = "FALSE"; - parameter CLK_COR_KEEP_IDLE_0 = "FALSE"; - parameter CLK_COR_KEEP_IDLE_1 = "FALSE"; - parameter integer CLK_COR_MAX_LAT_0 = 20; - parameter integer CLK_COR_MAX_LAT_1 = 20; - parameter integer CLK_COR_MIN_LAT_0 = 18; - parameter integer CLK_COR_MIN_LAT_1 = 18; - parameter CLK_COR_PRECEDENCE_0 = "TRUE"; - parameter CLK_COR_PRECEDENCE_1 = "TRUE"; - parameter integer CLK_COR_REPEAT_WAIT_0 = 0; - parameter integer CLK_COR_REPEAT_WAIT_1 = 0; - parameter [9:0] CLK_COR_SEQ_1_1_0 = 10'b0100011100; - parameter [9:0] CLK_COR_SEQ_1_1_1 = 10'b0100011100; - parameter [9:0] CLK_COR_SEQ_1_2_0 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_2_1 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_3_0 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_3_1 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_4_0 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_4_1 = 10'b0000000000; - parameter [3:0] CLK_COR_SEQ_1_ENABLE_0 = 4'b1111; - parameter [3:0] CLK_COR_SEQ_1_ENABLE_1 = 4'b1111; - parameter [9:0] CLK_COR_SEQ_2_1_0 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_2_1_1 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_2_2_0 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_2_2_1 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_2_3_0 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_2_3_1 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_2_4_0 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_2_4_1 = 10'b0000000000; - parameter [3:0] CLK_COR_SEQ_2_ENABLE_0 = 4'b1111; - parameter [3:0] CLK_COR_SEQ_2_ENABLE_1 = 4'b1111; - parameter CLK_COR_SEQ_2_USE_0 = "FALSE"; - parameter CLK_COR_SEQ_2_USE_1 = "FALSE"; - parameter CLK_OUT_GTP_SEL_0 = "REFCLKPLL0"; - parameter CLK_OUT_GTP_SEL_1 = "REFCLKPLL1"; - parameter [1:0] CM_TRIM_0 = 2'b00; - parameter [1:0] CM_TRIM_1 = 2'b00; - parameter [9:0] COMMA_10B_ENABLE_0 = 10'b1111111111; - parameter [9:0] COMMA_10B_ENABLE_1 = 10'b1111111111; - parameter [3:0] COM_BURST_VAL_0 = 4'b1111; - parameter [3:0] COM_BURST_VAL_1 = 4'b1111; - parameter DEC_MCOMMA_DETECT_0 = "TRUE"; - parameter DEC_MCOMMA_DETECT_1 = "TRUE"; - parameter DEC_PCOMMA_DETECT_0 = "TRUE"; - parameter DEC_PCOMMA_DETECT_1 = "TRUE"; - parameter DEC_VALID_COMMA_ONLY_0 = "TRUE"; - parameter DEC_VALID_COMMA_ONLY_1 = "TRUE"; - parameter GTP_CFG_PWRUP_0 = "TRUE"; - parameter GTP_CFG_PWRUP_1 = "TRUE"; - parameter [9:0] MCOMMA_10B_VALUE_0 = 10'b1010000011; - parameter [9:0] MCOMMA_10B_VALUE_1 = 10'b1010000011; - parameter MCOMMA_DETECT_0 = "TRUE"; - parameter MCOMMA_DETECT_1 = "TRUE"; - parameter [2:0] OOBDETECT_THRESHOLD_0 = 3'b110; - parameter [2:0] OOBDETECT_THRESHOLD_1 = 3'b110; - parameter integer OOB_CLK_DIVIDER_0 = 4; - parameter integer OOB_CLK_DIVIDER_1 = 4; - parameter PCI_EXPRESS_MODE_0 = "FALSE"; - parameter PCI_EXPRESS_MODE_1 = "FALSE"; - parameter [9:0] PCOMMA_10B_VALUE_0 = 10'b0101111100; - parameter [9:0] PCOMMA_10B_VALUE_1 = 10'b0101111100; - parameter PCOMMA_DETECT_0 = "TRUE"; - parameter PCOMMA_DETECT_1 = "TRUE"; - parameter [2:0] PLLLKDET_CFG_0 = 3'b101; - parameter [2:0] PLLLKDET_CFG_1 = 3'b101; - parameter [23:0] PLL_COM_CFG_0 = 24'h21680A; - parameter [23:0] PLL_COM_CFG_1 = 24'h21680A; - parameter [7:0] PLL_CP_CFG_0 = 8'h00; - parameter [7:0] PLL_CP_CFG_1 = 8'h00; - parameter integer PLL_DIVSEL_FB_0 = 5; - parameter integer PLL_DIVSEL_FB_1 = 5; - parameter integer PLL_DIVSEL_REF_0 = 2; - parameter integer PLL_DIVSEL_REF_1 = 2; - parameter integer PLL_RXDIVSEL_OUT_0 = 1; - parameter integer PLL_RXDIVSEL_OUT_1 = 1; - parameter PLL_SATA_0 = "FALSE"; - parameter PLL_SATA_1 = "FALSE"; - parameter PLL_SOURCE_0 = "PLL0"; - parameter PLL_SOURCE_1 = "PLL0"; - parameter integer PLL_TXDIVSEL_OUT_0 = 1; - parameter integer PLL_TXDIVSEL_OUT_1 = 1; - parameter [26:0] PMA_CDR_SCAN_0 = 27'h6404040; - parameter [26:0] PMA_CDR_SCAN_1 = 27'h6404040; - parameter [35:0] PMA_COM_CFG_EAST = 36'h000008000; - parameter [35:0] PMA_COM_CFG_WEST = 36'h00000A000; - parameter [6:0] PMA_RXSYNC_CFG_0 = 7'h00; - parameter [6:0] PMA_RXSYNC_CFG_1 = 7'h00; - parameter [24:0] PMA_RX_CFG_0 = 25'h05CE048; - parameter [24:0] PMA_RX_CFG_1 = 25'h05CE048; - parameter [19:0] PMA_TX_CFG_0 = 20'h00082; - parameter [19:0] PMA_TX_CFG_1 = 20'h00082; - parameter RCV_TERM_GND_0 = "FALSE"; - parameter RCV_TERM_GND_1 = "FALSE"; - parameter RCV_TERM_VTTRX_0 = "TRUE"; - parameter RCV_TERM_VTTRX_1 = "TRUE"; - parameter [7:0] RXEQ_CFG_0 = 8'b01111011; - parameter [7:0] RXEQ_CFG_1 = 8'b01111011; - parameter [0:0] RXPRBSERR_LOOPBACK_0 = 1'b0; - parameter [0:0] RXPRBSERR_LOOPBACK_1 = 1'b0; - parameter RX_BUFFER_USE_0 = "TRUE"; - parameter RX_BUFFER_USE_1 = "TRUE"; - parameter RX_DECODE_SEQ_MATCH_0 = "TRUE"; - parameter RX_DECODE_SEQ_MATCH_1 = "TRUE"; - parameter RX_EN_IDLE_HOLD_CDR_0 = "FALSE"; - parameter RX_EN_IDLE_HOLD_CDR_1 = "FALSE"; - parameter RX_EN_IDLE_RESET_BUF_0 = "TRUE"; - parameter RX_EN_IDLE_RESET_BUF_1 = "TRUE"; - parameter RX_EN_IDLE_RESET_FR_0 = "TRUE"; - parameter RX_EN_IDLE_RESET_FR_1 = "TRUE"; - parameter RX_EN_IDLE_RESET_PH_0 = "TRUE"; - parameter RX_EN_IDLE_RESET_PH_1 = "TRUE"; - parameter RX_EN_MODE_RESET_BUF_0 = "TRUE"; - parameter RX_EN_MODE_RESET_BUF_1 = "TRUE"; - parameter [3:0] RX_IDLE_HI_CNT_0 = 4'b1000; - parameter [3:0] RX_IDLE_HI_CNT_1 = 4'b1000; - parameter [3:0] RX_IDLE_LO_CNT_0 = 4'b0000; - parameter [3:0] RX_IDLE_LO_CNT_1 = 4'b0000; - parameter RX_LOSS_OF_SYNC_FSM_0 = "FALSE"; - parameter RX_LOSS_OF_SYNC_FSM_1 = "FALSE"; - parameter integer RX_LOS_INVALID_INCR_0 = 1; - parameter integer RX_LOS_INVALID_INCR_1 = 1; - parameter integer RX_LOS_THRESHOLD_0 = 4; - parameter integer RX_LOS_THRESHOLD_1 = 4; - parameter RX_SLIDE_MODE_0 = "PCS"; - parameter RX_SLIDE_MODE_1 = "PCS"; - parameter RX_STATUS_FMT_0 = "PCIE"; - parameter RX_STATUS_FMT_1 = "PCIE"; - parameter RX_XCLK_SEL_0 = "RXREC"; - parameter RX_XCLK_SEL_1 = "RXREC"; - parameter [2:0] SATA_BURST_VAL_0 = 3'b100; - parameter [2:0] SATA_BURST_VAL_1 = 3'b100; - parameter [2:0] SATA_IDLE_VAL_0 = 3'b011; - parameter [2:0] SATA_IDLE_VAL_1 = 3'b011; - parameter integer SATA_MAX_BURST_0 = 7; - parameter integer SATA_MAX_BURST_1 = 7; - parameter integer SATA_MAX_INIT_0 = 22; - parameter integer SATA_MAX_INIT_1 = 22; - parameter integer SATA_MAX_WAKE_0 = 7; - parameter integer SATA_MAX_WAKE_1 = 7; - parameter integer SATA_MIN_BURST_0 = 4; - parameter integer SATA_MIN_BURST_1 = 4; - parameter integer SATA_MIN_INIT_0 = 12; - parameter integer SATA_MIN_INIT_1 = 12; - parameter integer SATA_MIN_WAKE_0 = 4; - parameter integer SATA_MIN_WAKE_1 = 4; - parameter integer SIM_GTPRESET_SPEEDUP = 0; - parameter SIM_RECEIVER_DETECT_PASS = "FALSE"; - parameter [2:0] SIM_REFCLK0_SOURCE = 3'b000; - parameter [2:0] SIM_REFCLK1_SOURCE = 3'b000; - parameter SIM_TX_ELEC_IDLE_LEVEL = "X"; - parameter SIM_VERSION = "2.0"; - parameter [4:0] TERMINATION_CTRL_0 = 5'b10100; - parameter [4:0] TERMINATION_CTRL_1 = 5'b10100; - parameter TERMINATION_OVRD_0 = "FALSE"; - parameter TERMINATION_OVRD_1 = "FALSE"; - parameter [11:0] TRANS_TIME_FROM_P2_0 = 12'h03C; - parameter [11:0] TRANS_TIME_FROM_P2_1 = 12'h03C; - parameter [7:0] TRANS_TIME_NON_P2_0 = 8'h19; - parameter [7:0] TRANS_TIME_NON_P2_1 = 8'h19; - parameter [9:0] TRANS_TIME_TO_P2_0 = 10'h064; - parameter [9:0] TRANS_TIME_TO_P2_1 = 10'h064; - parameter [31:0] TST_ATTR_0 = 32'h00000000; - parameter [31:0] TST_ATTR_1 = 32'h00000000; - parameter [2:0] TXRX_INVERT_0 = 3'b011; - parameter [2:0] TXRX_INVERT_1 = 3'b011; - parameter TX_BUFFER_USE_0 = "FALSE"; - parameter TX_BUFFER_USE_1 = "FALSE"; - parameter [13:0] TX_DETECT_RX_CFG_0 = 14'h1832; - parameter [13:0] TX_DETECT_RX_CFG_1 = 14'h1832; - parameter [2:0] TX_IDLE_DELAY_0 = 3'b011; - parameter [2:0] TX_IDLE_DELAY_1 = 3'b011; - parameter [1:0] TX_TDCC_CFG_0 = 2'b00; - parameter [1:0] TX_TDCC_CFG_1 = 2'b00; - parameter TX_XCLK_SEL_0 = "TXUSR"; - parameter TX_XCLK_SEL_1 = "TXUSR"; - output DRDY; - output PHYSTATUS0; - output PHYSTATUS1; - output PLLLKDET0; - output PLLLKDET1; - output REFCLKOUT0; - output REFCLKOUT1; - output REFCLKPLL0; - output REFCLKPLL1; - output RESETDONE0; - output RESETDONE1; - output RXBYTEISALIGNED0; - output RXBYTEISALIGNED1; - output RXBYTEREALIGN0; - output RXBYTEREALIGN1; - output RXCHANBONDSEQ0; - output RXCHANBONDSEQ1; - output RXCHANISALIGNED0; - output RXCHANISALIGNED1; - output RXCHANREALIGN0; - output RXCHANREALIGN1; - output RXCOMMADET0; - output RXCOMMADET1; - output RXELECIDLE0; - output RXELECIDLE1; - output RXPRBSERR0; - output RXPRBSERR1; - output RXRECCLK0; - output RXRECCLK1; - output RXVALID0; - output RXVALID1; - output TXN0; - output TXN1; - output TXOUTCLK0; - output TXOUTCLK1; - output TXP0; - output TXP1; - output [15:0] DRPDO; - output [1:0] GTPCLKFBEAST; - output [1:0] GTPCLKFBWEST; - output [1:0] GTPCLKOUT0; - output [1:0] GTPCLKOUT1; - output [1:0] RXLOSSOFSYNC0; - output [1:0] RXLOSSOFSYNC1; - output [1:0] TXBUFSTATUS0; - output [1:0] TXBUFSTATUS1; - output [2:0] RXBUFSTATUS0; - output [2:0] RXBUFSTATUS1; - output [2:0] RXCHBONDO; - output [2:0] RXCLKCORCNT0; - output [2:0] RXCLKCORCNT1; - output [2:0] RXSTATUS0; - output [2:0] RXSTATUS1; - output [31:0] RXDATA0; - output [31:0] RXDATA1; - output [3:0] RXCHARISCOMMA0; - output [3:0] RXCHARISCOMMA1; - output [3:0] RXCHARISK0; - output [3:0] RXCHARISK1; - output [3:0] RXDISPERR0; - output [3:0] RXDISPERR1; - output [3:0] RXNOTINTABLE0; - output [3:0] RXNOTINTABLE1; - output [3:0] RXRUNDISP0; - output [3:0] RXRUNDISP1; - output [3:0] TXKERR0; - output [3:0] TXKERR1; - output [3:0] TXRUNDISP0; - output [3:0] TXRUNDISP1; - output [4:0] RCALOUTEAST; - output [4:0] RCALOUTWEST; - output [4:0] TSTOUT0; - output [4:0] TSTOUT1; - input CLK00; - input CLK01; - input CLK10; - input CLK11; - input CLKINEAST0; - input CLKINEAST1; - input CLKINWEST0; - input CLKINWEST1; - input DCLK; - input DEN; - input DWE; - input GATERXELECIDLE0; - input GATERXELECIDLE1; - input GCLK00; - input GCLK01; - input GCLK10; - input GCLK11; - input GTPRESET0; - input GTPRESET1; - input IGNORESIGDET0; - input IGNORESIGDET1; - input INTDATAWIDTH0; - input INTDATAWIDTH1; - input PLLCLK00; - input PLLCLK01; - input PLLCLK10; - input PLLCLK11; - input PLLLKDETEN0; - input PLLLKDETEN1; - input PLLPOWERDOWN0; - input PLLPOWERDOWN1; - input PRBSCNTRESET0; - input PRBSCNTRESET1; - input REFCLKPWRDNB0; - input REFCLKPWRDNB1; - input RXBUFRESET0; - input RXBUFRESET1; - input RXCDRRESET0; - input RXCDRRESET1; - input RXCHBONDMASTER0; - input RXCHBONDMASTER1; - input RXCHBONDSLAVE0; - input RXCHBONDSLAVE1; - input RXCOMMADETUSE0; - input RXCOMMADETUSE1; - input RXDEC8B10BUSE0; - input RXDEC8B10BUSE1; - input RXENCHANSYNC0; - input RXENCHANSYNC1; - input RXENMCOMMAALIGN0; - input RXENMCOMMAALIGN1; - input RXENPCOMMAALIGN0; - input RXENPCOMMAALIGN1; - input RXENPMAPHASEALIGN0; - input RXENPMAPHASEALIGN1; - input RXN0; - input RXN1; - input RXP0; - input RXP1; - input RXPMASETPHASE0; - input RXPMASETPHASE1; - input RXPOLARITY0; - input RXPOLARITY1; - input RXRESET0; - input RXRESET1; - input RXSLIDE0; - input RXSLIDE1; - input RXUSRCLK0; - input RXUSRCLK1; - input RXUSRCLK20; - input RXUSRCLK21; - input TSTCLK0; - input TSTCLK1; - input TXCOMSTART0; - input TXCOMSTART1; - input TXCOMTYPE0; - input TXCOMTYPE1; - input TXDETECTRX0; - input TXDETECTRX1; - input TXELECIDLE0; - input TXELECIDLE1; - input TXENC8B10BUSE0; - input TXENC8B10BUSE1; - input TXENPMAPHASEALIGN0; - input TXENPMAPHASEALIGN1; - input TXINHIBIT0; - input TXINHIBIT1; - input TXPDOWNASYNCH0; - input TXPDOWNASYNCH1; - input TXPMASETPHASE0; - input TXPMASETPHASE1; - input TXPOLARITY0; - input TXPOLARITY1; - input TXPRBSFORCEERR0; - input TXPRBSFORCEERR1; - input TXRESET0; - input TXRESET1; - input TXUSRCLK0; - input TXUSRCLK1; - input TXUSRCLK20; - input TXUSRCLK21; - input USRCODEERR0; - input USRCODEERR1; - input [11:0] TSTIN0; - input [11:0] TSTIN1; - input [15:0] DI; - input [1:0] GTPCLKFBSEL0EAST; - input [1:0] GTPCLKFBSEL0WEST; - input [1:0] GTPCLKFBSEL1EAST; - input [1:0] GTPCLKFBSEL1WEST; - input [1:0] RXDATAWIDTH0; - input [1:0] RXDATAWIDTH1; - input [1:0] RXEQMIX0; - input [1:0] RXEQMIX1; - input [1:0] RXPOWERDOWN0; - input [1:0] RXPOWERDOWN1; - input [1:0] TXDATAWIDTH0; - input [1:0] TXDATAWIDTH1; - input [1:0] TXPOWERDOWN0; - input [1:0] TXPOWERDOWN1; - input [2:0] LOOPBACK0; - input [2:0] LOOPBACK1; - input [2:0] REFSELDYPLL0; - input [2:0] REFSELDYPLL1; - input [2:0] RXCHBONDI; - input [2:0] RXENPRBSTST0; - input [2:0] RXENPRBSTST1; - input [2:0] TXBUFDIFFCTRL0; - input [2:0] TXBUFDIFFCTRL1; - input [2:0] TXENPRBSTST0; - input [2:0] TXENPRBSTST1; - input [2:0] TXPREEMPHASIS0; - input [2:0] TXPREEMPHASIS1; - input [31:0] TXDATA0; - input [31:0] TXDATA1; - input [3:0] TXBYPASS8B10B0; - input [3:0] TXBYPASS8B10B1; - input [3:0] TXCHARDISPMODE0; - input [3:0] TXCHARDISPMODE1; - input [3:0] TXCHARDISPVAL0; - input [3:0] TXCHARDISPVAL1; - input [3:0] TXCHARISK0; - input [3:0] TXCHARISK1; - input [3:0] TXDIFFCTRL0; - input [3:0] TXDIFFCTRL1; - input [4:0] RCALINEAST; - input [4:0] RCALINWEST; - input [7:0] DADDR; - input [7:0] GTPTEST0; - input [7:0] GTPTEST1; -endmodule - -module GT11_CUSTOM (...); - parameter ALIGN_COMMA_WORD = 1; - parameter BANDGAPSEL = "FALSE"; - parameter BIASRESSEL = "TRUE"; - parameter CCCB_ARBITRATOR_DISABLE = "FALSE"; - parameter CHAN_BOND_LIMIT = 16; - parameter CHAN_BOND_MODE = "NONE"; - parameter CHAN_BOND_ONE_SHOT = "FALSE"; - parameter CHAN_BOND_SEQ_1_1 = 11'b00000000000; - parameter CHAN_BOND_SEQ_1_2 = 11'b00000000000; - parameter CHAN_BOND_SEQ_1_3 = 11'b00000000000; - parameter CHAN_BOND_SEQ_1_4 = 11'b00000000000; - parameter CHAN_BOND_SEQ_1_MASK = 4'b0000; - parameter CHAN_BOND_SEQ_2_1 = 11'b00000000000; - parameter CHAN_BOND_SEQ_2_2 = 11'b00000000000; - parameter CHAN_BOND_SEQ_2_3 = 11'b00000000000; - parameter CHAN_BOND_SEQ_2_4 = 11'b00000000000; - parameter CHAN_BOND_SEQ_2_MASK = 4'b0000; - parameter CHAN_BOND_SEQ_2_USE = "FALSE"; - parameter CHAN_BOND_SEQ_LEN = 1; - parameter CLK_CORRECT_USE = "TRUE"; - parameter CLK_COR_8B10B_DE = "FALSE"; - parameter CLK_COR_MAX_LAT = 36; - parameter CLK_COR_MIN_LAT = 28; - parameter CLK_COR_SEQ_1_1 = 11'b00000000000; - parameter CLK_COR_SEQ_1_2 = 11'b00000000000; - parameter CLK_COR_SEQ_1_3 = 11'b00000000000; - parameter CLK_COR_SEQ_1_4 = 11'b00000000000; - parameter CLK_COR_SEQ_1_MASK = 4'b0000; - parameter CLK_COR_SEQ_2_1 = 11'b00000000000; - parameter CLK_COR_SEQ_2_2 = 11'b00000000000; - parameter CLK_COR_SEQ_2_3 = 11'b00000000000; - parameter CLK_COR_SEQ_2_4 = 11'b00000000000; - parameter CLK_COR_SEQ_2_MASK = 4'b0000; - parameter CLK_COR_SEQ_2_USE = "FALSE"; - parameter CLK_COR_SEQ_DROP = "FALSE"; - parameter CLK_COR_SEQ_LEN = 1; - parameter COMMA32 = "FALSE"; - parameter COMMA_10B_MASK = 10'h3FF; - parameter CYCLE_LIMIT_SEL = 2'b00; - parameter DCDR_FILTER = 3'b010; - parameter DEC_MCOMMA_DETECT = "TRUE"; - parameter DEC_PCOMMA_DETECT = "TRUE"; - parameter DEC_VALID_COMMA_ONLY = "TRUE"; - parameter DIGRX_FWDCLK = 2'b00; - parameter DIGRX_SYNC_MODE = "FALSE"; - parameter ENABLE_DCDR = "FALSE"; - parameter FDET_HYS_CAL = 3'b110; - parameter FDET_HYS_SEL = 3'b110; - parameter FDET_LCK_CAL = 3'b101; - parameter FDET_LCK_SEL = 3'b101; - parameter GT11_MODE = "SINGLE"; - parameter IREFBIASMODE = 2'b11; - parameter LOOPCAL_WAIT = 2'b00; - parameter MCOMMA_32B_VALUE = 32'h000000F6; - parameter MCOMMA_DETECT = "TRUE"; - parameter OPPOSITE_SELECT = "FALSE"; - parameter PCOMMA_32B_VALUE = 32'hF6F62828; - parameter PCOMMA_DETECT = "TRUE"; - parameter PCS_BIT_SLIP = "FALSE"; - parameter PMACLKENABLE = "TRUE"; - parameter PMACOREPWRENABLE = "TRUE"; - parameter PMAIREFTRIM = 4'b0111; - parameter PMAVBGCTRL = 5'b00000; - parameter PMAVREFTRIM = 4'b0111; - parameter PMA_BIT_SLIP = "FALSE"; - parameter REPEATER = "FALSE"; - parameter RXACTST = "FALSE"; - parameter RXAFEEQ = 9'b000000000; - parameter RXAFEPD = "FALSE"; - parameter RXAFETST = "FALSE"; - parameter RXAPD = "FALSE"; - parameter RXASYNCDIVIDE = 2'b11; - parameter RXBY_32 = "TRUE"; - parameter RXCDRLOS = 6'b000000; - parameter RXCLK0_FORCE_PMACLK = "FALSE"; - parameter RXCLKMODE = 6'b110001; - parameter RXCMADJ = 2'b10; - parameter RXCPSEL = "TRUE"; - parameter RXCPTST = "FALSE"; - parameter RXCRCCLOCKDOUBLE = "FALSE"; - parameter RXCRCENABLE = "FALSE"; - parameter RXCRCINITVAL = 32'h00000000; - parameter RXCRCINVERTGEN = "FALSE"; - parameter RXCRCSAMECLOCK = "FALSE"; - parameter RXCTRL1 = 10'h200; - parameter RXCYCLE_LIMIT_SEL = 2'b00; - parameter RXDATA_SEL = 2'b00; - parameter RXDCCOUPLE = "FALSE"; - parameter RXDIGRESET = "FALSE"; - parameter RXDIGRX = "FALSE"; - parameter RXEQ = 64'h4000000000000000; - parameter RXFDCAL_CLOCK_DIVIDE = "NONE"; - parameter RXFDET_HYS_CAL = 3'b110; - parameter RXFDET_HYS_SEL = 3'b110; - parameter RXFDET_LCK_CAL = 3'b101; - parameter RXFDET_LCK_SEL = 3'b101; - parameter RXFECONTROL1 = 2'b00; - parameter RXFECONTROL2 = 3'b000; - parameter RXFETUNE = 2'b01; - parameter RXLB = "FALSE"; - parameter RXLKADJ = 5'b00000; - parameter RXLKAPD = "FALSE"; - parameter RXLOOPCAL_WAIT = 2'b00; - parameter RXLOOPFILT = 4'b0111; - parameter RXOUTDIV2SEL = 1; - parameter RXPD = "FALSE"; - parameter RXPDDTST = "FALSE"; - parameter RXPLLNDIVSEL = 8; - parameter RXPMACLKSEL = "REFCLK1"; - parameter RXRCPADJ = 3'b011; - parameter RXRCPPD = "FALSE"; - parameter RXRECCLK1_USE_SYNC = "FALSE"; - parameter RXRIBADJ = 2'b11; - parameter RXRPDPD = "FALSE"; - parameter RXRSDPD = "FALSE"; - parameter RXSLOWDOWN_CAL = 2'b00; - parameter RXUSRDIVISOR = 1; - parameter RXVCODAC_INIT = 10'b1010000000; - parameter RXVCO_CTRL_ENABLE = "TRUE"; - parameter RX_BUFFER_USE = "TRUE"; - parameter RX_CLOCK_DIVIDER = 2'b00; - parameter RX_LOS_INVALID_INCR = 1; - parameter RX_LOS_THRESHOLD = 4; - parameter SAMPLE_8X = "FALSE"; - parameter SH_CNT_MAX = 64; - parameter SH_INVALID_CNT_MAX = 16; - parameter SLOWDOWN_CAL = 2'b00; - parameter TXABPMACLKSEL = "REFCLK1"; - parameter TXAPD = "FALSE"; - parameter TXAREFBIASSEL = "FALSE"; - parameter TXASYNCDIVIDE = 2'b11; - parameter TXCLK0_FORCE_PMACLK = "FALSE"; - parameter TXCLKMODE = 4'b1001; - parameter TXCPSEL = "TRUE"; - parameter TXCRCCLOCKDOUBLE = "FALSE"; - parameter TXCRCENABLE = "FALSE"; - parameter TXCRCINITVAL = 32'h00000000; - parameter TXCRCINVERTGEN = "FALSE"; - parameter TXCRCSAMECLOCK = "FALSE"; - parameter TXCTRL1 = 10'h200; - parameter TXDATA_SEL = 2'b00; - parameter TXDAT_PRDRV_DAC = 3'b111; - parameter TXDAT_TAP_DAC = 5'b10110; - parameter TXDIGPD = "FALSE"; - parameter TXFDCAL_CLOCK_DIVIDE = "NONE"; - parameter TXHIGHSIGNALEN = "TRUE"; - parameter TXLOOPFILT = 4'b0111; - parameter TXLVLSHFTPD = "FALSE"; - parameter TXOUTCLK1_USE_SYNC = "FALSE"; - parameter TXOUTDIV2SEL = 1; - parameter TXPD = "FALSE"; - parameter TXPHASESEL = "FALSE"; - parameter TXPLLNDIVSEL = 8; - parameter TXPOST_PRDRV_DAC = 3'b111; - parameter TXPOST_TAP_DAC = 5'b01110; - parameter TXPOST_TAP_PD = "TRUE"; - parameter TXPRE_PRDRV_DAC = 3'b111; - parameter TXPRE_TAP_DAC = 5'b00000; - parameter TXPRE_TAP_PD = "TRUE"; - parameter TXSLEWRATE = "FALSE"; - parameter TXTERMTRIM = 4'b1100; - parameter TX_BUFFER_USE = "TRUE"; - parameter TX_CLOCK_DIVIDER = 2'b00; - parameter VCODAC_INIT = 10'b1010000000; - parameter VCO_CTRL_ENABLE = "TRUE"; - parameter VREFBIASMODE = 2'b11; - output DRDY; - output RXBUFERR; - output RXCALFAIL; - output RXCOMMADET; - output RXCYCLELIMIT; - output RXLOCK; - output RXMCLK; - output RXPCSHCLKOUT; - output RXREALIGN; - output RXRECCLK1; - output RXRECCLK2; - output RXSIGDET; - output TX1N; - output TX1P; - output TXBUFERR; - output TXCALFAIL; - output TXCYCLELIMIT; - output TXLOCK; - output TXOUTCLK1; - output TXOUTCLK2; - output TXPCSHCLKOUT; - output [15:0] DO; - output [1:0] RXLOSSOFSYNC; - output [31:0] RXCRCOUT; - output [31:0] TXCRCOUT; - output [4:0] CHBONDO; - output [5:0] RXSTATUS; - output [63:0] RXDATA; - output [7:0] RXCHARISCOMMA; - output [7:0] RXCHARISK; - output [7:0] RXDISPERR; - output [7:0] RXNOTINTABLE; - output [7:0] RXRUNDISP; - output [7:0] TXKERR; - output [7:0] TXRUNDISP; - input DCLK; - input DEN; - input DWE; - input ENCHANSYNC; - input ENMCOMMAALIGN; - input ENPCOMMAALIGN; - input GREFCLK; - input POWERDOWN; - input REFCLK1; - input REFCLK2; - input RX1N; - input RX1P; - input RXBLOCKSYNC64B66BUSE; - input RXCLKSTABLE; - input RXCOMMADETUSE; - input RXCRCCLK; - input RXCRCDATAVALID; - input RXCRCINIT; - input RXCRCINTCLK; - input RXCRCPD; - input RXCRCRESET; - input RXDEC64B66BUSE; - input RXDEC8B10BUSE; - input RXDESCRAM64B66BUSE; - input RXIGNOREBTF; - input RXPMARESET; - input RXPOLARITY; - input RXRESET; - input RXSLIDE; - input RXSYNC; - input RXUSRCLK2; - input RXUSRCLK; - input TXCLKSTABLE; - input TXCRCCLK; - input TXCRCDATAVALID; - input TXCRCINIT; - input TXCRCINTCLK; - input TXCRCPD; - input TXCRCRESET; - input TXENC64B66BUSE; - input TXENC8B10BUSE; - input TXENOOB; - input TXGEARBOX64B66BUSE; - input TXINHIBIT; - input TXPMARESET; - input TXPOLARITY; - input TXRESET; - input TXSCRAM64B66BUSE; - input TXSYNC; - input TXUSRCLK2; - input TXUSRCLK; - input [15:0] DI; - input [1:0] LOOPBACK; - input [1:0] RXDATAWIDTH; - input [1:0] RXINTDATAWIDTH; - input [1:0] TXDATAWIDTH; - input [1:0] TXINTDATAWIDTH; - input [2:0] RXCRCDATAWIDTH; - input [2:0] TXCRCDATAWIDTH; - input [4:0] CHBONDI; - input [63:0] RXCRCIN; - input [63:0] TXCRCIN; - input [63:0] TXDATA; - input [7:0] DADDR; - input [7:0] TXBYPASS8B10B; - input [7:0] TXCHARDISPMODE; - input [7:0] TXCHARDISPVAL; - input [7:0] TXCHARISK; -endmodule - -module GT11_DUAL (...); - parameter ALIGN_COMMA_WORD_A = 1; - parameter ALIGN_COMMA_WORD_B = 1; - parameter BANDGAPSEL_A = "FALSE"; - parameter BANDGAPSEL_B = "FALSE"; - parameter BIASRESSEL_A = "TRUE"; - parameter BIASRESSEL_B = "TRUE"; - parameter CCCB_ARBITRATOR_DISABLE_A = "FALSE"; - parameter CCCB_ARBITRATOR_DISABLE_B = "FALSE"; - parameter CHAN_BOND_LIMIT_A = 16; - parameter CHAN_BOND_LIMIT_B = 16; - parameter CHAN_BOND_MODE_A = "NONE"; - parameter CHAN_BOND_MODE_B = "NONE"; - parameter CHAN_BOND_ONE_SHOT_A = "FALSE"; - parameter CHAN_BOND_ONE_SHOT_B = "FALSE"; - parameter CHAN_BOND_SEQ_1_1_A = 11'b00000000000; - parameter CHAN_BOND_SEQ_1_1_B = 11'b00000000000; - parameter CHAN_BOND_SEQ_1_2_A = 11'b00000000000; - parameter CHAN_BOND_SEQ_1_2_B = 11'b00000000000; - parameter CHAN_BOND_SEQ_1_3_A = 11'b00000000000; - parameter CHAN_BOND_SEQ_1_3_B = 11'b00000000000; - parameter CHAN_BOND_SEQ_1_4_A = 11'b00000000000; - parameter CHAN_BOND_SEQ_1_4_B = 11'b00000000000; - parameter CHAN_BOND_SEQ_1_MASK_A = 4'b0000; - parameter CHAN_BOND_SEQ_1_MASK_B = 4'b0000; - parameter CHAN_BOND_SEQ_2_1_A = 11'b00000000000; - parameter CHAN_BOND_SEQ_2_1_B = 11'b00000000000; - parameter CHAN_BOND_SEQ_2_2_A = 11'b00000000000; - parameter CHAN_BOND_SEQ_2_2_B = 11'b00000000000; - parameter CHAN_BOND_SEQ_2_3_A = 11'b00000000000; - parameter CHAN_BOND_SEQ_2_3_B = 11'b00000000000; - parameter CHAN_BOND_SEQ_2_4_A = 11'b00000000000; - parameter CHAN_BOND_SEQ_2_4_B = 11'b00000000000; - parameter CHAN_BOND_SEQ_2_MASK_A = 4'b0000; - parameter CHAN_BOND_SEQ_2_MASK_B = 4'b0000; - parameter CHAN_BOND_SEQ_2_USE_A = "FALSE"; - parameter CHAN_BOND_SEQ_2_USE_B = "FALSE"; - parameter CHAN_BOND_SEQ_LEN_A = 1; - parameter CHAN_BOND_SEQ_LEN_B = 1; - parameter CLK_CORRECT_USE_A = "TRUE"; - parameter CLK_CORRECT_USE_B = "TRUE"; - parameter CLK_COR_8B10B_DE_A = "FALSE"; - parameter CLK_COR_8B10B_DE_B = "FALSE"; - parameter CLK_COR_MAX_LAT_A = 36; - parameter CLK_COR_MAX_LAT_B = 36; - parameter CLK_COR_MIN_LAT_A = 28; - parameter CLK_COR_MIN_LAT_B = 28; - parameter CLK_COR_SEQ_1_1_A = 11'b00000000000; - parameter CLK_COR_SEQ_1_1_B = 11'b00000000000; - parameter CLK_COR_SEQ_1_2_A = 11'b00000000000; - parameter CLK_COR_SEQ_1_2_B = 11'b00000000000; - parameter CLK_COR_SEQ_1_3_A = 11'b00000000000; - parameter CLK_COR_SEQ_1_3_B = 11'b00000000000; - parameter CLK_COR_SEQ_1_4_A = 11'b00000000000; - parameter CLK_COR_SEQ_1_4_B = 11'b00000000000; - parameter CLK_COR_SEQ_1_MASK_A = 4'b0000; - parameter CLK_COR_SEQ_1_MASK_B = 4'b0000; - parameter CLK_COR_SEQ_2_1_A = 11'b00000000000; - parameter CLK_COR_SEQ_2_1_B = 11'b00000000000; - parameter CLK_COR_SEQ_2_2_A = 11'b00000000000; - parameter CLK_COR_SEQ_2_2_B = 11'b00000000000; - parameter CLK_COR_SEQ_2_3_A = 11'b00000000000; - parameter CLK_COR_SEQ_2_3_B = 11'b00000000000; - parameter CLK_COR_SEQ_2_4_A = 11'b00000000000; - parameter CLK_COR_SEQ_2_4_B = 11'b00000000000; - parameter CLK_COR_SEQ_2_MASK_A = 4'b0000; - parameter CLK_COR_SEQ_2_MASK_B = 4'b0000; - parameter CLK_COR_SEQ_2_USE_A = "FALSE"; - parameter CLK_COR_SEQ_2_USE_B = "FALSE"; - parameter CLK_COR_SEQ_DROP_A = "FALSE"; - parameter CLK_COR_SEQ_DROP_B = "FALSE"; - parameter CLK_COR_SEQ_LEN_A = 1; - parameter CLK_COR_SEQ_LEN_B = 1; - parameter COMMA32_A = "FALSE"; - parameter COMMA32_B = "FALSE"; - parameter COMMA_10B_MASK_A = 10'h3FF; - parameter COMMA_10B_MASK_B = 10'h3FF; - parameter CYCLE_LIMIT_SEL_A = 2'b00; - parameter CYCLE_LIMIT_SEL_B = 2'b00; - parameter DCDR_FILTER_A = 3'b010; - parameter DCDR_FILTER_B = 3'b010; - parameter DEC_MCOMMA_DETECT_A = "TRUE"; - parameter DEC_MCOMMA_DETECT_B = "TRUE"; - parameter DEC_PCOMMA_DETECT_A = "TRUE"; - parameter DEC_PCOMMA_DETECT_B = "TRUE"; - parameter DEC_VALID_COMMA_ONLY_A = "TRUE"; - parameter DEC_VALID_COMMA_ONLY_B = "TRUE"; - parameter DIGRX_FWDCLK_A = 2'b00; - parameter DIGRX_FWDCLK_B = 2'b00; - parameter DIGRX_SYNC_MODE_A = "FALSE"; - parameter DIGRX_SYNC_MODE_B = "FALSE"; - parameter ENABLE_DCDR_A = "FALSE"; - parameter ENABLE_DCDR_B = "FALSE"; - parameter FDET_HYS_CAL_A = 3'b110; - parameter FDET_HYS_CAL_B = 3'b110; - parameter FDET_HYS_SEL_A = 3'b110; - parameter FDET_HYS_SEL_B = 3'b110; - parameter FDET_LCK_CAL_A = 3'b101; - parameter FDET_LCK_CAL_B = 3'b101; - parameter FDET_LCK_SEL_A = 3'b101; - parameter FDET_LCK_SEL_B = 3'b101; - parameter IREFBIASMODE_A = 2'b11; - parameter IREFBIASMODE_B = 2'b11; - parameter LOOPCAL_WAIT_A = 2'b00; - parameter LOOPCAL_WAIT_B = 2'b00; - parameter MCOMMA_32B_VALUE_A = 32'hA1A1A2A2; - parameter MCOMMA_32B_VALUE_B = 32'hA1A1A2A2; - parameter MCOMMA_DETECT_A = "TRUE"; - parameter MCOMMA_DETECT_B = "TRUE"; - parameter OPPOSITE_SELECT_A = "FALSE"; - parameter OPPOSITE_SELECT_B = "FALSE"; - parameter PCOMMA_32B_VALUE_A = 32'hA1A1A2A2; - parameter PCOMMA_32B_VALUE_B = 32'hA1A1A2A2; - parameter PCOMMA_DETECT_A = "TRUE"; - parameter PCOMMA_DETECT_B = "TRUE"; - parameter PCS_BIT_SLIP_A = "FALSE"; - parameter PCS_BIT_SLIP_B = "FALSE"; - parameter PMACLKENABLE_A = "TRUE"; - parameter PMACLKENABLE_B = "TRUE"; - parameter PMACOREPWRENABLE_A = "TRUE"; - parameter PMACOREPWRENABLE_B = "TRUE"; - parameter PMAIREFTRIM_A = 4'b0111; - parameter PMAIREFTRIM_B = 4'b0111; - parameter PMAVBGCTRL_A = 5'b00000; - parameter PMAVBGCTRL_B = 5'b00000; - parameter PMAVREFTRIM_A = 4'b0111; - parameter PMAVREFTRIM_B = 4'b0111; - parameter PMA_BIT_SLIP_A = "FALSE"; - parameter PMA_BIT_SLIP_B = "FALSE"; - parameter POWER_ENABLE_A = "TRUE"; - parameter POWER_ENABLE_B = "TRUE"; - parameter REPEATER_A = "FALSE"; - parameter REPEATER_B = "FALSE"; - parameter RXACTST_A = "FALSE"; - parameter RXACTST_B = "FALSE"; - parameter RXAFEEQ_A = 9'b000000000; - parameter RXAFEEQ_B = 9'b000000000; - parameter RXAFEPD_A = "FALSE"; - parameter RXAFEPD_B = "FALSE"; - parameter RXAFETST_A = "FALSE"; - parameter RXAFETST_B = "FALSE"; - parameter RXAPD_A = "FALSE"; - parameter RXAPD_B = "FALSE"; - parameter RXASYNCDIVIDE_A = 2'b00; - parameter RXASYNCDIVIDE_B = 2'b00; - parameter RXBY_32_A = "TRUE"; - parameter RXBY_32_B = "TRUE"; - parameter RXCDRLOS_A = 6'b000000; - parameter RXCDRLOS_B = 6'b000000; - parameter RXCLK0_FORCE_PMACLK_A = "FALSE"; - parameter RXCLK0_FORCE_PMACLK_B = "FALSE"; - parameter RXCLKMODE_A = 6'b110001; - parameter RXCLKMODE_B = 6'b110001; - parameter RXCMADJ_A = 2'b10; - parameter RXCMADJ_B = 2'b10; - parameter RXCPSEL_A = "TRUE"; - parameter RXCPSEL_B = "TRUE"; - parameter RXCPTST_A = "FALSE"; - parameter RXCPTST_B = "FALSE"; - parameter RXCRCCLOCKDOUBLE_A = "FALSE"; - parameter RXCRCCLOCKDOUBLE_B = "FALSE"; - parameter RXCRCENABLE_A = "FALSE"; - parameter RXCRCENABLE_B = "FALSE"; - parameter RXCRCINITVAL_A = 32'h00000000; - parameter RXCRCINITVAL_B = 32'h00000000; - parameter RXCRCINVERTGEN_A = "FALSE"; - parameter RXCRCINVERTGEN_B = "FALSE"; - parameter RXCRCSAMECLOCK_A = "FALSE"; - parameter RXCRCSAMECLOCK_B = "FALSE"; - parameter RXCTRL1_A = 10'h006; - parameter RXCTRL1_B = 10'h006; - parameter RXCYCLE_LIMIT_SEL_A = 2'b00; - parameter RXCYCLE_LIMIT_SEL_B = 2'b00; - parameter RXDATA_SEL_A = 2'b00; - parameter RXDATA_SEL_B = 2'b00; - parameter RXDCCOUPLE_A = "FALSE"; - parameter RXDCCOUPLE_B = "FALSE"; - parameter RXDIGRESET_A = "FALSE"; - parameter RXDIGRESET_B = "FALSE"; - parameter RXDIGRX_A = "FALSE"; - parameter RXDIGRX_B = "FALSE"; - parameter RXEQ_A = 64'h4000000000000000; - parameter RXEQ_B = 64'h4000000000000000; - parameter RXFDCAL_CLOCK_DIVIDE_A = "NONE"; - parameter RXFDCAL_CLOCK_DIVIDE_B = "NONE"; - parameter RXFDET_HYS_CAL_A = 3'b110; - parameter RXFDET_HYS_CAL_B = 3'b110; - parameter RXFDET_HYS_SEL_A = 3'b110; - parameter RXFDET_HYS_SEL_B = 3'b110; - parameter RXFDET_LCK_CAL_A = 3'b101; - parameter RXFDET_LCK_CAL_B = 3'b101; - parameter RXFDET_LCK_SEL_A = 3'b101; - parameter RXFDET_LCK_SEL_B = 3'b101; - parameter RXFECONTROL1_A = 2'b00; - parameter RXFECONTROL1_B = 2'b00; - parameter RXFECONTROL2_A = 3'b000; - parameter RXFECONTROL2_B = 3'b000; - parameter RXFETUNE_A = 2'b01; - parameter RXFETUNE_B = 2'b01; - parameter RXLB_A = "FALSE"; - parameter RXLB_B = "FALSE"; - parameter RXLKADJ_A = 5'b00000; - parameter RXLKADJ_B = 5'b00000; - parameter RXLKAPD_A = "FALSE"; - parameter RXLKAPD_B = "FALSE"; - parameter RXLOOPCAL_WAIT_A = 2'b00; - parameter RXLOOPCAL_WAIT_B = 2'b00; - parameter RXLOOPFILT_A = 4'b0111; - parameter RXLOOPFILT_B = 4'b0111; - parameter RXOUTDIV2SEL_A = 1; - parameter RXOUTDIV2SEL_B = 1; - parameter RXPDDTST_A = "FALSE"; - parameter RXPDDTST_B = "FALSE"; - parameter RXPD_A = "FALSE"; - parameter RXPD_B = "FALSE"; - parameter RXPLLNDIVSEL_A = 8; - parameter RXPLLNDIVSEL_B = 8; - parameter RXPMACLKSEL_A = "REFCLK1"; - parameter RXPMACLKSEL_B = "REFCLK1"; - parameter RXRCPADJ_A = 3'b011; - parameter RXRCPADJ_B = 3'b011; - parameter RXRCPPD_A = "FALSE"; - parameter RXRCPPD_B = "FALSE"; - parameter RXRECCLK1_USE_SYNC_A = "FALSE"; - parameter RXRECCLK1_USE_SYNC_B = "FALSE"; - parameter RXRIBADJ_A = 2'b11; - parameter RXRIBADJ_B = 2'b11; - parameter RXRPDPD_A = "FALSE"; - parameter RXRPDPD_B = "FALSE"; - parameter RXRSDPD_A = "FALSE"; - parameter RXRSDPD_B = "FALSE"; - parameter RXSLOWDOWN_CAL_A = 2'b00; - parameter RXSLOWDOWN_CAL_B = 2'b00; - parameter RXUSRDIVISOR_A = 1; - parameter RXUSRDIVISOR_B = 1; - parameter RXVCODAC_INIT_A = 10'b1010000000; - parameter RXVCODAC_INIT_B = 10'b1010000000; - parameter RXVCO_CTRL_ENABLE_A = "TRUE"; - parameter RXVCO_CTRL_ENABLE_B = "TRUE"; - parameter RX_BUFFER_USE_A = "TRUE"; - parameter RX_BUFFER_USE_B = "TRUE"; - parameter RX_CLOCK_DIVIDER_A = 2'b00; - parameter RX_CLOCK_DIVIDER_B = 2'b00; - parameter RX_LOS_INVALID_INCR_A = 1; - parameter RX_LOS_INVALID_INCR_B = 1; - parameter RX_LOS_THRESHOLD_A = 4; - parameter RX_LOS_THRESHOLD_B = 4; - parameter SAMPLE_8X_A = "FALSE"; - parameter SAMPLE_8X_B = "FALSE"; - parameter SH_CNT_MAX_A = 64; - parameter SH_CNT_MAX_B = 64; - parameter SH_INVALID_CNT_MAX_A = 16; - parameter SH_INVALID_CNT_MAX_B = 16; - parameter SLOWDOWN_CAL_A = 2'b00; - parameter SLOWDOWN_CAL_B = 2'b00; - parameter TXABPMACLKSEL_A = "REFCLK1"; - parameter TXABPMACLKSEL_B = "REFCLK1"; - parameter TXAPD_A = "FALSE"; - parameter TXAPD_B = "FALSE"; - parameter TXAREFBIASSEL_A = "FALSE"; - parameter TXAREFBIASSEL_B = "FALSE"; - parameter TXASYNCDIVIDE_A = 2'b00; - parameter TXASYNCDIVIDE_B = 2'b00; - parameter TXCLK0_FORCE_PMACLK_A = "FALSE"; - parameter TXCLK0_FORCE_PMACLK_B = "FALSE"; - parameter TXCLKMODE_A = 4'b1001; - parameter TXCLKMODE_B = 4'b1001; - parameter TXCPSEL_A = "TRUE"; - parameter TXCPSEL_B = "TRUE"; - parameter TXCRCCLOCKDOUBLE_A = "FALSE"; - parameter TXCRCCLOCKDOUBLE_B = "FALSE"; - parameter TXCRCENABLE_A = "FALSE"; - parameter TXCRCENABLE_B = "FALSE"; - parameter TXCRCINITVAL_A = 32'h00000000; - parameter TXCRCINITVAL_B = 32'h00000000; - parameter TXCRCINVERTGEN_A = "FALSE"; - parameter TXCRCINVERTGEN_B = "FALSE"; - parameter TXCRCSAMECLOCK_A = "FALSE"; - parameter TXCRCSAMECLOCK_B = "FALSE"; - parameter TXCTRL1_A = 10'h006; - parameter TXCTRL1_B = 10'h006; - parameter TXDATA_SEL_A = 2'b00; - parameter TXDATA_SEL_B = 2'b00; - parameter TXDAT_PRDRV_DAC_A = 3'b111; - parameter TXDAT_PRDRV_DAC_B = 3'b111; - parameter TXDAT_TAP_DAC_A = 5'b10110; - parameter TXDAT_TAP_DAC_B = 5'b10110; - parameter TXDIGPD_A = "FALSE"; - parameter TXDIGPD_B = "FALSE"; - parameter TXFDCAL_CLOCK_DIVIDE_A = "NONE"; - parameter TXFDCAL_CLOCK_DIVIDE_B = "NONE"; - parameter TXHIGHSIGNALEN_A = "TRUE"; - parameter TXHIGHSIGNALEN_B = "TRUE"; - parameter TXLOOPFILT_A = 4'b0111; - parameter TXLOOPFILT_B = 4'b0111; - parameter TXLVLSHFTPD_A = "FALSE"; - parameter TXLVLSHFTPD_B = "FALSE"; - parameter TXOUTCLK1_USE_SYNC_A = "FALSE"; - parameter TXOUTCLK1_USE_SYNC_B = "FALSE"; - parameter TXOUTDIV2SEL_A = 1; - parameter TXOUTDIV2SEL_B = 1; - parameter TXPD_A = "FALSE"; - parameter TXPD_B = "FALSE"; - parameter TXPHASESEL_A = "FALSE"; - parameter TXPHASESEL_B = "FALSE"; - parameter TXPLLNDIVSEL_A = 8; - parameter TXPLLNDIVSEL_B = 8; - parameter TXPOST_PRDRV_DAC_A = 3'b111; - parameter TXPOST_PRDRV_DAC_B = 3'b111; - parameter TXPOST_TAP_DAC_A = 5'b01110; - parameter TXPOST_TAP_DAC_B = 5'b01110; - parameter TXPOST_TAP_PD_A = "TRUE"; - parameter TXPOST_TAP_PD_B = "TRUE"; - parameter TXPRE_PRDRV_DAC_A = 3'b111; - parameter TXPRE_PRDRV_DAC_B = 3'b111; - parameter TXPRE_TAP_DAC_A = 5'b00000; - parameter TXPRE_TAP_DAC_B = 5'b00000; - parameter TXPRE_TAP_PD_A = "TRUE"; - parameter TXPRE_TAP_PD_B = "TRUE"; - parameter TXSLEWRATE_A = "FALSE"; - parameter TXSLEWRATE_B = "FALSE"; - parameter TXTERMTRIM_A = 4'b1100; - parameter TXTERMTRIM_B = 4'b1100; - parameter TX_BUFFER_USE_A = "TRUE"; - parameter TX_BUFFER_USE_B = "TRUE"; - parameter TX_CLOCK_DIVIDER_A = 2'b00; - parameter TX_CLOCK_DIVIDER_B = 2'b00; - parameter VCODAC_INIT_A = 10'b1010000000; - parameter VCODAC_INIT_B = 10'b1010000000; - parameter VCO_CTRL_ENABLE_A = "TRUE"; - parameter VCO_CTRL_ENABLE_B = "TRUE"; - parameter VREFBIASMODE_A = 2'b11; - parameter VREFBIASMODE_B = 2'b11; - output DRDYA; - output DRDYB; - output RXBUFERRA; - output RXBUFERRB; - output RXCALFAILA; - output RXCALFAILB; - output RXCOMMADETA; - output RXCOMMADETB; - output RXCYCLELIMITA; - output RXCYCLELIMITB; - output RXLOCKA; - output RXLOCKB; - output RXMCLKA; - output RXMCLKB; - output RXPCSHCLKOUTA; - output RXPCSHCLKOUTB; - output RXREALIGNA; - output RXREALIGNB; - output RXRECCLK1A; - output RXRECCLK1B; - output RXRECCLK2A; - output RXRECCLK2B; - output RXSIGDETA; - output RXSIGDETB; - output TX1NA; - output TX1NB; - output TX1PA; - output TX1PB; - output TXBUFERRA; - output TXBUFERRB; - output TXCALFAILA; - output TXCALFAILB; - output TXCYCLELIMITA; - output TXCYCLELIMITB; - output TXLOCKA; - output TXLOCKB; - output TXOUTCLK1A; - output TXOUTCLK1B; - output TXOUTCLK2A; - output TXOUTCLK2B; - output TXPCSHCLKOUTA; - output TXPCSHCLKOUTB; - output [15:0] DOA; - output [15:0] DOB; - output [1:0] RXLOSSOFSYNCA; - output [1:0] RXLOSSOFSYNCB; - output [31:0] RXCRCOUTA; - output [31:0] RXCRCOUTB; - output [31:0] TXCRCOUTA; - output [31:0] TXCRCOUTB; - output [4:0] CHBONDOA; - output [4:0] CHBONDOB; - output [5:0] RXSTATUSA; - output [5:0] RXSTATUSB; - output [63:0] RXDATAA; - output [63:0] RXDATAB; - output [7:0] RXCHARISCOMMAA; - output [7:0] RXCHARISCOMMAB; - output [7:0] RXCHARISKA; - output [7:0] RXCHARISKB; - output [7:0] RXDISPERRA; - output [7:0] RXDISPERRB; - output [7:0] RXNOTINTABLEA; - output [7:0] RXNOTINTABLEB; - output [7:0] RXRUNDISPA; - output [7:0] RXRUNDISPB; - output [7:0] TXKERRA; - output [7:0] TXKERRB; - output [7:0] TXRUNDISPA; - output [7:0] TXRUNDISPB; - input DCLKA; - input DCLKB; - input DENA; - input DENB; - input DWEA; - input DWEB; - input ENCHANSYNCA; - input ENCHANSYNCB; - input ENMCOMMAALIGNA; - input ENMCOMMAALIGNB; - input ENPCOMMAALIGNA; - input ENPCOMMAALIGNB; - input GREFCLKA; - input GREFCLKB; - input POWERDOWNA; - input POWERDOWNB; - input REFCLK1A; - input REFCLK1B; - input REFCLK2A; - input REFCLK2B; - input RX1NA; - input RX1NB; - input RX1PA; - input RX1PB; - input RXBLOCKSYNC64B66BUSEA; - input RXBLOCKSYNC64B66BUSEB; - input RXCLKSTABLEA; - input RXCLKSTABLEB; - input RXCOMMADETUSEA; - input RXCOMMADETUSEB; - input RXCRCCLKA; - input RXCRCCLKB; - input RXCRCDATAVALIDA; - input RXCRCDATAVALIDB; - input RXCRCINITA; - input RXCRCINITB; - input RXCRCINTCLKA; - input RXCRCINTCLKB; - input RXCRCPDA; - input RXCRCPDB; - input RXCRCRESETA; - input RXCRCRESETB; - input RXDEC64B66BUSEA; - input RXDEC64B66BUSEB; - input RXDEC8B10BUSEA; - input RXDEC8B10BUSEB; - input RXDESCRAM64B66BUSEA; - input RXDESCRAM64B66BUSEB; - input RXIGNOREBTFA; - input RXIGNOREBTFB; - input RXPMARESETA; - input RXPMARESETB; - input RXPOLARITYA; - input RXPOLARITYB; - input RXRESETA; - input RXRESETB; - input RXSLIDEA; - input RXSLIDEB; - input RXSYNCA; - input RXSYNCB; - input RXUSRCLK2A; - input RXUSRCLK2B; - input RXUSRCLKA; - input RXUSRCLKB; - input TXCLKSTABLEA; - input TXCLKSTABLEB; - input TXCRCCLKA; - input TXCRCCLKB; - input TXCRCDATAVALIDA; - input TXCRCDATAVALIDB; - input TXCRCINITA; - input TXCRCINITB; - input TXCRCINTCLKA; - input TXCRCINTCLKB; - input TXCRCPDA; - input TXCRCPDB; - input TXCRCRESETA; - input TXCRCRESETB; - input TXENC64B66BUSEA; - input TXENC64B66BUSEB; - input TXENC8B10BUSEA; - input TXENC8B10BUSEB; - input TXENOOBA; - input TXENOOBB; - input TXGEARBOX64B66BUSEA; - input TXGEARBOX64B66BUSEB; - input TXINHIBITA; - input TXINHIBITB; - input TXPMARESETA; - input TXPMARESETB; - input TXPOLARITYA; - input TXPOLARITYB; - input TXRESETA; - input TXRESETB; - input TXSCRAM64B66BUSEA; - input TXSCRAM64B66BUSEB; - input TXSYNCA; - input TXSYNCB; - input TXUSRCLK2A; - input TXUSRCLK2B; - input TXUSRCLKA; - input TXUSRCLKB; - input [15:0] DIA; - input [15:0] DIB; - input [1:0] LOOPBACKA; - input [1:0] LOOPBACKB; - input [1:0] RXDATAWIDTHA; - input [1:0] RXDATAWIDTHB; - input [1:0] RXINTDATAWIDTHA; - input [1:0] RXINTDATAWIDTHB; - input [1:0] TXDATAWIDTHA; - input [1:0] TXDATAWIDTHB; - input [1:0] TXINTDATAWIDTHA; - input [1:0] TXINTDATAWIDTHB; - input [2:0] RXCRCDATAWIDTHA; - input [2:0] RXCRCDATAWIDTHB; - input [2:0] TXCRCDATAWIDTHA; - input [2:0] TXCRCDATAWIDTHB; - input [4:0] CHBONDIA; - input [4:0] CHBONDIB; - input [63:0] RXCRCINA; - input [63:0] RXCRCINB; - input [63:0] TXCRCINA; - input [63:0] TXCRCINB; - input [63:0] TXDATAA; - input [63:0] TXDATAB; - input [7:0] DADDRA; - input [7:0] DADDRB; - input [7:0] TXBYPASS8B10BA; - input [7:0] TXBYPASS8B10BB; - input [7:0] TXCHARDISPMODEA; - input [7:0] TXCHARDISPMODEB; - input [7:0] TXCHARDISPVALA; - input [7:0] TXCHARDISPVALB; - input [7:0] TXCHARISKA; - input [7:0] TXCHARISKB; -endmodule - -module GT11CLK (...); - parameter REFCLKSEL = "MGTCLK"; - parameter SYNCLK1OUTEN = "ENABLE"; - parameter SYNCLK2OUTEN = "DISABLE"; - output SYNCLK1OUT; - output SYNCLK2OUT; - input MGTCLKN; - input MGTCLKP; - input REFCLK; - input RXBCLK; - input SYNCLK1IN; - input SYNCLK2IN; -endmodule - -module GT11CLK_MGT (...); - parameter SYNCLK1OUTEN = "ENABLE"; - parameter SYNCLK2OUTEN = "DISABLE"; - output SYNCLK1OUT; - output SYNCLK2OUT; - input MGTCLKN; - input MGTCLKP; -endmodule - -module GTP_DUAL (...); - parameter AC_CAP_DIS_0 = "TRUE"; - parameter AC_CAP_DIS_1 = "TRUE"; - parameter CHAN_BOND_MODE_0 = "OFF"; - parameter CHAN_BOND_MODE_1 = "OFF"; - parameter CHAN_BOND_SEQ_2_USE_0 = "TRUE"; - parameter CHAN_BOND_SEQ_2_USE_1 = "TRUE"; - parameter CLKINDC_B = "TRUE"; - parameter CLK_CORRECT_USE_0 = "TRUE"; - parameter CLK_CORRECT_USE_1 = "TRUE"; - parameter CLK_COR_INSERT_IDLE_FLAG_0 = "FALSE"; - parameter CLK_COR_INSERT_IDLE_FLAG_1 = "FALSE"; - parameter CLK_COR_KEEP_IDLE_0 = "FALSE"; - parameter CLK_COR_KEEP_IDLE_1 = "FALSE"; - parameter CLK_COR_PRECEDENCE_0 = "TRUE"; - parameter CLK_COR_PRECEDENCE_1 = "TRUE"; - parameter CLK_COR_SEQ_2_USE_0 = "FALSE"; - parameter CLK_COR_SEQ_2_USE_1 = "FALSE"; - parameter COMMA_DOUBLE_0 = "FALSE"; - parameter COMMA_DOUBLE_1 = "FALSE"; - parameter DEC_MCOMMA_DETECT_0 = "TRUE"; - parameter DEC_MCOMMA_DETECT_1 = "TRUE"; - parameter DEC_PCOMMA_DETECT_0 = "TRUE"; - parameter DEC_PCOMMA_DETECT_1 = "TRUE"; - parameter DEC_VALID_COMMA_ONLY_0 = "TRUE"; - parameter DEC_VALID_COMMA_ONLY_1 = "TRUE"; - parameter MCOMMA_DETECT_0 = "TRUE"; - parameter MCOMMA_DETECT_1 = "TRUE"; - parameter OVERSAMPLE_MODE = "FALSE"; - parameter PCI_EXPRESS_MODE_0 = "TRUE"; - parameter PCI_EXPRESS_MODE_1 = "TRUE"; - parameter PCOMMA_DETECT_0 = "TRUE"; - parameter PCOMMA_DETECT_1 = "TRUE"; - parameter PLL_SATA_0 = "FALSE"; - parameter PLL_SATA_1 = "FALSE"; - parameter RCV_TERM_GND_0 = "TRUE"; - parameter RCV_TERM_GND_1 = "TRUE"; - parameter RCV_TERM_MID_0 = "FALSE"; - parameter RCV_TERM_MID_1 = "FALSE"; - parameter RCV_TERM_VTTRX_0 = "FALSE"; - parameter RCV_TERM_VTTRX_1 = "FALSE"; - parameter RX_BUFFER_USE_0 = "TRUE"; - parameter RX_BUFFER_USE_1 = "TRUE"; - parameter RX_DECODE_SEQ_MATCH_0 = "TRUE"; - parameter RX_DECODE_SEQ_MATCH_1 = "TRUE"; - parameter RX_LOSS_OF_SYNC_FSM_0 = "FALSE"; - parameter RX_LOSS_OF_SYNC_FSM_1 = "FALSE"; - parameter RX_SLIDE_MODE_0 = "PCS"; - parameter RX_SLIDE_MODE_1 = "PCS"; - parameter RX_STATUS_FMT_0 = "PCIE"; - parameter RX_STATUS_FMT_1 = "PCIE"; - parameter RX_XCLK_SEL_0 = "RXREC"; - parameter RX_XCLK_SEL_1 = "RXREC"; - parameter SIM_PLL_PERDIV2 = 9'h190; - parameter SIM_RECEIVER_DETECT_PASS0 = "FALSE"; - parameter SIM_RECEIVER_DETECT_PASS1 = "FALSE"; - parameter TERMINATION_OVRD = "FALSE"; - parameter TX_BUFFER_USE_0 = "TRUE"; - parameter TX_BUFFER_USE_1 = "TRUE"; - parameter TX_DIFF_BOOST_0 = "TRUE"; - parameter TX_DIFF_BOOST_1 = "TRUE"; - parameter TX_XCLK_SEL_0 = "TXUSR"; - parameter TX_XCLK_SEL_1 = "TXUSR"; - parameter [15:0] TRANS_TIME_FROM_P2_0 = 16'h003c; - parameter [15:0] TRANS_TIME_FROM_P2_1 = 16'h003c; - parameter [15:0] TRANS_TIME_NON_P2_0 = 16'h0019; - parameter [15:0] TRANS_TIME_NON_P2_1 = 16'h0019; - parameter [15:0] TRANS_TIME_TO_P2_0 = 16'h0064; - parameter [15:0] TRANS_TIME_TO_P2_1 = 16'h0064; - parameter [24:0] PMA_RX_CFG_0 = 25'h09f0089; - parameter [24:0] PMA_RX_CFG_1 = 25'h09f0089; - parameter [26:0] PMA_CDR_SCAN_0 = 27'h6c07640; - parameter [26:0] PMA_CDR_SCAN_1 = 27'h6c07640; - parameter [27:0] PCS_COM_CFG = 28'h1680a0e; - parameter [2:0] OOBDETECT_THRESHOLD_0 = 3'b001; - parameter [2:0] OOBDETECT_THRESHOLD_1 = 3'b001; - parameter [2:0] SATA_BURST_VAL_0 = 3'b100; - parameter [2:0] SATA_BURST_VAL_1 = 3'b100; - parameter [2:0] SATA_IDLE_VAL_0 = 3'b011; - parameter [2:0] SATA_IDLE_VAL_1 = 3'b011; - parameter [31:0] PRBS_ERR_THRESHOLD_0 = 32'h1; - parameter [31:0] PRBS_ERR_THRESHOLD_1 = 32'h1; - parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_0 = 4'b1111; - parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_1 = 4'b1111; - parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_0 = 4'b1111; - parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_1 = 4'b1111; - parameter [3:0] CLK_COR_SEQ_1_ENABLE_0 = 4'b1111; - parameter [3:0] CLK_COR_SEQ_1_ENABLE_1 = 4'b1111; - parameter [3:0] CLK_COR_SEQ_2_ENABLE_0 = 4'b1111; - parameter [3:0] CLK_COR_SEQ_2_ENABLE_1 = 4'b1111; - parameter [3:0] COM_BURST_VAL_0 = 4'b1111; - parameter [3:0] COM_BURST_VAL_1 = 4'b1111; - parameter [4:0] TERMINATION_CTRL = 5'b10100; - parameter [4:0] TXRX_INVERT_0 = 5'b00000; - parameter [4:0] TXRX_INVERT_1 = 5'b00000; - parameter [9:0] CHAN_BOND_SEQ_1_1_0 = 10'b0001001010; - parameter [9:0] CHAN_BOND_SEQ_1_1_1 = 10'b0001001010; - parameter [9:0] CHAN_BOND_SEQ_1_2_0 = 10'b0001001010; - parameter [9:0] CHAN_BOND_SEQ_1_2_1 = 10'b0001001010; - parameter [9:0] CHAN_BOND_SEQ_1_3_0 = 10'b0001001010; - parameter [9:0] CHAN_BOND_SEQ_1_3_1 = 10'b0001001010; - parameter [9:0] CHAN_BOND_SEQ_1_4_0 = 10'b0110111100; - parameter [9:0] CHAN_BOND_SEQ_1_4_1 = 10'b0110111100; - parameter [9:0] CHAN_BOND_SEQ_2_1_0 = 10'b0110111100; - parameter [9:0] CHAN_BOND_SEQ_2_1_1 = 10'b0110111100; - parameter [9:0] CHAN_BOND_SEQ_2_2_0 = 10'b0100111100; - parameter [9:0] CHAN_BOND_SEQ_2_2_1 = 10'b0100111100; - parameter [9:0] CHAN_BOND_SEQ_2_3_0 = 10'b0100111100; - parameter [9:0] CHAN_BOND_SEQ_2_3_1 = 10'b0100111100; - parameter [9:0] CHAN_BOND_SEQ_2_4_0 = 10'b0100111100; - parameter [9:0] CHAN_BOND_SEQ_2_4_1 = 10'b0100111100; - parameter [9:0] CLK_COR_SEQ_1_1_0 = 10'b0100011100; - parameter [9:0] CLK_COR_SEQ_1_1_1 = 10'b0100011100; - parameter [9:0] CLK_COR_SEQ_1_2_0 = 10'b0; - parameter [9:0] CLK_COR_SEQ_1_2_1 = 10'b0; - parameter [9:0] CLK_COR_SEQ_1_3_0 = 10'b0; - parameter [9:0] CLK_COR_SEQ_1_3_1 = 10'b0; - parameter [9:0] CLK_COR_SEQ_1_4_0 = 10'b0; - parameter [9:0] CLK_COR_SEQ_1_4_1 = 10'b0; - parameter [9:0] CLK_COR_SEQ_2_1_0 = 10'b0; - parameter [9:0] CLK_COR_SEQ_2_1_1 = 10'b0; - parameter [9:0] CLK_COR_SEQ_2_2_0 = 10'b0; - parameter [9:0] CLK_COR_SEQ_2_2_1 = 10'b0; - parameter [9:0] CLK_COR_SEQ_2_3_0 = 10'b0; - parameter [9:0] CLK_COR_SEQ_2_3_1 = 10'b0; - parameter [9:0] CLK_COR_SEQ_2_4_0 = 10'b0; - parameter [9:0] CLK_COR_SEQ_2_4_1 = 10'b0; - parameter [9:0] COMMA_10B_ENABLE_0 = 10'b1111111111; - parameter [9:0] COMMA_10B_ENABLE_1 = 10'b1111111111; - parameter [9:0] MCOMMA_10B_VALUE_0 = 10'b1010000011; - parameter [9:0] MCOMMA_10B_VALUE_1 = 10'b1010000011; - parameter [9:0] PCOMMA_10B_VALUE_0 = 10'b0101111100; - parameter [9:0] PCOMMA_10B_VALUE_1 = 10'b0101111100; - parameter ALIGN_COMMA_WORD_0 = 1; - parameter ALIGN_COMMA_WORD_1 = 1; - parameter CHAN_BOND_1_MAX_SKEW_0 = 7; - parameter CHAN_BOND_1_MAX_SKEW_1 = 7; - parameter CHAN_BOND_2_MAX_SKEW_0 = 1; - parameter CHAN_BOND_2_MAX_SKEW_1 = 1; - parameter CHAN_BOND_LEVEL_0 = 0; - parameter CHAN_BOND_LEVEL_1 = 0; - parameter CHAN_BOND_SEQ_LEN_0 = 4; - parameter CHAN_BOND_SEQ_LEN_1 = 4; - parameter CLK25_DIVIDER = 4; - parameter CLK_COR_ADJ_LEN_0 = 1; - parameter CLK_COR_ADJ_LEN_1 = 1; - parameter CLK_COR_DET_LEN_0 = 1; - parameter CLK_COR_DET_LEN_1 = 1; - parameter CLK_COR_MAX_LAT_0 = 18; - parameter CLK_COR_MAX_LAT_1 = 18; - parameter CLK_COR_MIN_LAT_0 = 16; - parameter CLK_COR_MIN_LAT_1 = 16; - parameter CLK_COR_REPEAT_WAIT_0 = 5; - parameter CLK_COR_REPEAT_WAIT_1 = 5; - parameter OOB_CLK_DIVIDER = 4; - parameter PLL_DIVSEL_FB = 5; - parameter PLL_DIVSEL_REF = 2; - parameter PLL_RXDIVSEL_OUT_0 = 1; - parameter PLL_RXDIVSEL_OUT_1 = 1; - parameter PLL_TXDIVSEL_COMM_OUT = 1; - parameter PLL_TXDIVSEL_OUT_0 = 1; - parameter PLL_TXDIVSEL_OUT_1 = 1; - parameter RX_LOS_INVALID_INCR_0 = 8; - parameter RX_LOS_INVALID_INCR_1 = 8; - parameter RX_LOS_THRESHOLD_0 = 128; - parameter RX_LOS_THRESHOLD_1 = 128; - parameter SATA_MAX_BURST_0 = 7; - parameter SATA_MAX_BURST_1 = 7; - parameter SATA_MAX_INIT_0 = 22; - parameter SATA_MAX_INIT_1 = 22; - parameter SATA_MAX_WAKE_0 = 7; - parameter SATA_MAX_WAKE_1 = 7; - parameter SATA_MIN_BURST_0 = 4; - parameter SATA_MIN_BURST_1 = 4; - parameter SATA_MIN_INIT_0 = 12; - parameter SATA_MIN_INIT_1 = 12; - parameter SATA_MIN_WAKE_0 = 4; - parameter SATA_MIN_WAKE_1 = 4; - parameter SIM_GTPRESET_SPEEDUP = 0; - parameter TERMINATION_IMP_0 = 50; - parameter TERMINATION_IMP_1 = 50; - parameter TX_SYNC_FILTERB = 1; - output DRDY; - output PHYSTATUS0; - output PHYSTATUS1; - output PLLLKDET; - output REFCLKOUT; - output RESETDONE0; - output RESETDONE1; - output RXBYTEISALIGNED0; - output RXBYTEISALIGNED1; - output RXBYTEREALIGN0; - output RXBYTEREALIGN1; - output RXCHANBONDSEQ0; - output RXCHANBONDSEQ1; - output RXCHANISALIGNED0; - output RXCHANISALIGNED1; - output RXCHANREALIGN0; - output RXCHANREALIGN1; - output RXCOMMADET0; - output RXCOMMADET1; - output RXELECIDLE0; - output RXELECIDLE1; - output RXOVERSAMPLEERR0; - output RXOVERSAMPLEERR1; - output RXPRBSERR0; - output RXPRBSERR1; - output RXRECCLK0; - output RXRECCLK1; - output RXVALID0; - output RXVALID1; - output TXN0; - output TXN1; - output TXOUTCLK0; - output TXOUTCLK1; - output TXP0; - output TXP1; - output [15:0] DO; - output [15:0] RXDATA0; - output [15:0] RXDATA1; - output [1:0] RXCHARISCOMMA0; - output [1:0] RXCHARISCOMMA1; - output [1:0] RXCHARISK0; - output [1:0] RXCHARISK1; - output [1:0] RXDISPERR0; - output [1:0] RXDISPERR1; - output [1:0] RXLOSSOFSYNC0; - output [1:0] RXLOSSOFSYNC1; - output [1:0] RXNOTINTABLE0; - output [1:0] RXNOTINTABLE1; - output [1:0] RXRUNDISP0; - output [1:0] RXRUNDISP1; - output [1:0] TXBUFSTATUS0; - output [1:0] TXBUFSTATUS1; - output [1:0] TXKERR0; - output [1:0] TXKERR1; - output [1:0] TXRUNDISP0; - output [1:0] TXRUNDISP1; - output [2:0] RXBUFSTATUS0; - output [2:0] RXBUFSTATUS1; - output [2:0] RXCHBONDO0; - output [2:0] RXCHBONDO1; - output [2:0] RXCLKCORCNT0; - output [2:0] RXCLKCORCNT1; - output [2:0] RXSTATUS0; - output [2:0] RXSTATUS1; - input CLKIN; - input DCLK; - input DEN; - input DWE; - input GTPRESET; - input INTDATAWIDTH; - input PLLLKDETEN; - input PLLPOWERDOWN; - input PRBSCNTRESET0; - input PRBSCNTRESET1; - input REFCLKPWRDNB; - input RXBUFRESET0; - input RXBUFRESET1; - input RXCDRRESET0; - input RXCDRRESET1; - input RXCOMMADETUSE0; - input RXCOMMADETUSE1; - input RXDATAWIDTH0; - input RXDATAWIDTH1; - input RXDEC8B10BUSE0; - input RXDEC8B10BUSE1; - input RXELECIDLERESET0; - input RXELECIDLERESET1; - input RXENCHANSYNC0; - input RXENCHANSYNC1; - input RXENELECIDLERESETB; - input RXENEQB0; - input RXENEQB1; - input RXENMCOMMAALIGN0; - input RXENMCOMMAALIGN1; - input RXENPCOMMAALIGN0; - input RXENPCOMMAALIGN1; - input RXENSAMPLEALIGN0; - input RXENSAMPLEALIGN1; - input RXN0; - input RXN1; - input RXP0; - input RXP1; - input RXPMASETPHASE0; - input RXPMASETPHASE1; - input RXPOLARITY0; - input RXPOLARITY1; - input RXRESET0; - input RXRESET1; - input RXSLIDE0; - input RXSLIDE1; - input RXUSRCLK0; - input RXUSRCLK1; - input RXUSRCLK20; - input RXUSRCLK21; - input TXCOMSTART0; - input TXCOMSTART1; - input TXCOMTYPE0; - input TXCOMTYPE1; - input TXDATAWIDTH0; - input TXDATAWIDTH1; - input TXDETECTRX0; - input TXDETECTRX1; - input TXELECIDLE0; - input TXELECIDLE1; - input TXENC8B10BUSE0; - input TXENC8B10BUSE1; - input TXENPMAPHASEALIGN; - input TXINHIBIT0; - input TXINHIBIT1; - input TXPMASETPHASE; - input TXPOLARITY0; - input TXPOLARITY1; - input TXRESET0; - input TXRESET1; - input TXUSRCLK0; - input TXUSRCLK1; - input TXUSRCLK20; - input TXUSRCLK21; - input [15:0] DI; - input [15:0] TXDATA0; - input [15:0] TXDATA1; - input [1:0] RXENPRBSTST0; - input [1:0] RXENPRBSTST1; - input [1:0] RXEQMIX0; - input [1:0] RXEQMIX1; - input [1:0] RXPOWERDOWN0; - input [1:0] RXPOWERDOWN1; - input [1:0] TXBYPASS8B10B0; - input [1:0] TXBYPASS8B10B1; - input [1:0] TXCHARDISPMODE0; - input [1:0] TXCHARDISPMODE1; - input [1:0] TXCHARDISPVAL0; - input [1:0] TXCHARDISPVAL1; - input [1:0] TXCHARISK0; - input [1:0] TXCHARISK1; - input [1:0] TXENPRBSTST0; - input [1:0] TXENPRBSTST1; - input [1:0] TXPOWERDOWN0; - input [1:0] TXPOWERDOWN1; - input [2:0] LOOPBACK0; - input [2:0] LOOPBACK1; - input [2:0] RXCHBONDI0; - input [2:0] RXCHBONDI1; - input [2:0] TXBUFDIFFCTRL0; - input [2:0] TXBUFDIFFCTRL1; - input [2:0] TXDIFFCTRL0; - input [2:0] TXDIFFCTRL1; - input [2:0] TXPREEMPHASIS0; - input [2:0] TXPREEMPHASIS1; - input [3:0] GTPTEST; - input [3:0] RXEQPOLE0; - input [3:0] RXEQPOLE1; - input [6:0] DADDR; -endmodule - -module GTX_DUAL (...); - parameter STEPPING = "0"; - parameter AC_CAP_DIS_0 = "TRUE"; - parameter AC_CAP_DIS_1 = "TRUE"; - parameter CHAN_BOND_KEEP_ALIGN_0 = "FALSE"; - parameter CHAN_BOND_KEEP_ALIGN_1 = "FALSE"; - parameter CHAN_BOND_MODE_0 = "OFF"; - parameter CHAN_BOND_MODE_1 = "OFF"; - parameter CHAN_BOND_SEQ_2_USE_0 = "TRUE"; - parameter CHAN_BOND_SEQ_2_USE_1 = "TRUE"; - parameter CLKINDC_B = "TRUE"; - parameter CLKRCV_TRST = "FALSE"; - parameter CLK_CORRECT_USE_0 = "TRUE"; - parameter CLK_CORRECT_USE_1 = "TRUE"; - parameter CLK_COR_INSERT_IDLE_FLAG_0 = "FALSE"; - parameter CLK_COR_INSERT_IDLE_FLAG_1 = "FALSE"; - parameter CLK_COR_KEEP_IDLE_0 = "FALSE"; - parameter CLK_COR_KEEP_IDLE_1 = "FALSE"; - parameter CLK_COR_PRECEDENCE_0 = "TRUE"; - parameter CLK_COR_PRECEDENCE_1 = "TRUE"; - parameter CLK_COR_SEQ_2_USE_0 = "FALSE"; - parameter CLK_COR_SEQ_2_USE_1 = "FALSE"; - parameter COMMA_DOUBLE_0 = "FALSE"; - parameter COMMA_DOUBLE_1 = "FALSE"; - parameter DEC_MCOMMA_DETECT_0 = "TRUE"; - parameter DEC_MCOMMA_DETECT_1 = "TRUE"; - parameter DEC_PCOMMA_DETECT_0 = "TRUE"; - parameter DEC_PCOMMA_DETECT_1 = "TRUE"; - parameter DEC_VALID_COMMA_ONLY_0 = "TRUE"; - parameter DEC_VALID_COMMA_ONLY_1 = "TRUE"; - parameter MCOMMA_DETECT_0 = "TRUE"; - parameter MCOMMA_DETECT_1 = "TRUE"; - parameter OVERSAMPLE_MODE = "FALSE"; - parameter PCI_EXPRESS_MODE_0 = "TRUE"; - parameter PCI_EXPRESS_MODE_1 = "TRUE"; - parameter PCOMMA_DETECT_0 = "TRUE"; - parameter PCOMMA_DETECT_1 = "TRUE"; - parameter PLL_FB_DCCEN = "FALSE"; - parameter PLL_SATA_0 = "FALSE"; - parameter PLL_SATA_1 = "FALSE"; - parameter RCV_TERM_GND_0 = "TRUE"; - parameter RCV_TERM_GND_1 = "TRUE"; - parameter RCV_TERM_VTTRX_0 = "FALSE"; - parameter RCV_TERM_VTTRX_1 = "FALSE"; - parameter RXGEARBOX_USE_0 = "FALSE"; - parameter RXGEARBOX_USE_1 = "FALSE"; - parameter RX_BUFFER_USE_0 = "TRUE"; - parameter RX_BUFFER_USE_1 = "TRUE"; - parameter RX_DECODE_SEQ_MATCH_0 = "TRUE"; - parameter RX_DECODE_SEQ_MATCH_1 = "TRUE"; - parameter RX_EN_IDLE_HOLD_CDR = "FALSE"; - parameter RX_EN_IDLE_HOLD_DFE_0 = "TRUE"; - parameter RX_EN_IDLE_HOLD_DFE_1 = "TRUE"; - parameter RX_EN_IDLE_RESET_BUF_0 = "TRUE"; - parameter RX_EN_IDLE_RESET_BUF_1 = "TRUE"; - parameter RX_EN_IDLE_RESET_FR = "TRUE"; - parameter RX_EN_IDLE_RESET_PH = "TRUE"; - parameter RX_LOSS_OF_SYNC_FSM_0 = "FALSE"; - parameter RX_LOSS_OF_SYNC_FSM_1 = "FALSE"; - parameter RX_SLIDE_MODE_0 = "PCS"; - parameter RX_SLIDE_MODE_1 = "PCS"; - parameter RX_STATUS_FMT_0 = "PCIE"; - parameter RX_STATUS_FMT_1 = "PCIE"; - parameter RX_XCLK_SEL_0 = "RXREC"; - parameter RX_XCLK_SEL_1 = "RXREC"; - parameter SIM_PLL_PERDIV2 = 9'h190; - parameter SIM_RECEIVER_DETECT_PASS_0 = "FALSE"; - parameter SIM_RECEIVER_DETECT_PASS_1 = "FALSE"; - parameter TERMINATION_OVRD = "FALSE"; - parameter TXGEARBOX_USE_0 = "FALSE"; - parameter TXGEARBOX_USE_1 = "FALSE"; - parameter TX_BUFFER_USE_0 = "TRUE"; - parameter TX_BUFFER_USE_1 = "TRUE"; - parameter TX_XCLK_SEL_0 = "TXUSR"; - parameter TX_XCLK_SEL_1 = "TXUSR"; - parameter [11:0] TRANS_TIME_FROM_P2_0 = 12'h03c; - parameter [11:0] TRANS_TIME_FROM_P2_1 = 12'h03c; - parameter [13:0] TX_DETECT_RX_CFG_0 = 14'h1832; - parameter [13:0] TX_DETECT_RX_CFG_1 = 14'h1832; - parameter [19:0] PMA_TX_CFG_0 = 20'h00082; - parameter [19:0] PMA_TX_CFG_1 = 20'h00082; - parameter [1:0] CM_TRIM_0 = 2'b10; - parameter [1:0] CM_TRIM_1 = 2'b10; - parameter [23:0] PLL_COM_CFG = 24'h21680a; - parameter [24:0] PMA_RX_CFG_0 = 25'h05ce109; - parameter [24:0] PMA_RX_CFG_1 = 25'h05ce109; - parameter [26:0] PMA_CDR_SCAN_0 = 27'h6c08040; - parameter [26:0] PMA_CDR_SCAN_1 = 27'h6c08040; - parameter [2:0] GEARBOX_ENDEC_0 = 3'b000; - parameter [2:0] GEARBOX_ENDEC_1 = 3'b000; - parameter [2:0] OOBDETECT_THRESHOLD_0 = 3'b111; - parameter [2:0] OOBDETECT_THRESHOLD_1 = 3'b111; - parameter [2:0] PLL_LKDET_CFG = 3'b111; - parameter [2:0] PLL_TDCC_CFG = 3'b000; - parameter [2:0] SATA_BURST_VAL_0 = 3'b100; - parameter [2:0] SATA_BURST_VAL_1 = 3'b100; - parameter [2:0] SATA_IDLE_VAL_0 = 3'b011; - parameter [2:0] SATA_IDLE_VAL_1 = 3'b011; - parameter [2:0] TXRX_INVERT_0 = 3'b000; - parameter [2:0] TXRX_INVERT_1 = 3'b000; - parameter [2:0] TX_IDLE_DELAY_0 = 3'b010; - parameter [2:0] TX_IDLE_DELAY_1 = 3'b010; - parameter [31:0] PRBS_ERR_THRESHOLD_0 = 32'h1; - parameter [31:0] PRBS_ERR_THRESHOLD_1 = 32'h1; - parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_0 = 4'b1111; - parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_1 = 4'b1111; - parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_0 = 4'b1111; - parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_1 = 4'b1111; - parameter [3:0] CLK_COR_SEQ_1_ENABLE_0 = 4'b1111; - parameter [3:0] CLK_COR_SEQ_1_ENABLE_1 = 4'b1111; - parameter [3:0] CLK_COR_SEQ_2_ENABLE_0 = 4'b1111; - parameter [3:0] CLK_COR_SEQ_2_ENABLE_1 = 4'b1111; - parameter [3:0] COM_BURST_VAL_0 = 4'b1111; - parameter [3:0] COM_BURST_VAL_1 = 4'b1111; - parameter [3:0] RX_IDLE_HI_CNT_0 = 4'b1000; - parameter [3:0] RX_IDLE_HI_CNT_1 = 4'b1000; - parameter [3:0] RX_IDLE_LO_CNT_0 = 4'b0000; - parameter [3:0] RX_IDLE_LO_CNT_1 = 4'b0000; - parameter [4:0] CDR_PH_ADJ_TIME = 5'b01010; - parameter [4:0] DFE_CAL_TIME = 5'b00110; - parameter [4:0] TERMINATION_CTRL = 5'b10100; - parameter [68:0] PMA_COM_CFG = 69'h0; - parameter [6:0] PMA_RXSYNC_CFG_0 = 7'h0; - parameter [6:0] PMA_RXSYNC_CFG_1 = 7'h0; - parameter [7:0] PLL_CP_CFG = 8'h00; - parameter [7:0] TRANS_TIME_NON_P2_0 = 8'h19; - parameter [7:0] TRANS_TIME_NON_P2_1 = 8'h19; - parameter [9:0] CHAN_BOND_SEQ_1_1_0 = 10'b0001001010; - parameter [9:0] CHAN_BOND_SEQ_1_1_1 = 10'b0001001010; - parameter [9:0] CHAN_BOND_SEQ_1_2_0 = 10'b0001001010; - parameter [9:0] CHAN_BOND_SEQ_1_2_1 = 10'b0001001010; - parameter [9:0] CHAN_BOND_SEQ_1_3_0 = 10'b0001001010; - parameter [9:0] CHAN_BOND_SEQ_1_3_1 = 10'b0001001010; - parameter [9:0] CHAN_BOND_SEQ_1_4_0 = 10'b0110111100; - parameter [9:0] CHAN_BOND_SEQ_1_4_1 = 10'b0110111100; - parameter [9:0] CHAN_BOND_SEQ_2_1_0 = 10'b0110111100; - parameter [9:0] CHAN_BOND_SEQ_2_1_1 = 10'b0110111100; - parameter [9:0] CHAN_BOND_SEQ_2_2_0 = 10'b0100111100; - parameter [9:0] CHAN_BOND_SEQ_2_2_1 = 10'b0100111100; - parameter [9:0] CHAN_BOND_SEQ_2_3_0 = 10'b0100111100; - parameter [9:0] CHAN_BOND_SEQ_2_3_1 = 10'b0100111100; - parameter [9:0] CHAN_BOND_SEQ_2_4_0 = 10'b0100111100; - parameter [9:0] CHAN_BOND_SEQ_2_4_1 = 10'b0100111100; - parameter [9:0] CLK_COR_SEQ_1_1_0 = 10'b0100011100; - parameter [9:0] CLK_COR_SEQ_1_1_1 = 10'b0100011100; - parameter [9:0] CLK_COR_SEQ_1_2_0 = 10'b0; - parameter [9:0] CLK_COR_SEQ_1_2_1 = 10'b0; - parameter [9:0] CLK_COR_SEQ_1_3_0 = 10'b0; - parameter [9:0] CLK_COR_SEQ_1_3_1 = 10'b0; - parameter [9:0] CLK_COR_SEQ_1_4_0 = 10'b0; - parameter [9:0] CLK_COR_SEQ_1_4_1 = 10'b0; - parameter [9:0] CLK_COR_SEQ_2_1_0 = 10'b0; - parameter [9:0] CLK_COR_SEQ_2_1_1 = 10'b0; - parameter [9:0] CLK_COR_SEQ_2_2_0 = 10'b0; - parameter [9:0] CLK_COR_SEQ_2_2_1 = 10'b0; - parameter [9:0] CLK_COR_SEQ_2_3_0 = 10'b0; - parameter [9:0] CLK_COR_SEQ_2_3_1 = 10'b0; - parameter [9:0] CLK_COR_SEQ_2_4_0 = 10'b0; - parameter [9:0] CLK_COR_SEQ_2_4_1 = 10'b0; - parameter [9:0] COMMA_10B_ENABLE_0 = 10'b1111111111; - parameter [9:0] COMMA_10B_ENABLE_1 = 10'b1111111111; - parameter [9:0] DFE_CFG_0 = 10'b0001111011; - parameter [9:0] DFE_CFG_1 = 10'b0001111011; - parameter [9:0] MCOMMA_10B_VALUE_0 = 10'b1010000011; - parameter [9:0] MCOMMA_10B_VALUE_1 = 10'b1010000011; - parameter [9:0] PCOMMA_10B_VALUE_0 = 10'b0101111100; - parameter [9:0] PCOMMA_10B_VALUE_1 = 10'b0101111100; - parameter [9:0] TRANS_TIME_TO_P2_0 = 10'h064; - parameter [9:0] TRANS_TIME_TO_P2_1 = 10'h064; - parameter ALIGN_COMMA_WORD_0 = 1; - parameter ALIGN_COMMA_WORD_1 = 1; - parameter CB2_INH_CC_PERIOD_0 = 8; - parameter CB2_INH_CC_PERIOD_1 = 8; - parameter CHAN_BOND_1_MAX_SKEW_0 = 7; - parameter CHAN_BOND_1_MAX_SKEW_1 = 7; - parameter CHAN_BOND_2_MAX_SKEW_0 = 1; - parameter CHAN_BOND_2_MAX_SKEW_1 = 1; - parameter CHAN_BOND_LEVEL_0 = 0; - parameter CHAN_BOND_LEVEL_1 = 0; - parameter CHAN_BOND_SEQ_LEN_0 = 4; - parameter CHAN_BOND_SEQ_LEN_1 = 4; - parameter CLK25_DIVIDER = 4; - parameter CLK_COR_ADJ_LEN_0 = 1; - parameter CLK_COR_ADJ_LEN_1 = 1; - parameter CLK_COR_DET_LEN_0 = 1; - parameter CLK_COR_DET_LEN_1 = 1; - parameter CLK_COR_MAX_LAT_0 = 18; - parameter CLK_COR_MAX_LAT_1 = 18; - parameter CLK_COR_MIN_LAT_0 = 16; - parameter CLK_COR_MIN_LAT_1 = 16; - parameter CLK_COR_REPEAT_WAIT_0 = 5; - parameter CLK_COR_REPEAT_WAIT_1 = 5; - parameter OOB_CLK_DIVIDER = 4; - parameter PLL_DIVSEL_FB = 5; - parameter PLL_DIVSEL_REF = 2; - parameter PLL_RXDIVSEL_OUT_0 = 1; - parameter PLL_RXDIVSEL_OUT_1 = 1; - parameter PLL_TXDIVSEL_OUT_0 = 1; - parameter PLL_TXDIVSEL_OUT_1 = 1; - parameter RX_LOS_INVALID_INCR_0 = 8; - parameter RX_LOS_INVALID_INCR_1 = 8; - parameter RX_LOS_THRESHOLD_0 = 128; - parameter RX_LOS_THRESHOLD_1 = 128; - parameter SATA_MAX_BURST_0 = 7; - parameter SATA_MAX_BURST_1 = 7; - parameter SATA_MAX_INIT_0 = 22; - parameter SATA_MAX_INIT_1 = 22; - parameter SATA_MAX_WAKE_0 = 7; - parameter SATA_MAX_WAKE_1 = 7; - parameter SATA_MIN_BURST_0 = 4; - parameter SATA_MIN_BURST_1 = 4; - parameter SATA_MIN_INIT_0 = 12; - parameter SATA_MIN_INIT_1 = 12; - parameter SATA_MIN_WAKE_0 = 4; - parameter SATA_MIN_WAKE_1 = 4; - parameter SIM_GTXRESET_SPEEDUP = 0; - parameter TERMINATION_IMP_0 = 50; - parameter TERMINATION_IMP_1 = 50; - output DRDY; - output PHYSTATUS0; - output PHYSTATUS1; - output PLLLKDET; - output REFCLKOUT; - output RESETDONE0; - output RESETDONE1; - output RXBYTEISALIGNED0; - output RXBYTEISALIGNED1; - output RXBYTEREALIGN0; - output RXBYTEREALIGN1; - output RXCHANBONDSEQ0; - output RXCHANBONDSEQ1; - output RXCHANISALIGNED0; - output RXCHANISALIGNED1; - output RXCHANREALIGN0; - output RXCHANREALIGN1; - output RXCOMMADET0; - output RXCOMMADET1; - output RXDATAVALID0; - output RXDATAVALID1; - output RXELECIDLE0; - output RXELECIDLE1; - output RXHEADERVALID0; - output RXHEADERVALID1; - output RXOVERSAMPLEERR0; - output RXOVERSAMPLEERR1; - output RXPRBSERR0; - output RXPRBSERR1; - output RXRECCLK0; - output RXRECCLK1; - output RXSTARTOFSEQ0; - output RXSTARTOFSEQ1; - output RXVALID0; - output RXVALID1; - output TXGEARBOXREADY0; - output TXGEARBOXREADY1; - output TXN0; - output TXN1; - output TXOUTCLK0; - output TXOUTCLK1; - output TXP0; - output TXP1; - output [15:0] DO; - output [1:0] RXLOSSOFSYNC0; - output [1:0] RXLOSSOFSYNC1; - output [1:0] TXBUFSTATUS0; - output [1:0] TXBUFSTATUS1; - output [2:0] DFESENSCAL0; - output [2:0] DFESENSCAL1; - output [2:0] RXBUFSTATUS0; - output [2:0] RXBUFSTATUS1; - output [2:0] RXCLKCORCNT0; - output [2:0] RXCLKCORCNT1; - output [2:0] RXHEADER0; - output [2:0] RXHEADER1; - output [2:0] RXSTATUS0; - output [2:0] RXSTATUS1; - output [31:0] RXDATA0; - output [31:0] RXDATA1; - output [3:0] DFETAP3MONITOR0; - output [3:0] DFETAP3MONITOR1; - output [3:0] DFETAP4MONITOR0; - output [3:0] DFETAP4MONITOR1; - output [3:0] RXCHARISCOMMA0; - output [3:0] RXCHARISCOMMA1; - output [3:0] RXCHARISK0; - output [3:0] RXCHARISK1; - output [3:0] RXCHBONDO0; - output [3:0] RXCHBONDO1; - output [3:0] RXDISPERR0; - output [3:0] RXDISPERR1; - output [3:0] RXNOTINTABLE0; - output [3:0] RXNOTINTABLE1; - output [3:0] RXRUNDISP0; - output [3:0] RXRUNDISP1; - output [3:0] TXKERR0; - output [3:0] TXKERR1; - output [3:0] TXRUNDISP0; - output [3:0] TXRUNDISP1; - output [4:0] DFEEYEDACMONITOR0; - output [4:0] DFEEYEDACMONITOR1; - output [4:0] DFETAP1MONITOR0; - output [4:0] DFETAP1MONITOR1; - output [4:0] DFETAP2MONITOR0; - output [4:0] DFETAP2MONITOR1; - output [5:0] DFECLKDLYADJMONITOR0; - output [5:0] DFECLKDLYADJMONITOR1; - input CLKIN; - input DCLK; - input DEN; - input DWE; - input GTXRESET; - input INTDATAWIDTH; - input PLLLKDETEN; - input PLLPOWERDOWN; - input PRBSCNTRESET0; - input PRBSCNTRESET1; - input REFCLKPWRDNB; - input RXBUFRESET0; - input RXBUFRESET1; - input RXCDRRESET0; - input RXCDRRESET1; - input RXCOMMADETUSE0; - input RXCOMMADETUSE1; - input RXDEC8B10BUSE0; - input RXDEC8B10BUSE1; - input RXENCHANSYNC0; - input RXENCHANSYNC1; - input RXENEQB0; - input RXENEQB1; - input RXENMCOMMAALIGN0; - input RXENMCOMMAALIGN1; - input RXENPCOMMAALIGN0; - input RXENPCOMMAALIGN1; - input RXENPMAPHASEALIGN0; - input RXENPMAPHASEALIGN1; - input RXENSAMPLEALIGN0; - input RXENSAMPLEALIGN1; - input RXGEARBOXSLIP0; - input RXGEARBOXSLIP1; - input RXN0; - input RXN1; - input RXP0; - input RXP1; - input RXPMASETPHASE0; - input RXPMASETPHASE1; - input RXPOLARITY0; - input RXPOLARITY1; - input RXRESET0; - input RXRESET1; - input RXSLIDE0; - input RXSLIDE1; - input RXUSRCLK0; - input RXUSRCLK1; - input RXUSRCLK20; - input RXUSRCLK21; - input TXCOMSTART0; - input TXCOMSTART1; - input TXCOMTYPE0; - input TXCOMTYPE1; - input TXDETECTRX0; - input TXDETECTRX1; - input TXELECIDLE0; - input TXELECIDLE1; - input TXENC8B10BUSE0; - input TXENC8B10BUSE1; - input TXENPMAPHASEALIGN0; - input TXENPMAPHASEALIGN1; - input TXINHIBIT0; - input TXINHIBIT1; - input TXPMASETPHASE0; - input TXPMASETPHASE1; - input TXPOLARITY0; - input TXPOLARITY1; - input TXRESET0; - input TXRESET1; - input TXSTARTSEQ0; - input TXSTARTSEQ1; - input TXUSRCLK0; - input TXUSRCLK1; - input TXUSRCLK20; - input TXUSRCLK21; - input [13:0] GTXTEST; - input [15:0] DI; - input [1:0] RXDATAWIDTH0; - input [1:0] RXDATAWIDTH1; - input [1:0] RXENPRBSTST0; - input [1:0] RXENPRBSTST1; - input [1:0] RXEQMIX0; - input [1:0] RXEQMIX1; - input [1:0] RXPOWERDOWN0; - input [1:0] RXPOWERDOWN1; - input [1:0] TXDATAWIDTH0; - input [1:0] TXDATAWIDTH1; - input [1:0] TXENPRBSTST0; - input [1:0] TXENPRBSTST1; - input [1:0] TXPOWERDOWN0; - input [1:0] TXPOWERDOWN1; - input [2:0] LOOPBACK0; - input [2:0] LOOPBACK1; - input [2:0] TXBUFDIFFCTRL0; - input [2:0] TXBUFDIFFCTRL1; - input [2:0] TXDIFFCTRL0; - input [2:0] TXDIFFCTRL1; - input [2:0] TXHEADER0; - input [2:0] TXHEADER1; - input [31:0] TXDATA0; - input [31:0] TXDATA1; - input [3:0] DFETAP30; - input [3:0] DFETAP31; - input [3:0] DFETAP40; - input [3:0] DFETAP41; - input [3:0] RXCHBONDI0; - input [3:0] RXCHBONDI1; - input [3:0] RXEQPOLE0; - input [3:0] RXEQPOLE1; - input [3:0] TXBYPASS8B10B0; - input [3:0] TXBYPASS8B10B1; - input [3:0] TXCHARDISPMODE0; - input [3:0] TXCHARDISPMODE1; - input [3:0] TXCHARDISPVAL0; - input [3:0] TXCHARDISPVAL1; - input [3:0] TXCHARISK0; - input [3:0] TXCHARISK1; - input [3:0] TXPREEMPHASIS0; - input [3:0] TXPREEMPHASIS1; - input [4:0] DFETAP10; - input [4:0] DFETAP11; - input [4:0] DFETAP20; - input [4:0] DFETAP21; - input [5:0] DFECLKDLYADJ0; - input [5:0] DFECLKDLYADJ1; - input [6:0] DADDR; - input [6:0] TXSEQUENCE0; - input [6:0] TXSEQUENCE1; -endmodule - -module CRC32 (...); - parameter CRC_INIT = 32'hFFFFFFFF; - output [31:0] CRCOUT; - (* clkbuf_sink *) - input CRCCLK; - input CRCDATAVALID; - input [2:0] CRCDATAWIDTH; - input [31:0] CRCIN; - input CRCRESET; -endmodule - -module CRC64 (...); - parameter CRC_INIT = 32'hFFFFFFFF; - output [31:0] CRCOUT; - (* clkbuf_sink *) - input CRCCLK; - input CRCDATAVALID; - input [2:0] CRCDATAWIDTH; - input [63:0] CRCIN; - input CRCRESET; -endmodule - -module GTHE1_QUAD (...); - parameter [15:0] BER_CONST_PTRN0 = 16'h0000; - parameter [15:0] BER_CONST_PTRN1 = 16'h0000; - parameter [15:0] BUFFER_CONFIG_LANE0 = 16'h4004; - parameter [15:0] BUFFER_CONFIG_LANE1 = 16'h4004; - parameter [15:0] BUFFER_CONFIG_LANE2 = 16'h4004; - parameter [15:0] BUFFER_CONFIG_LANE3 = 16'h4004; - parameter [15:0] DFE_TRAIN_CTRL_LANE0 = 16'h0000; - parameter [15:0] DFE_TRAIN_CTRL_LANE1 = 16'h0000; - parameter [15:0] DFE_TRAIN_CTRL_LANE2 = 16'h0000; - parameter [15:0] DFE_TRAIN_CTRL_LANE3 = 16'h0000; - parameter [15:0] DLL_CFG0 = 16'h8202; - parameter [15:0] DLL_CFG1 = 16'h0000; - parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE0 = 16'h0000; - parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE1 = 16'h0000; - parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE2 = 16'h0000; - parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE3 = 16'h0000; - parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE0 = 16'h0000; - parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE1 = 16'h0000; - parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE2 = 16'h0000; - parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE3 = 16'h0000; - parameter [15:0] E10GBASEKR_PMA_CTRL_LANE0 = 16'h0002; - parameter [15:0] E10GBASEKR_PMA_CTRL_LANE1 = 16'h0002; - parameter [15:0] E10GBASEKR_PMA_CTRL_LANE2 = 16'h0002; - parameter [15:0] E10GBASEKR_PMA_CTRL_LANE3 = 16'h0002; - parameter [15:0] E10GBASEKX_CTRL_LANE0 = 16'h0000; - parameter [15:0] E10GBASEKX_CTRL_LANE1 = 16'h0000; - parameter [15:0] E10GBASEKX_CTRL_LANE2 = 16'h0000; - parameter [15:0] E10GBASEKX_CTRL_LANE3 = 16'h0000; - parameter [15:0] E10GBASER_PCS_CFG_LANE0 = 16'h070C; - parameter [15:0] E10GBASER_PCS_CFG_LANE1 = 16'h070C; - parameter [15:0] E10GBASER_PCS_CFG_LANE2 = 16'h070C; - parameter [15:0] E10GBASER_PCS_CFG_LANE3 = 16'h070C; - parameter [15:0] E10GBASER_PCS_SEEDA0_LANE0 = 16'h0001; - parameter [15:0] E10GBASER_PCS_SEEDA0_LANE1 = 16'h0001; - parameter [15:0] E10GBASER_PCS_SEEDA0_LANE2 = 16'h0001; - parameter [15:0] E10GBASER_PCS_SEEDA0_LANE3 = 16'h0001; - parameter [15:0] E10GBASER_PCS_SEEDA1_LANE0 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDA1_LANE1 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDA1_LANE2 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDA1_LANE3 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDA2_LANE0 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDA2_LANE1 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDA2_LANE2 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDA2_LANE3 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDA3_LANE0 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDA3_LANE1 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDA3_LANE2 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDA3_LANE3 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDB0_LANE0 = 16'h0001; - parameter [15:0] E10GBASER_PCS_SEEDB0_LANE1 = 16'h0001; - parameter [15:0] E10GBASER_PCS_SEEDB0_LANE2 = 16'h0001; - parameter [15:0] E10GBASER_PCS_SEEDB0_LANE3 = 16'h0001; - parameter [15:0] E10GBASER_PCS_SEEDB1_LANE0 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDB1_LANE1 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDB1_LANE2 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDB1_LANE3 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDB2_LANE0 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDB2_LANE1 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDB2_LANE2 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDB2_LANE3 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDB3_LANE0 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDB3_LANE1 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDB3_LANE2 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDB3_LANE3 = 16'h0000; - parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE0 = 16'h0000; - parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE1 = 16'h0000; - parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE2 = 16'h0000; - parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE3 = 16'h0000; - parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE0 = 16'h0000; - parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE1 = 16'h0000; - parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE2 = 16'h0000; - parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE3 = 16'h0000; - parameter [15:0] GLBL0_NOISE_CTRL = 16'hF0B8; - parameter [15:0] GLBL_AMON_SEL = 16'h0000; - parameter [15:0] GLBL_DMON_SEL = 16'h0200; - parameter [15:0] GLBL_PWR_CTRL = 16'h0000; - parameter [0:0] GTH_CFG_PWRUP_LANE0 = 1'b1; - parameter [0:0] GTH_CFG_PWRUP_LANE1 = 1'b1; - parameter [0:0] GTH_CFG_PWRUP_LANE2 = 1'b1; - parameter [0:0] GTH_CFG_PWRUP_LANE3 = 1'b1; - parameter [15:0] LANE_AMON_SEL = 16'h00F0; - parameter [15:0] LANE_DMON_SEL = 16'h0000; - parameter [15:0] LANE_LNK_CFGOVRD = 16'h0000; - parameter [15:0] LANE_PWR_CTRL_LANE0 = 16'h0400; - parameter [15:0] LANE_PWR_CTRL_LANE1 = 16'h0400; - parameter [15:0] LANE_PWR_CTRL_LANE2 = 16'h0400; - parameter [15:0] LANE_PWR_CTRL_LANE3 = 16'h0400; - parameter [15:0] LNK_TRN_CFG_LANE0 = 16'h0000; - parameter [15:0] LNK_TRN_CFG_LANE1 = 16'h0000; - parameter [15:0] LNK_TRN_CFG_LANE2 = 16'h0000; - parameter [15:0] LNK_TRN_CFG_LANE3 = 16'h0000; - parameter [15:0] LNK_TRN_COEFF_REQ_LANE0 = 16'h0000; - parameter [15:0] LNK_TRN_COEFF_REQ_LANE1 = 16'h0000; - parameter [15:0] LNK_TRN_COEFF_REQ_LANE2 = 16'h0000; - parameter [15:0] LNK_TRN_COEFF_REQ_LANE3 = 16'h0000; - parameter [15:0] MISC_CFG = 16'h0008; - parameter [15:0] MODE_CFG1 = 16'h0000; - parameter [15:0] MODE_CFG2 = 16'h0000; - parameter [15:0] MODE_CFG3 = 16'h0000; - parameter [15:0] MODE_CFG4 = 16'h0000; - parameter [15:0] MODE_CFG5 = 16'h0000; - parameter [15:0] MODE_CFG6 = 16'h0000; - parameter [15:0] MODE_CFG7 = 16'h0000; - parameter [15:0] PCS_ABILITY_LANE0 = 16'h0010; - parameter [15:0] PCS_ABILITY_LANE1 = 16'h0010; - parameter [15:0] PCS_ABILITY_LANE2 = 16'h0010; - parameter [15:0] PCS_ABILITY_LANE3 = 16'h0010; - parameter [15:0] PCS_CTRL1_LANE0 = 16'h2040; - parameter [15:0] PCS_CTRL1_LANE1 = 16'h2040; - parameter [15:0] PCS_CTRL1_LANE2 = 16'h2040; - parameter [15:0] PCS_CTRL1_LANE3 = 16'h2040; - parameter [15:0] PCS_CTRL2_LANE0 = 16'h0000; - parameter [15:0] PCS_CTRL2_LANE1 = 16'h0000; - parameter [15:0] PCS_CTRL2_LANE2 = 16'h0000; - parameter [15:0] PCS_CTRL2_LANE3 = 16'h0000; - parameter [15:0] PCS_MISC_CFG_0_LANE0 = 16'h1116; - parameter [15:0] PCS_MISC_CFG_0_LANE1 = 16'h1116; - parameter [15:0] PCS_MISC_CFG_0_LANE2 = 16'h1116; - parameter [15:0] PCS_MISC_CFG_0_LANE3 = 16'h1116; - parameter [15:0] PCS_MISC_CFG_1_LANE0 = 16'h0000; - parameter [15:0] PCS_MISC_CFG_1_LANE1 = 16'h0000; - parameter [15:0] PCS_MISC_CFG_1_LANE2 = 16'h0000; - parameter [15:0] PCS_MISC_CFG_1_LANE3 = 16'h0000; - parameter [15:0] PCS_MODE_LANE0 = 16'h0000; - parameter [15:0] PCS_MODE_LANE1 = 16'h0000; - parameter [15:0] PCS_MODE_LANE2 = 16'h0000; - parameter [15:0] PCS_MODE_LANE3 = 16'h0000; - parameter [15:0] PCS_RESET_1_LANE0 = 16'h0002; - parameter [15:0] PCS_RESET_1_LANE1 = 16'h0002; - parameter [15:0] PCS_RESET_1_LANE2 = 16'h0002; - parameter [15:0] PCS_RESET_1_LANE3 = 16'h0002; - parameter [15:0] PCS_RESET_LANE0 = 16'h0000; - parameter [15:0] PCS_RESET_LANE1 = 16'h0000; - parameter [15:0] PCS_RESET_LANE2 = 16'h0000; - parameter [15:0] PCS_RESET_LANE3 = 16'h0000; - parameter [15:0] PCS_TYPE_LANE0 = 16'h002C; - parameter [15:0] PCS_TYPE_LANE1 = 16'h002C; - parameter [15:0] PCS_TYPE_LANE2 = 16'h002C; - parameter [15:0] PCS_TYPE_LANE3 = 16'h002C; - parameter [15:0] PLL_CFG0 = 16'h95DF; - parameter [15:0] PLL_CFG1 = 16'h81C0; - parameter [15:0] PLL_CFG2 = 16'h0424; - parameter [15:0] PMA_CTRL1_LANE0 = 16'h0000; - parameter [15:0] PMA_CTRL1_LANE1 = 16'h0000; - parameter [15:0] PMA_CTRL1_LANE2 = 16'h0000; - parameter [15:0] PMA_CTRL1_LANE3 = 16'h0000; - parameter [15:0] PMA_CTRL2_LANE0 = 16'h000B; - parameter [15:0] PMA_CTRL2_LANE1 = 16'h000B; - parameter [15:0] PMA_CTRL2_LANE2 = 16'h000B; - parameter [15:0] PMA_CTRL2_LANE3 = 16'h000B; - parameter [15:0] PMA_LPBK_CTRL_LANE0 = 16'h0004; - parameter [15:0] PMA_LPBK_CTRL_LANE1 = 16'h0004; - parameter [15:0] PMA_LPBK_CTRL_LANE2 = 16'h0004; - parameter [15:0] PMA_LPBK_CTRL_LANE3 = 16'h0004; - parameter [15:0] PRBS_BER_CFG0_LANE0 = 16'h0000; - parameter [15:0] PRBS_BER_CFG0_LANE1 = 16'h0000; - parameter [15:0] PRBS_BER_CFG0_LANE2 = 16'h0000; - parameter [15:0] PRBS_BER_CFG0_LANE3 = 16'h0000; - parameter [15:0] PRBS_BER_CFG1_LANE0 = 16'h0000; - parameter [15:0] PRBS_BER_CFG1_LANE1 = 16'h0000; - parameter [15:0] PRBS_BER_CFG1_LANE2 = 16'h0000; - parameter [15:0] PRBS_BER_CFG1_LANE3 = 16'h0000; - parameter [15:0] PRBS_CFG_LANE0 = 16'h000A; - parameter [15:0] PRBS_CFG_LANE1 = 16'h000A; - parameter [15:0] PRBS_CFG_LANE2 = 16'h000A; - parameter [15:0] PRBS_CFG_LANE3 = 16'h000A; - parameter [15:0] PTRN_CFG0_LSB = 16'h5555; - parameter [15:0] PTRN_CFG0_MSB = 16'h5555; - parameter [15:0] PTRN_LEN_CFG = 16'h001F; - parameter [15:0] PWRUP_DLY = 16'h0000; - parameter [15:0] RX_AEQ_VAL0_LANE0 = 16'h03C0; - parameter [15:0] RX_AEQ_VAL0_LANE1 = 16'h03C0; - parameter [15:0] RX_AEQ_VAL0_LANE2 = 16'h03C0; - parameter [15:0] RX_AEQ_VAL0_LANE3 = 16'h03C0; - parameter [15:0] RX_AEQ_VAL1_LANE0 = 16'h0000; - parameter [15:0] RX_AEQ_VAL1_LANE1 = 16'h0000; - parameter [15:0] RX_AEQ_VAL1_LANE2 = 16'h0000; - parameter [15:0] RX_AEQ_VAL1_LANE3 = 16'h0000; - parameter [15:0] RX_AGC_CTRL_LANE0 = 16'h0000; - parameter [15:0] RX_AGC_CTRL_LANE1 = 16'h0000; - parameter [15:0] RX_AGC_CTRL_LANE2 = 16'h0000; - parameter [15:0] RX_AGC_CTRL_LANE3 = 16'h0000; - parameter [15:0] RX_CDR_CTRL0_LANE0 = 16'h0005; - parameter [15:0] RX_CDR_CTRL0_LANE1 = 16'h0005; - parameter [15:0] RX_CDR_CTRL0_LANE2 = 16'h0005; - parameter [15:0] RX_CDR_CTRL0_LANE3 = 16'h0005; - parameter [15:0] RX_CDR_CTRL1_LANE0 = 16'h4200; - parameter [15:0] RX_CDR_CTRL1_LANE1 = 16'h4200; - parameter [15:0] RX_CDR_CTRL1_LANE2 = 16'h4200; - parameter [15:0] RX_CDR_CTRL1_LANE3 = 16'h4200; - parameter [15:0] RX_CDR_CTRL2_LANE0 = 16'h2000; - parameter [15:0] RX_CDR_CTRL2_LANE1 = 16'h2000; - parameter [15:0] RX_CDR_CTRL2_LANE2 = 16'h2000; - parameter [15:0] RX_CDR_CTRL2_LANE3 = 16'h2000; - parameter [15:0] RX_CFG0_LANE0 = 16'h0500; - parameter [15:0] RX_CFG0_LANE1 = 16'h0500; - parameter [15:0] RX_CFG0_LANE2 = 16'h0500; - parameter [15:0] RX_CFG0_LANE3 = 16'h0500; - parameter [15:0] RX_CFG1_LANE0 = 16'h821F; - parameter [15:0] RX_CFG1_LANE1 = 16'h821F; - parameter [15:0] RX_CFG1_LANE2 = 16'h821F; - parameter [15:0] RX_CFG1_LANE3 = 16'h821F; - parameter [15:0] RX_CFG2_LANE0 = 16'h1001; - parameter [15:0] RX_CFG2_LANE1 = 16'h1001; - parameter [15:0] RX_CFG2_LANE2 = 16'h1001; - parameter [15:0] RX_CFG2_LANE3 = 16'h1001; - parameter [15:0] RX_CTLE_CTRL_LANE0 = 16'h008F; - parameter [15:0] RX_CTLE_CTRL_LANE1 = 16'h008F; - parameter [15:0] RX_CTLE_CTRL_LANE2 = 16'h008F; - parameter [15:0] RX_CTLE_CTRL_LANE3 = 16'h008F; - parameter [15:0] RX_CTRL_OVRD_LANE0 = 16'h000C; - parameter [15:0] RX_CTRL_OVRD_LANE1 = 16'h000C; - parameter [15:0] RX_CTRL_OVRD_LANE2 = 16'h000C; - parameter [15:0] RX_CTRL_OVRD_LANE3 = 16'h000C; - parameter integer RX_FABRIC_WIDTH0 = 6466; - parameter integer RX_FABRIC_WIDTH1 = 6466; - parameter integer RX_FABRIC_WIDTH2 = 6466; - parameter integer RX_FABRIC_WIDTH3 = 6466; - parameter [15:0] RX_LOOP_CTRL_LANE0 = 16'h007F; - parameter [15:0] RX_LOOP_CTRL_LANE1 = 16'h007F; - parameter [15:0] RX_LOOP_CTRL_LANE2 = 16'h007F; - parameter [15:0] RX_LOOP_CTRL_LANE3 = 16'h007F; - parameter [15:0] RX_MVAL0_LANE0 = 16'h0000; - parameter [15:0] RX_MVAL0_LANE1 = 16'h0000; - parameter [15:0] RX_MVAL0_LANE2 = 16'h0000; - parameter [15:0] RX_MVAL0_LANE3 = 16'h0000; - parameter [15:0] RX_MVAL1_LANE0 = 16'h0000; - parameter [15:0] RX_MVAL1_LANE1 = 16'h0000; - parameter [15:0] RX_MVAL1_LANE2 = 16'h0000; - parameter [15:0] RX_MVAL1_LANE3 = 16'h0000; - parameter [15:0] RX_P0S_CTRL = 16'h1206; - parameter [15:0] RX_P0_CTRL = 16'h11F0; - parameter [15:0] RX_P1_CTRL = 16'h120F; - parameter [15:0] RX_P2_CTRL = 16'h0E0F; - parameter [15:0] RX_PI_CTRL0 = 16'hD2F0; - parameter [15:0] RX_PI_CTRL1 = 16'h0080; - parameter integer SIM_GTHRESET_SPEEDUP = 1; - parameter SIM_VERSION = "1.0"; - parameter [15:0] SLICE_CFG = 16'h0000; - parameter [15:0] SLICE_NOISE_CTRL_0_LANE01 = 16'h0000; - parameter [15:0] SLICE_NOISE_CTRL_0_LANE23 = 16'h0000; - parameter [15:0] SLICE_NOISE_CTRL_1_LANE01 = 16'h0000; - parameter [15:0] SLICE_NOISE_CTRL_1_LANE23 = 16'h0000; - parameter [15:0] SLICE_NOISE_CTRL_2_LANE01 = 16'h7FFF; - parameter [15:0] SLICE_NOISE_CTRL_2_LANE23 = 16'h7FFF; - parameter [15:0] SLICE_TX_RESET_LANE01 = 16'h0000; - parameter [15:0] SLICE_TX_RESET_LANE23 = 16'h0000; - parameter [15:0] TERM_CTRL_LANE0 = 16'h5007; - parameter [15:0] TERM_CTRL_LANE1 = 16'h5007; - parameter [15:0] TERM_CTRL_LANE2 = 16'h5007; - parameter [15:0] TERM_CTRL_LANE3 = 16'h5007; - parameter [15:0] TX_CFG0_LANE0 = 16'h203D; - parameter [15:0] TX_CFG0_LANE1 = 16'h203D; - parameter [15:0] TX_CFG0_LANE2 = 16'h203D; - parameter [15:0] TX_CFG0_LANE3 = 16'h203D; - parameter [15:0] TX_CFG1_LANE0 = 16'h0F00; - parameter [15:0] TX_CFG1_LANE1 = 16'h0F00; - parameter [15:0] TX_CFG1_LANE2 = 16'h0F00; - parameter [15:0] TX_CFG1_LANE3 = 16'h0F00; - parameter [15:0] TX_CFG2_LANE0 = 16'h0081; - parameter [15:0] TX_CFG2_LANE1 = 16'h0081; - parameter [15:0] TX_CFG2_LANE2 = 16'h0081; - parameter [15:0] TX_CFG2_LANE3 = 16'h0081; - parameter [15:0] TX_CLK_SEL0_LANE0 = 16'h2121; - parameter [15:0] TX_CLK_SEL0_LANE1 = 16'h2121; - parameter [15:0] TX_CLK_SEL0_LANE2 = 16'h2121; - parameter [15:0] TX_CLK_SEL0_LANE3 = 16'h2121; - parameter [15:0] TX_CLK_SEL1_LANE0 = 16'h2121; - parameter [15:0] TX_CLK_SEL1_LANE1 = 16'h2121; - parameter [15:0] TX_CLK_SEL1_LANE2 = 16'h2121; - parameter [15:0] TX_CLK_SEL1_LANE3 = 16'h2121; - parameter [15:0] TX_DISABLE_LANE0 = 16'h0000; - parameter [15:0] TX_DISABLE_LANE1 = 16'h0000; - parameter [15:0] TX_DISABLE_LANE2 = 16'h0000; - parameter [15:0] TX_DISABLE_LANE3 = 16'h0000; - parameter integer TX_FABRIC_WIDTH0 = 6466; - parameter integer TX_FABRIC_WIDTH1 = 6466; - parameter integer TX_FABRIC_WIDTH2 = 6466; - parameter integer TX_FABRIC_WIDTH3 = 6466; - parameter [15:0] TX_P0P0S_CTRL = 16'h060C; - parameter [15:0] TX_P1P2_CTRL = 16'h0C39; - parameter [15:0] TX_PREEMPH_LANE0 = 16'h00A1; - parameter [15:0] TX_PREEMPH_LANE1 = 16'h00A1; - parameter [15:0] TX_PREEMPH_LANE2 = 16'h00A1; - parameter [15:0] TX_PREEMPH_LANE3 = 16'h00A1; - parameter [15:0] TX_PWR_RATE_OVRD_LANE0 = 16'h0060; - parameter [15:0] TX_PWR_RATE_OVRD_LANE1 = 16'h0060; - parameter [15:0] TX_PWR_RATE_OVRD_LANE2 = 16'h0060; - parameter [15:0] TX_PWR_RATE_OVRD_LANE3 = 16'h0060; - output DRDY; - output GTHINITDONE; - output MGMTPCSRDACK; - output RXCTRLACK0; - output RXCTRLACK1; - output RXCTRLACK2; - output RXCTRLACK3; - output RXDATATAP0; - output RXDATATAP1; - output RXDATATAP2; - output RXDATATAP3; - output RXPCSCLKSMPL0; - output RXPCSCLKSMPL1; - output RXPCSCLKSMPL2; - output RXPCSCLKSMPL3; - output RXUSERCLKOUT0; - output RXUSERCLKOUT1; - output RXUSERCLKOUT2; - output RXUSERCLKOUT3; - output TSTPATH; - output TSTREFCLKFAB; - output TSTREFCLKOUT; - output TXCTRLACK0; - output TXCTRLACK1; - output TXCTRLACK2; - output TXCTRLACK3; - output TXDATATAP10; - output TXDATATAP11; - output TXDATATAP12; - output TXDATATAP13; - output TXDATATAP20; - output TXDATATAP21; - output TXDATATAP22; - output TXDATATAP23; - output TXN0; - output TXN1; - output TXN2; - output TXN3; - output TXP0; - output TXP1; - output TXP2; - output TXP3; - output TXPCSCLKSMPL0; - output TXPCSCLKSMPL1; - output TXPCSCLKSMPL2; - output TXPCSCLKSMPL3; - output TXUSERCLKOUT0; - output TXUSERCLKOUT1; - output TXUSERCLKOUT2; - output TXUSERCLKOUT3; - output [15:0] DRPDO; - output [15:0] MGMTPCSRDDATA; - output [63:0] RXDATA0; - output [63:0] RXDATA1; - output [63:0] RXDATA2; - output [63:0] RXDATA3; - output [7:0] RXCODEERR0; - output [7:0] RXCODEERR1; - output [7:0] RXCODEERR2; - output [7:0] RXCODEERR3; - output [7:0] RXCTRL0; - output [7:0] RXCTRL1; - output [7:0] RXCTRL2; - output [7:0] RXCTRL3; - output [7:0] RXDISPERR0; - output [7:0] RXDISPERR1; - output [7:0] RXDISPERR2; - output [7:0] RXDISPERR3; - output [7:0] RXVALID0; - output [7:0] RXVALID1; - output [7:0] RXVALID2; - output [7:0] RXVALID3; - input DCLK; - input DEN; - input DFETRAINCTRL0; - input DFETRAINCTRL1; - input DFETRAINCTRL2; - input DFETRAINCTRL3; - input DISABLEDRP; - input DWE; - input GTHINIT; - input GTHRESET; - input GTHX2LANE01; - input GTHX2LANE23; - input GTHX4LANE; - input MGMTPCSREGRD; - input MGMTPCSREGWR; - input POWERDOWN0; - input POWERDOWN1; - input POWERDOWN2; - input POWERDOWN3; - input REFCLK; - input RXBUFRESET0; - input RXBUFRESET1; - input RXBUFRESET2; - input RXBUFRESET3; - input RXENCOMMADET0; - input RXENCOMMADET1; - input RXENCOMMADET2; - input RXENCOMMADET3; - input RXN0; - input RXN1; - input RXN2; - input RXN3; - input RXP0; - input RXP1; - input RXP2; - input RXP3; - input RXPOLARITY0; - input RXPOLARITY1; - input RXPOLARITY2; - input RXPOLARITY3; - input RXSLIP0; - input RXSLIP1; - input RXSLIP2; - input RXSLIP3; - input RXUSERCLKIN0; - input RXUSERCLKIN1; - input RXUSERCLKIN2; - input RXUSERCLKIN3; - input TXBUFRESET0; - input TXBUFRESET1; - input TXBUFRESET2; - input TXBUFRESET3; - input TXDEEMPH0; - input TXDEEMPH1; - input TXDEEMPH2; - input TXDEEMPH3; - input TXUSERCLKIN0; - input TXUSERCLKIN1; - input TXUSERCLKIN2; - input TXUSERCLKIN3; - input [15:0] DADDR; - input [15:0] DI; - input [15:0] MGMTPCSREGADDR; - input [15:0] MGMTPCSWRDATA; - input [1:0] RXPOWERDOWN0; - input [1:0] RXPOWERDOWN1; - input [1:0] RXPOWERDOWN2; - input [1:0] RXPOWERDOWN3; - input [1:0] RXRATE0; - input [1:0] RXRATE1; - input [1:0] RXRATE2; - input [1:0] RXRATE3; - input [1:0] TXPOWERDOWN0; - input [1:0] TXPOWERDOWN1; - input [1:0] TXPOWERDOWN2; - input [1:0] TXPOWERDOWN3; - input [1:0] TXRATE0; - input [1:0] TXRATE1; - input [1:0] TXRATE2; - input [1:0] TXRATE3; - input [2:0] PLLREFCLKSEL; - input [2:0] SAMPLERATE0; - input [2:0] SAMPLERATE1; - input [2:0] SAMPLERATE2; - input [2:0] SAMPLERATE3; - input [2:0] TXMARGIN0; - input [2:0] TXMARGIN1; - input [2:0] TXMARGIN2; - input [2:0] TXMARGIN3; - input [3:0] MGMTPCSLANESEL; - input [4:0] MGMTPCSMMDADDR; - input [5:0] PLLPCSCLKDIV; - input [63:0] TXDATA0; - input [63:0] TXDATA1; - input [63:0] TXDATA2; - input [63:0] TXDATA3; - input [7:0] TXCTRL0; - input [7:0] TXCTRL1; - input [7:0] TXCTRL2; - input [7:0] TXCTRL3; - input [7:0] TXDATAMSB0; - input [7:0] TXDATAMSB1; - input [7:0] TXDATAMSB2; - input [7:0] TXDATAMSB3; -endmodule - -module GTXE1 (...); - parameter AC_CAP_DIS = "TRUE"; - parameter integer ALIGN_COMMA_WORD = 1; - parameter [1:0] BGTEST_CFG = 2'b00; - parameter [16:0] BIAS_CFG = 17'h00000; - parameter [4:0] CDR_PH_ADJ_TIME = 5'b10100; - parameter integer CHAN_BOND_1_MAX_SKEW = 7; - parameter integer CHAN_BOND_2_MAX_SKEW = 1; - parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; - parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; - parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0001001010; - parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0001001010; - parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0110111100; - parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100111100; - parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100111100; - parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0110111100; - parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100111100; - parameter [4:0] CHAN_BOND_SEQ_2_CFG = 5'b00000; - parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; - parameter CHAN_BOND_SEQ_2_USE = "FALSE"; - parameter integer CHAN_BOND_SEQ_LEN = 1; - parameter CLK_CORRECT_USE = "TRUE"; - parameter integer CLK_COR_ADJ_LEN = 1; - parameter integer CLK_COR_DET_LEN = 1; - parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE"; - parameter CLK_COR_KEEP_IDLE = "FALSE"; - parameter integer CLK_COR_MAX_LAT = 20; - parameter integer CLK_COR_MIN_LAT = 18; - parameter CLK_COR_PRECEDENCE = "TRUE"; - parameter integer CLK_COR_REPEAT_WAIT = 0; - parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; - parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0000000000; - parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; - parameter CLK_COR_SEQ_2_USE = "FALSE"; - parameter [1:0] CM_TRIM = 2'b01; - parameter [9:0] COMMA_10B_ENABLE = 10'b1111111111; - parameter COMMA_DOUBLE = "FALSE"; - parameter [3:0] COM_BURST_VAL = 4'b1111; - parameter DEC_MCOMMA_DETECT = "TRUE"; - parameter DEC_PCOMMA_DETECT = "TRUE"; - parameter DEC_VALID_COMMA_ONLY = "TRUE"; - parameter [4:0] DFE_CAL_TIME = 5'b01100; - parameter [7:0] DFE_CFG = 8'b00011011; - parameter [2:0] GEARBOX_ENDEC = 3'b000; - parameter GEN_RXUSRCLK = "TRUE"; - parameter GEN_TXUSRCLK = "TRUE"; - parameter GTX_CFG_PWRUP = "TRUE"; - parameter [9:0] MCOMMA_10B_VALUE = 10'b1010000011; - parameter MCOMMA_DETECT = "TRUE"; - parameter [2:0] OOBDETECT_THRESHOLD = 3'b011; - parameter PCI_EXPRESS_MODE = "FALSE"; - parameter [9:0] PCOMMA_10B_VALUE = 10'b0101111100; - parameter PCOMMA_DETECT = "TRUE"; - parameter PMA_CAS_CLK_EN = "FALSE"; - parameter [26:0] PMA_CDR_SCAN = 27'h640404C; - parameter [75:0] PMA_CFG = 76'h0040000040000000003; - parameter [6:0] PMA_RXSYNC_CFG = 7'h00; - parameter [24:0] PMA_RX_CFG = 25'h05CE048; - parameter [19:0] PMA_TX_CFG = 20'h00082; - parameter [9:0] POWER_SAVE = 10'b0000110100; - parameter RCV_TERM_GND = "FALSE"; - parameter RCV_TERM_VTTRX = "TRUE"; - parameter RXGEARBOX_USE = "FALSE"; - parameter [23:0] RXPLL_COM_CFG = 24'h21680A; - parameter [7:0] RXPLL_CP_CFG = 8'h00; - parameter integer RXPLL_DIVSEL45_FB = 5; - parameter integer RXPLL_DIVSEL_FB = 2; - parameter integer RXPLL_DIVSEL_OUT = 1; - parameter integer RXPLL_DIVSEL_REF = 1; - parameter [2:0] RXPLL_LKDET_CFG = 3'b111; - parameter [0:0] RXPRBSERR_LOOPBACK = 1'b0; - parameter RXRECCLK_CTRL = "RXRECCLKPCS"; - parameter [9:0] RXRECCLK_DLY = 10'b0000000000; - parameter [15:0] RXUSRCLK_DLY = 16'h0000; - parameter RX_BUFFER_USE = "TRUE"; - parameter integer RX_CLK25_DIVIDER = 6; - parameter integer RX_DATA_WIDTH = 20; - parameter RX_DECODE_SEQ_MATCH = "TRUE"; - parameter [3:0] RX_DLYALIGN_CTRINC = 4'b0100; - parameter [4:0] RX_DLYALIGN_EDGESET = 5'b00110; - parameter [3:0] RX_DLYALIGN_LPFINC = 4'b0111; - parameter [2:0] RX_DLYALIGN_MONSEL = 3'b000; - parameter [7:0] RX_DLYALIGN_OVRDSETTING = 8'b00000000; - parameter RX_EN_IDLE_HOLD_CDR = "FALSE"; - parameter RX_EN_IDLE_HOLD_DFE = "TRUE"; - parameter RX_EN_IDLE_RESET_BUF = "TRUE"; - parameter RX_EN_IDLE_RESET_FR = "TRUE"; - parameter RX_EN_IDLE_RESET_PH = "TRUE"; - parameter RX_EN_MODE_RESET_BUF = "TRUE"; - parameter RX_EN_RATE_RESET_BUF = "TRUE"; - parameter RX_EN_REALIGN_RESET_BUF = "FALSE"; - parameter RX_EN_REALIGN_RESET_BUF2 = "FALSE"; - parameter [7:0] RX_EYE_OFFSET = 8'h4C; - parameter [1:0] RX_EYE_SCANMODE = 2'b00; - parameter RX_FIFO_ADDR_MODE = "FULL"; - parameter [3:0] RX_IDLE_HI_CNT = 4'b1000; - parameter [3:0] RX_IDLE_LO_CNT = 4'b0000; - parameter RX_LOSS_OF_SYNC_FSM = "FALSE"; - parameter integer RX_LOS_INVALID_INCR = 1; - parameter integer RX_LOS_THRESHOLD = 4; - parameter RX_OVERSAMPLE_MODE = "FALSE"; - parameter integer RX_SLIDE_AUTO_WAIT = 5; - parameter RX_SLIDE_MODE = "OFF"; - parameter RX_XCLK_SEL = "RXREC"; - parameter integer SAS_MAX_COMSAS = 52; - parameter integer SAS_MIN_COMSAS = 40; - parameter [2:0] SATA_BURST_VAL = 3'b100; - parameter [2:0] SATA_IDLE_VAL = 3'b100; - parameter integer SATA_MAX_BURST = 7; - parameter integer SATA_MAX_INIT = 22; - parameter integer SATA_MAX_WAKE = 7; - parameter integer SATA_MIN_BURST = 4; - parameter integer SATA_MIN_INIT = 12; - parameter integer SATA_MIN_WAKE = 4; - parameter SHOW_REALIGN_COMMA = "TRUE"; - parameter integer SIM_GTXRESET_SPEEDUP = 1; - parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; - parameter [2:0] SIM_RXREFCLK_SOURCE = 3'b000; - parameter [2:0] SIM_TXREFCLK_SOURCE = 3'b000; - parameter SIM_TX_ELEC_IDLE_LEVEL = "X"; - parameter SIM_VERSION = "2.0"; - parameter [4:0] TERMINATION_CTRL = 5'b10100; - parameter TERMINATION_OVRD = "FALSE"; - parameter [11:0] TRANS_TIME_FROM_P2 = 12'h03C; - parameter [7:0] TRANS_TIME_NON_P2 = 8'h19; - parameter [7:0] TRANS_TIME_RATE = 8'h0E; - parameter [9:0] TRANS_TIME_TO_P2 = 10'h064; - parameter [31:0] TST_ATTR = 32'h00000000; - parameter TXDRIVE_LOOPBACK_HIZ = "FALSE"; - parameter TXDRIVE_LOOPBACK_PD = "FALSE"; - parameter TXGEARBOX_USE = "FALSE"; - parameter TXOUTCLK_CTRL = "TXOUTCLKPCS"; - parameter [9:0] TXOUTCLK_DLY = 10'b0000000000; - parameter [23:0] TXPLL_COM_CFG = 24'h21680A; - parameter [7:0] TXPLL_CP_CFG = 8'h00; - parameter integer TXPLL_DIVSEL45_FB = 5; - parameter integer TXPLL_DIVSEL_FB = 2; - parameter integer TXPLL_DIVSEL_OUT = 1; - parameter integer TXPLL_DIVSEL_REF = 1; - parameter [2:0] TXPLL_LKDET_CFG = 3'b111; - parameter [1:0] TXPLL_SATA = 2'b00; - parameter TX_BUFFER_USE = "TRUE"; - parameter [5:0] TX_BYTECLK_CFG = 6'h00; - parameter integer TX_CLK25_DIVIDER = 6; - parameter TX_CLK_SOURCE = "RXPLL"; - parameter integer TX_DATA_WIDTH = 20; - parameter [4:0] TX_DEEMPH_0 = 5'b11010; - parameter [4:0] TX_DEEMPH_1 = 5'b10000; - parameter [13:0] TX_DETECT_RX_CFG = 14'h1832; - parameter [3:0] TX_DLYALIGN_CTRINC = 4'b0100; - parameter [3:0] TX_DLYALIGN_LPFINC = 4'b0110; - parameter [2:0] TX_DLYALIGN_MONSEL = 3'b000; - parameter [7:0] TX_DLYALIGN_OVRDSETTING = 8'b10000000; - parameter TX_DRIVE_MODE = "DIRECT"; - parameter TX_EN_RATE_RESET_BUF = "TRUE"; - parameter [2:0] TX_IDLE_ASSERT_DELAY = 3'b100; - parameter [2:0] TX_IDLE_DEASSERT_DELAY = 3'b010; - parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; - parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; - parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; - parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; - parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; - parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; - parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; - parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; - parameter TX_OVERSAMPLE_MODE = "FALSE"; - parameter [0:0] TX_PMADATA_OPT = 1'b0; - parameter [1:0] TX_TDCC_CFG = 2'b11; - parameter [5:0] TX_USRCLK_CFG = 6'h00; - parameter TX_XCLK_SEL = "TXUSR"; - output COMFINISH; - output COMINITDET; - output COMSASDET; - output COMWAKEDET; - output DRDY; - output PHYSTATUS; - output RXBYTEISALIGNED; - output RXBYTEREALIGN; - output RXCHANBONDSEQ; - output RXCHANISALIGNED; - output RXCHANREALIGN; - output RXCOMMADET; - output RXDATAVALID; - output RXELECIDLE; - output RXHEADERVALID; - output RXOVERSAMPLEERR; - output RXPLLLKDET; - output RXPRBSERR; - output RXRATEDONE; - output RXRECCLK; - output RXRECCLKPCS; - output RXRESETDONE; - output RXSTARTOFSEQ; - output RXVALID; - output TXGEARBOXREADY; - output TXN; - output TXOUTCLK; - output TXOUTCLKPCS; - output TXP; - output TXPLLLKDET; - output TXRATEDONE; - output TXRESETDONE; - output [15:0] DRPDO; - output [1:0] MGTREFCLKFAB; - output [1:0] RXLOSSOFSYNC; - output [1:0] TXBUFSTATUS; - output [2:0] DFESENSCAL; - output [2:0] RXBUFSTATUS; - output [2:0] RXCLKCORCNT; - output [2:0] RXHEADER; - output [2:0] RXSTATUS; - output [31:0] RXDATA; - output [3:0] DFETAP3MONITOR; - output [3:0] DFETAP4MONITOR; - output [3:0] RXCHARISCOMMA; - output [3:0] RXCHARISK; - output [3:0] RXCHBONDO; - output [3:0] RXDISPERR; - output [3:0] RXNOTINTABLE; - output [3:0] RXRUNDISP; - output [3:0] TXKERR; - output [3:0] TXRUNDISP; - output [4:0] DFEEYEDACMON; - output [4:0] DFETAP1MONITOR; - output [4:0] DFETAP2MONITOR; - output [5:0] DFECLKDLYADJMON; - output [7:0] RXDLYALIGNMONITOR; - output [7:0] TXDLYALIGNMONITOR; - output [9:0] TSTOUT; - input DCLK; - input DEN; - input DFEDLYOVRD; - input DFETAPOVRD; - input DWE; - input GATERXELECIDLE; - input GREFCLKRX; - input GREFCLKTX; - input GTXRXRESET; - input GTXTXRESET; - input IGNORESIGDET; - input PERFCLKRX; - input PERFCLKTX; - input PLLRXRESET; - input PLLTXRESET; - input PRBSCNTRESET; - input RXBUFRESET; - input RXCDRRESET; - input RXCHBONDMASTER; - input RXCHBONDSLAVE; - input RXCOMMADETUSE; - input RXDEC8B10BUSE; - input RXDLYALIGNDISABLE; - input RXDLYALIGNMONENB; - input RXDLYALIGNOVERRIDE; - input RXDLYALIGNRESET; - input RXDLYALIGNSWPPRECURB; - input RXDLYALIGNUPDSW; - input RXENCHANSYNC; - input RXENMCOMMAALIGN; - input RXENPCOMMAALIGN; - input RXENPMAPHASEALIGN; - input RXENSAMPLEALIGN; - input RXGEARBOXSLIP; - input RXN; - input RXP; - input RXPLLLKDETEN; - input RXPLLPOWERDOWN; - input RXPMASETPHASE; - input RXPOLARITY; - input RXRESET; - input RXSLIDE; - input RXUSRCLK2; - input RXUSRCLK; - input TSTCLK0; - input TSTCLK1; - input TXCOMINIT; - input TXCOMSAS; - input TXCOMWAKE; - input TXDEEMPH; - input TXDETECTRX; - input TXDLYALIGNDISABLE; - input TXDLYALIGNMONENB; - input TXDLYALIGNOVERRIDE; - input TXDLYALIGNRESET; - input TXDLYALIGNUPDSW; - input TXELECIDLE; - input TXENC8B10BUSE; - input TXENPMAPHASEALIGN; - input TXINHIBIT; - input TXPDOWNASYNCH; - input TXPLLLKDETEN; - input TXPLLPOWERDOWN; - input TXPMASETPHASE; - input TXPOLARITY; - input TXPRBSFORCEERR; - input TXRESET; - input TXSTARTSEQ; - input TXSWING; - input TXUSRCLK2; - input TXUSRCLK; - input USRCODEERR; - input [12:0] GTXTEST; - input [15:0] DI; - input [19:0] TSTIN; - input [1:0] MGTREFCLKRX; - input [1:0] MGTREFCLKTX; - input [1:0] NORTHREFCLKRX; - input [1:0] NORTHREFCLKTX; - input [1:0] RXPOWERDOWN; - input [1:0] RXRATE; - input [1:0] SOUTHREFCLKRX; - input [1:0] SOUTHREFCLKTX; - input [1:0] TXPOWERDOWN; - input [1:0] TXRATE; - input [2:0] LOOPBACK; - input [2:0] RXCHBONDLEVEL; - input [2:0] RXENPRBSTST; - input [2:0] RXPLLREFSELDY; - input [2:0] TXBUFDIFFCTRL; - input [2:0] TXENPRBSTST; - input [2:0] TXHEADER; - input [2:0] TXMARGIN; - input [2:0] TXPLLREFSELDY; - input [31:0] TXDATA; - input [3:0] DFETAP3; - input [3:0] DFETAP4; - input [3:0] RXCHBONDI; - input [3:0] TXBYPASS8B10B; - input [3:0] TXCHARDISPMODE; - input [3:0] TXCHARDISPVAL; - input [3:0] TXCHARISK; - input [3:0] TXDIFFCTRL; - input [3:0] TXPREEMPHASIS; - input [4:0] DFETAP1; - input [4:0] DFETAP2; - input [4:0] TXPOSTEMPHASIS; - input [5:0] DFECLKDLYADJ; - input [6:0] TXSEQUENCE; - input [7:0] DADDR; - input [9:0] RXEQMIX; -endmodule - -module IBUFDS_GTXE1 (...); - parameter CLKCM_CFG = "TRUE"; - parameter CLKRCV_TRST = "TRUE"; - parameter [9:0] REFCLKOUT_DLY = 10'b0000000000; - output O; - output ODIV2; - input CEB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module IBUFDS_GTHE1 (...); - output O; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module GTHE2_CHANNEL (...); - parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; - parameter [0:0] ACJTAG_MODE = 1'b0; - parameter [0:0] ACJTAG_RESET = 1'b0; - parameter [19:0] ADAPT_CFG0 = 20'h00C10; - parameter ALIGN_COMMA_DOUBLE = "FALSE"; - parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; - parameter integer ALIGN_COMMA_WORD = 1; - parameter ALIGN_MCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; - parameter ALIGN_PCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; - parameter [0:0] A_RXOSCALRESET = 1'b0; - parameter CBCC_DATA_SOURCE_SEL = "DECODED"; - parameter [41:0] CFOK_CFG = 42'h24800040E80; - parameter [5:0] CFOK_CFG2 = 6'b100000; - parameter [5:0] CFOK_CFG3 = 6'b100000; - parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; - parameter integer CHAN_BOND_MAX_SKEW = 7; - parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; - parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; - parameter CHAN_BOND_SEQ_2_USE = "FALSE"; - parameter integer CHAN_BOND_SEQ_LEN = 1; - parameter CLK_CORRECT_USE = "TRUE"; - parameter CLK_COR_KEEP_IDLE = "FALSE"; - parameter integer CLK_COR_MAX_LAT = 20; - parameter integer CLK_COR_MIN_LAT = 18; - parameter CLK_COR_PRECEDENCE = "TRUE"; - parameter integer CLK_COR_REPEAT_WAIT = 0; - parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; - parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; - parameter CLK_COR_SEQ_2_USE = "FALSE"; - parameter integer CLK_COR_SEQ_LEN = 1; - parameter [28:0] CPLL_CFG = 29'h00BC07DC; - parameter integer CPLL_FBDIV = 4; - parameter integer CPLL_FBDIV_45 = 5; - parameter [23:0] CPLL_INIT_CFG = 24'h00001E; - parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; - parameter integer CPLL_REFCLK_DIV = 1; - parameter DEC_MCOMMA_DETECT = "TRUE"; - parameter DEC_PCOMMA_DETECT = "TRUE"; - parameter DEC_VALID_COMMA_ONLY = "TRUE"; - parameter [23:0] DMONITOR_CFG = 24'h000A00; - parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; - parameter [5:0] ES_CONTROL = 6'b000000; - parameter ES_ERRDET_EN = "FALSE"; - parameter ES_EYE_SCAN_EN = "TRUE"; - parameter [11:0] ES_HORZ_OFFSET = 12'h000; - parameter [9:0] ES_PMA_CFG = 10'b0000000000; - parameter [4:0] ES_PRESCALE = 5'b00000; - parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000; - parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000; - parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000; - parameter [8:0] ES_VERT_OFFSET = 9'b000000000; - parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; - parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; - parameter FTS_LANE_DESKEW_EN = "FALSE"; - parameter [2:0] GEARBOX_MODE = 3'b000; - parameter [0:0] IS_CLKRSVD0_INVERTED = 1'b0; - parameter [0:0] IS_CLKRSVD1_INVERTED = 1'b0; - parameter [0:0] IS_CPLLLOCKDETCLK_INVERTED = 1'b0; - parameter [0:0] IS_DMONITORCLK_INVERTED = 1'b0; - parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; - parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0; - parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0; - parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0; - parameter [0:0] IS_SIGVALIDCLK_INVERTED = 1'b0; - parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0; - parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0; - parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0; - parameter [0:0] LOOPBACK_CFG = 1'b0; - parameter [1:0] OUTREFCLK_SEL_INV = 2'b11; - parameter PCS_PCIE_EN = "FALSE"; - parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000; - parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; - parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; - parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; - parameter [31:0] PMA_RSV = 32'b00000000000000000000000010000000; - parameter [31:0] PMA_RSV2 = 32'b00011100000000000000000000001010; - parameter [1:0] PMA_RSV3 = 2'b00; - parameter [14:0] PMA_RSV4 = 15'b000000000001000; - parameter [3:0] PMA_RSV5 = 4'b0000; - parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0; - parameter [4:0] RXBUFRESET_TIME = 5'b00001; - parameter RXBUF_ADDR_MODE = "FULL"; - parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; - parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; - parameter RXBUF_EN = "TRUE"; - parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; - parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; - parameter RXBUF_RESET_ON_EIDLE = "FALSE"; - parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; - parameter integer RXBUF_THRESH_OVFLW = 61; - parameter RXBUF_THRESH_OVRD = "FALSE"; - parameter integer RXBUF_THRESH_UNDFLW = 4; - parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; - parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; - parameter [82:0] RXCDR_CFG = 83'h0002007FE2000C208001A; - parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; - parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; - parameter [5:0] RXCDR_LOCK_CFG = 6'b001001; - parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; - parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; - parameter [15:0] RXDLY_CFG = 16'h001F; - parameter [8:0] RXDLY_LCFG = 9'h030; - parameter [15:0] RXDLY_TAP_CFG = 16'h0000; - parameter RXGEARBOX_EN = "FALSE"; - parameter [4:0] RXISCANRESET_TIME = 5'b00001; - parameter [13:0] RXLPM_HF_CFG = 14'b00001000000000; - parameter [17:0] RXLPM_LF_CFG = 18'b001001000000000000; - parameter [6:0] RXOOB_CFG = 7'b0000110; - parameter RXOOB_CLK_CFG = "PMA"; - parameter [4:0] RXOSCALRESET_TIME = 5'b00011; - parameter [4:0] RXOSCALRESET_TIMEOUT = 5'b00000; - parameter integer RXOUT_DIV = 2; - parameter [4:0] RXPCSRESET_TIME = 5'b00001; - parameter [23:0] RXPHDLY_CFG = 24'h084020; - parameter [23:0] RXPH_CFG = 24'hC00002; - parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; - parameter [1:0] RXPI_CFG0 = 2'b00; - parameter [1:0] RXPI_CFG1 = 2'b00; - parameter [1:0] RXPI_CFG2 = 2'b00; - parameter [1:0] RXPI_CFG3 = 2'b00; - parameter [0:0] RXPI_CFG4 = 1'b0; - parameter [0:0] RXPI_CFG5 = 1'b0; - parameter [2:0] RXPI_CFG6 = 3'b100; - parameter [4:0] RXPMARESET_TIME = 5'b00011; - parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; - parameter integer RXSLIDE_AUTO_WAIT = 7; - parameter RXSLIDE_MODE = "OFF"; - parameter [0:0] RXSYNC_MULTILANE = 1'b0; - parameter [0:0] RXSYNC_OVRD = 1'b0; - parameter [0:0] RXSYNC_SKIP_DA = 1'b0; - parameter [23:0] RX_BIAS_CFG = 24'b000011000000000000010000; - parameter [5:0] RX_BUFFER_CFG = 6'b000000; - parameter integer RX_CLK25_DIV = 7; - parameter [0:0] RX_CLKMUX_PD = 1'b1; - parameter [1:0] RX_CM_SEL = 2'b11; - parameter [3:0] RX_CM_TRIM = 4'b0100; - parameter integer RX_DATA_WIDTH = 20; - parameter [5:0] RX_DDI_SEL = 6'b000000; - parameter [13:0] RX_DEBUG_CFG = 14'b00000000000000; - parameter RX_DEFER_RESET_BUF_EN = "TRUE"; - parameter [3:0] RX_DFELPM_CFG0 = 4'b0110; - parameter [0:0] RX_DFELPM_CFG1 = 1'b0; - parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1; - parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00; - parameter [2:0] RX_DFE_AGC_CFG1 = 3'b010; - parameter [3:0] RX_DFE_AGC_CFG2 = 4'b0000; - parameter [0:0] RX_DFE_AGC_OVRDEN = 1'b1; - parameter [22:0] RX_DFE_GAIN_CFG = 23'h0020C0; - parameter [11:0] RX_DFE_H2_CFG = 12'b000000000000; - parameter [11:0] RX_DFE_H3_CFG = 12'b000001000000; - parameter [10:0] RX_DFE_H4_CFG = 11'b00011100000; - parameter [10:0] RX_DFE_H5_CFG = 11'b00011100000; - parameter [10:0] RX_DFE_H6_CFG = 11'b00000100000; - parameter [10:0] RX_DFE_H7_CFG = 11'b00000100000; - parameter [32:0] RX_DFE_KL_CFG = 33'b000000000000000000000001100010000; - parameter [1:0] RX_DFE_KL_LPM_KH_CFG0 = 2'b01; - parameter [2:0] RX_DFE_KL_LPM_KH_CFG1 = 3'b010; - parameter [3:0] RX_DFE_KL_LPM_KH_CFG2 = 4'b0010; - parameter [0:0] RX_DFE_KL_LPM_KH_OVRDEN = 1'b1; - parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b10; - parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010; - parameter [3:0] RX_DFE_KL_LPM_KL_CFG2 = 4'b0010; - parameter [0:0] RX_DFE_KL_LPM_KL_OVRDEN = 1'b1; - parameter [15:0] RX_DFE_LPM_CFG = 16'h0080; - parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; - parameter [53:0] RX_DFE_ST_CFG = 54'h00E100000C003F; - parameter [16:0] RX_DFE_UT_CFG = 17'b00011100000000000; - parameter [16:0] RX_DFE_VP_CFG = 17'b00011101010100011; - parameter RX_DISPERR_SEQ_MATCH = "TRUE"; - parameter integer RX_INT_DATAWIDTH = 0; - parameter [12:0] RX_OS_CFG = 13'b0000010000000; - parameter integer RX_SIG_VALID_DLY = 10; - parameter RX_XCLK_SEL = "RXREC"; - parameter integer SAS_MAX_COM = 64; - parameter integer SAS_MIN_COM = 36; - parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; - parameter [2:0] SATA_BURST_VAL = 3'b100; - parameter SATA_CPLL_CFG = "VCO_3000MHZ"; - parameter [2:0] SATA_EIDLE_VAL = 3'b100; - parameter integer SATA_MAX_BURST = 8; - parameter integer SATA_MAX_INIT = 21; - parameter integer SATA_MAX_WAKE = 7; - parameter integer SATA_MIN_BURST = 4; - parameter integer SATA_MIN_INIT = 12; - parameter integer SATA_MIN_WAKE = 4; - parameter SHOW_REALIGN_COMMA = "TRUE"; - parameter [2:0] SIM_CPLLREFCLK_SEL = 3'b001; - parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X"; - parameter SIM_VERSION = "1.1"; - parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; - parameter [2:0] TERM_RCAL_OVRD = 3'b000; - parameter [7:0] TRANS_TIME_RATE = 8'h0E; - parameter [31:0] TST_RSV = 32'h00000000; - parameter TXBUF_EN = "TRUE"; - parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; - parameter [15:0] TXDLY_CFG = 16'h001F; - parameter [8:0] TXDLY_LCFG = 9'h030; - parameter [15:0] TXDLY_TAP_CFG = 16'h0000; - parameter TXGEARBOX_EN = "FALSE"; - parameter [0:0] TXOOB_CFG = 1'b0; - parameter integer TXOUT_DIV = 2; - parameter [4:0] TXPCSRESET_TIME = 5'b00001; - parameter [23:0] TXPHDLY_CFG = 24'h084020; - parameter [15:0] TXPH_CFG = 16'h0780; - parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; - parameter [1:0] TXPI_CFG0 = 2'b00; - parameter [1:0] TXPI_CFG1 = 2'b00; - parameter [1:0] TXPI_CFG2 = 2'b00; - parameter [0:0] TXPI_CFG3 = 1'b0; - parameter [0:0] TXPI_CFG4 = 1'b0; - parameter [2:0] TXPI_CFG5 = 3'b100; - parameter [0:0] TXPI_GREY_SEL = 1'b0; - parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; - parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; - parameter [7:0] TXPI_PPM_CFG = 8'b00000000; - parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; - parameter [4:0] TXPMARESET_TIME = 5'b00001; - parameter [0:0] TXSYNC_MULTILANE = 1'b0; - parameter [0:0] TXSYNC_OVRD = 1'b0; - parameter [0:0] TXSYNC_SKIP_DA = 1'b0; - parameter integer TX_CLK25_DIV = 7; - parameter [0:0] TX_CLKMUX_PD = 1'b1; - parameter integer TX_DATA_WIDTH = 20; - parameter [5:0] TX_DEEMPH0 = 6'b000000; - parameter [5:0] TX_DEEMPH1 = 6'b000000; - parameter TX_DRIVE_MODE = "DIRECT"; - parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; - parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; - parameter integer TX_INT_DATAWIDTH = 0; - parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; - parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; - parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; - parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; - parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; - parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; - parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; - parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; - parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; - parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; - parameter [0:0] TX_QPI_STATUS_EN = 1'b0; - parameter [13:0] TX_RXDETECT_CFG = 14'h1832; - parameter [16:0] TX_RXDETECT_PRECHARGE_TIME = 17'h00000; - parameter [2:0] TX_RXDETECT_REF = 3'b100; - parameter TX_XCLK_SEL = "TXUSR"; - parameter [0:0] UCODEER_CLR = 1'b0; - parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; - output CPLLFBCLKLOST; - output CPLLLOCK; - output CPLLREFCLKLOST; - output DRPRDY; - output EYESCANDATAERROR; - output GTHTXN; - output GTHTXP; - output GTREFCLKMONITOR; - output PHYSTATUS; - output RSOSINTDONE; - output RXBYTEISALIGNED; - output RXBYTEREALIGN; - output RXCDRLOCK; - output RXCHANBONDSEQ; - output RXCHANISALIGNED; - output RXCHANREALIGN; - output RXCOMINITDET; - output RXCOMMADET; - output RXCOMSASDET; - output RXCOMWAKEDET; - output RXDFESLIDETAPSTARTED; - output RXDFESLIDETAPSTROBEDONE; - output RXDFESLIDETAPSTROBESTARTED; - output RXDFESTADAPTDONE; - output RXDLYSRESETDONE; - output RXELECIDLE; - output RXOSINTSTARTED; - output RXOSINTSTROBEDONE; - output RXOSINTSTROBESTARTED; - output RXOUTCLK; - output RXOUTCLKFABRIC; - output RXOUTCLKPCS; - output RXPHALIGNDONE; - output RXPMARESETDONE; - output RXPRBSERR; - output RXQPISENN; - output RXQPISENP; - output RXRATEDONE; - output RXRESETDONE; - output RXSYNCDONE; - output RXSYNCOUT; - output RXVALID; - output TXCOMFINISH; - output TXDLYSRESETDONE; - output TXGEARBOXREADY; - output TXOUTCLK; - output TXOUTCLKFABRIC; - output TXOUTCLKPCS; - output TXPHALIGNDONE; - output TXPHINITDONE; - output TXPMARESETDONE; - output TXQPISENN; - output TXQPISENP; - output TXRATEDONE; - output TXRESETDONE; - output TXSYNCDONE; - output TXSYNCOUT; - output [14:0] DMONITOROUT; - output [15:0] DRPDO; - output [15:0] PCSRSVDOUT; - output [1:0] RXCLKCORCNT; - output [1:0] RXDATAVALID; - output [1:0] RXHEADERVALID; - output [1:0] RXSTARTOFSEQ; - output [1:0] TXBUFSTATUS; - output [2:0] RXBUFSTATUS; - output [2:0] RXSTATUS; - output [4:0] RXCHBONDO; - output [4:0] RXPHMONITOR; - output [4:0] RXPHSLIPMONITOR; - output [5:0] RXHEADER; - output [63:0] RXDATA; - output [6:0] RXMONITOROUT; - output [7:0] RXCHARISCOMMA; - output [7:0] RXCHARISK; - output [7:0] RXDISPERR; - output [7:0] RXNOTINTABLE; - input CFGRESET; - (* invertible_pin = "IS_CLKRSVD0_INVERTED" *) - input CLKRSVD0; - (* invertible_pin = "IS_CLKRSVD1_INVERTED" *) - input CLKRSVD1; - (* invertible_pin = "IS_CPLLLOCKDETCLK_INVERTED" *) - input CPLLLOCKDETCLK; - input CPLLLOCKEN; - input CPLLPD; - input CPLLRESET; - input DMONFIFORESET; - (* invertible_pin = "IS_DMONITORCLK_INVERTED" *) - input DMONITORCLK; - (* invertible_pin = "IS_DRPCLK_INVERTED" *) - input DRPCLK; - input DRPEN; - input DRPWE; - input EYESCANMODE; - input EYESCANRESET; - input EYESCANTRIGGER; - (* invertible_pin = "IS_GTGREFCLK_INVERTED" *) - input GTGREFCLK; - input GTHRXN; - input GTHRXP; - input GTNORTHREFCLK0; - input GTNORTHREFCLK1; - input GTREFCLK0; - input GTREFCLK1; - input GTRESETSEL; - input GTRXRESET; - input GTSOUTHREFCLK0; - input GTSOUTHREFCLK1; - input GTTXRESET; - input QPLLCLK; - input QPLLREFCLK; - input RESETOVRD; - input RX8B10BEN; - input RXBUFRESET; - input RXCDRFREQRESET; - input RXCDRHOLD; - input RXCDROVRDEN; - input RXCDRRESET; - input RXCDRRESETRSV; - input RXCHBONDEN; - input RXCHBONDMASTER; - input RXCHBONDSLAVE; - input RXCOMMADETEN; - input RXDDIEN; - input RXDFEAGCHOLD; - input RXDFEAGCOVRDEN; - input RXDFECM1EN; - input RXDFELFHOLD; - input RXDFELFOVRDEN; - input RXDFELPMRESET; - input RXDFESLIDETAPADAPTEN; - input RXDFESLIDETAPHOLD; - input RXDFESLIDETAPINITOVRDEN; - input RXDFESLIDETAPONLYADAPTEN; - input RXDFESLIDETAPOVRDEN; - input RXDFESLIDETAPSTROBE; - input RXDFETAP2HOLD; - input RXDFETAP2OVRDEN; - input RXDFETAP3HOLD; - input RXDFETAP3OVRDEN; - input RXDFETAP4HOLD; - input RXDFETAP4OVRDEN; - input RXDFETAP5HOLD; - input RXDFETAP5OVRDEN; - input RXDFETAP6HOLD; - input RXDFETAP6OVRDEN; - input RXDFETAP7HOLD; - input RXDFETAP7OVRDEN; - input RXDFEUTHOLD; - input RXDFEUTOVRDEN; - input RXDFEVPHOLD; - input RXDFEVPOVRDEN; - input RXDFEVSEN; - input RXDFEXYDEN; - input RXDLYBYPASS; - input RXDLYEN; - input RXDLYOVRDEN; - input RXDLYSRESET; - input RXGEARBOXSLIP; - input RXLPMEN; - input RXLPMHFHOLD; - input RXLPMHFOVRDEN; - input RXLPMLFHOLD; - input RXLPMLFKLOVRDEN; - input RXMCOMMAALIGNEN; - input RXOOBRESET; - input RXOSCALRESET; - input RXOSHOLD; - input RXOSINTEN; - input RXOSINTHOLD; - input RXOSINTNTRLEN; - input RXOSINTOVRDEN; - input RXOSINTSTROBE; - input RXOSINTTESTOVRDEN; - input RXOSOVRDEN; - input RXPCOMMAALIGNEN; - input RXPCSRESET; - input RXPHALIGN; - input RXPHALIGNEN; - input RXPHDLYPD; - input RXPHDLYRESET; - input RXPHOVRDEN; - input RXPMARESET; - input RXPOLARITY; - input RXPRBSCNTRESET; - input RXQPIEN; - input RXRATEMODE; - input RXSLIDE; - input RXSYNCALLIN; - input RXSYNCIN; - input RXSYNCMODE; - input RXUSERRDY; - (* invertible_pin = "IS_RXUSRCLK2_INVERTED" *) - input RXUSRCLK2; - (* invertible_pin = "IS_RXUSRCLK_INVERTED" *) - input RXUSRCLK; - input SETERRSTATUS; - (* invertible_pin = "IS_SIGVALIDCLK_INVERTED" *) - input SIGVALIDCLK; - input TX8B10BEN; - input TXCOMINIT; - input TXCOMSAS; - input TXCOMWAKE; - input TXDEEMPH; - input TXDETECTRX; - input TXDIFFPD; - input TXDLYBYPASS; - input TXDLYEN; - input TXDLYHOLD; - input TXDLYOVRDEN; - input TXDLYSRESET; - input TXDLYUPDOWN; - input TXELECIDLE; - input TXINHIBIT; - input TXPCSRESET; - input TXPDELECIDLEMODE; - input TXPHALIGN; - input TXPHALIGNEN; - input TXPHDLYPD; - input TXPHDLYRESET; - (* invertible_pin = "IS_TXPHDLYTSTCLK_INVERTED" *) - input TXPHDLYTSTCLK; - input TXPHINIT; - input TXPHOVRDEN; - input TXPIPPMEN; - input TXPIPPMOVRDEN; - input TXPIPPMPD; - input TXPIPPMSEL; - input TXPISOPD; - input TXPMARESET; - input TXPOLARITY; - input TXPOSTCURSORINV; - input TXPRBSFORCEERR; - input TXPRECURSORINV; - input TXQPIBIASEN; - input TXQPISTRONGPDOWN; - input TXQPIWEAKPUP; - input TXRATEMODE; - input TXSTARTSEQ; - input TXSWING; - input TXSYNCALLIN; - input TXSYNCIN; - input TXSYNCMODE; - input TXUSERRDY; - (* invertible_pin = "IS_TXUSRCLK2_INVERTED" *) - input TXUSRCLK2; - (* invertible_pin = "IS_TXUSRCLK_INVERTED" *) - input TXUSRCLK; - input [13:0] RXADAPTSELTEST; - input [15:0] DRPDI; - input [15:0] GTRSVD; - input [15:0] PCSRSVDIN; - input [19:0] TSTIN; - input [1:0] RXELECIDLEMODE; - input [1:0] RXMONITORSEL; - input [1:0] RXPD; - input [1:0] RXSYSCLKSEL; - input [1:0] TXPD; - input [1:0] TXSYSCLKSEL; - input [2:0] CPLLREFCLKSEL; - input [2:0] LOOPBACK; - input [2:0] RXCHBONDLEVEL; - input [2:0] RXOUTCLKSEL; - input [2:0] RXPRBSSEL; - input [2:0] RXRATE; - input [2:0] TXBUFDIFFCTRL; - input [2:0] TXHEADER; - input [2:0] TXMARGIN; - input [2:0] TXOUTCLKSEL; - input [2:0] TXPRBSSEL; - input [2:0] TXRATE; - input [3:0] RXOSINTCFG; - input [3:0] RXOSINTID0; - input [3:0] TXDIFFCTRL; - input [4:0] PCSRSVDIN2; - input [4:0] PMARSVDIN; - input [4:0] RXCHBONDI; - input [4:0] RXDFEAGCTRL; - input [4:0] RXDFESLIDETAP; - input [4:0] TXPIPPMSTEPSIZE; - input [4:0] TXPOSTCURSOR; - input [4:0] TXPRECURSOR; - input [5:0] RXDFESLIDETAPID; - input [63:0] TXDATA; - input [6:0] TXMAINCURSOR; - input [6:0] TXSEQUENCE; - input [7:0] TX8B10BBYPASS; - input [7:0] TXCHARDISPMODE; - input [7:0] TXCHARDISPVAL; - input [7:0] TXCHARISK; - input [8:0] DRPADDR; -endmodule - -module GTHE2_COMMON (...); - parameter [63:0] BIAS_CFG = 64'h0000040000001000; - parameter [31:0] COMMON_CFG = 32'h0000001C; - parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; - parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0; - parameter [0:0] IS_QPLLLOCKDETCLK_INVERTED = 1'b0; - parameter [26:0] QPLL_CFG = 27'h0480181; - parameter [3:0] QPLL_CLKOUT_CFG = 4'b0000; - parameter [5:0] QPLL_COARSE_FREQ_OVRD = 6'b010000; - parameter [0:0] QPLL_COARSE_FREQ_OVRD_EN = 1'b0; - parameter [9:0] QPLL_CP = 10'b0000011111; - parameter [0:0] QPLL_CP_MONITOR_EN = 1'b0; - parameter [0:0] QPLL_DMONITOR_SEL = 1'b0; - parameter [9:0] QPLL_FBDIV = 10'b0000000000; - parameter [0:0] QPLL_FBDIV_MONITOR_EN = 1'b0; - parameter [0:0] QPLL_FBDIV_RATIO = 1'b0; - parameter [23:0] QPLL_INIT_CFG = 24'h000006; - parameter [15:0] QPLL_LOCK_CFG = 16'h01E8; - parameter [3:0] QPLL_LPF = 4'b1111; - parameter integer QPLL_REFCLK_DIV = 2; - parameter [0:0] QPLL_RP_COMP = 1'b0; - parameter [1:0] QPLL_VTRL_RESET = 2'b00; - parameter [1:0] RCAL_CFG = 2'b00; - parameter [15:0] RSVD_ATTR0 = 16'h0000; - parameter [15:0] RSVD_ATTR1 = 16'h0000; - parameter [2:0] SIM_QPLLREFCLK_SEL = 3'b001; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter SIM_VERSION = "1.1"; - output DRPRDY; - output QPLLFBCLKLOST; - output QPLLLOCK; - output QPLLOUTCLK; - output QPLLOUTREFCLK; - output QPLLREFCLKLOST; - output REFCLKOUTMONITOR; - output [15:0] DRPDO; - output [15:0] PMARSVDOUT; - output [7:0] QPLLDMONITOR; - input BGBYPASSB; - input BGMONITORENB; - input BGPDB; - input BGRCALOVRDENB; - (* invertible_pin = "IS_DRPCLK_INVERTED" *) - input DRPCLK; - input DRPEN; - input DRPWE; - (* invertible_pin = "IS_GTGREFCLK_INVERTED" *) - input GTGREFCLK; - input GTNORTHREFCLK0; - input GTNORTHREFCLK1; - input GTREFCLK0; - input GTREFCLK1; - input GTSOUTHREFCLK0; - input GTSOUTHREFCLK1; - (* invertible_pin = "IS_QPLLLOCKDETCLK_INVERTED" *) - input QPLLLOCKDETCLK; - input QPLLLOCKEN; - input QPLLOUTRESET; - input QPLLPD; - input QPLLRESET; - input RCALENB; - input [15:0] DRPDI; - input [15:0] QPLLRSVD1; - input [2:0] QPLLREFCLKSEL; - input [4:0] BGRCALOVRD; - input [4:0] QPLLRSVD2; - input [7:0] DRPADDR; - input [7:0] PMARSVD; -endmodule - -module GTPE2_CHANNEL (...); - parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; - parameter [0:0] ACJTAG_MODE = 1'b0; - parameter [0:0] ACJTAG_RESET = 1'b0; - parameter [19:0] ADAPT_CFG0 = 20'b00000000000000000000; - parameter ALIGN_COMMA_DOUBLE = "FALSE"; - parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; - parameter integer ALIGN_COMMA_WORD = 1; - parameter ALIGN_MCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; - parameter ALIGN_PCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; - parameter CBCC_DATA_SOURCE_SEL = "DECODED"; - parameter [42:0] CFOK_CFG = 43'b1001001000000000000000001000000111010000000; - parameter [6:0] CFOK_CFG2 = 7'b0100000; - parameter [6:0] CFOK_CFG3 = 7'b0100000; - parameter [0:0] CFOK_CFG4 = 1'b0; - parameter [1:0] CFOK_CFG5 = 2'b00; - parameter [3:0] CFOK_CFG6 = 4'b0000; - parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; - parameter integer CHAN_BOND_MAX_SKEW = 7; - parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; - parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; - parameter CHAN_BOND_SEQ_2_USE = "FALSE"; - parameter integer CHAN_BOND_SEQ_LEN = 1; - parameter [0:0] CLK_COMMON_SWING = 1'b0; - parameter CLK_CORRECT_USE = "TRUE"; - parameter CLK_COR_KEEP_IDLE = "FALSE"; - parameter integer CLK_COR_MAX_LAT = 20; - parameter integer CLK_COR_MIN_LAT = 18; - parameter CLK_COR_PRECEDENCE = "TRUE"; - parameter integer CLK_COR_REPEAT_WAIT = 0; - parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; - parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; - parameter CLK_COR_SEQ_2_USE = "FALSE"; - parameter integer CLK_COR_SEQ_LEN = 1; - parameter DEC_MCOMMA_DETECT = "TRUE"; - parameter DEC_PCOMMA_DETECT = "TRUE"; - parameter DEC_VALID_COMMA_ONLY = "TRUE"; - parameter [23:0] DMONITOR_CFG = 24'h000A00; - parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; - parameter [5:0] ES_CONTROL = 6'b000000; - parameter ES_ERRDET_EN = "FALSE"; - parameter ES_EYE_SCAN_EN = "FALSE"; - parameter [11:0] ES_HORZ_OFFSET = 12'h010; - parameter [9:0] ES_PMA_CFG = 10'b0000000000; - parameter [4:0] ES_PRESCALE = 5'b00000; - parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000; - parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000; - parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000; - parameter [8:0] ES_VERT_OFFSET = 9'b000000000; - parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; - parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; - parameter FTS_LANE_DESKEW_EN = "FALSE"; - parameter [2:0] GEARBOX_MODE = 3'b000; - parameter [0:0] IS_CLKRSVD0_INVERTED = 1'b0; - parameter [0:0] IS_CLKRSVD1_INVERTED = 1'b0; - parameter [0:0] IS_DMONITORCLK_INVERTED = 1'b0; - parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; - parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0; - parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0; - parameter [0:0] IS_SIGVALIDCLK_INVERTED = 1'b0; - parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0; - parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0; - parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0; - parameter [0:0] LOOPBACK_CFG = 1'b0; - parameter [1:0] OUTREFCLK_SEL_INV = 2'b11; - parameter PCS_PCIE_EN = "FALSE"; - parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000; - parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; - parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; - parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; - parameter [0:0] PMA_LOOPBACK_CFG = 1'b0; - parameter [31:0] PMA_RSV = 32'h00000333; - parameter [31:0] PMA_RSV2 = 32'h00002050; - parameter [1:0] PMA_RSV3 = 2'b00; - parameter [3:0] PMA_RSV4 = 4'b0000; - parameter [0:0] PMA_RSV5 = 1'b0; - parameter [0:0] PMA_RSV6 = 1'b0; - parameter [0:0] PMA_RSV7 = 1'b0; - parameter [4:0] RXBUFRESET_TIME = 5'b00001; - parameter RXBUF_ADDR_MODE = "FULL"; - parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; - parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; - parameter RXBUF_EN = "TRUE"; - parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; - parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; - parameter RXBUF_RESET_ON_EIDLE = "FALSE"; - parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; - parameter integer RXBUF_THRESH_OVFLW = 61; - parameter RXBUF_THRESH_OVRD = "FALSE"; - parameter integer RXBUF_THRESH_UNDFLW = 4; - parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; - parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; - parameter [82:0] RXCDR_CFG = 83'h0000107FE406001041010; - parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; - parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; - parameter [5:0] RXCDR_LOCK_CFG = 6'b001001; - parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; - parameter [15:0] RXDLY_CFG = 16'h0010; - parameter [8:0] RXDLY_LCFG = 9'h020; - parameter [15:0] RXDLY_TAP_CFG = 16'h0000; - parameter RXGEARBOX_EN = "FALSE"; - parameter [4:0] RXISCANRESET_TIME = 5'b00001; - parameter [6:0] RXLPMRESET_TIME = 7'b0001111; - parameter [0:0] RXLPM_BIAS_STARTUP_DISABLE = 1'b0; - parameter [3:0] RXLPM_CFG = 4'b0110; - parameter [0:0] RXLPM_CFG1 = 1'b0; - parameter [0:0] RXLPM_CM_CFG = 1'b0; - parameter [8:0] RXLPM_GC_CFG = 9'b111100010; - parameter [2:0] RXLPM_GC_CFG2 = 3'b001; - parameter [13:0] RXLPM_HF_CFG = 14'b00001111110000; - parameter [4:0] RXLPM_HF_CFG2 = 5'b01010; - parameter [3:0] RXLPM_HF_CFG3 = 4'b0000; - parameter [0:0] RXLPM_HOLD_DURING_EIDLE = 1'b0; - parameter [0:0] RXLPM_INCM_CFG = 1'b0; - parameter [0:0] RXLPM_IPCM_CFG = 1'b0; - parameter [17:0] RXLPM_LF_CFG = 18'b000000001111110000; - parameter [4:0] RXLPM_LF_CFG2 = 5'b01010; - parameter [2:0] RXLPM_OSINT_CFG = 3'b100; - parameter [6:0] RXOOB_CFG = 7'b0000110; - parameter RXOOB_CLK_CFG = "PMA"; - parameter [4:0] RXOSCALRESET_TIME = 5'b00011; - parameter [4:0] RXOSCALRESET_TIMEOUT = 5'b00000; - parameter integer RXOUT_DIV = 2; - parameter [4:0] RXPCSRESET_TIME = 5'b00001; - parameter [23:0] RXPHDLY_CFG = 24'h084000; - parameter [23:0] RXPH_CFG = 24'hC00002; - parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; - parameter [2:0] RXPI_CFG0 = 3'b000; - parameter [0:0] RXPI_CFG1 = 1'b0; - parameter [0:0] RXPI_CFG2 = 1'b0; - parameter [4:0] RXPMARESET_TIME = 5'b00011; - parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; - parameter integer RXSLIDE_AUTO_WAIT = 7; - parameter RXSLIDE_MODE = "OFF"; - parameter [0:0] RXSYNC_MULTILANE = 1'b0; - parameter [0:0] RXSYNC_OVRD = 1'b0; - parameter [0:0] RXSYNC_SKIP_DA = 1'b0; - parameter [15:0] RX_BIAS_CFG = 16'b0000111100110011; - parameter [5:0] RX_BUFFER_CFG = 6'b000000; - parameter integer RX_CLK25_DIV = 7; - parameter [0:0] RX_CLKMUX_EN = 1'b1; - parameter [1:0] RX_CM_SEL = 2'b11; - parameter [3:0] RX_CM_TRIM = 4'b0100; - parameter integer RX_DATA_WIDTH = 20; - parameter [5:0] RX_DDI_SEL = 6'b000000; - parameter [13:0] RX_DEBUG_CFG = 14'b00000000000000; - parameter RX_DEFER_RESET_BUF_EN = "TRUE"; - parameter RX_DISPERR_SEQ_MATCH = "TRUE"; - parameter [12:0] RX_OS_CFG = 13'b0001111110000; - parameter integer RX_SIG_VALID_DLY = 10; - parameter RX_XCLK_SEL = "RXREC"; - parameter integer SAS_MAX_COM = 64; - parameter integer SAS_MIN_COM = 36; - parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; - parameter [2:0] SATA_BURST_VAL = 3'b100; - parameter [2:0] SATA_EIDLE_VAL = 3'b100; - parameter integer SATA_MAX_BURST = 8; - parameter integer SATA_MAX_INIT = 21; - parameter integer SATA_MAX_WAKE = 7; - parameter integer SATA_MIN_BURST = 4; - parameter integer SATA_MIN_INIT = 12; - parameter integer SATA_MIN_WAKE = 4; - parameter SATA_PLL_CFG = "VCO_3000MHZ"; - parameter SHOW_REALIGN_COMMA = "TRUE"; - parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X"; - parameter SIM_VERSION = "1.0"; - parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; - parameter [2:0] TERM_RCAL_OVRD = 3'b000; - parameter [7:0] TRANS_TIME_RATE = 8'h0E; - parameter [31:0] TST_RSV = 32'h00000000; - parameter TXBUF_EN = "TRUE"; - parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; - parameter [15:0] TXDLY_CFG = 16'h0010; - parameter [8:0] TXDLY_LCFG = 9'h020; - parameter [15:0] TXDLY_TAP_CFG = 16'h0000; - parameter TXGEARBOX_EN = "FALSE"; - parameter [0:0] TXOOB_CFG = 1'b0; - parameter integer TXOUT_DIV = 2; - parameter [4:0] TXPCSRESET_TIME = 5'b00001; - parameter [23:0] TXPHDLY_CFG = 24'h084000; - parameter [15:0] TXPH_CFG = 16'h0400; - parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; - parameter [1:0] TXPI_CFG0 = 2'b00; - parameter [1:0] TXPI_CFG1 = 2'b00; - parameter [1:0] TXPI_CFG2 = 2'b00; - parameter [0:0] TXPI_CFG3 = 1'b0; - parameter [0:0] TXPI_CFG4 = 1'b0; - parameter [2:0] TXPI_CFG5 = 3'b000; - parameter [0:0] TXPI_GREY_SEL = 1'b0; - parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; - parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; - parameter [7:0] TXPI_PPM_CFG = 8'b00000000; - parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; - parameter [4:0] TXPMARESET_TIME = 5'b00001; - parameter [0:0] TXSYNC_MULTILANE = 1'b0; - parameter [0:0] TXSYNC_OVRD = 1'b0; - parameter [0:0] TXSYNC_SKIP_DA = 1'b0; - parameter integer TX_CLK25_DIV = 7; - parameter [0:0] TX_CLKMUX_EN = 1'b1; - parameter integer TX_DATA_WIDTH = 20; - parameter [5:0] TX_DEEMPH0 = 6'b000000; - parameter [5:0] TX_DEEMPH1 = 6'b000000; - parameter TX_DRIVE_MODE = "DIRECT"; - parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; - parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; - parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; - parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; - parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; - parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; - parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; - parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; - parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; - parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; - parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; - parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; - parameter [0:0] TX_PREDRIVER_MODE = 1'b0; - parameter [13:0] TX_RXDETECT_CFG = 14'h1832; - parameter [2:0] TX_RXDETECT_REF = 3'b100; - parameter TX_XCLK_SEL = "TXUSR"; - parameter [0:0] UCODEER_CLR = 1'b0; - parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; - output DRPRDY; - output EYESCANDATAERROR; - output GTPTXN; - output GTPTXP; - output PHYSTATUS; - output PMARSVDOUT0; - output PMARSVDOUT1; - output RXBYTEISALIGNED; - output RXBYTEREALIGN; - output RXCDRLOCK; - output RXCHANBONDSEQ; - output RXCHANISALIGNED; - output RXCHANREALIGN; - output RXCOMINITDET; - output RXCOMMADET; - output RXCOMSASDET; - output RXCOMWAKEDET; - output RXDLYSRESETDONE; - output RXELECIDLE; - output RXHEADERVALID; - output RXOSINTDONE; - output RXOSINTSTARTED; - output RXOSINTSTROBEDONE; - output RXOSINTSTROBESTARTED; - output RXOUTCLK; - output RXOUTCLKFABRIC; - output RXOUTCLKPCS; - output RXPHALIGNDONE; - output RXPMARESETDONE; - output RXPRBSERR; - output RXRATEDONE; - output RXRESETDONE; - output RXSYNCDONE; - output RXSYNCOUT; - output RXVALID; - output TXCOMFINISH; - output TXDLYSRESETDONE; - output TXGEARBOXREADY; - output TXOUTCLK; - output TXOUTCLKFABRIC; - output TXOUTCLKPCS; - output TXPHALIGNDONE; - output TXPHINITDONE; - output TXPMARESETDONE; - output TXRATEDONE; - output TXRESETDONE; - output TXSYNCDONE; - output TXSYNCOUT; - output [14:0] DMONITOROUT; - output [15:0] DRPDO; - output [15:0] PCSRSVDOUT; - output [1:0] RXCLKCORCNT; - output [1:0] RXDATAVALID; - output [1:0] RXSTARTOFSEQ; - output [1:0] TXBUFSTATUS; - output [2:0] RXBUFSTATUS; - output [2:0] RXHEADER; - output [2:0] RXSTATUS; - output [31:0] RXDATA; - output [3:0] RXCHARISCOMMA; - output [3:0] RXCHARISK; - output [3:0] RXCHBONDO; - output [3:0] RXDISPERR; - output [3:0] RXNOTINTABLE; - output [4:0] RXPHMONITOR; - output [4:0] RXPHSLIPMONITOR; - input CFGRESET; - (* invertible_pin = "IS_CLKRSVD0_INVERTED" *) - input CLKRSVD0; - (* invertible_pin = "IS_CLKRSVD1_INVERTED" *) - input CLKRSVD1; - input DMONFIFORESET; - (* invertible_pin = "IS_DMONITORCLK_INVERTED" *) - input DMONITORCLK; - (* invertible_pin = "IS_DRPCLK_INVERTED" *) - input DRPCLK; - input DRPEN; - input DRPWE; - input EYESCANMODE; - input EYESCANRESET; - input EYESCANTRIGGER; - input GTPRXN; - input GTPRXP; - input GTRESETSEL; - input GTRXRESET; - input GTTXRESET; - input PLL0CLK; - input PLL0REFCLK; - input PLL1CLK; - input PLL1REFCLK; - input PMARSVDIN0; - input PMARSVDIN1; - input PMARSVDIN2; - input PMARSVDIN3; - input PMARSVDIN4; - input RESETOVRD; - input RX8B10BEN; - input RXBUFRESET; - input RXCDRFREQRESET; - input RXCDRHOLD; - input RXCDROVRDEN; - input RXCDRRESET; - input RXCDRRESETRSV; - input RXCHBONDEN; - input RXCHBONDMASTER; - input RXCHBONDSLAVE; - input RXCOMMADETEN; - input RXDDIEN; - input RXDFEXYDEN; - input RXDLYBYPASS; - input RXDLYEN; - input RXDLYOVRDEN; - input RXDLYSRESET; - input RXGEARBOXSLIP; - input RXLPMHFHOLD; - input RXLPMHFOVRDEN; - input RXLPMLFHOLD; - input RXLPMLFOVRDEN; - input RXLPMOSINTNTRLEN; - input RXLPMRESET; - input RXMCOMMAALIGNEN; - input RXOOBRESET; - input RXOSCALRESET; - input RXOSHOLD; - input RXOSINTEN; - input RXOSINTHOLD; - input RXOSINTNTRLEN; - input RXOSINTOVRDEN; - input RXOSINTPD; - input RXOSINTSTROBE; - input RXOSINTTESTOVRDEN; - input RXOSOVRDEN; - input RXPCOMMAALIGNEN; - input RXPCSRESET; - input RXPHALIGN; - input RXPHALIGNEN; - input RXPHDLYPD; - input RXPHDLYRESET; - input RXPHOVRDEN; - input RXPMARESET; - input RXPOLARITY; - input RXPRBSCNTRESET; - input RXRATEMODE; - input RXSLIDE; - input RXSYNCALLIN; - input RXSYNCIN; - input RXSYNCMODE; - input RXUSERRDY; - (* invertible_pin = "IS_RXUSRCLK2_INVERTED" *) - input RXUSRCLK2; - (* invertible_pin = "IS_RXUSRCLK_INVERTED" *) - input RXUSRCLK; - input SETERRSTATUS; - (* invertible_pin = "IS_SIGVALIDCLK_INVERTED" *) - input SIGVALIDCLK; - input TX8B10BEN; - input TXCOMINIT; - input TXCOMSAS; - input TXCOMWAKE; - input TXDEEMPH; - input TXDETECTRX; - input TXDIFFPD; - input TXDLYBYPASS; - input TXDLYEN; - input TXDLYHOLD; - input TXDLYOVRDEN; - input TXDLYSRESET; - input TXDLYUPDOWN; - input TXELECIDLE; - input TXINHIBIT; - input TXPCSRESET; - input TXPDELECIDLEMODE; - input TXPHALIGN; - input TXPHALIGNEN; - input TXPHDLYPD; - input TXPHDLYRESET; - (* invertible_pin = "IS_TXPHDLYTSTCLK_INVERTED" *) - input TXPHDLYTSTCLK; - input TXPHINIT; - input TXPHOVRDEN; - input TXPIPPMEN; - input TXPIPPMOVRDEN; - input TXPIPPMPD; - input TXPIPPMSEL; - input TXPISOPD; - input TXPMARESET; - input TXPOLARITY; - input TXPOSTCURSORINV; - input TXPRBSFORCEERR; - input TXPRECURSORINV; - input TXRATEMODE; - input TXSTARTSEQ; - input TXSWING; - input TXSYNCALLIN; - input TXSYNCIN; - input TXSYNCMODE; - input TXUSERRDY; - (* invertible_pin = "IS_TXUSRCLK2_INVERTED" *) - input TXUSRCLK2; - (* invertible_pin = "IS_TXUSRCLK_INVERTED" *) - input TXUSRCLK; - input [13:0] RXADAPTSELTEST; - input [15:0] DRPDI; - input [15:0] GTRSVD; - input [15:0] PCSRSVDIN; - input [19:0] TSTIN; - input [1:0] RXELECIDLEMODE; - input [1:0] RXPD; - input [1:0] RXSYSCLKSEL; - input [1:0] TXPD; - input [1:0] TXSYSCLKSEL; - input [2:0] LOOPBACK; - input [2:0] RXCHBONDLEVEL; - input [2:0] RXOUTCLKSEL; - input [2:0] RXPRBSSEL; - input [2:0] RXRATE; - input [2:0] TXBUFDIFFCTRL; - input [2:0] TXHEADER; - input [2:0] TXMARGIN; - input [2:0] TXOUTCLKSEL; - input [2:0] TXPRBSSEL; - input [2:0] TXRATE; - input [31:0] TXDATA; - input [3:0] RXCHBONDI; - input [3:0] RXOSINTCFG; - input [3:0] RXOSINTID0; - input [3:0] TX8B10BBYPASS; - input [3:0] TXCHARDISPMODE; - input [3:0] TXCHARDISPVAL; - input [3:0] TXCHARISK; - input [3:0] TXDIFFCTRL; - input [4:0] TXPIPPMSTEPSIZE; - input [4:0] TXPOSTCURSOR; - input [4:0] TXPRECURSOR; - input [6:0] TXMAINCURSOR; - input [6:0] TXSEQUENCE; - input [8:0] DRPADDR; -endmodule - -module GTPE2_COMMON (...); - parameter [63:0] BIAS_CFG = 64'h0000000000000000; - parameter [31:0] COMMON_CFG = 32'h00000000; - parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; - parameter [0:0] IS_GTGREFCLK0_INVERTED = 1'b0; - parameter [0:0] IS_GTGREFCLK1_INVERTED = 1'b0; - parameter [0:0] IS_PLL0LOCKDETCLK_INVERTED = 1'b0; - parameter [0:0] IS_PLL1LOCKDETCLK_INVERTED = 1'b0; - parameter [26:0] PLL0_CFG = 27'h01F03DC; - parameter [0:0] PLL0_DMON_CFG = 1'b0; - parameter integer PLL0_FBDIV = 4; - parameter integer PLL0_FBDIV_45 = 5; - parameter [23:0] PLL0_INIT_CFG = 24'h00001E; - parameter [8:0] PLL0_LOCK_CFG = 9'h1E8; - parameter integer PLL0_REFCLK_DIV = 1; - parameter [26:0] PLL1_CFG = 27'h01F03DC; - parameter [0:0] PLL1_DMON_CFG = 1'b0; - parameter integer PLL1_FBDIV = 4; - parameter integer PLL1_FBDIV_45 = 5; - parameter [23:0] PLL1_INIT_CFG = 24'h00001E; - parameter [8:0] PLL1_LOCK_CFG = 9'h1E8; - parameter integer PLL1_REFCLK_DIV = 1; - parameter [7:0] PLL_CLKOUT_CFG = 8'b00000000; - parameter [15:0] RSVD_ATTR0 = 16'h0000; - parameter [15:0] RSVD_ATTR1 = 16'h0000; - parameter [2:0] SIM_PLL0REFCLK_SEL = 3'b001; - parameter [2:0] SIM_PLL1REFCLK_SEL = 3'b001; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter SIM_VERSION = "1.0"; - output DRPRDY; - output PLL0FBCLKLOST; - output PLL0LOCK; - output PLL0OUTCLK; - output PLL0OUTREFCLK; - output PLL0REFCLKLOST; - output PLL1FBCLKLOST; - output PLL1LOCK; - output PLL1OUTCLK; - output PLL1OUTREFCLK; - output PLL1REFCLKLOST; - output REFCLKOUTMONITOR0; - output REFCLKOUTMONITOR1; - output [15:0] DRPDO; - output [15:0] PMARSVDOUT; - output [7:0] DMONITOROUT; - input BGBYPASSB; - input BGMONITORENB; - input BGPDB; - input BGRCALOVRDENB; - (* invertible_pin = "IS_DRPCLK_INVERTED" *) - input DRPCLK; - input DRPEN; - input DRPWE; - input GTEASTREFCLK0; - input GTEASTREFCLK1; - (* invertible_pin = "IS_GTGREFCLK0_INVERTED" *) - input GTGREFCLK0; - (* invertible_pin = "IS_GTGREFCLK1_INVERTED" *) - input GTGREFCLK1; - input GTREFCLK0; - input GTREFCLK1; - input GTWESTREFCLK0; - input GTWESTREFCLK1; - (* invertible_pin = "IS_PLL0LOCKDETCLK_INVERTED" *) - input PLL0LOCKDETCLK; - input PLL0LOCKEN; - input PLL0PD; - input PLL0RESET; - (* invertible_pin = "IS_PLL1LOCKDETCLK_INVERTED" *) - input PLL1LOCKDETCLK; - input PLL1LOCKEN; - input PLL1PD; - input PLL1RESET; - input RCALENB; - input [15:0] DRPDI; - input [15:0] PLLRSVD1; - input [2:0] PLL0REFCLKSEL; - input [2:0] PLL1REFCLKSEL; - input [4:0] BGRCALOVRD; - input [4:0] PLLRSVD2; - input [7:0] DRPADDR; - input [7:0] PMARSVD; -endmodule - -module GTXE2_CHANNEL (...); - parameter ALIGN_COMMA_DOUBLE = "FALSE"; - parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; - parameter integer ALIGN_COMMA_WORD = 1; - parameter ALIGN_MCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; - parameter ALIGN_PCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; - parameter CBCC_DATA_SOURCE_SEL = "DECODED"; - parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; - parameter integer CHAN_BOND_MAX_SKEW = 7; - parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; - parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; - parameter CHAN_BOND_SEQ_2_USE = "FALSE"; - parameter integer CHAN_BOND_SEQ_LEN = 1; - parameter CLK_CORRECT_USE = "TRUE"; - parameter CLK_COR_KEEP_IDLE = "FALSE"; - parameter integer CLK_COR_MAX_LAT = 20; - parameter integer CLK_COR_MIN_LAT = 18; - parameter CLK_COR_PRECEDENCE = "TRUE"; - parameter integer CLK_COR_REPEAT_WAIT = 0; - parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; - parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; - parameter CLK_COR_SEQ_2_USE = "FALSE"; - parameter integer CLK_COR_SEQ_LEN = 1; - parameter [23:0] CPLL_CFG = 24'hB007D8; - parameter integer CPLL_FBDIV = 4; - parameter integer CPLL_FBDIV_45 = 5; - parameter [23:0] CPLL_INIT_CFG = 24'h00001E; - parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; - parameter integer CPLL_REFCLK_DIV = 1; - parameter DEC_MCOMMA_DETECT = "TRUE"; - parameter DEC_PCOMMA_DETECT = "TRUE"; - parameter DEC_VALID_COMMA_ONLY = "TRUE"; - parameter [23:0] DMONITOR_CFG = 24'h000A00; - parameter [5:0] ES_CONTROL = 6'b000000; - parameter ES_ERRDET_EN = "FALSE"; - parameter ES_EYE_SCAN_EN = "FALSE"; - parameter [11:0] ES_HORZ_OFFSET = 12'h000; - parameter [9:0] ES_PMA_CFG = 10'b0000000000; - parameter [4:0] ES_PRESCALE = 5'b00000; - parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000; - parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000; - parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000; - parameter [8:0] ES_VERT_OFFSET = 9'b000000000; - parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; - parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; - parameter FTS_LANE_DESKEW_EN = "FALSE"; - parameter [2:0] GEARBOX_MODE = 3'b000; - parameter [0:0] IS_CPLLLOCKDETCLK_INVERTED = 1'b0; - parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; - parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0; - parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0; - parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0; - parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0; - parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0; - parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0; - parameter [1:0] OUTREFCLK_SEL_INV = 2'b11; - parameter PCS_PCIE_EN = "FALSE"; - parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000; - parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; - parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; - parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; - parameter [31:0] PMA_RSV = 32'h00000000; - parameter [15:0] PMA_RSV2 = 16'h2050; - parameter [1:0] PMA_RSV3 = 2'b00; - parameter [31:0] PMA_RSV4 = 32'h00000000; - parameter [4:0] RXBUFRESET_TIME = 5'b00001; - parameter RXBUF_ADDR_MODE = "FULL"; - parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; - parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; - parameter RXBUF_EN = "TRUE"; - parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; - parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; - parameter RXBUF_RESET_ON_EIDLE = "FALSE"; - parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; - parameter integer RXBUF_THRESH_OVFLW = 61; - parameter RXBUF_THRESH_OVRD = "FALSE"; - parameter integer RXBUF_THRESH_UNDFLW = 4; - parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; - parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; - parameter [71:0] RXCDR_CFG = 72'h0B000023FF20400020; - parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; - parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; - parameter [5:0] RXCDR_LOCK_CFG = 6'b010101; - parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; - parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; - parameter [15:0] RXDLY_CFG = 16'h001F; - parameter [8:0] RXDLY_LCFG = 9'h030; - parameter [15:0] RXDLY_TAP_CFG = 16'h0000; - parameter RXGEARBOX_EN = "FALSE"; - parameter [4:0] RXISCANRESET_TIME = 5'b00001; - parameter [13:0] RXLPM_HF_CFG = 14'b00000011110000; - parameter [13:0] RXLPM_LF_CFG = 14'b00000011110000; - parameter [6:0] RXOOB_CFG = 7'b0000110; - parameter integer RXOUT_DIV = 2; - parameter [4:0] RXPCSRESET_TIME = 5'b00001; - parameter [23:0] RXPHDLY_CFG = 24'h084020; - parameter [23:0] RXPH_CFG = 24'h000000; - parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; - parameter [4:0] RXPMARESET_TIME = 5'b00011; - parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; - parameter integer RXSLIDE_AUTO_WAIT = 7; - parameter RXSLIDE_MODE = "OFF"; - parameter [11:0] RX_BIAS_CFG = 12'b000000000000; - parameter [5:0] RX_BUFFER_CFG = 6'b000000; - parameter integer RX_CLK25_DIV = 7; - parameter [0:0] RX_CLKMUX_PD = 1'b1; - parameter [1:0] RX_CM_SEL = 2'b11; - parameter [2:0] RX_CM_TRIM = 3'b100; - parameter integer RX_DATA_WIDTH = 20; - parameter [5:0] RX_DDI_SEL = 6'b000000; - parameter [11:0] RX_DEBUG_CFG = 12'b000000000000; - parameter RX_DEFER_RESET_BUF_EN = "TRUE"; - parameter [22:0] RX_DFE_GAIN_CFG = 23'h180E0F; - parameter [11:0] RX_DFE_H2_CFG = 12'b000111100000; - parameter [11:0] RX_DFE_H3_CFG = 12'b000111100000; - parameter [10:0] RX_DFE_H4_CFG = 11'b00011110000; - parameter [10:0] RX_DFE_H5_CFG = 11'b00011110000; - parameter [12:0] RX_DFE_KL_CFG = 13'b0001111110000; - parameter [31:0] RX_DFE_KL_CFG2 = 32'h3008E56A; - parameter [15:0] RX_DFE_LPM_CFG = 16'h0904; - parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; - parameter [16:0] RX_DFE_UT_CFG = 17'b00111111000000000; - parameter [16:0] RX_DFE_VP_CFG = 17'b00011111100000000; - parameter [12:0] RX_DFE_XYD_CFG = 13'b0000000010000; - parameter RX_DISPERR_SEQ_MATCH = "TRUE"; - parameter integer RX_INT_DATAWIDTH = 0; - parameter [12:0] RX_OS_CFG = 13'b0001111110000; - parameter integer RX_SIG_VALID_DLY = 10; - parameter RX_XCLK_SEL = "RXREC"; - parameter integer SAS_MAX_COM = 64; - parameter integer SAS_MIN_COM = 36; - parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; - parameter [2:0] SATA_BURST_VAL = 3'b100; - parameter SATA_CPLL_CFG = "VCO_3000MHZ"; - parameter [2:0] SATA_EIDLE_VAL = 3'b100; - parameter integer SATA_MAX_BURST = 8; - parameter integer SATA_MAX_INIT = 21; - parameter integer SATA_MAX_WAKE = 7; - parameter integer SATA_MIN_BURST = 4; - parameter integer SATA_MIN_INIT = 12; - parameter integer SATA_MIN_WAKE = 4; - parameter SHOW_REALIGN_COMMA = "TRUE"; - parameter [2:0] SIM_CPLLREFCLK_SEL = 3'b001; - parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X"; - parameter SIM_VERSION = "4.0"; - parameter [4:0] TERM_RCAL_CFG = 5'b10000; - parameter [0:0] TERM_RCAL_OVRD = 1'b0; - parameter [7:0] TRANS_TIME_RATE = 8'h0E; - parameter [31:0] TST_RSV = 32'h00000000; - parameter TXBUF_EN = "TRUE"; - parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; - parameter [15:0] TXDLY_CFG = 16'h001F; - parameter [8:0] TXDLY_LCFG = 9'h030; - parameter [15:0] TXDLY_TAP_CFG = 16'h0000; - parameter TXGEARBOX_EN = "FALSE"; - parameter integer TXOUT_DIV = 2; - parameter [4:0] TXPCSRESET_TIME = 5'b00001; - parameter [23:0] TXPHDLY_CFG = 24'h084020; - parameter [15:0] TXPH_CFG = 16'h0780; - parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; - parameter [4:0] TXPMARESET_TIME = 5'b00001; - parameter integer TX_CLK25_DIV = 7; - parameter [0:0] TX_CLKMUX_PD = 1'b1; - parameter integer TX_DATA_WIDTH = 20; - parameter [4:0] TX_DEEMPH0 = 5'b00000; - parameter [4:0] TX_DEEMPH1 = 5'b00000; - parameter TX_DRIVE_MODE = "DIRECT"; - parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; - parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; - parameter integer TX_INT_DATAWIDTH = 0; - parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; - parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; - parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; - parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; - parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; - parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; - parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; - parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; - parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; - parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; - parameter [0:0] TX_PREDRIVER_MODE = 1'b0; - parameter [0:0] TX_QPI_STATUS_EN = 1'b0; - parameter [13:0] TX_RXDETECT_CFG = 14'h1832; - parameter [2:0] TX_RXDETECT_REF = 3'b100; - parameter TX_XCLK_SEL = "TXUSR"; - parameter [0:0] UCODEER_CLR = 1'b0; - output CPLLFBCLKLOST; - output CPLLLOCK; - output CPLLREFCLKLOST; - output DRPRDY; - output EYESCANDATAERROR; - output GTREFCLKMONITOR; - output GTXTXN; - output GTXTXP; - output PHYSTATUS; - output RXBYTEISALIGNED; - output RXBYTEREALIGN; - output RXCDRLOCK; - output RXCHANBONDSEQ; - output RXCHANISALIGNED; - output RXCHANREALIGN; - output RXCOMINITDET; - output RXCOMMADET; - output RXCOMSASDET; - output RXCOMWAKEDET; - output RXDATAVALID; - output RXDLYSRESETDONE; - output RXELECIDLE; - output RXHEADERVALID; - output RXOUTCLK; - output RXOUTCLKFABRIC; - output RXOUTCLKPCS; - output RXPHALIGNDONE; - output RXPRBSERR; - output RXQPISENN; - output RXQPISENP; - output RXRATEDONE; - output RXRESETDONE; - output RXSTARTOFSEQ; - output RXVALID; - output TXCOMFINISH; - output TXDLYSRESETDONE; - output TXGEARBOXREADY; - output TXOUTCLK; - output TXOUTCLKFABRIC; - output TXOUTCLKPCS; - output TXPHALIGNDONE; - output TXPHINITDONE; - output TXQPISENN; - output TXQPISENP; - output TXRATEDONE; - output TXRESETDONE; - output [15:0] DRPDO; - output [15:0] PCSRSVDOUT; - output [1:0] RXCLKCORCNT; - output [1:0] TXBUFSTATUS; - output [2:0] RXBUFSTATUS; - output [2:0] RXHEADER; - output [2:0] RXSTATUS; - output [4:0] RXCHBONDO; - output [4:0] RXPHMONITOR; - output [4:0] RXPHSLIPMONITOR; - output [63:0] RXDATA; - output [6:0] RXMONITOROUT; - output [7:0] DMONITOROUT; - output [7:0] RXCHARISCOMMA; - output [7:0] RXCHARISK; - output [7:0] RXDISPERR; - output [7:0] RXNOTINTABLE; - output [9:0] TSTOUT; - input CFGRESET; - (* invertible_pin = "IS_CPLLLOCKDETCLK_INVERTED" *) - input CPLLLOCKDETCLK; - input CPLLLOCKEN; - input CPLLPD; - input CPLLRESET; - (* invertible_pin = "IS_DRPCLK_INVERTED" *) - input DRPCLK; - input DRPEN; - input DRPWE; - input EYESCANMODE; - input EYESCANRESET; - input EYESCANTRIGGER; - (* invertible_pin = "IS_GTGREFCLK_INVERTED" *) - input GTGREFCLK; - input GTNORTHREFCLK0; - input GTNORTHREFCLK1; - input GTREFCLK0; - input GTREFCLK1; - input GTRESETSEL; - input GTRXRESET; - input GTSOUTHREFCLK0; - input GTSOUTHREFCLK1; - input GTTXRESET; - input GTXRXN; - input GTXRXP; - input QPLLCLK; - input QPLLREFCLK; - input RESETOVRD; - input RX8B10BEN; - input RXBUFRESET; - input RXCDRFREQRESET; - input RXCDRHOLD; - input RXCDROVRDEN; - input RXCDRRESET; - input RXCDRRESETRSV; - input RXCHBONDEN; - input RXCHBONDMASTER; - input RXCHBONDSLAVE; - input RXCOMMADETEN; - input RXDDIEN; - input RXDFEAGCHOLD; - input RXDFEAGCOVRDEN; - input RXDFECM1EN; - input RXDFELFHOLD; - input RXDFELFOVRDEN; - input RXDFELPMRESET; - input RXDFETAP2HOLD; - input RXDFETAP2OVRDEN; - input RXDFETAP3HOLD; - input RXDFETAP3OVRDEN; - input RXDFETAP4HOLD; - input RXDFETAP4OVRDEN; - input RXDFETAP5HOLD; - input RXDFETAP5OVRDEN; - input RXDFEUTHOLD; - input RXDFEUTOVRDEN; - input RXDFEVPHOLD; - input RXDFEVPOVRDEN; - input RXDFEVSEN; - input RXDFEXYDEN; - input RXDFEXYDHOLD; - input RXDFEXYDOVRDEN; - input RXDLYBYPASS; - input RXDLYEN; - input RXDLYOVRDEN; - input RXDLYSRESET; - input RXGEARBOXSLIP; - input RXLPMEN; - input RXLPMHFHOLD; - input RXLPMHFOVRDEN; - input RXLPMLFHOLD; - input RXLPMLFKLOVRDEN; - input RXMCOMMAALIGNEN; - input RXOOBRESET; - input RXOSHOLD; - input RXOSOVRDEN; - input RXPCOMMAALIGNEN; - input RXPCSRESET; - input RXPHALIGN; - input RXPHALIGNEN; - input RXPHDLYPD; - input RXPHDLYRESET; - input RXPHOVRDEN; - input RXPMARESET; - input RXPOLARITY; - input RXPRBSCNTRESET; - input RXQPIEN; - input RXSLIDE; - input RXUSERRDY; - (* invertible_pin = "IS_RXUSRCLK2_INVERTED" *) - input RXUSRCLK2; - (* invertible_pin = "IS_RXUSRCLK_INVERTED" *) - input RXUSRCLK; - input SETERRSTATUS; - input TX8B10BEN; - input TXCOMINIT; - input TXCOMSAS; - input TXCOMWAKE; - input TXDEEMPH; - input TXDETECTRX; - input TXDIFFPD; - input TXDLYBYPASS; - input TXDLYEN; - input TXDLYHOLD; - input TXDLYOVRDEN; - input TXDLYSRESET; - input TXDLYUPDOWN; - input TXELECIDLE; - input TXINHIBIT; - input TXPCSRESET; - input TXPDELECIDLEMODE; - input TXPHALIGN; - input TXPHALIGNEN; - input TXPHDLYPD; - input TXPHDLYRESET; - (* invertible_pin = "IS_TXPHDLYTSTCLK_INVERTED" *) - input TXPHDLYTSTCLK; - input TXPHINIT; - input TXPHOVRDEN; - input TXPISOPD; - input TXPMARESET; - input TXPOLARITY; - input TXPOSTCURSORINV; - input TXPRBSFORCEERR; - input TXPRECURSORINV; - input TXQPIBIASEN; - input TXQPISTRONGPDOWN; - input TXQPIWEAKPUP; - input TXSTARTSEQ; - input TXSWING; - input TXUSERRDY; - (* invertible_pin = "IS_TXUSRCLK2_INVERTED" *) - input TXUSRCLK2; - (* invertible_pin = "IS_TXUSRCLK_INVERTED" *) - input TXUSRCLK; - input [15:0] DRPDI; - input [15:0] GTRSVD; - input [15:0] PCSRSVDIN; - input [19:0] TSTIN; - input [1:0] RXELECIDLEMODE; - input [1:0] RXMONITORSEL; - input [1:0] RXPD; - input [1:0] RXSYSCLKSEL; - input [1:0] TXPD; - input [1:0] TXSYSCLKSEL; - input [2:0] CPLLREFCLKSEL; - input [2:0] LOOPBACK; - input [2:0] RXCHBONDLEVEL; - input [2:0] RXOUTCLKSEL; - input [2:0] RXPRBSSEL; - input [2:0] RXRATE; - input [2:0] TXBUFDIFFCTRL; - input [2:0] TXHEADER; - input [2:0] TXMARGIN; - input [2:0] TXOUTCLKSEL; - input [2:0] TXPRBSSEL; - input [2:0] TXRATE; - input [3:0] CLKRSVD; - input [3:0] TXDIFFCTRL; - input [4:0] PCSRSVDIN2; - input [4:0] PMARSVDIN2; - input [4:0] PMARSVDIN; - input [4:0] RXCHBONDI; - input [4:0] TXPOSTCURSOR; - input [4:0] TXPRECURSOR; - input [63:0] TXDATA; - input [6:0] TXMAINCURSOR; - input [6:0] TXSEQUENCE; - input [7:0] TX8B10BBYPASS; - input [7:0] TXCHARDISPMODE; - input [7:0] TXCHARDISPVAL; - input [7:0] TXCHARISK; - input [8:0] DRPADDR; -endmodule - -module GTXE2_COMMON (...); - parameter [63:0] BIAS_CFG = 64'h0000040000001000; - parameter [31:0] COMMON_CFG = 32'h00000000; - parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; - parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0; - parameter [0:0] IS_QPLLLOCKDETCLK_INVERTED = 1'b0; - parameter [26:0] QPLL_CFG = 27'h0680181; - parameter [3:0] QPLL_CLKOUT_CFG = 4'b0000; - parameter [5:0] QPLL_COARSE_FREQ_OVRD = 6'b010000; - parameter [0:0] QPLL_COARSE_FREQ_OVRD_EN = 1'b0; - parameter [9:0] QPLL_CP = 10'b0000011111; - parameter [0:0] QPLL_CP_MONITOR_EN = 1'b0; - parameter [0:0] QPLL_DMONITOR_SEL = 1'b0; - parameter [9:0] QPLL_FBDIV = 10'b0000000000; - parameter [0:0] QPLL_FBDIV_MONITOR_EN = 1'b0; - parameter [0:0] QPLL_FBDIV_RATIO = 1'b0; - parameter [23:0] QPLL_INIT_CFG = 24'h000006; - parameter [15:0] QPLL_LOCK_CFG = 16'h21E8; - parameter [3:0] QPLL_LPF = 4'b1111; - parameter integer QPLL_REFCLK_DIV = 2; - parameter [2:0] SIM_QPLLREFCLK_SEL = 3'b001; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter SIM_VERSION = "4.0"; - output DRPRDY; - output QPLLFBCLKLOST; - output QPLLLOCK; - output QPLLOUTCLK; - output QPLLOUTREFCLK; - output QPLLREFCLKLOST; - output REFCLKOUTMONITOR; - output [15:0] DRPDO; - output [7:0] QPLLDMONITOR; - input BGBYPASSB; - input BGMONITORENB; - input BGPDB; - (* invertible_pin = "IS_DRPCLK_INVERTED" *) - input DRPCLK; - input DRPEN; - input DRPWE; - (* invertible_pin = "IS_GTGREFCLK_INVERTED" *) - input GTGREFCLK; - input GTNORTHREFCLK0; - input GTNORTHREFCLK1; - input GTREFCLK0; - input GTREFCLK1; - input GTSOUTHREFCLK0; - input GTSOUTHREFCLK1; - (* invertible_pin = "IS_QPLLLOCKDETCLK_INVERTED" *) - input QPLLLOCKDETCLK; - input QPLLLOCKEN; - input QPLLOUTRESET; - input QPLLPD; - input QPLLRESET; - input RCALENB; - input [15:0] DRPDI; - input [15:0] QPLLRSVD1; - input [2:0] QPLLREFCLKSEL; - input [4:0] BGRCALOVRD; - input [4:0] QPLLRSVD2; - input [7:0] DRPADDR; - input [7:0] PMARSVD; -endmodule - -module IBUFDS_GTE2 (...); - parameter CLKCM_CFG = "TRUE"; - parameter CLKRCV_TRST = "TRUE"; - parameter CLKSWING_CFG = "TRUE"; - output O; - output ODIV2; - input CEB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module GTHE3_CHANNEL (...); - parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; - parameter [0:0] ACJTAG_MODE = 1'b0; - parameter [0:0] ACJTAG_RESET = 1'b0; - parameter [15:0] ADAPT_CFG0 = 16'hF800; - parameter [15:0] ADAPT_CFG1 = 16'h0000; - parameter ALIGN_COMMA_DOUBLE = "FALSE"; - parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; - parameter integer ALIGN_COMMA_WORD = 1; - parameter ALIGN_MCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; - parameter ALIGN_PCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; - parameter [0:0] A_RXOSCALRESET = 1'b0; - parameter [0:0] A_RXPROGDIVRESET = 1'b0; - parameter [0:0] A_TXPROGDIVRESET = 1'b0; - parameter CBCC_DATA_SOURCE_SEL = "DECODED"; - parameter [0:0] CDR_SWAP_MODE_EN = 1'b0; - parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; - parameter integer CHAN_BOND_MAX_SKEW = 7; - parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; - parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; - parameter CHAN_BOND_SEQ_2_USE = "FALSE"; - parameter integer CHAN_BOND_SEQ_LEN = 2; - parameter CLK_CORRECT_USE = "TRUE"; - parameter CLK_COR_KEEP_IDLE = "FALSE"; - parameter integer CLK_COR_MAX_LAT = 20; - parameter integer CLK_COR_MIN_LAT = 18; - parameter CLK_COR_PRECEDENCE = "TRUE"; - parameter integer CLK_COR_REPEAT_WAIT = 0; - parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; - parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; - parameter CLK_COR_SEQ_2_USE = "FALSE"; - parameter integer CLK_COR_SEQ_LEN = 2; - parameter [15:0] CPLL_CFG0 = 16'h20F8; - parameter [15:0] CPLL_CFG1 = 16'hA494; - parameter [15:0] CPLL_CFG2 = 16'hF001; - parameter [5:0] CPLL_CFG3 = 6'h00; - parameter integer CPLL_FBDIV = 4; - parameter integer CPLL_FBDIV_45 = 4; - parameter [15:0] CPLL_INIT_CFG0 = 16'h001E; - parameter [7:0] CPLL_INIT_CFG1 = 8'h00; - parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; - parameter integer CPLL_REFCLK_DIV = 1; - parameter [1:0] DDI_CTRL = 2'b00; - parameter integer DDI_REALIGN_WAIT = 15; - parameter DEC_MCOMMA_DETECT = "TRUE"; - parameter DEC_PCOMMA_DETECT = "TRUE"; - parameter DEC_VALID_COMMA_ONLY = "TRUE"; - parameter [0:0] DFE_D_X_REL_POS = 1'b0; - parameter [0:0] DFE_VCM_COMP_EN = 1'b0; - parameter [9:0] DMONITOR_CFG0 = 10'h000; - parameter [7:0] DMONITOR_CFG1 = 8'h00; - parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; - parameter [5:0] ES_CONTROL = 6'b000000; - parameter ES_ERRDET_EN = "FALSE"; - parameter ES_EYE_SCAN_EN = "FALSE"; - parameter [11:0] ES_HORZ_OFFSET = 12'h000; - parameter [9:0] ES_PMA_CFG = 10'b0000000000; - parameter [4:0] ES_PRESCALE = 5'b00000; - parameter [15:0] ES_QUALIFIER0 = 16'h0000; - parameter [15:0] ES_QUALIFIER1 = 16'h0000; - parameter [15:0] ES_QUALIFIER2 = 16'h0000; - parameter [15:0] ES_QUALIFIER3 = 16'h0000; - parameter [15:0] ES_QUALIFIER4 = 16'h0000; - parameter [15:0] ES_QUAL_MASK0 = 16'h0000; - parameter [15:0] ES_QUAL_MASK1 = 16'h0000; - parameter [15:0] ES_QUAL_MASK2 = 16'h0000; - parameter [15:0] ES_QUAL_MASK3 = 16'h0000; - parameter [15:0] ES_QUAL_MASK4 = 16'h0000; - parameter [15:0] ES_SDATA_MASK0 = 16'h0000; - parameter [15:0] ES_SDATA_MASK1 = 16'h0000; - parameter [15:0] ES_SDATA_MASK2 = 16'h0000; - parameter [15:0] ES_SDATA_MASK3 = 16'h0000; - parameter [15:0] ES_SDATA_MASK4 = 16'h0000; - parameter [10:0] EVODD_PHI_CFG = 11'b00000000000; - parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0; - parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; - parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; - parameter FTS_LANE_DESKEW_EN = "FALSE"; - parameter [4:0] GEARBOX_MODE = 5'b00000; - parameter [0:0] GM_BIAS_SELECT = 1'b0; - parameter [0:0] LOCAL_MASTER = 1'b0; - parameter [1:0] OOBDIVCTL = 2'b00; - parameter [0:0] OOB_PWRUP = 1'b0; - parameter PCI3_AUTO_REALIGN = "FRST_SMPL"; - parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1; - parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00; - parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0; - parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000; - parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000; - parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000; - parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0; - parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0; - parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000; - parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000; - parameter [15:0] PCIE_RXPMA_CFG = 16'h0000; - parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000; - parameter [15:0] PCIE_TXPMA_CFG = 16'h0000; - parameter PCS_PCIE_EN = "FALSE"; - parameter [15:0] PCS_RSVD0 = 16'b0000000000000000; - parameter [2:0] PCS_RSVD1 = 3'b000; - parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; - parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; - parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; - parameter [1:0] PLL_SEL_MODE_GEN12 = 2'h0; - parameter [1:0] PLL_SEL_MODE_GEN3 = 2'h0; - parameter [15:0] PMA_RSV1 = 16'h0000; - parameter [2:0] PROCESS_PAR = 3'b010; - parameter [0:0] RATE_SW_USE_DRP = 1'b0; - parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0; - parameter [4:0] RXBUFRESET_TIME = 5'b00001; - parameter RXBUF_ADDR_MODE = "FULL"; - parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; - parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; - parameter RXBUF_EN = "TRUE"; - parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; - parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; - parameter RXBUF_RESET_ON_EIDLE = "FALSE"; - parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; - parameter integer RXBUF_THRESH_OVFLW = 0; - parameter RXBUF_THRESH_OVRD = "FALSE"; - parameter integer RXBUF_THRESH_UNDFLW = 4; - parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; - parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; - parameter [15:0] RXCDR_CFG0 = 16'h0000; - parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0000; - parameter [15:0] RXCDR_CFG1 = 16'h0080; - parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000; - parameter [15:0] RXCDR_CFG2 = 16'h07E6; - parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0000; - parameter [15:0] RXCDR_CFG3 = 16'h0000; - parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0000; - parameter [15:0] RXCDR_CFG4 = 16'h0000; - parameter [15:0] RXCDR_CFG4_GEN3 = 16'h0000; - parameter [15:0] RXCDR_CFG5 = 16'h0000; - parameter [15:0] RXCDR_CFG5_GEN3 = 16'h0000; - parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; - parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; - parameter [15:0] RXCDR_LOCK_CFG0 = 16'h5080; - parameter [15:0] RXCDR_LOCK_CFG1 = 16'h07E0; - parameter [15:0] RXCDR_LOCK_CFG2 = 16'h7C42; - parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; - parameter [15:0] RXCFOK_CFG0 = 16'h4000; - parameter [15:0] RXCFOK_CFG1 = 16'h0060; - parameter [15:0] RXCFOK_CFG2 = 16'h000E; - parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; - parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000; - parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0032; - parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0000; - parameter [15:0] RXDFE_CFG0 = 16'h0A00; - parameter [15:0] RXDFE_CFG1 = 16'h0000; - parameter [15:0] RXDFE_GC_CFG0 = 16'h0000; - parameter [15:0] RXDFE_GC_CFG1 = 16'h7840; - parameter [15:0] RXDFE_GC_CFG2 = 16'h0000; - parameter [15:0] RXDFE_H2_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H2_CFG1 = 16'h0000; - parameter [15:0] RXDFE_H3_CFG0 = 16'h4000; - parameter [15:0] RXDFE_H3_CFG1 = 16'h0000; - parameter [15:0] RXDFE_H4_CFG0 = 16'h2000; - parameter [15:0] RXDFE_H4_CFG1 = 16'h0003; - parameter [15:0] RXDFE_H5_CFG0 = 16'h2000; - parameter [15:0] RXDFE_H5_CFG1 = 16'h0003; - parameter [15:0] RXDFE_H6_CFG0 = 16'h2000; - parameter [15:0] RXDFE_H6_CFG1 = 16'h0000; - parameter [15:0] RXDFE_H7_CFG0 = 16'h2000; - parameter [15:0] RXDFE_H7_CFG1 = 16'h0000; - parameter [15:0] RXDFE_H8_CFG0 = 16'h2000; - parameter [15:0] RXDFE_H8_CFG1 = 16'h0000; - parameter [15:0] RXDFE_H9_CFG0 = 16'h2000; - parameter [15:0] RXDFE_H9_CFG1 = 16'h0000; - parameter [15:0] RXDFE_HA_CFG0 = 16'h2000; - parameter [15:0] RXDFE_HA_CFG1 = 16'h0000; - parameter [15:0] RXDFE_HB_CFG0 = 16'h2000; - parameter [15:0] RXDFE_HB_CFG1 = 16'h0000; - parameter [15:0] RXDFE_HC_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HC_CFG1 = 16'h0000; - parameter [15:0] RXDFE_HD_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HD_CFG1 = 16'h0000; - parameter [15:0] RXDFE_HE_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HE_CFG1 = 16'h0000; - parameter [15:0] RXDFE_HF_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HF_CFG1 = 16'h0000; - parameter [15:0] RXDFE_OS_CFG0 = 16'h8000; - parameter [15:0] RXDFE_OS_CFG1 = 16'h0000; - parameter [15:0] RXDFE_UT_CFG0 = 16'h8000; - parameter [15:0] RXDFE_UT_CFG1 = 16'h0003; - parameter [15:0] RXDFE_VP_CFG0 = 16'hAA00; - parameter [15:0] RXDFE_VP_CFG1 = 16'h0033; - parameter [15:0] RXDLY_CFG = 16'h001F; - parameter [15:0] RXDLY_LCFG = 16'h0030; - parameter RXELECIDLE_CFG = "Sigcfg_4"; - parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4; - parameter RXGEARBOX_EN = "FALSE"; - parameter [4:0] RXISCANRESET_TIME = 5'b00001; - parameter [15:0] RXLPM_CFG = 16'h0000; - parameter [15:0] RXLPM_GC_CFG = 16'h0000; - parameter [15:0] RXLPM_KH_CFG0 = 16'h0000; - parameter [15:0] RXLPM_KH_CFG1 = 16'h0002; - parameter [15:0] RXLPM_OS_CFG0 = 16'h8000; - parameter [15:0] RXLPM_OS_CFG1 = 16'h0002; - parameter [8:0] RXOOB_CFG = 9'b000000110; - parameter RXOOB_CLK_CFG = "PMA"; - parameter [4:0] RXOSCALRESET_TIME = 5'b00011; - parameter integer RXOUT_DIV = 4; - parameter [4:0] RXPCSRESET_TIME = 5'b00001; - parameter [15:0] RXPHBEACON_CFG = 16'h0000; - parameter [15:0] RXPHDLY_CFG = 16'h2020; - parameter [15:0] RXPHSAMP_CFG = 16'h2100; - parameter [15:0] RXPHSLIP_CFG = 16'h6622; - parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; - parameter [1:0] RXPI_CFG0 = 2'b00; - parameter [1:0] RXPI_CFG1 = 2'b00; - parameter [1:0] RXPI_CFG2 = 2'b00; - parameter [1:0] RXPI_CFG3 = 2'b00; - parameter [0:0] RXPI_CFG4 = 1'b0; - parameter [0:0] RXPI_CFG5 = 1'b1; - parameter [2:0] RXPI_CFG6 = 3'b000; - parameter [0:0] RXPI_LPM = 1'b0; - parameter [0:0] RXPI_VREFSEL = 1'b0; - parameter RXPMACLK_SEL = "DATA"; - parameter [4:0] RXPMARESET_TIME = 5'b00001; - parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; - parameter integer RXPRBS_LINKACQ_CNT = 15; - parameter integer RXSLIDE_AUTO_WAIT = 7; - parameter RXSLIDE_MODE = "OFF"; - parameter [0:0] RXSYNC_MULTILANE = 1'b0; - parameter [0:0] RXSYNC_OVRD = 1'b0; - parameter [0:0] RXSYNC_SKIP_DA = 1'b0; - parameter [0:0] RX_AFE_CM_EN = 1'b0; - parameter [15:0] RX_BIAS_CFG0 = 16'h0AD4; - parameter [5:0] RX_BUFFER_CFG = 6'b000000; - parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0; - parameter integer RX_CLK25_DIV = 8; - parameter [0:0] RX_CLKMUX_EN = 1'b1; - parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000; - parameter [3:0] RX_CM_BUF_CFG = 4'b1010; - parameter [0:0] RX_CM_BUF_PD = 1'b0; - parameter [1:0] RX_CM_SEL = 2'b11; - parameter [3:0] RX_CM_TRIM = 4'b0100; - parameter [7:0] RX_CTLE3_LPF = 8'b00000000; - parameter integer RX_DATA_WIDTH = 20; - parameter [5:0] RX_DDI_SEL = 6'b000000; - parameter RX_DEFER_RESET_BUF_EN = "TRUE"; - parameter [3:0] RX_DFELPM_CFG0 = 4'b0110; - parameter [0:0] RX_DFELPM_CFG1 = 1'b0; - parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1; - parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00; - parameter [2:0] RX_DFE_AGC_CFG1 = 3'b100; - parameter [1:0] RX_DFE_KL_LPM_KH_CFG0 = 2'b01; - parameter [2:0] RX_DFE_KL_LPM_KH_CFG1 = 3'b010; - parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01; - parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010; - parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; - parameter RX_DISPERR_SEQ_MATCH = "TRUE"; - parameter [4:0] RX_DIVRESET_TIME = 5'b00001; - parameter [0:0] RX_EN_HI_LR = 1'b0; - parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000; - parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0; - parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00; - parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0; - parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0; - parameter integer RX_INT_DATAWIDTH = 1; - parameter [0:0] RX_PMA_POWER_SAVE = 1'b0; - parameter real RX_PROGDIV_CFG = 4.0; - parameter [2:0] RX_SAMPLE_PERIOD = 3'b101; - parameter integer RX_SIG_VALID_DLY = 11; - parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0; - parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000; - parameter [1:0] RX_SUM_RES_CTRL = 2'b00; - parameter [3:0] RX_SUM_VCMTUNE = 4'b0000; - parameter [0:0] RX_SUM_VCM_OVWR = 1'b0; - parameter [2:0] RX_SUM_VREF_TUNE = 3'b000; - parameter [1:0] RX_TUNE_AFE_OS = 2'b00; - parameter [0:0] RX_WIDEMODE_CDR = 1'b0; - parameter RX_XCLK_SEL = "RXDES"; - parameter integer SAS_MAX_COM = 64; - parameter integer SAS_MIN_COM = 36; - parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; - parameter [2:0] SATA_BURST_VAL = 3'b100; - parameter SATA_CPLL_CFG = "VCO_3000MHZ"; - parameter [2:0] SATA_EIDLE_VAL = 3'b100; - parameter integer SATA_MAX_BURST = 8; - parameter integer SATA_MAX_INIT = 21; - parameter integer SATA_MAX_WAKE = 7; - parameter integer SATA_MIN_BURST = 4; - parameter integer SATA_MIN_INIT = 12; - parameter integer SATA_MIN_WAKE = 4; - parameter SHOW_REALIGN_COMMA = "TRUE"; - parameter SIM_MODE = "FAST"; - parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter [0:0] SIM_TX_EIDLE_DRIVE_LEVEL = 1'b0; - parameter integer SIM_VERSION = 2; - parameter [1:0] TAPDLY_SET_TX = 2'h0; - parameter [3:0] TEMPERATUR_PAR = 4'b0010; - parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; - parameter [2:0] TERM_RCAL_OVRD = 3'b000; - parameter [7:0] TRANS_TIME_RATE = 8'h0E; - parameter [7:0] TST_RSV0 = 8'h00; - parameter [7:0] TST_RSV1 = 8'h00; - parameter TXBUF_EN = "TRUE"; - parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; - parameter [15:0] TXDLY_CFG = 16'h001F; - parameter [15:0] TXDLY_LCFG = 16'h0030; - parameter [3:0] TXDRVBIAS_N = 4'b1010; - parameter [3:0] TXDRVBIAS_P = 4'b1100; - parameter TXFIFO_ADDR_CFG = "LOW"; - parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4; - parameter TXGEARBOX_EN = "FALSE"; - parameter integer TXOUT_DIV = 4; - parameter [4:0] TXPCSRESET_TIME = 5'b00001; - parameter [15:0] TXPHDLY_CFG0 = 16'h2020; - parameter [15:0] TXPHDLY_CFG1 = 16'h0001; - parameter [15:0] TXPH_CFG = 16'h0980; - parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; - parameter [1:0] TXPI_CFG0 = 2'b00; - parameter [1:0] TXPI_CFG1 = 2'b00; - parameter [1:0] TXPI_CFG2 = 2'b00; - parameter [0:0] TXPI_CFG3 = 1'b0; - parameter [0:0] TXPI_CFG4 = 1'b1; - parameter [2:0] TXPI_CFG5 = 3'b000; - parameter [0:0] TXPI_GRAY_SEL = 1'b0; - parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; - parameter [0:0] TXPI_LPM = 1'b0; - parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; - parameter [7:0] TXPI_PPM_CFG = 8'b00000000; - parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; - parameter [0:0] TXPI_VREFSEL = 1'b0; - parameter [4:0] TXPMARESET_TIME = 5'b00001; - parameter [0:0] TXSYNC_MULTILANE = 1'b0; - parameter [0:0] TXSYNC_OVRD = 1'b0; - parameter [0:0] TXSYNC_SKIP_DA = 1'b0; - parameter integer TX_CLK25_DIV = 8; - parameter [0:0] TX_CLKMUX_EN = 1'b1; - parameter integer TX_DATA_WIDTH = 20; - parameter [5:0] TX_DCD_CFG = 6'b000010; - parameter [0:0] TX_DCD_EN = 1'b0; - parameter [5:0] TX_DEEMPH0 = 6'b000000; - parameter [5:0] TX_DEEMPH1 = 6'b000000; - parameter [4:0] TX_DIVRESET_TIME = 5'b00001; - parameter TX_DRIVE_MODE = "DIRECT"; - parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; - parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; - parameter [0:0] TX_EML_PHI_TUNE = 1'b0; - parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0; - parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0; - parameter integer TX_INT_DATAWIDTH = 1; - parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; - parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; - parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; - parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; - parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; - parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; - parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; - parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; - parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; - parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; - parameter [2:0] TX_MODE_SEL = 3'b000; - parameter [0:0] TX_PMADATA_OPT = 1'b0; - parameter [0:0] TX_PMA_POWER_SAVE = 1'b0; - parameter TX_PROGCLK_SEL = "POSTPI"; - parameter real TX_PROGDIV_CFG = 4.0; - parameter [0:0] TX_QPI_STATUS_EN = 1'b0; - parameter [13:0] TX_RXDETECT_CFG = 14'h0032; - parameter [2:0] TX_RXDETECT_REF = 3'b100; - parameter [2:0] TX_SAMPLE_PERIOD = 3'b101; - parameter [0:0] TX_SARC_LPBK_ENB = 1'b0; - parameter TX_XCLK_SEL = "TXOUT"; - parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; - parameter [1:0] WB_MODE = 2'b00; - output [2:0] BUFGTCE; - output [2:0] BUFGTCEMASK; - output [8:0] BUFGTDIV; - output [2:0] BUFGTRESET; - output [2:0] BUFGTRSTMASK; - output CPLLFBCLKLOST; - output CPLLLOCK; - output CPLLREFCLKLOST; - output [16:0] DMONITOROUT; - output [15:0] DRPDO; - output DRPRDY; - output EYESCANDATAERROR; - output GTHTXN; - output GTHTXP; - output GTPOWERGOOD; - output GTREFCLKMONITOR; - output PCIERATEGEN3; - output PCIERATEIDLE; - output [1:0] PCIERATEQPLLPD; - output [1:0] PCIERATEQPLLRESET; - output PCIESYNCTXSYNCDONE; - output PCIEUSERGEN3RDY; - output PCIEUSERPHYSTATUSRST; - output PCIEUSERRATESTART; - output [11:0] PCSRSVDOUT; - output PHYSTATUS; - output [7:0] PINRSRVDAS; - output RESETEXCEPTION; - output [2:0] RXBUFSTATUS; - output RXBYTEISALIGNED; - output RXBYTEREALIGN; - output RXCDRLOCK; - output RXCDRPHDONE; - output RXCHANBONDSEQ; - output RXCHANISALIGNED; - output RXCHANREALIGN; - output [4:0] RXCHBONDO; - output [1:0] RXCLKCORCNT; - output RXCOMINITDET; - output RXCOMMADET; - output RXCOMSASDET; - output RXCOMWAKEDET; - output [15:0] RXCTRL0; - output [15:0] RXCTRL1; - output [7:0] RXCTRL2; - output [7:0] RXCTRL3; - output [127:0] RXDATA; - output [7:0] RXDATAEXTENDRSVD; - output [1:0] RXDATAVALID; - output RXDLYSRESETDONE; - output RXELECIDLE; - output [5:0] RXHEADER; - output [1:0] RXHEADERVALID; - output [6:0] RXMONITOROUT; - output RXOSINTDONE; - output RXOSINTSTARTED; - output RXOSINTSTROBEDONE; - output RXOSINTSTROBESTARTED; - output RXOUTCLK; - output RXOUTCLKFABRIC; - output RXOUTCLKPCS; - output RXPHALIGNDONE; - output RXPHALIGNERR; - output RXPMARESETDONE; - output RXPRBSERR; - output RXPRBSLOCKED; - output RXPRGDIVRESETDONE; - output RXQPISENN; - output RXQPISENP; - output RXRATEDONE; - output RXRECCLKOUT; - output RXRESETDONE; - output RXSLIDERDY; - output RXSLIPDONE; - output RXSLIPOUTCLKRDY; - output RXSLIPPMARDY; - output [1:0] RXSTARTOFSEQ; - output [2:0] RXSTATUS; - output RXSYNCDONE; - output RXSYNCOUT; - output RXVALID; - output [1:0] TXBUFSTATUS; - output TXCOMFINISH; - output TXDLYSRESETDONE; - output TXOUTCLK; - output TXOUTCLKFABRIC; - output TXOUTCLKPCS; - output TXPHALIGNDONE; - output TXPHINITDONE; - output TXPMARESETDONE; - output TXPRGDIVRESETDONE; - output TXQPISENN; - output TXQPISENP; - output TXRATEDONE; - output TXRESETDONE; - output TXSYNCDONE; - output TXSYNCOUT; - input CFGRESET; - input CLKRSVD0; - input CLKRSVD1; - input CPLLLOCKDETCLK; - input CPLLLOCKEN; - input CPLLPD; - input [2:0] CPLLREFCLKSEL; - input CPLLRESET; - input DMONFIFORESET; - input DMONITORCLK; - input [8:0] DRPADDR; - input DRPCLK; - input [15:0] DRPDI; - input DRPEN; - input DRPWE; - input EVODDPHICALDONE; - input EVODDPHICALSTART; - input EVODDPHIDRDEN; - input EVODDPHIDWREN; - input EVODDPHIXRDEN; - input EVODDPHIXWREN; - input EYESCANMODE; - input EYESCANRESET; - input EYESCANTRIGGER; - input GTGREFCLK; - input GTHRXN; - input GTHRXP; - input GTNORTHREFCLK0; - input GTNORTHREFCLK1; - input GTREFCLK0; - input GTREFCLK1; - input GTRESETSEL; - input [15:0] GTRSVD; - input GTRXRESET; - input GTSOUTHREFCLK0; - input GTSOUTHREFCLK1; - input GTTXRESET; - input [2:0] LOOPBACK; - input LPBKRXTXSEREN; - input LPBKTXRXSEREN; - input PCIEEQRXEQADAPTDONE; - input PCIERSTIDLE; - input PCIERSTTXSYNCSTART; - input PCIEUSERRATEDONE; - input [15:0] PCSRSVDIN; - input [4:0] PCSRSVDIN2; - input [4:0] PMARSVDIN; - input QPLL0CLK; - input QPLL0REFCLK; - input QPLL1CLK; - input QPLL1REFCLK; - input RESETOVRD; - input RSTCLKENTX; - input RX8B10BEN; - input RXBUFRESET; - input RXCDRFREQRESET; - input RXCDRHOLD; - input RXCDROVRDEN; - input RXCDRRESET; - input RXCDRRESETRSV; - input RXCHBONDEN; - input [4:0] RXCHBONDI; - input [2:0] RXCHBONDLEVEL; - input RXCHBONDMASTER; - input RXCHBONDSLAVE; - input RXCOMMADETEN; - input [1:0] RXDFEAGCCTRL; - input RXDFEAGCHOLD; - input RXDFEAGCOVRDEN; - input RXDFELFHOLD; - input RXDFELFOVRDEN; - input RXDFELPMRESET; - input RXDFETAP10HOLD; - input RXDFETAP10OVRDEN; - input RXDFETAP11HOLD; - input RXDFETAP11OVRDEN; - input RXDFETAP12HOLD; - input RXDFETAP12OVRDEN; - input RXDFETAP13HOLD; - input RXDFETAP13OVRDEN; - input RXDFETAP14HOLD; - input RXDFETAP14OVRDEN; - input RXDFETAP15HOLD; - input RXDFETAP15OVRDEN; - input RXDFETAP2HOLD; - input RXDFETAP2OVRDEN; - input RXDFETAP3HOLD; - input RXDFETAP3OVRDEN; - input RXDFETAP4HOLD; - input RXDFETAP4OVRDEN; - input RXDFETAP5HOLD; - input RXDFETAP5OVRDEN; - input RXDFETAP6HOLD; - input RXDFETAP6OVRDEN; - input RXDFETAP7HOLD; - input RXDFETAP7OVRDEN; - input RXDFETAP8HOLD; - input RXDFETAP8OVRDEN; - input RXDFETAP9HOLD; - input RXDFETAP9OVRDEN; - input RXDFEUTHOLD; - input RXDFEUTOVRDEN; - input RXDFEVPHOLD; - input RXDFEVPOVRDEN; - input RXDFEVSEN; - input RXDFEXYDEN; - input RXDLYBYPASS; - input RXDLYEN; - input RXDLYOVRDEN; - input RXDLYSRESET; - input [1:0] RXELECIDLEMODE; - input RXGEARBOXSLIP; - input RXLATCLK; - input RXLPMEN; - input RXLPMGCHOLD; - input RXLPMGCOVRDEN; - input RXLPMHFHOLD; - input RXLPMHFOVRDEN; - input RXLPMLFHOLD; - input RXLPMLFKLOVRDEN; - input RXLPMOSHOLD; - input RXLPMOSOVRDEN; - input RXMCOMMAALIGNEN; - input [1:0] RXMONITORSEL; - input RXOOBRESET; - input RXOSCALRESET; - input RXOSHOLD; - input [3:0] RXOSINTCFG; - input RXOSINTEN; - input RXOSINTHOLD; - input RXOSINTOVRDEN; - input RXOSINTSTROBE; - input RXOSINTTESTOVRDEN; - input RXOSOVRDEN; - input [2:0] RXOUTCLKSEL; - input RXPCOMMAALIGNEN; - input RXPCSRESET; - input [1:0] RXPD; - input RXPHALIGN; - input RXPHALIGNEN; - input RXPHDLYPD; - input RXPHDLYRESET; - input RXPHOVRDEN; - input [1:0] RXPLLCLKSEL; - input RXPMARESET; - input RXPOLARITY; - input RXPRBSCNTRESET; - input [3:0] RXPRBSSEL; - input RXPROGDIVRESET; - input RXQPIEN; - input [2:0] RXRATE; - input RXRATEMODE; - input RXSLIDE; - input RXSLIPOUTCLK; - input RXSLIPPMA; - input RXSYNCALLIN; - input RXSYNCIN; - input RXSYNCMODE; - input [1:0] RXSYSCLKSEL; - input RXUSERRDY; - input RXUSRCLK; - input RXUSRCLK2; - input SIGVALIDCLK; - input [19:0] TSTIN; - input [7:0] TX8B10BBYPASS; - input TX8B10BEN; - input [2:0] TXBUFDIFFCTRL; - input TXCOMINIT; - input TXCOMSAS; - input TXCOMWAKE; - input [15:0] TXCTRL0; - input [15:0] TXCTRL1; - input [7:0] TXCTRL2; - input [127:0] TXDATA; - input [7:0] TXDATAEXTENDRSVD; - input TXDEEMPH; - input TXDETECTRX; - input [3:0] TXDIFFCTRL; - input TXDIFFPD; - input TXDLYBYPASS; - input TXDLYEN; - input TXDLYHOLD; - input TXDLYOVRDEN; - input TXDLYSRESET; - input TXDLYUPDOWN; - input TXELECIDLE; - input [5:0] TXHEADER; - input TXINHIBIT; - input TXLATCLK; - input [6:0] TXMAINCURSOR; - input [2:0] TXMARGIN; - input [2:0] TXOUTCLKSEL; - input TXPCSRESET; - input [1:0] TXPD; - input TXPDELECIDLEMODE; - input TXPHALIGN; - input TXPHALIGNEN; - input TXPHDLYPD; - input TXPHDLYRESET; - input TXPHDLYTSTCLK; - input TXPHINIT; - input TXPHOVRDEN; - input TXPIPPMEN; - input TXPIPPMOVRDEN; - input TXPIPPMPD; - input TXPIPPMSEL; - input [4:0] TXPIPPMSTEPSIZE; - input TXPISOPD; - input [1:0] TXPLLCLKSEL; - input TXPMARESET; - input TXPOLARITY; - input [4:0] TXPOSTCURSOR; - input TXPOSTCURSORINV; - input TXPRBSFORCEERR; - input [3:0] TXPRBSSEL; - input [4:0] TXPRECURSOR; - input TXPRECURSORINV; - input TXPROGDIVRESET; - input TXQPIBIASEN; - input TXQPISTRONGPDOWN; - input TXQPIWEAKPUP; - input [2:0] TXRATE; - input TXRATEMODE; - input [6:0] TXSEQUENCE; - input TXSWING; - input TXSYNCALLIN; - input TXSYNCIN; - input TXSYNCMODE; - input [1:0] TXSYSCLKSEL; - input TXUSERRDY; - input TXUSRCLK; - input TXUSRCLK2; -endmodule - -module GTHE3_COMMON (...); - parameter [15:0] BIAS_CFG0 = 16'h0000; - parameter [15:0] BIAS_CFG1 = 16'h0000; - parameter [15:0] BIAS_CFG2 = 16'h0000; - parameter [15:0] BIAS_CFG3 = 16'h0000; - parameter [15:0] BIAS_CFG4 = 16'h0000; - parameter [9:0] BIAS_CFG_RSVD = 10'b0000000000; - parameter [15:0] COMMON_CFG0 = 16'h0000; - parameter [15:0] COMMON_CFG1 = 16'h0000; - parameter [15:0] POR_CFG = 16'h0004; - parameter [15:0] QPLL0_CFG0 = 16'h3018; - parameter [15:0] QPLL0_CFG1 = 16'h0000; - parameter [15:0] QPLL0_CFG1_G3 = 16'h0020; - parameter [15:0] QPLL0_CFG2 = 16'h0000; - parameter [15:0] QPLL0_CFG2_G3 = 16'h0000; - parameter [15:0] QPLL0_CFG3 = 16'h0120; - parameter [15:0] QPLL0_CFG4 = 16'h0009; - parameter [9:0] QPLL0_CP = 10'b0000011111; - parameter [9:0] QPLL0_CP_G3 = 10'b0000011111; - parameter integer QPLL0_FBDIV = 66; - parameter integer QPLL0_FBDIV_G3 = 80; - parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000; - parameter [7:0] QPLL0_INIT_CFG1 = 8'h00; - parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8; - parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h01E8; - parameter [9:0] QPLL0_LPF = 10'b1111111111; - parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111; - parameter integer QPLL0_REFCLK_DIV = 2; - parameter [15:0] QPLL0_SDM_CFG0 = 16'b0000000000000000; - parameter [15:0] QPLL0_SDM_CFG1 = 16'b0000000000000000; - parameter [15:0] QPLL0_SDM_CFG2 = 16'b0000000000000000; - parameter [15:0] QPLL1_CFG0 = 16'h3018; - parameter [15:0] QPLL1_CFG1 = 16'h0000; - parameter [15:0] QPLL1_CFG1_G3 = 16'h0020; - parameter [15:0] QPLL1_CFG2 = 16'h0000; - parameter [15:0] QPLL1_CFG2_G3 = 16'h0000; - parameter [15:0] QPLL1_CFG3 = 16'h0120; - parameter [15:0] QPLL1_CFG4 = 16'h0009; - parameter [9:0] QPLL1_CP = 10'b0000011111; - parameter [9:0] QPLL1_CP_G3 = 10'b0000011111; - parameter integer QPLL1_FBDIV = 66; - parameter integer QPLL1_FBDIV_G3 = 80; - parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000; - parameter [7:0] QPLL1_INIT_CFG1 = 8'h00; - parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8; - parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8; - parameter [9:0] QPLL1_LPF = 10'b1111111111; - parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111; - parameter integer QPLL1_REFCLK_DIV = 2; - parameter [15:0] QPLL1_SDM_CFG0 = 16'b0000000000000000; - parameter [15:0] QPLL1_SDM_CFG1 = 16'b0000000000000000; - parameter [15:0] QPLL1_SDM_CFG2 = 16'b0000000000000000; - parameter [15:0] RSVD_ATTR0 = 16'h0000; - parameter [15:0] RSVD_ATTR1 = 16'h0000; - parameter [15:0] RSVD_ATTR2 = 16'h0000; - parameter [15:0] RSVD_ATTR3 = 16'h0000; - parameter [1:0] RXRECCLKOUT0_SEL = 2'b00; - parameter [1:0] RXRECCLKOUT1_SEL = 2'b00; - parameter [0:0] SARC_EN = 1'b1; - parameter [0:0] SARC_SEL = 1'b0; - parameter [15:0] SDM0DATA1_0 = 16'b0000000000000000; - parameter [8:0] SDM0DATA1_1 = 9'b000000000; - parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000; - parameter [8:0] SDM0INITSEED0_1 = 9'b000000000; - parameter [0:0] SDM0_DATA_PIN_SEL = 1'b0; - parameter [0:0] SDM0_WIDTH_PIN_SEL = 1'b0; - parameter [15:0] SDM1DATA1_0 = 16'b0000000000000000; - parameter [8:0] SDM1DATA1_1 = 9'b000000000; - parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000; - parameter [8:0] SDM1INITSEED0_1 = 9'b000000000; - parameter [0:0] SDM1_DATA_PIN_SEL = 1'b0; - parameter [0:0] SDM1_WIDTH_PIN_SEL = 1'b0; - parameter SIM_MODE = "FAST"; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter integer SIM_VERSION = 2; - output [15:0] DRPDO; - output DRPRDY; - output [7:0] PMARSVDOUT0; - output [7:0] PMARSVDOUT1; - output QPLL0FBCLKLOST; - output QPLL0LOCK; - output QPLL0OUTCLK; - output QPLL0OUTREFCLK; - output QPLL0REFCLKLOST; - output QPLL1FBCLKLOST; - output QPLL1LOCK; - output QPLL1OUTCLK; - output QPLL1OUTREFCLK; - output QPLL1REFCLKLOST; - output [7:0] QPLLDMONITOR0; - output [7:0] QPLLDMONITOR1; - output REFCLKOUTMONITOR0; - output REFCLKOUTMONITOR1; - output [1:0] RXRECCLK0_SEL; - output [1:0] RXRECCLK1_SEL; - input BGBYPASSB; - input BGMONITORENB; - input BGPDB; - input [4:0] BGRCALOVRD; - input BGRCALOVRDENB; - input [8:0] DRPADDR; - input DRPCLK; - input [15:0] DRPDI; - input DRPEN; - input DRPWE; - input GTGREFCLK0; - input GTGREFCLK1; - input GTNORTHREFCLK00; - input GTNORTHREFCLK01; - input GTNORTHREFCLK10; - input GTNORTHREFCLK11; - input GTREFCLK00; - input GTREFCLK01; - input GTREFCLK10; - input GTREFCLK11; - input GTSOUTHREFCLK00; - input GTSOUTHREFCLK01; - input GTSOUTHREFCLK10; - input GTSOUTHREFCLK11; - input [7:0] PMARSVD0; - input [7:0] PMARSVD1; - input QPLL0CLKRSVD0; - input QPLL0CLKRSVD1; - input QPLL0LOCKDETCLK; - input QPLL0LOCKEN; - input QPLL0PD; - input [2:0] QPLL0REFCLKSEL; - input QPLL0RESET; - input QPLL1CLKRSVD0; - input QPLL1CLKRSVD1; - input QPLL1LOCKDETCLK; - input QPLL1LOCKEN; - input QPLL1PD; - input [2:0] QPLL1REFCLKSEL; - input QPLL1RESET; - input [7:0] QPLLRSVD1; - input [4:0] QPLLRSVD2; - input [4:0] QPLLRSVD3; - input [7:0] QPLLRSVD4; - input RCALENB; -endmodule - -module GTYE3_CHANNEL (...); - parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; - parameter [0:0] ACJTAG_MODE = 1'b0; - parameter [0:0] ACJTAG_RESET = 1'b0; - parameter [15:0] ADAPT_CFG0 = 16'h9200; - parameter [15:0] ADAPT_CFG1 = 16'h801C; - parameter [15:0] ADAPT_CFG2 = 16'b0000000000000000; - parameter ALIGN_COMMA_DOUBLE = "FALSE"; - parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; - parameter integer ALIGN_COMMA_WORD = 1; - parameter ALIGN_MCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; - parameter ALIGN_PCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; - parameter [0:0] AUTO_BW_SEL_BYPASS = 1'b0; - parameter [0:0] A_RXOSCALRESET = 1'b0; - parameter [0:0] A_RXPROGDIVRESET = 1'b0; - parameter [4:0] A_TXDIFFCTRL = 5'b01100; - parameter [0:0] A_TXPROGDIVRESET = 1'b0; - parameter [0:0] CAPBYPASS_FORCE = 1'b0; - parameter CBCC_DATA_SOURCE_SEL = "DECODED"; - parameter [0:0] CDR_SWAP_MODE_EN = 1'b0; - parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; - parameter integer CHAN_BOND_MAX_SKEW = 7; - parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; - parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; - parameter CHAN_BOND_SEQ_2_USE = "FALSE"; - parameter integer CHAN_BOND_SEQ_LEN = 2; - parameter [15:0] CH_HSPMUX = 16'h0000; - parameter [15:0] CKCAL1_CFG_0 = 16'b0000000000000000; - parameter [15:0] CKCAL1_CFG_1 = 16'b0000000000000000; - parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000; - parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_0 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_1 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000; - parameter [15:0] CKCAL_RSVD0 = 16'h0000; - parameter [15:0] CKCAL_RSVD1 = 16'h0000; - parameter CLK_CORRECT_USE = "TRUE"; - parameter CLK_COR_KEEP_IDLE = "FALSE"; - parameter integer CLK_COR_MAX_LAT = 20; - parameter integer CLK_COR_MIN_LAT = 18; - parameter CLK_COR_PRECEDENCE = "TRUE"; - parameter integer CLK_COR_REPEAT_WAIT = 0; - parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; - parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; - parameter CLK_COR_SEQ_2_USE = "FALSE"; - parameter integer CLK_COR_SEQ_LEN = 2; - parameter [15:0] CPLL_CFG0 = 16'h20F8; - parameter [15:0] CPLL_CFG1 = 16'hA494; - parameter [15:0] CPLL_CFG2 = 16'hF001; - parameter [5:0] CPLL_CFG3 = 6'h00; - parameter integer CPLL_FBDIV = 4; - parameter integer CPLL_FBDIV_45 = 4; - parameter [15:0] CPLL_INIT_CFG0 = 16'h001E; - parameter [7:0] CPLL_INIT_CFG1 = 8'h00; - parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; - parameter integer CPLL_REFCLK_DIV = 1; - parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000; - parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0; - parameter [1:0] DDI_CTRL = 2'b00; - parameter integer DDI_REALIGN_WAIT = 15; - parameter DEC_MCOMMA_DETECT = "TRUE"; - parameter DEC_PCOMMA_DETECT = "TRUE"; - parameter DEC_VALID_COMMA_ONLY = "TRUE"; - parameter [0:0] DFE_D_X_REL_POS = 1'b0; - parameter [0:0] DFE_VCM_COMP_EN = 1'b0; - parameter [9:0] DMONITOR_CFG0 = 10'h000; - parameter [7:0] DMONITOR_CFG1 = 8'h00; - parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; - parameter [5:0] ES_CONTROL = 6'b000000; - parameter ES_ERRDET_EN = "FALSE"; - parameter ES_EYE_SCAN_EN = "FALSE"; - parameter [11:0] ES_HORZ_OFFSET = 12'h000; - parameter [9:0] ES_PMA_CFG = 10'b0000000000; - parameter [4:0] ES_PRESCALE = 5'b00000; - parameter [15:0] ES_QUALIFIER0 = 16'h0000; - parameter [15:0] ES_QUALIFIER1 = 16'h0000; - parameter [15:0] ES_QUALIFIER2 = 16'h0000; - parameter [15:0] ES_QUALIFIER3 = 16'h0000; - parameter [15:0] ES_QUALIFIER4 = 16'h0000; - parameter [15:0] ES_QUALIFIER5 = 16'h0000; - parameter [15:0] ES_QUALIFIER6 = 16'h0000; - parameter [15:0] ES_QUALIFIER7 = 16'h0000; - parameter [15:0] ES_QUALIFIER8 = 16'h0000; - parameter [15:0] ES_QUALIFIER9 = 16'h0000; - parameter [15:0] ES_QUAL_MASK0 = 16'h0000; - parameter [15:0] ES_QUAL_MASK1 = 16'h0000; - parameter [15:0] ES_QUAL_MASK2 = 16'h0000; - parameter [15:0] ES_QUAL_MASK3 = 16'h0000; - parameter [15:0] ES_QUAL_MASK4 = 16'h0000; - parameter [15:0] ES_QUAL_MASK5 = 16'h0000; - parameter [15:0] ES_QUAL_MASK6 = 16'h0000; - parameter [15:0] ES_QUAL_MASK7 = 16'h0000; - parameter [15:0] ES_QUAL_MASK8 = 16'h0000; - parameter [15:0] ES_QUAL_MASK9 = 16'h0000; - parameter [15:0] ES_SDATA_MASK0 = 16'h0000; - parameter [15:0] ES_SDATA_MASK1 = 16'h0000; - parameter [15:0] ES_SDATA_MASK2 = 16'h0000; - parameter [15:0] ES_SDATA_MASK3 = 16'h0000; - parameter [15:0] ES_SDATA_MASK4 = 16'h0000; - parameter [15:0] ES_SDATA_MASK5 = 16'h0000; - parameter [15:0] ES_SDATA_MASK6 = 16'h0000; - parameter [15:0] ES_SDATA_MASK7 = 16'h0000; - parameter [15:0] ES_SDATA_MASK8 = 16'h0000; - parameter [15:0] ES_SDATA_MASK9 = 16'h0000; - parameter [10:0] EVODD_PHI_CFG = 11'b00000000000; - parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0; - parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; - parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; - parameter FTS_LANE_DESKEW_EN = "FALSE"; - parameter [4:0] GEARBOX_MODE = 5'b00000; - parameter [0:0] GM_BIAS_SELECT = 1'b0; - parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0; - parameter [0:0] LOCAL_MASTER = 1'b0; - parameter [15:0] LOOP0_CFG = 16'h0000; - parameter [15:0] LOOP10_CFG = 16'h0000; - parameter [15:0] LOOP11_CFG = 16'h0000; - parameter [15:0] LOOP12_CFG = 16'h0000; - parameter [15:0] LOOP13_CFG = 16'h0000; - parameter [15:0] LOOP1_CFG = 16'h0000; - parameter [15:0] LOOP2_CFG = 16'h0000; - parameter [15:0] LOOP3_CFG = 16'h0000; - parameter [15:0] LOOP4_CFG = 16'h0000; - parameter [15:0] LOOP5_CFG = 16'h0000; - parameter [15:0] LOOP6_CFG = 16'h0000; - parameter [15:0] LOOP7_CFG = 16'h0000; - parameter [15:0] LOOP8_CFG = 16'h0000; - parameter [15:0] LOOP9_CFG = 16'h0000; - parameter [2:0] LPBK_BIAS_CTRL = 3'b000; - parameter [0:0] LPBK_EN_RCAL_B = 1'b0; - parameter [3:0] LPBK_EXT_RCAL = 4'b0000; - parameter [3:0] LPBK_RG_CTRL = 4'b0000; - parameter [1:0] OOBDIVCTL = 2'b00; - parameter [0:0] OOB_PWRUP = 1'b0; - parameter PCI3_AUTO_REALIGN = "FRST_SMPL"; - parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1; - parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00; - parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0; - parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000; - parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000; - parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000; - parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0; - parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0; - parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000; - parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000; - parameter [15:0] PCIE_RXPMA_CFG = 16'h0000; - parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000; - parameter [15:0] PCIE_TXPMA_CFG = 16'h0000; - parameter PCS_PCIE_EN = "FALSE"; - parameter [15:0] PCS_RSVD0 = 16'b0000000000000000; - parameter [2:0] PCS_RSVD1 = 3'b000; - parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; - parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; - parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; - parameter [1:0] PLL_SEL_MODE_GEN12 = 2'h0; - parameter [1:0] PLL_SEL_MODE_GEN3 = 2'h0; - parameter [15:0] PMA_RSV0 = 16'h0000; - parameter [15:0] PMA_RSV1 = 16'h0000; - parameter integer PREIQ_FREQ_BST = 0; - parameter [2:0] PROCESS_PAR = 3'b010; - parameter [0:0] RATE_SW_USE_DRP = 1'b0; - parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0; - parameter [4:0] RXBUFRESET_TIME = 5'b00001; - parameter RXBUF_ADDR_MODE = "FULL"; - parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; - parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; - parameter RXBUF_EN = "TRUE"; - parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; - parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; - parameter RXBUF_RESET_ON_EIDLE = "FALSE"; - parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; - parameter integer RXBUF_THRESH_OVFLW = 0; - parameter RXBUF_THRESH_OVRD = "FALSE"; - parameter integer RXBUF_THRESH_UNDFLW = 4; - parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; - parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; - parameter [15:0] RXCDR_CFG0 = 16'h0000; - parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0000; - parameter [15:0] RXCDR_CFG1 = 16'h0300; - parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0300; - parameter [15:0] RXCDR_CFG2 = 16'h0060; - parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0060; - parameter [15:0] RXCDR_CFG3 = 16'h0000; - parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0000; - parameter [15:0] RXCDR_CFG4 = 16'h0002; - parameter [15:0] RXCDR_CFG4_GEN3 = 16'h0002; - parameter [15:0] RXCDR_CFG5 = 16'h0000; - parameter [15:0] RXCDR_CFG5_GEN3 = 16'h0000; - parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; - parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; - parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0001; - parameter [15:0] RXCDR_LOCK_CFG1 = 16'h0000; - parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000; - parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000; - parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; - parameter [1:0] RXCFOKDONE_SRC = 2'b00; - parameter [15:0] RXCFOK_CFG0 = 16'h3E00; - parameter [15:0] RXCFOK_CFG1 = 16'h0042; - parameter [15:0] RXCFOK_CFG2 = 16'h002D; - parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; - parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000; - parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022; - parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100; - parameter [15:0] RXDFE_CFG0 = 16'h4C00; - parameter [15:0] RXDFE_CFG1 = 16'h0000; - parameter [15:0] RXDFE_GC_CFG0 = 16'h1E00; - parameter [15:0] RXDFE_GC_CFG1 = 16'h1900; - parameter [15:0] RXDFE_GC_CFG2 = 16'h0000; - parameter [15:0] RXDFE_H2_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H2_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H3_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H3_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H4_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H4_CFG1 = 16'h0003; - parameter [15:0] RXDFE_H5_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H5_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H6_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H6_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H7_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H7_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H8_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H8_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H9_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H9_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HA_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HA_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HB_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HB_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HC_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HC_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HD_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HD_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HE_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HE_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HF_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HF_CFG1 = 16'h0002; - parameter [15:0] RXDFE_OS_CFG0 = 16'h0000; - parameter [15:0] RXDFE_OS_CFG1 = 16'h0200; - parameter [0:0] RXDFE_PWR_SAVING = 1'b0; - parameter [15:0] RXDFE_UT_CFG0 = 16'h0000; - parameter [15:0] RXDFE_UT_CFG1 = 16'h0002; - parameter [15:0] RXDFE_VP_CFG0 = 16'h0000; - parameter [15:0] RXDFE_VP_CFG1 = 16'h0022; - parameter [15:0] RXDLY_CFG = 16'h001F; - parameter [15:0] RXDLY_LCFG = 16'h0030; - parameter RXELECIDLE_CFG = "SIGCFG_4"; - parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4; - parameter RXGEARBOX_EN = "FALSE"; - parameter [4:0] RXISCANRESET_TIME = 5'b00001; - parameter [15:0] RXLPM_CFG = 16'h0000; - parameter [15:0] RXLPM_GC_CFG = 16'h0200; - parameter [15:0] RXLPM_KH_CFG0 = 16'h0000; - parameter [15:0] RXLPM_KH_CFG1 = 16'h0002; - parameter [15:0] RXLPM_OS_CFG0 = 16'h0400; - parameter [15:0] RXLPM_OS_CFG1 = 16'h0000; - parameter [8:0] RXOOB_CFG = 9'b000000110; - parameter RXOOB_CLK_CFG = "PMA"; - parameter [4:0] RXOSCALRESET_TIME = 5'b00011; - parameter integer RXOUT_DIV = 4; - parameter [4:0] RXPCSRESET_TIME = 5'b00001; - parameter [15:0] RXPHBEACON_CFG = 16'h0000; - parameter [15:0] RXPHDLY_CFG = 16'h2020; - parameter [15:0] RXPHSAMP_CFG = 16'h2100; - parameter [15:0] RXPHSLIP_CFG = 16'h9933; - parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; - parameter [0:0] RXPI_AUTO_BW_SEL_BYPASS = 1'b0; - parameter [15:0] RXPI_CFG = 16'h0100; - parameter [0:0] RXPI_LPM = 1'b0; - parameter [15:0] RXPI_RSV0 = 16'h0000; - parameter [1:0] RXPI_SEL_LC = 2'b00; - parameter [1:0] RXPI_STARTCODE = 2'b00; - parameter [0:0] RXPI_VREFSEL = 1'b0; - parameter RXPMACLK_SEL = "DATA"; - parameter [4:0] RXPMARESET_TIME = 5'b00001; - parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; - parameter integer RXPRBS_LINKACQ_CNT = 15; - parameter integer RXSLIDE_AUTO_WAIT = 7; - parameter RXSLIDE_MODE = "OFF"; - parameter [0:0] RXSYNC_MULTILANE = 1'b0; - parameter [0:0] RXSYNC_OVRD = 1'b0; - parameter [0:0] RXSYNC_SKIP_DA = 1'b0; - parameter [0:0] RX_AFE_CM_EN = 1'b0; - parameter [15:0] RX_BIAS_CFG0 = 16'h1534; - parameter [5:0] RX_BUFFER_CFG = 6'b000000; - parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0; - parameter integer RX_CLK25_DIV = 8; - parameter [0:0] RX_CLKMUX_EN = 1'b1; - parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000; - parameter [3:0] RX_CM_BUF_CFG = 4'b1010; - parameter [0:0] RX_CM_BUF_PD = 1'b0; - parameter integer RX_CM_SEL = 3; - parameter integer RX_CM_TRIM = 10; - parameter [0:0] RX_CTLE1_KHKL = 1'b0; - parameter [0:0] RX_CTLE2_KHKL = 1'b0; - parameter [0:0] RX_CTLE3_AGC = 1'b0; - parameter integer RX_DATA_WIDTH = 20; - parameter [5:0] RX_DDI_SEL = 6'b000000; - parameter RX_DEFER_RESET_BUF_EN = "TRUE"; - parameter [2:0] RX_DEGEN_CTRL = 3'b010; - parameter integer RX_DFELPM_CFG0 = 6; - parameter [0:0] RX_DFELPM_CFG1 = 1'b0; - parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1; - parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00; - parameter integer RX_DFE_AGC_CFG1 = 4; - parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1; - parameter integer RX_DFE_KL_LPM_KH_CFG1 = 2; - parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01; - parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010; - parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; - parameter RX_DISPERR_SEQ_MATCH = "TRUE"; - parameter [0:0] RX_DIV2_MODE_B = 1'b0; - parameter [4:0] RX_DIVRESET_TIME = 5'b00001; - parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0; - parameter [0:0] RX_EN_HI_LR = 1'b0; - parameter [8:0] RX_EXT_RL_CTRL = 9'b000000000; - parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000; - parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0; - parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00; - parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0; - parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0; - parameter integer RX_INT_DATAWIDTH = 1; - parameter [0:0] RX_PMA_POWER_SAVE = 1'b0; - parameter real RX_PROGDIV_CFG = 0.0; - parameter [15:0] RX_PROGDIV_RATE = 16'h0001; - parameter [3:0] RX_RESLOAD_CTRL = 4'b0000; - parameter [0:0] RX_RESLOAD_OVRD = 1'b0; - parameter [2:0] RX_SAMPLE_PERIOD = 3'b101; - parameter integer RX_SIG_VALID_DLY = 11; - parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0; - parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000; - parameter [3:0] RX_SUM_VCMTUNE = 4'b1000; - parameter [0:0] RX_SUM_VCM_OVWR = 1'b0; - parameter [2:0] RX_SUM_VREF_TUNE = 3'b100; - parameter [1:0] RX_TUNE_AFE_OS = 2'b00; - parameter [2:0] RX_VREG_CTRL = 3'b101; - parameter [0:0] RX_VREG_PDB = 1'b1; - parameter [1:0] RX_WIDEMODE_CDR = 2'b01; - parameter RX_XCLK_SEL = "RXDES"; - parameter [0:0] RX_XMODE_SEL = 1'b0; - parameter integer SAS_MAX_COM = 64; - parameter integer SAS_MIN_COM = 36; - parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; - parameter [2:0] SATA_BURST_VAL = 3'b100; - parameter SATA_CPLL_CFG = "VCO_3000MHZ"; - parameter [2:0] SATA_EIDLE_VAL = 3'b100; - parameter integer SATA_MAX_BURST = 8; - parameter integer SATA_MAX_INIT = 21; - parameter integer SATA_MAX_WAKE = 7; - parameter integer SATA_MIN_BURST = 4; - parameter integer SATA_MIN_INIT = 12; - parameter integer SATA_MIN_WAKE = 4; - parameter SHOW_REALIGN_COMMA = "TRUE"; - parameter SIM_MODE = "FAST"; - parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter [0:0] SIM_TX_EIDLE_DRIVE_LEVEL = 1'b0; - parameter integer SIM_VERSION = 2; - parameter [1:0] TAPDLY_SET_TX = 2'h0; - parameter [3:0] TEMPERATURE_PAR = 4'b0010; - parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; - parameter [2:0] TERM_RCAL_OVRD = 3'b000; - parameter [7:0] TRANS_TIME_RATE = 8'h0E; - parameter [7:0] TST_RSV0 = 8'h00; - parameter [7:0] TST_RSV1 = 8'h00; - parameter TXBUF_EN = "TRUE"; - parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; - parameter [15:0] TXDLY_CFG = 16'h001F; - parameter [15:0] TXDLY_LCFG = 16'h0030; - parameter TXFIFO_ADDR_CFG = "LOW"; - parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4; - parameter TXGEARBOX_EN = "FALSE"; - parameter integer TXOUT_DIV = 4; - parameter [4:0] TXPCSRESET_TIME = 5'b00001; - parameter [15:0] TXPHDLY_CFG0 = 16'h2020; - parameter [15:0] TXPHDLY_CFG1 = 16'h0001; - parameter [15:0] TXPH_CFG = 16'h0123; - parameter [15:0] TXPH_CFG2 = 16'h0000; - parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; - parameter [1:0] TXPI_CFG0 = 2'b00; - parameter [1:0] TXPI_CFG1 = 2'b00; - parameter [1:0] TXPI_CFG2 = 2'b00; - parameter [0:0] TXPI_CFG3 = 1'b0; - parameter [0:0] TXPI_CFG4 = 1'b1; - parameter [2:0] TXPI_CFG5 = 3'b000; - parameter [0:0] TXPI_GRAY_SEL = 1'b0; - parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; - parameter [0:0] TXPI_LPM = 1'b0; - parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; - parameter [7:0] TXPI_PPM_CFG = 8'b00000000; - parameter [15:0] TXPI_RSV0 = 16'h0000; - parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; - parameter [0:0] TXPI_VREFSEL = 1'b0; - parameter [4:0] TXPMARESET_TIME = 5'b00001; - parameter [0:0] TXSYNC_MULTILANE = 1'b0; - parameter [0:0] TXSYNC_OVRD = 1'b0; - parameter [0:0] TXSYNC_SKIP_DA = 1'b0; - parameter integer TX_CLK25_DIV = 8; - parameter [0:0] TX_CLKMUX_EN = 1'b1; - parameter [0:0] TX_CLKREG_PDB = 1'b0; - parameter [2:0] TX_CLKREG_SET = 3'b000; - parameter integer TX_DATA_WIDTH = 20; - parameter [5:0] TX_DCD_CFG = 6'b000010; - parameter [0:0] TX_DCD_EN = 1'b0; - parameter [5:0] TX_DEEMPH0 = 6'b000000; - parameter [5:0] TX_DEEMPH1 = 6'b000000; - parameter [4:0] TX_DIVRESET_TIME = 5'b00001; - parameter TX_DRIVE_MODE = "DIRECT"; - parameter integer TX_DRVMUX_CTRL = 2; - parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; - parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; - parameter [0:0] TX_EML_PHI_TUNE = 1'b0; - parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0; - parameter [0:0] TX_FIFO_BYP_EN = 1'b0; - parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0; - parameter integer TX_INT_DATAWIDTH = 1; - parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; - parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; - parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; - parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; - parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; - parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; - parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; - parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; - parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; - parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; - parameter [2:0] TX_MODE_SEL = 3'b000; - parameter [15:0] TX_PHICAL_CFG0 = 16'h0000; - parameter [15:0] TX_PHICAL_CFG1 = 16'h7E00; - parameter [15:0] TX_PHICAL_CFG2 = 16'h0000; - parameter integer TX_PI_BIASSET = 0; - parameter [15:0] TX_PI_CFG0 = 16'h0000; - parameter [15:0] TX_PI_CFG1 = 16'h0000; - parameter [0:0] TX_PI_DIV2_MODE_B = 1'b0; - parameter [0:0] TX_PI_SEL_QPLL0 = 1'b0; - parameter [0:0] TX_PI_SEL_QPLL1 = 1'b0; - parameter [0:0] TX_PMADATA_OPT = 1'b0; - parameter [0:0] TX_PMA_POWER_SAVE = 1'b0; - parameter integer TX_PREDRV_CTRL = 2; - parameter TX_PROGCLK_SEL = "POSTPI"; - parameter real TX_PROGDIV_CFG = 0.0; - parameter [15:0] TX_PROGDIV_RATE = 16'h0001; - parameter [13:0] TX_RXDETECT_CFG = 14'h0032; - parameter integer TX_RXDETECT_REF = 4; - parameter [2:0] TX_SAMPLE_PERIOD = 3'b101; - parameter [0:0] TX_SARC_LPBK_ENB = 1'b0; - parameter TX_XCLK_SEL = "TXOUT"; - parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; - output [2:0] BUFGTCE; - output [2:0] BUFGTCEMASK; - output [8:0] BUFGTDIV; - output [2:0] BUFGTRESET; - output [2:0] BUFGTRSTMASK; - output CPLLFBCLKLOST; - output CPLLLOCK; - output CPLLREFCLKLOST; - output [16:0] DMONITOROUT; - output [15:0] DRPDO; - output DRPRDY; - output EYESCANDATAERROR; - output GTPOWERGOOD; - output GTREFCLKMONITOR; - output GTYTXN; - output GTYTXP; - output PCIERATEGEN3; - output PCIERATEIDLE; - output [1:0] PCIERATEQPLLPD; - output [1:0] PCIERATEQPLLRESET; - output PCIESYNCTXSYNCDONE; - output PCIEUSERGEN3RDY; - output PCIEUSERPHYSTATUSRST; - output PCIEUSERRATESTART; - output [15:0] PCSRSVDOUT; - output PHYSTATUS; - output [7:0] PINRSRVDAS; - output RESETEXCEPTION; - output [2:0] RXBUFSTATUS; - output RXBYTEISALIGNED; - output RXBYTEREALIGN; - output RXCDRLOCK; - output RXCDRPHDONE; - output RXCHANBONDSEQ; - output RXCHANISALIGNED; - output RXCHANREALIGN; - output [4:0] RXCHBONDO; - output RXCKCALDONE; - output [1:0] RXCLKCORCNT; - output RXCOMINITDET; - output RXCOMMADET; - output RXCOMSASDET; - output RXCOMWAKEDET; - output [15:0] RXCTRL0; - output [15:0] RXCTRL1; - output [7:0] RXCTRL2; - output [7:0] RXCTRL3; - output [127:0] RXDATA; - output [7:0] RXDATAEXTENDRSVD; - output [1:0] RXDATAVALID; - output RXDLYSRESETDONE; - output RXELECIDLE; - output [5:0] RXHEADER; - output [1:0] RXHEADERVALID; - output [6:0] RXMONITOROUT; - output RXOSINTDONE; - output RXOSINTSTARTED; - output RXOSINTSTROBEDONE; - output RXOSINTSTROBESTARTED; - output RXOUTCLK; - output RXOUTCLKFABRIC; - output RXOUTCLKPCS; - output RXPHALIGNDONE; - output RXPHALIGNERR; - output RXPMARESETDONE; - output RXPRBSERR; - output RXPRBSLOCKED; - output RXPRGDIVRESETDONE; - output RXRATEDONE; - output RXRECCLKOUT; - output RXRESETDONE; - output RXSLIDERDY; - output RXSLIPDONE; - output RXSLIPOUTCLKRDY; - output RXSLIPPMARDY; - output [1:0] RXSTARTOFSEQ; - output [2:0] RXSTATUS; - output RXSYNCDONE; - output RXSYNCOUT; - output RXVALID; - output [1:0] TXBUFSTATUS; - output TXCOMFINISH; - output TXDCCDONE; - output TXDLYSRESETDONE; - output TXOUTCLK; - output TXOUTCLKFABRIC; - output TXOUTCLKPCS; - output TXPHALIGNDONE; - output TXPHINITDONE; - output TXPMARESETDONE; - output TXPRGDIVRESETDONE; - output TXRATEDONE; - output TXRESETDONE; - output TXSYNCDONE; - output TXSYNCOUT; - input CDRSTEPDIR; - input CDRSTEPSQ; - input CDRSTEPSX; - input CFGRESET; - input CLKRSVD0; - input CLKRSVD1; - input CPLLLOCKDETCLK; - input CPLLLOCKEN; - input CPLLPD; - input [2:0] CPLLREFCLKSEL; - input CPLLRESET; - input DMONFIFORESET; - input DMONITORCLK; - input [9:0] DRPADDR; - input DRPCLK; - input [15:0] DRPDI; - input DRPEN; - input DRPWE; - input ELPCALDVORWREN; - input ELPCALPAORWREN; - input EVODDPHICALDONE; - input EVODDPHICALSTART; - input EVODDPHIDRDEN; - input EVODDPHIDWREN; - input EVODDPHIXRDEN; - input EVODDPHIXWREN; - input EYESCANMODE; - input EYESCANRESET; - input EYESCANTRIGGER; - input GTGREFCLK; - input GTNORTHREFCLK0; - input GTNORTHREFCLK1; - input GTREFCLK0; - input GTREFCLK1; - input GTRESETSEL; - input [15:0] GTRSVD; - input GTRXRESET; - input GTSOUTHREFCLK0; - input GTSOUTHREFCLK1; - input GTTXRESET; - input GTYRXN; - input GTYRXP; - input [2:0] LOOPBACK; - input [15:0] LOOPRSVD; - input LPBKRXTXSEREN; - input LPBKTXRXSEREN; - input PCIEEQRXEQADAPTDONE; - input PCIERSTIDLE; - input PCIERSTTXSYNCSTART; - input PCIEUSERRATEDONE; - input [15:0] PCSRSVDIN; - input [4:0] PCSRSVDIN2; - input [4:0] PMARSVDIN; - input QPLL0CLK; - input QPLL0REFCLK; - input QPLL1CLK; - input QPLL1REFCLK; - input RESETOVRD; - input RSTCLKENTX; - input RX8B10BEN; - input RXBUFRESET; - input RXCDRFREQRESET; - input RXCDRHOLD; - input RXCDROVRDEN; - input RXCDRRESET; - input RXCDRRESETRSV; - input RXCHBONDEN; - input [4:0] RXCHBONDI; - input [2:0] RXCHBONDLEVEL; - input RXCHBONDMASTER; - input RXCHBONDSLAVE; - input RXCKCALRESET; - input RXCOMMADETEN; - input RXDCCFORCESTART; - input RXDFEAGCHOLD; - input RXDFEAGCOVRDEN; - input RXDFELFHOLD; - input RXDFELFOVRDEN; - input RXDFELPMRESET; - input RXDFETAP10HOLD; - input RXDFETAP10OVRDEN; - input RXDFETAP11HOLD; - input RXDFETAP11OVRDEN; - input RXDFETAP12HOLD; - input RXDFETAP12OVRDEN; - input RXDFETAP13HOLD; - input RXDFETAP13OVRDEN; - input RXDFETAP14HOLD; - input RXDFETAP14OVRDEN; - input RXDFETAP15HOLD; - input RXDFETAP15OVRDEN; - input RXDFETAP2HOLD; - input RXDFETAP2OVRDEN; - input RXDFETAP3HOLD; - input RXDFETAP3OVRDEN; - input RXDFETAP4HOLD; - input RXDFETAP4OVRDEN; - input RXDFETAP5HOLD; - input RXDFETAP5OVRDEN; - input RXDFETAP6HOLD; - input RXDFETAP6OVRDEN; - input RXDFETAP7HOLD; - input RXDFETAP7OVRDEN; - input RXDFETAP8HOLD; - input RXDFETAP8OVRDEN; - input RXDFETAP9HOLD; - input RXDFETAP9OVRDEN; - input RXDFEUTHOLD; - input RXDFEUTOVRDEN; - input RXDFEVPHOLD; - input RXDFEVPOVRDEN; - input RXDFEVSEN; - input RXDFEXYDEN; - input RXDLYBYPASS; - input RXDLYEN; - input RXDLYOVRDEN; - input RXDLYSRESET; - input [1:0] RXELECIDLEMODE; - input RXGEARBOXSLIP; - input RXLATCLK; - input RXLPMEN; - input RXLPMGCHOLD; - input RXLPMGCOVRDEN; - input RXLPMHFHOLD; - input RXLPMHFOVRDEN; - input RXLPMLFHOLD; - input RXLPMLFKLOVRDEN; - input RXLPMOSHOLD; - input RXLPMOSOVRDEN; - input RXMCOMMAALIGNEN; - input [1:0] RXMONITORSEL; - input RXOOBRESET; - input RXOSCALRESET; - input RXOSHOLD; - input [3:0] RXOSINTCFG; - input RXOSINTEN; - input RXOSINTHOLD; - input RXOSINTOVRDEN; - input RXOSINTSTROBE; - input RXOSINTTESTOVRDEN; - input RXOSOVRDEN; - input [2:0] RXOUTCLKSEL; - input RXPCOMMAALIGNEN; - input RXPCSRESET; - input [1:0] RXPD; - input RXPHALIGN; - input RXPHALIGNEN; - input RXPHDLYPD; - input RXPHDLYRESET; - input RXPHOVRDEN; - input [1:0] RXPLLCLKSEL; - input RXPMARESET; - input RXPOLARITY; - input RXPRBSCNTRESET; - input [3:0] RXPRBSSEL; - input RXPROGDIVRESET; - input [2:0] RXRATE; - input RXRATEMODE; - input RXSLIDE; - input RXSLIPOUTCLK; - input RXSLIPPMA; - input RXSYNCALLIN; - input RXSYNCIN; - input RXSYNCMODE; - input [1:0] RXSYSCLKSEL; - input RXUSERRDY; - input RXUSRCLK; - input RXUSRCLK2; - input SIGVALIDCLK; - input [19:0] TSTIN; - input [7:0] TX8B10BBYPASS; - input TX8B10BEN; - input [2:0] TXBUFDIFFCTRL; - input TXCOMINIT; - input TXCOMSAS; - input TXCOMWAKE; - input [15:0] TXCTRL0; - input [15:0] TXCTRL1; - input [7:0] TXCTRL2; - input [127:0] TXDATA; - input [7:0] TXDATAEXTENDRSVD; - input TXDCCFORCESTART; - input TXDCCRESET; - input TXDEEMPH; - input TXDETECTRX; - input [4:0] TXDIFFCTRL; - input TXDIFFPD; - input TXDLYBYPASS; - input TXDLYEN; - input TXDLYHOLD; - input TXDLYOVRDEN; - input TXDLYSRESET; - input TXDLYUPDOWN; - input TXELECIDLE; - input TXELFORCESTART; - input [5:0] TXHEADER; - input TXINHIBIT; - input TXLATCLK; - input [6:0] TXMAINCURSOR; - input [2:0] TXMARGIN; - input [2:0] TXOUTCLKSEL; - input TXPCSRESET; - input [1:0] TXPD; - input TXPDELECIDLEMODE; - input TXPHALIGN; - input TXPHALIGNEN; - input TXPHDLYPD; - input TXPHDLYRESET; - input TXPHDLYTSTCLK; - input TXPHINIT; - input TXPHOVRDEN; - input TXPIPPMEN; - input TXPIPPMOVRDEN; - input TXPIPPMPD; - input TXPIPPMSEL; - input [4:0] TXPIPPMSTEPSIZE; - input TXPISOPD; - input [1:0] TXPLLCLKSEL; - input TXPMARESET; - input TXPOLARITY; - input [4:0] TXPOSTCURSOR; - input TXPRBSFORCEERR; - input [3:0] TXPRBSSEL; - input [4:0] TXPRECURSOR; - input TXPROGDIVRESET; - input [2:0] TXRATE; - input TXRATEMODE; - input [6:0] TXSEQUENCE; - input TXSWING; - input TXSYNCALLIN; - input TXSYNCIN; - input TXSYNCMODE; - input [1:0] TXSYSCLKSEL; - input TXUSERRDY; - input TXUSRCLK; - input TXUSRCLK2; -endmodule - -module GTYE3_COMMON (...); - parameter [15:0] A_SDM1DATA1_0 = 16'b0000000000000000; - parameter [8:0] A_SDM1DATA1_1 = 9'b000000000; - parameter [15:0] BIAS_CFG0 = 16'h0000; - parameter [15:0] BIAS_CFG1 = 16'h0000; - parameter [15:0] BIAS_CFG2 = 16'h0000; - parameter [15:0] BIAS_CFG3 = 16'h0000; - parameter [15:0] BIAS_CFG4 = 16'h0000; - parameter [9:0] BIAS_CFG_RSVD = 10'b0000000000; - parameter [15:0] COMMON_CFG0 = 16'h0000; - parameter [15:0] COMMON_CFG1 = 16'h0000; - parameter [15:0] POR_CFG = 16'h0004; - parameter [15:0] PPF0_CFG = 16'h0FFF; - parameter [15:0] PPF1_CFG = 16'h0FFF; - parameter QPLL0CLKOUT_RATE = "FULL"; - parameter [15:0] QPLL0_CFG0 = 16'h301C; - parameter [15:0] QPLL0_CFG1 = 16'h0000; - parameter [15:0] QPLL0_CFG1_G3 = 16'h0020; - parameter [15:0] QPLL0_CFG2 = 16'h0780; - parameter [15:0] QPLL0_CFG2_G3 = 16'h0780; - parameter [15:0] QPLL0_CFG3 = 16'h0120; - parameter [15:0] QPLL0_CFG4 = 16'h0021; - parameter [9:0] QPLL0_CP = 10'b0000011111; - parameter [9:0] QPLL0_CP_G3 = 10'b0000011111; - parameter integer QPLL0_FBDIV = 66; - parameter integer QPLL0_FBDIV_G3 = 80; - parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000; - parameter [7:0] QPLL0_INIT_CFG1 = 8'h00; - parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8; - parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8; - parameter [9:0] QPLL0_LPF = 10'b1111111111; - parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111; - parameter integer QPLL0_REFCLK_DIV = 2; - parameter [15:0] QPLL0_SDM_CFG0 = 16'h0040; - parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000; - parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000; - parameter QPLL1CLKOUT_RATE = "FULL"; - parameter [15:0] QPLL1_CFG0 = 16'h301C; - parameter [15:0] QPLL1_CFG1 = 16'h0000; - parameter [15:0] QPLL1_CFG1_G3 = 16'h0020; - parameter [15:0] QPLL1_CFG2 = 16'h0780; - parameter [15:0] QPLL1_CFG2_G3 = 16'h0780; - parameter [15:0] QPLL1_CFG3 = 16'h0120; - parameter [15:0] QPLL1_CFG4 = 16'h0021; - parameter [9:0] QPLL1_CP = 10'b0000011111; - parameter [9:0] QPLL1_CP_G3 = 10'b0000011111; - parameter integer QPLL1_FBDIV = 66; - parameter integer QPLL1_FBDIV_G3 = 80; - parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000; - parameter [7:0] QPLL1_INIT_CFG1 = 8'h00; - parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8; - parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8; - parameter [9:0] QPLL1_LPF = 10'b1111111111; - parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111; - parameter integer QPLL1_REFCLK_DIV = 2; - parameter [15:0] QPLL1_SDM_CFG0 = 16'h0040; - parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000; - parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000; - parameter [15:0] RSVD_ATTR0 = 16'h0000; - parameter [15:0] RSVD_ATTR1 = 16'h0000; - parameter [15:0] RSVD_ATTR2 = 16'h0000; - parameter [15:0] RSVD_ATTR3 = 16'h0000; - parameter [1:0] RXRECCLKOUT0_SEL = 2'b00; - parameter [1:0] RXRECCLKOUT1_SEL = 2'b00; - parameter [0:0] SARC_EN = 1'b1; - parameter [0:0] SARC_SEL = 1'b0; - parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000; - parameter [8:0] SDM0INITSEED0_1 = 9'b000000000; - parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000; - parameter [8:0] SDM1INITSEED0_1 = 9'b000000000; - parameter SIM_MODE = "FAST"; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter integer SIM_VERSION = 2; - output [15:0] DRPDO; - output DRPRDY; - output [7:0] PMARSVDOUT0; - output [7:0] PMARSVDOUT1; - output QPLL0FBCLKLOST; - output QPLL0LOCK; - output QPLL0OUTCLK; - output QPLL0OUTREFCLK; - output QPLL0REFCLKLOST; - output QPLL1FBCLKLOST; - output QPLL1LOCK; - output QPLL1OUTCLK; - output QPLL1OUTREFCLK; - output QPLL1REFCLKLOST; - output [7:0] QPLLDMONITOR0; - output [7:0] QPLLDMONITOR1; - output REFCLKOUTMONITOR0; - output REFCLKOUTMONITOR1; - output [1:0] RXRECCLK0_SEL; - output [1:0] RXRECCLK1_SEL; - output [3:0] SDM0FINALOUT; - output [14:0] SDM0TESTDATA; - output [3:0] SDM1FINALOUT; - output [14:0] SDM1TESTDATA; - input BGBYPASSB; - input BGMONITORENB; - input BGPDB; - input [4:0] BGRCALOVRD; - input BGRCALOVRDENB; - input [9:0] DRPADDR; - input DRPCLK; - input [15:0] DRPDI; - input DRPEN; - input DRPWE; - input GTGREFCLK0; - input GTGREFCLK1; - input GTNORTHREFCLK00; - input GTNORTHREFCLK01; - input GTNORTHREFCLK10; - input GTNORTHREFCLK11; - input GTREFCLK00; - input GTREFCLK01; - input GTREFCLK10; - input GTREFCLK11; - input GTSOUTHREFCLK00; - input GTSOUTHREFCLK01; - input GTSOUTHREFCLK10; - input GTSOUTHREFCLK11; - input [7:0] PMARSVD0; - input [7:0] PMARSVD1; - input QPLL0CLKRSVD0; - input QPLL0LOCKDETCLK; - input QPLL0LOCKEN; - input QPLL0PD; - input [2:0] QPLL0REFCLKSEL; - input QPLL0RESET; - input QPLL1CLKRSVD0; - input QPLL1LOCKDETCLK; - input QPLL1LOCKEN; - input QPLL1PD; - input [2:0] QPLL1REFCLKSEL; - input QPLL1RESET; - input [7:0] QPLLRSVD1; - input [4:0] QPLLRSVD2; - input [4:0] QPLLRSVD3; - input [7:0] QPLLRSVD4; - input RCALENB; - input [24:0] SDM0DATA; - input SDM0RESET; - input [1:0] SDM0WIDTH; - input [24:0] SDM1DATA; - input SDM1RESET; - input [1:0] SDM1WIDTH; -endmodule - -module IBUFDS_GTE3 (...); - parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; - parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00; - parameter [1:0] REFCLK_ICNTL_RX = 2'b00; - output O; - output ODIV2; - input CEB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module OBUFDS_GTE3 (...); - parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; - parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; - (* iopad_external_pin *) - output O; - (* iopad_external_pin *) - output OB; - input CEB; - input I; -endmodule - -module OBUFDS_GTE3_ADV (...); - parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; - parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; - (* iopad_external_pin *) - output O; - (* iopad_external_pin *) - output OB; - input CEB; - input [3:0] I; - input [1:0] RXRECCLK_SEL; -endmodule - -module GTHE4_CHANNEL (...); - parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; - parameter [0:0] ACJTAG_MODE = 1'b0; - parameter [0:0] ACJTAG_RESET = 1'b0; - parameter [15:0] ADAPT_CFG0 = 16'h9200; - parameter [15:0] ADAPT_CFG1 = 16'h801C; - parameter [15:0] ADAPT_CFG2 = 16'h0000; - parameter ALIGN_COMMA_DOUBLE = "FALSE"; - parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; - parameter integer ALIGN_COMMA_WORD = 1; - parameter ALIGN_MCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; - parameter ALIGN_PCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; - parameter [0:0] A_RXOSCALRESET = 1'b0; - parameter [0:0] A_RXPROGDIVRESET = 1'b0; - parameter [0:0] A_RXTERMINATION = 1'b1; - parameter [4:0] A_TXDIFFCTRL = 5'b01100; - parameter [0:0] A_TXPROGDIVRESET = 1'b0; - parameter [0:0] CAPBYPASS_FORCE = 1'b0; - parameter CBCC_DATA_SOURCE_SEL = "DECODED"; - parameter [0:0] CDR_SWAP_MODE_EN = 1'b0; - parameter [0:0] CFOK_PWRSVE_EN = 1'b1; - parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; - parameter integer CHAN_BOND_MAX_SKEW = 7; - parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; - parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; - parameter CHAN_BOND_SEQ_2_USE = "FALSE"; - parameter integer CHAN_BOND_SEQ_LEN = 2; - parameter [15:0] CH_HSPMUX = 16'h2424; - parameter [15:0] CKCAL1_CFG_0 = 16'b0000000000000000; - parameter [15:0] CKCAL1_CFG_1 = 16'b0000000000000000; - parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000; - parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_0 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_1 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000; - parameter [15:0] CKCAL_RSVD0 = 16'h4000; - parameter [15:0] CKCAL_RSVD1 = 16'h0000; - parameter CLK_CORRECT_USE = "TRUE"; - parameter CLK_COR_KEEP_IDLE = "FALSE"; - parameter integer CLK_COR_MAX_LAT = 20; - parameter integer CLK_COR_MIN_LAT = 18; - parameter CLK_COR_PRECEDENCE = "TRUE"; - parameter integer CLK_COR_REPEAT_WAIT = 0; - parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; - parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; - parameter CLK_COR_SEQ_2_USE = "FALSE"; - parameter integer CLK_COR_SEQ_LEN = 2; - parameter [15:0] CPLL_CFG0 = 16'h01FA; - parameter [15:0] CPLL_CFG1 = 16'h24A9; - parameter [15:0] CPLL_CFG2 = 16'h6807; - parameter [15:0] CPLL_CFG3 = 16'h0000; - parameter integer CPLL_FBDIV = 4; - parameter integer CPLL_FBDIV_45 = 4; - parameter [15:0] CPLL_INIT_CFG0 = 16'h001E; - parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; - parameter integer CPLL_REFCLK_DIV = 1; - parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000; - parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0; - parameter [1:0] DDI_CTRL = 2'b00; - parameter integer DDI_REALIGN_WAIT = 15; - parameter DEC_MCOMMA_DETECT = "TRUE"; - parameter DEC_PCOMMA_DETECT = "TRUE"; - parameter DEC_VALID_COMMA_ONLY = "TRUE"; - parameter [0:0] DELAY_ELEC = 1'b0; - parameter [9:0] DMONITOR_CFG0 = 10'h000; - parameter [7:0] DMONITOR_CFG1 = 8'h00; - parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; - parameter [5:0] ES_CONTROL = 6'b000000; - parameter ES_ERRDET_EN = "FALSE"; - parameter ES_EYE_SCAN_EN = "FALSE"; - parameter [11:0] ES_HORZ_OFFSET = 12'h800; - parameter [4:0] ES_PRESCALE = 5'b00000; - parameter [15:0] ES_QUALIFIER0 = 16'h0000; - parameter [15:0] ES_QUALIFIER1 = 16'h0000; - parameter [15:0] ES_QUALIFIER2 = 16'h0000; - parameter [15:0] ES_QUALIFIER3 = 16'h0000; - parameter [15:0] ES_QUALIFIER4 = 16'h0000; - parameter [15:0] ES_QUALIFIER5 = 16'h0000; - parameter [15:0] ES_QUALIFIER6 = 16'h0000; - parameter [15:0] ES_QUALIFIER7 = 16'h0000; - parameter [15:0] ES_QUALIFIER8 = 16'h0000; - parameter [15:0] ES_QUALIFIER9 = 16'h0000; - parameter [15:0] ES_QUAL_MASK0 = 16'h0000; - parameter [15:0] ES_QUAL_MASK1 = 16'h0000; - parameter [15:0] ES_QUAL_MASK2 = 16'h0000; - parameter [15:0] ES_QUAL_MASK3 = 16'h0000; - parameter [15:0] ES_QUAL_MASK4 = 16'h0000; - parameter [15:0] ES_QUAL_MASK5 = 16'h0000; - parameter [15:0] ES_QUAL_MASK6 = 16'h0000; - parameter [15:0] ES_QUAL_MASK7 = 16'h0000; - parameter [15:0] ES_QUAL_MASK8 = 16'h0000; - parameter [15:0] ES_QUAL_MASK9 = 16'h0000; - parameter [15:0] ES_SDATA_MASK0 = 16'h0000; - parameter [15:0] ES_SDATA_MASK1 = 16'h0000; - parameter [15:0] ES_SDATA_MASK2 = 16'h0000; - parameter [15:0] ES_SDATA_MASK3 = 16'h0000; - parameter [15:0] ES_SDATA_MASK4 = 16'h0000; - parameter [15:0] ES_SDATA_MASK5 = 16'h0000; - parameter [15:0] ES_SDATA_MASK6 = 16'h0000; - parameter [15:0] ES_SDATA_MASK7 = 16'h0000; - parameter [15:0] ES_SDATA_MASK8 = 16'h0000; - parameter [15:0] ES_SDATA_MASK9 = 16'h0000; - parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0; - parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; - parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; - parameter FTS_LANE_DESKEW_EN = "FALSE"; - parameter [4:0] GEARBOX_MODE = 5'b00000; - parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0; - parameter [0:0] LOCAL_MASTER = 1'b0; - parameter [2:0] LPBK_BIAS_CTRL = 3'b000; - parameter [0:0] LPBK_EN_RCAL_B = 1'b0; - parameter [3:0] LPBK_EXT_RCAL = 4'b0000; - parameter [2:0] LPBK_IND_CTRL0 = 3'b000; - parameter [2:0] LPBK_IND_CTRL1 = 3'b000; - parameter [2:0] LPBK_IND_CTRL2 = 3'b000; - parameter [3:0] LPBK_RG_CTRL = 4'b0000; - parameter [1:0] OOBDIVCTL = 2'b00; - parameter [0:0] OOB_PWRUP = 1'b0; - parameter PCI3_AUTO_REALIGN = "FRST_SMPL"; - parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1; - parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00; - parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0; - parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000; - parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000; - parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000; - parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0; - parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0; - parameter [4:0] PCIE3_CLK_COR_EMPTY_THRSH = 5'b00000; - parameter [5:0] PCIE3_CLK_COR_FULL_THRSH = 6'b010000; - parameter [4:0] PCIE3_CLK_COR_MAX_LAT = 5'b01000; - parameter [4:0] PCIE3_CLK_COR_MIN_LAT = 5'b00100; - parameter [5:0] PCIE3_CLK_COR_THRSH_TIMER = 6'b001000; - parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000; - parameter [1:0] PCIE_PLL_SEL_MODE_GEN12 = 2'h0; - parameter [1:0] PCIE_PLL_SEL_MODE_GEN3 = 2'h0; - parameter [1:0] PCIE_PLL_SEL_MODE_GEN4 = 2'h0; - parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000; - parameter [15:0] PCIE_RXPMA_CFG = 16'h0000; - parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000; - parameter [15:0] PCIE_TXPMA_CFG = 16'h0000; - parameter PCS_PCIE_EN = "FALSE"; - parameter [15:0] PCS_RSVD0 = 16'b0000000000000000; - parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; - parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; - parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; - parameter integer PREIQ_FREQ_BST = 0; - parameter [2:0] PROCESS_PAR = 3'b010; - parameter [0:0] RATE_SW_USE_DRP = 1'b0; - parameter [0:0] RCLK_SIPO_DLY_ENB = 1'b0; - parameter [0:0] RCLK_SIPO_INV_EN = 1'b0; - parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0; - parameter [2:0] RTX_BUF_CML_CTRL = 3'b010; - parameter [1:0] RTX_BUF_TERM_CTRL = 2'b00; - parameter [4:0] RXBUFRESET_TIME = 5'b00001; - parameter RXBUF_ADDR_MODE = "FULL"; - parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; - parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; - parameter RXBUF_EN = "TRUE"; - parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; - parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; - parameter RXBUF_RESET_ON_EIDLE = "FALSE"; - parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; - parameter integer RXBUF_THRESH_OVFLW = 0; - parameter RXBUF_THRESH_OVRD = "FALSE"; - parameter integer RXBUF_THRESH_UNDFLW = 4; - parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; - parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; - parameter [15:0] RXCDR_CFG0 = 16'h0003; - parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0003; - parameter [15:0] RXCDR_CFG1 = 16'h0000; - parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000; - parameter [15:0] RXCDR_CFG2 = 16'h0164; - parameter [9:0] RXCDR_CFG2_GEN2 = 10'h164; - parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0034; - parameter [15:0] RXCDR_CFG2_GEN4 = 16'h0034; - parameter [15:0] RXCDR_CFG3 = 16'h0024; - parameter [5:0] RXCDR_CFG3_GEN2 = 6'h24; - parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0024; - parameter [15:0] RXCDR_CFG3_GEN4 = 16'h0024; - parameter [15:0] RXCDR_CFG4 = 16'h5CF6; - parameter [15:0] RXCDR_CFG4_GEN3 = 16'h5CF6; - parameter [15:0] RXCDR_CFG5 = 16'hB46B; - parameter [15:0] RXCDR_CFG5_GEN3 = 16'h146B; - parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; - parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; - parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0040; - parameter [15:0] RXCDR_LOCK_CFG1 = 16'h8000; - parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000; - parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000; - parameter [15:0] RXCDR_LOCK_CFG4 = 16'h0000; - parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; - parameter [15:0] RXCFOK_CFG0 = 16'h0000; - parameter [15:0] RXCFOK_CFG1 = 16'h0002; - parameter [15:0] RXCFOK_CFG2 = 16'h002D; - parameter [15:0] RXCKCAL1_IQ_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL1_I_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL1_Q_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL2_DX_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL2_D_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL2_S_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL2_X_LOOP_RST_CFG = 16'h0000; - parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; - parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000; - parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022; - parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100; - parameter [15:0] RXDFE_CFG0 = 16'h4000; - parameter [15:0] RXDFE_CFG1 = 16'h0000; - parameter [15:0] RXDFE_GC_CFG0 = 16'h0000; - parameter [15:0] RXDFE_GC_CFG1 = 16'h0000; - parameter [15:0] RXDFE_GC_CFG2 = 16'h0000; - parameter [15:0] RXDFE_H2_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H2_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H3_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H3_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H4_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H4_CFG1 = 16'h0003; - parameter [15:0] RXDFE_H5_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H5_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H6_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H6_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H7_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H7_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H8_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H8_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H9_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H9_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HA_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HA_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HB_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HB_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HC_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HC_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HD_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HD_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HE_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HE_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HF_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HF_CFG1 = 16'h0002; - parameter [15:0] RXDFE_KH_CFG0 = 16'h0000; - parameter [15:0] RXDFE_KH_CFG1 = 16'h0000; - parameter [15:0] RXDFE_KH_CFG2 = 16'h0000; - parameter [15:0] RXDFE_KH_CFG3 = 16'h0000; - parameter [15:0] RXDFE_OS_CFG0 = 16'h0000; - parameter [15:0] RXDFE_OS_CFG1 = 16'h0002; - parameter [0:0] RXDFE_PWR_SAVING = 1'b0; - parameter [15:0] RXDFE_UT_CFG0 = 16'h0000; - parameter [15:0] RXDFE_UT_CFG1 = 16'h0002; - parameter [15:0] RXDFE_UT_CFG2 = 16'h0000; - parameter [15:0] RXDFE_VP_CFG0 = 16'h0000; - parameter [15:0] RXDFE_VP_CFG1 = 16'h0022; - parameter [15:0] RXDLY_CFG = 16'h0010; - parameter [15:0] RXDLY_LCFG = 16'h0030; - parameter RXELECIDLE_CFG = "SIGCFG_4"; - parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4; - parameter RXGEARBOX_EN = "FALSE"; - parameter [4:0] RXISCANRESET_TIME = 5'b00001; - parameter [15:0] RXLPM_CFG = 16'h0000; - parameter [15:0] RXLPM_GC_CFG = 16'h1000; - parameter [15:0] RXLPM_KH_CFG0 = 16'h0000; - parameter [15:0] RXLPM_KH_CFG1 = 16'h0002; - parameter [15:0] RXLPM_OS_CFG0 = 16'h0000; - parameter [15:0] RXLPM_OS_CFG1 = 16'h0000; - parameter [8:0] RXOOB_CFG = 9'b000110000; - parameter RXOOB_CLK_CFG = "PMA"; - parameter [4:0] RXOSCALRESET_TIME = 5'b00011; - parameter integer RXOUT_DIV = 4; - parameter [4:0] RXPCSRESET_TIME = 5'b00001; - parameter [15:0] RXPHBEACON_CFG = 16'h0000; - parameter [15:0] RXPHDLY_CFG = 16'h2020; - parameter [15:0] RXPHSAMP_CFG = 16'h2100; - parameter [15:0] RXPHSLIP_CFG = 16'h9933; - parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; - parameter [0:0] RXPI_AUTO_BW_SEL_BYPASS = 1'b0; - parameter [15:0] RXPI_CFG0 = 16'h0002; - parameter [15:0] RXPI_CFG1 = 16'b0000000000000000; - parameter [0:0] RXPI_LPM = 1'b0; - parameter [1:0] RXPI_SEL_LC = 2'b00; - parameter [1:0] RXPI_STARTCODE = 2'b00; - parameter [0:0] RXPI_VREFSEL = 1'b0; - parameter RXPMACLK_SEL = "DATA"; - parameter [4:0] RXPMARESET_TIME = 5'b00001; - parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; - parameter integer RXPRBS_LINKACQ_CNT = 15; - parameter [0:0] RXREFCLKDIV2_SEL = 1'b0; - parameter integer RXSLIDE_AUTO_WAIT = 7; - parameter RXSLIDE_MODE = "OFF"; - parameter [0:0] RXSYNC_MULTILANE = 1'b0; - parameter [0:0] RXSYNC_OVRD = 1'b0; - parameter [0:0] RXSYNC_SKIP_DA = 1'b0; - parameter [0:0] RX_AFE_CM_EN = 1'b0; - parameter [15:0] RX_BIAS_CFG0 = 16'h12B0; - parameter [5:0] RX_BUFFER_CFG = 6'b000000; - parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0; - parameter integer RX_CLK25_DIV = 8; - parameter [0:0] RX_CLKMUX_EN = 1'b1; - parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000; - parameter [3:0] RX_CM_BUF_CFG = 4'b1010; - parameter [0:0] RX_CM_BUF_PD = 1'b0; - parameter integer RX_CM_SEL = 3; - parameter integer RX_CM_TRIM = 12; - parameter [7:0] RX_CTLE3_LPF = 8'b00000000; - parameter integer RX_DATA_WIDTH = 20; - parameter [5:0] RX_DDI_SEL = 6'b000000; - parameter RX_DEFER_RESET_BUF_EN = "TRUE"; - parameter [2:0] RX_DEGEN_CTRL = 3'b011; - parameter integer RX_DFELPM_CFG0 = 0; - parameter [0:0] RX_DFELPM_CFG1 = 1'b1; - parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1; - parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00; - parameter integer RX_DFE_AGC_CFG1 = 4; - parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1; - parameter integer RX_DFE_KL_LPM_KH_CFG1 = 4; - parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01; - parameter integer RX_DFE_KL_LPM_KL_CFG1 = 4; - parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; - parameter RX_DISPERR_SEQ_MATCH = "TRUE"; - parameter [0:0] RX_DIV2_MODE_B = 1'b0; - parameter [4:0] RX_DIVRESET_TIME = 5'b00001; - parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0; - parameter [0:0] RX_EN_HI_LR = 1'b1; - parameter [8:0] RX_EXT_RL_CTRL = 9'b000000000; - parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000; - parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0; - parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00; - parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0; - parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0; - parameter integer RX_INT_DATAWIDTH = 1; - parameter [0:0] RX_PMA_POWER_SAVE = 1'b0; - parameter [15:0] RX_PMA_RSV0 = 16'h0000; - parameter real RX_PROGDIV_CFG = 0.0; - parameter [15:0] RX_PROGDIV_RATE = 16'h0001; - parameter [3:0] RX_RESLOAD_CTRL = 4'b0000; - parameter [0:0] RX_RESLOAD_OVRD = 1'b0; - parameter [2:0] RX_SAMPLE_PERIOD = 3'b101; - parameter integer RX_SIG_VALID_DLY = 11; - parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0; - parameter [3:0] RX_SUM_IREF_TUNE = 4'b1001; - parameter [3:0] RX_SUM_RESLOAD_CTRL = 4'b0000; - parameter [3:0] RX_SUM_VCMTUNE = 4'b1010; - parameter [0:0] RX_SUM_VCM_OVWR = 1'b0; - parameter [2:0] RX_SUM_VREF_TUNE = 3'b100; - parameter [1:0] RX_TUNE_AFE_OS = 2'b00; - parameter [2:0] RX_VREG_CTRL = 3'b101; - parameter [0:0] RX_VREG_PDB = 1'b1; - parameter [1:0] RX_WIDEMODE_CDR = 2'b01; - parameter [1:0] RX_WIDEMODE_CDR_GEN3 = 2'b01; - parameter [1:0] RX_WIDEMODE_CDR_GEN4 = 2'b01; - parameter RX_XCLK_SEL = "RXDES"; - parameter [0:0] RX_XMODE_SEL = 1'b0; - parameter [0:0] SAMPLE_CLK_PHASE = 1'b0; - parameter [0:0] SAS_12G_MODE = 1'b0; - parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; - parameter [2:0] SATA_BURST_VAL = 3'b100; - parameter SATA_CPLL_CFG = "VCO_3000MHZ"; - parameter [2:0] SATA_EIDLE_VAL = 3'b100; - parameter SHOW_REALIGN_COMMA = "TRUE"; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter SIM_MODE = "FAST"; - parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter SIM_TX_EIDLE_DRIVE_LEVEL = "Z"; - parameter [0:0] SRSTMODE = 1'b0; - parameter [1:0] TAPDLY_SET_TX = 2'h0; - parameter [3:0] TEMPERATURE_PAR = 4'b0010; - parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; - parameter [2:0] TERM_RCAL_OVRD = 3'b000; - parameter [7:0] TRANS_TIME_RATE = 8'h0E; - parameter [7:0] TST_RSV0 = 8'h00; - parameter [7:0] TST_RSV1 = 8'h00; - parameter TXBUF_EN = "TRUE"; - parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; - parameter [15:0] TXDLY_CFG = 16'h0010; - parameter [15:0] TXDLY_LCFG = 16'h0030; - parameter [3:0] TXDRVBIAS_N = 4'b1010; - parameter TXFIFO_ADDR_CFG = "LOW"; - parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4; - parameter TXGEARBOX_EN = "FALSE"; - parameter integer TXOUT_DIV = 4; - parameter [4:0] TXPCSRESET_TIME = 5'b00001; - parameter [15:0] TXPHDLY_CFG0 = 16'h6020; - parameter [15:0] TXPHDLY_CFG1 = 16'h0002; - parameter [15:0] TXPH_CFG = 16'h0123; - parameter [15:0] TXPH_CFG2 = 16'h0000; - parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; - parameter [15:0] TXPI_CFG = 16'h0000; - parameter [1:0] TXPI_CFG0 = 2'b00; - parameter [1:0] TXPI_CFG1 = 2'b00; - parameter [1:0] TXPI_CFG2 = 2'b00; - parameter [0:0] TXPI_CFG3 = 1'b0; - parameter [0:0] TXPI_CFG4 = 1'b1; - parameter [2:0] TXPI_CFG5 = 3'b000; - parameter [0:0] TXPI_GRAY_SEL = 1'b0; - parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; - parameter [0:0] TXPI_LPM = 1'b0; - parameter [0:0] TXPI_PPM = 1'b0; - parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; - parameter [7:0] TXPI_PPM_CFG = 8'b00000000; - parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; - parameter [0:0] TXPI_VREFSEL = 1'b0; - parameter [4:0] TXPMARESET_TIME = 5'b00001; - parameter [0:0] TXREFCLKDIV2_SEL = 1'b0; - parameter [0:0] TXSYNC_MULTILANE = 1'b0; - parameter [0:0] TXSYNC_OVRD = 1'b0; - parameter [0:0] TXSYNC_SKIP_DA = 1'b0; - parameter integer TX_CLK25_DIV = 8; - parameter [0:0] TX_CLKMUX_EN = 1'b1; - parameter integer TX_DATA_WIDTH = 20; - parameter [15:0] TX_DCC_LOOP_RST_CFG = 16'h0000; - parameter [5:0] TX_DEEMPH0 = 6'b000000; - parameter [5:0] TX_DEEMPH1 = 6'b000000; - parameter [5:0] TX_DEEMPH2 = 6'b000000; - parameter [5:0] TX_DEEMPH3 = 6'b000000; - parameter [4:0] TX_DIVRESET_TIME = 5'b00001; - parameter TX_DRIVE_MODE = "DIRECT"; - parameter integer TX_DRVMUX_CTRL = 2; - parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; - parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; - parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0; - parameter [0:0] TX_FIFO_BYP_EN = 1'b0; - parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0; - parameter integer TX_INT_DATAWIDTH = 1; - parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; - parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; - parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; - parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; - parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; - parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; - parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; - parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; - parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; - parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; - parameter [15:0] TX_PHICAL_CFG0 = 16'h0000; - parameter [15:0] TX_PHICAL_CFG1 = 16'h003F; - parameter [15:0] TX_PHICAL_CFG2 = 16'h0000; - parameter integer TX_PI_BIASSET = 0; - parameter [1:0] TX_PI_IBIAS_MID = 2'b00; - parameter [0:0] TX_PMADATA_OPT = 1'b0; - parameter [0:0] TX_PMA_POWER_SAVE = 1'b0; - parameter [15:0] TX_PMA_RSV0 = 16'h0008; - parameter integer TX_PREDRV_CTRL = 2; - parameter TX_PROGCLK_SEL = "POSTPI"; - parameter real TX_PROGDIV_CFG = 0.0; - parameter [15:0] TX_PROGDIV_RATE = 16'h0001; - parameter [0:0] TX_QPI_STATUS_EN = 1'b0; - parameter [13:0] TX_RXDETECT_CFG = 14'h0032; - parameter integer TX_RXDETECT_REF = 3; - parameter [2:0] TX_SAMPLE_PERIOD = 3'b101; - parameter [0:0] TX_SARC_LPBK_ENB = 1'b0; - parameter [1:0] TX_SW_MEAS = 2'b00; - parameter [2:0] TX_VREG_CTRL = 3'b000; - parameter [0:0] TX_VREG_PDB = 1'b0; - parameter [1:0] TX_VREG_VREFSEL = 2'b00; - parameter TX_XCLK_SEL = "TXOUT"; - parameter [0:0] USB_BOTH_BURST_IDLE = 1'b0; - parameter [6:0] USB_BURSTMAX_U3WAKE = 7'b1111111; - parameter [6:0] USB_BURSTMIN_U3WAKE = 7'b1100011; - parameter [0:0] USB_CLK_COR_EQ_EN = 1'b0; - parameter [0:0] USB_EXT_CNTL = 1'b1; - parameter [9:0] USB_IDLEMAX_POLLING = 10'b1010111011; - parameter [9:0] USB_IDLEMIN_POLLING = 10'b0100101011; - parameter [8:0] USB_LFPSPING_BURST = 9'b000000101; - parameter [8:0] USB_LFPSPOLLING_BURST = 9'b000110001; - parameter [8:0] USB_LFPSPOLLING_IDLE_MS = 9'b000000100; - parameter [8:0] USB_LFPSU1EXIT_BURST = 9'b000011101; - parameter [8:0] USB_LFPSU2LPEXIT_BURST_MS = 9'b001100011; - parameter [8:0] USB_LFPSU3WAKE_BURST_MS = 9'b111110011; - parameter [3:0] USB_LFPS_TPERIOD = 4'b0011; - parameter [0:0] USB_LFPS_TPERIOD_ACCURATE = 1'b1; - parameter [0:0] USB_MODE = 1'b0; - parameter [0:0] USB_PCIE_ERR_REP_DIS = 1'b0; - parameter integer USB_PING_SATA_MAX_INIT = 21; - parameter integer USB_PING_SATA_MIN_INIT = 12; - parameter integer USB_POLL_SATA_MAX_BURST = 8; - parameter integer USB_POLL_SATA_MIN_BURST = 4; - parameter [0:0] USB_RAW_ELEC = 1'b0; - parameter [0:0] USB_RXIDLE_P0_CTRL = 1'b1; - parameter [0:0] USB_TXIDLE_TUNE_ENABLE = 1'b1; - parameter integer USB_U1_SATA_MAX_WAKE = 7; - parameter integer USB_U1_SATA_MIN_WAKE = 4; - parameter integer USB_U2_SAS_MAX_COM = 64; - parameter integer USB_U2_SAS_MIN_COM = 36; - parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; - parameter [0:0] Y_ALL_MODE = 1'b0; - output BUFGTCE; - output [2:0] BUFGTCEMASK; - output [8:0] BUFGTDIV; - output BUFGTRESET; - output [2:0] BUFGTRSTMASK; - output CPLLFBCLKLOST; - output CPLLLOCK; - output CPLLREFCLKLOST; - output [15:0] DMONITOROUT; - output DMONITOROUTCLK; - output [15:0] DRPDO; - output DRPRDY; - output EYESCANDATAERROR; - output GTHTXN; - output GTHTXP; - output GTPOWERGOOD; - output GTREFCLKMONITOR; - output PCIERATEGEN3; - output PCIERATEIDLE; - output [1:0] PCIERATEQPLLPD; - output [1:0] PCIERATEQPLLRESET; - output PCIESYNCTXSYNCDONE; - output PCIEUSERGEN3RDY; - output PCIEUSERPHYSTATUSRST; - output PCIEUSERRATESTART; - output [15:0] PCSRSVDOUT; - output PHYSTATUS; - output [15:0] PINRSRVDAS; - output POWERPRESENT; - output RESETEXCEPTION; - output [2:0] RXBUFSTATUS; - output RXBYTEISALIGNED; - output RXBYTEREALIGN; - output RXCDRLOCK; - output RXCDRPHDONE; - output RXCHANBONDSEQ; - output RXCHANISALIGNED; - output RXCHANREALIGN; - output [4:0] RXCHBONDO; - output RXCKCALDONE; - output [1:0] RXCLKCORCNT; - output RXCOMINITDET; - output RXCOMMADET; - output RXCOMSASDET; - output RXCOMWAKEDET; - output [15:0] RXCTRL0; - output [15:0] RXCTRL1; - output [7:0] RXCTRL2; - output [7:0] RXCTRL3; - output [127:0] RXDATA; - output [7:0] RXDATAEXTENDRSVD; - output [1:0] RXDATAVALID; - output RXDLYSRESETDONE; - output RXELECIDLE; - output [5:0] RXHEADER; - output [1:0] RXHEADERVALID; - output RXLFPSTRESETDET; - output RXLFPSU2LPEXITDET; - output RXLFPSU3WAKEDET; - output [7:0] RXMONITOROUT; - output RXOSINTDONE; - output RXOSINTSTARTED; - output RXOSINTSTROBEDONE; - output RXOSINTSTROBESTARTED; - output RXOUTCLK; - output RXOUTCLKFABRIC; - output RXOUTCLKPCS; - output RXPHALIGNDONE; - output RXPHALIGNERR; - output RXPMARESETDONE; - output RXPRBSERR; - output RXPRBSLOCKED; - output RXPRGDIVRESETDONE; - output RXQPISENN; - output RXQPISENP; - output RXRATEDONE; - output RXRECCLKOUT; - output RXRESETDONE; - output RXSLIDERDY; - output RXSLIPDONE; - output RXSLIPOUTCLKRDY; - output RXSLIPPMARDY; - output [1:0] RXSTARTOFSEQ; - output [2:0] RXSTATUS; - output RXSYNCDONE; - output RXSYNCOUT; - output RXVALID; - output [1:0] TXBUFSTATUS; - output TXCOMFINISH; - output TXDCCDONE; - output TXDLYSRESETDONE; - output TXOUTCLK; - output TXOUTCLKFABRIC; - output TXOUTCLKPCS; - output TXPHALIGNDONE; - output TXPHINITDONE; - output TXPMARESETDONE; - output TXPRGDIVRESETDONE; - output TXQPISENN; - output TXQPISENP; - output TXRATEDONE; - output TXRESETDONE; - output TXSYNCDONE; - output TXSYNCOUT; - input CDRSTEPDIR; - input CDRSTEPSQ; - input CDRSTEPSX; - input CFGRESET; - input CLKRSVD0; - input CLKRSVD1; - input CPLLFREQLOCK; - input CPLLLOCKDETCLK; - input CPLLLOCKEN; - input CPLLPD; - input [2:0] CPLLREFCLKSEL; - input CPLLRESET; - input DMONFIFORESET; - input DMONITORCLK; - input [9:0] DRPADDR; - input DRPCLK; - input [15:0] DRPDI; - input DRPEN; - input DRPRST; - input DRPWE; - input EYESCANRESET; - input EYESCANTRIGGER; - input FREQOS; - input GTGREFCLK; - input GTHRXN; - input GTHRXP; - input GTNORTHREFCLK0; - input GTNORTHREFCLK1; - input GTREFCLK0; - input GTREFCLK1; - input [15:0] GTRSVD; - input GTRXRESET; - input GTRXRESETSEL; - input GTSOUTHREFCLK0; - input GTSOUTHREFCLK1; - input GTTXRESET; - input GTTXRESETSEL; - input INCPCTRL; - input [2:0] LOOPBACK; - input PCIEEQRXEQADAPTDONE; - input PCIERSTIDLE; - input PCIERSTTXSYNCSTART; - input PCIEUSERRATEDONE; - input [15:0] PCSRSVDIN; - input QPLL0CLK; - input QPLL0FREQLOCK; - input QPLL0REFCLK; - input QPLL1CLK; - input QPLL1FREQLOCK; - input QPLL1REFCLK; - input RESETOVRD; - input RX8B10BEN; - input RXAFECFOKEN; - input RXBUFRESET; - input RXCDRFREQRESET; - input RXCDRHOLD; - input RXCDROVRDEN; - input RXCDRRESET; - input RXCHBONDEN; - input [4:0] RXCHBONDI; - input [2:0] RXCHBONDLEVEL; - input RXCHBONDMASTER; - input RXCHBONDSLAVE; - input RXCKCALRESET; - input [6:0] RXCKCALSTART; - input RXCOMMADETEN; - input [1:0] RXDFEAGCCTRL; - input RXDFEAGCHOLD; - input RXDFEAGCOVRDEN; - input [3:0] RXDFECFOKFCNUM; - input RXDFECFOKFEN; - input RXDFECFOKFPULSE; - input RXDFECFOKHOLD; - input RXDFECFOKOVREN; - input RXDFEKHHOLD; - input RXDFEKHOVRDEN; - input RXDFELFHOLD; - input RXDFELFOVRDEN; - input RXDFELPMRESET; - input RXDFETAP10HOLD; - input RXDFETAP10OVRDEN; - input RXDFETAP11HOLD; - input RXDFETAP11OVRDEN; - input RXDFETAP12HOLD; - input RXDFETAP12OVRDEN; - input RXDFETAP13HOLD; - input RXDFETAP13OVRDEN; - input RXDFETAP14HOLD; - input RXDFETAP14OVRDEN; - input RXDFETAP15HOLD; - input RXDFETAP15OVRDEN; - input RXDFETAP2HOLD; - input RXDFETAP2OVRDEN; - input RXDFETAP3HOLD; - input RXDFETAP3OVRDEN; - input RXDFETAP4HOLD; - input RXDFETAP4OVRDEN; - input RXDFETAP5HOLD; - input RXDFETAP5OVRDEN; - input RXDFETAP6HOLD; - input RXDFETAP6OVRDEN; - input RXDFETAP7HOLD; - input RXDFETAP7OVRDEN; - input RXDFETAP8HOLD; - input RXDFETAP8OVRDEN; - input RXDFETAP9HOLD; - input RXDFETAP9OVRDEN; - input RXDFEUTHOLD; - input RXDFEUTOVRDEN; - input RXDFEVPHOLD; - input RXDFEVPOVRDEN; - input RXDFEXYDEN; - input RXDLYBYPASS; - input RXDLYEN; - input RXDLYOVRDEN; - input RXDLYSRESET; - input [1:0] RXELECIDLEMODE; - input RXEQTRAINING; - input RXGEARBOXSLIP; - input RXLATCLK; - input RXLPMEN; - input RXLPMGCHOLD; - input RXLPMGCOVRDEN; - input RXLPMHFHOLD; - input RXLPMHFOVRDEN; - input RXLPMLFHOLD; - input RXLPMLFKLOVRDEN; - input RXLPMOSHOLD; - input RXLPMOSOVRDEN; - input RXMCOMMAALIGNEN; - input [1:0] RXMONITORSEL; - input RXOOBRESET; - input RXOSCALRESET; - input RXOSHOLD; - input RXOSOVRDEN; - input [2:0] RXOUTCLKSEL; - input RXPCOMMAALIGNEN; - input RXPCSRESET; - input [1:0] RXPD; - input RXPHALIGN; - input RXPHALIGNEN; - input RXPHDLYPD; - input RXPHDLYRESET; - input RXPHOVRDEN; - input [1:0] RXPLLCLKSEL; - input RXPMARESET; - input RXPOLARITY; - input RXPRBSCNTRESET; - input [3:0] RXPRBSSEL; - input RXPROGDIVRESET; - input RXQPIEN; - input [2:0] RXRATE; - input RXRATEMODE; - input RXSLIDE; - input RXSLIPOUTCLK; - input RXSLIPPMA; - input RXSYNCALLIN; - input RXSYNCIN; - input RXSYNCMODE; - input [1:0] RXSYSCLKSEL; - input RXTERMINATION; - input RXUSERRDY; - input RXUSRCLK; - input RXUSRCLK2; - input SIGVALIDCLK; - input [19:0] TSTIN; - input [7:0] TX8B10BBYPASS; - input TX8B10BEN; - input TXCOMINIT; - input TXCOMSAS; - input TXCOMWAKE; - input [15:0] TXCTRL0; - input [15:0] TXCTRL1; - input [7:0] TXCTRL2; - input [127:0] TXDATA; - input [7:0] TXDATAEXTENDRSVD; - input TXDCCFORCESTART; - input TXDCCRESET; - input [1:0] TXDEEMPH; - input TXDETECTRX; - input [4:0] TXDIFFCTRL; - input TXDLYBYPASS; - input TXDLYEN; - input TXDLYHOLD; - input TXDLYOVRDEN; - input TXDLYSRESET; - input TXDLYUPDOWN; - input TXELECIDLE; - input [5:0] TXHEADER; - input TXINHIBIT; - input TXLATCLK; - input TXLFPSTRESET; - input TXLFPSU2LPEXIT; - input TXLFPSU3WAKE; - input [6:0] TXMAINCURSOR; - input [2:0] TXMARGIN; - input TXMUXDCDEXHOLD; - input TXMUXDCDORWREN; - input TXONESZEROS; - input [2:0] TXOUTCLKSEL; - input TXPCSRESET; - input [1:0] TXPD; - input TXPDELECIDLEMODE; - input TXPHALIGN; - input TXPHALIGNEN; - input TXPHDLYPD; - input TXPHDLYRESET; - input TXPHDLYTSTCLK; - input TXPHINIT; - input TXPHOVRDEN; - input TXPIPPMEN; - input TXPIPPMOVRDEN; - input TXPIPPMPD; - input TXPIPPMSEL; - input [4:0] TXPIPPMSTEPSIZE; - input TXPISOPD; - input [1:0] TXPLLCLKSEL; - input TXPMARESET; - input TXPOLARITY; - input [4:0] TXPOSTCURSOR; - input TXPRBSFORCEERR; - input [3:0] TXPRBSSEL; - input [4:0] TXPRECURSOR; - input TXPROGDIVRESET; - input TXQPIBIASEN; - input TXQPIWEAKPUP; - input [2:0] TXRATE; - input TXRATEMODE; - input [6:0] TXSEQUENCE; - input TXSWING; - input TXSYNCALLIN; - input TXSYNCIN; - input TXSYNCMODE; - input [1:0] TXSYSCLKSEL; - input TXUSERRDY; - input TXUSRCLK; - input TXUSRCLK2; -endmodule - -module GTHE4_COMMON (...); - parameter [0:0] AEN_QPLL0_FBDIV = 1'b1; - parameter [0:0] AEN_QPLL1_FBDIV = 1'b1; - parameter [0:0] AEN_SDM0TOGGLE = 1'b0; - parameter [0:0] AEN_SDM1TOGGLE = 1'b0; - parameter [0:0] A_SDM0TOGGLE = 1'b0; - parameter [8:0] A_SDM1DATA_HIGH = 9'b000000000; - parameter [15:0] A_SDM1DATA_LOW = 16'b0000000000000000; - parameter [0:0] A_SDM1TOGGLE = 1'b0; - parameter [15:0] BIAS_CFG0 = 16'h0000; - parameter [15:0] BIAS_CFG1 = 16'h0000; - parameter [15:0] BIAS_CFG2 = 16'h0000; - parameter [15:0] BIAS_CFG3 = 16'h0000; - parameter [15:0] BIAS_CFG4 = 16'h0000; - parameter [15:0] BIAS_CFG_RSVD = 16'h0000; - parameter [15:0] COMMON_CFG0 = 16'h0000; - parameter [15:0] COMMON_CFG1 = 16'h0000; - parameter [15:0] POR_CFG = 16'h0000; - parameter [15:0] PPF0_CFG = 16'h0F00; - parameter [15:0] PPF1_CFG = 16'h0F00; - parameter QPLL0CLKOUT_RATE = "FULL"; - parameter [15:0] QPLL0_CFG0 = 16'h391C; - parameter [15:0] QPLL0_CFG1 = 16'h0000; - parameter [15:0] QPLL0_CFG1_G3 = 16'h0020; - parameter [15:0] QPLL0_CFG2 = 16'h0F80; - parameter [15:0] QPLL0_CFG2_G3 = 16'h0F80; - parameter [15:0] QPLL0_CFG3 = 16'h0120; - parameter [15:0] QPLL0_CFG4 = 16'h0002; - parameter [9:0] QPLL0_CP = 10'b0000011111; - parameter [9:0] QPLL0_CP_G3 = 10'b0000011111; - parameter integer QPLL0_FBDIV = 66; - parameter integer QPLL0_FBDIV_G3 = 80; - parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000; - parameter [7:0] QPLL0_INIT_CFG1 = 8'h00; - parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8; - parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8; - parameter [9:0] QPLL0_LPF = 10'b1011111111; - parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111; - parameter [0:0] QPLL0_PCI_EN = 1'b0; - parameter [0:0] QPLL0_RATE_SW_USE_DRP = 1'b0; - parameter integer QPLL0_REFCLK_DIV = 1; - parameter [15:0] QPLL0_SDM_CFG0 = 16'h0040; - parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000; - parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000; - parameter QPLL1CLKOUT_RATE = "FULL"; - parameter [15:0] QPLL1_CFG0 = 16'h691C; - parameter [15:0] QPLL1_CFG1 = 16'h0020; - parameter [15:0] QPLL1_CFG1_G3 = 16'h0020; - parameter [15:0] QPLL1_CFG2 = 16'h0F80; - parameter [15:0] QPLL1_CFG2_G3 = 16'h0F80; - parameter [15:0] QPLL1_CFG3 = 16'h0120; - parameter [15:0] QPLL1_CFG4 = 16'h0002; - parameter [9:0] QPLL1_CP = 10'b0000011111; - parameter [9:0] QPLL1_CP_G3 = 10'b0000011111; - parameter integer QPLL1_FBDIV = 66; - parameter integer QPLL1_FBDIV_G3 = 80; - parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000; - parameter [7:0] QPLL1_INIT_CFG1 = 8'h00; - parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8; - parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8; - parameter [9:0] QPLL1_LPF = 10'b1011111111; - parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111; - parameter [0:0] QPLL1_PCI_EN = 1'b0; - parameter [0:0] QPLL1_RATE_SW_USE_DRP = 1'b0; - parameter integer QPLL1_REFCLK_DIV = 1; - parameter [15:0] QPLL1_SDM_CFG0 = 16'h0000; - parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000; - parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000; - parameter [15:0] RSVD_ATTR0 = 16'h0000; - parameter [15:0] RSVD_ATTR1 = 16'h0000; - parameter [15:0] RSVD_ATTR2 = 16'h0000; - parameter [15:0] RSVD_ATTR3 = 16'h0000; - parameter [1:0] RXRECCLKOUT0_SEL = 2'b00; - parameter [1:0] RXRECCLKOUT1_SEL = 2'b00; - parameter [0:0] SARC_ENB = 1'b0; - parameter [0:0] SARC_SEL = 1'b0; - parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000; - parameter [8:0] SDM0INITSEED0_1 = 9'b000000000; - parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000; - parameter [8:0] SDM1INITSEED0_1 = 9'b000000000; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter SIM_MODE = "FAST"; - parameter SIM_RESET_SPEEDUP = "TRUE"; - output [15:0] DRPDO; - output DRPRDY; - output [7:0] PMARSVDOUT0; - output [7:0] PMARSVDOUT1; - output QPLL0FBCLKLOST; - output QPLL0LOCK; - output QPLL0OUTCLK; - output QPLL0OUTREFCLK; - output QPLL0REFCLKLOST; - output QPLL1FBCLKLOST; - output QPLL1LOCK; - output QPLL1OUTCLK; - output QPLL1OUTREFCLK; - output QPLL1REFCLKLOST; - output [7:0] QPLLDMONITOR0; - output [7:0] QPLLDMONITOR1; - output REFCLKOUTMONITOR0; - output REFCLKOUTMONITOR1; - output [1:0] RXRECCLK0SEL; - output [1:0] RXRECCLK1SEL; - output [3:0] SDM0FINALOUT; - output [14:0] SDM0TESTDATA; - output [3:0] SDM1FINALOUT; - output [14:0] SDM1TESTDATA; - output [9:0] TCONGPO; - output TCONRSVDOUT0; - input BGBYPASSB; - input BGMONITORENB; - input BGPDB; - input [4:0] BGRCALOVRD; - input BGRCALOVRDENB; - input [15:0] DRPADDR; - input DRPCLK; - input [15:0] DRPDI; - input DRPEN; - input DRPWE; - input GTGREFCLK0; - input GTGREFCLK1; - input GTNORTHREFCLK00; - input GTNORTHREFCLK01; - input GTNORTHREFCLK10; - input GTNORTHREFCLK11; - input GTREFCLK00; - input GTREFCLK01; - input GTREFCLK10; - input GTREFCLK11; - input GTSOUTHREFCLK00; - input GTSOUTHREFCLK01; - input GTSOUTHREFCLK10; - input GTSOUTHREFCLK11; - input [2:0] PCIERATEQPLL0; - input [2:0] PCIERATEQPLL1; - input [7:0] PMARSVD0; - input [7:0] PMARSVD1; - input QPLL0CLKRSVD0; - input QPLL0CLKRSVD1; - input [7:0] QPLL0FBDIV; - input QPLL0LOCKDETCLK; - input QPLL0LOCKEN; - input QPLL0PD; - input [2:0] QPLL0REFCLKSEL; - input QPLL0RESET; - input QPLL1CLKRSVD0; - input QPLL1CLKRSVD1; - input [7:0] QPLL1FBDIV; - input QPLL1LOCKDETCLK; - input QPLL1LOCKEN; - input QPLL1PD; - input [2:0] QPLL1REFCLKSEL; - input QPLL1RESET; - input [7:0] QPLLRSVD1; - input [4:0] QPLLRSVD2; - input [4:0] QPLLRSVD3; - input [7:0] QPLLRSVD4; - input RCALENB; - input [24:0] SDM0DATA; - input SDM0RESET; - input SDM0TOGGLE; - input [1:0] SDM0WIDTH; - input [24:0] SDM1DATA; - input SDM1RESET; - input SDM1TOGGLE; - input [1:0] SDM1WIDTH; - input [9:0] TCONGPI; - input TCONPOWERUP; - input [1:0] TCONRESET; - input [1:0] TCONRSVDIN1; -endmodule - -module GTYE4_CHANNEL (...); - parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; - parameter [0:0] ACJTAG_MODE = 1'b0; - parameter [0:0] ACJTAG_RESET = 1'b0; - parameter [15:0] ADAPT_CFG0 = 16'h9200; - parameter [15:0] ADAPT_CFG1 = 16'h801C; - parameter [15:0] ADAPT_CFG2 = 16'h0000; - parameter ALIGN_COMMA_DOUBLE = "FALSE"; - parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; - parameter integer ALIGN_COMMA_WORD = 1; - parameter ALIGN_MCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; - parameter ALIGN_PCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; - parameter [0:0] A_RXOSCALRESET = 1'b0; - parameter [0:0] A_RXPROGDIVRESET = 1'b0; - parameter [0:0] A_RXTERMINATION = 1'b1; - parameter [4:0] A_TXDIFFCTRL = 5'b01100; - parameter [0:0] A_TXPROGDIVRESET = 1'b0; - parameter CBCC_DATA_SOURCE_SEL = "DECODED"; - parameter [0:0] CDR_SWAP_MODE_EN = 1'b0; - parameter [0:0] CFOK_PWRSVE_EN = 1'b1; - parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; - parameter integer CHAN_BOND_MAX_SKEW = 7; - parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; - parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; - parameter CHAN_BOND_SEQ_2_USE = "FALSE"; - parameter integer CHAN_BOND_SEQ_LEN = 2; - parameter [15:0] CH_HSPMUX = 16'h2424; - parameter [15:0] CKCAL1_CFG_0 = 16'b1100000011000000; - parameter [15:0] CKCAL1_CFG_1 = 16'b0101000011000000; - parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000; - parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_0 = 16'b1100000011000000; - parameter [15:0] CKCAL2_CFG_1 = 16'b1000000011000000; - parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000; - parameter CLK_CORRECT_USE = "TRUE"; - parameter CLK_COR_KEEP_IDLE = "FALSE"; - parameter integer CLK_COR_MAX_LAT = 20; - parameter integer CLK_COR_MIN_LAT = 18; - parameter CLK_COR_PRECEDENCE = "TRUE"; - parameter integer CLK_COR_REPEAT_WAIT = 0; - parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; - parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; - parameter CLK_COR_SEQ_2_USE = "FALSE"; - parameter integer CLK_COR_SEQ_LEN = 2; - parameter [15:0] CPLL_CFG0 = 16'h01FA; - parameter [15:0] CPLL_CFG1 = 16'h24A9; - parameter [15:0] CPLL_CFG2 = 16'h6807; - parameter [15:0] CPLL_CFG3 = 16'h0000; - parameter integer CPLL_FBDIV = 4; - parameter integer CPLL_FBDIV_45 = 4; - parameter [15:0] CPLL_INIT_CFG0 = 16'h001E; - parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; - parameter integer CPLL_REFCLK_DIV = 1; - parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000; - parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0; - parameter [1:0] DDI_CTRL = 2'b00; - parameter integer DDI_REALIGN_WAIT = 15; - parameter DEC_MCOMMA_DETECT = "TRUE"; - parameter DEC_PCOMMA_DETECT = "TRUE"; - parameter DEC_VALID_COMMA_ONLY = "TRUE"; - parameter [0:0] DELAY_ELEC = 1'b0; - parameter [9:0] DMONITOR_CFG0 = 10'h000; - parameter [7:0] DMONITOR_CFG1 = 8'h00; - parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; - parameter [5:0] ES_CONTROL = 6'b000000; - parameter ES_ERRDET_EN = "FALSE"; - parameter ES_EYE_SCAN_EN = "FALSE"; - parameter [11:0] ES_HORZ_OFFSET = 12'h800; - parameter [4:0] ES_PRESCALE = 5'b00000; - parameter [15:0] ES_QUALIFIER0 = 16'h0000; - parameter [15:0] ES_QUALIFIER1 = 16'h0000; - parameter [15:0] ES_QUALIFIER2 = 16'h0000; - parameter [15:0] ES_QUALIFIER3 = 16'h0000; - parameter [15:0] ES_QUALIFIER4 = 16'h0000; - parameter [15:0] ES_QUALIFIER5 = 16'h0000; - parameter [15:0] ES_QUALIFIER6 = 16'h0000; - parameter [15:0] ES_QUALIFIER7 = 16'h0000; - parameter [15:0] ES_QUALIFIER8 = 16'h0000; - parameter [15:0] ES_QUALIFIER9 = 16'h0000; - parameter [15:0] ES_QUAL_MASK0 = 16'h0000; - parameter [15:0] ES_QUAL_MASK1 = 16'h0000; - parameter [15:0] ES_QUAL_MASK2 = 16'h0000; - parameter [15:0] ES_QUAL_MASK3 = 16'h0000; - parameter [15:0] ES_QUAL_MASK4 = 16'h0000; - parameter [15:0] ES_QUAL_MASK5 = 16'h0000; - parameter [15:0] ES_QUAL_MASK6 = 16'h0000; - parameter [15:0] ES_QUAL_MASK7 = 16'h0000; - parameter [15:0] ES_QUAL_MASK8 = 16'h0000; - parameter [15:0] ES_QUAL_MASK9 = 16'h0000; - parameter [15:0] ES_SDATA_MASK0 = 16'h0000; - parameter [15:0] ES_SDATA_MASK1 = 16'h0000; - parameter [15:0] ES_SDATA_MASK2 = 16'h0000; - parameter [15:0] ES_SDATA_MASK3 = 16'h0000; - parameter [15:0] ES_SDATA_MASK4 = 16'h0000; - parameter [15:0] ES_SDATA_MASK5 = 16'h0000; - parameter [15:0] ES_SDATA_MASK6 = 16'h0000; - parameter [15:0] ES_SDATA_MASK7 = 16'h0000; - parameter [15:0] ES_SDATA_MASK8 = 16'h0000; - parameter [15:0] ES_SDATA_MASK9 = 16'h0000; - parameter integer EYESCAN_VP_RANGE = 0; - parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0; - parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; - parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; - parameter FTS_LANE_DESKEW_EN = "FALSE"; - parameter [4:0] GEARBOX_MODE = 5'b00000; - parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0; - parameter [0:0] LOCAL_MASTER = 1'b0; - parameter integer LPBK_BIAS_CTRL = 4; - parameter [0:0] LPBK_EN_RCAL_B = 1'b0; - parameter [3:0] LPBK_EXT_RCAL = 4'b0000; - parameter integer LPBK_IND_CTRL0 = 5; - parameter integer LPBK_IND_CTRL1 = 5; - parameter integer LPBK_IND_CTRL2 = 5; - parameter integer LPBK_RG_CTRL = 2; - parameter [1:0] OOBDIVCTL = 2'b00; - parameter [0:0] OOB_PWRUP = 1'b0; - parameter PCI3_AUTO_REALIGN = "FRST_SMPL"; - parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1; - parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00; - parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0; - parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000; - parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000; - parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000; - parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0; - parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0; - parameter [4:0] PCIE3_CLK_COR_EMPTY_THRSH = 5'b00000; - parameter [5:0] PCIE3_CLK_COR_FULL_THRSH = 6'b010000; - parameter [4:0] PCIE3_CLK_COR_MAX_LAT = 5'b01000; - parameter [4:0] PCIE3_CLK_COR_MIN_LAT = 5'b00100; - parameter [5:0] PCIE3_CLK_COR_THRSH_TIMER = 6'b001000; - parameter PCIE_64B_DYN_CLKSW_DIS = "FALSE"; - parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000; - parameter PCIE_GEN4_64BIT_INT_EN = "FALSE"; - parameter [1:0] PCIE_PLL_SEL_MODE_GEN12 = 2'h0; - parameter [1:0] PCIE_PLL_SEL_MODE_GEN3 = 2'h0; - parameter [1:0] PCIE_PLL_SEL_MODE_GEN4 = 2'h0; - parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000; - parameter [15:0] PCIE_RXPMA_CFG = 16'h0000; - parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000; - parameter [15:0] PCIE_TXPMA_CFG = 16'h0000; - parameter PCS_PCIE_EN = "FALSE"; - parameter [15:0] PCS_RSVD0 = 16'h0000; - parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; - parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; - parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; - parameter integer PREIQ_FREQ_BST = 0; - parameter [0:0] RATE_SW_USE_DRP = 1'b0; - parameter [0:0] RCLK_SIPO_DLY_ENB = 1'b0; - parameter [0:0] RCLK_SIPO_INV_EN = 1'b0; - parameter [2:0] RTX_BUF_CML_CTRL = 3'b010; - parameter [1:0] RTX_BUF_TERM_CTRL = 2'b00; - parameter [4:0] RXBUFRESET_TIME = 5'b00001; - parameter RXBUF_ADDR_MODE = "FULL"; - parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; - parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; - parameter RXBUF_EN = "TRUE"; - parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; - parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; - parameter RXBUF_RESET_ON_EIDLE = "FALSE"; - parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; - parameter integer RXBUF_THRESH_OVFLW = 0; - parameter RXBUF_THRESH_OVRD = "FALSE"; - parameter integer RXBUF_THRESH_UNDFLW = 4; - parameter [4:0] RXCDRFREQRESET_TIME = 5'b10000; - parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; - parameter [15:0] RXCDR_CFG0 = 16'h0003; - parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0003; - parameter [15:0] RXCDR_CFG1 = 16'h0000; - parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000; - parameter [15:0] RXCDR_CFG2 = 16'h0164; - parameter [9:0] RXCDR_CFG2_GEN2 = 10'h164; - parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0034; - parameter [15:0] RXCDR_CFG2_GEN4 = 16'h0034; - parameter [15:0] RXCDR_CFG3 = 16'h0024; - parameter [5:0] RXCDR_CFG3_GEN2 = 6'h24; - parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0024; - parameter [15:0] RXCDR_CFG3_GEN4 = 16'h0024; - parameter [15:0] RXCDR_CFG4 = 16'h5CF6; - parameter [15:0] RXCDR_CFG4_GEN3 = 16'h5CF6; - parameter [15:0] RXCDR_CFG5 = 16'hB46B; - parameter [15:0] RXCDR_CFG5_GEN3 = 16'h146B; - parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; - parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; - parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0040; - parameter [15:0] RXCDR_LOCK_CFG1 = 16'h8000; - parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000; - parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000; - parameter [15:0] RXCDR_LOCK_CFG4 = 16'h0000; - parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; - parameter [15:0] RXCFOK_CFG0 = 16'h0000; - parameter [15:0] RXCFOK_CFG1 = 16'h0002; - parameter [15:0] RXCFOK_CFG2 = 16'h002D; - parameter [15:0] RXCKCAL1_IQ_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL1_I_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL1_Q_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL2_DX_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL2_D_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL2_S_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL2_X_LOOP_RST_CFG = 16'h0000; - parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; - parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000; - parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022; - parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100; - parameter [15:0] RXDFE_CFG0 = 16'h4000; - parameter [15:0] RXDFE_CFG1 = 16'h0000; - parameter [15:0] RXDFE_GC_CFG0 = 16'h0000; - parameter [15:0] RXDFE_GC_CFG1 = 16'h0000; - parameter [15:0] RXDFE_GC_CFG2 = 16'h0000; - parameter [15:0] RXDFE_H2_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H2_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H3_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H3_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H4_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H4_CFG1 = 16'h0003; - parameter [15:0] RXDFE_H5_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H5_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H6_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H6_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H7_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H7_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H8_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H8_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H9_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H9_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HA_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HA_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HB_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HB_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HC_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HC_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HD_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HD_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HE_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HE_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HF_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HF_CFG1 = 16'h0002; - parameter [15:0] RXDFE_KH_CFG0 = 16'h0000; - parameter [15:0] RXDFE_KH_CFG1 = 16'h0000; - parameter [15:0] RXDFE_KH_CFG2 = 16'h0000; - parameter [15:0] RXDFE_KH_CFG3 = 16'h2000; - parameter [15:0] RXDFE_OS_CFG0 = 16'h0000; - parameter [15:0] RXDFE_OS_CFG1 = 16'h0000; - parameter [15:0] RXDFE_UT_CFG0 = 16'h0000; - parameter [15:0] RXDFE_UT_CFG1 = 16'h0002; - parameter [15:0] RXDFE_UT_CFG2 = 16'h0000; - parameter [15:0] RXDFE_VP_CFG0 = 16'h0000; - parameter [15:0] RXDFE_VP_CFG1 = 16'h0022; - parameter [15:0] RXDLY_CFG = 16'h0010; - parameter [15:0] RXDLY_LCFG = 16'h0030; - parameter RXELECIDLE_CFG = "SIGCFG_4"; - parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4; - parameter RXGEARBOX_EN = "FALSE"; - parameter [4:0] RXISCANRESET_TIME = 5'b00001; - parameter [15:0] RXLPM_CFG = 16'h0000; - parameter [15:0] RXLPM_GC_CFG = 16'h1000; - parameter [15:0] RXLPM_KH_CFG0 = 16'h0000; - parameter [15:0] RXLPM_KH_CFG1 = 16'h0002; - parameter [15:0] RXLPM_OS_CFG0 = 16'h0000; - parameter [15:0] RXLPM_OS_CFG1 = 16'h0000; - parameter [8:0] RXOOB_CFG = 9'b000110000; - parameter RXOOB_CLK_CFG = "PMA"; - parameter [4:0] RXOSCALRESET_TIME = 5'b00011; - parameter integer RXOUT_DIV = 4; - parameter [4:0] RXPCSRESET_TIME = 5'b00001; - parameter [15:0] RXPHBEACON_CFG = 16'h0000; - parameter [15:0] RXPHDLY_CFG = 16'h2020; - parameter [15:0] RXPHSAMP_CFG = 16'h2100; - parameter [15:0] RXPHSLIP_CFG = 16'h9933; - parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; - parameter [15:0] RXPI_CFG0 = 16'h0102; - parameter [15:0] RXPI_CFG1 = 16'b0000000001010100; - parameter RXPMACLK_SEL = "DATA"; - parameter [4:0] RXPMARESET_TIME = 5'b00001; - parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; - parameter integer RXPRBS_LINKACQ_CNT = 15; - parameter [0:0] RXREFCLKDIV2_SEL = 1'b0; - parameter integer RXSLIDE_AUTO_WAIT = 7; - parameter RXSLIDE_MODE = "OFF"; - parameter [0:0] RXSYNC_MULTILANE = 1'b0; - parameter [0:0] RXSYNC_OVRD = 1'b0; - parameter [0:0] RXSYNC_SKIP_DA = 1'b0; - parameter [0:0] RX_AFE_CM_EN = 1'b0; - parameter [15:0] RX_BIAS_CFG0 = 16'h12B0; - parameter [5:0] RX_BUFFER_CFG = 6'b000000; - parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0; - parameter integer RX_CLK25_DIV = 8; - parameter [0:0] RX_CLKMUX_EN = 1'b1; - parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000; - parameter [3:0] RX_CM_BUF_CFG = 4'b1010; - parameter [0:0] RX_CM_BUF_PD = 1'b0; - parameter integer RX_CM_SEL = 2; - parameter integer RX_CM_TRIM = 12; - parameter [0:0] RX_CTLE_PWR_SAVING = 1'b0; - parameter [3:0] RX_CTLE_RES_CTRL = 4'b0000; - parameter integer RX_DATA_WIDTH = 20; - parameter [5:0] RX_DDI_SEL = 6'b000000; - parameter RX_DEFER_RESET_BUF_EN = "TRUE"; - parameter [2:0] RX_DEGEN_CTRL = 3'b100; - parameter integer RX_DFELPM_CFG0 = 10; - parameter [0:0] RX_DFELPM_CFG1 = 1'b1; - parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1; - parameter integer RX_DFE_AGC_CFG1 = 4; - parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1; - parameter integer RX_DFE_KL_LPM_KH_CFG1 = 2; - parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01; - parameter integer RX_DFE_KL_LPM_KL_CFG1 = 4; - parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; - parameter RX_DISPERR_SEQ_MATCH = "TRUE"; - parameter [4:0] RX_DIVRESET_TIME = 5'b00001; - parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0; - parameter integer RX_EN_SUM_RCAL_B = 0; - parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000; - parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0; - parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b10; - parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0; - parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0; - parameter [0:0] RX_I2V_FILTER_EN = 1'b1; - parameter integer RX_INT_DATAWIDTH = 1; - parameter [0:0] RX_PMA_POWER_SAVE = 1'b0; - parameter [15:0] RX_PMA_RSV0 = 16'h002F; - parameter real RX_PROGDIV_CFG = 0.0; - parameter [15:0] RX_PROGDIV_RATE = 16'h0001; - parameter [3:0] RX_RESLOAD_CTRL = 4'b0000; - parameter [0:0] RX_RESLOAD_OVRD = 1'b0; - parameter [2:0] RX_SAMPLE_PERIOD = 3'b101; - parameter integer RX_SIG_VALID_DLY = 11; - parameter integer RX_SUM_DEGEN_AVTT_OVERITE = 0; - parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0; - parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000; - parameter integer RX_SUM_PWR_SAVING = 0; - parameter [3:0] RX_SUM_RES_CTRL = 4'b0000; - parameter [3:0] RX_SUM_VCMTUNE = 4'b0011; - parameter [0:0] RX_SUM_VCM_BIAS_TUNE_EN = 1'b1; - parameter [0:0] RX_SUM_VCM_OVWR = 1'b0; - parameter [2:0] RX_SUM_VREF_TUNE = 3'b100; - parameter [1:0] RX_TUNE_AFE_OS = 2'b00; - parameter [2:0] RX_VREG_CTRL = 3'b010; - parameter [0:0] RX_VREG_PDB = 1'b1; - parameter [1:0] RX_WIDEMODE_CDR = 2'b01; - parameter [1:0] RX_WIDEMODE_CDR_GEN3 = 2'b01; - parameter [1:0] RX_WIDEMODE_CDR_GEN4 = 2'b01; - parameter RX_XCLK_SEL = "RXDES"; - parameter [0:0] RX_XMODE_SEL = 1'b0; - parameter [0:0] SAMPLE_CLK_PHASE = 1'b0; - parameter [0:0] SAS_12G_MODE = 1'b0; - parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; - parameter [2:0] SATA_BURST_VAL = 3'b100; - parameter SATA_CPLL_CFG = "VCO_3000MHZ"; - parameter [2:0] SATA_EIDLE_VAL = 3'b100; - parameter SHOW_REALIGN_COMMA = "TRUE"; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter SIM_MODE = "FAST"; - parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter SIM_TX_EIDLE_DRIVE_LEVEL = "Z"; - parameter [0:0] SRSTMODE = 1'b0; - parameter [1:0] TAPDLY_SET_TX = 2'h0; - parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; - parameter [2:0] TERM_RCAL_OVRD = 3'b000; - parameter [7:0] TRANS_TIME_RATE = 8'h0E; - parameter [7:0] TST_RSV0 = 8'h00; - parameter [7:0] TST_RSV1 = 8'h00; - parameter TXBUF_EN = "TRUE"; - parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; - parameter [15:0] TXDLY_CFG = 16'h0010; - parameter [15:0] TXDLY_LCFG = 16'h0030; - parameter integer TXDRV_FREQBAND = 0; - parameter [15:0] TXFE_CFG0 = 16'b0000000000000000; - parameter [15:0] TXFE_CFG1 = 16'b0000000000000000; - parameter [15:0] TXFE_CFG2 = 16'b0000000000000000; - parameter [15:0] TXFE_CFG3 = 16'b0000000000000000; - parameter TXFIFO_ADDR_CFG = "LOW"; - parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4; - parameter TXGEARBOX_EN = "FALSE"; - parameter integer TXOUT_DIV = 4; - parameter [4:0] TXPCSRESET_TIME = 5'b00001; - parameter [15:0] TXPHDLY_CFG0 = 16'h6020; - parameter [15:0] TXPHDLY_CFG1 = 16'h0002; - parameter [15:0] TXPH_CFG = 16'h0123; - parameter [15:0] TXPH_CFG2 = 16'h0000; - parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; - parameter [15:0] TXPI_CFG0 = 16'b0000000100000000; - parameter [15:0] TXPI_CFG1 = 16'b0000000000000000; - parameter [0:0] TXPI_GRAY_SEL = 1'b0; - parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; - parameter [0:0] TXPI_PPM = 1'b0; - parameter [7:0] TXPI_PPM_CFG = 8'b00000000; - parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; - parameter [4:0] TXPMARESET_TIME = 5'b00001; - parameter [0:0] TXREFCLKDIV2_SEL = 1'b0; - parameter integer TXSWBST_BST = 1; - parameter integer TXSWBST_EN = 0; - parameter integer TXSWBST_MAG = 6; - parameter [0:0] TXSYNC_MULTILANE = 1'b0; - parameter [0:0] TXSYNC_OVRD = 1'b0; - parameter [0:0] TXSYNC_SKIP_DA = 1'b0; - parameter integer TX_CLK25_DIV = 8; - parameter [0:0] TX_CLKMUX_EN = 1'b1; - parameter integer TX_DATA_WIDTH = 20; - parameter [15:0] TX_DCC_LOOP_RST_CFG = 16'h0000; - parameter [5:0] TX_DEEMPH0 = 6'b000000; - parameter [5:0] TX_DEEMPH1 = 6'b000000; - parameter [5:0] TX_DEEMPH2 = 6'b000000; - parameter [5:0] TX_DEEMPH3 = 6'b000000; - parameter [4:0] TX_DIVRESET_TIME = 5'b00001; - parameter TX_DRIVE_MODE = "DIRECT"; - parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; - parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; - parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0; - parameter [0:0] TX_FIFO_BYP_EN = 1'b0; - parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0; - parameter integer TX_INT_DATAWIDTH = 1; - parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; - parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; - parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; - parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; - parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; - parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; - parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; - parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; - parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; - parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; - parameter [15:0] TX_PHICAL_CFG0 = 16'h0000; - parameter [15:0] TX_PHICAL_CFG1 = 16'h003F; - parameter integer TX_PI_BIASSET = 0; - parameter [0:0] TX_PMADATA_OPT = 1'b0; - parameter [0:0] TX_PMA_POWER_SAVE = 1'b0; - parameter [15:0] TX_PMA_RSV0 = 16'h0000; - parameter [15:0] TX_PMA_RSV1 = 16'h0000; - parameter TX_PROGCLK_SEL = "POSTPI"; - parameter real TX_PROGDIV_CFG = 0.0; - parameter [15:0] TX_PROGDIV_RATE = 16'h0001; - parameter [13:0] TX_RXDETECT_CFG = 14'h0032; - parameter integer TX_RXDETECT_REF = 3; - parameter [2:0] TX_SAMPLE_PERIOD = 3'b101; - parameter [1:0] TX_SW_MEAS = 2'b00; - parameter [2:0] TX_VREG_CTRL = 3'b000; - parameter [0:0] TX_VREG_PDB = 1'b0; - parameter [1:0] TX_VREG_VREFSEL = 2'b00; - parameter TX_XCLK_SEL = "TXOUT"; - parameter [0:0] USB_BOTH_BURST_IDLE = 1'b0; - parameter [6:0] USB_BURSTMAX_U3WAKE = 7'b1111111; - parameter [6:0] USB_BURSTMIN_U3WAKE = 7'b1100011; - parameter [0:0] USB_CLK_COR_EQ_EN = 1'b0; - parameter [0:0] USB_EXT_CNTL = 1'b1; - parameter [9:0] USB_IDLEMAX_POLLING = 10'b1010111011; - parameter [9:0] USB_IDLEMIN_POLLING = 10'b0100101011; - parameter [8:0] USB_LFPSPING_BURST = 9'b000000101; - parameter [8:0] USB_LFPSPOLLING_BURST = 9'b000110001; - parameter [8:0] USB_LFPSPOLLING_IDLE_MS = 9'b000000100; - parameter [8:0] USB_LFPSU1EXIT_BURST = 9'b000011101; - parameter [8:0] USB_LFPSU2LPEXIT_BURST_MS = 9'b001100011; - parameter [8:0] USB_LFPSU3WAKE_BURST_MS = 9'b111110011; - parameter [3:0] USB_LFPS_TPERIOD = 4'b0011; - parameter [0:0] USB_LFPS_TPERIOD_ACCURATE = 1'b1; - parameter [0:0] USB_MODE = 1'b0; - parameter [0:0] USB_PCIE_ERR_REP_DIS = 1'b0; - parameter integer USB_PING_SATA_MAX_INIT = 21; - parameter integer USB_PING_SATA_MIN_INIT = 12; - parameter integer USB_POLL_SATA_MAX_BURST = 8; - parameter integer USB_POLL_SATA_MIN_BURST = 4; - parameter [0:0] USB_RAW_ELEC = 1'b0; - parameter [0:0] USB_RXIDLE_P0_CTRL = 1'b1; - parameter [0:0] USB_TXIDLE_TUNE_ENABLE = 1'b1; - parameter integer USB_U1_SATA_MAX_WAKE = 7; - parameter integer USB_U1_SATA_MIN_WAKE = 4; - parameter integer USB_U2_SAS_MAX_COM = 64; - parameter integer USB_U2_SAS_MIN_COM = 36; - parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; - parameter [0:0] Y_ALL_MODE = 1'b0; - output BUFGTCE; - output [2:0] BUFGTCEMASK; - output [8:0] BUFGTDIV; - output BUFGTRESET; - output [2:0] BUFGTRSTMASK; - output CPLLFBCLKLOST; - output CPLLLOCK; - output CPLLREFCLKLOST; - output [15:0] DMONITOROUT; - output DMONITOROUTCLK; - output [15:0] DRPDO; - output DRPRDY; - output EYESCANDATAERROR; - output GTPOWERGOOD; - output GTREFCLKMONITOR; - output GTYTXN; - output GTYTXP; - output PCIERATEGEN3; - output PCIERATEIDLE; - output [1:0] PCIERATEQPLLPD; - output [1:0] PCIERATEQPLLRESET; - output PCIESYNCTXSYNCDONE; - output PCIEUSERGEN3RDY; - output PCIEUSERPHYSTATUSRST; - output PCIEUSERRATESTART; - output [15:0] PCSRSVDOUT; - output PHYSTATUS; - output [15:0] PINRSRVDAS; - output POWERPRESENT; - output RESETEXCEPTION; - output [2:0] RXBUFSTATUS; - output RXBYTEISALIGNED; - output RXBYTEREALIGN; - output RXCDRLOCK; - output RXCDRPHDONE; - output RXCHANBONDSEQ; - output RXCHANISALIGNED; - output RXCHANREALIGN; - output [4:0] RXCHBONDO; - output RXCKCALDONE; - output [1:0] RXCLKCORCNT; - output RXCOMINITDET; - output RXCOMMADET; - output RXCOMSASDET; - output RXCOMWAKEDET; - output [15:0] RXCTRL0; - output [15:0] RXCTRL1; - output [7:0] RXCTRL2; - output [7:0] RXCTRL3; - output [127:0] RXDATA; - output [7:0] RXDATAEXTENDRSVD; - output [1:0] RXDATAVALID; - output RXDLYSRESETDONE; - output RXELECIDLE; - output [5:0] RXHEADER; - output [1:0] RXHEADERVALID; - output RXLFPSTRESETDET; - output RXLFPSU2LPEXITDET; - output RXLFPSU3WAKEDET; - output [7:0] RXMONITOROUT; - output RXOSINTDONE; - output RXOSINTSTARTED; - output RXOSINTSTROBEDONE; - output RXOSINTSTROBESTARTED; - output RXOUTCLK; - output RXOUTCLKFABRIC; - output RXOUTCLKPCS; - output RXPHALIGNDONE; - output RXPHALIGNERR; - output RXPMARESETDONE; - output RXPRBSERR; - output RXPRBSLOCKED; - output RXPRGDIVRESETDONE; - output RXRATEDONE; - output RXRECCLKOUT; - output RXRESETDONE; - output RXSLIDERDY; - output RXSLIPDONE; - output RXSLIPOUTCLKRDY; - output RXSLIPPMARDY; - output [1:0] RXSTARTOFSEQ; - output [2:0] RXSTATUS; - output RXSYNCDONE; - output RXSYNCOUT; - output RXVALID; - output [1:0] TXBUFSTATUS; - output TXCOMFINISH; - output TXDCCDONE; - output TXDLYSRESETDONE; - output TXOUTCLK; - output TXOUTCLKFABRIC; - output TXOUTCLKPCS; - output TXPHALIGNDONE; - output TXPHINITDONE; - output TXPMARESETDONE; - output TXPRGDIVRESETDONE; - output TXRATEDONE; - output TXRESETDONE; - output TXSYNCDONE; - output TXSYNCOUT; - input CDRSTEPDIR; - input CDRSTEPSQ; - input CDRSTEPSX; - input CFGRESET; - input CLKRSVD0; - input CLKRSVD1; - input CPLLFREQLOCK; - input CPLLLOCKDETCLK; - input CPLLLOCKEN; - input CPLLPD; - input [2:0] CPLLREFCLKSEL; - input CPLLRESET; - input DMONFIFORESET; - input DMONITORCLK; - input [9:0] DRPADDR; - input DRPCLK; - input [15:0] DRPDI; - input DRPEN; - input DRPRST; - input DRPWE; - input EYESCANRESET; - input EYESCANTRIGGER; - input FREQOS; - input GTGREFCLK; - input GTNORTHREFCLK0; - input GTNORTHREFCLK1; - input GTREFCLK0; - input GTREFCLK1; - input [15:0] GTRSVD; - input GTRXRESET; - input GTRXRESETSEL; - input GTSOUTHREFCLK0; - input GTSOUTHREFCLK1; - input GTTXRESET; - input GTTXRESETSEL; - input GTYRXN; - input GTYRXP; - input INCPCTRL; - input [2:0] LOOPBACK; - input PCIEEQRXEQADAPTDONE; - input PCIERSTIDLE; - input PCIERSTTXSYNCSTART; - input PCIEUSERRATEDONE; - input [15:0] PCSRSVDIN; - input QPLL0CLK; - input QPLL0FREQLOCK; - input QPLL0REFCLK; - input QPLL1CLK; - input QPLL1FREQLOCK; - input QPLL1REFCLK; - input RESETOVRD; - input RX8B10BEN; - input RXAFECFOKEN; - input RXBUFRESET; - input RXCDRFREQRESET; - input RXCDRHOLD; - input RXCDROVRDEN; - input RXCDRRESET; - input RXCHBONDEN; - input [4:0] RXCHBONDI; - input [2:0] RXCHBONDLEVEL; - input RXCHBONDMASTER; - input RXCHBONDSLAVE; - input RXCKCALRESET; - input [6:0] RXCKCALSTART; - input RXCOMMADETEN; - input RXDFEAGCHOLD; - input RXDFEAGCOVRDEN; - input [3:0] RXDFECFOKFCNUM; - input RXDFECFOKFEN; - input RXDFECFOKFPULSE; - input RXDFECFOKHOLD; - input RXDFECFOKOVREN; - input RXDFEKHHOLD; - input RXDFEKHOVRDEN; - input RXDFELFHOLD; - input RXDFELFOVRDEN; - input RXDFELPMRESET; - input RXDFETAP10HOLD; - input RXDFETAP10OVRDEN; - input RXDFETAP11HOLD; - input RXDFETAP11OVRDEN; - input RXDFETAP12HOLD; - input RXDFETAP12OVRDEN; - input RXDFETAP13HOLD; - input RXDFETAP13OVRDEN; - input RXDFETAP14HOLD; - input RXDFETAP14OVRDEN; - input RXDFETAP15HOLD; - input RXDFETAP15OVRDEN; - input RXDFETAP2HOLD; - input RXDFETAP2OVRDEN; - input RXDFETAP3HOLD; - input RXDFETAP3OVRDEN; - input RXDFETAP4HOLD; - input RXDFETAP4OVRDEN; - input RXDFETAP5HOLD; - input RXDFETAP5OVRDEN; - input RXDFETAP6HOLD; - input RXDFETAP6OVRDEN; - input RXDFETAP7HOLD; - input RXDFETAP7OVRDEN; - input RXDFETAP8HOLD; - input RXDFETAP8OVRDEN; - input RXDFETAP9HOLD; - input RXDFETAP9OVRDEN; - input RXDFEUTHOLD; - input RXDFEUTOVRDEN; - input RXDFEVPHOLD; - input RXDFEVPOVRDEN; - input RXDFEXYDEN; - input RXDLYBYPASS; - input RXDLYEN; - input RXDLYOVRDEN; - input RXDLYSRESET; - input [1:0] RXELECIDLEMODE; - input RXEQTRAINING; - input RXGEARBOXSLIP; - input RXLATCLK; - input RXLPMEN; - input RXLPMGCHOLD; - input RXLPMGCOVRDEN; - input RXLPMHFHOLD; - input RXLPMHFOVRDEN; - input RXLPMLFHOLD; - input RXLPMLFKLOVRDEN; - input RXLPMOSHOLD; - input RXLPMOSOVRDEN; - input RXMCOMMAALIGNEN; - input [1:0] RXMONITORSEL; - input RXOOBRESET; - input RXOSCALRESET; - input RXOSHOLD; - input RXOSOVRDEN; - input [2:0] RXOUTCLKSEL; - input RXPCOMMAALIGNEN; - input RXPCSRESET; - input [1:0] RXPD; - input RXPHALIGN; - input RXPHALIGNEN; - input RXPHDLYPD; - input RXPHDLYRESET; - input [1:0] RXPLLCLKSEL; - input RXPMARESET; - input RXPOLARITY; - input RXPRBSCNTRESET; - input [3:0] RXPRBSSEL; - input RXPROGDIVRESET; - input [2:0] RXRATE; - input RXRATEMODE; - input RXSLIDE; - input RXSLIPOUTCLK; - input RXSLIPPMA; - input RXSYNCALLIN; - input RXSYNCIN; - input RXSYNCMODE; - input [1:0] RXSYSCLKSEL; - input RXTERMINATION; - input RXUSERRDY; - input RXUSRCLK; - input RXUSRCLK2; - input SIGVALIDCLK; - input [19:0] TSTIN; - input [7:0] TX8B10BBYPASS; - input TX8B10BEN; - input TXCOMINIT; - input TXCOMSAS; - input TXCOMWAKE; - input [15:0] TXCTRL0; - input [15:0] TXCTRL1; - input [7:0] TXCTRL2; - input [127:0] TXDATA; - input [7:0] TXDATAEXTENDRSVD; - input TXDCCFORCESTART; - input TXDCCRESET; - input [1:0] TXDEEMPH; - input TXDETECTRX; - input [4:0] TXDIFFCTRL; - input TXDLYBYPASS; - input TXDLYEN; - input TXDLYHOLD; - input TXDLYOVRDEN; - input TXDLYSRESET; - input TXDLYUPDOWN; - input TXELECIDLE; - input [5:0] TXHEADER; - input TXINHIBIT; - input TXLATCLK; - input TXLFPSTRESET; - input TXLFPSU2LPEXIT; - input TXLFPSU3WAKE; - input [6:0] TXMAINCURSOR; - input [2:0] TXMARGIN; - input TXMUXDCDEXHOLD; - input TXMUXDCDORWREN; - input TXONESZEROS; - input [2:0] TXOUTCLKSEL; - input TXPCSRESET; - input [1:0] TXPD; - input TXPDELECIDLEMODE; - input TXPHALIGN; - input TXPHALIGNEN; - input TXPHDLYPD; - input TXPHDLYRESET; - input TXPHDLYTSTCLK; - input TXPHINIT; - input TXPHOVRDEN; - input TXPIPPMEN; - input TXPIPPMOVRDEN; - input TXPIPPMPD; - input TXPIPPMSEL; - input [4:0] TXPIPPMSTEPSIZE; - input TXPISOPD; - input [1:0] TXPLLCLKSEL; - input TXPMARESET; - input TXPOLARITY; - input [4:0] TXPOSTCURSOR; - input TXPRBSFORCEERR; - input [3:0] TXPRBSSEL; - input [4:0] TXPRECURSOR; - input TXPROGDIVRESET; - input [2:0] TXRATE; - input TXRATEMODE; - input [6:0] TXSEQUENCE; - input TXSWING; - input TXSYNCALLIN; - input TXSYNCIN; - input TXSYNCMODE; - input [1:0] TXSYSCLKSEL; - input TXUSERRDY; - input TXUSRCLK; - input TXUSRCLK2; -endmodule - -module GTYE4_COMMON (...); - parameter [0:0] AEN_QPLL0_FBDIV = 1'b1; - parameter [0:0] AEN_QPLL1_FBDIV = 1'b1; - parameter [0:0] AEN_SDM0TOGGLE = 1'b0; - parameter [0:0] AEN_SDM1TOGGLE = 1'b0; - parameter [0:0] A_SDM0TOGGLE = 1'b0; - parameter [8:0] A_SDM1DATA_HIGH = 9'b000000000; - parameter [15:0] A_SDM1DATA_LOW = 16'b0000000000000000; - parameter [0:0] A_SDM1TOGGLE = 1'b0; - parameter [15:0] BIAS_CFG0 = 16'h0000; - parameter [15:0] BIAS_CFG1 = 16'h0000; - parameter [15:0] BIAS_CFG2 = 16'h0000; - parameter [15:0] BIAS_CFG3 = 16'h0000; - parameter [15:0] BIAS_CFG4 = 16'h0000; - parameter [15:0] BIAS_CFG_RSVD = 16'h0000; - parameter [15:0] COMMON_CFG0 = 16'h0000; - parameter [15:0] COMMON_CFG1 = 16'h0000; - parameter [15:0] POR_CFG = 16'h0000; - parameter [15:0] PPF0_CFG = 16'h0F00; - parameter [15:0] PPF1_CFG = 16'h0F00; - parameter QPLL0CLKOUT_RATE = "FULL"; - parameter [15:0] QPLL0_CFG0 = 16'h391C; - parameter [15:0] QPLL0_CFG1 = 16'h0000; - parameter [15:0] QPLL0_CFG1_G3 = 16'h0020; - parameter [15:0] QPLL0_CFG2 = 16'h0F80; - parameter [15:0] QPLL0_CFG2_G3 = 16'h0F80; - parameter [15:0] QPLL0_CFG3 = 16'h0120; - parameter [15:0] QPLL0_CFG4 = 16'h0002; - parameter [9:0] QPLL0_CP = 10'b0000011111; - parameter [9:0] QPLL0_CP_G3 = 10'b0000011111; - parameter integer QPLL0_FBDIV = 66; - parameter integer QPLL0_FBDIV_G3 = 80; - parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000; - parameter [7:0] QPLL0_INIT_CFG1 = 8'h00; - parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8; - parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8; - parameter [9:0] QPLL0_LPF = 10'b1011111111; - parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111; - parameter [0:0] QPLL0_PCI_EN = 1'b0; - parameter [0:0] QPLL0_RATE_SW_USE_DRP = 1'b0; - parameter integer QPLL0_REFCLK_DIV = 1; - parameter [15:0] QPLL0_SDM_CFG0 = 16'h0040; - parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000; - parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000; - parameter QPLL1CLKOUT_RATE = "FULL"; - parameter [15:0] QPLL1_CFG0 = 16'h691C; - parameter [15:0] QPLL1_CFG1 = 16'h0020; - parameter [15:0] QPLL1_CFG1_G3 = 16'h0020; - parameter [15:0] QPLL1_CFG2 = 16'h0F80; - parameter [15:0] QPLL1_CFG2_G3 = 16'h0F80; - parameter [15:0] QPLL1_CFG3 = 16'h0120; - parameter [15:0] QPLL1_CFG4 = 16'h0002; - parameter [9:0] QPLL1_CP = 10'b0000011111; - parameter [9:0] QPLL1_CP_G3 = 10'b0000011111; - parameter integer QPLL1_FBDIV = 66; - parameter integer QPLL1_FBDIV_G3 = 80; - parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000; - parameter [7:0] QPLL1_INIT_CFG1 = 8'h00; - parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8; - parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8; - parameter [9:0] QPLL1_LPF = 10'b1011111111; - parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111; - parameter [0:0] QPLL1_PCI_EN = 1'b0; - parameter [0:0] QPLL1_RATE_SW_USE_DRP = 1'b0; - parameter integer QPLL1_REFCLK_DIV = 1; - parameter [15:0] QPLL1_SDM_CFG0 = 16'h0000; - parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000; - parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000; - parameter [15:0] RSVD_ATTR0 = 16'h0000; - parameter [15:0] RSVD_ATTR1 = 16'h0000; - parameter [15:0] RSVD_ATTR2 = 16'h0000; - parameter [15:0] RSVD_ATTR3 = 16'h0000; - parameter [1:0] RXRECCLKOUT0_SEL = 2'b00; - parameter [1:0] RXRECCLKOUT1_SEL = 2'b00; - parameter [0:0] SARC_ENB = 1'b0; - parameter [0:0] SARC_SEL = 1'b0; - parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000; - parameter [8:0] SDM0INITSEED0_1 = 9'b000000000; - parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000; - parameter [8:0] SDM1INITSEED0_1 = 9'b000000000; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter SIM_MODE = "FAST"; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter [15:0] UB_CFG0 = 16'h0000; - parameter [15:0] UB_CFG1 = 16'h0000; - parameter [15:0] UB_CFG2 = 16'h0000; - parameter [15:0] UB_CFG3 = 16'h0000; - parameter [15:0] UB_CFG4 = 16'h0000; - parameter [15:0] UB_CFG5 = 16'h0400; - parameter [15:0] UB_CFG6 = 16'h0000; - output [15:0] DRPDO; - output DRPRDY; - output [7:0] PMARSVDOUT0; - output [7:0] PMARSVDOUT1; - output QPLL0FBCLKLOST; - output QPLL0LOCK; - output QPLL0OUTCLK; - output QPLL0OUTREFCLK; - output QPLL0REFCLKLOST; - output QPLL1FBCLKLOST; - output QPLL1LOCK; - output QPLL1OUTCLK; - output QPLL1OUTREFCLK; - output QPLL1REFCLKLOST; - output [7:0] QPLLDMONITOR0; - output [7:0] QPLLDMONITOR1; - output REFCLKOUTMONITOR0; - output REFCLKOUTMONITOR1; - output [1:0] RXRECCLK0SEL; - output [1:0] RXRECCLK1SEL; - output [3:0] SDM0FINALOUT; - output [14:0] SDM0TESTDATA; - output [3:0] SDM1FINALOUT; - output [14:0] SDM1TESTDATA; - output [15:0] UBDADDR; - output UBDEN; - output [15:0] UBDI; - output UBDWE; - output UBMDMTDO; - output UBRSVDOUT; - output UBTXUART; - input BGBYPASSB; - input BGMONITORENB; - input BGPDB; - input [4:0] BGRCALOVRD; - input BGRCALOVRDENB; - input [15:0] DRPADDR; - input DRPCLK; - input [15:0] DRPDI; - input DRPEN; - input DRPWE; - input GTGREFCLK0; - input GTGREFCLK1; - input GTNORTHREFCLK00; - input GTNORTHREFCLK01; - input GTNORTHREFCLK10; - input GTNORTHREFCLK11; - input GTREFCLK00; - input GTREFCLK01; - input GTREFCLK10; - input GTREFCLK11; - input GTSOUTHREFCLK00; - input GTSOUTHREFCLK01; - input GTSOUTHREFCLK10; - input GTSOUTHREFCLK11; - input [2:0] PCIERATEQPLL0; - input [2:0] PCIERATEQPLL1; - input [7:0] PMARSVD0; - input [7:0] PMARSVD1; - input QPLL0CLKRSVD0; - input QPLL0CLKRSVD1; - input [7:0] QPLL0FBDIV; - input QPLL0LOCKDETCLK; - input QPLL0LOCKEN; - input QPLL0PD; - input [2:0] QPLL0REFCLKSEL; - input QPLL0RESET; - input QPLL1CLKRSVD0; - input QPLL1CLKRSVD1; - input [7:0] QPLL1FBDIV; - input QPLL1LOCKDETCLK; - input QPLL1LOCKEN; - input QPLL1PD; - input [2:0] QPLL1REFCLKSEL; - input QPLL1RESET; - input [7:0] QPLLRSVD1; - input [4:0] QPLLRSVD2; - input [4:0] QPLLRSVD3; - input [7:0] QPLLRSVD4; - input RCALENB; - input [24:0] SDM0DATA; - input SDM0RESET; - input SDM0TOGGLE; - input [1:0] SDM0WIDTH; - input [24:0] SDM1DATA; - input SDM1RESET; - input SDM1TOGGLE; - input [1:0] SDM1WIDTH; - input UBCFGSTREAMEN; - input [15:0] UBDO; - input UBDRDY; - input UBENABLE; - input [1:0] UBGPI; - input [1:0] UBINTR; - input UBIOLMBRST; - input UBMBRST; - input UBMDMCAPTURE; - input UBMDMDBGRST; - input UBMDMDBGUPDATE; - input [3:0] UBMDMREGEN; - input UBMDMSHIFT; - input UBMDMSYSRST; - input UBMDMTCK; - input UBMDMTDI; -endmodule - -module IBUFDS_GTE4 (...); - parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; - parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00; - parameter [1:0] REFCLK_ICNTL_RX = 2'b00; - output O; - output ODIV2; - input CEB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module OBUFDS_GTE4 (...); - parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; - parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; - (* iopad_external_pin *) - output O; - (* iopad_external_pin *) - output OB; - input CEB; - input I; -endmodule - -module OBUFDS_GTE4_ADV (...); - parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; - parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; - (* iopad_external_pin *) - output O; - (* iopad_external_pin *) - output OB; - input CEB; - input [3:0] I; - input [1:0] RXRECCLK_SEL; -endmodule - -module GTM_DUAL (...); - parameter [15:0] A_CFG = 16'b0000100001000000; - parameter [15:0] A_SDM_DATA_CFG0 = 16'b0000000011010000; - parameter [15:0] A_SDM_DATA_CFG1 = 16'b0000000011010000; - parameter [15:0] BIAS_CFG0 = 16'b0000000000000000; - parameter [15:0] BIAS_CFG1 = 16'b0000000000000000; - parameter [15:0] BIAS_CFG2 = 16'b0001000000000000; - parameter [15:0] BIAS_CFG3 = 16'b0000000000000001; - parameter [15:0] BIAS_CFG4 = 16'b0000000000000000; - parameter [15:0] BIAS_CFG5 = 16'b0000000000000000; - parameter [15:0] BIAS_CFG6 = 16'b0000000010000000; - parameter [15:0] BIAS_CFG7 = 16'b0000000000000000; - parameter [15:0] CH0_A_CH_CFG0 = 16'b0000000000000011; - parameter [15:0] CH0_A_CH_CFG1 = 16'b0000000000000000; - parameter [15:0] CH0_A_CH_CFG2 = 16'b0111101111110000; - parameter [15:0] CH0_A_CH_CFG3 = 16'b0000000000000000; - parameter [15:0] CH0_A_CH_CFG4 = 16'b0000000000000000; - parameter [15:0] CH0_A_CH_CFG5 = 16'b0000000000000000; - parameter [15:0] CH0_A_CH_CFG6 = 16'b0000000000000000; - parameter [15:0] CH0_RST_LP_CFG0 = 16'b0001000000010000; - parameter [15:0] CH0_RST_LP_CFG1 = 16'b0011001000010000; - parameter [15:0] CH0_RST_LP_CFG2 = 16'b0110010100000100; - parameter [15:0] CH0_RST_LP_CFG3 = 16'b0011001000010000; - parameter [15:0] CH0_RST_LP_CFG4 = 16'b0000000001000100; - parameter [15:0] CH0_RST_LP_ID_CFG0 = 16'b0011000001110000; - parameter [15:0] CH0_RST_LP_ID_CFG1 = 16'b0001000000010000; - parameter [15:0] CH0_RST_TIME_CFG0 = 16'b0000010000100001; - parameter [15:0] CH0_RST_TIME_CFG1 = 16'b0000010000100001; - parameter [15:0] CH0_RST_TIME_CFG2 = 16'b0000010000100001; - parameter [15:0] CH0_RST_TIME_CFG3 = 16'b0000010000100000; - parameter [15:0] CH0_RST_TIME_CFG4 = 16'b0000010000100001; - parameter [15:0] CH0_RST_TIME_CFG5 = 16'b0000000000000001; - parameter [15:0] CH0_RST_TIME_CFG6 = 16'b0000000000100001; - parameter [15:0] CH0_RX_ADC_CFG0 = 16'b0011010010001111; - parameter [15:0] CH0_RX_ADC_CFG1 = 16'b0011111001010101; - parameter [15:0] CH0_RX_ANA_CFG0 = 16'b1000000000011101; - parameter [15:0] CH0_RX_ANA_CFG1 = 16'b1110100010000000; - parameter [15:0] CH0_RX_ANA_CFG2 = 16'b0000000010001010; - parameter [15:0] CH0_RX_APT_CFG0A = 16'b0000000001110000; - parameter [15:0] CH0_RX_APT_CFG0B = 16'b0000000001110000; - parameter [15:0] CH0_RX_APT_CFG10A = 16'b0000000001110000; - parameter [15:0] CH0_RX_APT_CFG10B = 16'b0000000001010000; - parameter [15:0] CH0_RX_APT_CFG11A = 16'b0000000001000000; - parameter [15:0] CH0_RX_APT_CFG11B = 16'b0000000001110000; - parameter [15:0] CH0_RX_APT_CFG12A = 16'b0000000001010000; - parameter [15:0] CH0_RX_APT_CFG12B = 16'b0000000000000000; - parameter [15:0] CH0_RX_APT_CFG13A = 16'b0000000000000000; - parameter [15:0] CH0_RX_APT_CFG13B = 16'b0000000000000000; - parameter [15:0] CH0_RX_APT_CFG14A = 16'b0000000000000000; - parameter [15:0] CH0_RX_APT_CFG14B = 16'b0000000000000000; - parameter [15:0] CH0_RX_APT_CFG15A = 16'b0000000000000000; - parameter [15:0] CH0_RX_APT_CFG15B = 16'b0000100000000000; - parameter [15:0] CH0_RX_APT_CFG16A = 16'b0000000000000000; - parameter [15:0] CH0_RX_APT_CFG16B = 16'b0010000000000000; - parameter [15:0] CH0_RX_APT_CFG17A = 16'b0000000000000000; - parameter [15:0] CH0_RX_APT_CFG17B = 16'b0001000001000000; - parameter [15:0] CH0_RX_APT_CFG18A = 16'b0000100000100000; - parameter [15:0] CH0_RX_APT_CFG18B = 16'b0000000000000000; - parameter [15:0] CH0_RX_APT_CFG19A = 16'b0000000000000000; - parameter [15:0] CH0_RX_APT_CFG19B = 16'b0000100000000000; - parameter [15:0] CH0_RX_APT_CFG1A = 16'b0000000001110000; - parameter [15:0] CH0_RX_APT_CFG1B = 16'b0000000001110000; - parameter [15:0] CH0_RX_APT_CFG20A = 16'b1110000000100000; - parameter [15:0] CH0_RX_APT_CFG20B = 16'b0000000001000000; - parameter [15:0] CH0_RX_APT_CFG21A = 16'b0001000000000100; - parameter [15:0] CH0_RX_APT_CFG21B = 16'b0000000000000000; - parameter [15:0] CH0_RX_APT_CFG22A = 16'b0000000001110000; - parameter [15:0] CH0_RX_APT_CFG22B = 16'b0000000001110000; - parameter [15:0] CH0_RX_APT_CFG23A = 16'b0000100000000000; - parameter [15:0] CH0_RX_APT_CFG23B = 16'b0000000000000000; - parameter [15:0] CH0_RX_APT_CFG24A = 16'b0000000000000000; - parameter [15:0] CH0_RX_APT_CFG24B = 16'b0000000000000000; - parameter [15:0] CH0_RX_APT_CFG25A = 16'b0000000000000000; - parameter [15:0] CH0_RX_APT_CFG25B = 16'b0000000000000000; - parameter [15:0] CH0_RX_APT_CFG26A = 16'b0000000000000000; - parameter [15:0] CH0_RX_APT_CFG26B = 16'b0000000000000000; - parameter [15:0] CH0_RX_APT_CFG27A = 16'b0100000000000000; - parameter [15:0] CH0_RX_APT_CFG27B = 16'b0000000000000000; - parameter [15:0] CH0_RX_APT_CFG28A = 16'b0000000000000000; - parameter [15:0] CH0_RX_APT_CFG28B = 16'b1000000000000000; - parameter [15:0] CH0_RX_APT_CFG2A = 16'b0000000001110000; - parameter [15:0] CH0_RX_APT_CFG2B = 16'b0000000001110000; - parameter [15:0] CH0_RX_APT_CFG3A = 16'b0000000001110000; - parameter [15:0] CH0_RX_APT_CFG3B = 16'b0000000001110000; - parameter [15:0] CH0_RX_APT_CFG4A = 16'b0000000001110000; - parameter [15:0] CH0_RX_APT_CFG4B = 16'b0000000001110000; - parameter [15:0] CH0_RX_APT_CFG5A = 16'b0000000001110000; - parameter [15:0] CH0_RX_APT_CFG5B = 16'b0000000001110000; - parameter [15:0] CH0_RX_APT_CFG6A = 16'b0000000001110000; - parameter [15:0] CH0_RX_APT_CFG6B = 16'b0000000001110000; - parameter [15:0] CH0_RX_APT_CFG7A = 16'b0000000001110000; - parameter [15:0] CH0_RX_APT_CFG7B = 16'b0000000001110000; - parameter [15:0] CH0_RX_APT_CFG8A = 16'b0000100000000000; - parameter [15:0] CH0_RX_APT_CFG8B = 16'b0000100000000000; - parameter [15:0] CH0_RX_APT_CFG9A = 16'b0000000001110000; - parameter [15:0] CH0_RX_APT_CFG9B = 16'b0000000001110000; - parameter [15:0] CH0_RX_APT_CTRL_CFG2 = 16'b0000000000000100; - parameter [15:0] CH0_RX_APT_CTRL_CFG3 = 16'b0000000000000000; - parameter [15:0] CH0_RX_CAL_CFG0A = 16'b0000000000000000; - parameter [15:0] CH0_RX_CAL_CFG0B = 16'b0011001100110000; - parameter [15:0] CH0_RX_CAL_CFG1A = 16'b1110111011100001; - parameter [15:0] CH0_RX_CAL_CFG1B = 16'b1111111100000100; - parameter [15:0] CH0_RX_CAL_CFG2A = 16'b0000000000000000; - parameter [15:0] CH0_RX_CAL_CFG2B = 16'b0011000000000000; - parameter [15:0] CH0_RX_CDR_CFG0A = 16'b0000000000000011; - parameter [15:0] CH0_RX_CDR_CFG0B = 16'b0000000000000000; - parameter [15:0] CH0_RX_CDR_CFG1A = 16'b0000000000000000; - parameter [15:0] CH0_RX_CDR_CFG1B = 16'b0000000000000000; - parameter [15:0] CH0_RX_CDR_CFG2A = 16'b1001000101100100; - parameter [15:0] CH0_RX_CDR_CFG2B = 16'b0000000100100100; - parameter [15:0] CH0_RX_CDR_CFG3A = 16'b0101110011110110; - parameter [15:0] CH0_RX_CDR_CFG3B = 16'b0000000000001011; - parameter [15:0] CH0_RX_CDR_CFG4A = 16'b0000000000000110; - parameter [15:0] CH0_RX_CDR_CFG4B = 16'b0000000000000000; - parameter [15:0] CH0_RX_CLKGN_CFG0 = 16'b1100000000000000; - parameter [15:0] CH0_RX_CLKGN_CFG1 = 16'b0000000110000000; - parameter [15:0] CH0_RX_CTLE_CFG0 = 16'b0011010010001000; - parameter [15:0] CH0_RX_CTLE_CFG1 = 16'b0010000000100010; - parameter [15:0] CH0_RX_CTLE_CFG2 = 16'b0000101000000000; - parameter [15:0] CH0_RX_CTLE_CFG3 = 16'b1111001001000000; - parameter [15:0] CH0_RX_DSP_CFG = 16'b0000000000000000; - parameter [15:0] CH0_RX_MON_CFG = 16'b0000000000000000; - parameter [15:0] CH0_RX_PAD_CFG0 = 16'b0001111000000000; - parameter [15:0] CH0_RX_PAD_CFG1 = 16'b0001100000001010; - parameter [15:0] CH0_RX_PCS_CFG0 = 16'b0000000100000000; - parameter [15:0] CH0_RX_PCS_CFG1 = 16'b0000000000000000; - parameter [15:0] CH0_TX_ANA_CFG0 = 16'b0000001010101111; - parameter [15:0] CH0_TX_ANA_CFG1 = 16'b0000000100000000; - parameter [15:0] CH0_TX_ANA_CFG2 = 16'b1000000000010100; - parameter [15:0] CH0_TX_ANA_CFG3 = 16'b0000101000100010; - parameter [15:0] CH0_TX_ANA_CFG4 = 16'b0000000000000000; - parameter [15:0] CH0_TX_CAL_CFG0 = 16'b0000000000100000; - parameter [15:0] CH0_TX_CAL_CFG1 = 16'b0000000001000000; - parameter [15:0] CH0_TX_DRV_CFG0 = 16'b0000000000000000; - parameter [15:0] CH0_TX_DRV_CFG1 = 16'b0000000000100111; - parameter [15:0] CH0_TX_DRV_CFG2 = 16'b0000000000000000; - parameter [15:0] CH0_TX_DRV_CFG3 = 16'b0110110000000000; - parameter [15:0] CH0_TX_DRV_CFG4 = 16'b0000000011000101; - parameter [15:0] CH0_TX_DRV_CFG5 = 16'b0000000000000000; - parameter [15:0] CH0_TX_LPBK_CFG0 = 16'b0000000000000011; - parameter [15:0] CH0_TX_LPBK_CFG1 = 16'b0000000000000000; - parameter [15:0] CH0_TX_PCS_CFG0 = 16'b0000000101100000; - parameter [15:0] CH0_TX_PCS_CFG1 = 16'b0000000000000000; - parameter [15:0] CH0_TX_PCS_CFG10 = 16'b0000000000000000; - parameter [15:0] CH0_TX_PCS_CFG11 = 16'b0000000000000000; - parameter [15:0] CH0_TX_PCS_CFG12 = 16'b0000000000000000; - parameter [15:0] CH0_TX_PCS_CFG13 = 16'b0000000000000000; - parameter [15:0] CH0_TX_PCS_CFG14 = 16'b0000000000000000; - parameter [15:0] CH0_TX_PCS_CFG15 = 16'b0000000000000000; - parameter [15:0] CH0_TX_PCS_CFG16 = 16'b0000000000000000; - parameter [15:0] CH0_TX_PCS_CFG17 = 16'b0000000000000000; - parameter [15:0] CH0_TX_PCS_CFG2 = 16'b0000000000000000; - parameter [15:0] CH0_TX_PCS_CFG3 = 16'b0000000000000000; - parameter [15:0] CH0_TX_PCS_CFG4 = 16'b0000000000000000; - parameter [15:0] CH0_TX_PCS_CFG5 = 16'b0000000000000000; - parameter [15:0] CH0_TX_PCS_CFG6 = 16'b0000000000000000; - parameter [15:0] CH0_TX_PCS_CFG7 = 16'b0000000000000000; - parameter [15:0] CH0_TX_PCS_CFG8 = 16'b0000000000000000; - parameter [15:0] CH0_TX_PCS_CFG9 = 16'b0000000000000000; - parameter [15:0] CH1_A_CH_CFG0 = 16'b0000000000000011; - parameter [15:0] CH1_A_CH_CFG1 = 16'b0000000000000000; - parameter [15:0] CH1_A_CH_CFG2 = 16'b0111101111110000; - parameter [15:0] CH1_A_CH_CFG3 = 16'b0000000000000000; - parameter [15:0] CH1_A_CH_CFG4 = 16'b0000000000000000; - parameter [15:0] CH1_A_CH_CFG5 = 16'b0000000000000000; - parameter [15:0] CH1_A_CH_CFG6 = 16'b0000000000000000; - parameter [15:0] CH1_RST_LP_CFG0 = 16'b0001000000010000; - parameter [15:0] CH1_RST_LP_CFG1 = 16'b0011001000010000; - parameter [15:0] CH1_RST_LP_CFG2 = 16'b0110010100000100; - parameter [15:0] CH1_RST_LP_CFG3 = 16'b0011001000010000; - parameter [15:0] CH1_RST_LP_CFG4 = 16'b0000000001000100; - parameter [15:0] CH1_RST_LP_ID_CFG0 = 16'b0011000001110000; - parameter [15:0] CH1_RST_LP_ID_CFG1 = 16'b0001000000010000; - parameter [15:0] CH1_RST_TIME_CFG0 = 16'b0000010000100001; - parameter [15:0] CH1_RST_TIME_CFG1 = 16'b0000010000100001; - parameter [15:0] CH1_RST_TIME_CFG2 = 16'b0000010000100001; - parameter [15:0] CH1_RST_TIME_CFG3 = 16'b0000010000100000; - parameter [15:0] CH1_RST_TIME_CFG4 = 16'b0000010000100001; - parameter [15:0] CH1_RST_TIME_CFG5 = 16'b0000000000000001; - parameter [15:0] CH1_RST_TIME_CFG6 = 16'b0000000000100001; - parameter [15:0] CH1_RX_ADC_CFG0 = 16'b0011010010001111; - parameter [15:0] CH1_RX_ADC_CFG1 = 16'b0011111001010101; - parameter [15:0] CH1_RX_ANA_CFG0 = 16'b1000000000011101; - parameter [15:0] CH1_RX_ANA_CFG1 = 16'b1110100010000000; - parameter [15:0] CH1_RX_ANA_CFG2 = 16'b0000000010001010; - parameter [15:0] CH1_RX_APT_CFG0A = 16'b0000000001110000; - parameter [15:0] CH1_RX_APT_CFG0B = 16'b0000000001110000; - parameter [15:0] CH1_RX_APT_CFG10A = 16'b0000000001110000; - parameter [15:0] CH1_RX_APT_CFG10B = 16'b0000000001010000; - parameter [15:0] CH1_RX_APT_CFG11A = 16'b0000000001000000; - parameter [15:0] CH1_RX_APT_CFG11B = 16'b0000000001110000; - parameter [15:0] CH1_RX_APT_CFG12A = 16'b0000000001010000; - parameter [15:0] CH1_RX_APT_CFG12B = 16'b0000000000000000; - parameter [15:0] CH1_RX_APT_CFG13A = 16'b0000000000000000; - parameter [15:0] CH1_RX_APT_CFG13B = 16'b0000000000000000; - parameter [15:0] CH1_RX_APT_CFG14A = 16'b0000000000000000; - parameter [15:0] CH1_RX_APT_CFG14B = 16'b0000000000000000; - parameter [15:0] CH1_RX_APT_CFG15A = 16'b0000000000000000; - parameter [15:0] CH1_RX_APT_CFG15B = 16'b0000100000000000; - parameter [15:0] CH1_RX_APT_CFG16A = 16'b0000000000000000; - parameter [15:0] CH1_RX_APT_CFG16B = 16'b0010000000000000; - parameter [15:0] CH1_RX_APT_CFG17A = 16'b0000000000000000; - parameter [15:0] CH1_RX_APT_CFG17B = 16'b0001000001000000; - parameter [15:0] CH1_RX_APT_CFG18A = 16'b0000100000100000; - parameter [15:0] CH1_RX_APT_CFG18B = 16'b0000100010000000; - parameter [15:0] CH1_RX_APT_CFG19A = 16'b0000000000000000; - parameter [15:0] CH1_RX_APT_CFG19B = 16'b0000100000000000; - parameter [15:0] CH1_RX_APT_CFG1A = 16'b0000000001110000; - parameter [15:0] CH1_RX_APT_CFG1B = 16'b0000000001110000; - parameter [15:0] CH1_RX_APT_CFG20A = 16'b1110000000100000; - parameter [15:0] CH1_RX_APT_CFG20B = 16'b0000000001000000; - parameter [15:0] CH1_RX_APT_CFG21A = 16'b0001000000000100; - parameter [15:0] CH1_RX_APT_CFG21B = 16'b0000000000000000; - parameter [15:0] CH1_RX_APT_CFG22A = 16'b0000000001110000; - parameter [15:0] CH1_RX_APT_CFG22B = 16'b0000000001110000; - parameter [15:0] CH1_RX_APT_CFG23A = 16'b0000100000000000; - parameter [15:0] CH1_RX_APT_CFG23B = 16'b0000100000000000; - parameter [15:0] CH1_RX_APT_CFG24A = 16'b0000000000000000; - parameter [15:0] CH1_RX_APT_CFG24B = 16'b0000000000000000; - parameter [15:0] CH1_RX_APT_CFG25A = 16'b0000000000000000; - parameter [15:0] CH1_RX_APT_CFG25B = 16'b0000000000000000; - parameter [15:0] CH1_RX_APT_CFG26A = 16'b0000000000000000; - parameter [15:0] CH1_RX_APT_CFG26B = 16'b0000000000000000; - parameter [15:0] CH1_RX_APT_CFG27A = 16'b0100000000000000; - parameter [15:0] CH1_RX_APT_CFG27B = 16'b0000000000000000; - parameter [15:0] CH1_RX_APT_CFG28A = 16'b0000000000000000; - parameter [15:0] CH1_RX_APT_CFG28B = 16'b1000000000000000; - parameter [15:0] CH1_RX_APT_CFG2A = 16'b0000000001110000; - parameter [15:0] CH1_RX_APT_CFG2B = 16'b0000000001110000; - parameter [15:0] CH1_RX_APT_CFG3A = 16'b0000000001110000; - parameter [15:0] CH1_RX_APT_CFG3B = 16'b0000000001110000; - parameter [15:0] CH1_RX_APT_CFG4A = 16'b0000000001110000; - parameter [15:0] CH1_RX_APT_CFG4B = 16'b0000000001110000; - parameter [15:0] CH1_RX_APT_CFG5A = 16'b0000000001110000; - parameter [15:0] CH1_RX_APT_CFG5B = 16'b0000000001110000; - parameter [15:0] CH1_RX_APT_CFG6A = 16'b0000000001110000; - parameter [15:0] CH1_RX_APT_CFG6B = 16'b0000000001110000; - parameter [15:0] CH1_RX_APT_CFG7A = 16'b0000000001110000; - parameter [15:0] CH1_RX_APT_CFG7B = 16'b0000000001110000; - parameter [15:0] CH1_RX_APT_CFG8A = 16'b0000100000000000; - parameter [15:0] CH1_RX_APT_CFG8B = 16'b0000100000000000; - parameter [15:0] CH1_RX_APT_CFG9A = 16'b0000000001110000; - parameter [15:0] CH1_RX_APT_CFG9B = 16'b0000000001110000; - parameter [15:0] CH1_RX_APT_CTRL_CFG2 = 16'b0000000000000100; - parameter [15:0] CH1_RX_APT_CTRL_CFG3 = 16'b0000000000000000; - parameter [15:0] CH1_RX_CAL_CFG0A = 16'b0000000000000000; - parameter [15:0] CH1_RX_CAL_CFG0B = 16'b0011001100110000; - parameter [15:0] CH1_RX_CAL_CFG1A = 16'b1110111011100001; - parameter [15:0] CH1_RX_CAL_CFG1B = 16'b1111111100000100; - parameter [15:0] CH1_RX_CAL_CFG2A = 16'b0000000000000000; - parameter [15:0] CH1_RX_CAL_CFG2B = 16'b0011000000000000; - parameter [15:0] CH1_RX_CDR_CFG0A = 16'b0000000000000011; - parameter [15:0] CH1_RX_CDR_CFG0B = 16'b0000000000000000; - parameter [15:0] CH1_RX_CDR_CFG1A = 16'b0000000000000000; - parameter [15:0] CH1_RX_CDR_CFG1B = 16'b0000000000000000; - parameter [15:0] CH1_RX_CDR_CFG2A = 16'b1001000101100100; - parameter [15:0] CH1_RX_CDR_CFG2B = 16'b0000000100100100; - parameter [15:0] CH1_RX_CDR_CFG3A = 16'b0101110011110110; - parameter [15:0] CH1_RX_CDR_CFG3B = 16'b0000000000001011; - parameter [15:0] CH1_RX_CDR_CFG4A = 16'b0000000000000110; - parameter [15:0] CH1_RX_CDR_CFG4B = 16'b0000000000000000; - parameter [15:0] CH1_RX_CLKGN_CFG0 = 16'b1100000000000000; - parameter [15:0] CH1_RX_CLKGN_CFG1 = 16'b0000000110000000; - parameter [15:0] CH1_RX_CTLE_CFG0 = 16'b0011010010001000; - parameter [15:0] CH1_RX_CTLE_CFG1 = 16'b0010000000100010; - parameter [15:0] CH1_RX_CTLE_CFG2 = 16'b0000101000000000; - parameter [15:0] CH1_RX_CTLE_CFG3 = 16'b1111001001000000; - parameter [15:0] CH1_RX_DSP_CFG = 16'b0000000000000000; - parameter [15:0] CH1_RX_MON_CFG = 16'b0000000000000000; - parameter [15:0] CH1_RX_PAD_CFG0 = 16'b0001111000000000; - parameter [15:0] CH1_RX_PAD_CFG1 = 16'b0001100000001010; - parameter [15:0] CH1_RX_PCS_CFG0 = 16'b0000000100000000; - parameter [15:0] CH1_RX_PCS_CFG1 = 16'b0000000000000000; - parameter [15:0] CH1_TX_ANA_CFG0 = 16'b0000001010101111; - parameter [15:0] CH1_TX_ANA_CFG1 = 16'b0000000100000000; - parameter [15:0] CH1_TX_ANA_CFG2 = 16'b1000000000010100; - parameter [15:0] CH1_TX_ANA_CFG3 = 16'b0000101000100010; - parameter [15:0] CH1_TX_ANA_CFG4 = 16'b0000000000000000; - parameter [15:0] CH1_TX_CAL_CFG0 = 16'b0000000000100000; - parameter [15:0] CH1_TX_CAL_CFG1 = 16'b0000000001000000; - parameter [15:0] CH1_TX_DRV_CFG0 = 16'b0000000000000000; - parameter [15:0] CH1_TX_DRV_CFG1 = 16'b0000000000100111; - parameter [15:0] CH1_TX_DRV_CFG2 = 16'b0000000000000000; - parameter [15:0] CH1_TX_DRV_CFG3 = 16'b0110110000000000; - parameter [15:0] CH1_TX_DRV_CFG4 = 16'b0000000011000101; - parameter [15:0] CH1_TX_DRV_CFG5 = 16'b0000000000000000; - parameter [15:0] CH1_TX_LPBK_CFG0 = 16'b0000000000000011; - parameter [15:0] CH1_TX_LPBK_CFG1 = 16'b0000000000000000; - parameter [15:0] CH1_TX_PCS_CFG0 = 16'b0000000101100000; - parameter [15:0] CH1_TX_PCS_CFG1 = 16'b0000000000000000; - parameter [15:0] CH1_TX_PCS_CFG10 = 16'b0000000000000000; - parameter [15:0] CH1_TX_PCS_CFG11 = 16'b0000000000000000; - parameter [15:0] CH1_TX_PCS_CFG12 = 16'b0000000000000000; - parameter [15:0] CH1_TX_PCS_CFG13 = 16'b0000000000000000; - parameter [15:0] CH1_TX_PCS_CFG14 = 16'b0000000000000000; - parameter [15:0] CH1_TX_PCS_CFG15 = 16'b0000000000000000; - parameter [15:0] CH1_TX_PCS_CFG16 = 16'b0000000000000000; - parameter [15:0] CH1_TX_PCS_CFG17 = 16'b0000000000000000; - parameter [15:0] CH1_TX_PCS_CFG2 = 16'b0000000000000000; - parameter [15:0] CH1_TX_PCS_CFG3 = 16'b0000000000000000; - parameter [15:0] CH1_TX_PCS_CFG4 = 16'b0000000000000000; - parameter [15:0] CH1_TX_PCS_CFG5 = 16'b0000000000000000; - parameter [15:0] CH1_TX_PCS_CFG6 = 16'b0000000000000000; - parameter [15:0] CH1_TX_PCS_CFG7 = 16'b0000000000000000; - parameter [15:0] CH1_TX_PCS_CFG8 = 16'b0000000000000000; - parameter [15:0] CH1_TX_PCS_CFG9 = 16'b0000000000000000; - parameter real DATARATE = 10.000; - parameter [15:0] DRPEN_CFG = 16'b0000000000000000; - parameter [15:0] FEC_CFG0 = 16'b0000000000000000; - parameter [15:0] FEC_CFG1 = 16'b0000000000000000; - parameter [15:0] FEC_CFG10 = 16'b0000000000000000; - parameter [15:0] FEC_CFG11 = 16'b0000000000000000; - parameter [15:0] FEC_CFG12 = 16'b0000000000000000; - parameter [15:0] FEC_CFG13 = 16'b0000000000000000; - parameter [15:0] FEC_CFG14 = 16'b0000000000000000; - parameter [15:0] FEC_CFG15 = 16'b0000000000000000; - parameter [15:0] FEC_CFG16 = 16'b0000000000000000; - parameter [15:0] FEC_CFG17 = 16'b0000000000000000; - parameter [15:0] FEC_CFG18 = 16'b0000000000000000; - parameter [15:0] FEC_CFG19 = 16'b0000000000000000; - parameter [15:0] FEC_CFG2 = 16'b0000000000000000; - parameter [15:0] FEC_CFG20 = 16'b0000000000000000; - parameter [15:0] FEC_CFG21 = 16'b0000000000000000; - parameter [15:0] FEC_CFG22 = 16'b0000000000000000; - parameter [15:0] FEC_CFG23 = 16'b0000000000000000; - parameter [15:0] FEC_CFG24 = 16'b0000000000000000; - parameter [15:0] FEC_CFG25 = 16'b0000000000000000; - parameter [15:0] FEC_CFG26 = 16'b0000000000000000; - parameter [15:0] FEC_CFG27 = 16'b0000000000000000; - parameter [15:0] FEC_CFG3 = 16'b0000000000000000; - parameter [15:0] FEC_CFG4 = 16'b0000000000000000; - parameter [15:0] FEC_CFG5 = 16'b0000000000000000; - parameter [15:0] FEC_CFG6 = 16'b0000000000000000; - parameter [15:0] FEC_CFG7 = 16'b0000000000000000; - parameter [15:0] FEC_CFG8 = 16'b0000000000000000; - parameter [15:0] FEC_CFG9 = 16'b0000000000000000; - parameter FEC_MODE = "BYPASS"; - parameter real INS_LOSS_NYQ = 20.000; - parameter integer INTERFACE_WIDTH = 64; - parameter MODULATION_MODE = "NRZ"; - parameter [15:0] PLL_CFG0 = 16'b0001100111110000; - parameter [15:0] PLL_CFG1 = 16'b0000111101110000; - parameter [15:0] PLL_CFG2 = 16'b1000000111101000; - parameter [15:0] PLL_CFG3 = 16'b0100000000000000; - parameter [15:0] PLL_CFG4 = 16'b0111111111101010; - parameter [15:0] PLL_CFG5 = 16'b0100101100111000; - parameter [15:0] PLL_CFG6 = 16'b0000000000100101; - parameter [15:0] PLL_CRS_CTRL_CFG0 = 16'b0000101100100000; - parameter [15:0] PLL_CRS_CTRL_CFG1 = 16'b1100010111010100; - parameter [0:0] PLL_IPS_PIN_EN = 1'b1; - parameter integer PLL_IPS_REFCLK_SEL = 0; - parameter [0:0] RCALSAP_TESTEN = 1'b0; - parameter [0:0] RCAL_APROBE = 1'b0; - parameter [15:0] RST_CFG = 16'b0000000000000010; - parameter [15:0] RST_PLL_CFG0 = 16'b0111011000010100; - parameter [15:0] SAP_CFG0 = 16'b0000000000000000; - parameter [15:0] SDM_CFG0 = 16'b0001100001000000; - parameter [15:0] SDM_CFG1 = 16'b0000000000000000; - parameter [15:0] SDM_CFG2 = 16'b0000000000000000; - parameter [15:0] SDM_SEED_CFG0 = 16'b0000000000000000; - parameter [15:0] SDM_SEED_CFG1 = 16'b0000000000000000; - parameter SIM_DEVICE = "ULTRASCALE_PLUS_ES1"; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter integer TX_AMPLITUDE_SWING = 250; - output [27:0] CH0_AXISTDATA; - output CH0_AXISTLAST; - output CH0_AXISTVALID; - output [31:0] CH0_DMONITOROUT; - output CH0_DMONITOROUTCLK; - output CH0_GTMTXN; - output CH0_GTMTXP; - output [15:0] CH0_PCSRSVDOUT; - output [15:0] CH0_PMARSVDOUT; - output CH0_RESETEXCEPTION; - output [2:0] CH0_RXBUFSTATUS; - output [255:0] CH0_RXDATA; - output [3:0] CH0_RXDATAFLAGS; - output CH0_RXDATAISAM; - output CH0_RXDATASTART; - output CH0_RXOUTCLK; - output CH0_RXPMARESETDONE; - output CH0_RXPRBSERR; - output CH0_RXPRBSLOCKED; - output CH0_RXPRGDIVRESETDONE; - output CH0_RXPROGDIVCLK; - output CH0_RXRESETDONE; - output [1:0] CH0_TXBUFSTATUS; - output CH0_TXOUTCLK; - output CH0_TXPMARESETDONE; - output CH0_TXPRGDIVRESETDONE; - output CH0_TXPROGDIVCLK; - output CH0_TXRESETDONE; - output [27:0] CH1_AXISTDATA; - output CH1_AXISTLAST; - output CH1_AXISTVALID; - output [31:0] CH1_DMONITOROUT; - output CH1_DMONITOROUTCLK; - output CH1_GTMTXN; - output CH1_GTMTXP; - output [15:0] CH1_PCSRSVDOUT; - output [15:0] CH1_PMARSVDOUT; - output CH1_RESETEXCEPTION; - output [2:0] CH1_RXBUFSTATUS; - output [255:0] CH1_RXDATA; - output [3:0] CH1_RXDATAFLAGS; - output CH1_RXDATAISAM; - output CH1_RXDATASTART; - output CH1_RXOUTCLK; - output CH1_RXPMARESETDONE; - output CH1_RXPRBSERR; - output CH1_RXPRBSLOCKED; - output CH1_RXPRGDIVRESETDONE; - output CH1_RXPROGDIVCLK; - output CH1_RXRESETDONE; - output [1:0] CH1_TXBUFSTATUS; - output CH1_TXOUTCLK; - output CH1_TXPMARESETDONE; - output CH1_TXPRGDIVRESETDONE; - output CH1_TXPROGDIVCLK; - output CH1_TXRESETDONE; - output CLKTESTSIG2PAD; - output DMONITOROUTPLLCLK; - output [15:0] DRPDO; - output DRPRDY; - output FECRX0ALIGNED; - output FECRX0CORRCWINC; - output FECRX0CWINC; - output FECRX0UNCORRCWINC; - output FECRX1ALIGNED; - output FECRX1CORRCWINC; - output FECRX1CWINC; - output FECRX1UNCORRCWINC; - output [7:0] FECRXLN0BITERR0TO1INC; - output [7:0] FECRXLN0BITERR1TO0INC; - output [14:0] FECRXLN0DLY; - output [3:0] FECRXLN0ERRCNTINC; - output [1:0] FECRXLN0MAPPING; - output [7:0] FECRXLN1BITERR0TO1INC; - output [7:0] FECRXLN1BITERR1TO0INC; - output [14:0] FECRXLN1DLY; - output [3:0] FECRXLN1ERRCNTINC; - output [1:0] FECRXLN1MAPPING; - output [7:0] FECRXLN2BITERR0TO1INC; - output [7:0] FECRXLN2BITERR1TO0INC; - output [14:0] FECRXLN2DLY; - output [3:0] FECRXLN2ERRCNTINC; - output [1:0] FECRXLN2MAPPING; - output [7:0] FECRXLN3BITERR0TO1INC; - output [7:0] FECRXLN3BITERR1TO0INC; - output [14:0] FECRXLN3DLY; - output [3:0] FECRXLN3ERRCNTINC; - output [1:0] FECRXLN3MAPPING; - output FECTRXLN0LOCK; - output FECTRXLN1LOCK; - output FECTRXLN2LOCK; - output FECTRXLN3LOCK; - output GTPOWERGOOD; - output PLLFBCLKLOST; - output PLLLOCK; - output PLLREFCLKLOST; - output PLLREFCLKMONITOR; - output PLLRESETDONE; - output [15:0] PLLRSVDOUT; - output RCALCMP; - output [4:0] RCALOUT; - output RXRECCLK0; - output RXRECCLK1; - input BGBYPASSB; - input BGMONITORENB; - input BGPDB; - input [4:0] BGRCALOVRD; - input BGRCALOVRDENB; - input CH0_AXISEN; - input CH0_AXISRST; - input CH0_AXISTRDY; - input CH0_CFGRESET; - input CH0_DMONFIFORESET; - input CH0_DMONITORCLK; - input CH0_GTMRXN; - input CH0_GTMRXP; - input CH0_GTRXRESET; - input CH0_GTTXRESET; - input [2:0] CH0_LOOPBACK; - input [15:0] CH0_PCSRSVDIN; - input [15:0] CH0_PMARSVDIN; - input CH0_RESETOVRD; - input CH0_RXADAPTRESET; - input CH0_RXADCCALRESET; - input CH0_RXADCCLKGENRESET; - input CH0_RXBUFRESET; - input CH0_RXCDRFREQOS; - input CH0_RXCDRFRRESET; - input CH0_RXCDRHOLD; - input CH0_RXCDRINCPCTRL; - input CH0_RXCDROVRDEN; - input CH0_RXCDRPHRESET; - input CH0_RXDFERESET; - input CH0_RXDSPRESET; - input CH0_RXEQTRAINING; - input CH0_RXEYESCANRESET; - input CH0_RXFECRESET; - input [2:0] CH0_RXOUTCLKSEL; - input CH0_RXPCSRESET; - input [3:0] CH0_RXPCSRESETMASK; - input CH0_RXPMARESET; - input [7:0] CH0_RXPMARESETMASK; - input CH0_RXPOLARITY; - input CH0_RXPRBSCNTSTOP; - input CH0_RXPRBSCSCNTRST; - input [3:0] CH0_RXPRBSPTN; - input CH0_RXPROGDIVRESET; - input CH0_RXQPRBSEN; - input [1:0] CH0_RXRESETMODE; - input CH0_RXSPCSEQADV; - input CH0_RXUSRCLK; - input CH0_RXUSRCLK2; - input CH0_RXUSRRDY; - input CH0_RXUSRSTART; - input CH0_RXUSRSTOP; - input CH0_TXCKALRESET; - input [5:0] CH0_TXCTLFIRDAT; - input [255:0] CH0_TXDATA; - input CH0_TXDATASTART; - input [4:0] CH0_TXDRVAMP; - input [5:0] CH0_TXEMPMAIN; - input [4:0] CH0_TXEMPPOST; - input [4:0] CH0_TXEMPPRE; - input [3:0] CH0_TXEMPPRE2; - input CH0_TXFECRESET; - input CH0_TXINHIBIT; - input CH0_TXMUXDCDEXHOLD; - input CH0_TXMUXDCDORWREN; - input [2:0] CH0_TXOUTCLKSEL; - input CH0_TXPCSRESET; - input [1:0] CH0_TXPCSRESETMASK; - input CH0_TXPMARESET; - input [1:0] CH0_TXPMARESETMASK; - input CH0_TXPOLARITY; - input CH0_TXPRBSINERR; - input [3:0] CH0_TXPRBSPTN; - input CH0_TXPROGDIVRESET; - input CH0_TXQPRBSEN; - input [1:0] CH0_TXRESETMODE; - input CH0_TXSPCSEQADV; - input CH0_TXUSRCLK; - input CH0_TXUSRCLK2; - input CH0_TXUSRRDY; - input CH1_AXISEN; - input CH1_AXISRST; - input CH1_AXISTRDY; - input CH1_CFGRESET; - input CH1_DMONFIFORESET; - input CH1_DMONITORCLK; - input CH1_GTMRXN; - input CH1_GTMRXP; - input CH1_GTRXRESET; - input CH1_GTTXRESET; - input [2:0] CH1_LOOPBACK; - input [15:0] CH1_PCSRSVDIN; - input [15:0] CH1_PMARSVDIN; - input CH1_RESETOVRD; - input CH1_RXADAPTRESET; - input CH1_RXADCCALRESET; - input CH1_RXADCCLKGENRESET; - input CH1_RXBUFRESET; - input CH1_RXCDRFREQOS; - input CH1_RXCDRFRRESET; - input CH1_RXCDRHOLD; - input CH1_RXCDRINCPCTRL; - input CH1_RXCDROVRDEN; - input CH1_RXCDRPHRESET; - input CH1_RXDFERESET; - input CH1_RXDSPRESET; - input CH1_RXEQTRAINING; - input CH1_RXEYESCANRESET; - input CH1_RXFECRESET; - input [2:0] CH1_RXOUTCLKSEL; - input CH1_RXPCSRESET; - input [3:0] CH1_RXPCSRESETMASK; - input CH1_RXPMARESET; - input [7:0] CH1_RXPMARESETMASK; - input CH1_RXPOLARITY; - input CH1_RXPRBSCNTSTOP; - input CH1_RXPRBSCSCNTRST; - input [3:0] CH1_RXPRBSPTN; - input CH1_RXPROGDIVRESET; - input CH1_RXQPRBSEN; - input [1:0] CH1_RXRESETMODE; - input CH1_RXSPCSEQADV; - input CH1_RXUSRCLK; - input CH1_RXUSRCLK2; - input CH1_RXUSRRDY; - input CH1_RXUSRSTART; - input CH1_RXUSRSTOP; - input CH1_TXCKALRESET; - input [5:0] CH1_TXCTLFIRDAT; - input [255:0] CH1_TXDATA; - input CH1_TXDATASTART; - input [4:0] CH1_TXDRVAMP; - input [5:0] CH1_TXEMPMAIN; - input [4:0] CH1_TXEMPPOST; - input [4:0] CH1_TXEMPPRE; - input [3:0] CH1_TXEMPPRE2; - input CH1_TXFECRESET; - input CH1_TXINHIBIT; - input CH1_TXMUXDCDEXHOLD; - input CH1_TXMUXDCDORWREN; - input [2:0] CH1_TXOUTCLKSEL; - input CH1_TXPCSRESET; - input [1:0] CH1_TXPCSRESETMASK; - input CH1_TXPMARESET; - input [1:0] CH1_TXPMARESETMASK; - input CH1_TXPOLARITY; - input CH1_TXPRBSINERR; - input [3:0] CH1_TXPRBSPTN; - input CH1_TXPROGDIVRESET; - input CH1_TXQPRBSEN; - input [1:0] CH1_TXRESETMODE; - input CH1_TXSPCSEQADV; - input CH1_TXUSRCLK; - input CH1_TXUSRCLK2; - input CH1_TXUSRRDY; - input [10:0] DRPADDR; - input DRPCLK; - input [15:0] DRPDI; - input DRPEN; - input DRPRST; - input DRPWE; - input FECCTRLRX0BITSLIPFS; - input FECCTRLRX1BITSLIPFS; - input GTGREFCLK2PLL; - input GTNORTHREFCLK; - input GTREFCLK; - input GTSOUTHREFCLK; - input [7:0] PLLFBDIV; - input PLLMONCLK; - input PLLPD; - input [2:0] PLLREFCLKSEL; - input PLLRESET; - input PLLRESETBYPASSMODE; - input [1:0] PLLRESETMASK; - input [15:0] PLLRSVDIN; - input RCALENB; - input [25:0] SDMDATA; - input SDMTOGGLE; -endmodule - -module IBUFDS_GTM (...); - parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; - parameter integer REFCLK_HROW_CK_SEL = 0; - parameter integer REFCLK_ICNTL_RX = 0; - output O; - output ODIV2; - input CEB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module OBUFDS_GTM (...); - parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; - parameter integer REFCLK_ICNTL_TX = 0; - (* iopad_external_pin *) - output O; - (* iopad_external_pin *) - output OB; - input CEB; - input I; -endmodule - -module OBUFDS_GTM_ADV (...); - parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; - parameter integer REFCLK_ICNTL_TX = 0; - parameter [1:0] RXRECCLK_SEL = 2'b00; - (* iopad_external_pin *) - output O; - (* iopad_external_pin *) - output OB; - input CEB; - input [3:0] I; -endmodule - -module HSDAC (...); - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter integer XPA_CFG0 = 0; - parameter integer XPA_CFG1 = 0; - parameter integer XPA_NUM_DACS = 0; - parameter integer XPA_NUM_DUCS = 0; - parameter XPA_PLL_USED = "No"; - parameter integer XPA_SAMPLE_RATE_MSPS = 0; - output CLK_DAC; - output [15:0] DOUT; - output DRDY; - output PLL_DMON_OUT; - output PLL_REFCLK_OUT; - output [15:0] STATUS_COMMON; - output [15:0] STATUS_DAC0; - output [15:0] STATUS_DAC1; - output [15:0] STATUS_DAC2; - output [15:0] STATUS_DAC3; - output SYSREF_OUT_NORTH; - output SYSREF_OUT_SOUTH; - output VOUT0_N; - output VOUT0_P; - output VOUT1_N; - output VOUT1_P; - output VOUT2_N; - output VOUT2_P; - output VOUT3_N; - output VOUT3_P; - input CLK_FIFO_LM; - input [15:0] CONTROL_COMMON; - input [15:0] CONTROL_DAC0; - input [15:0] CONTROL_DAC1; - input [15:0] CONTROL_DAC2; - input [15:0] CONTROL_DAC3; - input DAC_CLK_N; - input DAC_CLK_P; - input [11:0] DADDR; - input [255:0] DATA_DAC0; - input [255:0] DATA_DAC1; - input [255:0] DATA_DAC2; - input [255:0] DATA_DAC3; - input DCLK; - input DEN; - input [15:0] DI; - input DWE; - input FABRIC_CLK; - input PLL_MONCLK; - input PLL_REFCLK_IN; - input SYSREF_IN_NORTH; - input SYSREF_IN_SOUTH; - input SYSREF_N; - input SYSREF_P; -endmodule - -module HSADC (...); - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter integer XPA_CFG0 = 0; - parameter integer XPA_CFG1 = 0; - parameter XPA_NUM_ADCS = "0"; - parameter integer XPA_NUM_DDCS = 0; - parameter XPA_PLL_USED = "No"; - parameter integer XPA_SAMPLE_RATE_MSPS = 0; - output CLK_ADC; - output [127:0] DATA_ADC0; - output [127:0] DATA_ADC1; - output [127:0] DATA_ADC2; - output [127:0] DATA_ADC3; - output [15:0] DOUT; - output DRDY; - output PLL_DMON_OUT; - output PLL_REFCLK_OUT; - output [15:0] STATUS_ADC0; - output [15:0] STATUS_ADC1; - output [15:0] STATUS_ADC2; - output [15:0] STATUS_ADC3; - output [15:0] STATUS_COMMON; - output SYSREF_OUT_NORTH; - output SYSREF_OUT_SOUTH; - input ADC_CLK_N; - input ADC_CLK_P; - input CLK_FIFO_LM; - input [15:0] CONTROL_ADC0; - input [15:0] CONTROL_ADC1; - input [15:0] CONTROL_ADC2; - input [15:0] CONTROL_ADC3; - input [15:0] CONTROL_COMMON; - input [11:0] DADDR; - input DCLK; - input DEN; - input [15:0] DI; - input DWE; - input FABRIC_CLK; - input PLL_MONCLK; - input PLL_REFCLK_IN; - input SYSREF_IN_NORTH; - input SYSREF_IN_SOUTH; - input SYSREF_N; - input SYSREF_P; - input VIN0_N; - input VIN0_P; - input VIN1_N; - input VIN1_P; - input VIN2_N; - input VIN2_P; - input VIN3_N; - input VIN3_P; - input VIN_I01_N; - input VIN_I01_P; - input VIN_I23_N; - input VIN_I23_P; -endmodule - -module RFDAC (...); - parameter integer LD_DEVICE = 0; - parameter integer OPT_CLK_DIST = 0; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter integer XPA_ACTIVE_DUTYCYCLE = 100; - parameter integer XPA_CFG0 = 0; - parameter integer XPA_CFG1 = 0; - parameter integer XPA_CFG2 = 0; - parameter integer XPA_NUM_DACS = 0; - parameter integer XPA_NUM_DUCS = 0; - parameter XPA_PLL_USED = "EXTERNAL"; - parameter integer XPA_SAMPLE_RATE_MSPS = 0; - output CLK_DAC; - output CLK_DIST_OUT_NORTH; - output CLK_DIST_OUT_SOUTH; - output [15:0] DOUT; - output DRDY; - output PLL_DMON_OUT; - output PLL_REFCLK_OUT; - output [23:0] STATUS_COMMON; - output [23:0] STATUS_DAC0; - output [23:0] STATUS_DAC1; - output [23:0] STATUS_DAC2; - output [23:0] STATUS_DAC3; - output SYSREF_OUT_NORTH; - output SYSREF_OUT_SOUTH; - output T1_ALLOWED_SOUTH; - output VOUT0_N; - output VOUT0_P; - output VOUT1_N; - output VOUT1_P; - output VOUT2_N; - output VOUT2_P; - output VOUT3_N; - output VOUT3_P; - input CLK_DIST_IN_NORTH; - input CLK_DIST_IN_SOUTH; - input CLK_FIFO_LM; - input [15:0] CONTROL_COMMON; - input [15:0] CONTROL_DAC0; - input [15:0] CONTROL_DAC1; - input [15:0] CONTROL_DAC2; - input [15:0] CONTROL_DAC3; - input DAC_CLK_N; - input DAC_CLK_P; - input [11:0] DADDR; - input [255:0] DATA_DAC0; - input [255:0] DATA_DAC1; - input [255:0] DATA_DAC2; - input [255:0] DATA_DAC3; - input DCLK; - input DEN; - input [15:0] DI; - input DWE; - input FABRIC_CLK; - input PLL_MONCLK; - input PLL_REFCLK_IN; - input SYSREF_IN_NORTH; - input SYSREF_IN_SOUTH; - input SYSREF_N; - input SYSREF_P; - input T1_ALLOWED_NORTH; -endmodule - -module RFADC (...); - parameter integer LD_DEVICE = 0; - parameter integer OPT_ANALOG = 0; - parameter integer OPT_CLK_DIST = 0; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter integer XPA_ACTIVE_DUTYCYCLE = 100; - parameter integer XPA_CFG0 = 0; - parameter integer XPA_CFG1 = 0; - parameter integer XPA_CFG2 = 0; - parameter XPA_NUM_ADCS = "0"; - parameter integer XPA_NUM_DDCS = 0; - parameter XPA_PLL_USED = "EXTERNAL"; - parameter integer XPA_SAMPLE_RATE_MSPS = 0; - output CLK_ADC; - output CLK_DIST_OUT_NORTH; - output CLK_DIST_OUT_SOUTH; - output [191:0] DATA_ADC0; - output [191:0] DATA_ADC1; - output [191:0] DATA_ADC2; - output [191:0] DATA_ADC3; - output [15:0] DOUT; - output DRDY; - output PLL_DMON_OUT; - output PLL_REFCLK_OUT; - output [23:0] STATUS_ADC0; - output [23:0] STATUS_ADC1; - output [23:0] STATUS_ADC2; - output [23:0] STATUS_ADC3; - output [23:0] STATUS_COMMON; - output SYSREF_OUT_NORTH; - output SYSREF_OUT_SOUTH; - output T1_ALLOWED_SOUTH; - input ADC_CLK_N; - input ADC_CLK_P; - input CLK_DIST_IN_NORTH; - input CLK_DIST_IN_SOUTH; - input CLK_FIFO_LM; - input [15:0] CONTROL_ADC0; - input [15:0] CONTROL_ADC1; - input [15:0] CONTROL_ADC2; - input [15:0] CONTROL_ADC3; - input [15:0] CONTROL_COMMON; - input [11:0] DADDR; - input DCLK; - input DEN; - input [15:0] DI; - input DWE; - input FABRIC_CLK; - input PLL_MONCLK; - input PLL_REFCLK_IN; - input SYSREF_IN_NORTH; - input SYSREF_IN_SOUTH; - input SYSREF_N; - input SYSREF_P; - input T1_ALLOWED_NORTH; - input VIN0_N; - input VIN0_P; - input VIN1_N; - input VIN1_P; - input VIN2_N; - input VIN2_P; - input VIN3_N; - input VIN3_P; - input VIN_I01_N; - input VIN_I01_P; - input VIN_I23_N; - input VIN_I23_P; -endmodule - -module PCIE_A1 (...); - parameter [31:0] BAR0 = 32'h00000000; - parameter [31:0] BAR1 = 32'h00000000; - parameter [31:0] BAR2 = 32'h00000000; - parameter [31:0] BAR3 = 32'h00000000; - parameter [31:0] BAR4 = 32'h00000000; - parameter [31:0] BAR5 = 32'h00000000; - parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000; - parameter [23:0] CLASS_CODE = 24'h000000; - parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 7; - parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 7; - parameter DEV_CAP_EXT_TAG_SUPPORTED = "FALSE"; - parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2; - parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0; - parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE"; - parameter DISABLE_BAR_FILTERING = "FALSE"; - parameter DISABLE_ID_CHECK = "FALSE"; - parameter DISABLE_SCRAMBLING = "FALSE"; - parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE"; - parameter [21:0] EXPANSION_ROM = 22'h000000; - parameter FAST_TRAIN = "FALSE"; - parameter integer GTP_SEL = 0; - parameter integer LINK_CAP_ASPM_SUPPORT = 1; - parameter integer LINK_CAP_L0S_EXIT_LATENCY = 7; - parameter integer LINK_CAP_L1_EXIT_LATENCY = 7; - parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "FALSE"; - parameter [14:0] LL_ACK_TIMEOUT = 15'h0204; - parameter LL_ACK_TIMEOUT_EN = "FALSE"; - parameter [14:0] LL_REPLAY_TIMEOUT = 15'h060D; - parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; - parameter integer MSI_CAP_MULTIMSGCAP = 0; - parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0; - parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h1; - parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0; - parameter [4:0] PCIE_CAP_INT_MSG_NUM = 5'b00000; - parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE"; - parameter [11:0] PCIE_GENERIC = 12'h000; - parameter PLM_AUTO_CONFIG = "FALSE"; - parameter integer PM_CAP_AUXCURRENT = 0; - parameter PM_CAP_D1SUPPORT = "TRUE"; - parameter PM_CAP_D2SUPPORT = "TRUE"; - parameter PM_CAP_DSI = "FALSE"; - parameter [4:0] PM_CAP_PMESUPPORT = 5'b01111; - parameter PM_CAP_PME_CLOCK = "FALSE"; - parameter integer PM_CAP_VERSION = 3; - parameter [7:0] PM_DATA0 = 8'h1E; - parameter [7:0] PM_DATA1 = 8'h1E; - parameter [7:0] PM_DATA2 = 8'h1E; - parameter [7:0] PM_DATA3 = 8'h1E; - parameter [7:0] PM_DATA4 = 8'h1E; - parameter [7:0] PM_DATA5 = 8'h1E; - parameter [7:0] PM_DATA6 = 8'h1E; - parameter [7:0] PM_DATA7 = 8'h1E; - parameter [1:0] PM_DATA_SCALE0 = 2'b01; - parameter [1:0] PM_DATA_SCALE1 = 2'b01; - parameter [1:0] PM_DATA_SCALE2 = 2'b01; - parameter [1:0] PM_DATA_SCALE3 = 2'b01; - parameter [1:0] PM_DATA_SCALE4 = 2'b01; - parameter [1:0] PM_DATA_SCALE5 = 2'b01; - parameter [1:0] PM_DATA_SCALE6 = 2'b01; - parameter [1:0] PM_DATA_SCALE7 = 2'b01; - parameter SIM_VERSION = "1.0"; - parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE"; - parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE"; - parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE"; - parameter integer TL_RX_RAM_RADDR_LATENCY = 1; - parameter integer TL_RX_RAM_RDATA_LATENCY = 2; - parameter integer TL_RX_RAM_WRITE_LATENCY = 0; - parameter TL_TFC_DISABLE = "FALSE"; - parameter TL_TX_CHECKS_DISABLE = "FALSE"; - parameter integer TL_TX_RAM_RADDR_LATENCY = 0; - parameter integer TL_TX_RAM_RDATA_LATENCY = 2; - parameter USR_CFG = "FALSE"; - parameter USR_EXT_CFG = "FALSE"; - parameter VC0_CPL_INFINITE = "TRUE"; - parameter [11:0] VC0_RX_RAM_LIMIT = 12'h01E; - parameter integer VC0_TOTAL_CREDITS_CD = 104; - parameter integer VC0_TOTAL_CREDITS_CH = 36; - parameter integer VC0_TOTAL_CREDITS_NPH = 8; - parameter integer VC0_TOTAL_CREDITS_PD = 288; - parameter integer VC0_TOTAL_CREDITS_PH = 32; - parameter integer VC0_TX_LASTPACKET = 31; - output CFGCOMMANDBUSMASTERENABLE; - output CFGCOMMANDINTERRUPTDISABLE; - output CFGCOMMANDIOENABLE; - output CFGCOMMANDMEMENABLE; - output CFGCOMMANDSERREN; - output CFGDEVCONTROLAUXPOWEREN; - output CFGDEVCONTROLCORRERRREPORTINGEN; - output CFGDEVCONTROLENABLERO; - output CFGDEVCONTROLEXTTAGEN; - output CFGDEVCONTROLFATALERRREPORTINGEN; - output CFGDEVCONTROLNONFATALREPORTINGEN; - output CFGDEVCONTROLNOSNOOPEN; - output CFGDEVCONTROLPHANTOMEN; - output CFGDEVCONTROLURERRREPORTINGEN; - output CFGDEVSTATUSCORRERRDETECTED; - output CFGDEVSTATUSFATALERRDETECTED; - output CFGDEVSTATUSNONFATALERRDETECTED; - output CFGDEVSTATUSURDETECTED; - output CFGERRCPLRDYN; - output CFGINTERRUPTMSIENABLE; - output CFGINTERRUPTRDYN; - output CFGLINKCONTOLRCB; - output CFGLINKCONTROLCOMMONCLOCK; - output CFGLINKCONTROLEXTENDEDSYNC; - output CFGRDWRDONEN; - output CFGTOTURNOFFN; - output DBGBADDLLPSTATUS; - output DBGBADTLPLCRC; - output DBGBADTLPSEQNUM; - output DBGBADTLPSTATUS; - output DBGDLPROTOCOLSTATUS; - output DBGFCPROTOCOLERRSTATUS; - output DBGMLFRMDLENGTH; - output DBGMLFRMDMPS; - output DBGMLFRMDTCVC; - output DBGMLFRMDTLPSTATUS; - output DBGMLFRMDUNRECTYPE; - output DBGPOISTLPSTATUS; - output DBGRCVROVERFLOWSTATUS; - output DBGREGDETECTEDCORRECTABLE; - output DBGREGDETECTEDFATAL; - output DBGREGDETECTEDNONFATAL; - output DBGREGDETECTEDUNSUPPORTED; - output DBGRPLYROLLOVERSTATUS; - output DBGRPLYTIMEOUTSTATUS; - output DBGURNOBARHIT; - output DBGURPOISCFGWR; - output DBGURSTATUS; - output DBGURUNSUPMSG; - output MIMRXREN; - output MIMRXWEN; - output MIMTXREN; - output MIMTXWEN; - output PIPEGTTXELECIDLEA; - output PIPEGTTXELECIDLEB; - output PIPERXPOLARITYA; - output PIPERXPOLARITYB; - output PIPERXRESETA; - output PIPERXRESETB; - output PIPETXRCVRDETA; - output PIPETXRCVRDETB; - output RECEIVEDHOTRESET; - output TRNLNKUPN; - output TRNREOFN; - output TRNRERRFWDN; - output TRNRSOFN; - output TRNRSRCDSCN; - output TRNRSRCRDYN; - output TRNTCFGREQN; - output TRNTDSTRDYN; - output TRNTERRDROPN; - output USERRSTN; - output [11:0] MIMRXRADDR; - output [11:0] MIMRXWADDR; - output [11:0] MIMTXRADDR; - output [11:0] MIMTXWADDR; - output [11:0] TRNFCCPLD; - output [11:0] TRNFCNPD; - output [11:0] TRNFCPD; - output [15:0] PIPETXDATAA; - output [15:0] PIPETXDATAB; - output [1:0] CFGLINKCONTROLASPMCONTROL; - output [1:0] PIPEGTPOWERDOWNA; - output [1:0] PIPEGTPOWERDOWNB; - output [1:0] PIPETXCHARDISPMODEA; - output [1:0] PIPETXCHARDISPMODEB; - output [1:0] PIPETXCHARDISPVALA; - output [1:0] PIPETXCHARDISPVALB; - output [1:0] PIPETXCHARISKA; - output [1:0] PIPETXCHARISKB; - output [2:0] CFGDEVCONTROLMAXPAYLOAD; - output [2:0] CFGDEVCONTROLMAXREADREQ; - output [2:0] CFGFUNCTIONNUMBER; - output [2:0] CFGINTERRUPTMMENABLE; - output [2:0] CFGPCIELINKSTATEN; - output [31:0] CFGDO; - output [31:0] TRNRD; - output [34:0] MIMRXWDATA; - output [35:0] MIMTXWDATA; - output [4:0] CFGDEVICENUMBER; - output [4:0] CFGLTSSMSTATE; - output [5:0] TRNTBUFAV; - output [6:0] TRNRBARHITN; - output [7:0] CFGBUSNUMBER; - output [7:0] CFGINTERRUPTDO; - output [7:0] TRNFCCPLH; - output [7:0] TRNFCNPH; - output [7:0] TRNFCPH; - input CFGERRCORN; - input CFGERRCPLABORTN; - input CFGERRCPLTIMEOUTN; - input CFGERRECRCN; - input CFGERRLOCKEDN; - input CFGERRPOSTEDN; - input CFGERRURN; - input CFGINTERRUPTASSERTN; - input CFGINTERRUPTN; - input CFGPMWAKEN; - input CFGRDENN; - input CFGTRNPENDINGN; - input CFGTURNOFFOKN; - input CLOCKLOCKED; - input MGTCLK; - input PIPEGTRESETDONEA; - input PIPEGTRESETDONEB; - input PIPEPHYSTATUSA; - input PIPEPHYSTATUSB; - input PIPERXENTERELECIDLEA; - input PIPERXENTERELECIDLEB; - input SYSRESETN; - input TRNRDSTRDYN; - input TRNRNPOKN; - input TRNTCFGGNTN; - input TRNTEOFN; - input TRNTERRFWDN; - input TRNTSOFN; - input TRNTSRCDSCN; - input TRNTSRCRDYN; - input TRNTSTRN; - input USERCLK; - input [15:0] CFGDEVID; - input [15:0] CFGSUBSYSID; - input [15:0] CFGSUBSYSVENID; - input [15:0] CFGVENID; - input [15:0] PIPERXDATAA; - input [15:0] PIPERXDATAB; - input [1:0] PIPERXCHARISKA; - input [1:0] PIPERXCHARISKB; - input [2:0] PIPERXSTATUSA; - input [2:0] PIPERXSTATUSB; - input [2:0] TRNFCSEL; - input [31:0] TRNTD; - input [34:0] MIMRXRDATA; - input [35:0] MIMTXRDATA; - input [47:0] CFGERRTLPCPLHEADER; - input [63:0] CFGDSN; - input [7:0] CFGINTERRUPTDI; - input [7:0] CFGREVID; - input [9:0] CFGDWADDR; -endmodule - -module PCIE_EP (...); - parameter BAR0EXIST = "TRUE"; - parameter BAR0PREFETCHABLE = "TRUE"; - parameter BAR1EXIST = "FALSE"; - parameter BAR1PREFETCHABLE = "FALSE"; - parameter BAR2EXIST = "FALSE"; - parameter BAR2PREFETCHABLE = "FALSE"; - parameter BAR3EXIST = "FALSE"; - parameter BAR3PREFETCHABLE = "FALSE"; - parameter BAR4EXIST = "FALSE"; - parameter BAR4PREFETCHABLE = "FALSE"; - parameter BAR5EXIST = "FALSE"; - parameter BAR5PREFETCHABLE = "FALSE"; - parameter CLKDIVIDED = "FALSE"; - parameter INFINITECOMPLETIONS = "TRUE"; - parameter LINKSTATUSSLOTCLOCKCONFIG = "FALSE"; - parameter PBCAPABILITYSYSTEMALLOCATED = "FALSE"; - parameter PMCAPABILITYD1SUPPORT = "FALSE"; - parameter PMCAPABILITYD2SUPPORT = "FALSE"; - parameter PMCAPABILITYDSI = "TRUE"; - parameter RESETMODE = "FALSE"; - parameter [10:0] VC0TOTALCREDITSCD = 11'h0; - parameter [10:0] VC0TOTALCREDITSPD = 11'h34; - parameter [10:0] VC1TOTALCREDITSCD = 11'h0; - parameter [10:0] VC1TOTALCREDITSPD = 11'h0; - parameter [11:0] AERBASEPTR = 12'h110; - parameter [11:0] AERCAPABILITYNEXTPTR = 12'h138; - parameter [11:0] DSNBASEPTR = 12'h148; - parameter [11:0] DSNCAPABILITYNEXTPTR = 12'h154; - parameter [11:0] MSIBASEPTR = 12'h48; - parameter [11:0] PBBASEPTR = 12'h138; - parameter [11:0] PBCAPABILITYNEXTPTR = 12'h148; - parameter [11:0] PMBASEPTR = 12'h40; - parameter [11:0] RETRYRAMSIZE = 12'h9; - parameter [11:0] VCBASEPTR = 12'h154; - parameter [11:0] VCCAPABILITYNEXTPTR = 12'h0; - parameter [12:0] VC0RXFIFOBASEC = 13'h98; - parameter [12:0] VC0RXFIFOBASENP = 13'h80; - parameter [12:0] VC0RXFIFOBASEP = 13'h0; - parameter [12:0] VC0RXFIFOLIMITC = 13'h117; - parameter [12:0] VC0RXFIFOLIMITNP = 13'h97; - parameter [12:0] VC0RXFIFOLIMITP = 13'h7f; - parameter [12:0] VC0TXFIFOBASEC = 13'h98; - parameter [12:0] VC0TXFIFOBASENP = 13'h80; - parameter [12:0] VC0TXFIFOBASEP = 13'h0; - parameter [12:0] VC0TXFIFOLIMITC = 13'h117; - parameter [12:0] VC0TXFIFOLIMITNP = 13'h97; - parameter [12:0] VC0TXFIFOLIMITP = 13'h7f; - parameter [12:0] VC1RXFIFOBASEC = 13'h118; - parameter [12:0] VC1RXFIFOBASENP = 13'h118; - parameter [12:0] VC1RXFIFOBASEP = 13'h118; - parameter [12:0] VC1RXFIFOLIMITC = 13'h118; - parameter [12:0] VC1RXFIFOLIMITNP = 13'h118; - parameter [12:0] VC1RXFIFOLIMITP = 13'h118; - parameter [12:0] VC1TXFIFOBASEC = 13'h118; - parameter [12:0] VC1TXFIFOBASENP = 13'h118; - parameter [12:0] VC1TXFIFOBASEP = 13'h118; - parameter [12:0] VC1TXFIFOLIMITC = 13'h118; - parameter [12:0] VC1TXFIFOLIMITNP = 13'h118; - parameter [12:0] VC1TXFIFOLIMITP = 13'h118; - parameter [15:0] DEVICEID = 16'h5050; - parameter [15:0] SUBSYSTEMID = 16'h5050; - parameter [15:0] SUBSYSTEMVENDORID = 16'h10EE; - parameter [15:0] VENDORID = 16'h10EE; - parameter [1:0] LINKCAPABILITYASPMSUPPORT = 2'h1; - parameter [1:0] PBCAPABILITYDW0DATASCALE = 2'h0; - parameter [1:0] PBCAPABILITYDW0PMSTATE = 2'h0; - parameter [1:0] PBCAPABILITYDW1DATASCALE = 2'h0; - parameter [1:0] PBCAPABILITYDW1PMSTATE = 2'h0; - parameter [1:0] PBCAPABILITYDW2DATASCALE = 2'h0; - parameter [1:0] PBCAPABILITYDW2PMSTATE = 2'h0; - parameter [1:0] PBCAPABILITYDW3DATASCALE = 2'h0; - parameter [1:0] PBCAPABILITYDW3PMSTATE = 2'h0; - parameter [23:0] CLASSCODE = 24'h058000; - parameter [2:0] DEVICECAPABILITYENDPOINTL0SLATENCY = 3'h0; - parameter [2:0] DEVICECAPABILITYENDPOINTL1LATENCY = 3'h0; - parameter [2:0] MSICAPABILITYMULTIMSGCAP = 3'h0; - parameter [2:0] PBCAPABILITYDW0PMSUBSTATE = 3'h0; - parameter [2:0] PBCAPABILITYDW0POWERRAIL = 3'h0; - parameter [2:0] PBCAPABILITYDW0TYPE = 3'h0; - parameter [2:0] PBCAPABILITYDW1PMSUBSTATE = 3'h0; - parameter [2:0] PBCAPABILITYDW1POWERRAIL = 3'h0; - parameter [2:0] PBCAPABILITYDW1TYPE = 3'h0; - parameter [2:0] PBCAPABILITYDW2PMSUBSTATE = 3'h0; - parameter [2:0] PBCAPABILITYDW2POWERRAIL = 3'h0; - parameter [2:0] PBCAPABILITYDW2TYPE = 3'h0; - parameter [2:0] PBCAPABILITYDW3PMSUBSTATE = 3'h0; - parameter [2:0] PBCAPABILITYDW3POWERRAIL = 3'h0; - parameter [2:0] PBCAPABILITYDW3TYPE = 3'h0; - parameter [2:0] PMCAPABILITYAUXCURRENT = 3'h0; - parameter [2:0] PORTVCCAPABILITYEXTENDEDVCCOUNT = 3'h0; - parameter [31:0] CARDBUSCISPOINTER = 32'h0; - parameter [3:0] XPDEVICEPORTTYPE = 4'h0; - parameter [4:0] PMCAPABILITYPMESUPPORT = 5'h0; - parameter [5:0] BAR0MASKWIDTH = 6'h14; - parameter [5:0] BAR1MASKWIDTH = 6'h0; - parameter [5:0] BAR2MASKWIDTH = 6'h0; - parameter [5:0] BAR3MASKWIDTH = 6'h0; - parameter [5:0] BAR4MASKWIDTH = 6'h0; - parameter [5:0] BAR5MASKWIDTH = 6'h0; - parameter [5:0] LINKCAPABILITYMAXLINKWIDTH = 6'h01; - parameter [63:0] DEVICESERIALNUMBER = 64'hE000000001000A35; - parameter [6:0] VC0TOTALCREDITSCH = 7'h0; - parameter [6:0] VC0TOTALCREDITSNPH = 7'h08; - parameter [6:0] VC0TOTALCREDITSPH = 7'h08; - parameter [6:0] VC1TOTALCREDITSCH = 7'h0; - parameter [6:0] VC1TOTALCREDITSNPH = 7'h0; - parameter [6:0] VC1TOTALCREDITSPH = 7'h0; - parameter [7:0] ACTIVELANESIN = 8'h1; - parameter [7:0] CAPABILITIESPOINTER = 8'h40; - parameter [7:0] INTERRUPTPIN = 8'h0; - parameter [7:0] MSICAPABILITYNEXTPTR = 8'h60; - parameter [7:0] PBCAPABILITYDW0BASEPOWER = 8'h0; - parameter [7:0] PBCAPABILITYDW1BASEPOWER = 8'h0; - parameter [7:0] PBCAPABILITYDW2BASEPOWER = 8'h0; - parameter [7:0] PBCAPABILITYDW3BASEPOWER = 8'h0; - parameter [7:0] PCIECAPABILITYNEXTPTR = 8'h0; - parameter [7:0] PMCAPABILITYNEXTPTR = 8'h60; - parameter [7:0] PMDATA0 = 8'h0; - parameter [7:0] PMDATA1 = 8'h0; - parameter [7:0] PMDATA2 = 8'h0; - parameter [7:0] PMDATA3 = 8'h0; - parameter [7:0] PMDATA4 = 8'h0; - parameter [7:0] PMDATA5 = 8'h0; - parameter [7:0] PMDATA6 = 8'h0; - parameter [7:0] PMDATA7 = 8'h0; - parameter [7:0] PORTVCCAPABILITYVCARBCAP = 8'h0; - parameter [7:0] PORTVCCAPABILITYVCARBTABLEOFFSET = 8'h0; - parameter [7:0] REVISIONID = 8'h0; - parameter [7:0] XPBASEPTR = 8'h60; - parameter BAR0ADDRWIDTH = 0; - parameter BAR0IOMEMN = 0; - parameter BAR1ADDRWIDTH = 0; - parameter BAR1IOMEMN = 0; - parameter BAR2ADDRWIDTH = 0; - parameter BAR2IOMEMN = 0; - parameter BAR3ADDRWIDTH = 0; - parameter BAR3IOMEMN = 0; - parameter BAR4ADDRWIDTH = 0; - parameter BAR4IOMEMN = 0; - parameter BAR5IOMEMN = 0; - parameter L0SEXITLATENCY = 7; - parameter L0SEXITLATENCYCOMCLK = 7; - parameter L1EXITLATENCY = 7; - parameter L1EXITLATENCYCOMCLK = 7; - parameter LOWPRIORITYVCCOUNT = 0; - parameter PMDATASCALE0 = 0; - parameter PMDATASCALE1 = 0; - parameter PMDATASCALE2 = 0; - parameter PMDATASCALE3 = 0; - parameter PMDATASCALE4 = 0; - parameter PMDATASCALE5 = 0; - parameter PMDATASCALE6 = 0; - parameter PMDATASCALE7 = 0; - parameter RETRYRAMREADLATENCY = 3; - parameter RETRYRAMWRITELATENCY = 1; - parameter TLRAMREADLATENCY = 3; - parameter TLRAMWRITELATENCY = 1; - parameter TXTSNFTS = 255; - parameter TXTSNFTSCOMCLK = 255; - parameter XPMAXPAYLOAD = 0; - output BUSMASTERENABLE; - output CRMDOHOTRESETN; - output CRMPWRSOFTRESETN; - output DLLTXPMDLLPOUTSTANDING; - output INTERRUPTDISABLE; - output IOSPACEENABLE; - output L0CFGLOOPBACKACK; - output L0DLLRXACKOUTSTANDING; - output L0DLLTXNONFCOUTSTANDING; - output L0DLLTXOUTSTANDING; - output L0FIRSTCFGWRITEOCCURRED; - output L0MACENTEREDL0; - output L0MACLINKTRAINING; - output L0MACLINKUP; - output L0MACNEWSTATEACK; - output L0MACRXL0SSTATE; - output L0MSIENABLE0; - output L0PMEACK; - output L0PMEEN; - output L0PMEREQOUT; - output L0PWRL1STATE; - output L0PWRL23READYSTATE; - output L0PWRTURNOFFREQ; - output L0PWRTXL0SSTATE; - output L0RXDLLPM; - output L0STATSCFGOTHERRECEIVED; - output L0STATSCFGOTHERTRANSMITTED; - output L0STATSCFGRECEIVED; - output L0STATSCFGTRANSMITTED; - output L0STATSDLLPRECEIVED; - output L0STATSDLLPTRANSMITTED; - output L0STATSOSRECEIVED; - output L0STATSOSTRANSMITTED; - output L0STATSTLPRECEIVED; - output L0STATSTLPTRANSMITTED; - output L0UNLOCKRECEIVED; - output LLKRXEOFN; - output LLKRXEOPN; - output LLKRXSOFN; - output LLKRXSOPN; - output LLKRXSRCLASTREQN; - output LLKRXSRCRDYN; - output LLKTXCONFIGREADYN; - output LLKTXDSTRDYN; - output MEMSPACEENABLE; - output MIMDLLBREN; - output MIMDLLBWEN; - output MIMRXBREN; - output MIMRXBWEN; - output MIMTXBREN; - output MIMTXBWEN; - output PARITYERRORRESPONSE; - output PIPEDESKEWLANESL0; - output PIPEDESKEWLANESL1; - output PIPEDESKEWLANESL2; - output PIPEDESKEWLANESL3; - output PIPEDESKEWLANESL4; - output PIPEDESKEWLANESL5; - output PIPEDESKEWLANESL6; - output PIPEDESKEWLANESL7; - output PIPERESETL0; - output PIPERESETL1; - output PIPERESETL2; - output PIPERESETL3; - output PIPERESETL4; - output PIPERESETL5; - output PIPERESETL6; - output PIPERESETL7; - output PIPERXPOLARITYL0; - output PIPERXPOLARITYL1; - output PIPERXPOLARITYL2; - output PIPERXPOLARITYL3; - output PIPERXPOLARITYL4; - output PIPERXPOLARITYL5; - output PIPERXPOLARITYL6; - output PIPERXPOLARITYL7; - output PIPETXCOMPLIANCEL0; - output PIPETXCOMPLIANCEL1; - output PIPETXCOMPLIANCEL2; - output PIPETXCOMPLIANCEL3; - output PIPETXCOMPLIANCEL4; - output PIPETXCOMPLIANCEL5; - output PIPETXCOMPLIANCEL6; - output PIPETXCOMPLIANCEL7; - output PIPETXDATAKL0; - output PIPETXDATAKL1; - output PIPETXDATAKL2; - output PIPETXDATAKL3; - output PIPETXDATAKL4; - output PIPETXDATAKL5; - output PIPETXDATAKL6; - output PIPETXDATAKL7; - output PIPETXDETECTRXLOOPBACKL0; - output PIPETXDETECTRXLOOPBACKL1; - output PIPETXDETECTRXLOOPBACKL2; - output PIPETXDETECTRXLOOPBACKL3; - output PIPETXDETECTRXLOOPBACKL4; - output PIPETXDETECTRXLOOPBACKL5; - output PIPETXDETECTRXLOOPBACKL6; - output PIPETXDETECTRXLOOPBACKL7; - output PIPETXELECIDLEL0; - output PIPETXELECIDLEL1; - output PIPETXELECIDLEL2; - output PIPETXELECIDLEL3; - output PIPETXELECIDLEL4; - output PIPETXELECIDLEL5; - output PIPETXELECIDLEL6; - output PIPETXELECIDLEL7; - output SERRENABLE; - output URREPORTINGENABLE; - output [11:0] MGMTSTATSCREDIT; - output [11:0] MIMDLLBRADD; - output [11:0] MIMDLLBWADD; - output [12:0] L0COMPLETERID; - output [12:0] MIMRXBRADD; - output [12:0] MIMRXBWADD; - output [12:0] MIMTXBRADD; - output [12:0] MIMTXBWADD; - output [15:0] LLKRXPREFERREDTYPE; - output [16:0] MGMTPSO; - output [1:0] L0PWRSTATE0; - output [1:0] L0RXMACLINKERROR; - output [1:0] LLKRXVALIDN; - output [1:0] PIPEPOWERDOWNL0; - output [1:0] PIPEPOWERDOWNL1; - output [1:0] PIPEPOWERDOWNL2; - output [1:0] PIPEPOWERDOWNL3; - output [1:0] PIPEPOWERDOWNL4; - output [1:0] PIPEPOWERDOWNL5; - output [1:0] PIPEPOWERDOWNL6; - output [1:0] PIPEPOWERDOWNL7; - output [2:0] L0MULTIMSGEN0; - output [2:0] L0RXDLLPMTYPE; - output [2:0] MAXPAYLOADSIZE; - output [2:0] MAXREADREQUESTSIZE; - output [31:0] MGMTRDATA; - output [3:0] L0LTSSMSTATE; - output [3:0] L0MACNEGOTIATEDLINKWIDTH; - output [63:0] LLKRXDATA; - output [63:0] MIMDLLBWDATA; - output [63:0] MIMRXBWDATA; - output [63:0] MIMTXBWDATA; - output [6:0] L0DLLERRORVECTOR; - output [7:0] L0DLLVCSTATUS; - output [7:0] L0DLUPDOWN; - output [7:0] LLKRXCHCOMPLETIONAVAILABLEN; - output [7:0] LLKRXCHNONPOSTEDAVAILABLEN; - output [7:0] LLKRXCHPOSTEDAVAILABLEN; - output [7:0] LLKTCSTATUS; - output [7:0] LLKTXCHCOMPLETIONREADYN; - output [7:0] LLKTXCHNONPOSTEDREADYN; - output [7:0] LLKTXCHPOSTEDREADYN; - output [7:0] PIPETXDATAL0; - output [7:0] PIPETXDATAL1; - output [7:0] PIPETXDATAL2; - output [7:0] PIPETXDATAL3; - output [7:0] PIPETXDATAL4; - output [7:0] PIPETXDATAL5; - output [7:0] PIPETXDATAL6; - output [7:0] PIPETXDATAL7; - output [9:0] LLKTXCHANSPACE; - input AUXPOWER; - input COMPLIANCEAVOID; - input CRMCORECLK; - input CRMCORECLKDLO; - input CRMCORECLKRXO; - input CRMCORECLKTXO; - input CRMLINKRSTN; - input CRMMACRSTN; - input CRMMGMTRSTN; - input CRMNVRSTN; - input CRMURSTN; - input CRMUSERCFGRSTN; - input CRMUSERCLK; - input CRMUSERCLKRXO; - input CRMUSERCLKTXO; - input L0CFGDISABLESCRAMBLE; - input L0CFGLOOPBACKMASTER; - input L0LEGACYINTFUNCT0; - input L0PMEREQIN; - input L0SETCOMPLETERABORTERROR; - input L0SETCOMPLETIONTIMEOUTCORRERROR; - input L0SETCOMPLETIONTIMEOUTUNCORRERROR; - input L0SETDETECTEDCORRERROR; - input L0SETDETECTEDFATALERROR; - input L0SETDETECTEDNONFATALERROR; - input L0SETUNEXPECTEDCOMPLETIONCORRERROR; - input L0SETUNEXPECTEDCOMPLETIONUNCORRERROR; - input L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR; - input L0SETUNSUPPORTEDREQUESTOTHERERROR; - input L0SETUSERDETECTEDPARITYERROR; - input L0SETUSERMASTERDATAPARITY; - input L0SETUSERRECEIVEDMASTERABORT; - input L0SETUSERRECEIVEDTARGETABORT; - input L0SETUSERSIGNALLEDTARGETABORT; - input L0SETUSERSYSTEMERROR; - input L0TRANSACTIONSPENDING; - input LLKRXDSTCONTREQN; - input LLKRXDSTREQN; - input LLKTXEOFN; - input LLKTXEOPN; - input LLKTXSOFN; - input LLKTXSOPN; - input LLKTXSRCDSCN; - input LLKTXSRCRDYN; - input MGMTRDEN; - input MGMTWREN; - input PIPEPHYSTATUSL0; - input PIPEPHYSTATUSL1; - input PIPEPHYSTATUSL2; - input PIPEPHYSTATUSL3; - input PIPEPHYSTATUSL4; - input PIPEPHYSTATUSL5; - input PIPEPHYSTATUSL6; - input PIPEPHYSTATUSL7; - input PIPERXCHANISALIGNEDL0; - input PIPERXCHANISALIGNEDL1; - input PIPERXCHANISALIGNEDL2; - input PIPERXCHANISALIGNEDL3; - input PIPERXCHANISALIGNEDL4; - input PIPERXCHANISALIGNEDL5; - input PIPERXCHANISALIGNEDL6; - input PIPERXCHANISALIGNEDL7; - input PIPERXDATAKL0; - input PIPERXDATAKL1; - input PIPERXDATAKL2; - input PIPERXDATAKL3; - input PIPERXDATAKL4; - input PIPERXDATAKL5; - input PIPERXDATAKL6; - input PIPERXDATAKL7; - input PIPERXELECIDLEL0; - input PIPERXELECIDLEL1; - input PIPERXELECIDLEL2; - input PIPERXELECIDLEL3; - input PIPERXELECIDLEL4; - input PIPERXELECIDLEL5; - input PIPERXELECIDLEL6; - input PIPERXELECIDLEL7; - input PIPERXVALIDL0; - input PIPERXVALIDL1; - input PIPERXVALIDL2; - input PIPERXVALIDL3; - input PIPERXVALIDL4; - input PIPERXVALIDL5; - input PIPERXVALIDL6; - input PIPERXVALIDL7; - input [10:0] MGMTADDR; - input [127:0] L0PACKETHEADERFROMUSER; - input [1:0] LLKRXCHFIFO; - input [1:0] LLKTXCHFIFO; - input [1:0] LLKTXENABLEN; - input [2:0] LLKRXCHTC; - input [2:0] LLKTXCHTC; - input [2:0] PIPERXSTATUSL0; - input [2:0] PIPERXSTATUSL1; - input [2:0] PIPERXSTATUSL2; - input [2:0] PIPERXSTATUSL3; - input [2:0] PIPERXSTATUSL4; - input [2:0] PIPERXSTATUSL5; - input [2:0] PIPERXSTATUSL6; - input [2:0] PIPERXSTATUSL7; - input [31:0] MGMTWDATA; - input [3:0] L0MSIREQUEST0; - input [3:0] MGMTBWREN; - input [63:0] LLKTXDATA; - input [63:0] MIMDLLBRDATA; - input [63:0] MIMRXBRDATA; - input [63:0] MIMTXBRDATA; - input [6:0] MGMTSTATSCREDITSEL; - input [7:0] PIPERXDATAL0; - input [7:0] PIPERXDATAL1; - input [7:0] PIPERXDATAL2; - input [7:0] PIPERXDATAL3; - input [7:0] PIPERXDATAL4; - input [7:0] PIPERXDATAL5; - input [7:0] PIPERXDATAL6; - input [7:0] PIPERXDATAL7; -endmodule - -module PCIE_2_0 (...); - parameter [11:0] AER_BASE_PTR = 12'h128; - parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; - parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; - parameter [15:0] AER_CAP_ID = 16'h0001; - parameter [4:0] AER_CAP_INT_MSG_NUM_MSI = 5'h0A; - parameter [4:0] AER_CAP_INT_MSG_NUM_MSIX = 5'h15; - parameter [11:0] AER_CAP_NEXTPTR = 12'h160; - parameter AER_CAP_ON = "FALSE"; - parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE"; - parameter [3:0] AER_CAP_VERSION = 4'h1; - parameter ALLOW_X8_GEN2 = "FALSE"; - parameter [31:0] BAR0 = 32'hFFFFFF00; - parameter [31:0] BAR1 = 32'hFFFF0000; - parameter [31:0] BAR2 = 32'hFFFF000C; - parameter [31:0] BAR3 = 32'hFFFFFFFF; - parameter [31:0] BAR4 = 32'h00000000; - parameter [31:0] BAR5 = 32'h00000000; - parameter [7:0] CAPABILITIES_PTR = 8'h40; - parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000; - parameter [23:0] CLASS_CODE = 24'h000000; - parameter CMD_INTX_IMPLEMENTED = "TRUE"; - parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE"; - parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0; - parameter [6:0] CRM_MODULE_RSTS = 7'h00; - parameter [15:0] DEVICE_ID = 16'h0007; - parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE"; - parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE"; - parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0; - parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0; - parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; - parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE"; - parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2; - parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0; - parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE"; - parameter integer DEV_CAP_RSVD_14_12 = 0; - parameter integer DEV_CAP_RSVD_17_16 = 0; - parameter integer DEV_CAP_RSVD_31_29 = 0; - parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE"; - parameter DISABLE_ASPM_L1_TIMER = "FALSE"; - parameter DISABLE_BAR_FILTERING = "FALSE"; - parameter DISABLE_ID_CHECK = "FALSE"; - parameter DISABLE_LANE_REVERSAL = "FALSE"; - parameter DISABLE_RX_TC_FILTER = "FALSE"; - parameter DISABLE_SCRAMBLING = "FALSE"; - parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; - parameter [11:0] DSN_BASE_PTR = 12'h100; - parameter [15:0] DSN_CAP_ID = 16'h0003; - parameter [11:0] DSN_CAP_NEXTPTR = 12'h000; - parameter DSN_CAP_ON = "TRUE"; - parameter [3:0] DSN_CAP_VERSION = 4'h1; - parameter [10:0] ENABLE_MSG_ROUTE = 11'h000; - parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE"; - parameter ENTER_RVRY_EI_L0 = "TRUE"; - parameter EXIT_LOOPBACK_ON_EI = "TRUE"; - parameter [31:0] EXPANSION_ROM = 32'hFFFFF001; - parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F; - parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF; - parameter [7:0] HEADER_TYPE = 8'h00; - parameter [4:0] INFER_EI = 5'h00; - parameter [7:0] INTERRUPT_PIN = 8'h01; - parameter IS_SWITCH = "FALSE"; - parameter [9:0] LAST_CONFIG_DWORD = 10'h042; - parameter integer LINK_CAP_ASPM_SUPPORT = 1; - parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE"; - parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE"; - parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; - parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; - parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; - parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; - parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; - parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; - parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; - parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; - parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE"; - parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1; - parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08; - parameter integer LINK_CAP_RSVD_23_22 = 0; - parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE"; - parameter integer LINK_CONTROL_RCB = 0; - parameter LINK_CTRL2_DEEMPHASIS = "FALSE"; - parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE"; - parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2; - parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; - parameter [14:0] LL_ACK_TIMEOUT = 15'h0000; - parameter LL_ACK_TIMEOUT_EN = "FALSE"; - parameter integer LL_ACK_TIMEOUT_FUNC = 0; - parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000; - parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; - parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; - parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01; - parameter [7:0] MSIX_BASE_PTR = 8'h9C; - parameter [7:0] MSIX_CAP_ID = 8'h11; - parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00; - parameter MSIX_CAP_ON = "FALSE"; - parameter integer MSIX_CAP_PBA_BIR = 0; - parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000; - parameter [7:0] MSI_BASE_PTR = 8'h48; - parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE"; - parameter [7:0] MSI_CAP_ID = 8'h05; - parameter integer MSI_CAP_MULTIMSGCAP = 0; - parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0; - parameter [7:0] MSI_CAP_NEXTPTR = 8'h60; - parameter MSI_CAP_ON = "FALSE"; - parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE"; - parameter integer N_FTS_COMCLK_GEN1 = 255; - parameter integer N_FTS_COMCLK_GEN2 = 255; - parameter integer N_FTS_GEN1 = 255; - parameter integer N_FTS_GEN2 = 255; - parameter [7:0] PCIE_BASE_PTR = 8'h60; - parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10; - parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2; - parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0; - parameter [4:0] PCIE_CAP_INT_MSG_NUM = 5'h00; - parameter [7:0] PCIE_CAP_NEXTPTR = 8'h00; - parameter PCIE_CAP_ON = "TRUE"; - parameter integer PCIE_CAP_RSVD_15_14 = 0; - parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE"; - parameter integer PCIE_REVISION = 2; - parameter integer PGL0_LANE = 0; - parameter integer PGL1_LANE = 1; - parameter integer PGL2_LANE = 2; - parameter integer PGL3_LANE = 3; - parameter integer PGL4_LANE = 4; - parameter integer PGL5_LANE = 5; - parameter integer PGL6_LANE = 6; - parameter integer PGL7_LANE = 7; - parameter integer PL_AUTO_CONFIG = 0; - parameter PL_FAST_TRAIN = "FALSE"; - parameter [7:0] PM_BASE_PTR = 8'h40; - parameter integer PM_CAP_AUXCURRENT = 0; - parameter PM_CAP_D1SUPPORT = "TRUE"; - parameter PM_CAP_D2SUPPORT = "TRUE"; - parameter PM_CAP_DSI = "FALSE"; - parameter [7:0] PM_CAP_ID = 8'h01; - parameter [7:0] PM_CAP_NEXTPTR = 8'h48; - parameter PM_CAP_ON = "TRUE"; - parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F; - parameter PM_CAP_PME_CLOCK = "FALSE"; - parameter integer PM_CAP_RSVD_04 = 0; - parameter integer PM_CAP_VERSION = 3; - parameter PM_CSR_B2B3 = "FALSE"; - parameter PM_CSR_BPCCEN = "FALSE"; - parameter PM_CSR_NOSOFTRST = "TRUE"; - parameter [7:0] PM_DATA0 = 8'h01; - parameter [7:0] PM_DATA1 = 8'h01; - parameter [7:0] PM_DATA2 = 8'h01; - parameter [7:0] PM_DATA3 = 8'h01; - parameter [7:0] PM_DATA4 = 8'h01; - parameter [7:0] PM_DATA5 = 8'h01; - parameter [7:0] PM_DATA6 = 8'h01; - parameter [7:0] PM_DATA7 = 8'h01; - parameter [1:0] PM_DATA_SCALE0 = 2'h1; - parameter [1:0] PM_DATA_SCALE1 = 2'h1; - parameter [1:0] PM_DATA_SCALE2 = 2'h1; - parameter [1:0] PM_DATA_SCALE3 = 2'h1; - parameter [1:0] PM_DATA_SCALE4 = 2'h1; - parameter [1:0] PM_DATA_SCALE5 = 2'h1; - parameter [1:0] PM_DATA_SCALE6 = 2'h1; - parameter [1:0] PM_DATA_SCALE7 = 2'h1; - parameter integer RECRC_CHK = 0; - parameter RECRC_CHK_TRIM = "FALSE"; - parameter [7:0] REVISION_ID = 8'h00; - parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE"; - parameter SELECT_DLL_IF = "FALSE"; - parameter SIM_VERSION = "1.0"; - parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE"; - parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE"; - parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE"; - parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE"; - parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE"; - parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE"; - parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE"; - parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000; - parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE"; - parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE"; - parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0; - parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00; - parameter integer SPARE_BIT0 = 0; - parameter integer SPARE_BIT1 = 0; - parameter integer SPARE_BIT2 = 0; - parameter integer SPARE_BIT3 = 0; - parameter integer SPARE_BIT4 = 0; - parameter integer SPARE_BIT5 = 0; - parameter integer SPARE_BIT6 = 0; - parameter integer SPARE_BIT7 = 0; - parameter integer SPARE_BIT8 = 0; - parameter [7:0] SPARE_BYTE0 = 8'h00; - parameter [7:0] SPARE_BYTE1 = 8'h00; - parameter [7:0] SPARE_BYTE2 = 8'h00; - parameter [7:0] SPARE_BYTE3 = 8'h00; - parameter [31:0] SPARE_WORD0 = 32'h00000000; - parameter [31:0] SPARE_WORD1 = 32'h00000000; - parameter [31:0] SPARE_WORD2 = 32'h00000000; - parameter [31:0] SPARE_WORD3 = 32'h00000000; - parameter [15:0] SUBSYSTEM_ID = 16'h0007; - parameter [15:0] SUBSYSTEM_VENDOR_ID = 16'h10EE; - parameter TL_RBYPASS = "FALSE"; - parameter integer TL_RX_RAM_RADDR_LATENCY = 0; - parameter integer TL_RX_RAM_RDATA_LATENCY = 2; - parameter integer TL_RX_RAM_WRITE_LATENCY = 0; - parameter TL_TFC_DISABLE = "FALSE"; - parameter TL_TX_CHECKS_DISABLE = "FALSE"; - parameter integer TL_TX_RAM_RADDR_LATENCY = 0; - parameter integer TL_TX_RAM_RDATA_LATENCY = 2; - parameter integer TL_TX_RAM_WRITE_LATENCY = 0; - parameter UPCONFIG_CAPABLE = "TRUE"; - parameter UPSTREAM_FACING = "TRUE"; - parameter UR_INV_REQ = "TRUE"; - parameter integer USER_CLK_FREQ = 3; - parameter VC0_CPL_INFINITE = "TRUE"; - parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF; - parameter integer VC0_TOTAL_CREDITS_CD = 127; - parameter integer VC0_TOTAL_CREDITS_CH = 31; - parameter integer VC0_TOTAL_CREDITS_NPH = 12; - parameter integer VC0_TOTAL_CREDITS_PD = 288; - parameter integer VC0_TOTAL_CREDITS_PH = 32; - parameter integer VC0_TX_LASTPACKET = 31; - parameter [11:0] VC_BASE_PTR = 12'h10C; - parameter [15:0] VC_CAP_ID = 16'h0002; - parameter [11:0] VC_CAP_NEXTPTR = 12'h000; - parameter VC_CAP_ON = "FALSE"; - parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE"; - parameter [3:0] VC_CAP_VERSION = 4'h1; - parameter [15:0] VENDOR_ID = 16'h10EE; - parameter [11:0] VSEC_BASE_PTR = 12'h160; - parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234; - parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018; - parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1; - parameter [15:0] VSEC_CAP_ID = 16'h000B; - parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE"; - parameter [11:0] VSEC_CAP_NEXTPTR = 12'h000; - parameter VSEC_CAP_ON = "FALSE"; - parameter [3:0] VSEC_CAP_VERSION = 4'h1; - output CFGAERECRCCHECKEN; - output CFGAERECRCGENEN; - output CFGCOMMANDBUSMASTERENABLE; - output CFGCOMMANDINTERRUPTDISABLE; - output CFGCOMMANDIOENABLE; - output CFGCOMMANDMEMENABLE; - output CFGCOMMANDSERREN; - output CFGDEVCONTROL2CPLTIMEOUTDIS; - output CFGDEVCONTROLAUXPOWEREN; - output CFGDEVCONTROLCORRERRREPORTINGEN; - output CFGDEVCONTROLENABLERO; - output CFGDEVCONTROLEXTTAGEN; - output CFGDEVCONTROLFATALERRREPORTINGEN; - output CFGDEVCONTROLNONFATALREPORTINGEN; - output CFGDEVCONTROLNOSNOOPEN; - output CFGDEVCONTROLPHANTOMEN; - output CFGDEVCONTROLURERRREPORTINGEN; - output CFGDEVSTATUSCORRERRDETECTED; - output CFGDEVSTATUSFATALERRDETECTED; - output CFGDEVSTATUSNONFATALERRDETECTED; - output CFGDEVSTATUSURDETECTED; - output CFGERRAERHEADERLOGSETN; - output CFGERRCPLRDYN; - output CFGINTERRUPTMSIENABLE; - output CFGINTERRUPTMSIXENABLE; - output CFGINTERRUPTMSIXFM; - output CFGINTERRUPTRDYN; - output CFGLINKCONTROLAUTOBANDWIDTHINTEN; - output CFGLINKCONTROLBANDWIDTHINTEN; - output CFGLINKCONTROLCLOCKPMEN; - output CFGLINKCONTROLCOMMONCLOCK; - output CFGLINKCONTROLEXTENDEDSYNC; - output CFGLINKCONTROLHWAUTOWIDTHDIS; - output CFGLINKCONTROLLINKDISABLE; - output CFGLINKCONTROLRCB; - output CFGLINKCONTROLRETRAINLINK; - output CFGLINKSTATUSAUTOBANDWIDTHSTATUS; - output CFGLINKSTATUSBANDWITHSTATUS; - output CFGLINKSTATUSDLLACTIVE; - output CFGLINKSTATUSLINKTRAINING; - output CFGMSGRECEIVED; - output CFGMSGRECEIVEDASSERTINTA; - output CFGMSGRECEIVEDASSERTINTB; - output CFGMSGRECEIVEDASSERTINTC; - output CFGMSGRECEIVEDASSERTINTD; - output CFGMSGRECEIVEDDEASSERTINTA; - output CFGMSGRECEIVEDDEASSERTINTB; - output CFGMSGRECEIVEDDEASSERTINTC; - output CFGMSGRECEIVEDDEASSERTINTD; - output CFGMSGRECEIVEDERRCOR; - output CFGMSGRECEIVEDERRFATAL; - output CFGMSGRECEIVEDERRNONFATAL; - output CFGMSGRECEIVEDPMASNAK; - output CFGMSGRECEIVEDPMETO; - output CFGMSGRECEIVEDPMETOACK; - output CFGMSGRECEIVEDPMPME; - output CFGMSGRECEIVEDSETSLOTPOWERLIMIT; - output CFGMSGRECEIVEDUNLOCK; - output CFGPMCSRPMEEN; - output CFGPMCSRPMESTATUS; - output CFGPMRCVASREQL1N; - output CFGPMRCVENTERL1N; - output CFGPMRCVENTERL23N; - output CFGPMRCVREQACKN; - output CFGRDWRDONEN; - output CFGSLOTCONTROLELECTROMECHILCTLPULSE; - output CFGTRANSACTION; - output CFGTRANSACTIONTYPE; - output DBGSCLRA; - output DBGSCLRB; - output DBGSCLRC; - output DBGSCLRD; - output DBGSCLRE; - output DBGSCLRF; - output DBGSCLRG; - output DBGSCLRH; - output DBGSCLRI; - output DBGSCLRJ; - output DBGSCLRK; - output DRPDRDY; - output LL2BADDLLPERRN; - output LL2BADTLPERRN; - output LL2PROTOCOLERRN; - output LL2REPLAYROERRN; - output LL2REPLAYTOERRN; - output LL2SUSPENDOKN; - output LL2TFCINIT1SEQN; - output LL2TFCINIT2SEQN; - output LNKCLKEN; - output MIMRXRCE; - output MIMRXREN; - output MIMRXWEN; - output MIMTXRCE; - output MIMTXREN; - output MIMTXWEN; - output PIPERX0POLARITY; - output PIPERX1POLARITY; - output PIPERX2POLARITY; - output PIPERX3POLARITY; - output PIPERX4POLARITY; - output PIPERX5POLARITY; - output PIPERX6POLARITY; - output PIPERX7POLARITY; - output PIPETX0COMPLIANCE; - output PIPETX0ELECIDLE; - output PIPETX1COMPLIANCE; - output PIPETX1ELECIDLE; - output PIPETX2COMPLIANCE; - output PIPETX2ELECIDLE; - output PIPETX3COMPLIANCE; - output PIPETX3ELECIDLE; - output PIPETX4COMPLIANCE; - output PIPETX4ELECIDLE; - output PIPETX5COMPLIANCE; - output PIPETX5ELECIDLE; - output PIPETX6COMPLIANCE; - output PIPETX6ELECIDLE; - output PIPETX7COMPLIANCE; - output PIPETX7ELECIDLE; - output PIPETXDEEMPH; - output PIPETXRATE; - output PIPETXRCVRDET; - output PIPETXRESET; - output PL2LINKUPN; - output PL2RECEIVERERRN; - output PL2RECOVERYN; - output PL2RXELECIDLE; - output PL2SUSPENDOK; - output PLLINKGEN2CAP; - output PLLINKPARTNERGEN2SUPPORTED; - output PLLINKUPCFGCAP; - output PLPHYLNKUPN; - output PLRECEIVEDHOTRST; - output PLSELLNKRATE; - output RECEIVEDFUNCLVLRSTN; - output TL2ASPMSUSPENDCREDITCHECKOKN; - output TL2ASPMSUSPENDREQN; - output TL2PPMSUSPENDOKN; - output TRNLNKUPN; - output TRNRDLLPSRCRDYN; - output TRNRECRCERRN; - output TRNREOFN; - output TRNRERRFWDN; - output TRNRREMN; - output TRNRSOFN; - output TRNRSRCDSCN; - output TRNRSRCRDYN; - output TRNTCFGREQN; - output TRNTDLLPDSTRDYN; - output TRNTDSTRDYN; - output TRNTERRDROPN; - output USERRSTN; - output [11:0] DBGVECC; - output [11:0] PLDBGVEC; - output [11:0] TRNFCCPLD; - output [11:0] TRNFCNPD; - output [11:0] TRNFCPD; - output [12:0] MIMRXRADDR; - output [12:0] MIMRXWADDR; - output [12:0] MIMTXRADDR; - output [12:0] MIMTXWADDR; - output [15:0] CFGMSGDATA; - output [15:0] DRPDO; - output [15:0] PIPETX0DATA; - output [15:0] PIPETX1DATA; - output [15:0] PIPETX2DATA; - output [15:0] PIPETX3DATA; - output [15:0] PIPETX4DATA; - output [15:0] PIPETX5DATA; - output [15:0] PIPETX6DATA; - output [15:0] PIPETX7DATA; - output [1:0] CFGLINKCONTROLASPMCONTROL; - output [1:0] CFGLINKSTATUSCURRENTSPEED; - output [1:0] CFGPMCSRPOWERSTATE; - output [1:0] PIPETX0CHARISK; - output [1:0] PIPETX0POWERDOWN; - output [1:0] PIPETX1CHARISK; - output [1:0] PIPETX1POWERDOWN; - output [1:0] PIPETX2CHARISK; - output [1:0] PIPETX2POWERDOWN; - output [1:0] PIPETX3CHARISK; - output [1:0] PIPETX3POWERDOWN; - output [1:0] PIPETX4CHARISK; - output [1:0] PIPETX4POWERDOWN; - output [1:0] PIPETX5CHARISK; - output [1:0] PIPETX5POWERDOWN; - output [1:0] PIPETX6CHARISK; - output [1:0] PIPETX6POWERDOWN; - output [1:0] PIPETX7CHARISK; - output [1:0] PIPETX7POWERDOWN; - output [1:0] PLLANEREVERSALMODE; - output [1:0] PLRXPMSTATE; - output [1:0] PLSELLNKWIDTH; - output [2:0] CFGDEVCONTROLMAXPAYLOAD; - output [2:0] CFGDEVCONTROLMAXREADREQ; - output [2:0] CFGINTERRUPTMMENABLE; - output [2:0] CFGPCIELINKSTATE; - output [2:0] PIPETXMARGIN; - output [2:0] PLINITIALLINKWIDTH; - output [2:0] PLTXPMSTATE; - output [31:0] CFGDO; - output [31:0] TRNRDLLPDATA; - output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL; - output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH; - output [5:0] PLLTSSMSTATE; - output [5:0] TRNTBUFAV; - output [63:0] DBGVECA; - output [63:0] DBGVECB; - output [63:0] TRNRD; - output [67:0] MIMRXWDATA; - output [68:0] MIMTXWDATA; - output [6:0] CFGTRANSACTIONADDR; - output [6:0] CFGVCTCVCMAP; - output [6:0] TRNRBARHITN; - output [7:0] CFGINTERRUPTDO; - output [7:0] TRNFCCPLH; - output [7:0] TRNFCNPH; - output [7:0] TRNFCPH; - input CFGERRACSN; - input CFGERRCORN; - input CFGERRCPLABORTN; - input CFGERRCPLTIMEOUTN; - input CFGERRCPLUNEXPECTN; - input CFGERRECRCN; - input CFGERRLOCKEDN; - input CFGERRPOSTEDN; - input CFGERRURN; - input CFGINTERRUPTASSERTN; - input CFGINTERRUPTN; - input CFGPMDIRECTASPML1N; - input CFGPMSENDPMACKN; - input CFGPMSENDPMETON; - input CFGPMSENDPMNAKN; - input CFGPMTURNOFFOKN; - input CFGPMWAKEN; - input CFGRDENN; - input CFGTRNPENDINGN; - input CFGWRENN; - input CFGWRREADONLYN; - input CFGWRRW1CASRWN; - input CMRSTN; - input CMSTICKYRSTN; - input DBGSUBMODE; - input DLRSTN; - input DRPCLK; - input DRPDEN; - input DRPDWE; - input FUNCLVLRSTN; - input LL2SENDASREQL1N; - input LL2SENDENTERL1N; - input LL2SENDENTERL23N; - input LL2SUSPENDNOWN; - input LL2TLPRCVN; - input PIPECLK; - input PIPERX0CHANISALIGNED; - input PIPERX0ELECIDLE; - input PIPERX0PHYSTATUS; - input PIPERX0VALID; - input PIPERX1CHANISALIGNED; - input PIPERX1ELECIDLE; - input PIPERX1PHYSTATUS; - input PIPERX1VALID; - input PIPERX2CHANISALIGNED; - input PIPERX2ELECIDLE; - input PIPERX2PHYSTATUS; - input PIPERX2VALID; - input PIPERX3CHANISALIGNED; - input PIPERX3ELECIDLE; - input PIPERX3PHYSTATUS; - input PIPERX3VALID; - input PIPERX4CHANISALIGNED; - input PIPERX4ELECIDLE; - input PIPERX4PHYSTATUS; - input PIPERX4VALID; - input PIPERX5CHANISALIGNED; - input PIPERX5ELECIDLE; - input PIPERX5PHYSTATUS; - input PIPERX5VALID; - input PIPERX6CHANISALIGNED; - input PIPERX6ELECIDLE; - input PIPERX6PHYSTATUS; - input PIPERX6VALID; - input PIPERX7CHANISALIGNED; - input PIPERX7ELECIDLE; - input PIPERX7PHYSTATUS; - input PIPERX7VALID; - input PLDIRECTEDLINKAUTON; - input PLDIRECTEDLINKSPEED; - input PLDOWNSTREAMDEEMPHSOURCE; - input PLRSTN; - input PLTRANSMITHOTRST; - input PLUPSTREAMPREFERDEEMPH; - input SYSRSTN; - input TL2ASPMSUSPENDCREDITCHECKN; - input TL2PPMSUSPENDREQN; - input TLRSTN; - input TRNRDSTRDYN; - input TRNRNPOKN; - input TRNTCFGGNTN; - input TRNTDLLPSRCRDYN; - input TRNTECRCGENN; - input TRNTEOFN; - input TRNTERRFWDN; - input TRNTREMN; - input TRNTSOFN; - input TRNTSRCDSCN; - input TRNTSRCRDYN; - input TRNTSTRN; - input USERCLK; - input [127:0] CFGERRAERHEADERLOG; - input [15:0] DRPDI; - input [15:0] PIPERX0DATA; - input [15:0] PIPERX1DATA; - input [15:0] PIPERX2DATA; - input [15:0] PIPERX3DATA; - input [15:0] PIPERX4DATA; - input [15:0] PIPERX5DATA; - input [15:0] PIPERX6DATA; - input [15:0] PIPERX7DATA; - input [1:0] DBGMODE; - input [1:0] PIPERX0CHARISK; - input [1:0] PIPERX1CHARISK; - input [1:0] PIPERX2CHARISK; - input [1:0] PIPERX3CHARISK; - input [1:0] PIPERX4CHARISK; - input [1:0] PIPERX5CHARISK; - input [1:0] PIPERX6CHARISK; - input [1:0] PIPERX7CHARISK; - input [1:0] PLDIRECTEDLINKCHANGE; - input [1:0] PLDIRECTEDLINKWIDTH; - input [2:0] CFGDSFUNCTIONNUMBER; - input [2:0] PIPERX0STATUS; - input [2:0] PIPERX1STATUS; - input [2:0] PIPERX2STATUS; - input [2:0] PIPERX3STATUS; - input [2:0] PIPERX4STATUS; - input [2:0] PIPERX5STATUS; - input [2:0] PIPERX6STATUS; - input [2:0] PIPERX7STATUS; - input [2:0] PLDBGMODE; - input [2:0] TRNFCSEL; - input [31:0] CFGDI; - input [31:0] TRNTDLLPDATA; - input [3:0] CFGBYTEENN; - input [47:0] CFGERRTLPCPLHEADER; - input [4:0] CFGDSDEVICENUMBER; - input [4:0] PL2DIRECTEDLSTATE; - input [63:0] CFGDSN; - input [63:0] TRNTD; - input [67:0] MIMRXRDATA; - input [68:0] MIMTXRDATA; - input [7:0] CFGDSBUSNUMBER; - input [7:0] CFGINTERRUPTDI; - input [7:0] CFGPORTNUMBER; - input [8:0] DRPDADDR; - input [9:0] CFGDWADDR; -endmodule - -module PCIE_2_1 (...); - parameter [11:0] AER_BASE_PTR = 12'h140; - parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; - parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; - parameter [15:0] AER_CAP_ID = 16'h0001; - parameter AER_CAP_MULTIHEADER = "FALSE"; - parameter [11:0] AER_CAP_NEXTPTR = 12'h178; - parameter AER_CAP_ON = "FALSE"; - parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000; - parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE"; - parameter [3:0] AER_CAP_VERSION = 4'h2; - parameter ALLOW_X8_GEN2 = "FALSE"; - parameter [31:0] BAR0 = 32'hFFFFFF00; - parameter [31:0] BAR1 = 32'hFFFF0000; - parameter [31:0] BAR2 = 32'hFFFF000C; - parameter [31:0] BAR3 = 32'hFFFFFFFF; - parameter [31:0] BAR4 = 32'h00000000; - parameter [31:0] BAR5 = 32'h00000000; - parameter [7:0] CAPABILITIES_PTR = 8'h40; - parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000; - parameter integer CFG_ECRC_ERR_CPLSTAT = 0; - parameter [23:0] CLASS_CODE = 24'h000000; - parameter CMD_INTX_IMPLEMENTED = "TRUE"; - parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE"; - parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0; - parameter [6:0] CRM_MODULE_RSTS = 7'h00; - parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE"; - parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE"; - parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE"; - parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE"; - parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE"; - parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE"; - parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE"; - parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE"; - parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0; - parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE"; - parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'h0; - parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE"; - parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE"; - parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0; - parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0; - parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; - parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE"; - parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2; - parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0; - parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE"; - parameter integer DEV_CAP_RSVD_14_12 = 0; - parameter integer DEV_CAP_RSVD_17_16 = 0; - parameter integer DEV_CAP_RSVD_31_29 = 0; - parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE"; - parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE"; - parameter DISABLE_ASPM_L1_TIMER = "FALSE"; - parameter DISABLE_BAR_FILTERING = "FALSE"; - parameter DISABLE_ERR_MSG = "FALSE"; - parameter DISABLE_ID_CHECK = "FALSE"; - parameter DISABLE_LANE_REVERSAL = "FALSE"; - parameter DISABLE_LOCKED_FILTER = "FALSE"; - parameter DISABLE_PPM_FILTER = "FALSE"; - parameter DISABLE_RX_POISONED_RESP = "FALSE"; - parameter DISABLE_RX_TC_FILTER = "FALSE"; - parameter DISABLE_SCRAMBLING = "FALSE"; - parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; - parameter [11:0] DSN_BASE_PTR = 12'h100; - parameter [15:0] DSN_CAP_ID = 16'h0003; - parameter [11:0] DSN_CAP_NEXTPTR = 12'h10C; - parameter DSN_CAP_ON = "TRUE"; - parameter [3:0] DSN_CAP_VERSION = 4'h1; - parameter [10:0] ENABLE_MSG_ROUTE = 11'h000; - parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE"; - parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE"; - parameter ENTER_RVRY_EI_L0 = "TRUE"; - parameter EXIT_LOOPBACK_ON_EI = "TRUE"; - parameter [31:0] EXPANSION_ROM = 32'hFFFFF001; - parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F; - parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF; - parameter [7:0] HEADER_TYPE = 8'h00; - parameter [4:0] INFER_EI = 5'h00; - parameter [7:0] INTERRUPT_PIN = 8'h01; - parameter INTERRUPT_STAT_AUTO = "TRUE"; - parameter IS_SWITCH = "FALSE"; - parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF; - parameter LINK_CAP_ASPM_OPTIONALITY = "TRUE"; - parameter integer LINK_CAP_ASPM_SUPPORT = 1; - parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE"; - parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE"; - parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; - parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; - parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; - parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; - parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; - parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; - parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; - parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; - parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE"; - parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1; - parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08; - parameter integer LINK_CAP_RSVD_23 = 0; - parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE"; - parameter integer LINK_CONTROL_RCB = 0; - parameter LINK_CTRL2_DEEMPHASIS = "FALSE"; - parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE"; - parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2; - parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; - parameter [14:0] LL_ACK_TIMEOUT = 15'h0000; - parameter LL_ACK_TIMEOUT_EN = "FALSE"; - parameter integer LL_ACK_TIMEOUT_FUNC = 0; - parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000; - parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; - parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; - parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01; - parameter MPS_FORCE = "FALSE"; - parameter [7:0] MSIX_BASE_PTR = 8'h9C; - parameter [7:0] MSIX_CAP_ID = 8'h11; - parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00; - parameter MSIX_CAP_ON = "FALSE"; - parameter integer MSIX_CAP_PBA_BIR = 0; - parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000; - parameter [7:0] MSI_BASE_PTR = 8'h48; - parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE"; - parameter [7:0] MSI_CAP_ID = 8'h05; - parameter integer MSI_CAP_MULTIMSGCAP = 0; - parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0; - parameter [7:0] MSI_CAP_NEXTPTR = 8'h60; - parameter MSI_CAP_ON = "FALSE"; - parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE"; - parameter integer N_FTS_COMCLK_GEN1 = 255; - parameter integer N_FTS_COMCLK_GEN2 = 255; - parameter integer N_FTS_GEN1 = 255; - parameter integer N_FTS_GEN2 = 255; - parameter [7:0] PCIE_BASE_PTR = 8'h60; - parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10; - parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2; - parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0; - parameter [7:0] PCIE_CAP_NEXTPTR = 8'h9C; - parameter PCIE_CAP_ON = "TRUE"; - parameter integer PCIE_CAP_RSVD_15_14 = 0; - parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE"; - parameter integer PCIE_REVISION = 2; - parameter integer PL_AUTO_CONFIG = 0; - parameter PL_FAST_TRAIN = "FALSE"; - parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000; - parameter PM_ASPML0S_TIMEOUT_EN = "FALSE"; - parameter integer PM_ASPML0S_TIMEOUT_FUNC = 0; - parameter PM_ASPM_FASTEXIT = "FALSE"; - parameter [7:0] PM_BASE_PTR = 8'h40; - parameter integer PM_CAP_AUXCURRENT = 0; - parameter PM_CAP_D1SUPPORT = "TRUE"; - parameter PM_CAP_D2SUPPORT = "TRUE"; - parameter PM_CAP_DSI = "FALSE"; - parameter [7:0] PM_CAP_ID = 8'h01; - parameter [7:0] PM_CAP_NEXTPTR = 8'h48; - parameter PM_CAP_ON = "TRUE"; - parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F; - parameter PM_CAP_PME_CLOCK = "FALSE"; - parameter integer PM_CAP_RSVD_04 = 0; - parameter integer PM_CAP_VERSION = 3; - parameter PM_CSR_B2B3 = "FALSE"; - parameter PM_CSR_BPCCEN = "FALSE"; - parameter PM_CSR_NOSOFTRST = "TRUE"; - parameter [7:0] PM_DATA0 = 8'h01; - parameter [7:0] PM_DATA1 = 8'h01; - parameter [7:0] PM_DATA2 = 8'h01; - parameter [7:0] PM_DATA3 = 8'h01; - parameter [7:0] PM_DATA4 = 8'h01; - parameter [7:0] PM_DATA5 = 8'h01; - parameter [7:0] PM_DATA6 = 8'h01; - parameter [7:0] PM_DATA7 = 8'h01; - parameter [1:0] PM_DATA_SCALE0 = 2'h1; - parameter [1:0] PM_DATA_SCALE1 = 2'h1; - parameter [1:0] PM_DATA_SCALE2 = 2'h1; - parameter [1:0] PM_DATA_SCALE3 = 2'h1; - parameter [1:0] PM_DATA_SCALE4 = 2'h1; - parameter [1:0] PM_DATA_SCALE5 = 2'h1; - parameter [1:0] PM_DATA_SCALE6 = 2'h1; - parameter [1:0] PM_DATA_SCALE7 = 2'h1; - parameter PM_MF = "FALSE"; - parameter [11:0] RBAR_BASE_PTR = 12'h178; - parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00; - parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00; - parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00; - parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00; - parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00; - parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00; - parameter [15:0] RBAR_CAP_ID = 16'h0015; - parameter [2:0] RBAR_CAP_INDEX0 = 3'h0; - parameter [2:0] RBAR_CAP_INDEX1 = 3'h0; - parameter [2:0] RBAR_CAP_INDEX2 = 3'h0; - parameter [2:0] RBAR_CAP_INDEX3 = 3'h0; - parameter [2:0] RBAR_CAP_INDEX4 = 3'h0; - parameter [2:0] RBAR_CAP_INDEX5 = 3'h0; - parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000; - parameter RBAR_CAP_ON = "FALSE"; - parameter [31:0] RBAR_CAP_SUP0 = 32'h00000000; - parameter [31:0] RBAR_CAP_SUP1 = 32'h00000000; - parameter [31:0] RBAR_CAP_SUP2 = 32'h00000000; - parameter [31:0] RBAR_CAP_SUP3 = 32'h00000000; - parameter [31:0] RBAR_CAP_SUP4 = 32'h00000000; - parameter [31:0] RBAR_CAP_SUP5 = 32'h00000000; - parameter [3:0] RBAR_CAP_VERSION = 4'h1; - parameter [2:0] RBAR_NUM = 3'h1; - parameter integer RECRC_CHK = 0; - parameter RECRC_CHK_TRIM = "FALSE"; - parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE"; - parameter [1:0] RP_AUTO_SPD = 2'h1; - parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1F; - parameter SELECT_DLL_IF = "FALSE"; - parameter SIM_VERSION = "1.0"; - parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE"; - parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE"; - parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE"; - parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE"; - parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE"; - parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE"; - parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE"; - parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000; - parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE"; - parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE"; - parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0; - parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00; - parameter integer SPARE_BIT0 = 0; - parameter integer SPARE_BIT1 = 0; - parameter integer SPARE_BIT2 = 0; - parameter integer SPARE_BIT3 = 0; - parameter integer SPARE_BIT4 = 0; - parameter integer SPARE_BIT5 = 0; - parameter integer SPARE_BIT6 = 0; - parameter integer SPARE_BIT7 = 0; - parameter integer SPARE_BIT8 = 0; - parameter [7:0] SPARE_BYTE0 = 8'h00; - parameter [7:0] SPARE_BYTE1 = 8'h00; - parameter [7:0] SPARE_BYTE2 = 8'h00; - parameter [7:0] SPARE_BYTE3 = 8'h00; - parameter [31:0] SPARE_WORD0 = 32'h00000000; - parameter [31:0] SPARE_WORD1 = 32'h00000000; - parameter [31:0] SPARE_WORD2 = 32'h00000000; - parameter [31:0] SPARE_WORD3 = 32'h00000000; - parameter SSL_MESSAGE_AUTO = "FALSE"; - parameter TECRC_EP_INV = "FALSE"; - parameter TL_RBYPASS = "FALSE"; - parameter integer TL_RX_RAM_RADDR_LATENCY = 0; - parameter integer TL_RX_RAM_RDATA_LATENCY = 2; - parameter integer TL_RX_RAM_WRITE_LATENCY = 0; - parameter TL_TFC_DISABLE = "FALSE"; - parameter TL_TX_CHECKS_DISABLE = "FALSE"; - parameter integer TL_TX_RAM_RADDR_LATENCY = 0; - parameter integer TL_TX_RAM_RDATA_LATENCY = 2; - parameter integer TL_TX_RAM_WRITE_LATENCY = 0; - parameter TRN_DW = "FALSE"; - parameter TRN_NP_FC = "FALSE"; - parameter UPCONFIG_CAPABLE = "TRUE"; - parameter UPSTREAM_FACING = "TRUE"; - parameter UR_ATOMIC = "TRUE"; - parameter UR_CFG1 = "TRUE"; - parameter UR_INV_REQ = "TRUE"; - parameter UR_PRS_RESPONSE = "TRUE"; - parameter USER_CLK2_DIV2 = "FALSE"; - parameter integer USER_CLK_FREQ = 3; - parameter USE_RID_PINS = "FALSE"; - parameter VC0_CPL_INFINITE = "TRUE"; - parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF; - parameter integer VC0_TOTAL_CREDITS_CD = 127; - parameter integer VC0_TOTAL_CREDITS_CH = 31; - parameter integer VC0_TOTAL_CREDITS_NPD = 24; - parameter integer VC0_TOTAL_CREDITS_NPH = 12; - parameter integer VC0_TOTAL_CREDITS_PD = 288; - parameter integer VC0_TOTAL_CREDITS_PH = 32; - parameter integer VC0_TX_LASTPACKET = 31; - parameter [11:0] VC_BASE_PTR = 12'h10C; - parameter [15:0] VC_CAP_ID = 16'h0002; - parameter [11:0] VC_CAP_NEXTPTR = 12'h000; - parameter VC_CAP_ON = "FALSE"; - parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE"; - parameter [3:0] VC_CAP_VERSION = 4'h1; - parameter [11:0] VSEC_BASE_PTR = 12'h128; - parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234; - parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018; - parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1; - parameter [15:0] VSEC_CAP_ID = 16'h000B; - parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE"; - parameter [11:0] VSEC_CAP_NEXTPTR = 12'h140; - parameter VSEC_CAP_ON = "FALSE"; - parameter [3:0] VSEC_CAP_VERSION = 4'h1; - output CFGAERECRCCHECKEN; - output CFGAERECRCGENEN; - output CFGAERROOTERRCORRERRRECEIVED; - output CFGAERROOTERRCORRERRREPORTINGEN; - output CFGAERROOTERRFATALERRRECEIVED; - output CFGAERROOTERRFATALERRREPORTINGEN; - output CFGAERROOTERRNONFATALERRRECEIVED; - output CFGAERROOTERRNONFATALERRREPORTINGEN; - output CFGBRIDGESERREN; - output CFGCOMMANDBUSMASTERENABLE; - output CFGCOMMANDINTERRUPTDISABLE; - output CFGCOMMANDIOENABLE; - output CFGCOMMANDMEMENABLE; - output CFGCOMMANDSERREN; - output CFGDEVCONTROL2ARIFORWARDEN; - output CFGDEVCONTROL2ATOMICEGRESSBLOCK; - output CFGDEVCONTROL2ATOMICREQUESTEREN; - output CFGDEVCONTROL2CPLTIMEOUTDIS; - output CFGDEVCONTROL2IDOCPLEN; - output CFGDEVCONTROL2IDOREQEN; - output CFGDEVCONTROL2LTREN; - output CFGDEVCONTROL2TLPPREFIXBLOCK; - output CFGDEVCONTROLAUXPOWEREN; - output CFGDEVCONTROLCORRERRREPORTINGEN; - output CFGDEVCONTROLENABLERO; - output CFGDEVCONTROLEXTTAGEN; - output CFGDEVCONTROLFATALERRREPORTINGEN; - output CFGDEVCONTROLNONFATALREPORTINGEN; - output CFGDEVCONTROLNOSNOOPEN; - output CFGDEVCONTROLPHANTOMEN; - output CFGDEVCONTROLURERRREPORTINGEN; - output CFGDEVSTATUSCORRERRDETECTED; - output CFGDEVSTATUSFATALERRDETECTED; - output CFGDEVSTATUSNONFATALERRDETECTED; - output CFGDEVSTATUSURDETECTED; - output CFGERRAERHEADERLOGSETN; - output CFGERRCPLRDYN; - output CFGINTERRUPTMSIENABLE; - output CFGINTERRUPTMSIXENABLE; - output CFGINTERRUPTMSIXFM; - output CFGINTERRUPTRDYN; - output CFGLINKCONTROLAUTOBANDWIDTHINTEN; - output CFGLINKCONTROLBANDWIDTHINTEN; - output CFGLINKCONTROLCLOCKPMEN; - output CFGLINKCONTROLCOMMONCLOCK; - output CFGLINKCONTROLEXTENDEDSYNC; - output CFGLINKCONTROLHWAUTOWIDTHDIS; - output CFGLINKCONTROLLINKDISABLE; - output CFGLINKCONTROLRCB; - output CFGLINKCONTROLRETRAINLINK; - output CFGLINKSTATUSAUTOBANDWIDTHSTATUS; - output CFGLINKSTATUSBANDWIDTHSTATUS; - output CFGLINKSTATUSDLLACTIVE; - output CFGLINKSTATUSLINKTRAINING; - output CFGMGMTRDWRDONEN; - output CFGMSGRECEIVED; - output CFGMSGRECEIVEDASSERTINTA; - output CFGMSGRECEIVEDASSERTINTB; - output CFGMSGRECEIVEDASSERTINTC; - output CFGMSGRECEIVEDASSERTINTD; - output CFGMSGRECEIVEDDEASSERTINTA; - output CFGMSGRECEIVEDDEASSERTINTB; - output CFGMSGRECEIVEDDEASSERTINTC; - output CFGMSGRECEIVEDDEASSERTINTD; - output CFGMSGRECEIVEDERRCOR; - output CFGMSGRECEIVEDERRFATAL; - output CFGMSGRECEIVEDERRNONFATAL; - output CFGMSGRECEIVEDPMASNAK; - output CFGMSGRECEIVEDPMETO; - output CFGMSGRECEIVEDPMETOACK; - output CFGMSGRECEIVEDPMPME; - output CFGMSGRECEIVEDSETSLOTPOWERLIMIT; - output CFGMSGRECEIVEDUNLOCK; - output CFGPMCSRPMEEN; - output CFGPMCSRPMESTATUS; - output CFGPMRCVASREQL1N; - output CFGPMRCVENTERL1N; - output CFGPMRCVENTERL23N; - output CFGPMRCVREQACKN; - output CFGROOTCONTROLPMEINTEN; - output CFGROOTCONTROLSYSERRCORRERREN; - output CFGROOTCONTROLSYSERRFATALERREN; - output CFGROOTCONTROLSYSERRNONFATALERREN; - output CFGSLOTCONTROLELECTROMECHILCTLPULSE; - output CFGTRANSACTION; - output CFGTRANSACTIONTYPE; - output DBGSCLRA; - output DBGSCLRB; - output DBGSCLRC; - output DBGSCLRD; - output DBGSCLRE; - output DBGSCLRF; - output DBGSCLRG; - output DBGSCLRH; - output DBGSCLRI; - output DBGSCLRJ; - output DBGSCLRK; - output DRPRDY; - output LL2BADDLLPERR; - output LL2BADTLPERR; - output LL2PROTOCOLERR; - output LL2RECEIVERERR; - output LL2REPLAYROERR; - output LL2REPLAYTOERR; - output LL2SUSPENDOK; - output LL2TFCINIT1SEQ; - output LL2TFCINIT2SEQ; - output LL2TXIDLE; - output LNKCLKEN; - output MIMRXREN; - output MIMRXWEN; - output MIMTXREN; - output MIMTXWEN; - output PIPERX0POLARITY; - output PIPERX1POLARITY; - output PIPERX2POLARITY; - output PIPERX3POLARITY; - output PIPERX4POLARITY; - output PIPERX5POLARITY; - output PIPERX6POLARITY; - output PIPERX7POLARITY; - output PIPETX0COMPLIANCE; - output PIPETX0ELECIDLE; - output PIPETX1COMPLIANCE; - output PIPETX1ELECIDLE; - output PIPETX2COMPLIANCE; - output PIPETX2ELECIDLE; - output PIPETX3COMPLIANCE; - output PIPETX3ELECIDLE; - output PIPETX4COMPLIANCE; - output PIPETX4ELECIDLE; - output PIPETX5COMPLIANCE; - output PIPETX5ELECIDLE; - output PIPETX6COMPLIANCE; - output PIPETX6ELECIDLE; - output PIPETX7COMPLIANCE; - output PIPETX7ELECIDLE; - output PIPETXDEEMPH; - output PIPETXRATE; - output PIPETXRCVRDET; - output PIPETXRESET; - output PL2L0REQ; - output PL2LINKUP; - output PL2RECEIVERERR; - output PL2RECOVERY; - output PL2RXELECIDLE; - output PL2SUSPENDOK; - output PLDIRECTEDCHANGEDONE; - output PLLINKGEN2CAP; - output PLLINKPARTNERGEN2SUPPORTED; - output PLLINKUPCFGCAP; - output PLPHYLNKUPN; - output PLRECEIVEDHOTRST; - output PLSELLNKRATE; - output RECEIVEDFUNCLVLRSTN; - output TL2ASPMSUSPENDCREDITCHECKOK; - output TL2ASPMSUSPENDREQ; - output TL2ERRFCPE; - output TL2ERRMALFORMED; - output TL2ERRRXOVERFLOW; - output TL2PPMSUSPENDOK; - output TRNLNKUP; - output TRNRECRCERR; - output TRNREOF; - output TRNRERRFWD; - output TRNRSOF; - output TRNRSRCDSC; - output TRNRSRCRDY; - output TRNTCFGREQ; - output TRNTDLLPDSTRDY; - output TRNTERRDROP; - output USERRSTN; - output [11:0] DBGVECC; - output [11:0] PLDBGVEC; - output [11:0] TRNFCCPLD; - output [11:0] TRNFCNPD; - output [11:0] TRNFCPD; - output [127:0] TRNRD; - output [12:0] MIMRXRADDR; - output [12:0] MIMRXWADDR; - output [12:0] MIMTXRADDR; - output [12:0] MIMTXWADDR; - output [15:0] CFGMSGDATA; - output [15:0] DRPDO; - output [15:0] PIPETX0DATA; - output [15:0] PIPETX1DATA; - output [15:0] PIPETX2DATA; - output [15:0] PIPETX3DATA; - output [15:0] PIPETX4DATA; - output [15:0] PIPETX5DATA; - output [15:0] PIPETX6DATA; - output [15:0] PIPETX7DATA; - output [1:0] CFGLINKCONTROLASPMCONTROL; - output [1:0] CFGLINKSTATUSCURRENTSPEED; - output [1:0] CFGPMCSRPOWERSTATE; - output [1:0] PIPETX0CHARISK; - output [1:0] PIPETX0POWERDOWN; - output [1:0] PIPETX1CHARISK; - output [1:0] PIPETX1POWERDOWN; - output [1:0] PIPETX2CHARISK; - output [1:0] PIPETX2POWERDOWN; - output [1:0] PIPETX3CHARISK; - output [1:0] PIPETX3POWERDOWN; - output [1:0] PIPETX4CHARISK; - output [1:0] PIPETX4POWERDOWN; - output [1:0] PIPETX5CHARISK; - output [1:0] PIPETX5POWERDOWN; - output [1:0] PIPETX6CHARISK; - output [1:0] PIPETX6POWERDOWN; - output [1:0] PIPETX7CHARISK; - output [1:0] PIPETX7POWERDOWN; - output [1:0] PL2RXPMSTATE; - output [1:0] PLLANEREVERSALMODE; - output [1:0] PLRXPMSTATE; - output [1:0] PLSELLNKWIDTH; - output [1:0] TRNRDLLPSRCRDY; - output [1:0] TRNRREM; - output [2:0] CFGDEVCONTROLMAXPAYLOAD; - output [2:0] CFGDEVCONTROLMAXREADREQ; - output [2:0] CFGINTERRUPTMMENABLE; - output [2:0] CFGPCIELINKSTATE; - output [2:0] PIPETXMARGIN; - output [2:0] PLINITIALLINKWIDTH; - output [2:0] PLTXPMSTATE; - output [31:0] CFGMGMTDO; - output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL; - output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH; - output [3:0] TRNTDSTRDY; - output [4:0] LL2LINKSTATUS; - output [5:0] PLLTSSMSTATE; - output [5:0] TRNTBUFAV; - output [63:0] DBGVECA; - output [63:0] DBGVECB; - output [63:0] TL2ERRHDR; - output [63:0] TRNRDLLPDATA; - output [67:0] MIMRXWDATA; - output [68:0] MIMTXWDATA; - output [6:0] CFGTRANSACTIONADDR; - output [6:0] CFGVCTCVCMAP; - output [7:0] CFGINTERRUPTDO; - output [7:0] TRNFCCPLH; - output [7:0] TRNFCNPH; - output [7:0] TRNFCPH; - output [7:0] TRNRBARHIT; - input CFGERRACSN; - input CFGERRATOMICEGRESSBLOCKEDN; - input CFGERRCORN; - input CFGERRCPLABORTN; - input CFGERRCPLTIMEOUTN; - input CFGERRCPLUNEXPECTN; - input CFGERRECRCN; - input CFGERRINTERNALCORN; - input CFGERRINTERNALUNCORN; - input CFGERRLOCKEDN; - input CFGERRMALFORMEDN; - input CFGERRMCBLOCKEDN; - input CFGERRNORECOVERYN; - input CFGERRPOISONEDN; - input CFGERRPOSTEDN; - input CFGERRURN; - input CFGFORCECOMMONCLOCKOFF; - input CFGFORCEEXTENDEDSYNCON; - input CFGINTERRUPTASSERTN; - input CFGINTERRUPTN; - input CFGINTERRUPTSTATN; - input CFGMGMTRDENN; - input CFGMGMTWRENN; - input CFGMGMTWRREADONLYN; - input CFGMGMTWRRW1CASRWN; - input CFGPMFORCESTATEENN; - input CFGPMHALTASPML0SN; - input CFGPMHALTASPML1N; - input CFGPMSENDPMETON; - input CFGPMTURNOFFOKN; - input CFGPMWAKEN; - input CFGTRNPENDINGN; - input CMRSTN; - input CMSTICKYRSTN; - input DBGSUBMODE; - input DLRSTN; - input DRPCLK; - input DRPEN; - input DRPWE; - input FUNCLVLRSTN; - input LL2SENDASREQL1; - input LL2SENDENTERL1; - input LL2SENDENTERL23; - input LL2SENDPMACK; - input LL2SUSPENDNOW; - input LL2TLPRCV; - input PIPECLK; - input PIPERX0CHANISALIGNED; - input PIPERX0ELECIDLE; - input PIPERX0PHYSTATUS; - input PIPERX0VALID; - input PIPERX1CHANISALIGNED; - input PIPERX1ELECIDLE; - input PIPERX1PHYSTATUS; - input PIPERX1VALID; - input PIPERX2CHANISALIGNED; - input PIPERX2ELECIDLE; - input PIPERX2PHYSTATUS; - input PIPERX2VALID; - input PIPERX3CHANISALIGNED; - input PIPERX3ELECIDLE; - input PIPERX3PHYSTATUS; - input PIPERX3VALID; - input PIPERX4CHANISALIGNED; - input PIPERX4ELECIDLE; - input PIPERX4PHYSTATUS; - input PIPERX4VALID; - input PIPERX5CHANISALIGNED; - input PIPERX5ELECIDLE; - input PIPERX5PHYSTATUS; - input PIPERX5VALID; - input PIPERX6CHANISALIGNED; - input PIPERX6ELECIDLE; - input PIPERX6PHYSTATUS; - input PIPERX6VALID; - input PIPERX7CHANISALIGNED; - input PIPERX7ELECIDLE; - input PIPERX7PHYSTATUS; - input PIPERX7VALID; - input PLDIRECTEDLINKAUTON; - input PLDIRECTEDLINKSPEED; - input PLDIRECTEDLTSSMNEWVLD; - input PLDIRECTEDLTSSMSTALL; - input PLDOWNSTREAMDEEMPHSOURCE; - input PLRSTN; - input PLTRANSMITHOTRST; - input PLUPSTREAMPREFERDEEMPH; - input SYSRSTN; - input TL2ASPMSUSPENDCREDITCHECK; - input TL2PPMSUSPENDREQ; - input TLRSTN; - input TRNRDSTRDY; - input TRNRFCPRET; - input TRNRNPOK; - input TRNRNPREQ; - input TRNTCFGGNT; - input TRNTDLLPSRCRDY; - input TRNTECRCGEN; - input TRNTEOF; - input TRNTERRFWD; - input TRNTSOF; - input TRNTSRCDSC; - input TRNTSRCRDY; - input TRNTSTR; - input USERCLK2; - input USERCLK; - input [127:0] CFGERRAERHEADERLOG; - input [127:0] TRNTD; - input [15:0] CFGDEVID; - input [15:0] CFGSUBSYSID; - input [15:0] CFGSUBSYSVENDID; - input [15:0] CFGVENDID; - input [15:0] DRPDI; - input [15:0] PIPERX0DATA; - input [15:0] PIPERX1DATA; - input [15:0] PIPERX2DATA; - input [15:0] PIPERX3DATA; - input [15:0] PIPERX4DATA; - input [15:0] PIPERX5DATA; - input [15:0] PIPERX6DATA; - input [15:0] PIPERX7DATA; - input [1:0] CFGPMFORCESTATE; - input [1:0] DBGMODE; - input [1:0] PIPERX0CHARISK; - input [1:0] PIPERX1CHARISK; - input [1:0] PIPERX2CHARISK; - input [1:0] PIPERX3CHARISK; - input [1:0] PIPERX4CHARISK; - input [1:0] PIPERX5CHARISK; - input [1:0] PIPERX6CHARISK; - input [1:0] PIPERX7CHARISK; - input [1:0] PLDIRECTEDLINKCHANGE; - input [1:0] PLDIRECTEDLINKWIDTH; - input [1:0] TRNTREM; - input [2:0] CFGDSFUNCTIONNUMBER; - input [2:0] CFGFORCEMPS; - input [2:0] PIPERX0STATUS; - input [2:0] PIPERX1STATUS; - input [2:0] PIPERX2STATUS; - input [2:0] PIPERX3STATUS; - input [2:0] PIPERX4STATUS; - input [2:0] PIPERX5STATUS; - input [2:0] PIPERX6STATUS; - input [2:0] PIPERX7STATUS; - input [2:0] PLDBGMODE; - input [2:0] TRNFCSEL; - input [31:0] CFGMGMTDI; - input [31:0] TRNTDLLPDATA; - input [3:0] CFGMGMTBYTEENN; - input [47:0] CFGERRTLPCPLHEADER; - input [4:0] CFGAERINTERRUPTMSGNUM; - input [4:0] CFGDSDEVICENUMBER; - input [4:0] CFGPCIECAPINTERRUPTMSGNUM; - input [4:0] PL2DIRECTEDLSTATE; - input [5:0] PLDIRECTEDLTSSMNEW; - input [63:0] CFGDSN; - input [67:0] MIMRXRDATA; - input [68:0] MIMTXRDATA; - input [7:0] CFGDSBUSNUMBER; - input [7:0] CFGINTERRUPTDI; - input [7:0] CFGPORTNUMBER; - input [7:0] CFGREVID; - input [8:0] DRPADDR; - input [9:0] CFGMGMTDWADDR; -endmodule - -module PCIE_3_0 (...); - parameter ARI_CAP_ENABLE = "FALSE"; - parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE"; - parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE"; - parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE"; - parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE"; - parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000; - parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE"; - parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE"; - parameter AXISTEN_IF_RC_STRADDLE = "FALSE"; - parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE"; - parameter AXISTEN_IF_RQ_PARITY_CHK = "TRUE"; - parameter [1:0] AXISTEN_IF_WIDTH = 2'h2; - parameter CRM_CORE_CLK_FREQ_500 = "TRUE"; - parameter [1:0] CRM_USER_CLK_FREQ = 2'h2; - parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; - parameter [1:0] GEN3_PCS_AUTO_REALIGN = 2'h1; - parameter GEN3_PCS_RX_ELECIDLE_INTERNAL = "TRUE"; - parameter [8:0] LL_ACK_TIMEOUT = 9'h000; - parameter LL_ACK_TIMEOUT_EN = "FALSE"; - parameter integer LL_ACK_TIMEOUT_FUNC = 0; - parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0000; - parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; - parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0000; - parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; - parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0000; - parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; - parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0000; - parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; - parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000; - parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; - parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; - parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0FA; - parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE"; - parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE"; - parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; - parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; - parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000; - parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00; - parameter [3:0] PF0_ARI_CAP_VER = 4'h1; - parameter [4:0] PF0_BAR0_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_BAR0_CONTROL = 3'h4; - parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF0_BAR1_CONTROL = 3'h0; - parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_BAR2_CONTROL = 3'h4; - parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_BAR3_CONTROL = 3'h0; - parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_BAR4_CONTROL = 3'h4; - parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_BAR5_CONTROL = 3'h0; - parameter [7:0] PF0_BIST_REGISTER = 8'h00; - parameter [7:0] PF0_CAPABILITY_POINTER = 8'h50; - parameter [23:0] PF0_CLASS_CODE = 24'h000000; - parameter [15:0] PF0_DEVICE_ID = 16'h0000; - parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE"; - parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; - parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; - parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE"; - parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE"; - parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0; - parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE"; - parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0; - parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0; - parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; - parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE"; - parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; - parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h000; - parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h00; - parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; - parameter [3:0] PF0_DPA_CAP_VER = 4'h1; - parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C; - parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03; - parameter PF0_EXPANSION_ROM_ENABLE = "FALSE"; - parameter [7:0] PF0_INTERRUPT_LINE = 8'h00; - parameter [2:0] PF0_INTERRUPT_PIN = 3'h1; - parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7; - parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; - parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000; - parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000; - parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000; - parameter [3:0] PF0_LTR_CAP_VER = 4'h1; - parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer PF0_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer PF0_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00; - parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h000; - parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; - parameter [3:0] PF0_PB_CAP_VER = 4'h1; - parameter [7:0] PF0_PM_CAP_ID = 8'h01; - parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00; - parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE"; - parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE"; - parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE"; - parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE"; - parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3; - parameter PF0_PM_CSR_NOSOFTRESET = "TRUE"; - parameter PF0_RBAR_CAP_ENABLE = "FALSE"; - parameter [2:0] PF0_RBAR_CAP_INDEX0 = 3'h0; - parameter [2:0] PF0_RBAR_CAP_INDEX1 = 3'h0; - parameter [2:0] PF0_RBAR_CAP_INDEX2 = 3'h0; - parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h000; - parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h00000; - parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h00000; - parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h00000; - parameter [3:0] PF0_RBAR_CAP_VER = 4'h1; - parameter [2:0] PF0_RBAR_NUM = 3'h1; - parameter [7:0] PF0_REVISION_ID = 8'h00; - parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4; - parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0; - parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4; - parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0; - parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4; - parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0; - parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000; - parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000; - parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000; - parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1; - parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000; - parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000; - parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; - parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000; - parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0000; - parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter PF0_TPHR_CAP_ENABLE = "FALSE"; - parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] PF0_TPHR_CAP_VER = 4'h1; - parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000; - parameter [3:0] PF0_VC_CAP_VER = 4'h1; - parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; - parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; - parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000; - parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00; - parameter [4:0] PF1_BAR0_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_BAR0_CONTROL = 3'h4; - parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF1_BAR1_CONTROL = 3'h0; - parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_BAR2_CONTROL = 3'h4; - parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_BAR3_CONTROL = 3'h0; - parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_BAR4_CONTROL = 3'h4; - parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_BAR5_CONTROL = 3'h0; - parameter [7:0] PF1_BIST_REGISTER = 8'h00; - parameter [7:0] PF1_CAPABILITY_POINTER = 8'h50; - parameter [23:0] PF1_CLASS_CODE = 24'h000000; - parameter [15:0] PF1_DEVICE_ID = 16'h0000; - parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; - parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h000; - parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h00; - parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; - parameter [3:0] PF1_DPA_CAP_VER = 4'h1; - parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C; - parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03; - parameter PF1_EXPANSION_ROM_ENABLE = "FALSE"; - parameter [7:0] PF1_INTERRUPT_LINE = 8'h00; - parameter [2:0] PF1_INTERRUPT_PIN = 3'h1; - parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer PF1_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer PF1_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00; - parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h000; - parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; - parameter [3:0] PF1_PB_CAP_VER = 4'h1; - parameter [7:0] PF1_PM_CAP_ID = 8'h01; - parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] PF1_PM_CAP_VER_ID = 3'h3; - parameter PF1_RBAR_CAP_ENABLE = "FALSE"; - parameter [2:0] PF1_RBAR_CAP_INDEX0 = 3'h0; - parameter [2:0] PF1_RBAR_CAP_INDEX1 = 3'h0; - parameter [2:0] PF1_RBAR_CAP_INDEX2 = 3'h0; - parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h000; - parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h00000; - parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h00000; - parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h00000; - parameter [3:0] PF1_RBAR_CAP_VER = 4'h1; - parameter [2:0] PF1_RBAR_NUM = 3'h1; - parameter [7:0] PF1_REVISION_ID = 8'h00; - parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4; - parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0; - parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4; - parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0; - parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4; - parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0; - parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000; - parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000; - parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000; - parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1; - parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000; - parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000; - parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; - parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000; - parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0000; - parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter PF1_TPHR_CAP_ENABLE = "FALSE"; - parameter PF1_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] PF1_TPHR_CAP_VER = 4'h1; - parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE"; - parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE"; - parameter PL_DISABLE_SCRAMBLING = "FALSE"; - parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE"; - parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE"; - parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE"; - parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02; - parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1; - parameter PL_EQ_BYPASS_PHASE23 = "FALSE"; - parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE"; - parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h3F00; - parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4; - parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h8; - parameter integer PL_N_FTS_COMCLK_GEN1 = 255; - parameter integer PL_N_FTS_COMCLK_GEN2 = 255; - parameter integer PL_N_FTS_COMCLK_GEN3 = 255; - parameter integer PL_N_FTS_GEN1 = 255; - parameter integer PL_N_FTS_GEN2 = 255; - parameter integer PL_N_FTS_GEN3 = 255; - parameter PL_SIM_FAST_LINK_TRAINING = "FALSE"; - parameter PL_UPSTREAM_FACING = "TRUE"; - parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h05DC; - parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h00000; - parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE"; - parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000000; - parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h186A0; - parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0064; - parameter SIM_VERSION = "1.0"; - parameter integer SPARE_BIT0 = 0; - parameter integer SPARE_BIT1 = 0; - parameter integer SPARE_BIT2 = 0; - parameter integer SPARE_BIT3 = 0; - parameter integer SPARE_BIT4 = 0; - parameter integer SPARE_BIT5 = 0; - parameter integer SPARE_BIT6 = 0; - parameter integer SPARE_BIT7 = 0; - parameter integer SPARE_BIT8 = 0; - parameter [7:0] SPARE_BYTE0 = 8'h00; - parameter [7:0] SPARE_BYTE1 = 8'h00; - parameter [7:0] SPARE_BYTE2 = 8'h00; - parameter [7:0] SPARE_BYTE3 = 8'h00; - parameter [31:0] SPARE_WORD0 = 32'h00000000; - parameter [31:0] SPARE_WORD1 = 32'h00000000; - parameter [31:0] SPARE_WORD2 = 32'h00000000; - parameter [31:0] SPARE_WORD3 = 32'h00000000; - parameter SRIOV_CAP_ENABLE = "FALSE"; - parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'hBEBC20; - parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h0000000; - parameter [11:0] TL_CREDITS_CD = 12'h3E0; - parameter [7:0] TL_CREDITS_CH = 8'h20; - parameter [11:0] TL_CREDITS_NPD = 12'h028; - parameter [7:0] TL_CREDITS_NPH = 8'h20; - parameter [11:0] TL_CREDITS_PD = 12'h198; - parameter [7:0] TL_CREDITS_PH = 8'h20; - parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "TRUE"; - parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; - parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; - parameter TL_LEGACY_MODE_ENABLE = "FALSE"; - parameter TL_PF_ENABLE_REG = "FALSE"; - parameter TL_TAG_MGMT_ENABLE = "TRUE"; - parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] VF0_CAPABILITY_POINTER = 8'h50; - parameter integer VF0_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF0_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF0_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF0_PM_CAP_ID = 8'h01; - parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF0_PM_CAP_VER_ID = 3'h3; - parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF0_TPHR_CAP_ENABLE = "FALSE"; - parameter VF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF0_TPHR_CAP_VER = 4'h1; - parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h000; - parameter integer VF1_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF1_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF1_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF1_PM_CAP_ID = 8'h01; - parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF1_PM_CAP_VER_ID = 3'h3; - parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF1_TPHR_CAP_ENABLE = "FALSE"; - parameter VF1_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF1_TPHR_CAP_VER = 4'h1; - parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h000; - parameter integer VF2_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF2_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF2_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF2_PM_CAP_ID = 8'h01; - parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF2_PM_CAP_VER_ID = 3'h3; - parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF2_TPHR_CAP_ENABLE = "FALSE"; - parameter VF2_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF2_TPHR_CAP_VER = 4'h1; - parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h000; - parameter integer VF3_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF3_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF3_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF3_PM_CAP_ID = 8'h01; - parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF3_PM_CAP_VER_ID = 3'h3; - parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF3_TPHR_CAP_ENABLE = "FALSE"; - parameter VF3_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF3_TPHR_CAP_VER = 4'h1; - parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h000; - parameter integer VF4_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF4_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF4_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF4_PM_CAP_ID = 8'h01; - parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF4_PM_CAP_VER_ID = 3'h3; - parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF4_TPHR_CAP_ENABLE = "FALSE"; - parameter VF4_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF4_TPHR_CAP_VER = 4'h1; - parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h000; - parameter integer VF5_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF5_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF5_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF5_PM_CAP_ID = 8'h01; - parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF5_PM_CAP_VER_ID = 3'h3; - parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF5_TPHR_CAP_ENABLE = "FALSE"; - parameter VF5_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF5_TPHR_CAP_VER = 4'h1; - output CFGERRCOROUT; - output CFGERRFATALOUT; - output CFGERRNONFATALOUT; - output CFGEXTREADRECEIVED; - output CFGEXTWRITERECEIVED; - output CFGHOTRESETOUT; - output CFGINPUTUPDATEDONE; - output CFGINTERRUPTAOUTPUT; - output CFGINTERRUPTBOUTPUT; - output CFGINTERRUPTCOUTPUT; - output CFGINTERRUPTDOUTPUT; - output CFGINTERRUPTMSIFAIL; - output CFGINTERRUPTMSIMASKUPDATE; - output CFGINTERRUPTMSISENT; - output CFGINTERRUPTMSIXFAIL; - output CFGINTERRUPTMSIXSENT; - output CFGINTERRUPTSENT; - output CFGLOCALERROR; - output CFGLTRENABLE; - output CFGMCUPDATEDONE; - output CFGMGMTREADWRITEDONE; - output CFGMSGRECEIVED; - output CFGMSGTRANSMITDONE; - output CFGPERFUNCTIONUPDATEDONE; - output CFGPHYLINKDOWN; - output CFGPLSTATUSCHANGE; - output CFGPOWERSTATECHANGEINTERRUPT; - output CFGTPHSTTREADENABLE; - output CFGTPHSTTWRITEENABLE; - output DRPRDY; - output MAXISCQTLAST; - output MAXISCQTVALID; - output MAXISRCTLAST; - output MAXISRCTVALID; - output PCIERQSEQNUMVLD; - output PCIERQTAGVLD; - output PIPERX0POLARITY; - output PIPERX1POLARITY; - output PIPERX2POLARITY; - output PIPERX3POLARITY; - output PIPERX4POLARITY; - output PIPERX5POLARITY; - output PIPERX6POLARITY; - output PIPERX7POLARITY; - output PIPETX0COMPLIANCE; - output PIPETX0DATAVALID; - output PIPETX0ELECIDLE; - output PIPETX0STARTBLOCK; - output PIPETX1COMPLIANCE; - output PIPETX1DATAVALID; - output PIPETX1ELECIDLE; - output PIPETX1STARTBLOCK; - output PIPETX2COMPLIANCE; - output PIPETX2DATAVALID; - output PIPETX2ELECIDLE; - output PIPETX2STARTBLOCK; - output PIPETX3COMPLIANCE; - output PIPETX3DATAVALID; - output PIPETX3ELECIDLE; - output PIPETX3STARTBLOCK; - output PIPETX4COMPLIANCE; - output PIPETX4DATAVALID; - output PIPETX4ELECIDLE; - output PIPETX4STARTBLOCK; - output PIPETX5COMPLIANCE; - output PIPETX5DATAVALID; - output PIPETX5ELECIDLE; - output PIPETX5STARTBLOCK; - output PIPETX6COMPLIANCE; - output PIPETX6DATAVALID; - output PIPETX6ELECIDLE; - output PIPETX6STARTBLOCK; - output PIPETX7COMPLIANCE; - output PIPETX7DATAVALID; - output PIPETX7ELECIDLE; - output PIPETX7STARTBLOCK; - output PIPETXDEEMPH; - output PIPETXRCVRDET; - output PIPETXRESET; - output PIPETXSWING; - output PLEQINPROGRESS; - output [11:0] CFGFCCPLD; - output [11:0] CFGFCNPD; - output [11:0] CFGFCPD; - output [11:0] CFGVFSTATUS; - output [143:0] MIREPLAYRAMWRITEDATA; - output [143:0] MIREQUESTRAMWRITEDATA; - output [15:0] CFGPERFUNCSTATUSDATA; - output [15:0] DBGDATAOUT; - output [15:0] DRPDO; - output [17:0] CFGVFPOWERSTATE; - output [17:0] CFGVFTPHSTMODE; - output [1:0] CFGDPASUBSTATECHANGE; - output [1:0] CFGFLRINPROCESS; - output [1:0] CFGINTERRUPTMSIENABLE; - output [1:0] CFGINTERRUPTMSIXENABLE; - output [1:0] CFGINTERRUPTMSIXMASK; - output [1:0] CFGLINKPOWERSTATE; - output [1:0] CFGOBFFENABLE; - output [1:0] CFGPHYLINKSTATUS; - output [1:0] CFGRCBSTATUS; - output [1:0] CFGTPHREQUESTERENABLE; - output [1:0] MIREPLAYRAMREADENABLE; - output [1:0] MIREPLAYRAMWRITEENABLE; - output [1:0] PCIERQTAGAV; - output [1:0] PCIETFCNPDAV; - output [1:0] PCIETFCNPHAV; - output [1:0] PIPERX0EQCONTROL; - output [1:0] PIPERX1EQCONTROL; - output [1:0] PIPERX2EQCONTROL; - output [1:0] PIPERX3EQCONTROL; - output [1:0] PIPERX4EQCONTROL; - output [1:0] PIPERX5EQCONTROL; - output [1:0] PIPERX6EQCONTROL; - output [1:0] PIPERX7EQCONTROL; - output [1:0] PIPETX0CHARISK; - output [1:0] PIPETX0EQCONTROL; - output [1:0] PIPETX0POWERDOWN; - output [1:0] PIPETX0SYNCHEADER; - output [1:0] PIPETX1CHARISK; - output [1:0] PIPETX1EQCONTROL; - output [1:0] PIPETX1POWERDOWN; - output [1:0] PIPETX1SYNCHEADER; - output [1:0] PIPETX2CHARISK; - output [1:0] PIPETX2EQCONTROL; - output [1:0] PIPETX2POWERDOWN; - output [1:0] PIPETX2SYNCHEADER; - output [1:0] PIPETX3CHARISK; - output [1:0] PIPETX3EQCONTROL; - output [1:0] PIPETX3POWERDOWN; - output [1:0] PIPETX3SYNCHEADER; - output [1:0] PIPETX4CHARISK; - output [1:0] PIPETX4EQCONTROL; - output [1:0] PIPETX4POWERDOWN; - output [1:0] PIPETX4SYNCHEADER; - output [1:0] PIPETX5CHARISK; - output [1:0] PIPETX5EQCONTROL; - output [1:0] PIPETX5POWERDOWN; - output [1:0] PIPETX5SYNCHEADER; - output [1:0] PIPETX6CHARISK; - output [1:0] PIPETX6EQCONTROL; - output [1:0] PIPETX6POWERDOWN; - output [1:0] PIPETX6SYNCHEADER; - output [1:0] PIPETX7CHARISK; - output [1:0] PIPETX7EQCONTROL; - output [1:0] PIPETX7POWERDOWN; - output [1:0] PIPETX7SYNCHEADER; - output [1:0] PIPETXRATE; - output [1:0] PLEQPHASE; - output [255:0] MAXISCQTDATA; - output [255:0] MAXISRCTDATA; - output [2:0] CFGCURRENTSPEED; - output [2:0] CFGMAXPAYLOAD; - output [2:0] CFGMAXREADREQ; - output [2:0] CFGTPHFUNCTIONNUM; - output [2:0] PIPERX0EQPRESET; - output [2:0] PIPERX1EQPRESET; - output [2:0] PIPERX2EQPRESET; - output [2:0] PIPERX3EQPRESET; - output [2:0] PIPERX4EQPRESET; - output [2:0] PIPERX5EQPRESET; - output [2:0] PIPERX6EQPRESET; - output [2:0] PIPERX7EQPRESET; - output [2:0] PIPETXMARGIN; - output [31:0] CFGEXTWRITEDATA; - output [31:0] CFGINTERRUPTMSIDATA; - output [31:0] CFGMGMTREADDATA; - output [31:0] CFGTPHSTTWRITEDATA; - output [31:0] PIPETX0DATA; - output [31:0] PIPETX1DATA; - output [31:0] PIPETX2DATA; - output [31:0] PIPETX3DATA; - output [31:0] PIPETX4DATA; - output [31:0] PIPETX5DATA; - output [31:0] PIPETX6DATA; - output [31:0] PIPETX7DATA; - output [3:0] CFGEXTWRITEBYTEENABLE; - output [3:0] CFGNEGOTIATEDWIDTH; - output [3:0] CFGTPHSTTWRITEBYTEVALID; - output [3:0] MICOMPLETIONRAMREADENABLEL; - output [3:0] MICOMPLETIONRAMREADENABLEU; - output [3:0] MICOMPLETIONRAMWRITEENABLEL; - output [3:0] MICOMPLETIONRAMWRITEENABLEU; - output [3:0] MIREQUESTRAMREADENABLE; - output [3:0] MIREQUESTRAMWRITEENABLE; - output [3:0] PCIERQSEQNUM; - output [3:0] PIPERX0EQLPTXPRESET; - output [3:0] PIPERX1EQLPTXPRESET; - output [3:0] PIPERX2EQLPTXPRESET; - output [3:0] PIPERX3EQLPTXPRESET; - output [3:0] PIPERX4EQLPTXPRESET; - output [3:0] PIPERX5EQLPTXPRESET; - output [3:0] PIPERX6EQLPTXPRESET; - output [3:0] PIPERX7EQLPTXPRESET; - output [3:0] PIPETX0EQPRESET; - output [3:0] PIPETX1EQPRESET; - output [3:0] PIPETX2EQPRESET; - output [3:0] PIPETX3EQPRESET; - output [3:0] PIPETX4EQPRESET; - output [3:0] PIPETX5EQPRESET; - output [3:0] PIPETX6EQPRESET; - output [3:0] PIPETX7EQPRESET; - output [3:0] SAXISCCTREADY; - output [3:0] SAXISRQTREADY; - output [4:0] CFGMSGRECEIVEDTYPE; - output [4:0] CFGTPHSTTADDRESS; - output [5:0] CFGFUNCTIONPOWERSTATE; - output [5:0] CFGINTERRUPTMSIMMENABLE; - output [5:0] CFGINTERRUPTMSIVFENABLE; - output [5:0] CFGINTERRUPTMSIXVFENABLE; - output [5:0] CFGINTERRUPTMSIXVFMASK; - output [5:0] CFGLTSSMSTATE; - output [5:0] CFGTPHSTMODE; - output [5:0] CFGVFFLRINPROCESS; - output [5:0] CFGVFTPHREQUESTERENABLE; - output [5:0] PCIECQNPREQCOUNT; - output [5:0] PCIERQTAG; - output [5:0] PIPERX0EQLPLFFS; - output [5:0] PIPERX1EQLPLFFS; - output [5:0] PIPERX2EQLPLFFS; - output [5:0] PIPERX3EQLPLFFS; - output [5:0] PIPERX4EQLPLFFS; - output [5:0] PIPERX5EQLPLFFS; - output [5:0] PIPERX6EQLPLFFS; - output [5:0] PIPERX7EQLPLFFS; - output [5:0] PIPETX0EQDEEMPH; - output [5:0] PIPETX1EQDEEMPH; - output [5:0] PIPETX2EQDEEMPH; - output [5:0] PIPETX3EQDEEMPH; - output [5:0] PIPETX4EQDEEMPH; - output [5:0] PIPETX5EQDEEMPH; - output [5:0] PIPETX6EQDEEMPH; - output [5:0] PIPETX7EQDEEMPH; - output [71:0] MICOMPLETIONRAMWRITEDATAL; - output [71:0] MICOMPLETIONRAMWRITEDATAU; - output [74:0] MAXISRCTUSER; - output [7:0] CFGEXTFUNCTIONNUMBER; - output [7:0] CFGFCCPLH; - output [7:0] CFGFCNPH; - output [7:0] CFGFCPH; - output [7:0] CFGFUNCTIONSTATUS; - output [7:0] CFGMSGRECEIVEDDATA; - output [7:0] MAXISCQTKEEP; - output [7:0] MAXISRCTKEEP; - output [7:0] PLGEN3PCSRXSLIDE; - output [84:0] MAXISCQTUSER; - output [8:0] MIREPLAYRAMADDRESS; - output [8:0] MIREQUESTRAMREADADDRESSA; - output [8:0] MIREQUESTRAMREADADDRESSB; - output [8:0] MIREQUESTRAMWRITEADDRESSA; - output [8:0] MIREQUESTRAMWRITEADDRESSB; - output [9:0] CFGEXTREGISTERNUMBER; - output [9:0] MICOMPLETIONRAMREADADDRESSAL; - output [9:0] MICOMPLETIONRAMREADADDRESSAU; - output [9:0] MICOMPLETIONRAMREADADDRESSBL; - output [9:0] MICOMPLETIONRAMREADADDRESSBU; - output [9:0] MICOMPLETIONRAMWRITEADDRESSAL; - output [9:0] MICOMPLETIONRAMWRITEADDRESSAU; - output [9:0] MICOMPLETIONRAMWRITEADDRESSBL; - output [9:0] MICOMPLETIONRAMWRITEADDRESSBU; - input CFGCONFIGSPACEENABLE; - input CFGERRCORIN; - input CFGERRUNCORIN; - input CFGEXTREADDATAVALID; - input CFGHOTRESETIN; - input CFGINPUTUPDATEREQUEST; - input CFGINTERRUPTMSITPHPRESENT; - input CFGINTERRUPTMSIXINT; - input CFGLINKTRAININGENABLE; - input CFGMCUPDATEREQUEST; - input CFGMGMTREAD; - input CFGMGMTTYPE1CFGREGACCESS; - input CFGMGMTWRITE; - input CFGMSGTRANSMIT; - input CFGPERFUNCTIONOUTPUTREQUEST; - input CFGPOWERSTATECHANGEACK; - input CFGREQPMTRANSITIONL23READY; - input CFGTPHSTTREADDATAVALID; - input CORECLK; - input CORECLKMICOMPLETIONRAML; - input CORECLKMICOMPLETIONRAMU; - input CORECLKMIREPLAYRAM; - input CORECLKMIREQUESTRAM; - input DRPCLK; - input DRPEN; - input DRPWE; - input MGMTRESETN; - input MGMTSTICKYRESETN; - input PCIECQNPREQ; - input PIPECLK; - input PIPERESETN; - input PIPERX0DATAVALID; - input PIPERX0ELECIDLE; - input PIPERX0EQDONE; - input PIPERX0EQLPADAPTDONE; - input PIPERX0EQLPLFFSSEL; - input PIPERX0PHYSTATUS; - input PIPERX0STARTBLOCK; - input PIPERX0VALID; - input PIPERX1DATAVALID; - input PIPERX1ELECIDLE; - input PIPERX1EQDONE; - input PIPERX1EQLPADAPTDONE; - input PIPERX1EQLPLFFSSEL; - input PIPERX1PHYSTATUS; - input PIPERX1STARTBLOCK; - input PIPERX1VALID; - input PIPERX2DATAVALID; - input PIPERX2ELECIDLE; - input PIPERX2EQDONE; - input PIPERX2EQLPADAPTDONE; - input PIPERX2EQLPLFFSSEL; - input PIPERX2PHYSTATUS; - input PIPERX2STARTBLOCK; - input PIPERX2VALID; - input PIPERX3DATAVALID; - input PIPERX3ELECIDLE; - input PIPERX3EQDONE; - input PIPERX3EQLPADAPTDONE; - input PIPERX3EQLPLFFSSEL; - input PIPERX3PHYSTATUS; - input PIPERX3STARTBLOCK; - input PIPERX3VALID; - input PIPERX4DATAVALID; - input PIPERX4ELECIDLE; - input PIPERX4EQDONE; - input PIPERX4EQLPADAPTDONE; - input PIPERX4EQLPLFFSSEL; - input PIPERX4PHYSTATUS; - input PIPERX4STARTBLOCK; - input PIPERX4VALID; - input PIPERX5DATAVALID; - input PIPERX5ELECIDLE; - input PIPERX5EQDONE; - input PIPERX5EQLPADAPTDONE; - input PIPERX5EQLPLFFSSEL; - input PIPERX5PHYSTATUS; - input PIPERX5STARTBLOCK; - input PIPERX5VALID; - input PIPERX6DATAVALID; - input PIPERX6ELECIDLE; - input PIPERX6EQDONE; - input PIPERX6EQLPADAPTDONE; - input PIPERX6EQLPLFFSSEL; - input PIPERX6PHYSTATUS; - input PIPERX6STARTBLOCK; - input PIPERX6VALID; - input PIPERX7DATAVALID; - input PIPERX7ELECIDLE; - input PIPERX7EQDONE; - input PIPERX7EQLPADAPTDONE; - input PIPERX7EQLPLFFSSEL; - input PIPERX7PHYSTATUS; - input PIPERX7STARTBLOCK; - input PIPERX7VALID; - input PIPETX0EQDONE; - input PIPETX1EQDONE; - input PIPETX2EQDONE; - input PIPETX3EQDONE; - input PIPETX4EQDONE; - input PIPETX5EQDONE; - input PIPETX6EQDONE; - input PIPETX7EQDONE; - input PLDISABLESCRAMBLER; - input PLEQRESETEIEOSCOUNT; - input PLGEN3PCSDISABLE; - input RECCLK; - input RESETN; - input SAXISCCTLAST; - input SAXISCCTVALID; - input SAXISRQTLAST; - input SAXISRQTVALID; - input USERCLK; - input [10:0] DRPADDR; - input [143:0] MICOMPLETIONRAMREADDATA; - input [143:0] MIREPLAYRAMREADDATA; - input [143:0] MIREQUESTRAMREADDATA; - input [15:0] CFGDEVID; - input [15:0] CFGSUBSYSID; - input [15:0] CFGSUBSYSVENDID; - input [15:0] CFGVENDID; - input [15:0] DRPDI; - input [17:0] PIPERX0EQLPNEWTXCOEFFORPRESET; - input [17:0] PIPERX1EQLPNEWTXCOEFFORPRESET; - input [17:0] PIPERX2EQLPNEWTXCOEFFORPRESET; - input [17:0] PIPERX3EQLPNEWTXCOEFFORPRESET; - input [17:0] PIPERX4EQLPNEWTXCOEFFORPRESET; - input [17:0] PIPERX5EQLPNEWTXCOEFFORPRESET; - input [17:0] PIPERX6EQLPNEWTXCOEFFORPRESET; - input [17:0] PIPERX7EQLPNEWTXCOEFFORPRESET; - input [17:0] PIPETX0EQCOEFF; - input [17:0] PIPETX1EQCOEFF; - input [17:0] PIPETX2EQCOEFF; - input [17:0] PIPETX3EQCOEFF; - input [17:0] PIPETX4EQCOEFF; - input [17:0] PIPETX5EQCOEFF; - input [17:0] PIPETX6EQCOEFF; - input [17:0] PIPETX7EQCOEFF; - input [18:0] CFGMGMTADDR; - input [1:0] CFGFLRDONE; - input [1:0] CFGINTERRUPTMSITPHTYPE; - input [1:0] CFGINTERRUPTPENDING; - input [1:0] PIPERX0CHARISK; - input [1:0] PIPERX0SYNCHEADER; - input [1:0] PIPERX1CHARISK; - input [1:0] PIPERX1SYNCHEADER; - input [1:0] PIPERX2CHARISK; - input [1:0] PIPERX2SYNCHEADER; - input [1:0] PIPERX3CHARISK; - input [1:0] PIPERX3SYNCHEADER; - input [1:0] PIPERX4CHARISK; - input [1:0] PIPERX4SYNCHEADER; - input [1:0] PIPERX5CHARISK; - input [1:0] PIPERX5SYNCHEADER; - input [1:0] PIPERX6CHARISK; - input [1:0] PIPERX6SYNCHEADER; - input [1:0] PIPERX7CHARISK; - input [1:0] PIPERX7SYNCHEADER; - input [21:0] MAXISCQTREADY; - input [21:0] MAXISRCTREADY; - input [255:0] SAXISCCTDATA; - input [255:0] SAXISRQTDATA; - input [2:0] CFGDSFUNCTIONNUMBER; - input [2:0] CFGFCSEL; - input [2:0] CFGINTERRUPTMSIATTR; - input [2:0] CFGINTERRUPTMSIFUNCTIONNUMBER; - input [2:0] CFGMSGTRANSMITTYPE; - input [2:0] CFGPERFUNCSTATUSCONTROL; - input [2:0] CFGPERFUNCTIONNUMBER; - input [2:0] PIPERX0STATUS; - input [2:0] PIPERX1STATUS; - input [2:0] PIPERX2STATUS; - input [2:0] PIPERX3STATUS; - input [2:0] PIPERX4STATUS; - input [2:0] PIPERX5STATUS; - input [2:0] PIPERX6STATUS; - input [2:0] PIPERX7STATUS; - input [31:0] CFGEXTREADDATA; - input [31:0] CFGINTERRUPTMSIINT; - input [31:0] CFGINTERRUPTMSIXDATA; - input [31:0] CFGMGMTWRITEDATA; - input [31:0] CFGMSGTRANSMITDATA; - input [31:0] CFGTPHSTTREADDATA; - input [31:0] PIPERX0DATA; - input [31:0] PIPERX1DATA; - input [31:0] PIPERX2DATA; - input [31:0] PIPERX3DATA; - input [31:0] PIPERX4DATA; - input [31:0] PIPERX5DATA; - input [31:0] PIPERX6DATA; - input [31:0] PIPERX7DATA; - input [32:0] SAXISCCTUSER; - input [3:0] CFGINTERRUPTINT; - input [3:0] CFGINTERRUPTMSISELECT; - input [3:0] CFGMGMTBYTEENABLE; - input [4:0] CFGDSDEVICENUMBER; - input [59:0] SAXISRQTUSER; - input [5:0] CFGVFFLRDONE; - input [5:0] PIPEEQFS; - input [5:0] PIPEEQLF; - input [63:0] CFGDSN; - input [63:0] CFGINTERRUPTMSIPENDINGSTATUS; - input [63:0] CFGINTERRUPTMSIXADDRESS; - input [7:0] CFGDSBUSNUMBER; - input [7:0] CFGDSPORTNUMBER; - input [7:0] CFGREVID; - input [7:0] PLGEN3PCSRXSYNCDONE; - input [7:0] SAXISCCTKEEP; - input [7:0] SAXISRQTKEEP; - input [8:0] CFGINTERRUPTMSITPHSTTAG; -endmodule - -module PCIE_3_1 (...); - parameter ARI_CAP_ENABLE = "FALSE"; - parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE"; - parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE"; - parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE"; - parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE"; - parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000; - parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE"; - parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE"; - parameter AXISTEN_IF_RC_STRADDLE = "FALSE"; - parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE"; - parameter AXISTEN_IF_RQ_PARITY_CHK = "TRUE"; - parameter [1:0] AXISTEN_IF_WIDTH = 2'h2; - parameter CRM_CORE_CLK_FREQ_500 = "TRUE"; - parameter [1:0] CRM_USER_CLK_FREQ = 2'h2; - parameter DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE = "FALSE"; - parameter DEBUG_PL_DISABLE_EI_INFER_IN_L0 = "FALSE"; - parameter DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS = "FALSE"; - parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; - parameter [8:0] LL_ACK_TIMEOUT = 9'h000; - parameter LL_ACK_TIMEOUT_EN = "FALSE"; - parameter integer LL_ACK_TIMEOUT_FUNC = 0; - parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0000; - parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; - parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0000; - parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; - parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0000; - parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; - parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0000; - parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; - parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000; - parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; - parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; - parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0FA; - parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE"; - parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE"; - parameter [11:0] MCAP_CAP_NEXTPTR = 12'h000; - parameter MCAP_CONFIGURE_OVERRIDE = "FALSE"; - parameter MCAP_ENABLE = "FALSE"; - parameter MCAP_EOS_DESIGN_SWITCH = "FALSE"; - parameter [31:0] MCAP_FPGA_BITSTREAM_VERSION = 32'h00000000; - parameter MCAP_GATE_IO_ENABLE_DESIGN_SWITCH = "FALSE"; - parameter MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH = "FALSE"; - parameter MCAP_INPUT_GATE_DESIGN_SWITCH = "FALSE"; - parameter MCAP_INTERRUPT_ON_MCAP_EOS = "FALSE"; - parameter MCAP_INTERRUPT_ON_MCAP_ERROR = "FALSE"; - parameter [15:0] MCAP_VSEC_ID = 16'h0000; - parameter [11:0] MCAP_VSEC_LEN = 12'h02C; - parameter [3:0] MCAP_VSEC_REV = 4'h0; - parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; - parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; - parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000; - parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00; - parameter [3:0] PF0_ARI_CAP_VER = 4'h1; - parameter [5:0] PF0_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF0_BAR0_CONTROL = 3'h4; - parameter [5:0] PF0_BAR1_APERTURE_SIZE = 6'h00; - parameter [2:0] PF0_BAR1_CONTROL = 3'h0; - parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_BAR2_CONTROL = 3'h4; - parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_BAR3_CONTROL = 3'h0; - parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_BAR4_CONTROL = 3'h4; - parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_BAR5_CONTROL = 3'h0; - parameter [7:0] PF0_BIST_REGISTER = 8'h00; - parameter [7:0] PF0_CAPABILITY_POINTER = 8'h50; - parameter [23:0] PF0_CLASS_CODE = 24'h000000; - parameter [15:0] PF0_DEVICE_ID = 16'h0000; - parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE"; - parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; - parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; - parameter PF0_DEV_CAP2_ARI_FORWARD_ENABLE = "FALSE"; - parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE"; - parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE"; - parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0; - parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE"; - parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0; - parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0; - parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; - parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE"; - parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; - parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h000; - parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h00; - parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; - parameter [3:0] PF0_DPA_CAP_VER = 4'h1; - parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C; - parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03; - parameter PF0_EXPANSION_ROM_ENABLE = "FALSE"; - parameter [7:0] PF0_INTERRUPT_LINE = 8'h00; - parameter [2:0] PF0_INTERRUPT_PIN = 3'h1; - parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7; - parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; - parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000; - parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000; - parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000; - parameter [3:0] PF0_LTR_CAP_VER = 4'h1; - parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer PF0_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer PF0_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00; - parameter PF0_MSI_CAP_PERVECMASKCAP = "FALSE"; - parameter [31:0] PF0_PB_CAP_DATA_REG_D0 = 32'h00000000; - parameter [31:0] PF0_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000; - parameter [31:0] PF0_PB_CAP_DATA_REG_D1 = 32'h00000000; - parameter [31:0] PF0_PB_CAP_DATA_REG_D3HOT = 32'h00000000; - parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h000; - parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; - parameter [3:0] PF0_PB_CAP_VER = 4'h1; - parameter [7:0] PF0_PM_CAP_ID = 8'h01; - parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00; - parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE"; - parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE"; - parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE"; - parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE"; - parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3; - parameter PF0_PM_CSR_NOSOFTRESET = "TRUE"; - parameter PF0_RBAR_CAP_ENABLE = "FALSE"; - parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h000; - parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h00000; - parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h00000; - parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h00000; - parameter [3:0] PF0_RBAR_CAP_VER = 4'h1; - parameter [2:0] PF0_RBAR_CONTROL_INDEX0 = 3'h0; - parameter [2:0] PF0_RBAR_CONTROL_INDEX1 = 3'h0; - parameter [2:0] PF0_RBAR_CONTROL_INDEX2 = 3'h0; - parameter [4:0] PF0_RBAR_CONTROL_SIZE0 = 5'h00; - parameter [4:0] PF0_RBAR_CONTROL_SIZE1 = 5'h00; - parameter [4:0] PF0_RBAR_CONTROL_SIZE2 = 5'h00; - parameter [2:0] PF0_RBAR_NUM = 3'h1; - parameter [7:0] PF0_REVISION_ID = 8'h00; - parameter [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR = 12'h000; - parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4; - parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0; - parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4; - parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0; - parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4; - parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0; - parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000; - parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000; - parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000; - parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1; - parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000; - parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000; - parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; - parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000; - parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0000; - parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter PF0_TPHR_CAP_ENABLE = "FALSE"; - parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] PF0_TPHR_CAP_VER = 4'h1; - parameter PF0_VC_CAP_ENABLE = "FALSE"; - parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000; - parameter [3:0] PF0_VC_CAP_VER = 4'h1; - parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; - parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; - parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000; - parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00; - parameter [5:0] PF1_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF1_BAR0_CONTROL = 3'h4; - parameter [5:0] PF1_BAR1_APERTURE_SIZE = 6'h00; - parameter [2:0] PF1_BAR1_CONTROL = 3'h0; - parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_BAR2_CONTROL = 3'h4; - parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_BAR3_CONTROL = 3'h0; - parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_BAR4_CONTROL = 3'h4; - parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_BAR5_CONTROL = 3'h0; - parameter [7:0] PF1_BIST_REGISTER = 8'h00; - parameter [7:0] PF1_CAPABILITY_POINTER = 8'h50; - parameter [23:0] PF1_CLASS_CODE = 24'h000000; - parameter [15:0] PF1_DEVICE_ID = 16'h0000; - parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; - parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h000; - parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h00; - parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; - parameter [3:0] PF1_DPA_CAP_VER = 4'h1; - parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C; - parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03; - parameter PF1_EXPANSION_ROM_ENABLE = "FALSE"; - parameter [7:0] PF1_INTERRUPT_LINE = 8'h00; - parameter [2:0] PF1_INTERRUPT_PIN = 3'h1; - parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer PF1_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer PF1_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00; - parameter PF1_MSI_CAP_PERVECMASKCAP = "FALSE"; - parameter [31:0] PF1_PB_CAP_DATA_REG_D0 = 32'h00000000; - parameter [31:0] PF1_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000; - parameter [31:0] PF1_PB_CAP_DATA_REG_D1 = 32'h00000000; - parameter [31:0] PF1_PB_CAP_DATA_REG_D3HOT = 32'h00000000; - parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h000; - parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; - parameter [3:0] PF1_PB_CAP_VER = 4'h1; - parameter [7:0] PF1_PM_CAP_ID = 8'h01; - parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] PF1_PM_CAP_VER_ID = 3'h3; - parameter PF1_RBAR_CAP_ENABLE = "FALSE"; - parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h000; - parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h00000; - parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h00000; - parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h00000; - parameter [3:0] PF1_RBAR_CAP_VER = 4'h1; - parameter [2:0] PF1_RBAR_CONTROL_INDEX0 = 3'h0; - parameter [2:0] PF1_RBAR_CONTROL_INDEX1 = 3'h0; - parameter [2:0] PF1_RBAR_CONTROL_INDEX2 = 3'h0; - parameter [4:0] PF1_RBAR_CONTROL_SIZE0 = 5'h00; - parameter [4:0] PF1_RBAR_CONTROL_SIZE1 = 5'h00; - parameter [4:0] PF1_RBAR_CONTROL_SIZE2 = 5'h00; - parameter [2:0] PF1_RBAR_NUM = 3'h1; - parameter [7:0] PF1_REVISION_ID = 8'h00; - parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4; - parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0; - parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4; - parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0; - parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4; - parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0; - parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000; - parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000; - parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000; - parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1; - parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000; - parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000; - parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; - parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000; - parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0000; - parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter PF1_TPHR_CAP_ENABLE = "FALSE"; - parameter PF1_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] PF1_TPHR_CAP_VER = 4'h1; - parameter PF2_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; - parameter PF2_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; - parameter [11:0] PF2_AER_CAP_NEXTPTR = 12'h000; - parameter [11:0] PF2_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] PF2_ARI_CAP_NEXT_FUNC = 8'h00; - parameter [5:0] PF2_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF2_BAR0_CONTROL = 3'h4; - parameter [5:0] PF2_BAR1_APERTURE_SIZE = 6'h00; - parameter [2:0] PF2_BAR1_CONTROL = 3'h0; - parameter [4:0] PF2_BAR2_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_BAR2_CONTROL = 3'h4; - parameter [4:0] PF2_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_BAR3_CONTROL = 3'h0; - parameter [4:0] PF2_BAR4_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_BAR4_CONTROL = 3'h4; - parameter [4:0] PF2_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_BAR5_CONTROL = 3'h0; - parameter [7:0] PF2_BIST_REGISTER = 8'h00; - parameter [7:0] PF2_CAPABILITY_POINTER = 8'h50; - parameter [23:0] PF2_CLASS_CODE = 24'h000000; - parameter [15:0] PF2_DEVICE_ID = 16'h0000; - parameter [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; - parameter [11:0] PF2_DPA_CAP_NEXTPTR = 12'h000; - parameter [4:0] PF2_DPA_CAP_SUB_STATE_CONTROL = 5'h00; - parameter PF2_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; - parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; - parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; - parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; - parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; - parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; - parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; - parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; - parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; - parameter [3:0] PF2_DPA_CAP_VER = 4'h1; - parameter [11:0] PF2_DSN_CAP_NEXTPTR = 12'h10C; - parameter [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE = 5'h03; - parameter PF2_EXPANSION_ROM_ENABLE = "FALSE"; - parameter [7:0] PF2_INTERRUPT_LINE = 8'h00; - parameter [2:0] PF2_INTERRUPT_PIN = 3'h1; - parameter [7:0] PF2_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer PF2_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] PF2_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer PF2_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] PF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] PF2_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer PF2_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] PF2_MSI_CAP_NEXTPTR = 8'h00; - parameter PF2_MSI_CAP_PERVECMASKCAP = "FALSE"; - parameter [31:0] PF2_PB_CAP_DATA_REG_D0 = 32'h00000000; - parameter [31:0] PF2_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000; - parameter [31:0] PF2_PB_CAP_DATA_REG_D1 = 32'h00000000; - parameter [31:0] PF2_PB_CAP_DATA_REG_D3HOT = 32'h00000000; - parameter [11:0] PF2_PB_CAP_NEXTPTR = 12'h000; - parameter PF2_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; - parameter [3:0] PF2_PB_CAP_VER = 4'h1; - parameter [7:0] PF2_PM_CAP_ID = 8'h01; - parameter [7:0] PF2_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] PF2_PM_CAP_VER_ID = 3'h3; - parameter PF2_RBAR_CAP_ENABLE = "FALSE"; - parameter [11:0] PF2_RBAR_CAP_NEXTPTR = 12'h000; - parameter [19:0] PF2_RBAR_CAP_SIZE0 = 20'h00000; - parameter [19:0] PF2_RBAR_CAP_SIZE1 = 20'h00000; - parameter [19:0] PF2_RBAR_CAP_SIZE2 = 20'h00000; - parameter [3:0] PF2_RBAR_CAP_VER = 4'h1; - parameter [2:0] PF2_RBAR_CONTROL_INDEX0 = 3'h0; - parameter [2:0] PF2_RBAR_CONTROL_INDEX1 = 3'h0; - parameter [2:0] PF2_RBAR_CONTROL_INDEX2 = 3'h0; - parameter [4:0] PF2_RBAR_CONTROL_SIZE0 = 5'h00; - parameter [4:0] PF2_RBAR_CONTROL_SIZE1 = 5'h00; - parameter [4:0] PF2_RBAR_CONTROL_SIZE2 = 5'h00; - parameter [2:0] PF2_RBAR_NUM = 3'h1; - parameter [7:0] PF2_REVISION_ID = 8'h00; - parameter [4:0] PF2_SRIOV_BAR0_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_SRIOV_BAR0_CONTROL = 3'h4; - parameter [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF2_SRIOV_BAR1_CONTROL = 3'h0; - parameter [4:0] PF2_SRIOV_BAR2_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_SRIOV_BAR2_CONTROL = 3'h4; - parameter [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_SRIOV_BAR3_CONTROL = 3'h0; - parameter [4:0] PF2_SRIOV_BAR4_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_SRIOV_BAR4_CONTROL = 3'h4; - parameter [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_SRIOV_BAR5_CONTROL = 3'h0; - parameter [15:0] PF2_SRIOV_CAP_INITIAL_VF = 16'h0000; - parameter [11:0] PF2_SRIOV_CAP_NEXTPTR = 12'h000; - parameter [15:0] PF2_SRIOV_CAP_TOTAL_VF = 16'h0000; - parameter [3:0] PF2_SRIOV_CAP_VER = 4'h1; - parameter [15:0] PF2_SRIOV_FIRST_VF_OFFSET = 16'h0000; - parameter [15:0] PF2_SRIOV_FUNC_DEP_LINK = 16'h0000; - parameter [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; - parameter [15:0] PF2_SRIOV_VF_DEVICE_ID = 16'h0000; - parameter [15:0] PF2_SUBSYSTEM_ID = 16'h0000; - parameter PF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter PF2_TPHR_CAP_ENABLE = "FALSE"; - parameter PF2_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] PF2_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] PF2_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] PF2_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] PF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] PF2_TPHR_CAP_VER = 4'h1; - parameter PF3_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; - parameter PF3_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; - parameter [11:0] PF3_AER_CAP_NEXTPTR = 12'h000; - parameter [11:0] PF3_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] PF3_ARI_CAP_NEXT_FUNC = 8'h00; - parameter [5:0] PF3_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF3_BAR0_CONTROL = 3'h4; - parameter [5:0] PF3_BAR1_APERTURE_SIZE = 6'h00; - parameter [2:0] PF3_BAR1_CONTROL = 3'h0; - parameter [4:0] PF3_BAR2_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_BAR2_CONTROL = 3'h4; - parameter [4:0] PF3_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_BAR3_CONTROL = 3'h0; - parameter [4:0] PF3_BAR4_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_BAR4_CONTROL = 3'h4; - parameter [4:0] PF3_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_BAR5_CONTROL = 3'h0; - parameter [7:0] PF3_BIST_REGISTER = 8'h00; - parameter [7:0] PF3_CAPABILITY_POINTER = 8'h50; - parameter [23:0] PF3_CLASS_CODE = 24'h000000; - parameter [15:0] PF3_DEVICE_ID = 16'h0000; - parameter [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; - parameter [11:0] PF3_DPA_CAP_NEXTPTR = 12'h000; - parameter [4:0] PF3_DPA_CAP_SUB_STATE_CONTROL = 5'h00; - parameter PF3_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; - parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; - parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; - parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; - parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; - parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; - parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; - parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; - parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; - parameter [3:0] PF3_DPA_CAP_VER = 4'h1; - parameter [11:0] PF3_DSN_CAP_NEXTPTR = 12'h10C; - parameter [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE = 5'h03; - parameter PF3_EXPANSION_ROM_ENABLE = "FALSE"; - parameter [7:0] PF3_INTERRUPT_LINE = 8'h00; - parameter [2:0] PF3_INTERRUPT_PIN = 3'h1; - parameter [7:0] PF3_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer PF3_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] PF3_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer PF3_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] PF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] PF3_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer PF3_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] PF3_MSI_CAP_NEXTPTR = 8'h00; - parameter PF3_MSI_CAP_PERVECMASKCAP = "FALSE"; - parameter [31:0] PF3_PB_CAP_DATA_REG_D0 = 32'h00000000; - parameter [31:0] PF3_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000; - parameter [31:0] PF3_PB_CAP_DATA_REG_D1 = 32'h00000000; - parameter [31:0] PF3_PB_CAP_DATA_REG_D3HOT = 32'h00000000; - parameter [11:0] PF3_PB_CAP_NEXTPTR = 12'h000; - parameter PF3_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; - parameter [3:0] PF3_PB_CAP_VER = 4'h1; - parameter [7:0] PF3_PM_CAP_ID = 8'h01; - parameter [7:0] PF3_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] PF3_PM_CAP_VER_ID = 3'h3; - parameter PF3_RBAR_CAP_ENABLE = "FALSE"; - parameter [11:0] PF3_RBAR_CAP_NEXTPTR = 12'h000; - parameter [19:0] PF3_RBAR_CAP_SIZE0 = 20'h00000; - parameter [19:0] PF3_RBAR_CAP_SIZE1 = 20'h00000; - parameter [19:0] PF3_RBAR_CAP_SIZE2 = 20'h00000; - parameter [3:0] PF3_RBAR_CAP_VER = 4'h1; - parameter [2:0] PF3_RBAR_CONTROL_INDEX0 = 3'h0; - parameter [2:0] PF3_RBAR_CONTROL_INDEX1 = 3'h0; - parameter [2:0] PF3_RBAR_CONTROL_INDEX2 = 3'h0; - parameter [4:0] PF3_RBAR_CONTROL_SIZE0 = 5'h00; - parameter [4:0] PF3_RBAR_CONTROL_SIZE1 = 5'h00; - parameter [4:0] PF3_RBAR_CONTROL_SIZE2 = 5'h00; - parameter [2:0] PF3_RBAR_NUM = 3'h1; - parameter [7:0] PF3_REVISION_ID = 8'h00; - parameter [4:0] PF3_SRIOV_BAR0_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_SRIOV_BAR0_CONTROL = 3'h4; - parameter [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF3_SRIOV_BAR1_CONTROL = 3'h0; - parameter [4:0] PF3_SRIOV_BAR2_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_SRIOV_BAR2_CONTROL = 3'h4; - parameter [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_SRIOV_BAR3_CONTROL = 3'h0; - parameter [4:0] PF3_SRIOV_BAR4_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_SRIOV_BAR4_CONTROL = 3'h4; - parameter [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_SRIOV_BAR5_CONTROL = 3'h0; - parameter [15:0] PF3_SRIOV_CAP_INITIAL_VF = 16'h0000; - parameter [11:0] PF3_SRIOV_CAP_NEXTPTR = 12'h000; - parameter [15:0] PF3_SRIOV_CAP_TOTAL_VF = 16'h0000; - parameter [3:0] PF3_SRIOV_CAP_VER = 4'h1; - parameter [15:0] PF3_SRIOV_FIRST_VF_OFFSET = 16'h0000; - parameter [15:0] PF3_SRIOV_FUNC_DEP_LINK = 16'h0000; - parameter [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; - parameter [15:0] PF3_SRIOV_VF_DEVICE_ID = 16'h0000; - parameter [15:0] PF3_SUBSYSTEM_ID = 16'h0000; - parameter PF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter PF3_TPHR_CAP_ENABLE = "FALSE"; - parameter PF3_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] PF3_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] PF3_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] PF3_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] PF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] PF3_TPHR_CAP_VER = 4'h1; - parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 = "FALSE"; - parameter PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 = "FALSE"; - parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE"; - parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE"; - parameter PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP = "TRUE"; - parameter PL_DISABLE_RETRAIN_ON_FRAMING_ERROR = "FALSE"; - parameter PL_DISABLE_SCRAMBLING = "FALSE"; - parameter PL_DISABLE_SYNC_HEADER_FRAMING_ERROR = "FALSE"; - parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE"; - parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE"; - parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE"; - parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02; - parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1; - parameter PL_EQ_BYPASS_PHASE23 = "FALSE"; - parameter [2:0] PL_EQ_DEFAULT_GEN3_RX_PRESET_HINT = 3'h3; - parameter [3:0] PL_EQ_DEFAULT_GEN3_TX_PRESET = 4'h4; - parameter PL_EQ_PHASE01_RX_ADAPT = "FALSE"; - parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE"; - parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h3F00; - parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4; - parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h8; - parameter integer PL_N_FTS_COMCLK_GEN1 = 255; - parameter integer PL_N_FTS_COMCLK_GEN2 = 255; - parameter integer PL_N_FTS_COMCLK_GEN3 = 255; - parameter integer PL_N_FTS_GEN1 = 255; - parameter integer PL_N_FTS_GEN2 = 255; - parameter integer PL_N_FTS_GEN3 = 255; - parameter PL_REPORT_ALL_PHY_ERRORS = "TRUE"; - parameter PL_SIM_FAST_LINK_TRAINING = "FALSE"; - parameter PL_UPSTREAM_FACING = "TRUE"; - parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h05DC; - parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h00000; - parameter PM_ENABLE_L23_ENTRY = "FALSE"; - parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE"; - parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000000; - parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h186A0; - parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0064; - parameter [31:0] SIM_JTAG_IDCODE = 32'h00000000; - parameter SIM_VERSION = "1.0"; - parameter integer SPARE_BIT0 = 0; - parameter integer SPARE_BIT1 = 0; - parameter integer SPARE_BIT2 = 0; - parameter integer SPARE_BIT3 = 0; - parameter integer SPARE_BIT4 = 0; - parameter integer SPARE_BIT5 = 0; - parameter integer SPARE_BIT6 = 0; - parameter integer SPARE_BIT7 = 0; - parameter integer SPARE_BIT8 = 0; - parameter [7:0] SPARE_BYTE0 = 8'h00; - parameter [7:0] SPARE_BYTE1 = 8'h00; - parameter [7:0] SPARE_BYTE2 = 8'h00; - parameter [7:0] SPARE_BYTE3 = 8'h00; - parameter [31:0] SPARE_WORD0 = 32'h00000000; - parameter [31:0] SPARE_WORD1 = 32'h00000000; - parameter [31:0] SPARE_WORD2 = 32'h00000000; - parameter [31:0] SPARE_WORD3 = 32'h00000000; - parameter SRIOV_CAP_ENABLE = "FALSE"; - parameter TL_COMPLETION_RAM_SIZE_16K = "TRUE"; - parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'hBEBC20; - parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h2FAF080; - parameter [11:0] TL_CREDITS_CD = 12'h3E0; - parameter [7:0] TL_CREDITS_CH = 8'h20; - parameter [11:0] TL_CREDITS_NPD = 12'h028; - parameter [7:0] TL_CREDITS_NPH = 8'h20; - parameter [11:0] TL_CREDITS_PD = 12'h198; - parameter [7:0] TL_CREDITS_PH = 8'h20; - parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "TRUE"; - parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; - parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; - parameter TL_LEGACY_MODE_ENABLE = "FALSE"; - parameter [1:0] TL_PF_ENABLE_REG = 2'h0; - parameter TL_TX_MUX_STRICT_PRIORITY = "TRUE"; - parameter TWO_LAYER_MODE_DLCMSM_ENABLE = "TRUE"; - parameter TWO_LAYER_MODE_ENABLE = "FALSE"; - parameter TWO_LAYER_MODE_WIDTH_256 = "TRUE"; - parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] VF0_CAPABILITY_POINTER = 8'h50; - parameter integer VF0_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF0_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF0_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF0_PM_CAP_ID = 8'h01; - parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF0_PM_CAP_VER_ID = 3'h3; - parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF0_TPHR_CAP_ENABLE = "FALSE"; - parameter VF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF0_TPHR_CAP_VER = 4'h1; - parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h000; - parameter integer VF1_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF1_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF1_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF1_PM_CAP_ID = 8'h01; - parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF1_PM_CAP_VER_ID = 3'h3; - parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF1_TPHR_CAP_ENABLE = "FALSE"; - parameter VF1_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF1_TPHR_CAP_VER = 4'h1; - parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h000; - parameter integer VF2_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF2_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF2_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF2_PM_CAP_ID = 8'h01; - parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF2_PM_CAP_VER_ID = 3'h3; - parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF2_TPHR_CAP_ENABLE = "FALSE"; - parameter VF2_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF2_TPHR_CAP_VER = 4'h1; - parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h000; - parameter integer VF3_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF3_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF3_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF3_PM_CAP_ID = 8'h01; - parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF3_PM_CAP_VER_ID = 3'h3; - parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF3_TPHR_CAP_ENABLE = "FALSE"; - parameter VF3_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF3_TPHR_CAP_VER = 4'h1; - parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h000; - parameter integer VF4_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF4_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF4_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF4_PM_CAP_ID = 8'h01; - parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF4_PM_CAP_VER_ID = 3'h3; - parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF4_TPHR_CAP_ENABLE = "FALSE"; - parameter VF4_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF4_TPHR_CAP_VER = 4'h1; - parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h000; - parameter integer VF5_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF5_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF5_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF5_PM_CAP_ID = 8'h01; - parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF5_PM_CAP_VER_ID = 3'h3; - parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF5_TPHR_CAP_ENABLE = "FALSE"; - parameter VF5_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF5_TPHR_CAP_VER = 4'h1; - parameter [11:0] VF6_ARI_CAP_NEXTPTR = 12'h000; - parameter integer VF6_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF6_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF6_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF6_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF6_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF6_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF6_PM_CAP_ID = 8'h01; - parameter [7:0] VF6_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF6_PM_CAP_VER_ID = 3'h3; - parameter VF6_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF6_TPHR_CAP_ENABLE = "FALSE"; - parameter VF6_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF6_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF6_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF6_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF6_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF6_TPHR_CAP_VER = 4'h1; - parameter [11:0] VF7_ARI_CAP_NEXTPTR = 12'h000; - parameter integer VF7_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF7_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF7_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF7_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF7_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF7_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF7_PM_CAP_ID = 8'h01; - parameter [7:0] VF7_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF7_PM_CAP_VER_ID = 3'h3; - parameter VF7_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF7_TPHR_CAP_ENABLE = "FALSE"; - parameter VF7_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF7_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF7_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF7_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF7_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF7_TPHR_CAP_VER = 4'h1; - output [2:0] CFGCURRENTSPEED; - output [3:0] CFGDPASUBSTATECHANGE; - output CFGERRCOROUT; - output CFGERRFATALOUT; - output CFGERRNONFATALOUT; - output [7:0] CFGEXTFUNCTIONNUMBER; - output CFGEXTREADRECEIVED; - output [9:0] CFGEXTREGISTERNUMBER; - output [3:0] CFGEXTWRITEBYTEENABLE; - output [31:0] CFGEXTWRITEDATA; - output CFGEXTWRITERECEIVED; - output [11:0] CFGFCCPLD; - output [7:0] CFGFCCPLH; - output [11:0] CFGFCNPD; - output [7:0] CFGFCNPH; - output [11:0] CFGFCPD; - output [7:0] CFGFCPH; - output [3:0] CFGFLRINPROCESS; - output [11:0] CFGFUNCTIONPOWERSTATE; - output [15:0] CFGFUNCTIONSTATUS; - output CFGHOTRESETOUT; - output [31:0] CFGINTERRUPTMSIDATA; - output [3:0] CFGINTERRUPTMSIENABLE; - output CFGINTERRUPTMSIFAIL; - output CFGINTERRUPTMSIMASKUPDATE; - output [11:0] CFGINTERRUPTMSIMMENABLE; - output CFGINTERRUPTMSISENT; - output [7:0] CFGINTERRUPTMSIVFENABLE; - output [3:0] CFGINTERRUPTMSIXENABLE; - output CFGINTERRUPTMSIXFAIL; - output [3:0] CFGINTERRUPTMSIXMASK; - output CFGINTERRUPTMSIXSENT; - output [7:0] CFGINTERRUPTMSIXVFENABLE; - output [7:0] CFGINTERRUPTMSIXVFMASK; - output CFGINTERRUPTSENT; - output [1:0] CFGLINKPOWERSTATE; - output CFGLOCALERROR; - output CFGLTRENABLE; - output [5:0] CFGLTSSMSTATE; - output [2:0] CFGMAXPAYLOAD; - output [2:0] CFGMAXREADREQ; - output [31:0] CFGMGMTREADDATA; - output CFGMGMTREADWRITEDONE; - output CFGMSGRECEIVED; - output [7:0] CFGMSGRECEIVEDDATA; - output [4:0] CFGMSGRECEIVEDTYPE; - output CFGMSGTRANSMITDONE; - output [3:0] CFGNEGOTIATEDWIDTH; - output [1:0] CFGOBFFENABLE; - output [15:0] CFGPERFUNCSTATUSDATA; - output CFGPERFUNCTIONUPDATEDONE; - output CFGPHYLINKDOWN; - output [1:0] CFGPHYLINKSTATUS; - output CFGPLSTATUSCHANGE; - output CFGPOWERSTATECHANGEINTERRUPT; - output [3:0] CFGRCBSTATUS; - output [3:0] CFGTPHFUNCTIONNUM; - output [3:0] CFGTPHREQUESTERENABLE; - output [11:0] CFGTPHSTMODE; - output [4:0] CFGTPHSTTADDRESS; - output CFGTPHSTTREADENABLE; - output [3:0] CFGTPHSTTWRITEBYTEVALID; - output [31:0] CFGTPHSTTWRITEDATA; - output CFGTPHSTTWRITEENABLE; - output [7:0] CFGVFFLRINPROCESS; - output [23:0] CFGVFPOWERSTATE; - output [15:0] CFGVFSTATUS; - output [7:0] CFGVFTPHREQUESTERENABLE; - output [23:0] CFGVFTPHSTMODE; - output CONFMCAPDESIGNSWITCH; - output CONFMCAPEOS; - output CONFMCAPINUSEBYPCIE; - output CONFREQREADY; - output [31:0] CONFRESPRDATA; - output CONFRESPVALID; - output [15:0] DBGDATAOUT; - output DBGMCAPCSB; - output [31:0] DBGMCAPDATA; - output DBGMCAPEOS; - output DBGMCAPERROR; - output DBGMCAPMODE; - output DBGMCAPRDATAVALID; - output DBGMCAPRDWRB; - output DBGMCAPRESET; - output DBGPLDATABLOCKRECEIVEDAFTEREDS; - output DBGPLGEN3FRAMINGERRORDETECTED; - output DBGPLGEN3SYNCHEADERERRORDETECTED; - output [7:0] DBGPLINFERREDRXELECTRICALIDLE; - output [15:0] DRPDO; - output DRPRDY; - output LL2LMMASTERTLPSENT0; - output LL2LMMASTERTLPSENT1; - output [3:0] LL2LMMASTERTLPSENTTLPID0; - output [3:0] LL2LMMASTERTLPSENTTLPID1; - output [255:0] LL2LMMAXISRXTDATA; - output [17:0] LL2LMMAXISRXTUSER; - output [7:0] LL2LMMAXISRXTVALID; - output [7:0] LL2LMSAXISTXTREADY; - output [255:0] MAXISCQTDATA; - output [7:0] MAXISCQTKEEP; - output MAXISCQTLAST; - output [84:0] MAXISCQTUSER; - output MAXISCQTVALID; - output [255:0] MAXISRCTDATA; - output [7:0] MAXISRCTKEEP; - output MAXISRCTLAST; - output [74:0] MAXISRCTUSER; - output MAXISRCTVALID; - output [9:0] MICOMPLETIONRAMREADADDRESSAL; - output [9:0] MICOMPLETIONRAMREADADDRESSAU; - output [9:0] MICOMPLETIONRAMREADADDRESSBL; - output [9:0] MICOMPLETIONRAMREADADDRESSBU; - output [3:0] MICOMPLETIONRAMREADENABLEL; - output [3:0] MICOMPLETIONRAMREADENABLEU; - output [9:0] MICOMPLETIONRAMWRITEADDRESSAL; - output [9:0] MICOMPLETIONRAMWRITEADDRESSAU; - output [9:0] MICOMPLETIONRAMWRITEADDRESSBL; - output [9:0] MICOMPLETIONRAMWRITEADDRESSBU; - output [71:0] MICOMPLETIONRAMWRITEDATAL; - output [71:0] MICOMPLETIONRAMWRITEDATAU; - output [3:0] MICOMPLETIONRAMWRITEENABLEL; - output [3:0] MICOMPLETIONRAMWRITEENABLEU; - output [8:0] MIREPLAYRAMADDRESS; - output [1:0] MIREPLAYRAMREADENABLE; - output [143:0] MIREPLAYRAMWRITEDATA; - output [1:0] MIREPLAYRAMWRITEENABLE; - output [8:0] MIREQUESTRAMREADADDRESSA; - output [8:0] MIREQUESTRAMREADADDRESSB; - output [3:0] MIREQUESTRAMREADENABLE; - output [8:0] MIREQUESTRAMWRITEADDRESSA; - output [8:0] MIREQUESTRAMWRITEADDRESSB; - output [143:0] MIREQUESTRAMWRITEDATA; - output [3:0] MIREQUESTRAMWRITEENABLE; - output [5:0] PCIECQNPREQCOUNT; - output PCIEPERST0B; - output PCIEPERST1B; - output [3:0] PCIERQSEQNUM; - output PCIERQSEQNUMVLD; - output [5:0] PCIERQTAG; - output [1:0] PCIERQTAGAV; - output PCIERQTAGVLD; - output [1:0] PCIETFCNPDAV; - output [1:0] PCIETFCNPHAV; - output [1:0] PIPERX0EQCONTROL; - output [5:0] PIPERX0EQLPLFFS; - output [3:0] PIPERX0EQLPTXPRESET; - output [2:0] PIPERX0EQPRESET; - output PIPERX0POLARITY; - output [1:0] PIPERX1EQCONTROL; - output [5:0] PIPERX1EQLPLFFS; - output [3:0] PIPERX1EQLPTXPRESET; - output [2:0] PIPERX1EQPRESET; - output PIPERX1POLARITY; - output [1:0] PIPERX2EQCONTROL; - output [5:0] PIPERX2EQLPLFFS; - output [3:0] PIPERX2EQLPTXPRESET; - output [2:0] PIPERX2EQPRESET; - output PIPERX2POLARITY; - output [1:0] PIPERX3EQCONTROL; - output [5:0] PIPERX3EQLPLFFS; - output [3:0] PIPERX3EQLPTXPRESET; - output [2:0] PIPERX3EQPRESET; - output PIPERX3POLARITY; - output [1:0] PIPERX4EQCONTROL; - output [5:0] PIPERX4EQLPLFFS; - output [3:0] PIPERX4EQLPTXPRESET; - output [2:0] PIPERX4EQPRESET; - output PIPERX4POLARITY; - output [1:0] PIPERX5EQCONTROL; - output [5:0] PIPERX5EQLPLFFS; - output [3:0] PIPERX5EQLPTXPRESET; - output [2:0] PIPERX5EQPRESET; - output PIPERX5POLARITY; - output [1:0] PIPERX6EQCONTROL; - output [5:0] PIPERX6EQLPLFFS; - output [3:0] PIPERX6EQLPTXPRESET; - output [2:0] PIPERX6EQPRESET; - output PIPERX6POLARITY; - output [1:0] PIPERX7EQCONTROL; - output [5:0] PIPERX7EQLPLFFS; - output [3:0] PIPERX7EQLPTXPRESET; - output [2:0] PIPERX7EQPRESET; - output PIPERX7POLARITY; - output [1:0] PIPETX0CHARISK; - output PIPETX0COMPLIANCE; - output [31:0] PIPETX0DATA; - output PIPETX0DATAVALID; - output PIPETX0DEEMPH; - output PIPETX0ELECIDLE; - output [1:0] PIPETX0EQCONTROL; - output [5:0] PIPETX0EQDEEMPH; - output [3:0] PIPETX0EQPRESET; - output [2:0] PIPETX0MARGIN; - output [1:0] PIPETX0POWERDOWN; - output [1:0] PIPETX0RATE; - output PIPETX0RCVRDET; - output PIPETX0RESET; - output PIPETX0STARTBLOCK; - output PIPETX0SWING; - output [1:0] PIPETX0SYNCHEADER; - output [1:0] PIPETX1CHARISK; - output PIPETX1COMPLIANCE; - output [31:0] PIPETX1DATA; - output PIPETX1DATAVALID; - output PIPETX1DEEMPH; - output PIPETX1ELECIDLE; - output [1:0] PIPETX1EQCONTROL; - output [5:0] PIPETX1EQDEEMPH; - output [3:0] PIPETX1EQPRESET; - output [2:0] PIPETX1MARGIN; - output [1:0] PIPETX1POWERDOWN; - output [1:0] PIPETX1RATE; - output PIPETX1RCVRDET; - output PIPETX1RESET; - output PIPETX1STARTBLOCK; - output PIPETX1SWING; - output [1:0] PIPETX1SYNCHEADER; - output [1:0] PIPETX2CHARISK; - output PIPETX2COMPLIANCE; - output [31:0] PIPETX2DATA; - output PIPETX2DATAVALID; - output PIPETX2DEEMPH; - output PIPETX2ELECIDLE; - output [1:0] PIPETX2EQCONTROL; - output [5:0] PIPETX2EQDEEMPH; - output [3:0] PIPETX2EQPRESET; - output [2:0] PIPETX2MARGIN; - output [1:0] PIPETX2POWERDOWN; - output [1:0] PIPETX2RATE; - output PIPETX2RCVRDET; - output PIPETX2RESET; - output PIPETX2STARTBLOCK; - output PIPETX2SWING; - output [1:0] PIPETX2SYNCHEADER; - output [1:0] PIPETX3CHARISK; - output PIPETX3COMPLIANCE; - output [31:0] PIPETX3DATA; - output PIPETX3DATAVALID; - output PIPETX3DEEMPH; - output PIPETX3ELECIDLE; - output [1:0] PIPETX3EQCONTROL; - output [5:0] PIPETX3EQDEEMPH; - output [3:0] PIPETX3EQPRESET; - output [2:0] PIPETX3MARGIN; - output [1:0] PIPETX3POWERDOWN; - output [1:0] PIPETX3RATE; - output PIPETX3RCVRDET; - output PIPETX3RESET; - output PIPETX3STARTBLOCK; - output PIPETX3SWING; - output [1:0] PIPETX3SYNCHEADER; - output [1:0] PIPETX4CHARISK; - output PIPETX4COMPLIANCE; - output [31:0] PIPETX4DATA; - output PIPETX4DATAVALID; - output PIPETX4DEEMPH; - output PIPETX4ELECIDLE; - output [1:0] PIPETX4EQCONTROL; - output [5:0] PIPETX4EQDEEMPH; - output [3:0] PIPETX4EQPRESET; - output [2:0] PIPETX4MARGIN; - output [1:0] PIPETX4POWERDOWN; - output [1:0] PIPETX4RATE; - output PIPETX4RCVRDET; - output PIPETX4RESET; - output PIPETX4STARTBLOCK; - output PIPETX4SWING; - output [1:0] PIPETX4SYNCHEADER; - output [1:0] PIPETX5CHARISK; - output PIPETX5COMPLIANCE; - output [31:0] PIPETX5DATA; - output PIPETX5DATAVALID; - output PIPETX5DEEMPH; - output PIPETX5ELECIDLE; - output [1:0] PIPETX5EQCONTROL; - output [5:0] PIPETX5EQDEEMPH; - output [3:0] PIPETX5EQPRESET; - output [2:0] PIPETX5MARGIN; - output [1:0] PIPETX5POWERDOWN; - output [1:0] PIPETX5RATE; - output PIPETX5RCVRDET; - output PIPETX5RESET; - output PIPETX5STARTBLOCK; - output PIPETX5SWING; - output [1:0] PIPETX5SYNCHEADER; - output [1:0] PIPETX6CHARISK; - output PIPETX6COMPLIANCE; - output [31:0] PIPETX6DATA; - output PIPETX6DATAVALID; - output PIPETX6DEEMPH; - output PIPETX6ELECIDLE; - output [1:0] PIPETX6EQCONTROL; - output [5:0] PIPETX6EQDEEMPH; - output [3:0] PIPETX6EQPRESET; - output [2:0] PIPETX6MARGIN; - output [1:0] PIPETX6POWERDOWN; - output [1:0] PIPETX6RATE; - output PIPETX6RCVRDET; - output PIPETX6RESET; - output PIPETX6STARTBLOCK; - output PIPETX6SWING; - output [1:0] PIPETX6SYNCHEADER; - output [1:0] PIPETX7CHARISK; - output PIPETX7COMPLIANCE; - output [31:0] PIPETX7DATA; - output PIPETX7DATAVALID; - output PIPETX7DEEMPH; - output PIPETX7ELECIDLE; - output [1:0] PIPETX7EQCONTROL; - output [5:0] PIPETX7EQDEEMPH; - output [3:0] PIPETX7EQPRESET; - output [2:0] PIPETX7MARGIN; - output [1:0] PIPETX7POWERDOWN; - output [1:0] PIPETX7RATE; - output PIPETX7RCVRDET; - output PIPETX7RESET; - output PIPETX7STARTBLOCK; - output PIPETX7SWING; - output [1:0] PIPETX7SYNCHEADER; - output PLEQINPROGRESS; - output [1:0] PLEQPHASE; - output [3:0] SAXISCCTREADY; - output [3:0] SAXISRQTREADY; - output [31:0] SPAREOUT; - input CFGCONFIGSPACEENABLE; - input [15:0] CFGDEVID; - input [7:0] CFGDSBUSNUMBER; - input [4:0] CFGDSDEVICENUMBER; - input [2:0] CFGDSFUNCTIONNUMBER; - input [63:0] CFGDSN; - input [7:0] CFGDSPORTNUMBER; - input CFGERRCORIN; - input CFGERRUNCORIN; - input [31:0] CFGEXTREADDATA; - input CFGEXTREADDATAVALID; - input [2:0] CFGFCSEL; - input [3:0] CFGFLRDONE; - input CFGHOTRESETIN; - input [3:0] CFGINTERRUPTINT; - input [2:0] CFGINTERRUPTMSIATTR; - input [3:0] CFGINTERRUPTMSIFUNCTIONNUMBER; - input [31:0] CFGINTERRUPTMSIINT; - input [31:0] CFGINTERRUPTMSIPENDINGSTATUS; - input CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE; - input [3:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM; - input [3:0] CFGINTERRUPTMSISELECT; - input CFGINTERRUPTMSITPHPRESENT; - input [8:0] CFGINTERRUPTMSITPHSTTAG; - input [1:0] CFGINTERRUPTMSITPHTYPE; - input [63:0] CFGINTERRUPTMSIXADDRESS; - input [31:0] CFGINTERRUPTMSIXDATA; - input CFGINTERRUPTMSIXINT; - input [3:0] CFGINTERRUPTPENDING; - input CFGLINKTRAININGENABLE; - input [18:0] CFGMGMTADDR; - input [3:0] CFGMGMTBYTEENABLE; - input CFGMGMTREAD; - input CFGMGMTTYPE1CFGREGACCESS; - input CFGMGMTWRITE; - input [31:0] CFGMGMTWRITEDATA; - input CFGMSGTRANSMIT; - input [31:0] CFGMSGTRANSMITDATA; - input [2:0] CFGMSGTRANSMITTYPE; - input [2:0] CFGPERFUNCSTATUSCONTROL; - input [3:0] CFGPERFUNCTIONNUMBER; - input CFGPERFUNCTIONOUTPUTREQUEST; - input CFGPOWERSTATECHANGEACK; - input CFGREQPMTRANSITIONL23READY; - input [7:0] CFGREVID; - input [15:0] CFGSUBSYSID; - input [15:0] CFGSUBSYSVENDID; - input [31:0] CFGTPHSTTREADDATA; - input CFGTPHSTTREADDATAVALID; - input [15:0] CFGVENDID; - input [7:0] CFGVFFLRDONE; - input CONFMCAPREQUESTBYCONF; - input [31:0] CONFREQDATA; - input [3:0] CONFREQREGNUM; - input [1:0] CONFREQTYPE; - input CONFREQVALID; - input CORECLK; - input CORECLKMICOMPLETIONRAML; - input CORECLKMICOMPLETIONRAMU; - input CORECLKMIREPLAYRAM; - input CORECLKMIREQUESTRAM; - input DBGCFGLOCALMGMTREGOVERRIDE; - input [3:0] DBGDATASEL; - input [9:0] DRPADDR; - input DRPCLK; - input [15:0] DRPDI; - input DRPEN; - input DRPWE; - input [13:0] LL2LMSAXISTXTUSER; - input LL2LMSAXISTXTVALID; - input [3:0] LL2LMTXTLPID0; - input [3:0] LL2LMTXTLPID1; - input [21:0] MAXISCQTREADY; - input [21:0] MAXISRCTREADY; - input MCAPCLK; - input MCAPPERST0B; - input MCAPPERST1B; - input MGMTRESETN; - input MGMTSTICKYRESETN; - input [143:0] MICOMPLETIONRAMREADDATA; - input [143:0] MIREPLAYRAMREADDATA; - input [143:0] MIREQUESTRAMREADDATA; - input PCIECQNPREQ; - input PIPECLK; - input [5:0] PIPEEQFS; - input [5:0] PIPEEQLF; - input PIPERESETN; - input [1:0] PIPERX0CHARISK; - input [31:0] PIPERX0DATA; - input PIPERX0DATAVALID; - input PIPERX0ELECIDLE; - input PIPERX0EQDONE; - input PIPERX0EQLPADAPTDONE; - input PIPERX0EQLPLFFSSEL; - input [17:0] PIPERX0EQLPNEWTXCOEFFORPRESET; - input PIPERX0PHYSTATUS; - input PIPERX0STARTBLOCK; - input [2:0] PIPERX0STATUS; - input [1:0] PIPERX0SYNCHEADER; - input PIPERX0VALID; - input [1:0] PIPERX1CHARISK; - input [31:0] PIPERX1DATA; - input PIPERX1DATAVALID; - input PIPERX1ELECIDLE; - input PIPERX1EQDONE; - input PIPERX1EQLPADAPTDONE; - input PIPERX1EQLPLFFSSEL; - input [17:0] PIPERX1EQLPNEWTXCOEFFORPRESET; - input PIPERX1PHYSTATUS; - input PIPERX1STARTBLOCK; - input [2:0] PIPERX1STATUS; - input [1:0] PIPERX1SYNCHEADER; - input PIPERX1VALID; - input [1:0] PIPERX2CHARISK; - input [31:0] PIPERX2DATA; - input PIPERX2DATAVALID; - input PIPERX2ELECIDLE; - input PIPERX2EQDONE; - input PIPERX2EQLPADAPTDONE; - input PIPERX2EQLPLFFSSEL; - input [17:0] PIPERX2EQLPNEWTXCOEFFORPRESET; - input PIPERX2PHYSTATUS; - input PIPERX2STARTBLOCK; - input [2:0] PIPERX2STATUS; - input [1:0] PIPERX2SYNCHEADER; - input PIPERX2VALID; - input [1:0] PIPERX3CHARISK; - input [31:0] PIPERX3DATA; - input PIPERX3DATAVALID; - input PIPERX3ELECIDLE; - input PIPERX3EQDONE; - input PIPERX3EQLPADAPTDONE; - input PIPERX3EQLPLFFSSEL; - input [17:0] PIPERX3EQLPNEWTXCOEFFORPRESET; - input PIPERX3PHYSTATUS; - input PIPERX3STARTBLOCK; - input [2:0] PIPERX3STATUS; - input [1:0] PIPERX3SYNCHEADER; - input PIPERX3VALID; - input [1:0] PIPERX4CHARISK; - input [31:0] PIPERX4DATA; - input PIPERX4DATAVALID; - input PIPERX4ELECIDLE; - input PIPERX4EQDONE; - input PIPERX4EQLPADAPTDONE; - input PIPERX4EQLPLFFSSEL; - input [17:0] PIPERX4EQLPNEWTXCOEFFORPRESET; - input PIPERX4PHYSTATUS; - input PIPERX4STARTBLOCK; - input [2:0] PIPERX4STATUS; - input [1:0] PIPERX4SYNCHEADER; - input PIPERX4VALID; - input [1:0] PIPERX5CHARISK; - input [31:0] PIPERX5DATA; - input PIPERX5DATAVALID; - input PIPERX5ELECIDLE; - input PIPERX5EQDONE; - input PIPERX5EQLPADAPTDONE; - input PIPERX5EQLPLFFSSEL; - input [17:0] PIPERX5EQLPNEWTXCOEFFORPRESET; - input PIPERX5PHYSTATUS; - input PIPERX5STARTBLOCK; - input [2:0] PIPERX5STATUS; - input [1:0] PIPERX5SYNCHEADER; - input PIPERX5VALID; - input [1:0] PIPERX6CHARISK; - input [31:0] PIPERX6DATA; - input PIPERX6DATAVALID; - input PIPERX6ELECIDLE; - input PIPERX6EQDONE; - input PIPERX6EQLPADAPTDONE; - input PIPERX6EQLPLFFSSEL; - input [17:0] PIPERX6EQLPNEWTXCOEFFORPRESET; - input PIPERX6PHYSTATUS; - input PIPERX6STARTBLOCK; - input [2:0] PIPERX6STATUS; - input [1:0] PIPERX6SYNCHEADER; - input PIPERX6VALID; - input [1:0] PIPERX7CHARISK; - input [31:0] PIPERX7DATA; - input PIPERX7DATAVALID; - input PIPERX7ELECIDLE; - input PIPERX7EQDONE; - input PIPERX7EQLPADAPTDONE; - input PIPERX7EQLPLFFSSEL; - input [17:0] PIPERX7EQLPNEWTXCOEFFORPRESET; - input PIPERX7PHYSTATUS; - input PIPERX7STARTBLOCK; - input [2:0] PIPERX7STATUS; - input [1:0] PIPERX7SYNCHEADER; - input PIPERX7VALID; - input [17:0] PIPETX0EQCOEFF; - input PIPETX0EQDONE; - input [17:0] PIPETX1EQCOEFF; - input PIPETX1EQDONE; - input [17:0] PIPETX2EQCOEFF; - input PIPETX2EQDONE; - input [17:0] PIPETX3EQCOEFF; - input PIPETX3EQDONE; - input [17:0] PIPETX4EQCOEFF; - input PIPETX4EQDONE; - input [17:0] PIPETX5EQCOEFF; - input PIPETX5EQDONE; - input [17:0] PIPETX6EQCOEFF; - input PIPETX6EQDONE; - input [17:0] PIPETX7EQCOEFF; - input PIPETX7EQDONE; - input PLEQRESETEIEOSCOUNT; - input PLGEN2UPSTREAMPREFERDEEMPH; - input RESETN; - input [255:0] SAXISCCTDATA; - input [7:0] SAXISCCTKEEP; - input SAXISCCTLAST; - input [32:0] SAXISCCTUSER; - input SAXISCCTVALID; - input [255:0] SAXISRQTDATA; - input [7:0] SAXISRQTKEEP; - input SAXISRQTLAST; - input [59:0] SAXISRQTUSER; - input SAXISRQTVALID; - input [31:0] SPAREIN; - input USERCLK; -endmodule - -module PCIE40E4 (...); - parameter ARI_CAP_ENABLE = "FALSE"; - parameter AUTO_FLR_RESPONSE = "FALSE"; - parameter [1:0] AXISTEN_IF_CC_ALIGNMENT_MODE = 2'h0; - parameter [23:0] AXISTEN_IF_COMPL_TIMEOUT_REG0 = 24'hBEBC20; - parameter [27:0] AXISTEN_IF_COMPL_TIMEOUT_REG1 = 28'h2FAF080; - parameter [1:0] AXISTEN_IF_CQ_ALIGNMENT_MODE = 2'h0; - parameter AXISTEN_IF_CQ_EN_POISONED_MEM_WR = "FALSE"; - parameter AXISTEN_IF_ENABLE_256_TAGS = "FALSE"; - parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE"; - parameter AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = "FALSE"; - parameter AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK = "TRUE"; - parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000; - parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE"; - parameter AXISTEN_IF_EXT_512 = "FALSE"; - parameter AXISTEN_IF_EXT_512_CC_STRADDLE = "FALSE"; - parameter AXISTEN_IF_EXT_512_CQ_STRADDLE = "FALSE"; - parameter AXISTEN_IF_EXT_512_RC_STRADDLE = "FALSE"; - parameter AXISTEN_IF_EXT_512_RQ_STRADDLE = "FALSE"; - parameter AXISTEN_IF_LEGACY_MODE_ENABLE = "FALSE"; - parameter AXISTEN_IF_MSIX_FROM_RAM_PIPELINE = "FALSE"; - parameter AXISTEN_IF_MSIX_RX_PARITY_EN = "TRUE"; - parameter AXISTEN_IF_MSIX_TO_RAM_PIPELINE = "FALSE"; - parameter [1:0] AXISTEN_IF_RC_ALIGNMENT_MODE = 2'h0; - parameter AXISTEN_IF_RC_STRADDLE = "FALSE"; - parameter [1:0] AXISTEN_IF_RQ_ALIGNMENT_MODE = 2'h0; - parameter AXISTEN_IF_RX_PARITY_EN = "TRUE"; - parameter AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT = "FALSE"; - parameter AXISTEN_IF_TX_PARITY_EN = "TRUE"; - parameter [1:0] AXISTEN_IF_WIDTH = 2'h2; - parameter CFG_BYPASS_MODE_ENABLE = "FALSE"; - parameter CRM_CORE_CLK_FREQ_500 = "TRUE"; - parameter [1:0] CRM_USER_CLK_FREQ = 2'h2; - parameter [15:0] DEBUG_AXI4ST_SPARE = 16'h0000; - parameter [7:0] DEBUG_AXIST_DISABLE_FEATURE_BIT = 8'h00; - parameter [3:0] DEBUG_CAR_SPARE = 4'h0; - parameter [15:0] DEBUG_CFG_SPARE = 16'h0000; - parameter [15:0] DEBUG_LL_SPARE = 16'h0000; - parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR = "FALSE"; - parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR = "FALSE"; - parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR = "FALSE"; - parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL = "FALSE"; - parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW = "FALSE"; - parameter DEBUG_PL_DISABLE_SCRAMBLING = "FALSE"; - parameter DEBUG_PL_SIM_RESET_LFSR = "FALSE"; - parameter [15:0] DEBUG_PL_SPARE = 16'h0000; - parameter DEBUG_TL_DISABLE_FC_TIMEOUT = "FALSE"; - parameter DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS = "FALSE"; - parameter [15:0] DEBUG_TL_SPARE = 16'h0000; - parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; - parameter DSN_CAP_ENABLE = "FALSE"; - parameter EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; - parameter HEADER_TYPE_OVERRIDE = "FALSE"; - parameter IS_SWITCH_PORT = "FALSE"; - parameter LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; - parameter [8:0] LL_ACK_TIMEOUT = 9'h000; - parameter LL_ACK_TIMEOUT_EN = "FALSE"; - parameter integer LL_ACK_TIMEOUT_FUNC = 0; - parameter LL_DISABLE_SCHED_TX_NAK = "FALSE"; - parameter LL_REPLAY_FROM_RAM_PIPELINE = "FALSE"; - parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000; - parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; - parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; - parameter LL_REPLAY_TO_RAM_PIPELINE = "FALSE"; - parameter LL_RX_TLP_PARITY_GEN = "TRUE"; - parameter LL_TX_TLP_PARITY_CHK = "TRUE"; - parameter [15:0] LL_USER_SPARE = 16'h0000; - parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h250; - parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE"; - parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE"; - parameter [11:0] MCAP_CAP_NEXTPTR = 12'h000; - parameter MCAP_CONFIGURE_OVERRIDE = "FALSE"; - parameter MCAP_ENABLE = "FALSE"; - parameter MCAP_EOS_DESIGN_SWITCH = "FALSE"; - parameter [31:0] MCAP_FPGA_BITSTREAM_VERSION = 32'h00000000; - parameter MCAP_GATE_IO_ENABLE_DESIGN_SWITCH = "FALSE"; - parameter MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH = "FALSE"; - parameter MCAP_INPUT_GATE_DESIGN_SWITCH = "FALSE"; - parameter MCAP_INTERRUPT_ON_MCAP_EOS = "FALSE"; - parameter MCAP_INTERRUPT_ON_MCAP_ERROR = "FALSE"; - parameter [15:0] MCAP_VSEC_ID = 16'h0000; - parameter [11:0] MCAP_VSEC_LEN = 12'h02C; - parameter [3:0] MCAP_VSEC_REV = 4'h0; - parameter PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE = "FALSE"; - parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000; - parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00; - parameter [3:0] PF0_ARI_CAP_VER = 4'h1; - parameter [5:0] PF0_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF0_BAR0_CONTROL = 3'h4; - parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF0_BAR1_CONTROL = 3'h0; - parameter [5:0] PF0_BAR2_APERTURE_SIZE = 6'h03; - parameter [2:0] PF0_BAR2_CONTROL = 3'h4; - parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_BAR3_CONTROL = 3'h0; - parameter [5:0] PF0_BAR4_APERTURE_SIZE = 6'h03; - parameter [2:0] PF0_BAR4_CONTROL = 3'h4; - parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_BAR5_CONTROL = 3'h0; - parameter [7:0] PF0_CAPABILITY_POINTER = 8'h80; - parameter [23:0] PF0_CLASS_CODE = 24'h000000; - parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE"; - parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; - parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; - parameter PF0_DEV_CAP2_ARI_FORWARD_ENABLE = "FALSE"; - parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE"; - parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE"; - parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0; - parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE"; - parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0; - parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0; - parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; - parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE"; - parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; - parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C; - parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03; - parameter PF0_EXPANSION_ROM_ENABLE = "FALSE"; - parameter [2:0] PF0_INTERRUPT_PIN = 3'h1; - parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4 = 7; - parameter [0:0] PF0_LINK_CONTROL_RCB = 1'h0; - parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; - parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000; - parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000; - parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000; - parameter [3:0] PF0_LTR_CAP_VER = 4'h1; - parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer PF0_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer PF0_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter [5:0] PF0_MSIX_VECTOR_COUNT = 6'h04; - parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00; - parameter PF0_MSI_CAP_PERVECMASKCAP = "FALSE"; - parameter [7:0] PF0_PCIE_CAP_NEXTPTR = 8'h00; - parameter [7:0] PF0_PM_CAP_ID = 8'h01; - parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00; - parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE"; - parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE"; - parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE"; - parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE"; - parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3; - parameter PF0_PM_CSR_NOSOFTRESET = "TRUE"; - parameter [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR = 12'h000; - parameter PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; - parameter [5:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4; - parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0; - parameter [5:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 6'h03; - parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4; - parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0; - parameter [5:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 6'h03; - parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4; - parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0; - parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000; - parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000; - parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000; - parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1; - parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000; - parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000; - parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; - parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000; - parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter PF0_TPHR_CAP_ENABLE = "FALSE"; - parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] PF0_TPHR_CAP_VER = 4'h1; - parameter PF0_VC_CAP_ENABLE = "FALSE"; - parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000; - parameter [3:0] PF0_VC_CAP_VER = 4'h1; - parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000; - parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00; - parameter [5:0] PF1_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF1_BAR0_CONTROL = 3'h4; - parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF1_BAR1_CONTROL = 3'h0; - parameter [5:0] PF1_BAR2_APERTURE_SIZE = 6'h03; - parameter [2:0] PF1_BAR2_CONTROL = 3'h4; - parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_BAR3_CONTROL = 3'h0; - parameter [5:0] PF1_BAR4_APERTURE_SIZE = 6'h03; - parameter [2:0] PF1_BAR4_CONTROL = 3'h4; - parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_BAR5_CONTROL = 3'h0; - parameter [7:0] PF1_CAPABILITY_POINTER = 8'h80; - parameter [23:0] PF1_CLASS_CODE = 24'h000000; - parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; - parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C; - parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03; - parameter PF1_EXPANSION_ROM_ENABLE = "FALSE"; - parameter [2:0] PF1_INTERRUPT_PIN = 3'h1; - parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer PF1_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer PF1_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00; - parameter PF1_MSI_CAP_PERVECMASKCAP = "FALSE"; - parameter [7:0] PF1_PCIE_CAP_NEXTPTR = 8'h00; - parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00; - parameter PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; - parameter [5:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4; - parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0; - parameter [5:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 6'h03; - parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4; - parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0; - parameter [5:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 6'h03; - parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4; - parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0; - parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000; - parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000; - parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000; - parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1; - parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000; - parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000; - parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; - parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000; - parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [11:0] PF2_AER_CAP_NEXTPTR = 12'h000; - parameter [11:0] PF2_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] PF2_ARI_CAP_NEXT_FUNC = 8'h00; - parameter [5:0] PF2_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF2_BAR0_CONTROL = 3'h4; - parameter [4:0] PF2_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF2_BAR1_CONTROL = 3'h0; - parameter [5:0] PF2_BAR2_APERTURE_SIZE = 6'h03; - parameter [2:0] PF2_BAR2_CONTROL = 3'h4; - parameter [4:0] PF2_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_BAR3_CONTROL = 3'h0; - parameter [5:0] PF2_BAR4_APERTURE_SIZE = 6'h03; - parameter [2:0] PF2_BAR4_CONTROL = 3'h4; - parameter [4:0] PF2_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_BAR5_CONTROL = 3'h0; - parameter [7:0] PF2_CAPABILITY_POINTER = 8'h80; - parameter [23:0] PF2_CLASS_CODE = 24'h000000; - parameter [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; - parameter [11:0] PF2_DSN_CAP_NEXTPTR = 12'h10C; - parameter [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE = 5'h03; - parameter PF2_EXPANSION_ROM_ENABLE = "FALSE"; - parameter [2:0] PF2_INTERRUPT_PIN = 3'h1; - parameter [7:0] PF2_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer PF2_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] PF2_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer PF2_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] PF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] PF2_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer PF2_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] PF2_MSI_CAP_NEXTPTR = 8'h00; - parameter PF2_MSI_CAP_PERVECMASKCAP = "FALSE"; - parameter [7:0] PF2_PCIE_CAP_NEXTPTR = 8'h00; - parameter [7:0] PF2_PM_CAP_NEXTPTR = 8'h00; - parameter PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; - parameter [5:0] PF2_SRIOV_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF2_SRIOV_BAR0_CONTROL = 3'h4; - parameter [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF2_SRIOV_BAR1_CONTROL = 3'h0; - parameter [5:0] PF2_SRIOV_BAR2_APERTURE_SIZE = 6'h03; - parameter [2:0] PF2_SRIOV_BAR2_CONTROL = 3'h4; - parameter [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_SRIOV_BAR3_CONTROL = 3'h0; - parameter [5:0] PF2_SRIOV_BAR4_APERTURE_SIZE = 6'h03; - parameter [2:0] PF2_SRIOV_BAR4_CONTROL = 3'h4; - parameter [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_SRIOV_BAR5_CONTROL = 3'h0; - parameter [15:0] PF2_SRIOV_CAP_INITIAL_VF = 16'h0000; - parameter [11:0] PF2_SRIOV_CAP_NEXTPTR = 12'h000; - parameter [15:0] PF2_SRIOV_CAP_TOTAL_VF = 16'h0000; - parameter [3:0] PF2_SRIOV_CAP_VER = 4'h1; - parameter [15:0] PF2_SRIOV_FIRST_VF_OFFSET = 16'h0000; - parameter [15:0] PF2_SRIOV_FUNC_DEP_LINK = 16'h0000; - parameter [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; - parameter [15:0] PF2_SRIOV_VF_DEVICE_ID = 16'h0000; - parameter [11:0] PF2_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] PF2_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [11:0] PF3_AER_CAP_NEXTPTR = 12'h000; - parameter [11:0] PF3_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] PF3_ARI_CAP_NEXT_FUNC = 8'h00; - parameter [5:0] PF3_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF3_BAR0_CONTROL = 3'h4; - parameter [4:0] PF3_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF3_BAR1_CONTROL = 3'h0; - parameter [5:0] PF3_BAR2_APERTURE_SIZE = 6'h03; - parameter [2:0] PF3_BAR2_CONTROL = 3'h4; - parameter [4:0] PF3_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_BAR3_CONTROL = 3'h0; - parameter [5:0] PF3_BAR4_APERTURE_SIZE = 6'h03; - parameter [2:0] PF3_BAR4_CONTROL = 3'h4; - parameter [4:0] PF3_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_BAR5_CONTROL = 3'h0; - parameter [7:0] PF3_CAPABILITY_POINTER = 8'h80; - parameter [23:0] PF3_CLASS_CODE = 24'h000000; - parameter [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; - parameter [11:0] PF3_DSN_CAP_NEXTPTR = 12'h10C; - parameter [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE = 5'h03; - parameter PF3_EXPANSION_ROM_ENABLE = "FALSE"; - parameter [2:0] PF3_INTERRUPT_PIN = 3'h1; - parameter [7:0] PF3_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer PF3_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] PF3_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer PF3_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] PF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] PF3_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer PF3_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] PF3_MSI_CAP_NEXTPTR = 8'h00; - parameter PF3_MSI_CAP_PERVECMASKCAP = "FALSE"; - parameter [7:0] PF3_PCIE_CAP_NEXTPTR = 8'h00; - parameter [7:0] PF3_PM_CAP_NEXTPTR = 8'h00; - parameter PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; - parameter [5:0] PF3_SRIOV_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF3_SRIOV_BAR0_CONTROL = 3'h4; - parameter [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF3_SRIOV_BAR1_CONTROL = 3'h0; - parameter [5:0] PF3_SRIOV_BAR2_APERTURE_SIZE = 6'h03; - parameter [2:0] PF3_SRIOV_BAR2_CONTROL = 3'h4; - parameter [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_SRIOV_BAR3_CONTROL = 3'h0; - parameter [5:0] PF3_SRIOV_BAR4_APERTURE_SIZE = 6'h03; - parameter [2:0] PF3_SRIOV_BAR4_CONTROL = 3'h4; - parameter [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_SRIOV_BAR5_CONTROL = 3'h0; - parameter [15:0] PF3_SRIOV_CAP_INITIAL_VF = 16'h0000; - parameter [11:0] PF3_SRIOV_CAP_NEXTPTR = 12'h000; - parameter [15:0] PF3_SRIOV_CAP_TOTAL_VF = 16'h0000; - parameter [3:0] PF3_SRIOV_CAP_VER = 4'h1; - parameter [15:0] PF3_SRIOV_FIRST_VF_OFFSET = 16'h0000; - parameter [15:0] PF3_SRIOV_FUNC_DEP_LINK = 16'h0000; - parameter [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; - parameter [15:0] PF3_SRIOV_VF_DEVICE_ID = 16'h0000; - parameter [11:0] PF3_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] PF3_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter PL_CFG_STATE_ROBUSTNESS_ENABLE = "TRUE"; - parameter PL_DEEMPH_SOURCE_SELECT = "TRUE"; - parameter PL_DESKEW_ON_SKIP_IN_GEN12 = "FALSE"; - parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 = "FALSE"; - parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4 = "FALSE"; - parameter PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 = "FALSE"; - parameter PL_DISABLE_DC_BALANCE = "FALSE"; - parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE"; - parameter PL_DISABLE_LANE_REVERSAL = "FALSE"; - parameter [1:0] PL_DISABLE_LFSR_UPDATE_ON_SKP = 2'h0; - parameter PL_DISABLE_RETRAIN_ON_EB_ERROR = "FALSE"; - parameter PL_DISABLE_RETRAIN_ON_FRAMING_ERROR = "FALSE"; - parameter [15:0] PL_DISABLE_RETRAIN_ON_SPECIFIC_FRAMING_ERROR = 16'h0000; - parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE"; - parameter [1:0] PL_EQ_ADAPT_DISABLE_COEFF_CHECK = 2'h0; - parameter [1:0] PL_EQ_ADAPT_DISABLE_PRESET_CHECK = 2'h0; - parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02; - parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1; - parameter [1:0] PL_EQ_BYPASS_PHASE23 = 2'h0; - parameter [5:0] PL_EQ_DEFAULT_RX_PRESET_HINT = 6'h33; - parameter [7:0] PL_EQ_DEFAULT_TX_PRESET = 8'h44; - parameter PL_EQ_DISABLE_MISMATCH_CHECK = "TRUE"; - parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE0 = 2'h0; - parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE1 = 2'h0; - parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE"; - parameter PL_EQ_TX_8G_EQ_TS2_ENABLE = "FALSE"; - parameter PL_EXIT_LOOPBACK_ON_EI_ENTRY = "TRUE"; - parameter PL_INFER_EI_DISABLE_LPBK_ACTIVE = "TRUE"; - parameter PL_INFER_EI_DISABLE_REC_RC = "FALSE"; - parameter PL_INFER_EI_DISABLE_REC_SPD = "FALSE"; - parameter [31:0] PL_LANE0_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE10_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE11_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE12_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE13_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE14_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE15_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE1_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE2_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE3_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE4_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE5_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE6_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE7_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE8_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE9_EQ_CONTROL = 32'h00003F00; - parameter [3:0] PL_LINK_CAP_MAX_LINK_SPEED = 4'h4; - parameter [4:0] PL_LINK_CAP_MAX_LINK_WIDTH = 5'h08; - parameter integer PL_N_FTS = 255; - parameter PL_QUIESCE_GUARANTEE_DISABLE = "FALSE"; - parameter PL_REDO_EQ_SOURCE_SELECT = "TRUE"; - parameter [7:0] PL_REPORT_ALL_PHY_ERRORS = 8'h00; - parameter [1:0] PL_RX_ADAPT_TIMER_CLWS_CLOBBER_TX_TS = 2'h0; - parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN3 = 4'h0; - parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN4 = 4'h0; - parameter [1:0] PL_RX_ADAPT_TIMER_RRL_CLOBBER_TX_TS = 2'h0; - parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN3 = 4'h0; - parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN4 = 4'h0; - parameter [1:0] PL_RX_L0S_EXIT_TO_RECOVERY = 2'h0; - parameter [1:0] PL_SIM_FAST_LINK_TRAINING = 2'h0; - parameter PL_SRIS_ENABLE = "FALSE"; - parameter [6:0] PL_SRIS_SKPOS_GEN_SPD_VEC = 7'h00; - parameter [6:0] PL_SRIS_SKPOS_REC_SPD_VEC = 7'h00; - parameter PL_UPSTREAM_FACING = "TRUE"; - parameter [15:0] PL_USER_SPARE = 16'h0000; - parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h1500; - parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h003E8; - parameter PM_ENABLE_L23_ENTRY = "FALSE"; - parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE"; - parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000100; - parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h00000; - parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0100; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter [31:0] SIM_JTAG_IDCODE = 32'h00000000; - parameter SIM_VERSION = "1.0"; - parameter SPARE_BIT0 = "FALSE"; - parameter integer SPARE_BIT1 = 0; - parameter integer SPARE_BIT2 = 0; - parameter SPARE_BIT3 = "FALSE"; - parameter integer SPARE_BIT4 = 0; - parameter integer SPARE_BIT5 = 0; - parameter integer SPARE_BIT6 = 0; - parameter integer SPARE_BIT7 = 0; - parameter integer SPARE_BIT8 = 0; - parameter [7:0] SPARE_BYTE0 = 8'h00; - parameter [7:0] SPARE_BYTE1 = 8'h00; - parameter [7:0] SPARE_BYTE2 = 8'h00; - parameter [7:0] SPARE_BYTE3 = 8'h00; - parameter [31:0] SPARE_WORD0 = 32'h00000000; - parameter [31:0] SPARE_WORD1 = 32'h00000000; - parameter [31:0] SPARE_WORD2 = 32'h00000000; - parameter [31:0] SPARE_WORD3 = 32'h00000000; - parameter [3:0] SRIOV_CAP_ENABLE = 4'h0; - parameter TL2CFG_IF_PARITY_CHK = "TRUE"; - parameter [1:0] TL_COMPLETION_RAM_NUM_TLPS = 2'h0; - parameter [1:0] TL_COMPLETION_RAM_SIZE = 2'h1; - parameter [11:0] TL_CREDITS_CD = 12'h000; - parameter [7:0] TL_CREDITS_CH = 8'h00; - parameter [11:0] TL_CREDITS_NPD = 12'h004; - parameter [7:0] TL_CREDITS_NPH = 8'h20; - parameter [11:0] TL_CREDITS_PD = 12'h0E0; - parameter [7:0] TL_CREDITS_PH = 8'h20; - parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TIME = 5'h02; - parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT = 5'h08; - parameter [1:0] TL_PF_ENABLE_REG = 2'h0; - parameter [0:0] TL_POSTED_RAM_SIZE = 1'h0; - parameter TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE = "FALSE"; - parameter TL_RX_COMPLETION_TO_RAM_READ_PIPELINE = "FALSE"; - parameter TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE = "FALSE"; - parameter TL_RX_POSTED_FROM_RAM_READ_PIPELINE = "FALSE"; - parameter TL_RX_POSTED_TO_RAM_READ_PIPELINE = "FALSE"; - parameter TL_RX_POSTED_TO_RAM_WRITE_PIPELINE = "FALSE"; - parameter TL_TX_MUX_STRICT_PRIORITY = "TRUE"; - parameter TL_TX_TLP_STRADDLE_ENABLE = "FALSE"; - parameter TL_TX_TLP_TERMINATE_PARITY = "FALSE"; - parameter [15:0] TL_USER_SPARE = 16'h0000; - parameter TPH_FROM_RAM_PIPELINE = "FALSE"; - parameter TPH_TO_RAM_PIPELINE = "FALSE"; - parameter [7:0] VF0_CAPABILITY_POINTER = 8'h80; - parameter [11:0] VFG0_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] VFG0_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer VFG0_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VFG0_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VFG0_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VFG0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VFG0_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter [7:0] VFG0_PCIE_CAP_NEXTPTR = 8'h00; - parameter [11:0] VFG0_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VFG0_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [11:0] VFG1_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] VFG1_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer VFG1_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VFG1_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VFG1_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VFG1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VFG1_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter [7:0] VFG1_PCIE_CAP_NEXTPTR = 8'h00; - parameter [11:0] VFG1_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VFG1_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [11:0] VFG2_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] VFG2_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer VFG2_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VFG2_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VFG2_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VFG2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VFG2_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter [7:0] VFG2_PCIE_CAP_NEXTPTR = 8'h00; - parameter [11:0] VFG2_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VFG2_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [11:0] VFG3_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] VFG3_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer VFG3_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VFG3_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VFG3_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VFG3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VFG3_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter [7:0] VFG3_PCIE_CAP_NEXTPTR = 8'h00; - parameter [11:0] VFG3_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VFG3_TPHR_CAP_ST_MODE_SEL = 3'h0; - output [7:0] AXIUSEROUT; - output [7:0] CFGBUSNUMBER; - output [1:0] CFGCURRENTSPEED; - output CFGERRCOROUT; - output CFGERRFATALOUT; - output CFGERRNONFATALOUT; - output [7:0] CFGEXTFUNCTIONNUMBER; - output CFGEXTREADRECEIVED; - output [9:0] CFGEXTREGISTERNUMBER; - output [3:0] CFGEXTWRITEBYTEENABLE; - output [31:0] CFGEXTWRITEDATA; - output CFGEXTWRITERECEIVED; - output [11:0] CFGFCCPLD; - output [7:0] CFGFCCPLH; - output [11:0] CFGFCNPD; - output [7:0] CFGFCNPH; - output [11:0] CFGFCPD; - output [7:0] CFGFCPH; - output [3:0] CFGFLRINPROCESS; - output [11:0] CFGFUNCTIONPOWERSTATE; - output [15:0] CFGFUNCTIONSTATUS; - output CFGHOTRESETOUT; - output [31:0] CFGINTERRUPTMSIDATA; - output [3:0] CFGINTERRUPTMSIENABLE; - output CFGINTERRUPTMSIFAIL; - output CFGINTERRUPTMSIMASKUPDATE; - output [11:0] CFGINTERRUPTMSIMMENABLE; - output CFGINTERRUPTMSISENT; - output [3:0] CFGINTERRUPTMSIXENABLE; - output [3:0] CFGINTERRUPTMSIXMASK; - output CFGINTERRUPTMSIXVECPENDINGSTATUS; - output CFGINTERRUPTSENT; - output [1:0] CFGLINKPOWERSTATE; - output [4:0] CFGLOCALERROROUT; - output CFGLOCALERRORVALID; - output CFGLTRENABLE; - output [5:0] CFGLTSSMSTATE; - output [1:0] CFGMAXPAYLOAD; - output [2:0] CFGMAXREADREQ; - output [31:0] CFGMGMTREADDATA; - output CFGMGMTREADWRITEDONE; - output CFGMSGRECEIVED; - output [7:0] CFGMSGRECEIVEDDATA; - output [4:0] CFGMSGRECEIVEDTYPE; - output CFGMSGTRANSMITDONE; - output [12:0] CFGMSIXRAMADDRESS; - output CFGMSIXRAMREADENABLE; - output [3:0] CFGMSIXRAMWRITEBYTEENABLE; - output [35:0] CFGMSIXRAMWRITEDATA; - output [2:0] CFGNEGOTIATEDWIDTH; - output [1:0] CFGOBFFENABLE; - output CFGPHYLINKDOWN; - output [1:0] CFGPHYLINKSTATUS; - output CFGPLSTATUSCHANGE; - output CFGPOWERSTATECHANGEINTERRUPT; - output [3:0] CFGRCBSTATUS; - output [1:0] CFGRXPMSTATE; - output [11:0] CFGTPHRAMADDRESS; - output CFGTPHRAMREADENABLE; - output [3:0] CFGTPHRAMWRITEBYTEENABLE; - output [35:0] CFGTPHRAMWRITEDATA; - output [3:0] CFGTPHREQUESTERENABLE; - output [11:0] CFGTPHSTMODE; - output [1:0] CFGTXPMSTATE; - output CONFMCAPDESIGNSWITCH; - output CONFMCAPEOS; - output CONFMCAPINUSEBYPCIE; - output CONFREQREADY; - output [31:0] CONFRESPRDATA; - output CONFRESPVALID; - output [31:0] DBGCTRL0OUT; - output [31:0] DBGCTRL1OUT; - output [255:0] DBGDATA0OUT; - output [255:0] DBGDATA1OUT; - output [15:0] DRPDO; - output DRPRDY; - output [255:0] MAXISCQTDATA; - output [7:0] MAXISCQTKEEP; - output MAXISCQTLAST; - output [87:0] MAXISCQTUSER; - output MAXISCQTVALID; - output [255:0] MAXISRCTDATA; - output [7:0] MAXISRCTKEEP; - output MAXISRCTLAST; - output [74:0] MAXISRCTUSER; - output MAXISRCTVALID; - output [8:0] MIREPLAYRAMADDRESS0; - output [8:0] MIREPLAYRAMADDRESS1; - output MIREPLAYRAMREADENABLE0; - output MIREPLAYRAMREADENABLE1; - output [127:0] MIREPLAYRAMWRITEDATA0; - output [127:0] MIREPLAYRAMWRITEDATA1; - output MIREPLAYRAMWRITEENABLE0; - output MIREPLAYRAMWRITEENABLE1; - output [8:0] MIRXCOMPLETIONRAMREADADDRESS0; - output [8:0] MIRXCOMPLETIONRAMREADADDRESS1; - output [1:0] MIRXCOMPLETIONRAMREADENABLE0; - output [1:0] MIRXCOMPLETIONRAMREADENABLE1; - output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS0; - output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS1; - output [143:0] MIRXCOMPLETIONRAMWRITEDATA0; - output [143:0] MIRXCOMPLETIONRAMWRITEDATA1; - output [1:0] MIRXCOMPLETIONRAMWRITEENABLE0; - output [1:0] MIRXCOMPLETIONRAMWRITEENABLE1; - output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS0; - output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS1; - output MIRXPOSTEDREQUESTRAMREADENABLE0; - output MIRXPOSTEDREQUESTRAMREADENABLE1; - output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS0; - output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS1; - output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA0; - output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA1; - output MIRXPOSTEDREQUESTRAMWRITEENABLE0; - output MIRXPOSTEDREQUESTRAMWRITEENABLE1; - output [5:0] PCIECQNPREQCOUNT; - output PCIEPERST0B; - output PCIEPERST1B; - output [5:0] PCIERQSEQNUM0; - output [5:0] PCIERQSEQNUM1; - output PCIERQSEQNUMVLD0; - output PCIERQSEQNUMVLD1; - output [7:0] PCIERQTAG0; - output [7:0] PCIERQTAG1; - output [3:0] PCIERQTAGAV; - output PCIERQTAGVLD0; - output PCIERQTAGVLD1; - output [3:0] PCIETFCNPDAV; - output [3:0] PCIETFCNPHAV; - output [1:0] PIPERX00EQCONTROL; - output PIPERX00POLARITY; - output [1:0] PIPERX01EQCONTROL; - output PIPERX01POLARITY; - output [1:0] PIPERX02EQCONTROL; - output PIPERX02POLARITY; - output [1:0] PIPERX03EQCONTROL; - output PIPERX03POLARITY; - output [1:0] PIPERX04EQCONTROL; - output PIPERX04POLARITY; - output [1:0] PIPERX05EQCONTROL; - output PIPERX05POLARITY; - output [1:0] PIPERX06EQCONTROL; - output PIPERX06POLARITY; - output [1:0] PIPERX07EQCONTROL; - output PIPERX07POLARITY; - output [1:0] PIPERX08EQCONTROL; - output PIPERX08POLARITY; - output [1:0] PIPERX09EQCONTROL; - output PIPERX09POLARITY; - output [1:0] PIPERX10EQCONTROL; - output PIPERX10POLARITY; - output [1:0] PIPERX11EQCONTROL; - output PIPERX11POLARITY; - output [1:0] PIPERX12EQCONTROL; - output PIPERX12POLARITY; - output [1:0] PIPERX13EQCONTROL; - output PIPERX13POLARITY; - output [1:0] PIPERX14EQCONTROL; - output PIPERX14POLARITY; - output [1:0] PIPERX15EQCONTROL; - output PIPERX15POLARITY; - output [5:0] PIPERXEQLPLFFS; - output [3:0] PIPERXEQLPTXPRESET; - output [1:0] PIPETX00CHARISK; - output PIPETX00COMPLIANCE; - output [31:0] PIPETX00DATA; - output PIPETX00DATAVALID; - output PIPETX00ELECIDLE; - output [1:0] PIPETX00EQCONTROL; - output [5:0] PIPETX00EQDEEMPH; - output [1:0] PIPETX00POWERDOWN; - output PIPETX00STARTBLOCK; - output [1:0] PIPETX00SYNCHEADER; - output [1:0] PIPETX01CHARISK; - output PIPETX01COMPLIANCE; - output [31:0] PIPETX01DATA; - output PIPETX01DATAVALID; - output PIPETX01ELECIDLE; - output [1:0] PIPETX01EQCONTROL; - output [5:0] PIPETX01EQDEEMPH; - output [1:0] PIPETX01POWERDOWN; - output PIPETX01STARTBLOCK; - output [1:0] PIPETX01SYNCHEADER; - output [1:0] PIPETX02CHARISK; - output PIPETX02COMPLIANCE; - output [31:0] PIPETX02DATA; - output PIPETX02DATAVALID; - output PIPETX02ELECIDLE; - output [1:0] PIPETX02EQCONTROL; - output [5:0] PIPETX02EQDEEMPH; - output [1:0] PIPETX02POWERDOWN; - output PIPETX02STARTBLOCK; - output [1:0] PIPETX02SYNCHEADER; - output [1:0] PIPETX03CHARISK; - output PIPETX03COMPLIANCE; - output [31:0] PIPETX03DATA; - output PIPETX03DATAVALID; - output PIPETX03ELECIDLE; - output [1:0] PIPETX03EQCONTROL; - output [5:0] PIPETX03EQDEEMPH; - output [1:0] PIPETX03POWERDOWN; - output PIPETX03STARTBLOCK; - output [1:0] PIPETX03SYNCHEADER; - output [1:0] PIPETX04CHARISK; - output PIPETX04COMPLIANCE; - output [31:0] PIPETX04DATA; - output PIPETX04DATAVALID; - output PIPETX04ELECIDLE; - output [1:0] PIPETX04EQCONTROL; - output [5:0] PIPETX04EQDEEMPH; - output [1:0] PIPETX04POWERDOWN; - output PIPETX04STARTBLOCK; - output [1:0] PIPETX04SYNCHEADER; - output [1:0] PIPETX05CHARISK; - output PIPETX05COMPLIANCE; - output [31:0] PIPETX05DATA; - output PIPETX05DATAVALID; - output PIPETX05ELECIDLE; - output [1:0] PIPETX05EQCONTROL; - output [5:0] PIPETX05EQDEEMPH; - output [1:0] PIPETX05POWERDOWN; - output PIPETX05STARTBLOCK; - output [1:0] PIPETX05SYNCHEADER; - output [1:0] PIPETX06CHARISK; - output PIPETX06COMPLIANCE; - output [31:0] PIPETX06DATA; - output PIPETX06DATAVALID; - output PIPETX06ELECIDLE; - output [1:0] PIPETX06EQCONTROL; - output [5:0] PIPETX06EQDEEMPH; - output [1:0] PIPETX06POWERDOWN; - output PIPETX06STARTBLOCK; - output [1:0] PIPETX06SYNCHEADER; - output [1:0] PIPETX07CHARISK; - output PIPETX07COMPLIANCE; - output [31:0] PIPETX07DATA; - output PIPETX07DATAVALID; - output PIPETX07ELECIDLE; - output [1:0] PIPETX07EQCONTROL; - output [5:0] PIPETX07EQDEEMPH; - output [1:0] PIPETX07POWERDOWN; - output PIPETX07STARTBLOCK; - output [1:0] PIPETX07SYNCHEADER; - output [1:0] PIPETX08CHARISK; - output PIPETX08COMPLIANCE; - output [31:0] PIPETX08DATA; - output PIPETX08DATAVALID; - output PIPETX08ELECIDLE; - output [1:0] PIPETX08EQCONTROL; - output [5:0] PIPETX08EQDEEMPH; - output [1:0] PIPETX08POWERDOWN; - output PIPETX08STARTBLOCK; - output [1:0] PIPETX08SYNCHEADER; - output [1:0] PIPETX09CHARISK; - output PIPETX09COMPLIANCE; - output [31:0] PIPETX09DATA; - output PIPETX09DATAVALID; - output PIPETX09ELECIDLE; - output [1:0] PIPETX09EQCONTROL; - output [5:0] PIPETX09EQDEEMPH; - output [1:0] PIPETX09POWERDOWN; - output PIPETX09STARTBLOCK; - output [1:0] PIPETX09SYNCHEADER; - output [1:0] PIPETX10CHARISK; - output PIPETX10COMPLIANCE; - output [31:0] PIPETX10DATA; - output PIPETX10DATAVALID; - output PIPETX10ELECIDLE; - output [1:0] PIPETX10EQCONTROL; - output [5:0] PIPETX10EQDEEMPH; - output [1:0] PIPETX10POWERDOWN; - output PIPETX10STARTBLOCK; - output [1:0] PIPETX10SYNCHEADER; - output [1:0] PIPETX11CHARISK; - output PIPETX11COMPLIANCE; - output [31:0] PIPETX11DATA; - output PIPETX11DATAVALID; - output PIPETX11ELECIDLE; - output [1:0] PIPETX11EQCONTROL; - output [5:0] PIPETX11EQDEEMPH; - output [1:0] PIPETX11POWERDOWN; - output PIPETX11STARTBLOCK; - output [1:0] PIPETX11SYNCHEADER; - output [1:0] PIPETX12CHARISK; - output PIPETX12COMPLIANCE; - output [31:0] PIPETX12DATA; - output PIPETX12DATAVALID; - output PIPETX12ELECIDLE; - output [1:0] PIPETX12EQCONTROL; - output [5:0] PIPETX12EQDEEMPH; - output [1:0] PIPETX12POWERDOWN; - output PIPETX12STARTBLOCK; - output [1:0] PIPETX12SYNCHEADER; - output [1:0] PIPETX13CHARISK; - output PIPETX13COMPLIANCE; - output [31:0] PIPETX13DATA; - output PIPETX13DATAVALID; - output PIPETX13ELECIDLE; - output [1:0] PIPETX13EQCONTROL; - output [5:0] PIPETX13EQDEEMPH; - output [1:0] PIPETX13POWERDOWN; - output PIPETX13STARTBLOCK; - output [1:0] PIPETX13SYNCHEADER; - output [1:0] PIPETX14CHARISK; - output PIPETX14COMPLIANCE; - output [31:0] PIPETX14DATA; - output PIPETX14DATAVALID; - output PIPETX14ELECIDLE; - output [1:0] PIPETX14EQCONTROL; - output [5:0] PIPETX14EQDEEMPH; - output [1:0] PIPETX14POWERDOWN; - output PIPETX14STARTBLOCK; - output [1:0] PIPETX14SYNCHEADER; - output [1:0] PIPETX15CHARISK; - output PIPETX15COMPLIANCE; - output [31:0] PIPETX15DATA; - output PIPETX15DATAVALID; - output PIPETX15ELECIDLE; - output [1:0] PIPETX15EQCONTROL; - output [5:0] PIPETX15EQDEEMPH; - output [1:0] PIPETX15POWERDOWN; - output PIPETX15STARTBLOCK; - output [1:0] PIPETX15SYNCHEADER; - output PIPETXDEEMPH; - output [2:0] PIPETXMARGIN; - output [1:0] PIPETXRATE; - output PIPETXRCVRDET; - output PIPETXRESET; - output PIPETXSWING; - output PLEQINPROGRESS; - output [1:0] PLEQPHASE; - output PLGEN34EQMISMATCH; - output [3:0] SAXISCCTREADY; - output [3:0] SAXISRQTREADY; - output [31:0] USERSPAREOUT; - input [7:0] AXIUSERIN; - input CFGCONFIGSPACEENABLE; - input [15:0] CFGDEVIDPF0; - input [15:0] CFGDEVIDPF1; - input [15:0] CFGDEVIDPF2; - input [15:0] CFGDEVIDPF3; - input [7:0] CFGDSBUSNUMBER; - input [4:0] CFGDSDEVICENUMBER; - input [2:0] CFGDSFUNCTIONNUMBER; - input [63:0] CFGDSN; - input [7:0] CFGDSPORTNUMBER; - input CFGERRCORIN; - input CFGERRUNCORIN; - input [31:0] CFGEXTREADDATA; - input CFGEXTREADDATAVALID; - input [2:0] CFGFCSEL; - input [3:0] CFGFLRDONE; - input CFGHOTRESETIN; - input [3:0] CFGINTERRUPTINT; - input [2:0] CFGINTERRUPTMSIATTR; - input [7:0] CFGINTERRUPTMSIFUNCTIONNUMBER; - input [31:0] CFGINTERRUPTMSIINT; - input [31:0] CFGINTERRUPTMSIPENDINGSTATUS; - input CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE; - input [1:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM; - input [1:0] CFGINTERRUPTMSISELECT; - input CFGINTERRUPTMSITPHPRESENT; - input [7:0] CFGINTERRUPTMSITPHSTTAG; - input [1:0] CFGINTERRUPTMSITPHTYPE; - input [63:0] CFGINTERRUPTMSIXADDRESS; - input [31:0] CFGINTERRUPTMSIXDATA; - input CFGINTERRUPTMSIXINT; - input [1:0] CFGINTERRUPTMSIXVECPENDING; - input [3:0] CFGINTERRUPTPENDING; - input CFGLINKTRAININGENABLE; - input [9:0] CFGMGMTADDR; - input [3:0] CFGMGMTBYTEENABLE; - input CFGMGMTDEBUGACCESS; - input [7:0] CFGMGMTFUNCTIONNUMBER; - input CFGMGMTREAD; - input CFGMGMTWRITE; - input [31:0] CFGMGMTWRITEDATA; - input CFGMSGTRANSMIT; - input [31:0] CFGMSGTRANSMITDATA; - input [2:0] CFGMSGTRANSMITTYPE; - input [35:0] CFGMSIXRAMREADDATA; - input CFGPMASPML1ENTRYREJECT; - input CFGPMASPMTXL0SENTRYDISABLE; - input CFGPOWERSTATECHANGEACK; - input CFGREQPMTRANSITIONL23READY; - input [7:0] CFGREVIDPF0; - input [7:0] CFGREVIDPF1; - input [7:0] CFGREVIDPF2; - input [7:0] CFGREVIDPF3; - input [15:0] CFGSUBSYSIDPF0; - input [15:0] CFGSUBSYSIDPF1; - input [15:0] CFGSUBSYSIDPF2; - input [15:0] CFGSUBSYSIDPF3; - input [15:0] CFGSUBSYSVENDID; - input [35:0] CFGTPHRAMREADDATA; - input [15:0] CFGVENDID; - input CFGVFFLRDONE; - input [7:0] CFGVFFLRFUNCNUM; - input CONFMCAPREQUESTBYCONF; - input [31:0] CONFREQDATA; - input [3:0] CONFREQREGNUM; - input [1:0] CONFREQTYPE; - input CONFREQVALID; - input CORECLK; - input CORECLKMIREPLAYRAM0; - input CORECLKMIREPLAYRAM1; - input CORECLKMIRXCOMPLETIONRAM0; - input CORECLKMIRXCOMPLETIONRAM1; - input CORECLKMIRXPOSTEDREQUESTRAM0; - input CORECLKMIRXPOSTEDREQUESTRAM1; - input [5:0] DBGSEL0; - input [5:0] DBGSEL1; - input [9:0] DRPADDR; - input DRPCLK; - input [15:0] DRPDI; - input DRPEN; - input DRPWE; - input [21:0] MAXISCQTREADY; - input [21:0] MAXISRCTREADY; - input MCAPCLK; - input MCAPPERST0B; - input MCAPPERST1B; - input MGMTRESETN; - input MGMTSTICKYRESETN; - input [5:0] MIREPLAYRAMERRCOR; - input [5:0] MIREPLAYRAMERRUNCOR; - input [127:0] MIREPLAYRAMREADDATA0; - input [127:0] MIREPLAYRAMREADDATA1; - input [11:0] MIRXCOMPLETIONRAMERRCOR; - input [11:0] MIRXCOMPLETIONRAMERRUNCOR; - input [143:0] MIRXCOMPLETIONRAMREADDATA0; - input [143:0] MIRXCOMPLETIONRAMREADDATA1; - input [5:0] MIRXPOSTEDREQUESTRAMERRCOR; - input [5:0] MIRXPOSTEDREQUESTRAMERRUNCOR; - input [143:0] MIRXPOSTEDREQUESTRAMREADDATA0; - input [143:0] MIRXPOSTEDREQUESTRAMREADDATA1; - input [1:0] PCIECOMPLDELIVERED; - input [7:0] PCIECOMPLDELIVEREDTAG0; - input [7:0] PCIECOMPLDELIVEREDTAG1; - input [1:0] PCIECQNPREQ; - input PCIECQNPUSERCREDITRCVD; - input PCIECQPIPELINEEMPTY; - input PCIEPOSTEDREQDELIVERED; - input PIPECLK; - input PIPECLKEN; - input [5:0] PIPEEQFS; - input [5:0] PIPEEQLF; - input PIPERESETN; - input [1:0] PIPERX00CHARISK; - input [31:0] PIPERX00DATA; - input PIPERX00DATAVALID; - input PIPERX00ELECIDLE; - input PIPERX00EQDONE; - input PIPERX00EQLPADAPTDONE; - input PIPERX00EQLPLFFSSEL; - input [17:0] PIPERX00EQLPNEWTXCOEFFORPRESET; - input PIPERX00PHYSTATUS; - input [1:0] PIPERX00STARTBLOCK; - input [2:0] PIPERX00STATUS; - input [1:0] PIPERX00SYNCHEADER; - input PIPERX00VALID; - input [1:0] PIPERX01CHARISK; - input [31:0] PIPERX01DATA; - input PIPERX01DATAVALID; - input PIPERX01ELECIDLE; - input PIPERX01EQDONE; - input PIPERX01EQLPADAPTDONE; - input PIPERX01EQLPLFFSSEL; - input [17:0] PIPERX01EQLPNEWTXCOEFFORPRESET; - input PIPERX01PHYSTATUS; - input [1:0] PIPERX01STARTBLOCK; - input [2:0] PIPERX01STATUS; - input [1:0] PIPERX01SYNCHEADER; - input PIPERX01VALID; - input [1:0] PIPERX02CHARISK; - input [31:0] PIPERX02DATA; - input PIPERX02DATAVALID; - input PIPERX02ELECIDLE; - input PIPERX02EQDONE; - input PIPERX02EQLPADAPTDONE; - input PIPERX02EQLPLFFSSEL; - input [17:0] PIPERX02EQLPNEWTXCOEFFORPRESET; - input PIPERX02PHYSTATUS; - input [1:0] PIPERX02STARTBLOCK; - input [2:0] PIPERX02STATUS; - input [1:0] PIPERX02SYNCHEADER; - input PIPERX02VALID; - input [1:0] PIPERX03CHARISK; - input [31:0] PIPERX03DATA; - input PIPERX03DATAVALID; - input PIPERX03ELECIDLE; - input PIPERX03EQDONE; - input PIPERX03EQLPADAPTDONE; - input PIPERX03EQLPLFFSSEL; - input [17:0] PIPERX03EQLPNEWTXCOEFFORPRESET; - input PIPERX03PHYSTATUS; - input [1:0] PIPERX03STARTBLOCK; - input [2:0] PIPERX03STATUS; - input [1:0] PIPERX03SYNCHEADER; - input PIPERX03VALID; - input [1:0] PIPERX04CHARISK; - input [31:0] PIPERX04DATA; - input PIPERX04DATAVALID; - input PIPERX04ELECIDLE; - input PIPERX04EQDONE; - input PIPERX04EQLPADAPTDONE; - input PIPERX04EQLPLFFSSEL; - input [17:0] PIPERX04EQLPNEWTXCOEFFORPRESET; - input PIPERX04PHYSTATUS; - input [1:0] PIPERX04STARTBLOCK; - input [2:0] PIPERX04STATUS; - input [1:0] PIPERX04SYNCHEADER; - input PIPERX04VALID; - input [1:0] PIPERX05CHARISK; - input [31:0] PIPERX05DATA; - input PIPERX05DATAVALID; - input PIPERX05ELECIDLE; - input PIPERX05EQDONE; - input PIPERX05EQLPADAPTDONE; - input PIPERX05EQLPLFFSSEL; - input [17:0] PIPERX05EQLPNEWTXCOEFFORPRESET; - input PIPERX05PHYSTATUS; - input [1:0] PIPERX05STARTBLOCK; - input [2:0] PIPERX05STATUS; - input [1:0] PIPERX05SYNCHEADER; - input PIPERX05VALID; - input [1:0] PIPERX06CHARISK; - input [31:0] PIPERX06DATA; - input PIPERX06DATAVALID; - input PIPERX06ELECIDLE; - input PIPERX06EQDONE; - input PIPERX06EQLPADAPTDONE; - input PIPERX06EQLPLFFSSEL; - input [17:0] PIPERX06EQLPNEWTXCOEFFORPRESET; - input PIPERX06PHYSTATUS; - input [1:0] PIPERX06STARTBLOCK; - input [2:0] PIPERX06STATUS; - input [1:0] PIPERX06SYNCHEADER; - input PIPERX06VALID; - input [1:0] PIPERX07CHARISK; - input [31:0] PIPERX07DATA; - input PIPERX07DATAVALID; - input PIPERX07ELECIDLE; - input PIPERX07EQDONE; - input PIPERX07EQLPADAPTDONE; - input PIPERX07EQLPLFFSSEL; - input [17:0] PIPERX07EQLPNEWTXCOEFFORPRESET; - input PIPERX07PHYSTATUS; - input [1:0] PIPERX07STARTBLOCK; - input [2:0] PIPERX07STATUS; - input [1:0] PIPERX07SYNCHEADER; - input PIPERX07VALID; - input [1:0] PIPERX08CHARISK; - input [31:0] PIPERX08DATA; - input PIPERX08DATAVALID; - input PIPERX08ELECIDLE; - input PIPERX08EQDONE; - input PIPERX08EQLPADAPTDONE; - input PIPERX08EQLPLFFSSEL; - input [17:0] PIPERX08EQLPNEWTXCOEFFORPRESET; - input PIPERX08PHYSTATUS; - input [1:0] PIPERX08STARTBLOCK; - input [2:0] PIPERX08STATUS; - input [1:0] PIPERX08SYNCHEADER; - input PIPERX08VALID; - input [1:0] PIPERX09CHARISK; - input [31:0] PIPERX09DATA; - input PIPERX09DATAVALID; - input PIPERX09ELECIDLE; - input PIPERX09EQDONE; - input PIPERX09EQLPADAPTDONE; - input PIPERX09EQLPLFFSSEL; - input [17:0] PIPERX09EQLPNEWTXCOEFFORPRESET; - input PIPERX09PHYSTATUS; - input [1:0] PIPERX09STARTBLOCK; - input [2:0] PIPERX09STATUS; - input [1:0] PIPERX09SYNCHEADER; - input PIPERX09VALID; - input [1:0] PIPERX10CHARISK; - input [31:0] PIPERX10DATA; - input PIPERX10DATAVALID; - input PIPERX10ELECIDLE; - input PIPERX10EQDONE; - input PIPERX10EQLPADAPTDONE; - input PIPERX10EQLPLFFSSEL; - input [17:0] PIPERX10EQLPNEWTXCOEFFORPRESET; - input PIPERX10PHYSTATUS; - input [1:0] PIPERX10STARTBLOCK; - input [2:0] PIPERX10STATUS; - input [1:0] PIPERX10SYNCHEADER; - input PIPERX10VALID; - input [1:0] PIPERX11CHARISK; - input [31:0] PIPERX11DATA; - input PIPERX11DATAVALID; - input PIPERX11ELECIDLE; - input PIPERX11EQDONE; - input PIPERX11EQLPADAPTDONE; - input PIPERX11EQLPLFFSSEL; - input [17:0] PIPERX11EQLPNEWTXCOEFFORPRESET; - input PIPERX11PHYSTATUS; - input [1:0] PIPERX11STARTBLOCK; - input [2:0] PIPERX11STATUS; - input [1:0] PIPERX11SYNCHEADER; - input PIPERX11VALID; - input [1:0] PIPERX12CHARISK; - input [31:0] PIPERX12DATA; - input PIPERX12DATAVALID; - input PIPERX12ELECIDLE; - input PIPERX12EQDONE; - input PIPERX12EQLPADAPTDONE; - input PIPERX12EQLPLFFSSEL; - input [17:0] PIPERX12EQLPNEWTXCOEFFORPRESET; - input PIPERX12PHYSTATUS; - input [1:0] PIPERX12STARTBLOCK; - input [2:0] PIPERX12STATUS; - input [1:0] PIPERX12SYNCHEADER; - input PIPERX12VALID; - input [1:0] PIPERX13CHARISK; - input [31:0] PIPERX13DATA; - input PIPERX13DATAVALID; - input PIPERX13ELECIDLE; - input PIPERX13EQDONE; - input PIPERX13EQLPADAPTDONE; - input PIPERX13EQLPLFFSSEL; - input [17:0] PIPERX13EQLPNEWTXCOEFFORPRESET; - input PIPERX13PHYSTATUS; - input [1:0] PIPERX13STARTBLOCK; - input [2:0] PIPERX13STATUS; - input [1:0] PIPERX13SYNCHEADER; - input PIPERX13VALID; - input [1:0] PIPERX14CHARISK; - input [31:0] PIPERX14DATA; - input PIPERX14DATAVALID; - input PIPERX14ELECIDLE; - input PIPERX14EQDONE; - input PIPERX14EQLPADAPTDONE; - input PIPERX14EQLPLFFSSEL; - input [17:0] PIPERX14EQLPNEWTXCOEFFORPRESET; - input PIPERX14PHYSTATUS; - input [1:0] PIPERX14STARTBLOCK; - input [2:0] PIPERX14STATUS; - input [1:0] PIPERX14SYNCHEADER; - input PIPERX14VALID; - input [1:0] PIPERX15CHARISK; - input [31:0] PIPERX15DATA; - input PIPERX15DATAVALID; - input PIPERX15ELECIDLE; - input PIPERX15EQDONE; - input PIPERX15EQLPADAPTDONE; - input PIPERX15EQLPLFFSSEL; - input [17:0] PIPERX15EQLPNEWTXCOEFFORPRESET; - input PIPERX15PHYSTATUS; - input [1:0] PIPERX15STARTBLOCK; - input [2:0] PIPERX15STATUS; - input [1:0] PIPERX15SYNCHEADER; - input PIPERX15VALID; - input [17:0] PIPETX00EQCOEFF; - input PIPETX00EQDONE; - input [17:0] PIPETX01EQCOEFF; - input PIPETX01EQDONE; - input [17:0] PIPETX02EQCOEFF; - input PIPETX02EQDONE; - input [17:0] PIPETX03EQCOEFF; - input PIPETX03EQDONE; - input [17:0] PIPETX04EQCOEFF; - input PIPETX04EQDONE; - input [17:0] PIPETX05EQCOEFF; - input PIPETX05EQDONE; - input [17:0] PIPETX06EQCOEFF; - input PIPETX06EQDONE; - input [17:0] PIPETX07EQCOEFF; - input PIPETX07EQDONE; - input [17:0] PIPETX08EQCOEFF; - input PIPETX08EQDONE; - input [17:0] PIPETX09EQCOEFF; - input PIPETX09EQDONE; - input [17:0] PIPETX10EQCOEFF; - input PIPETX10EQDONE; - input [17:0] PIPETX11EQCOEFF; - input PIPETX11EQDONE; - input [17:0] PIPETX12EQCOEFF; - input PIPETX12EQDONE; - input [17:0] PIPETX13EQCOEFF; - input PIPETX13EQDONE; - input [17:0] PIPETX14EQCOEFF; - input PIPETX14EQDONE; - input [17:0] PIPETX15EQCOEFF; - input PIPETX15EQDONE; - input PLEQRESETEIEOSCOUNT; - input PLGEN2UPSTREAMPREFERDEEMPH; - input PLGEN34REDOEQSPEED; - input PLGEN34REDOEQUALIZATION; - input RESETN; - input [255:0] SAXISCCTDATA; - input [7:0] SAXISCCTKEEP; - input SAXISCCTLAST; - input [32:0] SAXISCCTUSER; - input SAXISCCTVALID; - input [255:0] SAXISRQTDATA; - input [7:0] SAXISRQTKEEP; - input SAXISRQTLAST; - input [61:0] SAXISRQTUSER; - input SAXISRQTVALID; - input USERCLK; - input USERCLK2; - input USERCLKEN; - input [31:0] USERSPAREIN; -endmodule - -module PCIE4CE4 (...); - parameter ARI_CAP_ENABLE = "FALSE"; - parameter AUTO_FLR_RESPONSE = "FALSE"; - parameter [7:0] AXISTEN_IF_CCIX_RX_CREDIT_LIMIT = 8'h08; - parameter [7:0] AXISTEN_IF_CCIX_TX_CREDIT_LIMIT = 8'h08; - parameter AXISTEN_IF_CCIX_TX_REGISTERED_TREADY = "FALSE"; - parameter [1:0] AXISTEN_IF_CC_ALIGNMENT_MODE = 2'h0; - parameter [23:0] AXISTEN_IF_COMPL_TIMEOUT_REG0 = 24'hBEBC20; - parameter [27:0] AXISTEN_IF_COMPL_TIMEOUT_REG1 = 28'h2FAF080; - parameter [1:0] AXISTEN_IF_CQ_ALIGNMENT_MODE = 2'h0; - parameter AXISTEN_IF_CQ_EN_POISONED_MEM_WR = "FALSE"; - parameter AXISTEN_IF_ENABLE_256_TAGS = "FALSE"; - parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE"; - parameter AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = "FALSE"; - parameter AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK = "TRUE"; - parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000; - parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE"; - parameter AXISTEN_IF_EXT_512 = "FALSE"; - parameter AXISTEN_IF_EXT_512_CC_STRADDLE = "FALSE"; - parameter AXISTEN_IF_EXT_512_CQ_STRADDLE = "FALSE"; - parameter AXISTEN_IF_EXT_512_RC_STRADDLE = "FALSE"; - parameter AXISTEN_IF_EXT_512_RQ_STRADDLE = "FALSE"; - parameter AXISTEN_IF_LEGACY_MODE_ENABLE = "FALSE"; - parameter AXISTEN_IF_MSIX_FROM_RAM_PIPELINE = "FALSE"; - parameter AXISTEN_IF_MSIX_RX_PARITY_EN = "TRUE"; - parameter AXISTEN_IF_MSIX_TO_RAM_PIPELINE = "FALSE"; - parameter [1:0] AXISTEN_IF_RC_ALIGNMENT_MODE = 2'h0; - parameter AXISTEN_IF_RC_STRADDLE = "FALSE"; - parameter [1:0] AXISTEN_IF_RQ_ALIGNMENT_MODE = 2'h0; - parameter AXISTEN_IF_RX_PARITY_EN = "TRUE"; - parameter AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT = "FALSE"; - parameter AXISTEN_IF_TX_PARITY_EN = "TRUE"; - parameter [1:0] AXISTEN_IF_WIDTH = 2'h2; - parameter CCIX_DIRECT_ATTACH_MODE = "FALSE"; - parameter CCIX_ENABLE = "FALSE"; - parameter [15:0] CCIX_VENDOR_ID = 16'h0000; - parameter CFG_BYPASS_MODE_ENABLE = "FALSE"; - parameter CRM_CORE_CLK_FREQ_500 = "TRUE"; - parameter [1:0] CRM_USER_CLK_FREQ = 2'h2; - parameter [15:0] DEBUG_AXI4ST_SPARE = 16'h0000; - parameter [7:0] DEBUG_AXIST_DISABLE_FEATURE_BIT = 8'h00; - parameter [3:0] DEBUG_CAR_SPARE = 4'h0; - parameter [15:0] DEBUG_CFG_SPARE = 16'h0000; - parameter [15:0] DEBUG_LL_SPARE = 16'h0000; - parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR = "FALSE"; - parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR = "FALSE"; - parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR = "FALSE"; - parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL = "FALSE"; - parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW = "FALSE"; - parameter DEBUG_PL_DISABLE_SCRAMBLING = "FALSE"; - parameter DEBUG_PL_SIM_RESET_LFSR = "FALSE"; - parameter [15:0] DEBUG_PL_SPARE = 16'h0000; - parameter DEBUG_TL_DISABLE_FC_TIMEOUT = "FALSE"; - parameter DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS = "FALSE"; - parameter [15:0] DEBUG_TL_SPARE = 16'h0000; - parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; - parameter DSN_CAP_ENABLE = "FALSE"; - parameter EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; - parameter HEADER_TYPE_OVERRIDE = "FALSE"; - parameter IS_SWITCH_PORT = "FALSE"; - parameter LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; - parameter [8:0] LL_ACK_TIMEOUT = 9'h000; - parameter LL_ACK_TIMEOUT_EN = "FALSE"; - parameter integer LL_ACK_TIMEOUT_FUNC = 0; - parameter LL_DISABLE_SCHED_TX_NAK = "FALSE"; - parameter LL_REPLAY_FROM_RAM_PIPELINE = "FALSE"; - parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000; - parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; - parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; - parameter LL_REPLAY_TO_RAM_PIPELINE = "FALSE"; - parameter LL_RX_TLP_PARITY_GEN = "TRUE"; - parameter LL_TX_TLP_PARITY_CHK = "TRUE"; - parameter [15:0] LL_USER_SPARE = 16'h0000; - parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h250; - parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE"; - parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE"; - parameter [11:0] MCAP_CAP_NEXTPTR = 12'h000; - parameter MCAP_CONFIGURE_OVERRIDE = "FALSE"; - parameter MCAP_ENABLE = "FALSE"; - parameter MCAP_EOS_DESIGN_SWITCH = "FALSE"; - parameter [31:0] MCAP_FPGA_BITSTREAM_VERSION = 32'h00000000; - parameter MCAP_GATE_IO_ENABLE_DESIGN_SWITCH = "FALSE"; - parameter MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH = "FALSE"; - parameter MCAP_INPUT_GATE_DESIGN_SWITCH = "FALSE"; - parameter MCAP_INTERRUPT_ON_MCAP_EOS = "FALSE"; - parameter MCAP_INTERRUPT_ON_MCAP_ERROR = "FALSE"; - parameter [15:0] MCAP_VSEC_ID = 16'h0000; - parameter [11:0] MCAP_VSEC_LEN = 12'h02C; - parameter [3:0] MCAP_VSEC_REV = 4'h0; - parameter PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE = "FALSE"; - parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000; - parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00; - parameter [3:0] PF0_ARI_CAP_VER = 4'h1; - parameter [4:0] PF0_ATS_CAP_INV_QUEUE_DEPTH = 5'h00; - parameter [11:0] PF0_ATS_CAP_NEXTPTR = 12'h000; - parameter PF0_ATS_CAP_ON = "FALSE"; - parameter [5:0] PF0_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF0_BAR0_CONTROL = 3'h4; - parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF0_BAR1_CONTROL = 3'h0; - parameter [5:0] PF0_BAR2_APERTURE_SIZE = 6'h03; - parameter [2:0] PF0_BAR2_CONTROL = 3'h4; - parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_BAR3_CONTROL = 3'h0; - parameter [5:0] PF0_BAR4_APERTURE_SIZE = 6'h03; - parameter [2:0] PF0_BAR4_CONTROL = 3'h4; - parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_BAR5_CONTROL = 3'h0; - parameter [7:0] PF0_CAPABILITY_POINTER = 8'h80; - parameter [23:0] PF0_CLASS_CODE = 24'h000000; - parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE"; - parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; - parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; - parameter PF0_DEV_CAP2_ARI_FORWARD_ENABLE = "FALSE"; - parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE"; - parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE"; - parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0; - parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE"; - parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0; - parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0; - parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; - parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE"; - parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; - parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C; - parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03; - parameter PF0_EXPANSION_ROM_ENABLE = "FALSE"; - parameter [2:0] PF0_INTERRUPT_PIN = 3'h1; - parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4 = 7; - parameter [0:0] PF0_LINK_CONTROL_RCB = 1'h0; - parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; - parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000; - parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000; - parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000; - parameter [3:0] PF0_LTR_CAP_VER = 4'h1; - parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer PF0_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer PF0_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter [5:0] PF0_MSIX_VECTOR_COUNT = 6'h04; - parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00; - parameter PF0_MSI_CAP_PERVECMASKCAP = "FALSE"; - parameter [7:0] PF0_PCIE_CAP_NEXTPTR = 8'h00; - parameter [7:0] PF0_PM_CAP_ID = 8'h01; - parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00; - parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE"; - parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE"; - parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE"; - parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE"; - parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3; - parameter PF0_PM_CSR_NOSOFTRESET = "TRUE"; - parameter [11:0] PF0_PRI_CAP_NEXTPTR = 12'h000; - parameter PF0_PRI_CAP_ON = "FALSE"; - parameter [31:0] PF0_PRI_OST_PR_CAPACITY = 32'h00000000; - parameter [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR = 12'h000; - parameter PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; - parameter [5:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4; - parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0; - parameter [5:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 6'h03; - parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4; - parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0; - parameter [5:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 6'h03; - parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4; - parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0; - parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000; - parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000; - parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000; - parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1; - parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000; - parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000; - parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; - parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000; - parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter PF0_TPHR_CAP_ENABLE = "FALSE"; - parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] PF0_TPHR_CAP_VER = 4'h1; - parameter [3:0] PF0_VC_ARB_CAPABILITY = 4'h0; - parameter [7:0] PF0_VC_ARB_TBL_OFFSET = 8'h00; - parameter PF0_VC_CAP_ENABLE = "FALSE"; - parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000; - parameter [3:0] PF0_VC_CAP_VER = 4'h1; - parameter PF0_VC_EXTENDED_COUNT = "FALSE"; - parameter PF0_VC_LOW_PRIORITY_EXTENDED_COUNT = "FALSE"; - parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000; - parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00; - parameter [4:0] PF1_ATS_CAP_INV_QUEUE_DEPTH = 5'h00; - parameter [11:0] PF1_ATS_CAP_NEXTPTR = 12'h000; - parameter PF1_ATS_CAP_ON = "FALSE"; - parameter [5:0] PF1_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF1_BAR0_CONTROL = 3'h4; - parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF1_BAR1_CONTROL = 3'h0; - parameter [5:0] PF1_BAR2_APERTURE_SIZE = 6'h03; - parameter [2:0] PF1_BAR2_CONTROL = 3'h4; - parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_BAR3_CONTROL = 3'h0; - parameter [5:0] PF1_BAR4_APERTURE_SIZE = 6'h03; - parameter [2:0] PF1_BAR4_CONTROL = 3'h4; - parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_BAR5_CONTROL = 3'h0; - parameter [7:0] PF1_CAPABILITY_POINTER = 8'h80; - parameter [23:0] PF1_CLASS_CODE = 24'h000000; - parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; - parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C; - parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03; - parameter PF1_EXPANSION_ROM_ENABLE = "FALSE"; - parameter [2:0] PF1_INTERRUPT_PIN = 3'h1; - parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer PF1_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer PF1_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00; - parameter PF1_MSI_CAP_PERVECMASKCAP = "FALSE"; - parameter [7:0] PF1_PCIE_CAP_NEXTPTR = 8'h00; - parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00; - parameter [11:0] PF1_PRI_CAP_NEXTPTR = 12'h000; - parameter PF1_PRI_CAP_ON = "FALSE"; - parameter [31:0] PF1_PRI_OST_PR_CAPACITY = 32'h00000000; - parameter PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; - parameter [5:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4; - parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0; - parameter [5:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 6'h03; - parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4; - parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0; - parameter [5:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 6'h03; - parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4; - parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0; - parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000; - parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000; - parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000; - parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1; - parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000; - parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000; - parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; - parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000; - parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [11:0] PF2_AER_CAP_NEXTPTR = 12'h000; - parameter [11:0] PF2_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] PF2_ARI_CAP_NEXT_FUNC = 8'h00; - parameter [4:0] PF2_ATS_CAP_INV_QUEUE_DEPTH = 5'h00; - parameter [11:0] PF2_ATS_CAP_NEXTPTR = 12'h000; - parameter PF2_ATS_CAP_ON = "FALSE"; - parameter [5:0] PF2_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF2_BAR0_CONTROL = 3'h4; - parameter [4:0] PF2_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF2_BAR1_CONTROL = 3'h0; - parameter [5:0] PF2_BAR2_APERTURE_SIZE = 6'h03; - parameter [2:0] PF2_BAR2_CONTROL = 3'h4; - parameter [4:0] PF2_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_BAR3_CONTROL = 3'h0; - parameter [5:0] PF2_BAR4_APERTURE_SIZE = 6'h03; - parameter [2:0] PF2_BAR4_CONTROL = 3'h4; - parameter [4:0] PF2_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_BAR5_CONTROL = 3'h0; - parameter [7:0] PF2_CAPABILITY_POINTER = 8'h80; - parameter [23:0] PF2_CLASS_CODE = 24'h000000; - parameter [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; - parameter [11:0] PF2_DSN_CAP_NEXTPTR = 12'h10C; - parameter [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE = 5'h03; - parameter PF2_EXPANSION_ROM_ENABLE = "FALSE"; - parameter [2:0] PF2_INTERRUPT_PIN = 3'h1; - parameter [7:0] PF2_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer PF2_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] PF2_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer PF2_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] PF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] PF2_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer PF2_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] PF2_MSI_CAP_NEXTPTR = 8'h00; - parameter PF2_MSI_CAP_PERVECMASKCAP = "FALSE"; - parameter [7:0] PF2_PCIE_CAP_NEXTPTR = 8'h00; - parameter [7:0] PF2_PM_CAP_NEXTPTR = 8'h00; - parameter [11:0] PF2_PRI_CAP_NEXTPTR = 12'h000; - parameter PF2_PRI_CAP_ON = "FALSE"; - parameter [31:0] PF2_PRI_OST_PR_CAPACITY = 32'h00000000; - parameter PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; - parameter [5:0] PF2_SRIOV_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF2_SRIOV_BAR0_CONTROL = 3'h4; - parameter [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF2_SRIOV_BAR1_CONTROL = 3'h0; - parameter [5:0] PF2_SRIOV_BAR2_APERTURE_SIZE = 6'h03; - parameter [2:0] PF2_SRIOV_BAR2_CONTROL = 3'h4; - parameter [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_SRIOV_BAR3_CONTROL = 3'h0; - parameter [5:0] PF2_SRIOV_BAR4_APERTURE_SIZE = 6'h03; - parameter [2:0] PF2_SRIOV_BAR4_CONTROL = 3'h4; - parameter [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_SRIOV_BAR5_CONTROL = 3'h0; - parameter [15:0] PF2_SRIOV_CAP_INITIAL_VF = 16'h0000; - parameter [11:0] PF2_SRIOV_CAP_NEXTPTR = 12'h000; - parameter [15:0] PF2_SRIOV_CAP_TOTAL_VF = 16'h0000; - parameter [3:0] PF2_SRIOV_CAP_VER = 4'h1; - parameter [15:0] PF2_SRIOV_FIRST_VF_OFFSET = 16'h0000; - parameter [15:0] PF2_SRIOV_FUNC_DEP_LINK = 16'h0000; - parameter [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; - parameter [15:0] PF2_SRIOV_VF_DEVICE_ID = 16'h0000; - parameter [11:0] PF2_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] PF2_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [11:0] PF3_AER_CAP_NEXTPTR = 12'h000; - parameter [11:0] PF3_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] PF3_ARI_CAP_NEXT_FUNC = 8'h00; - parameter [4:0] PF3_ATS_CAP_INV_QUEUE_DEPTH = 5'h00; - parameter [11:0] PF3_ATS_CAP_NEXTPTR = 12'h000; - parameter PF3_ATS_CAP_ON = "FALSE"; - parameter [5:0] PF3_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF3_BAR0_CONTROL = 3'h4; - parameter [4:0] PF3_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF3_BAR1_CONTROL = 3'h0; - parameter [5:0] PF3_BAR2_APERTURE_SIZE = 6'h03; - parameter [2:0] PF3_BAR2_CONTROL = 3'h4; - parameter [4:0] PF3_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_BAR3_CONTROL = 3'h0; - parameter [5:0] PF3_BAR4_APERTURE_SIZE = 6'h03; - parameter [2:0] PF3_BAR4_CONTROL = 3'h4; - parameter [4:0] PF3_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_BAR5_CONTROL = 3'h0; - parameter [7:0] PF3_CAPABILITY_POINTER = 8'h80; - parameter [23:0] PF3_CLASS_CODE = 24'h000000; - parameter [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; - parameter [11:0] PF3_DSN_CAP_NEXTPTR = 12'h10C; - parameter [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE = 5'h03; - parameter PF3_EXPANSION_ROM_ENABLE = "FALSE"; - parameter [2:0] PF3_INTERRUPT_PIN = 3'h1; - parameter [7:0] PF3_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer PF3_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] PF3_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer PF3_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] PF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] PF3_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer PF3_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] PF3_MSI_CAP_NEXTPTR = 8'h00; - parameter PF3_MSI_CAP_PERVECMASKCAP = "FALSE"; - parameter [7:0] PF3_PCIE_CAP_NEXTPTR = 8'h00; - parameter [7:0] PF3_PM_CAP_NEXTPTR = 8'h00; - parameter [11:0] PF3_PRI_CAP_NEXTPTR = 12'h000; - parameter PF3_PRI_CAP_ON = "FALSE"; - parameter [31:0] PF3_PRI_OST_PR_CAPACITY = 32'h00000000; - parameter PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; - parameter [5:0] PF3_SRIOV_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF3_SRIOV_BAR0_CONTROL = 3'h4; - parameter [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF3_SRIOV_BAR1_CONTROL = 3'h0; - parameter [5:0] PF3_SRIOV_BAR2_APERTURE_SIZE = 6'h03; - parameter [2:0] PF3_SRIOV_BAR2_CONTROL = 3'h4; - parameter [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_SRIOV_BAR3_CONTROL = 3'h0; - parameter [5:0] PF3_SRIOV_BAR4_APERTURE_SIZE = 6'h03; - parameter [2:0] PF3_SRIOV_BAR4_CONTROL = 3'h4; - parameter [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_SRIOV_BAR5_CONTROL = 3'h0; - parameter [15:0] PF3_SRIOV_CAP_INITIAL_VF = 16'h0000; - parameter [11:0] PF3_SRIOV_CAP_NEXTPTR = 12'h000; - parameter [15:0] PF3_SRIOV_CAP_TOTAL_VF = 16'h0000; - parameter [3:0] PF3_SRIOV_CAP_VER = 4'h1; - parameter [15:0] PF3_SRIOV_FIRST_VF_OFFSET = 16'h0000; - parameter [15:0] PF3_SRIOV_FUNC_DEP_LINK = 16'h0000; - parameter [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; - parameter [15:0] PF3_SRIOV_VF_DEVICE_ID = 16'h0000; - parameter [11:0] PF3_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] PF3_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter PL_CFG_STATE_ROBUSTNESS_ENABLE = "TRUE"; - parameter PL_CTRL_SKP_GEN_ENABLE = "FALSE"; - parameter PL_CTRL_SKP_PARITY_AND_CRC_CHECK_DISABLE = "TRUE"; - parameter PL_DEEMPH_SOURCE_SELECT = "TRUE"; - parameter PL_DESKEW_ON_SKIP_IN_GEN12 = "FALSE"; - parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 = "FALSE"; - parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4 = "FALSE"; - parameter PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 = "FALSE"; - parameter PL_DISABLE_DC_BALANCE = "FALSE"; - parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE"; - parameter PL_DISABLE_LANE_REVERSAL = "FALSE"; - parameter [1:0] PL_DISABLE_LFSR_UPDATE_ON_SKP = 2'h0; - parameter PL_DISABLE_RETRAIN_ON_EB_ERROR = "FALSE"; - parameter PL_DISABLE_RETRAIN_ON_FRAMING_ERROR = "FALSE"; - parameter [15:0] PL_DISABLE_RETRAIN_ON_SPECIFIC_FRAMING_ERROR = 16'h0000; - parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE"; - parameter [1:0] PL_EQ_ADAPT_DISABLE_COEFF_CHECK = 2'h0; - parameter [1:0] PL_EQ_ADAPT_DISABLE_PRESET_CHECK = 2'h0; - parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02; - parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1; - parameter [1:0] PL_EQ_BYPASS_PHASE23 = 2'h0; - parameter [5:0] PL_EQ_DEFAULT_RX_PRESET_HINT = 6'h33; - parameter [7:0] PL_EQ_DEFAULT_TX_PRESET = 8'h44; - parameter PL_EQ_DISABLE_MISMATCH_CHECK = "TRUE"; - parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE0 = 2'h0; - parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE1 = 2'h0; - parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE"; - parameter PL_EQ_TX_8G_EQ_TS2_ENABLE = "FALSE"; - parameter PL_EXIT_LOOPBACK_ON_EI_ENTRY = "TRUE"; - parameter PL_INFER_EI_DISABLE_LPBK_ACTIVE = "TRUE"; - parameter PL_INFER_EI_DISABLE_REC_RC = "FALSE"; - parameter PL_INFER_EI_DISABLE_REC_SPD = "FALSE"; - parameter [31:0] PL_LANE0_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE10_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE11_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE12_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE13_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE14_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE15_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE1_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE2_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE3_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE4_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE5_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE6_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE7_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE8_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE9_EQ_CONTROL = 32'h00003F00; - parameter [3:0] PL_LINK_CAP_MAX_LINK_SPEED = 4'h4; - parameter [4:0] PL_LINK_CAP_MAX_LINK_WIDTH = 5'h08; - parameter integer PL_N_FTS = 255; - parameter PL_QUIESCE_GUARANTEE_DISABLE = "FALSE"; - parameter PL_REDO_EQ_SOURCE_SELECT = "TRUE"; - parameter [7:0] PL_REPORT_ALL_PHY_ERRORS = 8'h00; - parameter [1:0] PL_RX_ADAPT_TIMER_CLWS_CLOBBER_TX_TS = 2'h0; - parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN3 = 4'h0; - parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN4 = 4'h0; - parameter [1:0] PL_RX_ADAPT_TIMER_RRL_CLOBBER_TX_TS = 2'h0; - parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN3 = 4'h0; - parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN4 = 4'h0; - parameter [1:0] PL_RX_L0S_EXIT_TO_RECOVERY = 2'h0; - parameter [1:0] PL_SIM_FAST_LINK_TRAINING = 2'h0; - parameter PL_SRIS_ENABLE = "FALSE"; - parameter [6:0] PL_SRIS_SKPOS_GEN_SPD_VEC = 7'h00; - parameter [6:0] PL_SRIS_SKPOS_REC_SPD_VEC = 7'h00; - parameter PL_UPSTREAM_FACING = "TRUE"; - parameter [15:0] PL_USER_SPARE = 16'h0000; - parameter [15:0] PL_USER_SPARE2 = 16'h0000; - parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h1500; - parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h003E8; - parameter PM_ENABLE_L23_ENTRY = "FALSE"; - parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE"; - parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000100; - parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h00000; - parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0100; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter [31:0] SIM_JTAG_IDCODE = 32'h00000000; - parameter SIM_VERSION = "1.0"; - parameter SPARE_BIT0 = "FALSE"; - parameter integer SPARE_BIT1 = 0; - parameter integer SPARE_BIT2 = 0; - parameter SPARE_BIT3 = "FALSE"; - parameter integer SPARE_BIT4 = 0; - parameter integer SPARE_BIT5 = 0; - parameter integer SPARE_BIT6 = 0; - parameter integer SPARE_BIT7 = 0; - parameter integer SPARE_BIT8 = 0; - parameter [7:0] SPARE_BYTE0 = 8'h00; - parameter [7:0] SPARE_BYTE1 = 8'h00; - parameter [7:0] SPARE_BYTE2 = 8'h00; - parameter [7:0] SPARE_BYTE3 = 8'h00; - parameter [31:0] SPARE_WORD0 = 32'h00000000; - parameter [31:0] SPARE_WORD1 = 32'h00000000; - parameter [31:0] SPARE_WORD2 = 32'h00000000; - parameter [31:0] SPARE_WORD3 = 32'h00000000; - parameter [3:0] SRIOV_CAP_ENABLE = 4'h0; - parameter TL2CFG_IF_PARITY_CHK = "TRUE"; - parameter [1:0] TL_COMPLETION_RAM_NUM_TLPS = 2'h0; - parameter [1:0] TL_COMPLETION_RAM_SIZE = 2'h1; - parameter [11:0] TL_CREDITS_CD = 12'h000; - parameter [11:0] TL_CREDITS_CD_VC1 = 12'h000; - parameter [7:0] TL_CREDITS_CH = 8'h00; - parameter [7:0] TL_CREDITS_CH_VC1 = 8'h00; - parameter [11:0] TL_CREDITS_NPD = 12'h004; - parameter [11:0] TL_CREDITS_NPD_VC1 = 12'h000; - parameter [7:0] TL_CREDITS_NPH = 8'h20; - parameter [7:0] TL_CREDITS_NPH_VC1 = 8'h01; - parameter [11:0] TL_CREDITS_PD = 12'h0E0; - parameter [11:0] TL_CREDITS_PD_VC1 = 12'h3E0; - parameter [7:0] TL_CREDITS_PH = 8'h20; - parameter [7:0] TL_CREDITS_PH_VC1 = 8'h20; - parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TIME = 5'h02; - parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TIME_VC1 = 5'h02; - parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT = 5'h08; - parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT_VC1 = 5'h08; - parameter TL_FEATURE_ENABLE_FC_SCALING = "FALSE"; - parameter [1:0] TL_PF_ENABLE_REG = 2'h0; - parameter [0:0] TL_POSTED_RAM_SIZE = 1'h0; - parameter TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE = "FALSE"; - parameter TL_RX_COMPLETION_TO_RAM_READ_PIPELINE = "FALSE"; - parameter TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE = "FALSE"; - parameter TL_RX_POSTED_FROM_RAM_READ_PIPELINE = "FALSE"; - parameter TL_RX_POSTED_TO_RAM_READ_PIPELINE = "FALSE"; - parameter TL_RX_POSTED_TO_RAM_WRITE_PIPELINE = "FALSE"; - parameter TL_TX_MUX_STRICT_PRIORITY = "TRUE"; - parameter TL_TX_TLP_STRADDLE_ENABLE = "FALSE"; - parameter TL_TX_TLP_TERMINATE_PARITY = "FALSE"; - parameter [15:0] TL_USER_SPARE = 16'h0000; - parameter TPH_FROM_RAM_PIPELINE = "FALSE"; - parameter TPH_TO_RAM_PIPELINE = "FALSE"; - parameter [7:0] VF0_CAPABILITY_POINTER = 8'h80; - parameter [11:0] VFG0_ARI_CAP_NEXTPTR = 12'h000; - parameter [4:0] VFG0_ATS_CAP_INV_QUEUE_DEPTH = 5'h00; - parameter [11:0] VFG0_ATS_CAP_NEXTPTR = 12'h000; - parameter VFG0_ATS_CAP_ON = "FALSE"; - parameter [7:0] VFG0_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer VFG0_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VFG0_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VFG0_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VFG0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VFG0_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter [7:0] VFG0_PCIE_CAP_NEXTPTR = 8'h00; - parameter [11:0] VFG0_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VFG0_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [11:0] VFG1_ARI_CAP_NEXTPTR = 12'h000; - parameter [4:0] VFG1_ATS_CAP_INV_QUEUE_DEPTH = 5'h00; - parameter [11:0] VFG1_ATS_CAP_NEXTPTR = 12'h000; - parameter VFG1_ATS_CAP_ON = "FALSE"; - parameter [7:0] VFG1_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer VFG1_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VFG1_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VFG1_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VFG1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VFG1_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter [7:0] VFG1_PCIE_CAP_NEXTPTR = 8'h00; - parameter [11:0] VFG1_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VFG1_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [11:0] VFG2_ARI_CAP_NEXTPTR = 12'h000; - parameter [4:0] VFG2_ATS_CAP_INV_QUEUE_DEPTH = 5'h00; - parameter [11:0] VFG2_ATS_CAP_NEXTPTR = 12'h000; - parameter VFG2_ATS_CAP_ON = "FALSE"; - parameter [7:0] VFG2_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer VFG2_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VFG2_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VFG2_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VFG2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VFG2_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter [7:0] VFG2_PCIE_CAP_NEXTPTR = 8'h00; - parameter [11:0] VFG2_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VFG2_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [11:0] VFG3_ARI_CAP_NEXTPTR = 12'h000; - parameter [4:0] VFG3_ATS_CAP_INV_QUEUE_DEPTH = 5'h00; - parameter [11:0] VFG3_ATS_CAP_NEXTPTR = 12'h000; - parameter VFG3_ATS_CAP_ON = "FALSE"; - parameter [7:0] VFG3_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer VFG3_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VFG3_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VFG3_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VFG3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VFG3_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter [7:0] VFG3_PCIE_CAP_NEXTPTR = 8'h00; - parameter [11:0] VFG3_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VFG3_TPHR_CAP_ST_MODE_SEL = 3'h0; - output [7:0] AXIUSEROUT; - output CCIXTXCREDIT; - output [7:0] CFGBUSNUMBER; - output [1:0] CFGCURRENTSPEED; - output CFGERRCOROUT; - output CFGERRFATALOUT; - output CFGERRNONFATALOUT; - output [7:0] CFGEXTFUNCTIONNUMBER; - output CFGEXTREADRECEIVED; - output [9:0] CFGEXTREGISTERNUMBER; - output [3:0] CFGEXTWRITEBYTEENABLE; - output [31:0] CFGEXTWRITEDATA; - output CFGEXTWRITERECEIVED; - output [11:0] CFGFCCPLD; - output [7:0] CFGFCCPLH; - output [11:0] CFGFCNPD; - output [7:0] CFGFCNPH; - output [11:0] CFGFCPD; - output [7:0] CFGFCPH; - output [3:0] CFGFLRINPROCESS; - output [11:0] CFGFUNCTIONPOWERSTATE; - output [15:0] CFGFUNCTIONSTATUS; - output CFGHOTRESETOUT; - output [31:0] CFGINTERRUPTMSIDATA; - output [3:0] CFGINTERRUPTMSIENABLE; - output CFGINTERRUPTMSIFAIL; - output CFGINTERRUPTMSIMASKUPDATE; - output [11:0] CFGINTERRUPTMSIMMENABLE; - output CFGINTERRUPTMSISENT; - output [3:0] CFGINTERRUPTMSIXENABLE; - output [3:0] CFGINTERRUPTMSIXMASK; - output CFGINTERRUPTMSIXVECPENDINGSTATUS; - output CFGINTERRUPTSENT; - output [1:0] CFGLINKPOWERSTATE; - output [4:0] CFGLOCALERROROUT; - output CFGLOCALERRORVALID; - output CFGLTRENABLE; - output [5:0] CFGLTSSMSTATE; - output [1:0] CFGMAXPAYLOAD; - output [2:0] CFGMAXREADREQ; - output [31:0] CFGMGMTREADDATA; - output CFGMGMTREADWRITEDONE; - output CFGMSGRECEIVED; - output [7:0] CFGMSGRECEIVEDDATA; - output [4:0] CFGMSGRECEIVEDTYPE; - output CFGMSGTRANSMITDONE; - output [12:0] CFGMSIXRAMADDRESS; - output CFGMSIXRAMREADENABLE; - output [3:0] CFGMSIXRAMWRITEBYTEENABLE; - output [35:0] CFGMSIXRAMWRITEDATA; - output [2:0] CFGNEGOTIATEDWIDTH; - output [1:0] CFGOBFFENABLE; - output CFGPHYLINKDOWN; - output [1:0] CFGPHYLINKSTATUS; - output CFGPLSTATUSCHANGE; - output CFGPOWERSTATECHANGEINTERRUPT; - output [3:0] CFGRCBSTATUS; - output [1:0] CFGRXPMSTATE; - output [11:0] CFGTPHRAMADDRESS; - output CFGTPHRAMREADENABLE; - output [3:0] CFGTPHRAMWRITEBYTEENABLE; - output [35:0] CFGTPHRAMWRITEDATA; - output [3:0] CFGTPHREQUESTERENABLE; - output [11:0] CFGTPHSTMODE; - output [1:0] CFGTXPMSTATE; - output CFGVC1ENABLE; - output CFGVC1NEGOTIATIONPENDING; - output CONFMCAPDESIGNSWITCH; - output CONFMCAPEOS; - output CONFMCAPINUSEBYPCIE; - output CONFREQREADY; - output [31:0] CONFRESPRDATA; - output CONFRESPVALID; - output [129:0] DBGCCIXOUT; - output [31:0] DBGCTRL0OUT; - output [31:0] DBGCTRL1OUT; - output [255:0] DBGDATA0OUT; - output [255:0] DBGDATA1OUT; - output [15:0] DRPDO; - output DRPRDY; - output [45:0] MAXISCCIXRXTUSER; - output MAXISCCIXRXTVALID; - output [255:0] MAXISCQTDATA; - output [7:0] MAXISCQTKEEP; - output MAXISCQTLAST; - output [87:0] MAXISCQTUSER; - output MAXISCQTVALID; - output [255:0] MAXISRCTDATA; - output [7:0] MAXISRCTKEEP; - output MAXISRCTLAST; - output [74:0] MAXISRCTUSER; - output MAXISRCTVALID; - output [8:0] MIREPLAYRAMADDRESS0; - output [8:0] MIREPLAYRAMADDRESS1; - output MIREPLAYRAMREADENABLE0; - output MIREPLAYRAMREADENABLE1; - output [127:0] MIREPLAYRAMWRITEDATA0; - output [127:0] MIREPLAYRAMWRITEDATA1; - output MIREPLAYRAMWRITEENABLE0; - output MIREPLAYRAMWRITEENABLE1; - output [8:0] MIRXCOMPLETIONRAMREADADDRESS0; - output [8:0] MIRXCOMPLETIONRAMREADADDRESS1; - output [1:0] MIRXCOMPLETIONRAMREADENABLE0; - output [1:0] MIRXCOMPLETIONRAMREADENABLE1; - output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS0; - output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS1; - output [143:0] MIRXCOMPLETIONRAMWRITEDATA0; - output [143:0] MIRXCOMPLETIONRAMWRITEDATA1; - output [1:0] MIRXCOMPLETIONRAMWRITEENABLE0; - output [1:0] MIRXCOMPLETIONRAMWRITEENABLE1; - output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS0; - output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS1; - output MIRXPOSTEDREQUESTRAMREADENABLE0; - output MIRXPOSTEDREQUESTRAMREADENABLE1; - output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS0; - output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS1; - output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA0; - output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA1; - output MIRXPOSTEDREQUESTRAMWRITEENABLE0; - output MIRXPOSTEDREQUESTRAMWRITEENABLE1; - output [5:0] PCIECQNPREQCOUNT; - output PCIEPERST0B; - output PCIEPERST1B; - output [5:0] PCIERQSEQNUM0; - output [5:0] PCIERQSEQNUM1; - output PCIERQSEQNUMVLD0; - output PCIERQSEQNUMVLD1; - output [7:0] PCIERQTAG0; - output [7:0] PCIERQTAG1; - output [3:0] PCIERQTAGAV; - output PCIERQTAGVLD0; - output PCIERQTAGVLD1; - output [3:0] PCIETFCNPDAV; - output [3:0] PCIETFCNPHAV; - output [1:0] PIPERX00EQCONTROL; - output PIPERX00POLARITY; - output [1:0] PIPERX01EQCONTROL; - output PIPERX01POLARITY; - output [1:0] PIPERX02EQCONTROL; - output PIPERX02POLARITY; - output [1:0] PIPERX03EQCONTROL; - output PIPERX03POLARITY; - output [1:0] PIPERX04EQCONTROL; - output PIPERX04POLARITY; - output [1:0] PIPERX05EQCONTROL; - output PIPERX05POLARITY; - output [1:0] PIPERX06EQCONTROL; - output PIPERX06POLARITY; - output [1:0] PIPERX07EQCONTROL; - output PIPERX07POLARITY; - output [1:0] PIPERX08EQCONTROL; - output PIPERX08POLARITY; - output [1:0] PIPERX09EQCONTROL; - output PIPERX09POLARITY; - output [1:0] PIPERX10EQCONTROL; - output PIPERX10POLARITY; - output [1:0] PIPERX11EQCONTROL; - output PIPERX11POLARITY; - output [1:0] PIPERX12EQCONTROL; - output PIPERX12POLARITY; - output [1:0] PIPERX13EQCONTROL; - output PIPERX13POLARITY; - output [1:0] PIPERX14EQCONTROL; - output PIPERX14POLARITY; - output [1:0] PIPERX15EQCONTROL; - output PIPERX15POLARITY; - output [5:0] PIPERXEQLPLFFS; - output [3:0] PIPERXEQLPTXPRESET; - output [1:0] PIPETX00CHARISK; - output PIPETX00COMPLIANCE; - output [31:0] PIPETX00DATA; - output PIPETX00DATAVALID; - output PIPETX00ELECIDLE; - output [1:0] PIPETX00EQCONTROL; - output [5:0] PIPETX00EQDEEMPH; - output [1:0] PIPETX00POWERDOWN; - output PIPETX00STARTBLOCK; - output [1:0] PIPETX00SYNCHEADER; - output [1:0] PIPETX01CHARISK; - output PIPETX01COMPLIANCE; - output [31:0] PIPETX01DATA; - output PIPETX01DATAVALID; - output PIPETX01ELECIDLE; - output [1:0] PIPETX01EQCONTROL; - output [5:0] PIPETX01EQDEEMPH; - output [1:0] PIPETX01POWERDOWN; - output PIPETX01STARTBLOCK; - output [1:0] PIPETX01SYNCHEADER; - output [1:0] PIPETX02CHARISK; - output PIPETX02COMPLIANCE; - output [31:0] PIPETX02DATA; - output PIPETX02DATAVALID; - output PIPETX02ELECIDLE; - output [1:0] PIPETX02EQCONTROL; - output [5:0] PIPETX02EQDEEMPH; - output [1:0] PIPETX02POWERDOWN; - output PIPETX02STARTBLOCK; - output [1:0] PIPETX02SYNCHEADER; - output [1:0] PIPETX03CHARISK; - output PIPETX03COMPLIANCE; - output [31:0] PIPETX03DATA; - output PIPETX03DATAVALID; - output PIPETX03ELECIDLE; - output [1:0] PIPETX03EQCONTROL; - output [5:0] PIPETX03EQDEEMPH; - output [1:0] PIPETX03POWERDOWN; - output PIPETX03STARTBLOCK; - output [1:0] PIPETX03SYNCHEADER; - output [1:0] PIPETX04CHARISK; - output PIPETX04COMPLIANCE; - output [31:0] PIPETX04DATA; - output PIPETX04DATAVALID; - output PIPETX04ELECIDLE; - output [1:0] PIPETX04EQCONTROL; - output [5:0] PIPETX04EQDEEMPH; - output [1:0] PIPETX04POWERDOWN; - output PIPETX04STARTBLOCK; - output [1:0] PIPETX04SYNCHEADER; - output [1:0] PIPETX05CHARISK; - output PIPETX05COMPLIANCE; - output [31:0] PIPETX05DATA; - output PIPETX05DATAVALID; - output PIPETX05ELECIDLE; - output [1:0] PIPETX05EQCONTROL; - output [5:0] PIPETX05EQDEEMPH; - output [1:0] PIPETX05POWERDOWN; - output PIPETX05STARTBLOCK; - output [1:0] PIPETX05SYNCHEADER; - output [1:0] PIPETX06CHARISK; - output PIPETX06COMPLIANCE; - output [31:0] PIPETX06DATA; - output PIPETX06DATAVALID; - output PIPETX06ELECIDLE; - output [1:0] PIPETX06EQCONTROL; - output [5:0] PIPETX06EQDEEMPH; - output [1:0] PIPETX06POWERDOWN; - output PIPETX06STARTBLOCK; - output [1:0] PIPETX06SYNCHEADER; - output [1:0] PIPETX07CHARISK; - output PIPETX07COMPLIANCE; - output [31:0] PIPETX07DATA; - output PIPETX07DATAVALID; - output PIPETX07ELECIDLE; - output [1:0] PIPETX07EQCONTROL; - output [5:0] PIPETX07EQDEEMPH; - output [1:0] PIPETX07POWERDOWN; - output PIPETX07STARTBLOCK; - output [1:0] PIPETX07SYNCHEADER; - output [1:0] PIPETX08CHARISK; - output PIPETX08COMPLIANCE; - output [31:0] PIPETX08DATA; - output PIPETX08DATAVALID; - output PIPETX08ELECIDLE; - output [1:0] PIPETX08EQCONTROL; - output [5:0] PIPETX08EQDEEMPH; - output [1:0] PIPETX08POWERDOWN; - output PIPETX08STARTBLOCK; - output [1:0] PIPETX08SYNCHEADER; - output [1:0] PIPETX09CHARISK; - output PIPETX09COMPLIANCE; - output [31:0] PIPETX09DATA; - output PIPETX09DATAVALID; - output PIPETX09ELECIDLE; - output [1:0] PIPETX09EQCONTROL; - output [5:0] PIPETX09EQDEEMPH; - output [1:0] PIPETX09POWERDOWN; - output PIPETX09STARTBLOCK; - output [1:0] PIPETX09SYNCHEADER; - output [1:0] PIPETX10CHARISK; - output PIPETX10COMPLIANCE; - output [31:0] PIPETX10DATA; - output PIPETX10DATAVALID; - output PIPETX10ELECIDLE; - output [1:0] PIPETX10EQCONTROL; - output [5:0] PIPETX10EQDEEMPH; - output [1:0] PIPETX10POWERDOWN; - output PIPETX10STARTBLOCK; - output [1:0] PIPETX10SYNCHEADER; - output [1:0] PIPETX11CHARISK; - output PIPETX11COMPLIANCE; - output [31:0] PIPETX11DATA; - output PIPETX11DATAVALID; - output PIPETX11ELECIDLE; - output [1:0] PIPETX11EQCONTROL; - output [5:0] PIPETX11EQDEEMPH; - output [1:0] PIPETX11POWERDOWN; - output PIPETX11STARTBLOCK; - output [1:0] PIPETX11SYNCHEADER; - output [1:0] PIPETX12CHARISK; - output PIPETX12COMPLIANCE; - output [31:0] PIPETX12DATA; - output PIPETX12DATAVALID; - output PIPETX12ELECIDLE; - output [1:0] PIPETX12EQCONTROL; - output [5:0] PIPETX12EQDEEMPH; - output [1:0] PIPETX12POWERDOWN; - output PIPETX12STARTBLOCK; - output [1:0] PIPETX12SYNCHEADER; - output [1:0] PIPETX13CHARISK; - output PIPETX13COMPLIANCE; - output [31:0] PIPETX13DATA; - output PIPETX13DATAVALID; - output PIPETX13ELECIDLE; - output [1:0] PIPETX13EQCONTROL; - output [5:0] PIPETX13EQDEEMPH; - output [1:0] PIPETX13POWERDOWN; - output PIPETX13STARTBLOCK; - output [1:0] PIPETX13SYNCHEADER; - output [1:0] PIPETX14CHARISK; - output PIPETX14COMPLIANCE; - output [31:0] PIPETX14DATA; - output PIPETX14DATAVALID; - output PIPETX14ELECIDLE; - output [1:0] PIPETX14EQCONTROL; - output [5:0] PIPETX14EQDEEMPH; - output [1:0] PIPETX14POWERDOWN; - output PIPETX14STARTBLOCK; - output [1:0] PIPETX14SYNCHEADER; - output [1:0] PIPETX15CHARISK; - output PIPETX15COMPLIANCE; - output [31:0] PIPETX15DATA; - output PIPETX15DATAVALID; - output PIPETX15ELECIDLE; - output [1:0] PIPETX15EQCONTROL; - output [5:0] PIPETX15EQDEEMPH; - output [1:0] PIPETX15POWERDOWN; - output PIPETX15STARTBLOCK; - output [1:0] PIPETX15SYNCHEADER; - output PIPETXDEEMPH; - output [2:0] PIPETXMARGIN; - output [1:0] PIPETXRATE; - output PIPETXRCVRDET; - output PIPETXRESET; - output PIPETXSWING; - output PLEQINPROGRESS; - output [1:0] PLEQPHASE; - output PLGEN34EQMISMATCH; - output [3:0] SAXISCCTREADY; - output [3:0] SAXISRQTREADY; - output [23:0] USERSPAREOUT; - input [7:0] AXIUSERIN; - input CCIXOPTIMIZEDTLPTXANDRXENABLE; - input CCIXRXCORRECTABLEERRORDETECTED; - input CCIXRXFIFOOVERFLOW; - input CCIXRXTLPFORWARDED0; - input CCIXRXTLPFORWARDED1; - input [5:0] CCIXRXTLPFORWARDEDLENGTH0; - input [5:0] CCIXRXTLPFORWARDEDLENGTH1; - input CCIXRXUNCORRECTABLEERRORDETECTED; - input CFGCONFIGSPACEENABLE; - input [15:0] CFGDEVIDPF0; - input [15:0] CFGDEVIDPF1; - input [15:0] CFGDEVIDPF2; - input [15:0] CFGDEVIDPF3; - input [7:0] CFGDSBUSNUMBER; - input [4:0] CFGDSDEVICENUMBER; - input [2:0] CFGDSFUNCTIONNUMBER; - input [63:0] CFGDSN; - input [7:0] CFGDSPORTNUMBER; - input CFGERRCORIN; - input CFGERRUNCORIN; - input [31:0] CFGEXTREADDATA; - input CFGEXTREADDATAVALID; - input [2:0] CFGFCSEL; - input CFGFCVCSEL; - input [3:0] CFGFLRDONE; - input CFGHOTRESETIN; - input [3:0] CFGINTERRUPTINT; - input [2:0] CFGINTERRUPTMSIATTR; - input [7:0] CFGINTERRUPTMSIFUNCTIONNUMBER; - input [31:0] CFGINTERRUPTMSIINT; - input [31:0] CFGINTERRUPTMSIPENDINGSTATUS; - input CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE; - input [1:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM; - input [1:0] CFGINTERRUPTMSISELECT; - input CFGINTERRUPTMSITPHPRESENT; - input [7:0] CFGINTERRUPTMSITPHSTTAG; - input [1:0] CFGINTERRUPTMSITPHTYPE; - input [63:0] CFGINTERRUPTMSIXADDRESS; - input [31:0] CFGINTERRUPTMSIXDATA; - input CFGINTERRUPTMSIXINT; - input [1:0] CFGINTERRUPTMSIXVECPENDING; - input [3:0] CFGINTERRUPTPENDING; - input CFGLINKTRAININGENABLE; - input [9:0] CFGMGMTADDR; - input [3:0] CFGMGMTBYTEENABLE; - input CFGMGMTDEBUGACCESS; - input [7:0] CFGMGMTFUNCTIONNUMBER; - input CFGMGMTREAD; - input CFGMGMTWRITE; - input [31:0] CFGMGMTWRITEDATA; - input CFGMSGTRANSMIT; - input [31:0] CFGMSGTRANSMITDATA; - input [2:0] CFGMSGTRANSMITTYPE; - input [35:0] CFGMSIXRAMREADDATA; - input CFGPMASPML1ENTRYREJECT; - input CFGPMASPMTXL0SENTRYDISABLE; - input CFGPOWERSTATECHANGEACK; - input CFGREQPMTRANSITIONL23READY; - input [7:0] CFGREVIDPF0; - input [7:0] CFGREVIDPF1; - input [7:0] CFGREVIDPF2; - input [7:0] CFGREVIDPF3; - input [15:0] CFGSUBSYSIDPF0; - input [15:0] CFGSUBSYSIDPF1; - input [15:0] CFGSUBSYSIDPF2; - input [15:0] CFGSUBSYSIDPF3; - input [15:0] CFGSUBSYSVENDID; - input [35:0] CFGTPHRAMREADDATA; - input [15:0] CFGVENDID; - input CFGVFFLRDONE; - input [7:0] CFGVFFLRFUNCNUM; - input CONFMCAPREQUESTBYCONF; - input [31:0] CONFREQDATA; - input [3:0] CONFREQREGNUM; - input [1:0] CONFREQTYPE; - input CONFREQVALID; - input CORECLK; - input CORECLKCCIX; - input CORECLKMIREPLAYRAM0; - input CORECLKMIREPLAYRAM1; - input CORECLKMIRXCOMPLETIONRAM0; - input CORECLKMIRXCOMPLETIONRAM1; - input CORECLKMIRXPOSTEDREQUESTRAM0; - input CORECLKMIRXPOSTEDREQUESTRAM1; - input [5:0] DBGSEL0; - input [5:0] DBGSEL1; - input [9:0] DRPADDR; - input DRPCLK; - input [15:0] DRPDI; - input DRPEN; - input DRPWE; - input [21:0] MAXISCQTREADY; - input [21:0] MAXISRCTREADY; - input MCAPCLK; - input MCAPPERST0B; - input MCAPPERST1B; - input MGMTRESETN; - input MGMTSTICKYRESETN; - input [5:0] MIREPLAYRAMERRCOR; - input [5:0] MIREPLAYRAMERRUNCOR; - input [127:0] MIREPLAYRAMREADDATA0; - input [127:0] MIREPLAYRAMREADDATA1; - input [11:0] MIRXCOMPLETIONRAMERRCOR; - input [11:0] MIRXCOMPLETIONRAMERRUNCOR; - input [143:0] MIRXCOMPLETIONRAMREADDATA0; - input [143:0] MIRXCOMPLETIONRAMREADDATA1; - input [5:0] MIRXPOSTEDREQUESTRAMERRCOR; - input [5:0] MIRXPOSTEDREQUESTRAMERRUNCOR; - input [143:0] MIRXPOSTEDREQUESTRAMREADDATA0; - input [143:0] MIRXPOSTEDREQUESTRAMREADDATA1; - input [1:0] PCIECOMPLDELIVERED; - input [7:0] PCIECOMPLDELIVEREDTAG0; - input [7:0] PCIECOMPLDELIVEREDTAG1; - input [1:0] PCIECQNPREQ; - input PCIECQNPUSERCREDITRCVD; - input PCIECQPIPELINEEMPTY; - input PCIEPOSTEDREQDELIVERED; - input PIPECLK; - input PIPECLKEN; - input [5:0] PIPEEQFS; - input [5:0] PIPEEQLF; - input PIPERESETN; - input [1:0] PIPERX00CHARISK; - input [31:0] PIPERX00DATA; - input PIPERX00DATAVALID; - input PIPERX00ELECIDLE; - input PIPERX00EQDONE; - input PIPERX00EQLPADAPTDONE; - input PIPERX00EQLPLFFSSEL; - input [17:0] PIPERX00EQLPNEWTXCOEFFORPRESET; - input PIPERX00PHYSTATUS; - input [1:0] PIPERX00STARTBLOCK; - input [2:0] PIPERX00STATUS; - input [1:0] PIPERX00SYNCHEADER; - input PIPERX00VALID; - input [1:0] PIPERX01CHARISK; - input [31:0] PIPERX01DATA; - input PIPERX01DATAVALID; - input PIPERX01ELECIDLE; - input PIPERX01EQDONE; - input PIPERX01EQLPADAPTDONE; - input PIPERX01EQLPLFFSSEL; - input [17:0] PIPERX01EQLPNEWTXCOEFFORPRESET; - input PIPERX01PHYSTATUS; - input [1:0] PIPERX01STARTBLOCK; - input [2:0] PIPERX01STATUS; - input [1:0] PIPERX01SYNCHEADER; - input PIPERX01VALID; - input [1:0] PIPERX02CHARISK; - input [31:0] PIPERX02DATA; - input PIPERX02DATAVALID; - input PIPERX02ELECIDLE; - input PIPERX02EQDONE; - input PIPERX02EQLPADAPTDONE; - input PIPERX02EQLPLFFSSEL; - input [17:0] PIPERX02EQLPNEWTXCOEFFORPRESET; - input PIPERX02PHYSTATUS; - input [1:0] PIPERX02STARTBLOCK; - input [2:0] PIPERX02STATUS; - input [1:0] PIPERX02SYNCHEADER; - input PIPERX02VALID; - input [1:0] PIPERX03CHARISK; - input [31:0] PIPERX03DATA; - input PIPERX03DATAVALID; - input PIPERX03ELECIDLE; - input PIPERX03EQDONE; - input PIPERX03EQLPADAPTDONE; - input PIPERX03EQLPLFFSSEL; - input [17:0] PIPERX03EQLPNEWTXCOEFFORPRESET; - input PIPERX03PHYSTATUS; - input [1:0] PIPERX03STARTBLOCK; - input [2:0] PIPERX03STATUS; - input [1:0] PIPERX03SYNCHEADER; - input PIPERX03VALID; - input [1:0] PIPERX04CHARISK; - input [31:0] PIPERX04DATA; - input PIPERX04DATAVALID; - input PIPERX04ELECIDLE; - input PIPERX04EQDONE; - input PIPERX04EQLPADAPTDONE; - input PIPERX04EQLPLFFSSEL; - input [17:0] PIPERX04EQLPNEWTXCOEFFORPRESET; - input PIPERX04PHYSTATUS; - input [1:0] PIPERX04STARTBLOCK; - input [2:0] PIPERX04STATUS; - input [1:0] PIPERX04SYNCHEADER; - input PIPERX04VALID; - input [1:0] PIPERX05CHARISK; - input [31:0] PIPERX05DATA; - input PIPERX05DATAVALID; - input PIPERX05ELECIDLE; - input PIPERX05EQDONE; - input PIPERX05EQLPADAPTDONE; - input PIPERX05EQLPLFFSSEL; - input [17:0] PIPERX05EQLPNEWTXCOEFFORPRESET; - input PIPERX05PHYSTATUS; - input [1:0] PIPERX05STARTBLOCK; - input [2:0] PIPERX05STATUS; - input [1:0] PIPERX05SYNCHEADER; - input PIPERX05VALID; - input [1:0] PIPERX06CHARISK; - input [31:0] PIPERX06DATA; - input PIPERX06DATAVALID; - input PIPERX06ELECIDLE; - input PIPERX06EQDONE; - input PIPERX06EQLPADAPTDONE; - input PIPERX06EQLPLFFSSEL; - input [17:0] PIPERX06EQLPNEWTXCOEFFORPRESET; - input PIPERX06PHYSTATUS; - input [1:0] PIPERX06STARTBLOCK; - input [2:0] PIPERX06STATUS; - input [1:0] PIPERX06SYNCHEADER; - input PIPERX06VALID; - input [1:0] PIPERX07CHARISK; - input [31:0] PIPERX07DATA; - input PIPERX07DATAVALID; - input PIPERX07ELECIDLE; - input PIPERX07EQDONE; - input PIPERX07EQLPADAPTDONE; - input PIPERX07EQLPLFFSSEL; - input [17:0] PIPERX07EQLPNEWTXCOEFFORPRESET; - input PIPERX07PHYSTATUS; - input [1:0] PIPERX07STARTBLOCK; - input [2:0] PIPERX07STATUS; - input [1:0] PIPERX07SYNCHEADER; - input PIPERX07VALID; - input [1:0] PIPERX08CHARISK; - input [31:0] PIPERX08DATA; - input PIPERX08DATAVALID; - input PIPERX08ELECIDLE; - input PIPERX08EQDONE; - input PIPERX08EQLPADAPTDONE; - input PIPERX08EQLPLFFSSEL; - input [17:0] PIPERX08EQLPNEWTXCOEFFORPRESET; - input PIPERX08PHYSTATUS; - input [1:0] PIPERX08STARTBLOCK; - input [2:0] PIPERX08STATUS; - input [1:0] PIPERX08SYNCHEADER; - input PIPERX08VALID; - input [1:0] PIPERX09CHARISK; - input [31:0] PIPERX09DATA; - input PIPERX09DATAVALID; - input PIPERX09ELECIDLE; - input PIPERX09EQDONE; - input PIPERX09EQLPADAPTDONE; - input PIPERX09EQLPLFFSSEL; - input [17:0] PIPERX09EQLPNEWTXCOEFFORPRESET; - input PIPERX09PHYSTATUS; - input [1:0] PIPERX09STARTBLOCK; - input [2:0] PIPERX09STATUS; - input [1:0] PIPERX09SYNCHEADER; - input PIPERX09VALID; - input [1:0] PIPERX10CHARISK; - input [31:0] PIPERX10DATA; - input PIPERX10DATAVALID; - input PIPERX10ELECIDLE; - input PIPERX10EQDONE; - input PIPERX10EQLPADAPTDONE; - input PIPERX10EQLPLFFSSEL; - input [17:0] PIPERX10EQLPNEWTXCOEFFORPRESET; - input PIPERX10PHYSTATUS; - input [1:0] PIPERX10STARTBLOCK; - input [2:0] PIPERX10STATUS; - input [1:0] PIPERX10SYNCHEADER; - input PIPERX10VALID; - input [1:0] PIPERX11CHARISK; - input [31:0] PIPERX11DATA; - input PIPERX11DATAVALID; - input PIPERX11ELECIDLE; - input PIPERX11EQDONE; - input PIPERX11EQLPADAPTDONE; - input PIPERX11EQLPLFFSSEL; - input [17:0] PIPERX11EQLPNEWTXCOEFFORPRESET; - input PIPERX11PHYSTATUS; - input [1:0] PIPERX11STARTBLOCK; - input [2:0] PIPERX11STATUS; - input [1:0] PIPERX11SYNCHEADER; - input PIPERX11VALID; - input [1:0] PIPERX12CHARISK; - input [31:0] PIPERX12DATA; - input PIPERX12DATAVALID; - input PIPERX12ELECIDLE; - input PIPERX12EQDONE; - input PIPERX12EQLPADAPTDONE; - input PIPERX12EQLPLFFSSEL; - input [17:0] PIPERX12EQLPNEWTXCOEFFORPRESET; - input PIPERX12PHYSTATUS; - input [1:0] PIPERX12STARTBLOCK; - input [2:0] PIPERX12STATUS; - input [1:0] PIPERX12SYNCHEADER; - input PIPERX12VALID; - input [1:0] PIPERX13CHARISK; - input [31:0] PIPERX13DATA; - input PIPERX13DATAVALID; - input PIPERX13ELECIDLE; - input PIPERX13EQDONE; - input PIPERX13EQLPADAPTDONE; - input PIPERX13EQLPLFFSSEL; - input [17:0] PIPERX13EQLPNEWTXCOEFFORPRESET; - input PIPERX13PHYSTATUS; - input [1:0] PIPERX13STARTBLOCK; - input [2:0] PIPERX13STATUS; - input [1:0] PIPERX13SYNCHEADER; - input PIPERX13VALID; - input [1:0] PIPERX14CHARISK; - input [31:0] PIPERX14DATA; - input PIPERX14DATAVALID; - input PIPERX14ELECIDLE; - input PIPERX14EQDONE; - input PIPERX14EQLPADAPTDONE; - input PIPERX14EQLPLFFSSEL; - input [17:0] PIPERX14EQLPNEWTXCOEFFORPRESET; - input PIPERX14PHYSTATUS; - input [1:0] PIPERX14STARTBLOCK; - input [2:0] PIPERX14STATUS; - input [1:0] PIPERX14SYNCHEADER; - input PIPERX14VALID; - input [1:0] PIPERX15CHARISK; - input [31:0] PIPERX15DATA; - input PIPERX15DATAVALID; - input PIPERX15ELECIDLE; - input PIPERX15EQDONE; - input PIPERX15EQLPADAPTDONE; - input PIPERX15EQLPLFFSSEL; - input [17:0] PIPERX15EQLPNEWTXCOEFFORPRESET; - input PIPERX15PHYSTATUS; - input [1:0] PIPERX15STARTBLOCK; - input [2:0] PIPERX15STATUS; - input [1:0] PIPERX15SYNCHEADER; - input PIPERX15VALID; - input [17:0] PIPETX00EQCOEFF; - input PIPETX00EQDONE; - input [17:0] PIPETX01EQCOEFF; - input PIPETX01EQDONE; - input [17:0] PIPETX02EQCOEFF; - input PIPETX02EQDONE; - input [17:0] PIPETX03EQCOEFF; - input PIPETX03EQDONE; - input [17:0] PIPETX04EQCOEFF; - input PIPETX04EQDONE; - input [17:0] PIPETX05EQCOEFF; - input PIPETX05EQDONE; - input [17:0] PIPETX06EQCOEFF; - input PIPETX06EQDONE; - input [17:0] PIPETX07EQCOEFF; - input PIPETX07EQDONE; - input [17:0] PIPETX08EQCOEFF; - input PIPETX08EQDONE; - input [17:0] PIPETX09EQCOEFF; - input PIPETX09EQDONE; - input [17:0] PIPETX10EQCOEFF; - input PIPETX10EQDONE; - input [17:0] PIPETX11EQCOEFF; - input PIPETX11EQDONE; - input [17:0] PIPETX12EQCOEFF; - input PIPETX12EQDONE; - input [17:0] PIPETX13EQCOEFF; - input PIPETX13EQDONE; - input [17:0] PIPETX14EQCOEFF; - input PIPETX14EQDONE; - input [17:0] PIPETX15EQCOEFF; - input PIPETX15EQDONE; - input PLEQRESETEIEOSCOUNT; - input PLGEN2UPSTREAMPREFERDEEMPH; - input PLGEN34REDOEQSPEED; - input PLGEN34REDOEQUALIZATION; - input RESETN; - input [255:0] SAXISCCIXTXTDATA; - input [45:0] SAXISCCIXTXTUSER; - input SAXISCCIXTXTVALID; - input [255:0] SAXISCCTDATA; - input [7:0] SAXISCCTKEEP; - input SAXISCCTLAST; - input [32:0] SAXISCCTUSER; - input SAXISCCTVALID; - input [255:0] SAXISRQTDATA; - input [7:0] SAXISRQTKEEP; - input SAXISRQTLAST; - input [61:0] SAXISRQTUSER; - input SAXISRQTVALID; - input USERCLK; - input USERCLK2; - input USERCLKEN; - input [31:0] USERSPAREIN; -endmodule - -module EMAC (...); - parameter EMAC0_MODE = "RGMII"; - parameter EMAC1_MODE = "RGMII"; - output DCRHOSTDONEIR; - output EMAC0CLIENTANINTERRUPT; - output EMAC0CLIENTRXBADFRAME; - output EMAC0CLIENTRXCLIENTCLKOUT; - output EMAC0CLIENTRXDVLD; - output EMAC0CLIENTRXDVLDMSW; - output EMAC0CLIENTRXDVREG6; - output EMAC0CLIENTRXFRAMEDROP; - output EMAC0CLIENTRXGOODFRAME; - output EMAC0CLIENTRXSTATSBYTEVLD; - output EMAC0CLIENTRXSTATSVLD; - output EMAC0CLIENTTXACK; - output EMAC0CLIENTTXCLIENTCLKOUT; - output EMAC0CLIENTTXCOLLISION; - output EMAC0CLIENTTXGMIIMIICLKOUT; - output EMAC0CLIENTTXRETRANSMIT; - output EMAC0CLIENTTXSTATS; - output EMAC0CLIENTTXSTATSBYTEVLD; - output EMAC0CLIENTTXSTATSVLD; - output EMAC0PHYENCOMMAALIGN; - output EMAC0PHYLOOPBACKMSB; - output EMAC0PHYMCLKOUT; - output EMAC0PHYMDOUT; - output EMAC0PHYMDTRI; - output EMAC0PHYMGTRXRESET; - output EMAC0PHYMGTTXRESET; - output EMAC0PHYPOWERDOWN; - output EMAC0PHYSYNCACQSTATUS; - output EMAC0PHYTXCHARDISPMODE; - output EMAC0PHYTXCHARDISPVAL; - output EMAC0PHYTXCHARISK; - output EMAC0PHYTXCLK; - output EMAC0PHYTXEN; - output EMAC0PHYTXER; - output EMAC1CLIENTANINTERRUPT; - output EMAC1CLIENTRXBADFRAME; - output EMAC1CLIENTRXCLIENTCLKOUT; - output EMAC1CLIENTRXDVLD; - output EMAC1CLIENTRXDVLDMSW; - output EMAC1CLIENTRXDVREG6; - output EMAC1CLIENTRXFRAMEDROP; - output EMAC1CLIENTRXGOODFRAME; - output EMAC1CLIENTRXSTATSBYTEVLD; - output EMAC1CLIENTRXSTATSVLD; - output EMAC1CLIENTTXACK; - output EMAC1CLIENTTXCLIENTCLKOUT; - output EMAC1CLIENTTXCOLLISION; - output EMAC1CLIENTTXGMIIMIICLKOUT; - output EMAC1CLIENTTXRETRANSMIT; - output EMAC1CLIENTTXSTATS; - output EMAC1CLIENTTXSTATSBYTEVLD; - output EMAC1CLIENTTXSTATSVLD; - output EMAC1PHYENCOMMAALIGN; - output EMAC1PHYLOOPBACKMSB; - output EMAC1PHYMCLKOUT; - output EMAC1PHYMDOUT; - output EMAC1PHYMDTRI; - output EMAC1PHYMGTRXRESET; - output EMAC1PHYMGTTXRESET; - output EMAC1PHYPOWERDOWN; - output EMAC1PHYSYNCACQSTATUS; - output EMAC1PHYTXCHARDISPMODE; - output EMAC1PHYTXCHARDISPVAL; - output EMAC1PHYTXCHARISK; - output EMAC1PHYTXCLK; - output EMAC1PHYTXEN; - output EMAC1PHYTXER; - output EMACDCRACK; - output HOSTMIIMRDY; - output [0:31] EMACDCRDBUS; - output [15:0] EMAC0CLIENTRXD; - output [15:0] EMAC1CLIENTRXD; - output [31:0] HOSTRDDATA; - output [6:0] EMAC0CLIENTRXSTATS; - output [6:0] EMAC1CLIENTRXSTATS; - output [7:0] EMAC0PHYTXD; - output [7:0] EMAC1PHYTXD; - input CLIENTEMAC0DCMLOCKED; - input CLIENTEMAC0PAUSEREQ; - input CLIENTEMAC0RXCLIENTCLKIN; - input CLIENTEMAC0TXCLIENTCLKIN; - input CLIENTEMAC0TXDVLD; - input CLIENTEMAC0TXDVLDMSW; - input CLIENTEMAC0TXFIRSTBYTE; - input CLIENTEMAC0TXGMIIMIICLKIN; - input CLIENTEMAC0TXUNDERRUN; - input CLIENTEMAC1DCMLOCKED; - input CLIENTEMAC1PAUSEREQ; - input CLIENTEMAC1RXCLIENTCLKIN; - input CLIENTEMAC1TXCLIENTCLKIN; - input CLIENTEMAC1TXDVLD; - input CLIENTEMAC1TXDVLDMSW; - input CLIENTEMAC1TXFIRSTBYTE; - input CLIENTEMAC1TXGMIIMIICLKIN; - input CLIENTEMAC1TXUNDERRUN; - input DCREMACCLK; - input DCREMACENABLE; - input DCREMACREAD; - input DCREMACWRITE; - input HOSTCLK; - input HOSTEMAC1SEL; - input HOSTMIIMSEL; - input HOSTREQ; - input PHYEMAC0COL; - input PHYEMAC0CRS; - input PHYEMAC0GTXCLK; - input PHYEMAC0MCLKIN; - input PHYEMAC0MDIN; - input PHYEMAC0MIITXCLK; - input PHYEMAC0RXBUFERR; - input PHYEMAC0RXCHARISCOMMA; - input PHYEMAC0RXCHARISK; - input PHYEMAC0RXCHECKINGCRC; - input PHYEMAC0RXCLK; - input PHYEMAC0RXCOMMADET; - input PHYEMAC0RXDISPERR; - input PHYEMAC0RXDV; - input PHYEMAC0RXER; - input PHYEMAC0RXNOTINTABLE; - input PHYEMAC0RXRUNDISP; - input PHYEMAC0SIGNALDET; - input PHYEMAC0TXBUFERR; - input PHYEMAC1COL; - input PHYEMAC1CRS; - input PHYEMAC1GTXCLK; - input PHYEMAC1MCLKIN; - input PHYEMAC1MDIN; - input PHYEMAC1MIITXCLK; - input PHYEMAC1RXBUFERR; - input PHYEMAC1RXCHARISCOMMA; - input PHYEMAC1RXCHARISK; - input PHYEMAC1RXCHECKINGCRC; - input PHYEMAC1RXCLK; - input PHYEMAC1RXCOMMADET; - input PHYEMAC1RXDISPERR; - input PHYEMAC1RXDV; - input PHYEMAC1RXER; - input PHYEMAC1RXNOTINTABLE; - input PHYEMAC1RXRUNDISP; - input PHYEMAC1SIGNALDET; - input PHYEMAC1TXBUFERR; - input RESET; - input [0:31] DCREMACDBUS; - input [15:0] CLIENTEMAC0PAUSEVAL; - input [15:0] CLIENTEMAC0TXD; - input [15:0] CLIENTEMAC1PAUSEVAL; - input [15:0] CLIENTEMAC1TXD; - input [1:0] HOSTOPCODE; - input [1:0] PHYEMAC0RXBUFSTATUS; - input [1:0] PHYEMAC0RXLOSSOFSYNC; - input [1:0] PHYEMAC1RXBUFSTATUS; - input [1:0] PHYEMAC1RXLOSSOFSYNC; - input [2:0] PHYEMAC0RXCLKCORCNT; - input [2:0] PHYEMAC1RXCLKCORCNT; - input [31:0] HOSTWRDATA; - input [47:0] TIEEMAC0UNICASTADDR; - input [47:0] TIEEMAC1UNICASTADDR; - input [4:0] PHYEMAC0PHYAD; - input [4:0] PHYEMAC1PHYAD; - input [79:0] TIEEMAC0CONFIGVEC; - input [79:0] TIEEMAC1CONFIGVEC; - input [7:0] CLIENTEMAC0TXIFGDELAY; - input [7:0] CLIENTEMAC1TXIFGDELAY; - input [7:0] PHYEMAC0RXD; - input [7:0] PHYEMAC1RXD; - input [8:9] DCREMACABUS; - input [9:0] HOSTADDR; -endmodule - -module TEMAC (...); - parameter EMAC0_1000BASEX_ENABLE = "FALSE"; - parameter EMAC0_ADDRFILTER_ENABLE = "FALSE"; - parameter EMAC0_BYTEPHY = "FALSE"; - parameter EMAC0_CONFIGVEC_79 = "FALSE"; - parameter EMAC0_GTLOOPBACK = "FALSE"; - parameter EMAC0_HOST_ENABLE = "FALSE"; - parameter EMAC0_LTCHECK_DISABLE = "FALSE"; - parameter EMAC0_MDIO_ENABLE = "FALSE"; - parameter EMAC0_PHYINITAUTONEG_ENABLE = "FALSE"; - parameter EMAC0_PHYISOLATE = "FALSE"; - parameter EMAC0_PHYLOOPBACKMSB = "FALSE"; - parameter EMAC0_PHYPOWERDOWN = "FALSE"; - parameter EMAC0_PHYRESET = "FALSE"; - parameter EMAC0_RGMII_ENABLE = "FALSE"; - parameter EMAC0_RX16BITCLIENT_ENABLE = "FALSE"; - parameter EMAC0_RXFLOWCTRL_ENABLE = "FALSE"; - parameter EMAC0_RXHALFDUPLEX = "FALSE"; - parameter EMAC0_RXINBANDFCS_ENABLE = "FALSE"; - parameter EMAC0_RXJUMBOFRAME_ENABLE = "FALSE"; - parameter EMAC0_RXRESET = "FALSE"; - parameter EMAC0_RXVLAN_ENABLE = "FALSE"; - parameter EMAC0_RX_ENABLE = "FALSE"; - parameter EMAC0_SGMII_ENABLE = "FALSE"; - parameter EMAC0_SPEED_LSB = "FALSE"; - parameter EMAC0_SPEED_MSB = "FALSE"; - parameter EMAC0_TX16BITCLIENT_ENABLE = "FALSE"; - parameter EMAC0_TXFLOWCTRL_ENABLE = "FALSE"; - parameter EMAC0_TXHALFDUPLEX = "FALSE"; - parameter EMAC0_TXIFGADJUST_ENABLE = "FALSE"; - parameter EMAC0_TXINBANDFCS_ENABLE = "FALSE"; - parameter EMAC0_TXJUMBOFRAME_ENABLE = "FALSE"; - parameter EMAC0_TXRESET = "FALSE"; - parameter EMAC0_TXVLAN_ENABLE = "FALSE"; - parameter EMAC0_TX_ENABLE = "FALSE"; - parameter EMAC0_UNIDIRECTION_ENABLE = "FALSE"; - parameter EMAC0_USECLKEN = "FALSE"; - parameter EMAC1_1000BASEX_ENABLE = "FALSE"; - parameter EMAC1_ADDRFILTER_ENABLE = "FALSE"; - parameter EMAC1_BYTEPHY = "FALSE"; - parameter EMAC1_CONFIGVEC_79 = "FALSE"; - parameter EMAC1_GTLOOPBACK = "FALSE"; - parameter EMAC1_HOST_ENABLE = "FALSE"; - parameter EMAC1_LTCHECK_DISABLE = "FALSE"; - parameter EMAC1_MDIO_ENABLE = "FALSE"; - parameter EMAC1_PHYINITAUTONEG_ENABLE = "FALSE"; - parameter EMAC1_PHYISOLATE = "FALSE"; - parameter EMAC1_PHYLOOPBACKMSB = "FALSE"; - parameter EMAC1_PHYPOWERDOWN = "FALSE"; - parameter EMAC1_PHYRESET = "FALSE"; - parameter EMAC1_RGMII_ENABLE = "FALSE"; - parameter EMAC1_RX16BITCLIENT_ENABLE = "FALSE"; - parameter EMAC1_RXFLOWCTRL_ENABLE = "FALSE"; - parameter EMAC1_RXHALFDUPLEX = "FALSE"; - parameter EMAC1_RXINBANDFCS_ENABLE = "FALSE"; - parameter EMAC1_RXJUMBOFRAME_ENABLE = "FALSE"; - parameter EMAC1_RXRESET = "FALSE"; - parameter EMAC1_RXVLAN_ENABLE = "FALSE"; - parameter EMAC1_RX_ENABLE = "FALSE"; - parameter EMAC1_SGMII_ENABLE = "FALSE"; - parameter EMAC1_SPEED_LSB = "FALSE"; - parameter EMAC1_SPEED_MSB = "FALSE"; - parameter EMAC1_TX16BITCLIENT_ENABLE = "FALSE"; - parameter EMAC1_TXFLOWCTRL_ENABLE = "FALSE"; - parameter EMAC1_TXHALFDUPLEX = "FALSE"; - parameter EMAC1_TXIFGADJUST_ENABLE = "FALSE"; - parameter EMAC1_TXINBANDFCS_ENABLE = "FALSE"; - parameter EMAC1_TXJUMBOFRAME_ENABLE = "FALSE"; - parameter EMAC1_TXRESET = "FALSE"; - parameter EMAC1_TXVLAN_ENABLE = "FALSE"; - parameter EMAC1_TX_ENABLE = "FALSE"; - parameter EMAC1_UNIDIRECTION_ENABLE = "FALSE"; - parameter EMAC1_USECLKEN = "FALSE"; - parameter [0:7] EMAC0_DCRBASEADDR = 8'h00; - parameter [0:7] EMAC1_DCRBASEADDR = 8'h00; - parameter [47:0] EMAC0_PAUSEADDR = 48'h000000000000; - parameter [47:0] EMAC0_UNICASTADDR = 48'h000000000000; - parameter [47:0] EMAC1_PAUSEADDR = 48'h000000000000; - parameter [47:0] EMAC1_UNICASTADDR = 48'h000000000000; - parameter [8:0] EMAC0_LINKTIMERVAL = 9'h000; - parameter [8:0] EMAC1_LINKTIMERVAL = 9'h000; - output DCRHOSTDONEIR; - output EMAC0CLIENTANINTERRUPT; - output EMAC0CLIENTRXBADFRAME; - output EMAC0CLIENTRXCLIENTCLKOUT; - output EMAC0CLIENTRXDVLD; - output EMAC0CLIENTRXDVLDMSW; - output EMAC0CLIENTRXFRAMEDROP; - output EMAC0CLIENTRXGOODFRAME; - output EMAC0CLIENTRXSTATSBYTEVLD; - output EMAC0CLIENTRXSTATSVLD; - output EMAC0CLIENTTXACK; - output EMAC0CLIENTTXCLIENTCLKOUT; - output EMAC0CLIENTTXCOLLISION; - output EMAC0CLIENTTXRETRANSMIT; - output EMAC0CLIENTTXSTATS; - output EMAC0CLIENTTXSTATSBYTEVLD; - output EMAC0CLIENTTXSTATSVLD; - output EMAC0PHYENCOMMAALIGN; - output EMAC0PHYLOOPBACKMSB; - output EMAC0PHYMCLKOUT; - output EMAC0PHYMDOUT; - output EMAC0PHYMDTRI; - output EMAC0PHYMGTRXRESET; - output EMAC0PHYMGTTXRESET; - output EMAC0PHYPOWERDOWN; - output EMAC0PHYSYNCACQSTATUS; - output EMAC0PHYTXCHARDISPMODE; - output EMAC0PHYTXCHARDISPVAL; - output EMAC0PHYTXCHARISK; - output EMAC0PHYTXCLK; - output EMAC0PHYTXEN; - output EMAC0PHYTXER; - output EMAC0PHYTXGMIIMIICLKOUT; - output EMAC0SPEEDIS10100; - output EMAC1CLIENTANINTERRUPT; - output EMAC1CLIENTRXBADFRAME; - output EMAC1CLIENTRXCLIENTCLKOUT; - output EMAC1CLIENTRXDVLD; - output EMAC1CLIENTRXDVLDMSW; - output EMAC1CLIENTRXFRAMEDROP; - output EMAC1CLIENTRXGOODFRAME; - output EMAC1CLIENTRXSTATSBYTEVLD; - output EMAC1CLIENTRXSTATSVLD; - output EMAC1CLIENTTXACK; - output EMAC1CLIENTTXCLIENTCLKOUT; - output EMAC1CLIENTTXCOLLISION; - output EMAC1CLIENTTXRETRANSMIT; - output EMAC1CLIENTTXSTATS; - output EMAC1CLIENTTXSTATSBYTEVLD; - output EMAC1CLIENTTXSTATSVLD; - output EMAC1PHYENCOMMAALIGN; - output EMAC1PHYLOOPBACKMSB; - output EMAC1PHYMCLKOUT; - output EMAC1PHYMDOUT; - output EMAC1PHYMDTRI; - output EMAC1PHYMGTRXRESET; - output EMAC1PHYMGTTXRESET; - output EMAC1PHYPOWERDOWN; - output EMAC1PHYSYNCACQSTATUS; - output EMAC1PHYTXCHARDISPMODE; - output EMAC1PHYTXCHARDISPVAL; - output EMAC1PHYTXCHARISK; - output EMAC1PHYTXCLK; - output EMAC1PHYTXEN; - output EMAC1PHYTXER; - output EMAC1PHYTXGMIIMIICLKOUT; - output EMAC1SPEEDIS10100; - output EMACDCRACK; - output HOSTMIIMRDY; - output [0:31] EMACDCRDBUS; - output [15:0] EMAC0CLIENTRXD; - output [15:0] EMAC1CLIENTRXD; - output [31:0] HOSTRDDATA; - output [6:0] EMAC0CLIENTRXSTATS; - output [6:0] EMAC1CLIENTRXSTATS; - output [7:0] EMAC0PHYTXD; - output [7:0] EMAC1PHYTXD; - input CLIENTEMAC0DCMLOCKED; - input CLIENTEMAC0PAUSEREQ; - input CLIENTEMAC0RXCLIENTCLKIN; - input CLIENTEMAC0TXCLIENTCLKIN; - input CLIENTEMAC0TXDVLD; - input CLIENTEMAC0TXDVLDMSW; - input CLIENTEMAC0TXFIRSTBYTE; - input CLIENTEMAC0TXUNDERRUN; - input CLIENTEMAC1DCMLOCKED; - input CLIENTEMAC1PAUSEREQ; - input CLIENTEMAC1RXCLIENTCLKIN; - input CLIENTEMAC1TXCLIENTCLKIN; - input CLIENTEMAC1TXDVLD; - input CLIENTEMAC1TXDVLDMSW; - input CLIENTEMAC1TXFIRSTBYTE; - input CLIENTEMAC1TXUNDERRUN; - input DCREMACCLK; - input DCREMACENABLE; - input DCREMACREAD; - input DCREMACWRITE; - input HOSTCLK; - input HOSTEMAC1SEL; - input HOSTMIIMSEL; - input HOSTREQ; - input PHYEMAC0COL; - input PHYEMAC0CRS; - input PHYEMAC0GTXCLK; - input PHYEMAC0MCLKIN; - input PHYEMAC0MDIN; - input PHYEMAC0MIITXCLK; - input PHYEMAC0RXBUFERR; - input PHYEMAC0RXCHARISCOMMA; - input PHYEMAC0RXCHARISK; - input PHYEMAC0RXCHECKINGCRC; - input PHYEMAC0RXCLK; - input PHYEMAC0RXCOMMADET; - input PHYEMAC0RXDISPERR; - input PHYEMAC0RXDV; - input PHYEMAC0RXER; - input PHYEMAC0RXNOTINTABLE; - input PHYEMAC0RXRUNDISP; - input PHYEMAC0SIGNALDET; - input PHYEMAC0TXBUFERR; - input PHYEMAC0TXGMIIMIICLKIN; - input PHYEMAC1COL; - input PHYEMAC1CRS; - input PHYEMAC1GTXCLK; - input PHYEMAC1MCLKIN; - input PHYEMAC1MDIN; - input PHYEMAC1MIITXCLK; - input PHYEMAC1RXBUFERR; - input PHYEMAC1RXCHARISCOMMA; - input PHYEMAC1RXCHARISK; - input PHYEMAC1RXCHECKINGCRC; - input PHYEMAC1RXCLK; - input PHYEMAC1RXCOMMADET; - input PHYEMAC1RXDISPERR; - input PHYEMAC1RXDV; - input PHYEMAC1RXER; - input PHYEMAC1RXNOTINTABLE; - input PHYEMAC1RXRUNDISP; - input PHYEMAC1SIGNALDET; - input PHYEMAC1TXBUFERR; - input PHYEMAC1TXGMIIMIICLKIN; - input RESET; - input [0:31] DCREMACDBUS; - input [0:9] DCREMACABUS; - input [15:0] CLIENTEMAC0PAUSEVAL; - input [15:0] CLIENTEMAC0TXD; - input [15:0] CLIENTEMAC1PAUSEVAL; - input [15:0] CLIENTEMAC1TXD; - input [1:0] HOSTOPCODE; - input [1:0] PHYEMAC0RXBUFSTATUS; - input [1:0] PHYEMAC0RXLOSSOFSYNC; - input [1:0] PHYEMAC1RXBUFSTATUS; - input [1:0] PHYEMAC1RXLOSSOFSYNC; - input [2:0] PHYEMAC0RXCLKCORCNT; - input [2:0] PHYEMAC1RXCLKCORCNT; - input [31:0] HOSTWRDATA; - input [4:0] PHYEMAC0PHYAD; - input [4:0] PHYEMAC1PHYAD; - input [7:0] CLIENTEMAC0TXIFGDELAY; - input [7:0] CLIENTEMAC1TXIFGDELAY; - input [7:0] PHYEMAC0RXD; - input [7:0] PHYEMAC1RXD; - input [9:0] HOSTADDR; -endmodule - -module TEMAC_SINGLE (...); - parameter EMAC_1000BASEX_ENABLE = "FALSE"; - parameter EMAC_ADDRFILTER_ENABLE = "FALSE"; - parameter EMAC_BYTEPHY = "FALSE"; - parameter EMAC_CTRLLENCHECK_DISABLE = "FALSE"; - parameter [0:7] EMAC_DCRBASEADDR = 8'h00; - parameter EMAC_GTLOOPBACK = "FALSE"; - parameter EMAC_HOST_ENABLE = "FALSE"; - parameter [8:0] EMAC_LINKTIMERVAL = 9'h000; - parameter EMAC_LTCHECK_DISABLE = "FALSE"; - parameter EMAC_MDIO_ENABLE = "FALSE"; - parameter EMAC_MDIO_IGNORE_PHYADZERO = "FALSE"; - parameter [47:0] EMAC_PAUSEADDR = 48'h000000000000; - parameter EMAC_PHYINITAUTONEG_ENABLE = "FALSE"; - parameter EMAC_PHYISOLATE = "FALSE"; - parameter EMAC_PHYLOOPBACKMSB = "FALSE"; - parameter EMAC_PHYPOWERDOWN = "FALSE"; - parameter EMAC_PHYRESET = "FALSE"; - parameter EMAC_RGMII_ENABLE = "FALSE"; - parameter EMAC_RX16BITCLIENT_ENABLE = "FALSE"; - parameter EMAC_RXFLOWCTRL_ENABLE = "FALSE"; - parameter EMAC_RXHALFDUPLEX = "FALSE"; - parameter EMAC_RXINBANDFCS_ENABLE = "FALSE"; - parameter EMAC_RXJUMBOFRAME_ENABLE = "FALSE"; - parameter EMAC_RXRESET = "FALSE"; - parameter EMAC_RXVLAN_ENABLE = "FALSE"; - parameter EMAC_RX_ENABLE = "TRUE"; - parameter EMAC_SGMII_ENABLE = "FALSE"; - parameter EMAC_SPEED_LSB = "FALSE"; - parameter EMAC_SPEED_MSB = "FALSE"; - parameter EMAC_TX16BITCLIENT_ENABLE = "FALSE"; - parameter EMAC_TXFLOWCTRL_ENABLE = "FALSE"; - parameter EMAC_TXHALFDUPLEX = "FALSE"; - parameter EMAC_TXIFGADJUST_ENABLE = "FALSE"; - parameter EMAC_TXINBANDFCS_ENABLE = "FALSE"; - parameter EMAC_TXJUMBOFRAME_ENABLE = "FALSE"; - parameter EMAC_TXRESET = "FALSE"; - parameter EMAC_TXVLAN_ENABLE = "FALSE"; - parameter EMAC_TX_ENABLE = "TRUE"; - parameter [47:0] EMAC_UNICASTADDR = 48'h000000000000; - parameter EMAC_UNIDIRECTION_ENABLE = "FALSE"; - parameter EMAC_USECLKEN = "FALSE"; - parameter SIM_VERSION = "1.0"; - output DCRHOSTDONEIR; - output EMACCLIENTANINTERRUPT; - output EMACCLIENTRXBADFRAME; - output EMACCLIENTRXCLIENTCLKOUT; - output EMACCLIENTRXDVLD; - output EMACCLIENTRXDVLDMSW; - output EMACCLIENTRXFRAMEDROP; - output EMACCLIENTRXGOODFRAME; - output EMACCLIENTRXSTATSBYTEVLD; - output EMACCLIENTRXSTATSVLD; - output EMACCLIENTTXACK; - output EMACCLIENTTXCLIENTCLKOUT; - output EMACCLIENTTXCOLLISION; - output EMACCLIENTTXRETRANSMIT; - output EMACCLIENTTXSTATS; - output EMACCLIENTTXSTATSBYTEVLD; - output EMACCLIENTTXSTATSVLD; - output EMACDCRACK; - output EMACPHYENCOMMAALIGN; - output EMACPHYLOOPBACKMSB; - output EMACPHYMCLKOUT; - output EMACPHYMDOUT; - output EMACPHYMDTRI; - output EMACPHYMGTRXRESET; - output EMACPHYMGTTXRESET; - output EMACPHYPOWERDOWN; - output EMACPHYSYNCACQSTATUS; - output EMACPHYTXCHARDISPMODE; - output EMACPHYTXCHARDISPVAL; - output EMACPHYTXCHARISK; - output EMACPHYTXCLK; - output EMACPHYTXEN; - output EMACPHYTXER; - output EMACPHYTXGMIIMIICLKOUT; - output EMACSPEEDIS10100; - output HOSTMIIMRDY; - output [0:31] EMACDCRDBUS; - output [15:0] EMACCLIENTRXD; - output [31:0] HOSTRDDATA; - output [6:0] EMACCLIENTRXSTATS; - output [7:0] EMACPHYTXD; - input CLIENTEMACDCMLOCKED; - input CLIENTEMACPAUSEREQ; - input CLIENTEMACRXCLIENTCLKIN; - input CLIENTEMACTXCLIENTCLKIN; - input CLIENTEMACTXDVLD; - input CLIENTEMACTXDVLDMSW; - input CLIENTEMACTXFIRSTBYTE; - input CLIENTEMACTXUNDERRUN; - input DCREMACCLK; - input DCREMACENABLE; - input DCREMACREAD; - input DCREMACWRITE; - input HOSTCLK; - input HOSTMIIMSEL; - input HOSTREQ; - input PHYEMACCOL; - input PHYEMACCRS; - input PHYEMACGTXCLK; - input PHYEMACMCLKIN; - input PHYEMACMDIN; - input PHYEMACMIITXCLK; - input PHYEMACRXCHARISCOMMA; - input PHYEMACRXCHARISK; - input PHYEMACRXCLK; - input PHYEMACRXDISPERR; - input PHYEMACRXDV; - input PHYEMACRXER; - input PHYEMACRXNOTINTABLE; - input PHYEMACRXRUNDISP; - input PHYEMACSIGNALDET; - input PHYEMACTXBUFERR; - input PHYEMACTXGMIIMIICLKIN; - input RESET; - input [0:31] DCREMACDBUS; - input [0:9] DCREMACABUS; - input [15:0] CLIENTEMACPAUSEVAL; - input [15:0] CLIENTEMACTXD; - input [1:0] HOSTOPCODE; - input [1:0] PHYEMACRXBUFSTATUS; - input [2:0] PHYEMACRXCLKCORCNT; - input [31:0] HOSTWRDATA; - input [4:0] PHYEMACPHYAD; - input [7:0] CLIENTEMACTXIFGDELAY; - input [7:0] PHYEMACRXD; - input [9:0] HOSTADDR; -endmodule - -module CMAC (...); - parameter CTL_PTP_TRANSPCLK_MODE = "FALSE"; - parameter CTL_RX_CHECK_ACK = "TRUE"; - parameter CTL_RX_CHECK_PREAMBLE = "FALSE"; - parameter CTL_RX_CHECK_SFD = "FALSE"; - parameter CTL_RX_DELETE_FCS = "TRUE"; - parameter [15:0] CTL_RX_ETYPE_GCP = 16'h8808; - parameter [15:0] CTL_RX_ETYPE_GPP = 16'h8808; - parameter [15:0] CTL_RX_ETYPE_PCP = 16'h8808; - parameter [15:0] CTL_RX_ETYPE_PPP = 16'h8808; - parameter CTL_RX_FORWARD_CONTROL = "FALSE"; - parameter CTL_RX_IGNORE_FCS = "FALSE"; - parameter [14:0] CTL_RX_MAX_PACKET_LEN = 15'h2580; - parameter [7:0] CTL_RX_MIN_PACKET_LEN = 8'h40; - parameter [15:0] CTL_RX_OPCODE_GPP = 16'h0001; - parameter [15:0] CTL_RX_OPCODE_MAX_GCP = 16'hFFFF; - parameter [15:0] CTL_RX_OPCODE_MAX_PCP = 16'hFFFF; - parameter [15:0] CTL_RX_OPCODE_MIN_GCP = 16'h0000; - parameter [15:0] CTL_RX_OPCODE_MIN_PCP = 16'h0000; - parameter [15:0] CTL_RX_OPCODE_PPP = 16'h0001; - parameter [47:0] CTL_RX_PAUSE_DA_MCAST = 48'h0180C2000001; - parameter [47:0] CTL_RX_PAUSE_DA_UCAST = 48'h000000000000; - parameter [47:0] CTL_RX_PAUSE_SA = 48'h000000000000; - parameter CTL_RX_PROCESS_LFI = "FALSE"; - parameter [15:0] CTL_RX_VL_LENGTH_MINUS1 = 16'h3FFF; - parameter [63:0] CTL_RX_VL_MARKER_ID0 = 64'hC16821003E97DE00; - parameter [63:0] CTL_RX_VL_MARKER_ID1 = 64'h9D718E00628E7100; - parameter [63:0] CTL_RX_VL_MARKER_ID10 = 64'hFD6C990002936600; - parameter [63:0] CTL_RX_VL_MARKER_ID11 = 64'hB9915500466EAA00; - parameter [63:0] CTL_RX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00; - parameter [63:0] CTL_RX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200; - parameter [63:0] CTL_RX_VL_MARKER_ID14 = 64'h83C7CA007C383500; - parameter [63:0] CTL_RX_VL_MARKER_ID15 = 64'h3536CD00CAC93200; - parameter [63:0] CTL_RX_VL_MARKER_ID16 = 64'hC4314C003BCEB300; - parameter [63:0] CTL_RX_VL_MARKER_ID17 = 64'hADD6B70052294800; - parameter [63:0] CTL_RX_VL_MARKER_ID18 = 64'h5F662A00A099D500; - parameter [63:0] CTL_RX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00; - parameter [63:0] CTL_RX_VL_MARKER_ID2 = 64'h594BE800A6B41700; - parameter [63:0] CTL_RX_VL_MARKER_ID3 = 64'h4D957B00B26A8400; - parameter [63:0] CTL_RX_VL_MARKER_ID4 = 64'hF50709000AF8F600; - parameter [63:0] CTL_RX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00; - parameter [63:0] CTL_RX_VL_MARKER_ID6 = 64'h9A4A260065B5D900; - parameter [63:0] CTL_RX_VL_MARKER_ID7 = 64'h7B45660084BA9900; - parameter [63:0] CTL_RX_VL_MARKER_ID8 = 64'hA02476005FDB8900; - parameter [63:0] CTL_RX_VL_MARKER_ID9 = 64'h68C9FB0097360400; - parameter CTL_TEST_MODE_PIN_CHAR = "FALSE"; - parameter [47:0] CTL_TX_DA_GPP = 48'h0180C2000001; - parameter [47:0] CTL_TX_DA_PPP = 48'h0180C2000001; - parameter [15:0] CTL_TX_ETHERTYPE_GPP = 16'h8808; - parameter [15:0] CTL_TX_ETHERTYPE_PPP = 16'h8808; - parameter CTL_TX_FCS_INS_ENABLE = "TRUE"; - parameter CTL_TX_IGNORE_FCS = "FALSE"; - parameter [15:0] CTL_TX_OPCODE_GPP = 16'h0001; - parameter [15:0] CTL_TX_OPCODE_PPP = 16'h0001; - parameter CTL_TX_PTP_1STEP_ENABLE = "FALSE"; - parameter [10:0] CTL_TX_PTP_LATENCY_ADJUST = 11'h2C1; - parameter [47:0] CTL_TX_SA_GPP = 48'h000000000000; - parameter [47:0] CTL_TX_SA_PPP = 48'h000000000000; - parameter [15:0] CTL_TX_VL_LENGTH_MINUS1 = 16'h3FFF; - parameter [63:0] CTL_TX_VL_MARKER_ID0 = 64'hC16821003E97DE00; - parameter [63:0] CTL_TX_VL_MARKER_ID1 = 64'h9D718E00628E7100; - parameter [63:0] CTL_TX_VL_MARKER_ID10 = 64'hFD6C990002936600; - parameter [63:0] CTL_TX_VL_MARKER_ID11 = 64'hB9915500466EAA00; - parameter [63:0] CTL_TX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00; - parameter [63:0] CTL_TX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200; - parameter [63:0] CTL_TX_VL_MARKER_ID14 = 64'h83C7CA007C383500; - parameter [63:0] CTL_TX_VL_MARKER_ID15 = 64'h3536CD00CAC93200; - parameter [63:0] CTL_TX_VL_MARKER_ID16 = 64'hC4314C003BCEB300; - parameter [63:0] CTL_TX_VL_MARKER_ID17 = 64'hADD6B70052294800; - parameter [63:0] CTL_TX_VL_MARKER_ID18 = 64'h5F662A00A099D500; - parameter [63:0] CTL_TX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00; - parameter [63:0] CTL_TX_VL_MARKER_ID2 = 64'h594BE800A6B41700; - parameter [63:0] CTL_TX_VL_MARKER_ID3 = 64'h4D957B00B26A8400; - parameter [63:0] CTL_TX_VL_MARKER_ID4 = 64'hF50709000AF8F600; - parameter [63:0] CTL_TX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00; - parameter [63:0] CTL_TX_VL_MARKER_ID6 = 64'h9A4A260065B5D900; - parameter [63:0] CTL_TX_VL_MARKER_ID7 = 64'h7B45660084BA9900; - parameter [63:0] CTL_TX_VL_MARKER_ID8 = 64'hA02476005FDB8900; - parameter [63:0] CTL_TX_VL_MARKER_ID9 = 64'h68C9FB0097360400; - parameter SIM_VERSION = "2.0"; - parameter TEST_MODE_PIN_CHAR = "FALSE"; - output [15:0] DRP_DO; - output DRP_RDY; - output [127:0] RX_DATAOUT0; - output [127:0] RX_DATAOUT1; - output [127:0] RX_DATAOUT2; - output [127:0] RX_DATAOUT3; - output RX_ENAOUT0; - output RX_ENAOUT1; - output RX_ENAOUT2; - output RX_ENAOUT3; - output RX_EOPOUT0; - output RX_EOPOUT1; - output RX_EOPOUT2; - output RX_EOPOUT3; - output RX_ERROUT0; - output RX_ERROUT1; - output RX_ERROUT2; - output RX_ERROUT3; - output [6:0] RX_LANE_ALIGNER_FILL_0; - output [6:0] RX_LANE_ALIGNER_FILL_1; - output [6:0] RX_LANE_ALIGNER_FILL_10; - output [6:0] RX_LANE_ALIGNER_FILL_11; - output [6:0] RX_LANE_ALIGNER_FILL_12; - output [6:0] RX_LANE_ALIGNER_FILL_13; - output [6:0] RX_LANE_ALIGNER_FILL_14; - output [6:0] RX_LANE_ALIGNER_FILL_15; - output [6:0] RX_LANE_ALIGNER_FILL_16; - output [6:0] RX_LANE_ALIGNER_FILL_17; - output [6:0] RX_LANE_ALIGNER_FILL_18; - output [6:0] RX_LANE_ALIGNER_FILL_19; - output [6:0] RX_LANE_ALIGNER_FILL_2; - output [6:0] RX_LANE_ALIGNER_FILL_3; - output [6:0] RX_LANE_ALIGNER_FILL_4; - output [6:0] RX_LANE_ALIGNER_FILL_5; - output [6:0] RX_LANE_ALIGNER_FILL_6; - output [6:0] RX_LANE_ALIGNER_FILL_7; - output [6:0] RX_LANE_ALIGNER_FILL_8; - output [6:0] RX_LANE_ALIGNER_FILL_9; - output [3:0] RX_MTYOUT0; - output [3:0] RX_MTYOUT1; - output [3:0] RX_MTYOUT2; - output [3:0] RX_MTYOUT3; - output [4:0] RX_PTP_PCSLANE_OUT; - output [79:0] RX_PTP_TSTAMP_OUT; - output RX_SOPOUT0; - output RX_SOPOUT1; - output RX_SOPOUT2; - output RX_SOPOUT3; - output STAT_RX_ALIGNED; - output STAT_RX_ALIGNED_ERR; - output [6:0] STAT_RX_BAD_CODE; - output [3:0] STAT_RX_BAD_FCS; - output STAT_RX_BAD_PREAMBLE; - output STAT_RX_BAD_SFD; - output STAT_RX_BIP_ERR_0; - output STAT_RX_BIP_ERR_1; - output STAT_RX_BIP_ERR_10; - output STAT_RX_BIP_ERR_11; - output STAT_RX_BIP_ERR_12; - output STAT_RX_BIP_ERR_13; - output STAT_RX_BIP_ERR_14; - output STAT_RX_BIP_ERR_15; - output STAT_RX_BIP_ERR_16; - output STAT_RX_BIP_ERR_17; - output STAT_RX_BIP_ERR_18; - output STAT_RX_BIP_ERR_19; - output STAT_RX_BIP_ERR_2; - output STAT_RX_BIP_ERR_3; - output STAT_RX_BIP_ERR_4; - output STAT_RX_BIP_ERR_5; - output STAT_RX_BIP_ERR_6; - output STAT_RX_BIP_ERR_7; - output STAT_RX_BIP_ERR_8; - output STAT_RX_BIP_ERR_9; - output [19:0] STAT_RX_BLOCK_LOCK; - output STAT_RX_BROADCAST; - output [3:0] STAT_RX_FRAGMENT; - output [3:0] STAT_RX_FRAMING_ERR_0; - output [3:0] STAT_RX_FRAMING_ERR_1; - output [3:0] STAT_RX_FRAMING_ERR_10; - output [3:0] STAT_RX_FRAMING_ERR_11; - output [3:0] STAT_RX_FRAMING_ERR_12; - output [3:0] STAT_RX_FRAMING_ERR_13; - output [3:0] STAT_RX_FRAMING_ERR_14; - output [3:0] STAT_RX_FRAMING_ERR_15; - output [3:0] STAT_RX_FRAMING_ERR_16; - output [3:0] STAT_RX_FRAMING_ERR_17; - output [3:0] STAT_RX_FRAMING_ERR_18; - output [3:0] STAT_RX_FRAMING_ERR_19; - output [3:0] STAT_RX_FRAMING_ERR_2; - output [3:0] STAT_RX_FRAMING_ERR_3; - output [3:0] STAT_RX_FRAMING_ERR_4; - output [3:0] STAT_RX_FRAMING_ERR_5; - output [3:0] STAT_RX_FRAMING_ERR_6; - output [3:0] STAT_RX_FRAMING_ERR_7; - output [3:0] STAT_RX_FRAMING_ERR_8; - output [3:0] STAT_RX_FRAMING_ERR_9; - output STAT_RX_FRAMING_ERR_VALID_0; - output STAT_RX_FRAMING_ERR_VALID_1; - output STAT_RX_FRAMING_ERR_VALID_10; - output STAT_RX_FRAMING_ERR_VALID_11; - output STAT_RX_FRAMING_ERR_VALID_12; - output STAT_RX_FRAMING_ERR_VALID_13; - output STAT_RX_FRAMING_ERR_VALID_14; - output STAT_RX_FRAMING_ERR_VALID_15; - output STAT_RX_FRAMING_ERR_VALID_16; - output STAT_RX_FRAMING_ERR_VALID_17; - output STAT_RX_FRAMING_ERR_VALID_18; - output STAT_RX_FRAMING_ERR_VALID_19; - output STAT_RX_FRAMING_ERR_VALID_2; - output STAT_RX_FRAMING_ERR_VALID_3; - output STAT_RX_FRAMING_ERR_VALID_4; - output STAT_RX_FRAMING_ERR_VALID_5; - output STAT_RX_FRAMING_ERR_VALID_6; - output STAT_RX_FRAMING_ERR_VALID_7; - output STAT_RX_FRAMING_ERR_VALID_8; - output STAT_RX_FRAMING_ERR_VALID_9; - output STAT_RX_GOT_SIGNAL_OS; - output STAT_RX_HI_BER; - output STAT_RX_INRANGEERR; - output STAT_RX_INTERNAL_LOCAL_FAULT; - output STAT_RX_JABBER; - output [7:0] STAT_RX_LANE0_VLM_BIP7; - output STAT_RX_LANE0_VLM_BIP7_VALID; - output STAT_RX_LOCAL_FAULT; - output [19:0] STAT_RX_MF_ERR; - output [19:0] STAT_RX_MF_LEN_ERR; - output [19:0] STAT_RX_MF_REPEAT_ERR; - output STAT_RX_MISALIGNED; - output STAT_RX_MULTICAST; - output STAT_RX_OVERSIZE; - output STAT_RX_PACKET_1024_1518_BYTES; - output STAT_RX_PACKET_128_255_BYTES; - output STAT_RX_PACKET_1519_1522_BYTES; - output STAT_RX_PACKET_1523_1548_BYTES; - output STAT_RX_PACKET_1549_2047_BYTES; - output STAT_RX_PACKET_2048_4095_BYTES; - output STAT_RX_PACKET_256_511_BYTES; - output STAT_RX_PACKET_4096_8191_BYTES; - output STAT_RX_PACKET_512_1023_BYTES; - output STAT_RX_PACKET_64_BYTES; - output STAT_RX_PACKET_65_127_BYTES; - output STAT_RX_PACKET_8192_9215_BYTES; - output STAT_RX_PACKET_BAD_FCS; - output STAT_RX_PACKET_LARGE; - output [3:0] STAT_RX_PACKET_SMALL; - output STAT_RX_PAUSE; - output [15:0] STAT_RX_PAUSE_QUANTA0; - output [15:0] STAT_RX_PAUSE_QUANTA1; - output [15:0] STAT_RX_PAUSE_QUANTA2; - output [15:0] STAT_RX_PAUSE_QUANTA3; - output [15:0] STAT_RX_PAUSE_QUANTA4; - output [15:0] STAT_RX_PAUSE_QUANTA5; - output [15:0] STAT_RX_PAUSE_QUANTA6; - output [15:0] STAT_RX_PAUSE_QUANTA7; - output [15:0] STAT_RX_PAUSE_QUANTA8; - output [8:0] STAT_RX_PAUSE_REQ; - output [8:0] STAT_RX_PAUSE_VALID; - output STAT_RX_RECEIVED_LOCAL_FAULT; - output STAT_RX_REMOTE_FAULT; - output STAT_RX_STATUS; - output [3:0] STAT_RX_STOMPED_FCS; - output [19:0] STAT_RX_SYNCED; - output [19:0] STAT_RX_SYNCED_ERR; - output [2:0] STAT_RX_TEST_PATTERN_MISMATCH; - output STAT_RX_TOOLONG; - output [7:0] STAT_RX_TOTAL_BYTES; - output [13:0] STAT_RX_TOTAL_GOOD_BYTES; - output STAT_RX_TOTAL_GOOD_PACKETS; - output [3:0] STAT_RX_TOTAL_PACKETS; - output STAT_RX_TRUNCATED; - output [3:0] STAT_RX_UNDERSIZE; - output STAT_RX_UNICAST; - output STAT_RX_USER_PAUSE; - output STAT_RX_VLAN; - output [19:0] STAT_RX_VL_DEMUXED; - output [4:0] STAT_RX_VL_NUMBER_0; - output [4:0] STAT_RX_VL_NUMBER_1; - output [4:0] STAT_RX_VL_NUMBER_10; - output [4:0] STAT_RX_VL_NUMBER_11; - output [4:0] STAT_RX_VL_NUMBER_12; - output [4:0] STAT_RX_VL_NUMBER_13; - output [4:0] STAT_RX_VL_NUMBER_14; - output [4:0] STAT_RX_VL_NUMBER_15; - output [4:0] STAT_RX_VL_NUMBER_16; - output [4:0] STAT_RX_VL_NUMBER_17; - output [4:0] STAT_RX_VL_NUMBER_18; - output [4:0] STAT_RX_VL_NUMBER_19; - output [4:0] STAT_RX_VL_NUMBER_2; - output [4:0] STAT_RX_VL_NUMBER_3; - output [4:0] STAT_RX_VL_NUMBER_4; - output [4:0] STAT_RX_VL_NUMBER_5; - output [4:0] STAT_RX_VL_NUMBER_6; - output [4:0] STAT_RX_VL_NUMBER_7; - output [4:0] STAT_RX_VL_NUMBER_8; - output [4:0] STAT_RX_VL_NUMBER_9; - output STAT_TX_BAD_FCS; - output STAT_TX_BROADCAST; - output STAT_TX_FRAME_ERROR; - output STAT_TX_LOCAL_FAULT; - output STAT_TX_MULTICAST; - output STAT_TX_PACKET_1024_1518_BYTES; - output STAT_TX_PACKET_128_255_BYTES; - output STAT_TX_PACKET_1519_1522_BYTES; - output STAT_TX_PACKET_1523_1548_BYTES; - output STAT_TX_PACKET_1549_2047_BYTES; - output STAT_TX_PACKET_2048_4095_BYTES; - output STAT_TX_PACKET_256_511_BYTES; - output STAT_TX_PACKET_4096_8191_BYTES; - output STAT_TX_PACKET_512_1023_BYTES; - output STAT_TX_PACKET_64_BYTES; - output STAT_TX_PACKET_65_127_BYTES; - output STAT_TX_PACKET_8192_9215_BYTES; - output STAT_TX_PACKET_LARGE; - output STAT_TX_PACKET_SMALL; - output STAT_TX_PAUSE; - output [8:0] STAT_TX_PAUSE_VALID; - output STAT_TX_PTP_FIFO_READ_ERROR; - output STAT_TX_PTP_FIFO_WRITE_ERROR; - output [6:0] STAT_TX_TOTAL_BYTES; - output [13:0] STAT_TX_TOTAL_GOOD_BYTES; - output STAT_TX_TOTAL_GOOD_PACKETS; - output STAT_TX_TOTAL_PACKETS; - output STAT_TX_UNICAST; - output STAT_TX_USER_PAUSE; - output STAT_TX_VLAN; - output TX_OVFOUT; - output [4:0] TX_PTP_PCSLANE_OUT; - output [79:0] TX_PTP_TSTAMP_OUT; - output [15:0] TX_PTP_TSTAMP_TAG_OUT; - output TX_PTP_TSTAMP_VALID_OUT; - output TX_RDYOUT; - output [15:0] TX_SERDES_ALT_DATA0; - output [15:0] TX_SERDES_ALT_DATA1; - output [15:0] TX_SERDES_ALT_DATA2; - output [15:0] TX_SERDES_ALT_DATA3; - output [63:0] TX_SERDES_DATA0; - output [63:0] TX_SERDES_DATA1; - output [63:0] TX_SERDES_DATA2; - output [63:0] TX_SERDES_DATA3; - output [31:0] TX_SERDES_DATA4; - output [31:0] TX_SERDES_DATA5; - output [31:0] TX_SERDES_DATA6; - output [31:0] TX_SERDES_DATA7; - output [31:0] TX_SERDES_DATA8; - output [31:0] TX_SERDES_DATA9; - output TX_UNFOUT; - input CTL_CAUI4_MODE; - input CTL_RX_CHECK_ETYPE_GCP; - input CTL_RX_CHECK_ETYPE_GPP; - input CTL_RX_CHECK_ETYPE_PCP; - input CTL_RX_CHECK_ETYPE_PPP; - input CTL_RX_CHECK_MCAST_GCP; - input CTL_RX_CHECK_MCAST_GPP; - input CTL_RX_CHECK_MCAST_PCP; - input CTL_RX_CHECK_MCAST_PPP; - input CTL_RX_CHECK_OPCODE_GCP; - input CTL_RX_CHECK_OPCODE_GPP; - input CTL_RX_CHECK_OPCODE_PCP; - input CTL_RX_CHECK_OPCODE_PPP; - input CTL_RX_CHECK_SA_GCP; - input CTL_RX_CHECK_SA_GPP; - input CTL_RX_CHECK_SA_PCP; - input CTL_RX_CHECK_SA_PPP; - input CTL_RX_CHECK_UCAST_GCP; - input CTL_RX_CHECK_UCAST_GPP; - input CTL_RX_CHECK_UCAST_PCP; - input CTL_RX_CHECK_UCAST_PPP; - input CTL_RX_ENABLE; - input CTL_RX_ENABLE_GCP; - input CTL_RX_ENABLE_GPP; - input CTL_RX_ENABLE_PCP; - input CTL_RX_ENABLE_PPP; - input CTL_RX_FORCE_RESYNC; - input [8:0] CTL_RX_PAUSE_ACK; - input [8:0] CTL_RX_PAUSE_ENABLE; - input [79:0] CTL_RX_SYSTEMTIMERIN; - input CTL_RX_TEST_PATTERN; - input CTL_TX_ENABLE; - input CTL_TX_LANE0_VLM_BIP7_OVERRIDE; - input [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE; - input [8:0] CTL_TX_PAUSE_ENABLE; - input [15:0] CTL_TX_PAUSE_QUANTA0; - input [15:0] CTL_TX_PAUSE_QUANTA1; - input [15:0] CTL_TX_PAUSE_QUANTA2; - input [15:0] CTL_TX_PAUSE_QUANTA3; - input [15:0] CTL_TX_PAUSE_QUANTA4; - input [15:0] CTL_TX_PAUSE_QUANTA5; - input [15:0] CTL_TX_PAUSE_QUANTA6; - input [15:0] CTL_TX_PAUSE_QUANTA7; - input [15:0] CTL_TX_PAUSE_QUANTA8; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER0; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER1; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER2; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER3; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER4; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER5; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER6; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER7; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER8; - input [8:0] CTL_TX_PAUSE_REQ; - input CTL_TX_PTP_VLANE_ADJUST_MODE; - input CTL_TX_RESEND_PAUSE; - input CTL_TX_SEND_IDLE; - input CTL_TX_SEND_RFI; - input [79:0] CTL_TX_SYSTEMTIMERIN; - input CTL_TX_TEST_PATTERN; - input [9:0] DRP_ADDR; - input DRP_CLK; - input [15:0] DRP_DI; - input DRP_EN; - input DRP_WE; - input RX_CLK; - input RX_RESET; - input [15:0] RX_SERDES_ALT_DATA0; - input [15:0] RX_SERDES_ALT_DATA1; - input [15:0] RX_SERDES_ALT_DATA2; - input [15:0] RX_SERDES_ALT_DATA3; - input [9:0] RX_SERDES_CLK; - input [63:0] RX_SERDES_DATA0; - input [63:0] RX_SERDES_DATA1; - input [63:0] RX_SERDES_DATA2; - input [63:0] RX_SERDES_DATA3; - input [31:0] RX_SERDES_DATA4; - input [31:0] RX_SERDES_DATA5; - input [31:0] RX_SERDES_DATA6; - input [31:0] RX_SERDES_DATA7; - input [31:0] RX_SERDES_DATA8; - input [31:0] RX_SERDES_DATA9; - input [9:0] RX_SERDES_RESET; - input TX_CLK; - input [127:0] TX_DATAIN0; - input [127:0] TX_DATAIN1; - input [127:0] TX_DATAIN2; - input [127:0] TX_DATAIN3; - input TX_ENAIN0; - input TX_ENAIN1; - input TX_ENAIN2; - input TX_ENAIN3; - input TX_EOPIN0; - input TX_EOPIN1; - input TX_EOPIN2; - input TX_EOPIN3; - input TX_ERRIN0; - input TX_ERRIN1; - input TX_ERRIN2; - input TX_ERRIN3; - input [3:0] TX_MTYIN0; - input [3:0] TX_MTYIN1; - input [3:0] TX_MTYIN2; - input [3:0] TX_MTYIN3; - input [1:0] TX_PTP_1588OP_IN; - input [15:0] TX_PTP_CHKSUM_OFFSET_IN; - input [63:0] TX_PTP_RXTSTAMP_IN; - input [15:0] TX_PTP_TAG_FIELD_IN; - input [15:0] TX_PTP_TSTAMP_OFFSET_IN; - input TX_PTP_UPD_CHKSUM_IN; - input TX_RESET; - input TX_SOPIN0; - input TX_SOPIN1; - input TX_SOPIN2; - input TX_SOPIN3; -endmodule - -module CMACE4 (...); - parameter CTL_PTP_TRANSPCLK_MODE = "FALSE"; - parameter CTL_RX_CHECK_ACK = "TRUE"; - parameter CTL_RX_CHECK_PREAMBLE = "FALSE"; - parameter CTL_RX_CHECK_SFD = "FALSE"; - parameter CTL_RX_DELETE_FCS = "TRUE"; - parameter [15:0] CTL_RX_ETYPE_GCP = 16'h8808; - parameter [15:0] CTL_RX_ETYPE_GPP = 16'h8808; - parameter [15:0] CTL_RX_ETYPE_PCP = 16'h8808; - parameter [15:0] CTL_RX_ETYPE_PPP = 16'h8808; - parameter CTL_RX_FORWARD_CONTROL = "FALSE"; - parameter CTL_RX_IGNORE_FCS = "FALSE"; - parameter [14:0] CTL_RX_MAX_PACKET_LEN = 15'h2580; - parameter [7:0] CTL_RX_MIN_PACKET_LEN = 8'h40; - parameter [15:0] CTL_RX_OPCODE_GPP = 16'h0001; - parameter [15:0] CTL_RX_OPCODE_MAX_GCP = 16'hFFFF; - parameter [15:0] CTL_RX_OPCODE_MAX_PCP = 16'hFFFF; - parameter [15:0] CTL_RX_OPCODE_MIN_GCP = 16'h0000; - parameter [15:0] CTL_RX_OPCODE_MIN_PCP = 16'h0000; - parameter [15:0] CTL_RX_OPCODE_PPP = 16'h0001; - parameter [47:0] CTL_RX_PAUSE_DA_MCAST = 48'h0180C2000001; - parameter [47:0] CTL_RX_PAUSE_DA_UCAST = 48'h000000000000; - parameter [47:0] CTL_RX_PAUSE_SA = 48'h000000000000; - parameter CTL_RX_PROCESS_LFI = "FALSE"; - parameter [8:0] CTL_RX_RSFEC_AM_THRESHOLD = 9'h046; - parameter [1:0] CTL_RX_RSFEC_FILL_ADJUST = 2'h0; - parameter [15:0] CTL_RX_VL_LENGTH_MINUS1 = 16'h3FFF; - parameter [63:0] CTL_RX_VL_MARKER_ID0 = 64'hC16821003E97DE00; - parameter [63:0] CTL_RX_VL_MARKER_ID1 = 64'h9D718E00628E7100; - parameter [63:0] CTL_RX_VL_MARKER_ID10 = 64'hFD6C990002936600; - parameter [63:0] CTL_RX_VL_MARKER_ID11 = 64'hB9915500466EAA00; - parameter [63:0] CTL_RX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00; - parameter [63:0] CTL_RX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200; - parameter [63:0] CTL_RX_VL_MARKER_ID14 = 64'h83C7CA007C383500; - parameter [63:0] CTL_RX_VL_MARKER_ID15 = 64'h3536CD00CAC93200; - parameter [63:0] CTL_RX_VL_MARKER_ID16 = 64'hC4314C003BCEB300; - parameter [63:0] CTL_RX_VL_MARKER_ID17 = 64'hADD6B70052294800; - parameter [63:0] CTL_RX_VL_MARKER_ID18 = 64'h5F662A00A099D500; - parameter [63:0] CTL_RX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00; - parameter [63:0] CTL_RX_VL_MARKER_ID2 = 64'h594BE800A6B41700; - parameter [63:0] CTL_RX_VL_MARKER_ID3 = 64'h4D957B00B26A8400; - parameter [63:0] CTL_RX_VL_MARKER_ID4 = 64'hF50709000AF8F600; - parameter [63:0] CTL_RX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00; - parameter [63:0] CTL_RX_VL_MARKER_ID6 = 64'h9A4A260065B5D900; - parameter [63:0] CTL_RX_VL_MARKER_ID7 = 64'h7B45660084BA9900; - parameter [63:0] CTL_RX_VL_MARKER_ID8 = 64'hA02476005FDB8900; - parameter [63:0] CTL_RX_VL_MARKER_ID9 = 64'h68C9FB0097360400; - parameter CTL_TEST_MODE_PIN_CHAR = "FALSE"; - parameter CTL_TX_CUSTOM_PREAMBLE_ENABLE = "FALSE"; - parameter [47:0] CTL_TX_DA_GPP = 48'h0180C2000001; - parameter [47:0] CTL_TX_DA_PPP = 48'h0180C2000001; - parameter [15:0] CTL_TX_ETHERTYPE_GPP = 16'h8808; - parameter [15:0] CTL_TX_ETHERTYPE_PPP = 16'h8808; - parameter CTL_TX_FCS_INS_ENABLE = "TRUE"; - parameter CTL_TX_IGNORE_FCS = "FALSE"; - parameter [3:0] CTL_TX_IPG_VALUE = 4'hC; - parameter [15:0] CTL_TX_OPCODE_GPP = 16'h0001; - parameter [15:0] CTL_TX_OPCODE_PPP = 16'h0001; - parameter CTL_TX_PTP_1STEP_ENABLE = "FALSE"; - parameter [10:0] CTL_TX_PTP_LATENCY_ADJUST = 11'h2C1; - parameter [47:0] CTL_TX_SA_GPP = 48'h000000000000; - parameter [47:0] CTL_TX_SA_PPP = 48'h000000000000; - parameter [15:0] CTL_TX_VL_LENGTH_MINUS1 = 16'h3FFF; - parameter [63:0] CTL_TX_VL_MARKER_ID0 = 64'hC16821003E97DE00; - parameter [63:0] CTL_TX_VL_MARKER_ID1 = 64'h9D718E00628E7100; - parameter [63:0] CTL_TX_VL_MARKER_ID10 = 64'hFD6C990002936600; - parameter [63:0] CTL_TX_VL_MARKER_ID11 = 64'hB9915500466EAA00; - parameter [63:0] CTL_TX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00; - parameter [63:0] CTL_TX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200; - parameter [63:0] CTL_TX_VL_MARKER_ID14 = 64'h83C7CA007C383500; - parameter [63:0] CTL_TX_VL_MARKER_ID15 = 64'h3536CD00CAC93200; - parameter [63:0] CTL_TX_VL_MARKER_ID16 = 64'hC4314C003BCEB300; - parameter [63:0] CTL_TX_VL_MARKER_ID17 = 64'hADD6B70052294800; - parameter [63:0] CTL_TX_VL_MARKER_ID18 = 64'h5F662A00A099D500; - parameter [63:0] CTL_TX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00; - parameter [63:0] CTL_TX_VL_MARKER_ID2 = 64'h594BE800A6B41700; - parameter [63:0] CTL_TX_VL_MARKER_ID3 = 64'h4D957B00B26A8400; - parameter [63:0] CTL_TX_VL_MARKER_ID4 = 64'hF50709000AF8F600; - parameter [63:0] CTL_TX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00; - parameter [63:0] CTL_TX_VL_MARKER_ID6 = 64'h9A4A260065B5D900; - parameter [63:0] CTL_TX_VL_MARKER_ID7 = 64'h7B45660084BA9900; - parameter [63:0] CTL_TX_VL_MARKER_ID8 = 64'hA02476005FDB8900; - parameter [63:0] CTL_TX_VL_MARKER_ID9 = 64'h68C9FB0097360400; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter TEST_MODE_PIN_CHAR = "FALSE"; - output [15:0] DRP_DO; - output DRP_RDY; - output [329:0] RSFEC_BYPASS_RX_DOUT; - output RSFEC_BYPASS_RX_DOUT_CW_START; - output RSFEC_BYPASS_RX_DOUT_VALID; - output [329:0] RSFEC_BYPASS_TX_DOUT; - output RSFEC_BYPASS_TX_DOUT_CW_START; - output RSFEC_BYPASS_TX_DOUT_VALID; - output [127:0] RX_DATAOUT0; - output [127:0] RX_DATAOUT1; - output [127:0] RX_DATAOUT2; - output [127:0] RX_DATAOUT3; - output RX_ENAOUT0; - output RX_ENAOUT1; - output RX_ENAOUT2; - output RX_ENAOUT3; - output RX_EOPOUT0; - output RX_EOPOUT1; - output RX_EOPOUT2; - output RX_EOPOUT3; - output RX_ERROUT0; - output RX_ERROUT1; - output RX_ERROUT2; - output RX_ERROUT3; - output [6:0] RX_LANE_ALIGNER_FILL_0; - output [6:0] RX_LANE_ALIGNER_FILL_1; - output [6:0] RX_LANE_ALIGNER_FILL_10; - output [6:0] RX_LANE_ALIGNER_FILL_11; - output [6:0] RX_LANE_ALIGNER_FILL_12; - output [6:0] RX_LANE_ALIGNER_FILL_13; - output [6:0] RX_LANE_ALIGNER_FILL_14; - output [6:0] RX_LANE_ALIGNER_FILL_15; - output [6:0] RX_LANE_ALIGNER_FILL_16; - output [6:0] RX_LANE_ALIGNER_FILL_17; - output [6:0] RX_LANE_ALIGNER_FILL_18; - output [6:0] RX_LANE_ALIGNER_FILL_19; - output [6:0] RX_LANE_ALIGNER_FILL_2; - output [6:0] RX_LANE_ALIGNER_FILL_3; - output [6:0] RX_LANE_ALIGNER_FILL_4; - output [6:0] RX_LANE_ALIGNER_FILL_5; - output [6:0] RX_LANE_ALIGNER_FILL_6; - output [6:0] RX_LANE_ALIGNER_FILL_7; - output [6:0] RX_LANE_ALIGNER_FILL_8; - output [6:0] RX_LANE_ALIGNER_FILL_9; - output [3:0] RX_MTYOUT0; - output [3:0] RX_MTYOUT1; - output [3:0] RX_MTYOUT2; - output [3:0] RX_MTYOUT3; - output [7:0] RX_OTN_BIP8_0; - output [7:0] RX_OTN_BIP8_1; - output [7:0] RX_OTN_BIP8_2; - output [7:0] RX_OTN_BIP8_3; - output [7:0] RX_OTN_BIP8_4; - output [65:0] RX_OTN_DATA_0; - output [65:0] RX_OTN_DATA_1; - output [65:0] RX_OTN_DATA_2; - output [65:0] RX_OTN_DATA_3; - output [65:0] RX_OTN_DATA_4; - output RX_OTN_ENA; - output RX_OTN_LANE0; - output RX_OTN_VLMARKER; - output [55:0] RX_PREOUT; - output [4:0] RX_PTP_PCSLANE_OUT; - output [79:0] RX_PTP_TSTAMP_OUT; - output RX_SOPOUT0; - output RX_SOPOUT1; - output RX_SOPOUT2; - output RX_SOPOUT3; - output STAT_RX_ALIGNED; - output STAT_RX_ALIGNED_ERR; - output [2:0] STAT_RX_BAD_CODE; - output [2:0] STAT_RX_BAD_FCS; - output STAT_RX_BAD_PREAMBLE; - output STAT_RX_BAD_SFD; - output STAT_RX_BIP_ERR_0; - output STAT_RX_BIP_ERR_1; - output STAT_RX_BIP_ERR_10; - output STAT_RX_BIP_ERR_11; - output STAT_RX_BIP_ERR_12; - output STAT_RX_BIP_ERR_13; - output STAT_RX_BIP_ERR_14; - output STAT_RX_BIP_ERR_15; - output STAT_RX_BIP_ERR_16; - output STAT_RX_BIP_ERR_17; - output STAT_RX_BIP_ERR_18; - output STAT_RX_BIP_ERR_19; - output STAT_RX_BIP_ERR_2; - output STAT_RX_BIP_ERR_3; - output STAT_RX_BIP_ERR_4; - output STAT_RX_BIP_ERR_5; - output STAT_RX_BIP_ERR_6; - output STAT_RX_BIP_ERR_7; - output STAT_RX_BIP_ERR_8; - output STAT_RX_BIP_ERR_9; - output [19:0] STAT_RX_BLOCK_LOCK; - output STAT_RX_BROADCAST; - output [2:0] STAT_RX_FRAGMENT; - output [1:0] STAT_RX_FRAMING_ERR_0; - output [1:0] STAT_RX_FRAMING_ERR_1; - output [1:0] STAT_RX_FRAMING_ERR_10; - output [1:0] STAT_RX_FRAMING_ERR_11; - output [1:0] STAT_RX_FRAMING_ERR_12; - output [1:0] STAT_RX_FRAMING_ERR_13; - output [1:0] STAT_RX_FRAMING_ERR_14; - output [1:0] STAT_RX_FRAMING_ERR_15; - output [1:0] STAT_RX_FRAMING_ERR_16; - output [1:0] STAT_RX_FRAMING_ERR_17; - output [1:0] STAT_RX_FRAMING_ERR_18; - output [1:0] STAT_RX_FRAMING_ERR_19; - output [1:0] STAT_RX_FRAMING_ERR_2; - output [1:0] STAT_RX_FRAMING_ERR_3; - output [1:0] STAT_RX_FRAMING_ERR_4; - output [1:0] STAT_RX_FRAMING_ERR_5; - output [1:0] STAT_RX_FRAMING_ERR_6; - output [1:0] STAT_RX_FRAMING_ERR_7; - output [1:0] STAT_RX_FRAMING_ERR_8; - output [1:0] STAT_RX_FRAMING_ERR_9; - output STAT_RX_FRAMING_ERR_VALID_0; - output STAT_RX_FRAMING_ERR_VALID_1; - output STAT_RX_FRAMING_ERR_VALID_10; - output STAT_RX_FRAMING_ERR_VALID_11; - output STAT_RX_FRAMING_ERR_VALID_12; - output STAT_RX_FRAMING_ERR_VALID_13; - output STAT_RX_FRAMING_ERR_VALID_14; - output STAT_RX_FRAMING_ERR_VALID_15; - output STAT_RX_FRAMING_ERR_VALID_16; - output STAT_RX_FRAMING_ERR_VALID_17; - output STAT_RX_FRAMING_ERR_VALID_18; - output STAT_RX_FRAMING_ERR_VALID_19; - output STAT_RX_FRAMING_ERR_VALID_2; - output STAT_RX_FRAMING_ERR_VALID_3; - output STAT_RX_FRAMING_ERR_VALID_4; - output STAT_RX_FRAMING_ERR_VALID_5; - output STAT_RX_FRAMING_ERR_VALID_6; - output STAT_RX_FRAMING_ERR_VALID_7; - output STAT_RX_FRAMING_ERR_VALID_8; - output STAT_RX_FRAMING_ERR_VALID_9; - output STAT_RX_GOT_SIGNAL_OS; - output STAT_RX_HI_BER; - output STAT_RX_INRANGEERR; - output STAT_RX_INTERNAL_LOCAL_FAULT; - output STAT_RX_JABBER; - output [7:0] STAT_RX_LANE0_VLM_BIP7; - output STAT_RX_LANE0_VLM_BIP7_VALID; - output STAT_RX_LOCAL_FAULT; - output [19:0] STAT_RX_MF_ERR; - output [19:0] STAT_RX_MF_LEN_ERR; - output [19:0] STAT_RX_MF_REPEAT_ERR; - output STAT_RX_MISALIGNED; - output STAT_RX_MULTICAST; - output STAT_RX_OVERSIZE; - output STAT_RX_PACKET_1024_1518_BYTES; - output STAT_RX_PACKET_128_255_BYTES; - output STAT_RX_PACKET_1519_1522_BYTES; - output STAT_RX_PACKET_1523_1548_BYTES; - output STAT_RX_PACKET_1549_2047_BYTES; - output STAT_RX_PACKET_2048_4095_BYTES; - output STAT_RX_PACKET_256_511_BYTES; - output STAT_RX_PACKET_4096_8191_BYTES; - output STAT_RX_PACKET_512_1023_BYTES; - output STAT_RX_PACKET_64_BYTES; - output STAT_RX_PACKET_65_127_BYTES; - output STAT_RX_PACKET_8192_9215_BYTES; - output STAT_RX_PACKET_BAD_FCS; - output STAT_RX_PACKET_LARGE; - output [2:0] STAT_RX_PACKET_SMALL; - output STAT_RX_PAUSE; - output [15:0] STAT_RX_PAUSE_QUANTA0; - output [15:0] STAT_RX_PAUSE_QUANTA1; - output [15:0] STAT_RX_PAUSE_QUANTA2; - output [15:0] STAT_RX_PAUSE_QUANTA3; - output [15:0] STAT_RX_PAUSE_QUANTA4; - output [15:0] STAT_RX_PAUSE_QUANTA5; - output [15:0] STAT_RX_PAUSE_QUANTA6; - output [15:0] STAT_RX_PAUSE_QUANTA7; - output [15:0] STAT_RX_PAUSE_QUANTA8; - output [8:0] STAT_RX_PAUSE_REQ; - output [8:0] STAT_RX_PAUSE_VALID; - output STAT_RX_RECEIVED_LOCAL_FAULT; - output STAT_RX_REMOTE_FAULT; - output STAT_RX_RSFEC_AM_LOCK0; - output STAT_RX_RSFEC_AM_LOCK1; - output STAT_RX_RSFEC_AM_LOCK2; - output STAT_RX_RSFEC_AM_LOCK3; - output STAT_RX_RSFEC_CORRECTED_CW_INC; - output STAT_RX_RSFEC_CW_INC; - output [2:0] STAT_RX_RSFEC_ERR_COUNT0_INC; - output [2:0] STAT_RX_RSFEC_ERR_COUNT1_INC; - output [2:0] STAT_RX_RSFEC_ERR_COUNT2_INC; - output [2:0] STAT_RX_RSFEC_ERR_COUNT3_INC; - output STAT_RX_RSFEC_HI_SER; - output STAT_RX_RSFEC_LANE_ALIGNMENT_STATUS; - output [13:0] STAT_RX_RSFEC_LANE_FILL_0; - output [13:0] STAT_RX_RSFEC_LANE_FILL_1; - output [13:0] STAT_RX_RSFEC_LANE_FILL_2; - output [13:0] STAT_RX_RSFEC_LANE_FILL_3; - output [7:0] STAT_RX_RSFEC_LANE_MAPPING; - output [31:0] STAT_RX_RSFEC_RSVD; - output STAT_RX_RSFEC_UNCORRECTED_CW_INC; - output STAT_RX_STATUS; - output [2:0] STAT_RX_STOMPED_FCS; - output [19:0] STAT_RX_SYNCED; - output [19:0] STAT_RX_SYNCED_ERR; - output [2:0] STAT_RX_TEST_PATTERN_MISMATCH; - output STAT_RX_TOOLONG; - output [6:0] STAT_RX_TOTAL_BYTES; - output [13:0] STAT_RX_TOTAL_GOOD_BYTES; - output STAT_RX_TOTAL_GOOD_PACKETS; - output [2:0] STAT_RX_TOTAL_PACKETS; - output STAT_RX_TRUNCATED; - output [2:0] STAT_RX_UNDERSIZE; - output STAT_RX_UNICAST; - output STAT_RX_USER_PAUSE; - output STAT_RX_VLAN; - output [19:0] STAT_RX_VL_DEMUXED; - output [4:0] STAT_RX_VL_NUMBER_0; - output [4:0] STAT_RX_VL_NUMBER_1; - output [4:0] STAT_RX_VL_NUMBER_10; - output [4:0] STAT_RX_VL_NUMBER_11; - output [4:0] STAT_RX_VL_NUMBER_12; - output [4:0] STAT_RX_VL_NUMBER_13; - output [4:0] STAT_RX_VL_NUMBER_14; - output [4:0] STAT_RX_VL_NUMBER_15; - output [4:0] STAT_RX_VL_NUMBER_16; - output [4:0] STAT_RX_VL_NUMBER_17; - output [4:0] STAT_RX_VL_NUMBER_18; - output [4:0] STAT_RX_VL_NUMBER_19; - output [4:0] STAT_RX_VL_NUMBER_2; - output [4:0] STAT_RX_VL_NUMBER_3; - output [4:0] STAT_RX_VL_NUMBER_4; - output [4:0] STAT_RX_VL_NUMBER_5; - output [4:0] STAT_RX_VL_NUMBER_6; - output [4:0] STAT_RX_VL_NUMBER_7; - output [4:0] STAT_RX_VL_NUMBER_8; - output [4:0] STAT_RX_VL_NUMBER_9; - output STAT_TX_BAD_FCS; - output STAT_TX_BROADCAST; - output STAT_TX_FRAME_ERROR; - output STAT_TX_LOCAL_FAULT; - output STAT_TX_MULTICAST; - output STAT_TX_PACKET_1024_1518_BYTES; - output STAT_TX_PACKET_128_255_BYTES; - output STAT_TX_PACKET_1519_1522_BYTES; - output STAT_TX_PACKET_1523_1548_BYTES; - output STAT_TX_PACKET_1549_2047_BYTES; - output STAT_TX_PACKET_2048_4095_BYTES; - output STAT_TX_PACKET_256_511_BYTES; - output STAT_TX_PACKET_4096_8191_BYTES; - output STAT_TX_PACKET_512_1023_BYTES; - output STAT_TX_PACKET_64_BYTES; - output STAT_TX_PACKET_65_127_BYTES; - output STAT_TX_PACKET_8192_9215_BYTES; - output STAT_TX_PACKET_LARGE; - output STAT_TX_PACKET_SMALL; - output STAT_TX_PAUSE; - output [8:0] STAT_TX_PAUSE_VALID; - output STAT_TX_PTP_FIFO_READ_ERROR; - output STAT_TX_PTP_FIFO_WRITE_ERROR; - output [5:0] STAT_TX_TOTAL_BYTES; - output [13:0] STAT_TX_TOTAL_GOOD_BYTES; - output STAT_TX_TOTAL_GOOD_PACKETS; - output STAT_TX_TOTAL_PACKETS; - output STAT_TX_UNICAST; - output STAT_TX_USER_PAUSE; - output STAT_TX_VLAN; - output TX_OVFOUT; - output [4:0] TX_PTP_PCSLANE_OUT; - output [79:0] TX_PTP_TSTAMP_OUT; - output [15:0] TX_PTP_TSTAMP_TAG_OUT; - output TX_PTP_TSTAMP_VALID_OUT; - output TX_RDYOUT; - output [15:0] TX_SERDES_ALT_DATA0; - output [15:0] TX_SERDES_ALT_DATA1; - output [15:0] TX_SERDES_ALT_DATA2; - output [15:0] TX_SERDES_ALT_DATA3; - output [63:0] TX_SERDES_DATA0; - output [63:0] TX_SERDES_DATA1; - output [63:0] TX_SERDES_DATA2; - output [63:0] TX_SERDES_DATA3; - output [31:0] TX_SERDES_DATA4; - output [31:0] TX_SERDES_DATA5; - output [31:0] TX_SERDES_DATA6; - output [31:0] TX_SERDES_DATA7; - output [31:0] TX_SERDES_DATA8; - output [31:0] TX_SERDES_DATA9; - output TX_UNFOUT; - input CTL_CAUI4_MODE; - input CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE; - input CTL_RSFEC_IEEE_ERROR_INDICATION_MODE; - input CTL_RX_CHECK_ETYPE_GCP; - input CTL_RX_CHECK_ETYPE_GPP; - input CTL_RX_CHECK_ETYPE_PCP; - input CTL_RX_CHECK_ETYPE_PPP; - input CTL_RX_CHECK_MCAST_GCP; - input CTL_RX_CHECK_MCAST_GPP; - input CTL_RX_CHECK_MCAST_PCP; - input CTL_RX_CHECK_MCAST_PPP; - input CTL_RX_CHECK_OPCODE_GCP; - input CTL_RX_CHECK_OPCODE_GPP; - input CTL_RX_CHECK_OPCODE_PCP; - input CTL_RX_CHECK_OPCODE_PPP; - input CTL_RX_CHECK_SA_GCP; - input CTL_RX_CHECK_SA_GPP; - input CTL_RX_CHECK_SA_PCP; - input CTL_RX_CHECK_SA_PPP; - input CTL_RX_CHECK_UCAST_GCP; - input CTL_RX_CHECK_UCAST_GPP; - input CTL_RX_CHECK_UCAST_PCP; - input CTL_RX_CHECK_UCAST_PPP; - input CTL_RX_ENABLE; - input CTL_RX_ENABLE_GCP; - input CTL_RX_ENABLE_GPP; - input CTL_RX_ENABLE_PCP; - input CTL_RX_ENABLE_PPP; - input CTL_RX_FORCE_RESYNC; - input [8:0] CTL_RX_PAUSE_ACK; - input [8:0] CTL_RX_PAUSE_ENABLE; - input CTL_RX_RSFEC_ENABLE; - input CTL_RX_RSFEC_ENABLE_CORRECTION; - input CTL_RX_RSFEC_ENABLE_INDICATION; - input [79:0] CTL_RX_SYSTEMTIMERIN; - input CTL_RX_TEST_PATTERN; - input CTL_TX_ENABLE; - input CTL_TX_LANE0_VLM_BIP7_OVERRIDE; - input [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE; - input [8:0] CTL_TX_PAUSE_ENABLE; - input [15:0] CTL_TX_PAUSE_QUANTA0; - input [15:0] CTL_TX_PAUSE_QUANTA1; - input [15:0] CTL_TX_PAUSE_QUANTA2; - input [15:0] CTL_TX_PAUSE_QUANTA3; - input [15:0] CTL_TX_PAUSE_QUANTA4; - input [15:0] CTL_TX_PAUSE_QUANTA5; - input [15:0] CTL_TX_PAUSE_QUANTA6; - input [15:0] CTL_TX_PAUSE_QUANTA7; - input [15:0] CTL_TX_PAUSE_QUANTA8; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER0; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER1; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER2; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER3; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER4; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER5; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER6; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER7; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER8; - input [8:0] CTL_TX_PAUSE_REQ; - input CTL_TX_PTP_VLANE_ADJUST_MODE; - input CTL_TX_RESEND_PAUSE; - input CTL_TX_RSFEC_ENABLE; - input CTL_TX_SEND_IDLE; - input CTL_TX_SEND_LFI; - input CTL_TX_SEND_RFI; - input [79:0] CTL_TX_SYSTEMTIMERIN; - input CTL_TX_TEST_PATTERN; - input [9:0] DRP_ADDR; - input DRP_CLK; - input [15:0] DRP_DI; - input DRP_EN; - input DRP_WE; - input [329:0] RSFEC_BYPASS_RX_DIN; - input RSFEC_BYPASS_RX_DIN_CW_START; - input [329:0] RSFEC_BYPASS_TX_DIN; - input RSFEC_BYPASS_TX_DIN_CW_START; - input RX_CLK; - input RX_RESET; - input [15:0] RX_SERDES_ALT_DATA0; - input [15:0] RX_SERDES_ALT_DATA1; - input [15:0] RX_SERDES_ALT_DATA2; - input [15:0] RX_SERDES_ALT_DATA3; - input [9:0] RX_SERDES_CLK; - input [63:0] RX_SERDES_DATA0; - input [63:0] RX_SERDES_DATA1; - input [63:0] RX_SERDES_DATA2; - input [63:0] RX_SERDES_DATA3; - input [31:0] RX_SERDES_DATA4; - input [31:0] RX_SERDES_DATA5; - input [31:0] RX_SERDES_DATA6; - input [31:0] RX_SERDES_DATA7; - input [31:0] RX_SERDES_DATA8; - input [31:0] RX_SERDES_DATA9; - input [9:0] RX_SERDES_RESET; - input TX_CLK; - input [127:0] TX_DATAIN0; - input [127:0] TX_DATAIN1; - input [127:0] TX_DATAIN2; - input [127:0] TX_DATAIN3; - input TX_ENAIN0; - input TX_ENAIN1; - input TX_ENAIN2; - input TX_ENAIN3; - input TX_EOPIN0; - input TX_EOPIN1; - input TX_EOPIN2; - input TX_EOPIN3; - input TX_ERRIN0; - input TX_ERRIN1; - input TX_ERRIN2; - input TX_ERRIN3; - input [3:0] TX_MTYIN0; - input [3:0] TX_MTYIN1; - input [3:0] TX_MTYIN2; - input [3:0] TX_MTYIN3; - input [55:0] TX_PREIN; - input [1:0] TX_PTP_1588OP_IN; - input [15:0] TX_PTP_CHKSUM_OFFSET_IN; - input [63:0] TX_PTP_RXTSTAMP_IN; - input [15:0] TX_PTP_TAG_FIELD_IN; - input [15:0] TX_PTP_TSTAMP_OFFSET_IN; - input TX_PTP_UPD_CHKSUM_IN; - input TX_RESET; - input TX_SOPIN0; - input TX_SOPIN1; - input TX_SOPIN2; - input TX_SOPIN3; -endmodule - -module MCB (...); - parameter integer ARB_NUM_TIME_SLOTS = 12; - parameter [17:0] ARB_TIME_SLOT_0 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_1 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_10 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_11 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_2 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_3 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_4 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_5 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_6 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_7 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_8 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_9 = 18'b111111111111111111; - parameter [2:0] CAL_BA = 3'h0; - parameter CAL_BYPASS = "YES"; - parameter [11:0] CAL_CA = 12'h000; - parameter CAL_CALIBRATION_MODE = "NOCALIBRATION"; - parameter integer CAL_CLK_DIV = 1; - parameter CAL_DELAY = "QUARTER"; - parameter [14:0] CAL_RA = 15'h0000; - parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN"; - parameter integer MEM_BA_SIZE = 3; - parameter integer MEM_BURST_LEN = 8; - parameter integer MEM_CAS_LATENCY = 4; - parameter integer MEM_CA_SIZE = 11; - parameter MEM_DDR1_2_ODS = "FULL"; - parameter MEM_DDR2_3_HIGH_TEMP_SR = "NORMAL"; - parameter MEM_DDR2_3_PA_SR = "FULL"; - parameter integer MEM_DDR2_ADD_LATENCY = 0; - parameter MEM_DDR2_DIFF_DQS_EN = "YES"; - parameter MEM_DDR2_RTT = "50OHMS"; - parameter integer MEM_DDR2_WRT_RECOVERY = 4; - parameter MEM_DDR3_ADD_LATENCY = "OFF"; - parameter MEM_DDR3_AUTO_SR = "ENABLED"; - parameter integer MEM_DDR3_CAS_LATENCY = 7; - parameter integer MEM_DDR3_CAS_WR_LATENCY = 5; - parameter MEM_DDR3_DYN_WRT_ODT = "OFF"; - parameter MEM_DDR3_ODS = "DIV7"; - parameter MEM_DDR3_RTT = "DIV2"; - parameter integer MEM_DDR3_WRT_RECOVERY = 7; - parameter MEM_MDDR_ODS = "FULL"; - parameter MEM_MOBILE_PA_SR = "FULL"; - parameter integer MEM_MOBILE_TC_SR = 0; - parameter integer MEM_RAS_VAL = 0; - parameter integer MEM_RA_SIZE = 13; - parameter integer MEM_RCD_VAL = 1; - parameter integer MEM_REFI_VAL = 0; - parameter integer MEM_RFC_VAL = 0; - parameter integer MEM_RP_VAL = 0; - parameter integer MEM_RTP_VAL = 0; - parameter MEM_TYPE = "DDR3"; - parameter integer MEM_WIDTH = 4; - parameter integer MEM_WR_VAL = 0; - parameter integer MEM_WTR_VAL = 3; - parameter PORT_CONFIG = "B32_B32_B32_B32"; - output CAS; - output CKE; - output DQIOWEN0; - output DQSIOWEN90N; - output DQSIOWEN90P; - output IOIDRPADD; - output IOIDRPBROADCAST; - output IOIDRPCLK; - output IOIDRPCS; - output IOIDRPSDO; - output IOIDRPTRAIN; - output IOIDRPUPDATE; - output LDMN; - output LDMP; - output ODT; - output P0CMDEMPTY; - output P0CMDFULL; - output P0RDEMPTY; - output P0RDERROR; - output P0RDFULL; - output P0RDOVERFLOW; - output P0WREMPTY; - output P0WRERROR; - output P0WRFULL; - output P0WRUNDERRUN; - output P1CMDEMPTY; - output P1CMDFULL; - output P1RDEMPTY; - output P1RDERROR; - output P1RDFULL; - output P1RDOVERFLOW; - output P1WREMPTY; - output P1WRERROR; - output P1WRFULL; - output P1WRUNDERRUN; - output P2CMDEMPTY; - output P2CMDFULL; - output P2EMPTY; - output P2ERROR; - output P2FULL; - output P2RDOVERFLOW; - output P2WRUNDERRUN; - output P3CMDEMPTY; - output P3CMDFULL; - output P3EMPTY; - output P3ERROR; - output P3FULL; - output P3RDOVERFLOW; - output P3WRUNDERRUN; - output P4CMDEMPTY; - output P4CMDFULL; - output P4EMPTY; - output P4ERROR; - output P4FULL; - output P4RDOVERFLOW; - output P4WRUNDERRUN; - output P5CMDEMPTY; - output P5CMDFULL; - output P5EMPTY; - output P5ERROR; - output P5FULL; - output P5RDOVERFLOW; - output P5WRUNDERRUN; - output RAS; - output RST; - output SELFREFRESHMODE; - output UDMN; - output UDMP; - output UOCALSTART; - output UOCMDREADYIN; - output UODATAVALID; - output UODONECAL; - output UOREFRSHFLAG; - output UOSDO; - output WE; - output [14:0] ADDR; - output [15:0] DQON; - output [15:0] DQOP; - output [2:0] BA; - output [31:0] P0RDDATA; - output [31:0] P1RDDATA; - output [31:0] P2RDDATA; - output [31:0] P3RDDATA; - output [31:0] P4RDDATA; - output [31:0] P5RDDATA; - output [31:0] STATUS; - output [4:0] IOIDRPADDR; - output [6:0] P0RDCOUNT; - output [6:0] P0WRCOUNT; - output [6:0] P1RDCOUNT; - output [6:0] P1WRCOUNT; - output [6:0] P2COUNT; - output [6:0] P3COUNT; - output [6:0] P4COUNT; - output [6:0] P5COUNT; - output [7:0] UODATA; - input DQSIOIN; - input DQSIOIP; - input IOIDRPSDI; - input P0ARBEN; - input P0CMDCLK; - input P0CMDEN; - input P0RDCLK; - input P0RDEN; - input P0WRCLK; - input P0WREN; - input P1ARBEN; - input P1CMDCLK; - input P1CMDEN; - input P1RDCLK; - input P1RDEN; - input P1WRCLK; - input P1WREN; - input P2ARBEN; - input P2CLK; - input P2CMDCLK; - input P2CMDEN; - input P2EN; - input P3ARBEN; - input P3CLK; - input P3CMDCLK; - input P3CMDEN; - input P3EN; - input P4ARBEN; - input P4CLK; - input P4CMDCLK; - input P4CMDEN; - input P4EN; - input P5ARBEN; - input P5CLK; - input P5CMDCLK; - input P5CMDEN; - input P5EN; - input PLLLOCK; - input RECAL; - input SELFREFRESHENTER; - input SYSRST; - input UDQSIOIN; - input UDQSIOIP; - input UIADD; - input UIBROADCAST; - input UICLK; - input UICMD; - input UICMDEN; - input UICMDIN; - input UICS; - input UIDONECAL; - input UIDQLOWERDEC; - input UIDQLOWERINC; - input UIDQUPPERDEC; - input UIDQUPPERINC; - input UIDRPUPDATE; - input UILDQSDEC; - input UILDQSINC; - input UIREAD; - input UISDI; - input UIUDQSDEC; - input UIUDQSINC; - input [11:0] P0CMDCA; - input [11:0] P1CMDCA; - input [11:0] P2CMDCA; - input [11:0] P3CMDCA; - input [11:0] P4CMDCA; - input [11:0] P5CMDCA; - input [14:0] P0CMDRA; - input [14:0] P1CMDRA; - input [14:0] P2CMDRA; - input [14:0] P3CMDRA; - input [14:0] P4CMDRA; - input [14:0] P5CMDRA; - input [15:0] DQI; - input [1:0] PLLCE; - input [1:0] PLLCLK; - input [2:0] P0CMDBA; - input [2:0] P0CMDINSTR; - input [2:0] P1CMDBA; - input [2:0] P1CMDINSTR; - input [2:0] P2CMDBA; - input [2:0] P2CMDINSTR; - input [2:0] P3CMDBA; - input [2:0] P3CMDINSTR; - input [2:0] P4CMDBA; - input [2:0] P4CMDINSTR; - input [2:0] P5CMDBA; - input [2:0] P5CMDINSTR; - input [31:0] P0WRDATA; - input [31:0] P1WRDATA; - input [31:0] P2WRDATA; - input [31:0] P3WRDATA; - input [31:0] P4WRDATA; - input [31:0] P5WRDATA; - input [3:0] P0RWRMASK; - input [3:0] P1RWRMASK; - input [3:0] P2WRMASK; - input [3:0] P3WRMASK; - input [3:0] P4WRMASK; - input [3:0] P5WRMASK; - input [3:0] UIDQCOUNT; - input [4:0] UIADDR; - input [5:0] P0CMDBL; - input [5:0] P1CMDBL; - input [5:0] P2CMDBL; - input [5:0] P3CMDBL; - input [5:0] P4CMDBL; - input [5:0] P5CMDBL; -endmodule - -(* keep *) -module HBM_REF_CLK (...); - input REF_CLK; -endmodule - -(* keep *) -module HBM_SNGLBLI_INTF_APB (...); - parameter CLK_SEL = "FALSE"; - parameter [0:0] IS_PCLK_INVERTED = 1'b0; - parameter [0:0] IS_PRESET_N_INVERTED = 1'b0; - parameter MC_ENABLE = "FALSE"; - parameter PHY_ENABLE = "FALSE"; - parameter PHY_PCLK_INVERT = "FALSE"; - parameter SWITCH_ENABLE = "FALSE"; - output CATTRIP_PIPE; - output [31:0] PRDATA_PIPE; - output PREADY_PIPE; - output PSLVERR_PIPE; - output [2:0] TEMP_PIPE; - input [21:0] PADDR; - (* invertible_pin = "IS_PCLK_INVERTED" *) - input PCLK; - input PENABLE; - (* invertible_pin = "IS_PRESET_N_INVERTED" *) - input PRESET_N; - input PSEL; - input [31:0] PWDATA; - input PWRITE; -endmodule - -(* keep *) -module HBM_SNGLBLI_INTF_AXI (...); - parameter CLK_SEL = "FALSE"; - parameter integer DATARATE = 1800; - parameter [0:0] IS_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_ARESET_N_INVERTED = 1'b0; - parameter MC_ENABLE = "FALSE"; - parameter integer PAGEHIT_PERCENT = 75; - parameter PHY_ENABLE = "FALSE"; - parameter integer READ_PERCENT = 50; - parameter SWITCH_ENABLE = "FALSE"; - parameter integer WRITE_PERCENT = 50; - output ARREADY_PIPE; - output AWREADY_PIPE; - output [5:0] BID_PIPE; - output [1:0] BRESP_PIPE; - output BVALID_PIPE; - output [1:0] DFI_AW_AERR_N_PIPE; - output DFI_CLK_BUF; - output DFI_CTRLUPD_ACK_PIPE; - output [7:0] DFI_DBI_BYTE_DISABLE_PIPE; - output [20:0] DFI_DW_RDDATA_DBI_PIPE; - output [7:0] DFI_DW_RDDATA_DERR_PIPE; - output [1:0] DFI_DW_RDDATA_PAR_VALID_PIPE; - output [1:0] DFI_DW_RDDATA_VALID_PIPE; - output DFI_INIT_COMPLETE_PIPE; - output DFI_PHYUPD_REQ_PIPE; - output DFI_PHYUPD_TYPE_PIPE; - output DFI_PHY_LP_STATE_PIPE; - output DFI_RST_N_BUF; - output [5:0] MC_STATUS; - output [7:0] PHY_STATUS; - output [31:0] RDATA_PARITY_PIPE; - output [255:0] RDATA_PIPE; - output [5:0] RID_PIPE; - output RLAST_PIPE; - output [1:0] RRESP_PIPE; - output RVALID_PIPE; - output [5:0] STATUS; - output WREADY_PIPE; - (* invertible_pin = "IS_ACLK_INVERTED" *) - input ACLK; - input [36:0] ARADDR; - input [1:0] ARBURST; - (* invertible_pin = "IS_ARESET_N_INVERTED" *) - input ARESET_N; - input [5:0] ARID; - input [3:0] ARLEN; - input [2:0] ARSIZE; - input ARVALID; - input [36:0] AWADDR; - input [1:0] AWBURST; - input [5:0] AWID; - input [3:0] AWLEN; - input [2:0] AWSIZE; - input AWVALID; - input BREADY; - input BSCAN_CK; - input DFI_LP_PWR_X_REQ; - input MBIST_EN; - input RREADY; - input [255:0] WDATA; - input [31:0] WDATA_PARITY; - input WLAST; - input [31:0] WSTRB; - input WVALID; -endmodule - -(* keep *) -module HBM_ONE_STACK_INTF (...); - parameter CLK_SEL_00 = "FALSE"; - parameter CLK_SEL_01 = "FALSE"; - parameter CLK_SEL_02 = "FALSE"; - parameter CLK_SEL_03 = "FALSE"; - parameter CLK_SEL_04 = "FALSE"; - parameter CLK_SEL_05 = "FALSE"; - parameter CLK_SEL_06 = "FALSE"; - parameter CLK_SEL_07 = "FALSE"; - parameter CLK_SEL_08 = "FALSE"; - parameter CLK_SEL_09 = "FALSE"; - parameter CLK_SEL_10 = "FALSE"; - parameter CLK_SEL_11 = "FALSE"; - parameter CLK_SEL_12 = "FALSE"; - parameter CLK_SEL_13 = "FALSE"; - parameter CLK_SEL_14 = "FALSE"; - parameter CLK_SEL_15 = "FALSE"; - parameter integer DATARATE_00 = 1800; - parameter integer DATARATE_01 = 1800; - parameter integer DATARATE_02 = 1800; - parameter integer DATARATE_03 = 1800; - parameter integer DATARATE_04 = 1800; - parameter integer DATARATE_05 = 1800; - parameter integer DATARATE_06 = 1800; - parameter integer DATARATE_07 = 1800; - parameter DA_LOCKOUT = "FALSE"; - parameter [0:0] IS_APB_0_PCLK_INVERTED = 1'b0; - parameter [0:0] IS_APB_0_PRESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_00_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_00_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_01_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_01_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_02_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_02_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_03_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_03_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_04_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_04_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_05_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_05_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_06_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_06_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_07_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_07_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_08_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_08_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_09_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_09_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_10_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_10_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_11_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_11_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_12_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_12_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_13_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_13_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_14_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_14_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_15_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_15_ARESET_N_INVERTED = 1'b0; - parameter MC_ENABLE_0 = "FALSE"; - parameter MC_ENABLE_1 = "FALSE"; - parameter MC_ENABLE_2 = "FALSE"; - parameter MC_ENABLE_3 = "FALSE"; - parameter MC_ENABLE_4 = "FALSE"; - parameter MC_ENABLE_5 = "FALSE"; - parameter MC_ENABLE_6 = "FALSE"; - parameter MC_ENABLE_7 = "FALSE"; - parameter MC_ENABLE_APB = "FALSE"; - parameter integer PAGEHIT_PERCENT_00 = 75; - parameter PHY_ENABLE_00 = "FALSE"; - parameter PHY_ENABLE_01 = "FALSE"; - parameter PHY_ENABLE_02 = "FALSE"; - parameter PHY_ENABLE_03 = "FALSE"; - parameter PHY_ENABLE_04 = "FALSE"; - parameter PHY_ENABLE_05 = "FALSE"; - parameter PHY_ENABLE_06 = "FALSE"; - parameter PHY_ENABLE_07 = "FALSE"; - parameter PHY_ENABLE_08 = "FALSE"; - parameter PHY_ENABLE_09 = "FALSE"; - parameter PHY_ENABLE_10 = "FALSE"; - parameter PHY_ENABLE_11 = "FALSE"; - parameter PHY_ENABLE_12 = "FALSE"; - parameter PHY_ENABLE_13 = "FALSE"; - parameter PHY_ENABLE_14 = "FALSE"; - parameter PHY_ENABLE_15 = "FALSE"; - parameter PHY_ENABLE_APB = "FALSE"; - parameter PHY_PCLK_INVERT_01 = "FALSE"; - parameter integer READ_PERCENT_00 = 50; - parameter integer READ_PERCENT_01 = 50; - parameter integer READ_PERCENT_02 = 50; - parameter integer READ_PERCENT_03 = 50; - parameter integer READ_PERCENT_04 = 50; - parameter integer READ_PERCENT_05 = 50; - parameter integer READ_PERCENT_06 = 50; - parameter integer READ_PERCENT_07 = 50; - parameter integer READ_PERCENT_08 = 50; - parameter integer READ_PERCENT_09 = 50; - parameter integer READ_PERCENT_10 = 50; - parameter integer READ_PERCENT_11 = 50; - parameter integer READ_PERCENT_12 = 50; - parameter integer READ_PERCENT_13 = 50; - parameter integer READ_PERCENT_14 = 50; - parameter integer READ_PERCENT_15 = 50; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter integer STACK_LOCATION = 0; - parameter SWITCH_ENABLE = "FALSE"; - parameter integer WRITE_PERCENT_00 = 50; - parameter integer WRITE_PERCENT_01 = 50; - parameter integer WRITE_PERCENT_02 = 50; - parameter integer WRITE_PERCENT_03 = 50; - parameter integer WRITE_PERCENT_04 = 50; - parameter integer WRITE_PERCENT_05 = 50; - parameter integer WRITE_PERCENT_06 = 50; - parameter integer WRITE_PERCENT_07 = 50; - parameter integer WRITE_PERCENT_08 = 50; - parameter integer WRITE_PERCENT_09 = 50; - parameter integer WRITE_PERCENT_10 = 50; - parameter integer WRITE_PERCENT_11 = 50; - parameter integer WRITE_PERCENT_12 = 50; - parameter integer WRITE_PERCENT_13 = 50; - parameter integer WRITE_PERCENT_14 = 50; - parameter integer WRITE_PERCENT_15 = 50; - output [31:0] APB_0_PRDATA; - output APB_0_PREADY; - output APB_0_PSLVERR; - output AXI_00_ARREADY; - output AXI_00_AWREADY; - output [5:0] AXI_00_BID; - output [1:0] AXI_00_BRESP; - output AXI_00_BVALID; - output [1:0] AXI_00_DFI_AW_AERR_N; - output AXI_00_DFI_CLK_BUF; - output [7:0] AXI_00_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_00_DFI_DW_RDDATA_DBI; - output [7:0] AXI_00_DFI_DW_RDDATA_DERR; - output [1:0] AXI_00_DFI_DW_RDDATA_VALID; - output AXI_00_DFI_INIT_COMPLETE; - output AXI_00_DFI_PHYUPD_REQ; - output AXI_00_DFI_PHY_LP_STATE; - output AXI_00_DFI_RST_N_BUF; - output [5:0] AXI_00_MC_STATUS; - output [7:0] AXI_00_PHY_STATUS; - output [255:0] AXI_00_RDATA; - output [31:0] AXI_00_RDATA_PARITY; - output [5:0] AXI_00_RID; - output AXI_00_RLAST; - output [1:0] AXI_00_RRESP; - output AXI_00_RVALID; - output AXI_00_WREADY; - output AXI_01_ARREADY; - output AXI_01_AWREADY; - output [5:0] AXI_01_BID; - output [1:0] AXI_01_BRESP; - output AXI_01_BVALID; - output [1:0] AXI_01_DFI_AW_AERR_N; - output AXI_01_DFI_CLK_BUF; - output [7:0] AXI_01_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_01_DFI_DW_RDDATA_DBI; - output [7:0] AXI_01_DFI_DW_RDDATA_DERR; - output [1:0] AXI_01_DFI_DW_RDDATA_VALID; - output AXI_01_DFI_INIT_COMPLETE; - output AXI_01_DFI_PHYUPD_REQ; - output AXI_01_DFI_PHY_LP_STATE; - output AXI_01_DFI_RST_N_BUF; - output [255:0] AXI_01_RDATA; - output [31:0] AXI_01_RDATA_PARITY; - output [5:0] AXI_01_RID; - output AXI_01_RLAST; - output [1:0] AXI_01_RRESP; - output AXI_01_RVALID; - output AXI_01_WREADY; - output AXI_02_ARREADY; - output AXI_02_AWREADY; - output [5:0] AXI_02_BID; - output [1:0] AXI_02_BRESP; - output AXI_02_BVALID; - output [1:0] AXI_02_DFI_AW_AERR_N; - output AXI_02_DFI_CLK_BUF; - output [7:0] AXI_02_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_02_DFI_DW_RDDATA_DBI; - output [7:0] AXI_02_DFI_DW_RDDATA_DERR; - output [1:0] AXI_02_DFI_DW_RDDATA_VALID; - output AXI_02_DFI_INIT_COMPLETE; - output AXI_02_DFI_PHYUPD_REQ; - output AXI_02_DFI_PHY_LP_STATE; - output AXI_02_DFI_RST_N_BUF; - output [5:0] AXI_02_MC_STATUS; - output [7:0] AXI_02_PHY_STATUS; - output [255:0] AXI_02_RDATA; - output [31:0] AXI_02_RDATA_PARITY; - output [5:0] AXI_02_RID; - output AXI_02_RLAST; - output [1:0] AXI_02_RRESP; - output AXI_02_RVALID; - output AXI_02_WREADY; - output AXI_03_ARREADY; - output AXI_03_AWREADY; - output [5:0] AXI_03_BID; - output [1:0] AXI_03_BRESP; - output AXI_03_BVALID; - output [1:0] AXI_03_DFI_AW_AERR_N; - output AXI_03_DFI_CLK_BUF; - output [7:0] AXI_03_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_03_DFI_DW_RDDATA_DBI; - output [7:0] AXI_03_DFI_DW_RDDATA_DERR; - output [1:0] AXI_03_DFI_DW_RDDATA_VALID; - output AXI_03_DFI_INIT_COMPLETE; - output AXI_03_DFI_PHYUPD_REQ; - output AXI_03_DFI_PHY_LP_STATE; - output AXI_03_DFI_RST_N_BUF; - output [255:0] AXI_03_RDATA; - output [31:0] AXI_03_RDATA_PARITY; - output [5:0] AXI_03_RID; - output AXI_03_RLAST; - output [1:0] AXI_03_RRESP; - output AXI_03_RVALID; - output AXI_03_WREADY; - output AXI_04_ARREADY; - output AXI_04_AWREADY; - output [5:0] AXI_04_BID; - output [1:0] AXI_04_BRESP; - output AXI_04_BVALID; - output [1:0] AXI_04_DFI_AW_AERR_N; - output AXI_04_DFI_CLK_BUF; - output [7:0] AXI_04_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_04_DFI_DW_RDDATA_DBI; - output [7:0] AXI_04_DFI_DW_RDDATA_DERR; - output [1:0] AXI_04_DFI_DW_RDDATA_VALID; - output AXI_04_DFI_INIT_COMPLETE; - output AXI_04_DFI_PHYUPD_REQ; - output AXI_04_DFI_PHY_LP_STATE; - output AXI_04_DFI_RST_N_BUF; - output [5:0] AXI_04_MC_STATUS; - output [7:0] AXI_04_PHY_STATUS; - output [255:0] AXI_04_RDATA; - output [31:0] AXI_04_RDATA_PARITY; - output [5:0] AXI_04_RID; - output AXI_04_RLAST; - output [1:0] AXI_04_RRESP; - output AXI_04_RVALID; - output AXI_04_WREADY; - output AXI_05_ARREADY; - output AXI_05_AWREADY; - output [5:0] AXI_05_BID; - output [1:0] AXI_05_BRESP; - output AXI_05_BVALID; - output [1:0] AXI_05_DFI_AW_AERR_N; - output AXI_05_DFI_CLK_BUF; - output [7:0] AXI_05_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_05_DFI_DW_RDDATA_DBI; - output [7:0] AXI_05_DFI_DW_RDDATA_DERR; - output [1:0] AXI_05_DFI_DW_RDDATA_VALID; - output AXI_05_DFI_INIT_COMPLETE; - output AXI_05_DFI_PHYUPD_REQ; - output AXI_05_DFI_PHY_LP_STATE; - output AXI_05_DFI_RST_N_BUF; - output [255:0] AXI_05_RDATA; - output [31:0] AXI_05_RDATA_PARITY; - output [5:0] AXI_05_RID; - output AXI_05_RLAST; - output [1:0] AXI_05_RRESP; - output AXI_05_RVALID; - output AXI_05_WREADY; - output AXI_06_ARREADY; - output AXI_06_AWREADY; - output [5:0] AXI_06_BID; - output [1:0] AXI_06_BRESP; - output AXI_06_BVALID; - output [1:0] AXI_06_DFI_AW_AERR_N; - output AXI_06_DFI_CLK_BUF; - output [7:0] AXI_06_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_06_DFI_DW_RDDATA_DBI; - output [7:0] AXI_06_DFI_DW_RDDATA_DERR; - output [1:0] AXI_06_DFI_DW_RDDATA_VALID; - output AXI_06_DFI_INIT_COMPLETE; - output AXI_06_DFI_PHYUPD_REQ; - output AXI_06_DFI_PHY_LP_STATE; - output AXI_06_DFI_RST_N_BUF; - output [5:0] AXI_06_MC_STATUS; - output [7:0] AXI_06_PHY_STATUS; - output [255:0] AXI_06_RDATA; - output [31:0] AXI_06_RDATA_PARITY; - output [5:0] AXI_06_RID; - output AXI_06_RLAST; - output [1:0] AXI_06_RRESP; - output AXI_06_RVALID; - output AXI_06_WREADY; - output AXI_07_ARREADY; - output AXI_07_AWREADY; - output [5:0] AXI_07_BID; - output [1:0] AXI_07_BRESP; - output AXI_07_BVALID; - output [1:0] AXI_07_DFI_AW_AERR_N; - output AXI_07_DFI_CLK_BUF; - output [7:0] AXI_07_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_07_DFI_DW_RDDATA_DBI; - output [7:0] AXI_07_DFI_DW_RDDATA_DERR; - output [1:0] AXI_07_DFI_DW_RDDATA_VALID; - output AXI_07_DFI_INIT_COMPLETE; - output AXI_07_DFI_PHYUPD_REQ; - output AXI_07_DFI_PHY_LP_STATE; - output AXI_07_DFI_RST_N_BUF; - output [255:0] AXI_07_RDATA; - output [31:0] AXI_07_RDATA_PARITY; - output [5:0] AXI_07_RID; - output AXI_07_RLAST; - output [1:0] AXI_07_RRESP; - output AXI_07_RVALID; - output AXI_07_WREADY; - output AXI_08_ARREADY; - output AXI_08_AWREADY; - output [5:0] AXI_08_BID; - output [1:0] AXI_08_BRESP; - output AXI_08_BVALID; - output [1:0] AXI_08_DFI_AW_AERR_N; - output AXI_08_DFI_CLK_BUF; - output [7:0] AXI_08_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_08_DFI_DW_RDDATA_DBI; - output [7:0] AXI_08_DFI_DW_RDDATA_DERR; - output [1:0] AXI_08_DFI_DW_RDDATA_VALID; - output AXI_08_DFI_INIT_COMPLETE; - output AXI_08_DFI_PHYUPD_REQ; - output AXI_08_DFI_PHY_LP_STATE; - output AXI_08_DFI_RST_N_BUF; - output [5:0] AXI_08_MC_STATUS; - output [7:0] AXI_08_PHY_STATUS; - output [255:0] AXI_08_RDATA; - output [31:0] AXI_08_RDATA_PARITY; - output [5:0] AXI_08_RID; - output AXI_08_RLAST; - output [1:0] AXI_08_RRESP; - output AXI_08_RVALID; - output AXI_08_WREADY; - output AXI_09_ARREADY; - output AXI_09_AWREADY; - output [5:0] AXI_09_BID; - output [1:0] AXI_09_BRESP; - output AXI_09_BVALID; - output [1:0] AXI_09_DFI_AW_AERR_N; - output AXI_09_DFI_CLK_BUF; - output [7:0] AXI_09_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_09_DFI_DW_RDDATA_DBI; - output [7:0] AXI_09_DFI_DW_RDDATA_DERR; - output [1:0] AXI_09_DFI_DW_RDDATA_VALID; - output AXI_09_DFI_INIT_COMPLETE; - output AXI_09_DFI_PHYUPD_REQ; - output AXI_09_DFI_PHY_LP_STATE; - output AXI_09_DFI_RST_N_BUF; - output [255:0] AXI_09_RDATA; - output [31:0] AXI_09_RDATA_PARITY; - output [5:0] AXI_09_RID; - output AXI_09_RLAST; - output [1:0] AXI_09_RRESP; - output AXI_09_RVALID; - output AXI_09_WREADY; - output AXI_10_ARREADY; - output AXI_10_AWREADY; - output [5:0] AXI_10_BID; - output [1:0] AXI_10_BRESP; - output AXI_10_BVALID; - output [1:0] AXI_10_DFI_AW_AERR_N; - output AXI_10_DFI_CLK_BUF; - output [7:0] AXI_10_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_10_DFI_DW_RDDATA_DBI; - output [7:0] AXI_10_DFI_DW_RDDATA_DERR; - output [1:0] AXI_10_DFI_DW_RDDATA_VALID; - output AXI_10_DFI_INIT_COMPLETE; - output AXI_10_DFI_PHYUPD_REQ; - output AXI_10_DFI_PHY_LP_STATE; - output AXI_10_DFI_RST_N_BUF; - output [5:0] AXI_10_MC_STATUS; - output [7:0] AXI_10_PHY_STATUS; - output [255:0] AXI_10_RDATA; - output [31:0] AXI_10_RDATA_PARITY; - output [5:0] AXI_10_RID; - output AXI_10_RLAST; - output [1:0] AXI_10_RRESP; - output AXI_10_RVALID; - output AXI_10_WREADY; - output AXI_11_ARREADY; - output AXI_11_AWREADY; - output [5:0] AXI_11_BID; - output [1:0] AXI_11_BRESP; - output AXI_11_BVALID; - output [1:0] AXI_11_DFI_AW_AERR_N; - output AXI_11_DFI_CLK_BUF; - output [7:0] AXI_11_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_11_DFI_DW_RDDATA_DBI; - output [7:0] AXI_11_DFI_DW_RDDATA_DERR; - output [1:0] AXI_11_DFI_DW_RDDATA_VALID; - output AXI_11_DFI_INIT_COMPLETE; - output AXI_11_DFI_PHYUPD_REQ; - output AXI_11_DFI_PHY_LP_STATE; - output AXI_11_DFI_RST_N_BUF; - output [255:0] AXI_11_RDATA; - output [31:0] AXI_11_RDATA_PARITY; - output [5:0] AXI_11_RID; - output AXI_11_RLAST; - output [1:0] AXI_11_RRESP; - output AXI_11_RVALID; - output AXI_11_WREADY; - output AXI_12_ARREADY; - output AXI_12_AWREADY; - output [5:0] AXI_12_BID; - output [1:0] AXI_12_BRESP; - output AXI_12_BVALID; - output [1:0] AXI_12_DFI_AW_AERR_N; - output AXI_12_DFI_CLK_BUF; - output [7:0] AXI_12_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_12_DFI_DW_RDDATA_DBI; - output [7:0] AXI_12_DFI_DW_RDDATA_DERR; - output [1:0] AXI_12_DFI_DW_RDDATA_VALID; - output AXI_12_DFI_INIT_COMPLETE; - output AXI_12_DFI_PHYUPD_REQ; - output AXI_12_DFI_PHY_LP_STATE; - output AXI_12_DFI_RST_N_BUF; - output [5:0] AXI_12_MC_STATUS; - output [7:0] AXI_12_PHY_STATUS; - output [255:0] AXI_12_RDATA; - output [31:0] AXI_12_RDATA_PARITY; - output [5:0] AXI_12_RID; - output AXI_12_RLAST; - output [1:0] AXI_12_RRESP; - output AXI_12_RVALID; - output AXI_12_WREADY; - output AXI_13_ARREADY; - output AXI_13_AWREADY; - output [5:0] AXI_13_BID; - output [1:0] AXI_13_BRESP; - output AXI_13_BVALID; - output [1:0] AXI_13_DFI_AW_AERR_N; - output AXI_13_DFI_CLK_BUF; - output [7:0] AXI_13_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_13_DFI_DW_RDDATA_DBI; - output [7:0] AXI_13_DFI_DW_RDDATA_DERR; - output [1:0] AXI_13_DFI_DW_RDDATA_VALID; - output AXI_13_DFI_INIT_COMPLETE; - output AXI_13_DFI_PHYUPD_REQ; - output AXI_13_DFI_PHY_LP_STATE; - output AXI_13_DFI_RST_N_BUF; - output [255:0] AXI_13_RDATA; - output [31:0] AXI_13_RDATA_PARITY; - output [5:0] AXI_13_RID; - output AXI_13_RLAST; - output [1:0] AXI_13_RRESP; - output AXI_13_RVALID; - output AXI_13_WREADY; - output AXI_14_ARREADY; - output AXI_14_AWREADY; - output [5:0] AXI_14_BID; - output [1:0] AXI_14_BRESP; - output AXI_14_BVALID; - output [1:0] AXI_14_DFI_AW_AERR_N; - output AXI_14_DFI_CLK_BUF; - output [7:0] AXI_14_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_14_DFI_DW_RDDATA_DBI; - output [7:0] AXI_14_DFI_DW_RDDATA_DERR; - output [1:0] AXI_14_DFI_DW_RDDATA_VALID; - output AXI_14_DFI_INIT_COMPLETE; - output AXI_14_DFI_PHYUPD_REQ; - output AXI_14_DFI_PHY_LP_STATE; - output AXI_14_DFI_RST_N_BUF; - output [5:0] AXI_14_MC_STATUS; - output [7:0] AXI_14_PHY_STATUS; - output [255:0] AXI_14_RDATA; - output [31:0] AXI_14_RDATA_PARITY; - output [5:0] AXI_14_RID; - output AXI_14_RLAST; - output [1:0] AXI_14_RRESP; - output AXI_14_RVALID; - output AXI_14_WREADY; - output AXI_15_ARREADY; - output AXI_15_AWREADY; - output [5:0] AXI_15_BID; - output [1:0] AXI_15_BRESP; - output AXI_15_BVALID; - output [1:0] AXI_15_DFI_AW_AERR_N; - output AXI_15_DFI_CLK_BUF; - output [7:0] AXI_15_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_15_DFI_DW_RDDATA_DBI; - output [7:0] AXI_15_DFI_DW_RDDATA_DERR; - output [1:0] AXI_15_DFI_DW_RDDATA_VALID; - output AXI_15_DFI_INIT_COMPLETE; - output AXI_15_DFI_PHYUPD_REQ; - output AXI_15_DFI_PHY_LP_STATE; - output AXI_15_DFI_RST_N_BUF; - output [255:0] AXI_15_RDATA; - output [31:0] AXI_15_RDATA_PARITY; - output [5:0] AXI_15_RID; - output AXI_15_RLAST; - output [1:0] AXI_15_RRESP; - output AXI_15_RVALID; - output AXI_15_WREADY; - output DRAM_0_STAT_CATTRIP; - output [2:0] DRAM_0_STAT_TEMP; - input [21:0] APB_0_PADDR; - (* invertible_pin = "IS_APB_0_PCLK_INVERTED" *) - input APB_0_PCLK; - input APB_0_PENABLE; - (* invertible_pin = "IS_APB_0_PRESET_N_INVERTED" *) - input APB_0_PRESET_N; - input APB_0_PSEL; - input [31:0] APB_0_PWDATA; - input APB_0_PWRITE; - (* invertible_pin = "IS_AXI_00_ACLK_INVERTED" *) - input AXI_00_ACLK; - input [36:0] AXI_00_ARADDR; - input [1:0] AXI_00_ARBURST; - (* invertible_pin = "IS_AXI_00_ARESET_N_INVERTED" *) - input AXI_00_ARESET_N; - input [5:0] AXI_00_ARID; - input [3:0] AXI_00_ARLEN; - input [2:0] AXI_00_ARSIZE; - input AXI_00_ARVALID; - input [36:0] AXI_00_AWADDR; - input [1:0] AXI_00_AWBURST; - input [5:0] AXI_00_AWID; - input [3:0] AXI_00_AWLEN; - input [2:0] AXI_00_AWSIZE; - input AXI_00_AWVALID; - input AXI_00_BREADY; - input AXI_00_DFI_LP_PWR_X_REQ; - input AXI_00_RREADY; - input [255:0] AXI_00_WDATA; - input [31:0] AXI_00_WDATA_PARITY; - input AXI_00_WLAST; - input [31:0] AXI_00_WSTRB; - input AXI_00_WVALID; - (* invertible_pin = "IS_AXI_01_ACLK_INVERTED" *) - input AXI_01_ACLK; - input [36:0] AXI_01_ARADDR; - input [1:0] AXI_01_ARBURST; - (* invertible_pin = "IS_AXI_01_ARESET_N_INVERTED" *) - input AXI_01_ARESET_N; - input [5:0] AXI_01_ARID; - input [3:0] AXI_01_ARLEN; - input [2:0] AXI_01_ARSIZE; - input AXI_01_ARVALID; - input [36:0] AXI_01_AWADDR; - input [1:0] AXI_01_AWBURST; - input [5:0] AXI_01_AWID; - input [3:0] AXI_01_AWLEN; - input [2:0] AXI_01_AWSIZE; - input AXI_01_AWVALID; - input AXI_01_BREADY; - input AXI_01_DFI_LP_PWR_X_REQ; - input AXI_01_RREADY; - input [255:0] AXI_01_WDATA; - input [31:0] AXI_01_WDATA_PARITY; - input AXI_01_WLAST; - input [31:0] AXI_01_WSTRB; - input AXI_01_WVALID; - (* invertible_pin = "IS_AXI_02_ACLK_INVERTED" *) - input AXI_02_ACLK; - input [36:0] AXI_02_ARADDR; - input [1:0] AXI_02_ARBURST; - (* invertible_pin = "IS_AXI_02_ARESET_N_INVERTED" *) - input AXI_02_ARESET_N; - input [5:0] AXI_02_ARID; - input [3:0] AXI_02_ARLEN; - input [2:0] AXI_02_ARSIZE; - input AXI_02_ARVALID; - input [36:0] AXI_02_AWADDR; - input [1:0] AXI_02_AWBURST; - input [5:0] AXI_02_AWID; - input [3:0] AXI_02_AWLEN; - input [2:0] AXI_02_AWSIZE; - input AXI_02_AWVALID; - input AXI_02_BREADY; - input AXI_02_DFI_LP_PWR_X_REQ; - input AXI_02_RREADY; - input [255:0] AXI_02_WDATA; - input [31:0] AXI_02_WDATA_PARITY; - input AXI_02_WLAST; - input [31:0] AXI_02_WSTRB; - input AXI_02_WVALID; - (* invertible_pin = "IS_AXI_03_ACLK_INVERTED" *) - input AXI_03_ACLK; - input [36:0] AXI_03_ARADDR; - input [1:0] AXI_03_ARBURST; - (* invertible_pin = "IS_AXI_03_ARESET_N_INVERTED" *) - input AXI_03_ARESET_N; - input [5:0] AXI_03_ARID; - input [3:0] AXI_03_ARLEN; - input [2:0] AXI_03_ARSIZE; - input AXI_03_ARVALID; - input [36:0] AXI_03_AWADDR; - input [1:0] AXI_03_AWBURST; - input [5:0] AXI_03_AWID; - input [3:0] AXI_03_AWLEN; - input [2:0] AXI_03_AWSIZE; - input AXI_03_AWVALID; - input AXI_03_BREADY; - input AXI_03_DFI_LP_PWR_X_REQ; - input AXI_03_RREADY; - input [255:0] AXI_03_WDATA; - input [31:0] AXI_03_WDATA_PARITY; - input AXI_03_WLAST; - input [31:0] AXI_03_WSTRB; - input AXI_03_WVALID; - (* invertible_pin = "IS_AXI_04_ACLK_INVERTED" *) - input AXI_04_ACLK; - input [36:0] AXI_04_ARADDR; - input [1:0] AXI_04_ARBURST; - (* invertible_pin = "IS_AXI_04_ARESET_N_INVERTED" *) - input AXI_04_ARESET_N; - input [5:0] AXI_04_ARID; - input [3:0] AXI_04_ARLEN; - input [2:0] AXI_04_ARSIZE; - input AXI_04_ARVALID; - input [36:0] AXI_04_AWADDR; - input [1:0] AXI_04_AWBURST; - input [5:0] AXI_04_AWID; - input [3:0] AXI_04_AWLEN; - input [2:0] AXI_04_AWSIZE; - input AXI_04_AWVALID; - input AXI_04_BREADY; - input AXI_04_DFI_LP_PWR_X_REQ; - input AXI_04_RREADY; - input [255:0] AXI_04_WDATA; - input [31:0] AXI_04_WDATA_PARITY; - input AXI_04_WLAST; - input [31:0] AXI_04_WSTRB; - input AXI_04_WVALID; - (* invertible_pin = "IS_AXI_05_ACLK_INVERTED" *) - input AXI_05_ACLK; - input [36:0] AXI_05_ARADDR; - input [1:0] AXI_05_ARBURST; - (* invertible_pin = "IS_AXI_05_ARESET_N_INVERTED" *) - input AXI_05_ARESET_N; - input [5:0] AXI_05_ARID; - input [3:0] AXI_05_ARLEN; - input [2:0] AXI_05_ARSIZE; - input AXI_05_ARVALID; - input [36:0] AXI_05_AWADDR; - input [1:0] AXI_05_AWBURST; - input [5:0] AXI_05_AWID; - input [3:0] AXI_05_AWLEN; - input [2:0] AXI_05_AWSIZE; - input AXI_05_AWVALID; - input AXI_05_BREADY; - input AXI_05_DFI_LP_PWR_X_REQ; - input AXI_05_RREADY; - input [255:0] AXI_05_WDATA; - input [31:0] AXI_05_WDATA_PARITY; - input AXI_05_WLAST; - input [31:0] AXI_05_WSTRB; - input AXI_05_WVALID; - (* invertible_pin = "IS_AXI_06_ACLK_INVERTED" *) - input AXI_06_ACLK; - input [36:0] AXI_06_ARADDR; - input [1:0] AXI_06_ARBURST; - (* invertible_pin = "IS_AXI_06_ARESET_N_INVERTED" *) - input AXI_06_ARESET_N; - input [5:0] AXI_06_ARID; - input [3:0] AXI_06_ARLEN; - input [2:0] AXI_06_ARSIZE; - input AXI_06_ARVALID; - input [36:0] AXI_06_AWADDR; - input [1:0] AXI_06_AWBURST; - input [5:0] AXI_06_AWID; - input [3:0] AXI_06_AWLEN; - input [2:0] AXI_06_AWSIZE; - input AXI_06_AWVALID; - input AXI_06_BREADY; - input AXI_06_DFI_LP_PWR_X_REQ; - input AXI_06_RREADY; - input [255:0] AXI_06_WDATA; - input [31:0] AXI_06_WDATA_PARITY; - input AXI_06_WLAST; - input [31:0] AXI_06_WSTRB; - input AXI_06_WVALID; - (* invertible_pin = "IS_AXI_07_ACLK_INVERTED" *) - input AXI_07_ACLK; - input [36:0] AXI_07_ARADDR; - input [1:0] AXI_07_ARBURST; - (* invertible_pin = "IS_AXI_07_ARESET_N_INVERTED" *) - input AXI_07_ARESET_N; - input [5:0] AXI_07_ARID; - input [3:0] AXI_07_ARLEN; - input [2:0] AXI_07_ARSIZE; - input AXI_07_ARVALID; - input [36:0] AXI_07_AWADDR; - input [1:0] AXI_07_AWBURST; - input [5:0] AXI_07_AWID; - input [3:0] AXI_07_AWLEN; - input [2:0] AXI_07_AWSIZE; - input AXI_07_AWVALID; - input AXI_07_BREADY; - input AXI_07_DFI_LP_PWR_X_REQ; - input AXI_07_RREADY; - input [255:0] AXI_07_WDATA; - input [31:0] AXI_07_WDATA_PARITY; - input AXI_07_WLAST; - input [31:0] AXI_07_WSTRB; - input AXI_07_WVALID; - (* invertible_pin = "IS_AXI_08_ACLK_INVERTED" *) - input AXI_08_ACLK; - input [36:0] AXI_08_ARADDR; - input [1:0] AXI_08_ARBURST; - (* invertible_pin = "IS_AXI_08_ARESET_N_INVERTED" *) - input AXI_08_ARESET_N; - input [5:0] AXI_08_ARID; - input [3:0] AXI_08_ARLEN; - input [2:0] AXI_08_ARSIZE; - input AXI_08_ARVALID; - input [36:0] AXI_08_AWADDR; - input [1:0] AXI_08_AWBURST; - input [5:0] AXI_08_AWID; - input [3:0] AXI_08_AWLEN; - input [2:0] AXI_08_AWSIZE; - input AXI_08_AWVALID; - input AXI_08_BREADY; - input AXI_08_DFI_LP_PWR_X_REQ; - input AXI_08_RREADY; - input [255:0] AXI_08_WDATA; - input [31:0] AXI_08_WDATA_PARITY; - input AXI_08_WLAST; - input [31:0] AXI_08_WSTRB; - input AXI_08_WVALID; - (* invertible_pin = "IS_AXI_09_ACLK_INVERTED" *) - input AXI_09_ACLK; - input [36:0] AXI_09_ARADDR; - input [1:0] AXI_09_ARBURST; - (* invertible_pin = "IS_AXI_09_ARESET_N_INVERTED" *) - input AXI_09_ARESET_N; - input [5:0] AXI_09_ARID; - input [3:0] AXI_09_ARLEN; - input [2:0] AXI_09_ARSIZE; - input AXI_09_ARVALID; - input [36:0] AXI_09_AWADDR; - input [1:0] AXI_09_AWBURST; - input [5:0] AXI_09_AWID; - input [3:0] AXI_09_AWLEN; - input [2:0] AXI_09_AWSIZE; - input AXI_09_AWVALID; - input AXI_09_BREADY; - input AXI_09_DFI_LP_PWR_X_REQ; - input AXI_09_RREADY; - input [255:0] AXI_09_WDATA; - input [31:0] AXI_09_WDATA_PARITY; - input AXI_09_WLAST; - input [31:0] AXI_09_WSTRB; - input AXI_09_WVALID; - (* invertible_pin = "IS_AXI_10_ACLK_INVERTED" *) - input AXI_10_ACLK; - input [36:0] AXI_10_ARADDR; - input [1:0] AXI_10_ARBURST; - (* invertible_pin = "IS_AXI_10_ARESET_N_INVERTED" *) - input AXI_10_ARESET_N; - input [5:0] AXI_10_ARID; - input [3:0] AXI_10_ARLEN; - input [2:0] AXI_10_ARSIZE; - input AXI_10_ARVALID; - input [36:0] AXI_10_AWADDR; - input [1:0] AXI_10_AWBURST; - input [5:0] AXI_10_AWID; - input [3:0] AXI_10_AWLEN; - input [2:0] AXI_10_AWSIZE; - input AXI_10_AWVALID; - input AXI_10_BREADY; - input AXI_10_DFI_LP_PWR_X_REQ; - input AXI_10_RREADY; - input [255:0] AXI_10_WDATA; - input [31:0] AXI_10_WDATA_PARITY; - input AXI_10_WLAST; - input [31:0] AXI_10_WSTRB; - input AXI_10_WVALID; - (* invertible_pin = "IS_AXI_11_ACLK_INVERTED" *) - input AXI_11_ACLK; - input [36:0] AXI_11_ARADDR; - input [1:0] AXI_11_ARBURST; - (* invertible_pin = "IS_AXI_11_ARESET_N_INVERTED" *) - input AXI_11_ARESET_N; - input [5:0] AXI_11_ARID; - input [3:0] AXI_11_ARLEN; - input [2:0] AXI_11_ARSIZE; - input AXI_11_ARVALID; - input [36:0] AXI_11_AWADDR; - input [1:0] AXI_11_AWBURST; - input [5:0] AXI_11_AWID; - input [3:0] AXI_11_AWLEN; - input [2:0] AXI_11_AWSIZE; - input AXI_11_AWVALID; - input AXI_11_BREADY; - input AXI_11_DFI_LP_PWR_X_REQ; - input AXI_11_RREADY; - input [255:0] AXI_11_WDATA; - input [31:0] AXI_11_WDATA_PARITY; - input AXI_11_WLAST; - input [31:0] AXI_11_WSTRB; - input AXI_11_WVALID; - (* invertible_pin = "IS_AXI_12_ACLK_INVERTED" *) - input AXI_12_ACLK; - input [36:0] AXI_12_ARADDR; - input [1:0] AXI_12_ARBURST; - (* invertible_pin = "IS_AXI_12_ARESET_N_INVERTED" *) - input AXI_12_ARESET_N; - input [5:0] AXI_12_ARID; - input [3:0] AXI_12_ARLEN; - input [2:0] AXI_12_ARSIZE; - input AXI_12_ARVALID; - input [36:0] AXI_12_AWADDR; - input [1:0] AXI_12_AWBURST; - input [5:0] AXI_12_AWID; - input [3:0] AXI_12_AWLEN; - input [2:0] AXI_12_AWSIZE; - input AXI_12_AWVALID; - input AXI_12_BREADY; - input AXI_12_DFI_LP_PWR_X_REQ; - input AXI_12_RREADY; - input [255:0] AXI_12_WDATA; - input [31:0] AXI_12_WDATA_PARITY; - input AXI_12_WLAST; - input [31:0] AXI_12_WSTRB; - input AXI_12_WVALID; - (* invertible_pin = "IS_AXI_13_ACLK_INVERTED" *) - input AXI_13_ACLK; - input [36:0] AXI_13_ARADDR; - input [1:0] AXI_13_ARBURST; - (* invertible_pin = "IS_AXI_13_ARESET_N_INVERTED" *) - input AXI_13_ARESET_N; - input [5:0] AXI_13_ARID; - input [3:0] AXI_13_ARLEN; - input [2:0] AXI_13_ARSIZE; - input AXI_13_ARVALID; - input [36:0] AXI_13_AWADDR; - input [1:0] AXI_13_AWBURST; - input [5:0] AXI_13_AWID; - input [3:0] AXI_13_AWLEN; - input [2:0] AXI_13_AWSIZE; - input AXI_13_AWVALID; - input AXI_13_BREADY; - input AXI_13_DFI_LP_PWR_X_REQ; - input AXI_13_RREADY; - input [255:0] AXI_13_WDATA; - input [31:0] AXI_13_WDATA_PARITY; - input AXI_13_WLAST; - input [31:0] AXI_13_WSTRB; - input AXI_13_WVALID; - (* invertible_pin = "IS_AXI_14_ACLK_INVERTED" *) - input AXI_14_ACLK; - input [36:0] AXI_14_ARADDR; - input [1:0] AXI_14_ARBURST; - (* invertible_pin = "IS_AXI_14_ARESET_N_INVERTED" *) - input AXI_14_ARESET_N; - input [5:0] AXI_14_ARID; - input [3:0] AXI_14_ARLEN; - input [2:0] AXI_14_ARSIZE; - input AXI_14_ARVALID; - input [36:0] AXI_14_AWADDR; - input [1:0] AXI_14_AWBURST; - input [5:0] AXI_14_AWID; - input [3:0] AXI_14_AWLEN; - input [2:0] AXI_14_AWSIZE; - input AXI_14_AWVALID; - input AXI_14_BREADY; - input AXI_14_DFI_LP_PWR_X_REQ; - input AXI_14_RREADY; - input [255:0] AXI_14_WDATA; - input [31:0] AXI_14_WDATA_PARITY; - input AXI_14_WLAST; - input [31:0] AXI_14_WSTRB; - input AXI_14_WVALID; - (* invertible_pin = "IS_AXI_15_ACLK_INVERTED" *) - input AXI_15_ACLK; - input [36:0] AXI_15_ARADDR; - input [1:0] AXI_15_ARBURST; - (* invertible_pin = "IS_AXI_15_ARESET_N_INVERTED" *) - input AXI_15_ARESET_N; - input [5:0] AXI_15_ARID; - input [3:0] AXI_15_ARLEN; - input [2:0] AXI_15_ARSIZE; - input AXI_15_ARVALID; - input [36:0] AXI_15_AWADDR; - input [1:0] AXI_15_AWBURST; - input [5:0] AXI_15_AWID; - input [3:0] AXI_15_AWLEN; - input [2:0] AXI_15_AWSIZE; - input AXI_15_AWVALID; - input AXI_15_BREADY; - input AXI_15_DFI_LP_PWR_X_REQ; - input AXI_15_RREADY; - input [255:0] AXI_15_WDATA; - input [31:0] AXI_15_WDATA_PARITY; - input AXI_15_WLAST; - input [31:0] AXI_15_WSTRB; - input AXI_15_WVALID; - input BSCAN_DRCK; - input BSCAN_TCK; - input HBM_REF_CLK; - input MBIST_EN_00; - input MBIST_EN_01; - input MBIST_EN_02; - input MBIST_EN_03; - input MBIST_EN_04; - input MBIST_EN_05; - input MBIST_EN_06; - input MBIST_EN_07; -endmodule - -(* keep *) -module HBM_TWO_STACK_INTF (...); - parameter CLK_SEL_00 = "FALSE"; - parameter CLK_SEL_01 = "FALSE"; - parameter CLK_SEL_02 = "FALSE"; - parameter CLK_SEL_03 = "FALSE"; - parameter CLK_SEL_04 = "FALSE"; - parameter CLK_SEL_05 = "FALSE"; - parameter CLK_SEL_06 = "FALSE"; - parameter CLK_SEL_07 = "FALSE"; - parameter CLK_SEL_08 = "FALSE"; - parameter CLK_SEL_09 = "FALSE"; - parameter CLK_SEL_10 = "FALSE"; - parameter CLK_SEL_11 = "FALSE"; - parameter CLK_SEL_12 = "FALSE"; - parameter CLK_SEL_13 = "FALSE"; - parameter CLK_SEL_14 = "FALSE"; - parameter CLK_SEL_15 = "FALSE"; - parameter CLK_SEL_16 = "FALSE"; - parameter CLK_SEL_17 = "FALSE"; - parameter CLK_SEL_18 = "FALSE"; - parameter CLK_SEL_19 = "FALSE"; - parameter CLK_SEL_20 = "FALSE"; - parameter CLK_SEL_21 = "FALSE"; - parameter CLK_SEL_22 = "FALSE"; - parameter CLK_SEL_23 = "FALSE"; - parameter CLK_SEL_24 = "FALSE"; - parameter CLK_SEL_25 = "FALSE"; - parameter CLK_SEL_26 = "FALSE"; - parameter CLK_SEL_27 = "FALSE"; - parameter CLK_SEL_28 = "FALSE"; - parameter CLK_SEL_29 = "FALSE"; - parameter CLK_SEL_30 = "FALSE"; - parameter CLK_SEL_31 = "FALSE"; - parameter integer DATARATE_00 = 1800; - parameter integer DATARATE_01 = 1800; - parameter integer DATARATE_02 = 1800; - parameter integer DATARATE_03 = 1800; - parameter integer DATARATE_04 = 1800; - parameter integer DATARATE_05 = 1800; - parameter integer DATARATE_06 = 1800; - parameter integer DATARATE_07 = 1800; - parameter integer DATARATE_08 = 1800; - parameter integer DATARATE_09 = 1800; - parameter integer DATARATE_10 = 1800; - parameter integer DATARATE_11 = 1800; - parameter integer DATARATE_12 = 1800; - parameter integer DATARATE_13 = 1800; - parameter integer DATARATE_14 = 1800; - parameter integer DATARATE_15 = 1800; - parameter DA_LOCKOUT_0 = "FALSE"; - parameter DA_LOCKOUT_1 = "FALSE"; - parameter [0:0] IS_APB_0_PCLK_INVERTED = 1'b0; - parameter [0:0] IS_APB_0_PRESET_N_INVERTED = 1'b0; - parameter [0:0] IS_APB_1_PCLK_INVERTED = 1'b0; - parameter [0:0] IS_APB_1_PRESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_00_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_00_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_01_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_01_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_02_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_02_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_03_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_03_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_04_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_04_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_05_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_05_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_06_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_06_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_07_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_07_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_08_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_08_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_09_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_09_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_10_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_10_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_11_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_11_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_12_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_12_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_13_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_13_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_14_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_14_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_15_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_15_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_16_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_16_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_17_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_17_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_18_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_18_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_19_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_19_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_20_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_20_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_21_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_21_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_22_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_22_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_23_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_23_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_24_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_24_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_25_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_25_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_26_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_26_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_27_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_27_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_28_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_28_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_29_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_29_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_30_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_30_ARESET_N_INVERTED = 1'b0; - parameter [0:0] IS_AXI_31_ACLK_INVERTED = 1'b0; - parameter [0:0] IS_AXI_31_ARESET_N_INVERTED = 1'b0; - parameter MC_ENABLE_00 = "FALSE"; - parameter MC_ENABLE_01 = "FALSE"; - parameter MC_ENABLE_02 = "FALSE"; - parameter MC_ENABLE_03 = "FALSE"; - parameter MC_ENABLE_04 = "FALSE"; - parameter MC_ENABLE_05 = "FALSE"; - parameter MC_ENABLE_06 = "FALSE"; - parameter MC_ENABLE_07 = "FALSE"; - parameter MC_ENABLE_08 = "FALSE"; - parameter MC_ENABLE_09 = "FALSE"; - parameter MC_ENABLE_10 = "FALSE"; - parameter MC_ENABLE_11 = "FALSE"; - parameter MC_ENABLE_12 = "FALSE"; - parameter MC_ENABLE_13 = "FALSE"; - parameter MC_ENABLE_14 = "FALSE"; - parameter MC_ENABLE_15 = "FALSE"; - parameter MC_ENABLE_APB_00 = "FALSE"; - parameter MC_ENABLE_APB_01 = "FALSE"; - parameter integer PAGEHIT_PERCENT_00 = 75; - parameter integer PAGEHIT_PERCENT_01 = 75; - parameter PHY_ENABLE_00 = "FALSE"; - parameter PHY_ENABLE_01 = "FALSE"; - parameter PHY_ENABLE_02 = "FALSE"; - parameter PHY_ENABLE_03 = "FALSE"; - parameter PHY_ENABLE_04 = "FALSE"; - parameter PHY_ENABLE_05 = "FALSE"; - parameter PHY_ENABLE_06 = "FALSE"; - parameter PHY_ENABLE_07 = "FALSE"; - parameter PHY_ENABLE_08 = "FALSE"; - parameter PHY_ENABLE_09 = "FALSE"; - parameter PHY_ENABLE_10 = "FALSE"; - parameter PHY_ENABLE_11 = "FALSE"; - parameter PHY_ENABLE_12 = "FALSE"; - parameter PHY_ENABLE_13 = "FALSE"; - parameter PHY_ENABLE_14 = "FALSE"; - parameter PHY_ENABLE_15 = "FALSE"; - parameter PHY_ENABLE_16 = "FALSE"; - parameter PHY_ENABLE_17 = "FALSE"; - parameter PHY_ENABLE_18 = "FALSE"; - parameter PHY_ENABLE_19 = "FALSE"; - parameter PHY_ENABLE_20 = "FALSE"; - parameter PHY_ENABLE_21 = "FALSE"; - parameter PHY_ENABLE_22 = "FALSE"; - parameter PHY_ENABLE_23 = "FALSE"; - parameter PHY_ENABLE_24 = "FALSE"; - parameter PHY_ENABLE_25 = "FALSE"; - parameter PHY_ENABLE_26 = "FALSE"; - parameter PHY_ENABLE_27 = "FALSE"; - parameter PHY_ENABLE_28 = "FALSE"; - parameter PHY_ENABLE_29 = "FALSE"; - parameter PHY_ENABLE_30 = "FALSE"; - parameter PHY_ENABLE_31 = "FALSE"; - parameter PHY_ENABLE_APB_00 = "FALSE"; - parameter PHY_ENABLE_APB_01 = "FALSE"; - parameter PHY_PCLK_INVERT_01 = "FALSE"; - parameter PHY_PCLK_INVERT_02 = "FALSE"; - parameter integer READ_PERCENT_00 = 50; - parameter integer READ_PERCENT_01 = 50; - parameter integer READ_PERCENT_02 = 50; - parameter integer READ_PERCENT_03 = 50; - parameter integer READ_PERCENT_04 = 50; - parameter integer READ_PERCENT_05 = 50; - parameter integer READ_PERCENT_06 = 50; - parameter integer READ_PERCENT_07 = 50; - parameter integer READ_PERCENT_08 = 50; - parameter integer READ_PERCENT_09 = 50; - parameter integer READ_PERCENT_10 = 50; - parameter integer READ_PERCENT_11 = 50; - parameter integer READ_PERCENT_12 = 50; - parameter integer READ_PERCENT_13 = 50; - parameter integer READ_PERCENT_14 = 50; - parameter integer READ_PERCENT_15 = 50; - parameter integer READ_PERCENT_16 = 50; - parameter integer READ_PERCENT_17 = 50; - parameter integer READ_PERCENT_18 = 50; - parameter integer READ_PERCENT_19 = 50; - parameter integer READ_PERCENT_20 = 50; - parameter integer READ_PERCENT_21 = 50; - parameter integer READ_PERCENT_22 = 50; - parameter integer READ_PERCENT_23 = 50; - parameter integer READ_PERCENT_24 = 50; - parameter integer READ_PERCENT_25 = 50; - parameter integer READ_PERCENT_26 = 50; - parameter integer READ_PERCENT_27 = 50; - parameter integer READ_PERCENT_28 = 50; - parameter integer READ_PERCENT_29 = 50; - parameter integer READ_PERCENT_30 = 50; - parameter integer READ_PERCENT_31 = 50; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter SWITCH_ENABLE_00 = "FALSE"; - parameter SWITCH_ENABLE_01 = "FALSE"; - parameter integer WRITE_PERCENT_00 = 50; - parameter integer WRITE_PERCENT_01 = 50; - parameter integer WRITE_PERCENT_02 = 50; - parameter integer WRITE_PERCENT_03 = 50; - parameter integer WRITE_PERCENT_04 = 50; - parameter integer WRITE_PERCENT_05 = 50; - parameter integer WRITE_PERCENT_06 = 50; - parameter integer WRITE_PERCENT_07 = 50; - parameter integer WRITE_PERCENT_08 = 50; - parameter integer WRITE_PERCENT_09 = 50; - parameter integer WRITE_PERCENT_10 = 50; - parameter integer WRITE_PERCENT_11 = 50; - parameter integer WRITE_PERCENT_12 = 50; - parameter integer WRITE_PERCENT_13 = 50; - parameter integer WRITE_PERCENT_14 = 50; - parameter integer WRITE_PERCENT_15 = 50; - parameter integer WRITE_PERCENT_16 = 50; - parameter integer WRITE_PERCENT_17 = 50; - parameter integer WRITE_PERCENT_18 = 50; - parameter integer WRITE_PERCENT_19 = 50; - parameter integer WRITE_PERCENT_20 = 50; - parameter integer WRITE_PERCENT_21 = 50; - parameter integer WRITE_PERCENT_22 = 50; - parameter integer WRITE_PERCENT_23 = 50; - parameter integer WRITE_PERCENT_24 = 50; - parameter integer WRITE_PERCENT_25 = 50; - parameter integer WRITE_PERCENT_26 = 50; - parameter integer WRITE_PERCENT_27 = 50; - parameter integer WRITE_PERCENT_28 = 50; - parameter integer WRITE_PERCENT_29 = 50; - parameter integer WRITE_PERCENT_30 = 50; - parameter integer WRITE_PERCENT_31 = 50; - output [31:0] APB_0_PRDATA; - output APB_0_PREADY; - output APB_0_PSLVERR; - output [31:0] APB_1_PRDATA; - output APB_1_PREADY; - output APB_1_PSLVERR; - output AXI_00_ARREADY; - output AXI_00_AWREADY; - output [5:0] AXI_00_BID; - output [1:0] AXI_00_BRESP; - output AXI_00_BVALID; - output [1:0] AXI_00_DFI_AW_AERR_N; - output AXI_00_DFI_CLK_BUF; - output [7:0] AXI_00_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_00_DFI_DW_RDDATA_DBI; - output [7:0] AXI_00_DFI_DW_RDDATA_DERR; - output [1:0] AXI_00_DFI_DW_RDDATA_VALID; - output AXI_00_DFI_INIT_COMPLETE; - output AXI_00_DFI_PHYUPD_REQ; - output AXI_00_DFI_PHY_LP_STATE; - output AXI_00_DFI_RST_N_BUF; - output [5:0] AXI_00_MC_STATUS; - output [7:0] AXI_00_PHY_STATUS; - output [255:0] AXI_00_RDATA; - output [31:0] AXI_00_RDATA_PARITY; - output [5:0] AXI_00_RID; - output AXI_00_RLAST; - output [1:0] AXI_00_RRESP; - output AXI_00_RVALID; - output AXI_00_WREADY; - output AXI_01_ARREADY; - output AXI_01_AWREADY; - output [5:0] AXI_01_BID; - output [1:0] AXI_01_BRESP; - output AXI_01_BVALID; - output [1:0] AXI_01_DFI_AW_AERR_N; - output AXI_01_DFI_CLK_BUF; - output [7:0] AXI_01_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_01_DFI_DW_RDDATA_DBI; - output [7:0] AXI_01_DFI_DW_RDDATA_DERR; - output [1:0] AXI_01_DFI_DW_RDDATA_VALID; - output AXI_01_DFI_INIT_COMPLETE; - output AXI_01_DFI_PHYUPD_REQ; - output AXI_01_DFI_PHY_LP_STATE; - output AXI_01_DFI_RST_N_BUF; - output [255:0] AXI_01_RDATA; - output [31:0] AXI_01_RDATA_PARITY; - output [5:0] AXI_01_RID; - output AXI_01_RLAST; - output [1:0] AXI_01_RRESP; - output AXI_01_RVALID; - output AXI_01_WREADY; - output AXI_02_ARREADY; - output AXI_02_AWREADY; - output [5:0] AXI_02_BID; - output [1:0] AXI_02_BRESP; - output AXI_02_BVALID; - output [1:0] AXI_02_DFI_AW_AERR_N; - output AXI_02_DFI_CLK_BUF; - output [7:0] AXI_02_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_02_DFI_DW_RDDATA_DBI; - output [7:0] AXI_02_DFI_DW_RDDATA_DERR; - output [1:0] AXI_02_DFI_DW_RDDATA_VALID; - output AXI_02_DFI_INIT_COMPLETE; - output AXI_02_DFI_PHYUPD_REQ; - output AXI_02_DFI_PHY_LP_STATE; - output AXI_02_DFI_RST_N_BUF; - output [5:0] AXI_02_MC_STATUS; - output [7:0] AXI_02_PHY_STATUS; - output [255:0] AXI_02_RDATA; - output [31:0] AXI_02_RDATA_PARITY; - output [5:0] AXI_02_RID; - output AXI_02_RLAST; - output [1:0] AXI_02_RRESP; - output AXI_02_RVALID; - output AXI_02_WREADY; - output AXI_03_ARREADY; - output AXI_03_AWREADY; - output [5:0] AXI_03_BID; - output [1:0] AXI_03_BRESP; - output AXI_03_BVALID; - output [1:0] AXI_03_DFI_AW_AERR_N; - output AXI_03_DFI_CLK_BUF; - output [7:0] AXI_03_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_03_DFI_DW_RDDATA_DBI; - output [7:0] AXI_03_DFI_DW_RDDATA_DERR; - output [1:0] AXI_03_DFI_DW_RDDATA_VALID; - output AXI_03_DFI_INIT_COMPLETE; - output AXI_03_DFI_PHYUPD_REQ; - output AXI_03_DFI_PHY_LP_STATE; - output AXI_03_DFI_RST_N_BUF; - output [255:0] AXI_03_RDATA; - output [31:0] AXI_03_RDATA_PARITY; - output [5:0] AXI_03_RID; - output AXI_03_RLAST; - output [1:0] AXI_03_RRESP; - output AXI_03_RVALID; - output AXI_03_WREADY; - output AXI_04_ARREADY; - output AXI_04_AWREADY; - output [5:0] AXI_04_BID; - output [1:0] AXI_04_BRESP; - output AXI_04_BVALID; - output [1:0] AXI_04_DFI_AW_AERR_N; - output AXI_04_DFI_CLK_BUF; - output [7:0] AXI_04_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_04_DFI_DW_RDDATA_DBI; - output [7:0] AXI_04_DFI_DW_RDDATA_DERR; - output [1:0] AXI_04_DFI_DW_RDDATA_VALID; - output AXI_04_DFI_INIT_COMPLETE; - output AXI_04_DFI_PHYUPD_REQ; - output AXI_04_DFI_PHY_LP_STATE; - output AXI_04_DFI_RST_N_BUF; - output [5:0] AXI_04_MC_STATUS; - output [7:0] AXI_04_PHY_STATUS; - output [255:0] AXI_04_RDATA; - output [31:0] AXI_04_RDATA_PARITY; - output [5:0] AXI_04_RID; - output AXI_04_RLAST; - output [1:0] AXI_04_RRESP; - output AXI_04_RVALID; - output AXI_04_WREADY; - output AXI_05_ARREADY; - output AXI_05_AWREADY; - output [5:0] AXI_05_BID; - output [1:0] AXI_05_BRESP; - output AXI_05_BVALID; - output [1:0] AXI_05_DFI_AW_AERR_N; - output AXI_05_DFI_CLK_BUF; - output [7:0] AXI_05_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_05_DFI_DW_RDDATA_DBI; - output [7:0] AXI_05_DFI_DW_RDDATA_DERR; - output [1:0] AXI_05_DFI_DW_RDDATA_VALID; - output AXI_05_DFI_INIT_COMPLETE; - output AXI_05_DFI_PHYUPD_REQ; - output AXI_05_DFI_PHY_LP_STATE; - output AXI_05_DFI_RST_N_BUF; - output [255:0] AXI_05_RDATA; - output [31:0] AXI_05_RDATA_PARITY; - output [5:0] AXI_05_RID; - output AXI_05_RLAST; - output [1:0] AXI_05_RRESP; - output AXI_05_RVALID; - output AXI_05_WREADY; - output AXI_06_ARREADY; - output AXI_06_AWREADY; - output [5:0] AXI_06_BID; - output [1:0] AXI_06_BRESP; - output AXI_06_BVALID; - output [1:0] AXI_06_DFI_AW_AERR_N; - output AXI_06_DFI_CLK_BUF; - output [7:0] AXI_06_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_06_DFI_DW_RDDATA_DBI; - output [7:0] AXI_06_DFI_DW_RDDATA_DERR; - output [1:0] AXI_06_DFI_DW_RDDATA_VALID; - output AXI_06_DFI_INIT_COMPLETE; - output AXI_06_DFI_PHYUPD_REQ; - output AXI_06_DFI_PHY_LP_STATE; - output AXI_06_DFI_RST_N_BUF; - output [5:0] AXI_06_MC_STATUS; - output [7:0] AXI_06_PHY_STATUS; - output [255:0] AXI_06_RDATA; - output [31:0] AXI_06_RDATA_PARITY; - output [5:0] AXI_06_RID; - output AXI_06_RLAST; - output [1:0] AXI_06_RRESP; - output AXI_06_RVALID; - output AXI_06_WREADY; - output AXI_07_ARREADY; - output AXI_07_AWREADY; - output [5:0] AXI_07_BID; - output [1:0] AXI_07_BRESP; - output AXI_07_BVALID; - output [1:0] AXI_07_DFI_AW_AERR_N; - output AXI_07_DFI_CLK_BUF; - output [7:0] AXI_07_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_07_DFI_DW_RDDATA_DBI; - output [7:0] AXI_07_DFI_DW_RDDATA_DERR; - output [1:0] AXI_07_DFI_DW_RDDATA_VALID; - output AXI_07_DFI_INIT_COMPLETE; - output AXI_07_DFI_PHYUPD_REQ; - output AXI_07_DFI_PHY_LP_STATE; - output AXI_07_DFI_RST_N_BUF; - output [255:0] AXI_07_RDATA; - output [31:0] AXI_07_RDATA_PARITY; - output [5:0] AXI_07_RID; - output AXI_07_RLAST; - output [1:0] AXI_07_RRESP; - output AXI_07_RVALID; - output AXI_07_WREADY; - output AXI_08_ARREADY; - output AXI_08_AWREADY; - output [5:0] AXI_08_BID; - output [1:0] AXI_08_BRESP; - output AXI_08_BVALID; - output [1:0] AXI_08_DFI_AW_AERR_N; - output AXI_08_DFI_CLK_BUF; - output [7:0] AXI_08_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_08_DFI_DW_RDDATA_DBI; - output [7:0] AXI_08_DFI_DW_RDDATA_DERR; - output [1:0] AXI_08_DFI_DW_RDDATA_VALID; - output AXI_08_DFI_INIT_COMPLETE; - output AXI_08_DFI_PHYUPD_REQ; - output AXI_08_DFI_PHY_LP_STATE; - output AXI_08_DFI_RST_N_BUF; - output [5:0] AXI_08_MC_STATUS; - output [7:0] AXI_08_PHY_STATUS; - output [255:0] AXI_08_RDATA; - output [31:0] AXI_08_RDATA_PARITY; - output [5:0] AXI_08_RID; - output AXI_08_RLAST; - output [1:0] AXI_08_RRESP; - output AXI_08_RVALID; - output AXI_08_WREADY; - output AXI_09_ARREADY; - output AXI_09_AWREADY; - output [5:0] AXI_09_BID; - output [1:0] AXI_09_BRESP; - output AXI_09_BVALID; - output [1:0] AXI_09_DFI_AW_AERR_N; - output AXI_09_DFI_CLK_BUF; - output [7:0] AXI_09_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_09_DFI_DW_RDDATA_DBI; - output [7:0] AXI_09_DFI_DW_RDDATA_DERR; - output [1:0] AXI_09_DFI_DW_RDDATA_VALID; - output AXI_09_DFI_INIT_COMPLETE; - output AXI_09_DFI_PHYUPD_REQ; - output AXI_09_DFI_PHY_LP_STATE; - output AXI_09_DFI_RST_N_BUF; - output [255:0] AXI_09_RDATA; - output [31:0] AXI_09_RDATA_PARITY; - output [5:0] AXI_09_RID; - output AXI_09_RLAST; - output [1:0] AXI_09_RRESP; - output AXI_09_RVALID; - output AXI_09_WREADY; - output AXI_10_ARREADY; - output AXI_10_AWREADY; - output [5:0] AXI_10_BID; - output [1:0] AXI_10_BRESP; - output AXI_10_BVALID; - output [1:0] AXI_10_DFI_AW_AERR_N; - output AXI_10_DFI_CLK_BUF; - output [7:0] AXI_10_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_10_DFI_DW_RDDATA_DBI; - output [7:0] AXI_10_DFI_DW_RDDATA_DERR; - output [1:0] AXI_10_DFI_DW_RDDATA_VALID; - output AXI_10_DFI_INIT_COMPLETE; - output AXI_10_DFI_PHYUPD_REQ; - output AXI_10_DFI_PHY_LP_STATE; - output AXI_10_DFI_RST_N_BUF; - output [5:0] AXI_10_MC_STATUS; - output [7:0] AXI_10_PHY_STATUS; - output [255:0] AXI_10_RDATA; - output [31:0] AXI_10_RDATA_PARITY; - output [5:0] AXI_10_RID; - output AXI_10_RLAST; - output [1:0] AXI_10_RRESP; - output AXI_10_RVALID; - output AXI_10_WREADY; - output AXI_11_ARREADY; - output AXI_11_AWREADY; - output [5:0] AXI_11_BID; - output [1:0] AXI_11_BRESP; - output AXI_11_BVALID; - output [1:0] AXI_11_DFI_AW_AERR_N; - output AXI_11_DFI_CLK_BUF; - output [7:0] AXI_11_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_11_DFI_DW_RDDATA_DBI; - output [7:0] AXI_11_DFI_DW_RDDATA_DERR; - output [1:0] AXI_11_DFI_DW_RDDATA_VALID; - output AXI_11_DFI_INIT_COMPLETE; - output AXI_11_DFI_PHYUPD_REQ; - output AXI_11_DFI_PHY_LP_STATE; - output AXI_11_DFI_RST_N_BUF; - output [255:0] AXI_11_RDATA; - output [31:0] AXI_11_RDATA_PARITY; - output [5:0] AXI_11_RID; - output AXI_11_RLAST; - output [1:0] AXI_11_RRESP; - output AXI_11_RVALID; - output AXI_11_WREADY; - output AXI_12_ARREADY; - output AXI_12_AWREADY; - output [5:0] AXI_12_BID; - output [1:0] AXI_12_BRESP; - output AXI_12_BVALID; - output [1:0] AXI_12_DFI_AW_AERR_N; - output AXI_12_DFI_CLK_BUF; - output [7:0] AXI_12_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_12_DFI_DW_RDDATA_DBI; - output [7:0] AXI_12_DFI_DW_RDDATA_DERR; - output [1:0] AXI_12_DFI_DW_RDDATA_VALID; - output AXI_12_DFI_INIT_COMPLETE; - output AXI_12_DFI_PHYUPD_REQ; - output AXI_12_DFI_PHY_LP_STATE; - output AXI_12_DFI_RST_N_BUF; - output [5:0] AXI_12_MC_STATUS; - output [7:0] AXI_12_PHY_STATUS; - output [255:0] AXI_12_RDATA; - output [31:0] AXI_12_RDATA_PARITY; - output [5:0] AXI_12_RID; - output AXI_12_RLAST; - output [1:0] AXI_12_RRESP; - output AXI_12_RVALID; - output AXI_12_WREADY; - output AXI_13_ARREADY; - output AXI_13_AWREADY; - output [5:0] AXI_13_BID; - output [1:0] AXI_13_BRESP; - output AXI_13_BVALID; - output [1:0] AXI_13_DFI_AW_AERR_N; - output AXI_13_DFI_CLK_BUF; - output [7:0] AXI_13_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_13_DFI_DW_RDDATA_DBI; - output [7:0] AXI_13_DFI_DW_RDDATA_DERR; - output [1:0] AXI_13_DFI_DW_RDDATA_VALID; - output AXI_13_DFI_INIT_COMPLETE; - output AXI_13_DFI_PHYUPD_REQ; - output AXI_13_DFI_PHY_LP_STATE; - output AXI_13_DFI_RST_N_BUF; - output [255:0] AXI_13_RDATA; - output [31:0] AXI_13_RDATA_PARITY; - output [5:0] AXI_13_RID; - output AXI_13_RLAST; - output [1:0] AXI_13_RRESP; - output AXI_13_RVALID; - output AXI_13_WREADY; - output AXI_14_ARREADY; - output AXI_14_AWREADY; - output [5:0] AXI_14_BID; - output [1:0] AXI_14_BRESP; - output AXI_14_BVALID; - output [1:0] AXI_14_DFI_AW_AERR_N; - output AXI_14_DFI_CLK_BUF; - output [7:0] AXI_14_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_14_DFI_DW_RDDATA_DBI; - output [7:0] AXI_14_DFI_DW_RDDATA_DERR; - output [1:0] AXI_14_DFI_DW_RDDATA_VALID; - output AXI_14_DFI_INIT_COMPLETE; - output AXI_14_DFI_PHYUPD_REQ; - output AXI_14_DFI_PHY_LP_STATE; - output AXI_14_DFI_RST_N_BUF; - output [5:0] AXI_14_MC_STATUS; - output [7:0] AXI_14_PHY_STATUS; - output [255:0] AXI_14_RDATA; - output [31:0] AXI_14_RDATA_PARITY; - output [5:0] AXI_14_RID; - output AXI_14_RLAST; - output [1:0] AXI_14_RRESP; - output AXI_14_RVALID; - output AXI_14_WREADY; - output AXI_15_ARREADY; - output AXI_15_AWREADY; - output [5:0] AXI_15_BID; - output [1:0] AXI_15_BRESP; - output AXI_15_BVALID; - output [1:0] AXI_15_DFI_AW_AERR_N; - output AXI_15_DFI_CLK_BUF; - output [7:0] AXI_15_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_15_DFI_DW_RDDATA_DBI; - output [7:0] AXI_15_DFI_DW_RDDATA_DERR; - output [1:0] AXI_15_DFI_DW_RDDATA_VALID; - output AXI_15_DFI_INIT_COMPLETE; - output AXI_15_DFI_PHYUPD_REQ; - output AXI_15_DFI_PHY_LP_STATE; - output AXI_15_DFI_RST_N_BUF; - output [255:0] AXI_15_RDATA; - output [31:0] AXI_15_RDATA_PARITY; - output [5:0] AXI_15_RID; - output AXI_15_RLAST; - output [1:0] AXI_15_RRESP; - output AXI_15_RVALID; - output AXI_15_WREADY; - output AXI_16_ARREADY; - output AXI_16_AWREADY; - output [5:0] AXI_16_BID; - output [1:0] AXI_16_BRESP; - output AXI_16_BVALID; - output [1:0] AXI_16_DFI_AW_AERR_N; - output AXI_16_DFI_CLK_BUF; - output [7:0] AXI_16_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_16_DFI_DW_RDDATA_DBI; - output [7:0] AXI_16_DFI_DW_RDDATA_DERR; - output [1:0] AXI_16_DFI_DW_RDDATA_VALID; - output AXI_16_DFI_INIT_COMPLETE; - output AXI_16_DFI_PHYUPD_REQ; - output AXI_16_DFI_PHY_LP_STATE; - output AXI_16_DFI_RST_N_BUF; - output [5:0] AXI_16_MC_STATUS; - output [7:0] AXI_16_PHY_STATUS; - output [255:0] AXI_16_RDATA; - output [31:0] AXI_16_RDATA_PARITY; - output [5:0] AXI_16_RID; - output AXI_16_RLAST; - output [1:0] AXI_16_RRESP; - output AXI_16_RVALID; - output AXI_16_WREADY; - output AXI_17_ARREADY; - output AXI_17_AWREADY; - output [5:0] AXI_17_BID; - output [1:0] AXI_17_BRESP; - output AXI_17_BVALID; - output [1:0] AXI_17_DFI_AW_AERR_N; - output AXI_17_DFI_CLK_BUF; - output [7:0] AXI_17_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_17_DFI_DW_RDDATA_DBI; - output [7:0] AXI_17_DFI_DW_RDDATA_DERR; - output [1:0] AXI_17_DFI_DW_RDDATA_VALID; - output AXI_17_DFI_INIT_COMPLETE; - output AXI_17_DFI_PHYUPD_REQ; - output AXI_17_DFI_PHY_LP_STATE; - output AXI_17_DFI_RST_N_BUF; - output [255:0] AXI_17_RDATA; - output [31:0] AXI_17_RDATA_PARITY; - output [5:0] AXI_17_RID; - output AXI_17_RLAST; - output [1:0] AXI_17_RRESP; - output AXI_17_RVALID; - output AXI_17_WREADY; - output AXI_18_ARREADY; - output AXI_18_AWREADY; - output [5:0] AXI_18_BID; - output [1:0] AXI_18_BRESP; - output AXI_18_BVALID; - output [1:0] AXI_18_DFI_AW_AERR_N; - output AXI_18_DFI_CLK_BUF; - output [7:0] AXI_18_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_18_DFI_DW_RDDATA_DBI; - output [7:0] AXI_18_DFI_DW_RDDATA_DERR; - output [1:0] AXI_18_DFI_DW_RDDATA_VALID; - output AXI_18_DFI_INIT_COMPLETE; - output AXI_18_DFI_PHYUPD_REQ; - output AXI_18_DFI_PHY_LP_STATE; - output AXI_18_DFI_RST_N_BUF; - output [5:0] AXI_18_MC_STATUS; - output [7:0] AXI_18_PHY_STATUS; - output [255:0] AXI_18_RDATA; - output [31:0] AXI_18_RDATA_PARITY; - output [5:0] AXI_18_RID; - output AXI_18_RLAST; - output [1:0] AXI_18_RRESP; - output AXI_18_RVALID; - output AXI_18_WREADY; - output AXI_19_ARREADY; - output AXI_19_AWREADY; - output [5:0] AXI_19_BID; - output [1:0] AXI_19_BRESP; - output AXI_19_BVALID; - output [1:0] AXI_19_DFI_AW_AERR_N; - output AXI_19_DFI_CLK_BUF; - output [7:0] AXI_19_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_19_DFI_DW_RDDATA_DBI; - output [7:0] AXI_19_DFI_DW_RDDATA_DERR; - output [1:0] AXI_19_DFI_DW_RDDATA_VALID; - output AXI_19_DFI_INIT_COMPLETE; - output AXI_19_DFI_PHYUPD_REQ; - output AXI_19_DFI_PHY_LP_STATE; - output AXI_19_DFI_RST_N_BUF; - output [255:0] AXI_19_RDATA; - output [31:0] AXI_19_RDATA_PARITY; - output [5:0] AXI_19_RID; - output AXI_19_RLAST; - output [1:0] AXI_19_RRESP; - output AXI_19_RVALID; - output AXI_19_WREADY; - output AXI_20_ARREADY; - output AXI_20_AWREADY; - output [5:0] AXI_20_BID; - output [1:0] AXI_20_BRESP; - output AXI_20_BVALID; - output [1:0] AXI_20_DFI_AW_AERR_N; - output AXI_20_DFI_CLK_BUF; - output [7:0] AXI_20_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_20_DFI_DW_RDDATA_DBI; - output [7:0] AXI_20_DFI_DW_RDDATA_DERR; - output [1:0] AXI_20_DFI_DW_RDDATA_VALID; - output AXI_20_DFI_INIT_COMPLETE; - output AXI_20_DFI_PHYUPD_REQ; - output AXI_20_DFI_PHY_LP_STATE; - output AXI_20_DFI_RST_N_BUF; - output [5:0] AXI_20_MC_STATUS; - output [7:0] AXI_20_PHY_STATUS; - output [255:0] AXI_20_RDATA; - output [31:0] AXI_20_RDATA_PARITY; - output [5:0] AXI_20_RID; - output AXI_20_RLAST; - output [1:0] AXI_20_RRESP; - output AXI_20_RVALID; - output AXI_20_WREADY; - output AXI_21_ARREADY; - output AXI_21_AWREADY; - output [5:0] AXI_21_BID; - output [1:0] AXI_21_BRESP; - output AXI_21_BVALID; - output [1:0] AXI_21_DFI_AW_AERR_N; - output AXI_21_DFI_CLK_BUF; - output [7:0] AXI_21_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_21_DFI_DW_RDDATA_DBI; - output [7:0] AXI_21_DFI_DW_RDDATA_DERR; - output [1:0] AXI_21_DFI_DW_RDDATA_VALID; - output AXI_21_DFI_INIT_COMPLETE; - output AXI_21_DFI_PHYUPD_REQ; - output AXI_21_DFI_PHY_LP_STATE; - output AXI_21_DFI_RST_N_BUF; - output [255:0] AXI_21_RDATA; - output [31:0] AXI_21_RDATA_PARITY; - output [5:0] AXI_21_RID; - output AXI_21_RLAST; - output [1:0] AXI_21_RRESP; - output AXI_21_RVALID; - output AXI_21_WREADY; - output AXI_22_ARREADY; - output AXI_22_AWREADY; - output [5:0] AXI_22_BID; - output [1:0] AXI_22_BRESP; - output AXI_22_BVALID; - output [1:0] AXI_22_DFI_AW_AERR_N; - output AXI_22_DFI_CLK_BUF; - output [7:0] AXI_22_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_22_DFI_DW_RDDATA_DBI; - output [7:0] AXI_22_DFI_DW_RDDATA_DERR; - output [1:0] AXI_22_DFI_DW_RDDATA_VALID; - output AXI_22_DFI_INIT_COMPLETE; - output AXI_22_DFI_PHYUPD_REQ; - output AXI_22_DFI_PHY_LP_STATE; - output AXI_22_DFI_RST_N_BUF; - output [5:0] AXI_22_MC_STATUS; - output [7:0] AXI_22_PHY_STATUS; - output [255:0] AXI_22_RDATA; - output [31:0] AXI_22_RDATA_PARITY; - output [5:0] AXI_22_RID; - output AXI_22_RLAST; - output [1:0] AXI_22_RRESP; - output AXI_22_RVALID; - output AXI_22_WREADY; - output AXI_23_ARREADY; - output AXI_23_AWREADY; - output [5:0] AXI_23_BID; - output [1:0] AXI_23_BRESP; - output AXI_23_BVALID; - output [1:0] AXI_23_DFI_AW_AERR_N; - output AXI_23_DFI_CLK_BUF; - output [7:0] AXI_23_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_23_DFI_DW_RDDATA_DBI; - output [7:0] AXI_23_DFI_DW_RDDATA_DERR; - output [1:0] AXI_23_DFI_DW_RDDATA_VALID; - output AXI_23_DFI_INIT_COMPLETE; - output AXI_23_DFI_PHYUPD_REQ; - output AXI_23_DFI_PHY_LP_STATE; - output AXI_23_DFI_RST_N_BUF; - output [255:0] AXI_23_RDATA; - output [31:0] AXI_23_RDATA_PARITY; - output [5:0] AXI_23_RID; - output AXI_23_RLAST; - output [1:0] AXI_23_RRESP; - output AXI_23_RVALID; - output AXI_23_WREADY; - output AXI_24_ARREADY; - output AXI_24_AWREADY; - output [5:0] AXI_24_BID; - output [1:0] AXI_24_BRESP; - output AXI_24_BVALID; - output [1:0] AXI_24_DFI_AW_AERR_N; - output AXI_24_DFI_CLK_BUF; - output [7:0] AXI_24_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_24_DFI_DW_RDDATA_DBI; - output [7:0] AXI_24_DFI_DW_RDDATA_DERR; - output [1:0] AXI_24_DFI_DW_RDDATA_VALID; - output AXI_24_DFI_INIT_COMPLETE; - output AXI_24_DFI_PHYUPD_REQ; - output AXI_24_DFI_PHY_LP_STATE; - output AXI_24_DFI_RST_N_BUF; - output [5:0] AXI_24_MC_STATUS; - output [7:0] AXI_24_PHY_STATUS; - output [255:0] AXI_24_RDATA; - output [31:0] AXI_24_RDATA_PARITY; - output [5:0] AXI_24_RID; - output AXI_24_RLAST; - output [1:0] AXI_24_RRESP; - output AXI_24_RVALID; - output AXI_24_WREADY; - output AXI_25_ARREADY; - output AXI_25_AWREADY; - output [5:0] AXI_25_BID; - output [1:0] AXI_25_BRESP; - output AXI_25_BVALID; - output [1:0] AXI_25_DFI_AW_AERR_N; - output AXI_25_DFI_CLK_BUF; - output [7:0] AXI_25_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_25_DFI_DW_RDDATA_DBI; - output [7:0] AXI_25_DFI_DW_RDDATA_DERR; - output [1:0] AXI_25_DFI_DW_RDDATA_VALID; - output AXI_25_DFI_INIT_COMPLETE; - output AXI_25_DFI_PHYUPD_REQ; - output AXI_25_DFI_PHY_LP_STATE; - output AXI_25_DFI_RST_N_BUF; - output [255:0] AXI_25_RDATA; - output [31:0] AXI_25_RDATA_PARITY; - output [5:0] AXI_25_RID; - output AXI_25_RLAST; - output [1:0] AXI_25_RRESP; - output AXI_25_RVALID; - output AXI_25_WREADY; - output AXI_26_ARREADY; - output AXI_26_AWREADY; - output [5:0] AXI_26_BID; - output [1:0] AXI_26_BRESP; - output AXI_26_BVALID; - output [1:0] AXI_26_DFI_AW_AERR_N; - output AXI_26_DFI_CLK_BUF; - output [7:0] AXI_26_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_26_DFI_DW_RDDATA_DBI; - output [7:0] AXI_26_DFI_DW_RDDATA_DERR; - output [1:0] AXI_26_DFI_DW_RDDATA_VALID; - output AXI_26_DFI_INIT_COMPLETE; - output AXI_26_DFI_PHYUPD_REQ; - output AXI_26_DFI_PHY_LP_STATE; - output AXI_26_DFI_RST_N_BUF; - output [5:0] AXI_26_MC_STATUS; - output [7:0] AXI_26_PHY_STATUS; - output [255:0] AXI_26_RDATA; - output [31:0] AXI_26_RDATA_PARITY; - output [5:0] AXI_26_RID; - output AXI_26_RLAST; - output [1:0] AXI_26_RRESP; - output AXI_26_RVALID; - output AXI_26_WREADY; - output AXI_27_ARREADY; - output AXI_27_AWREADY; - output [5:0] AXI_27_BID; - output [1:0] AXI_27_BRESP; - output AXI_27_BVALID; - output [1:0] AXI_27_DFI_AW_AERR_N; - output AXI_27_DFI_CLK_BUF; - output [7:0] AXI_27_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_27_DFI_DW_RDDATA_DBI; - output [7:0] AXI_27_DFI_DW_RDDATA_DERR; - output [1:0] AXI_27_DFI_DW_RDDATA_VALID; - output AXI_27_DFI_INIT_COMPLETE; - output AXI_27_DFI_PHYUPD_REQ; - output AXI_27_DFI_PHY_LP_STATE; - output AXI_27_DFI_RST_N_BUF; - output [255:0] AXI_27_RDATA; - output [31:0] AXI_27_RDATA_PARITY; - output [5:0] AXI_27_RID; - output AXI_27_RLAST; - output [1:0] AXI_27_RRESP; - output AXI_27_RVALID; - output AXI_27_WREADY; - output AXI_28_ARREADY; - output AXI_28_AWREADY; - output [5:0] AXI_28_BID; - output [1:0] AXI_28_BRESP; - output AXI_28_BVALID; - output [1:0] AXI_28_DFI_AW_AERR_N; - output AXI_28_DFI_CLK_BUF; - output [7:0] AXI_28_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_28_DFI_DW_RDDATA_DBI; - output [7:0] AXI_28_DFI_DW_RDDATA_DERR; - output [1:0] AXI_28_DFI_DW_RDDATA_VALID; - output AXI_28_DFI_INIT_COMPLETE; - output AXI_28_DFI_PHYUPD_REQ; - output AXI_28_DFI_PHY_LP_STATE; - output AXI_28_DFI_RST_N_BUF; - output [5:0] AXI_28_MC_STATUS; - output [7:0] AXI_28_PHY_STATUS; - output [255:0] AXI_28_RDATA; - output [31:0] AXI_28_RDATA_PARITY; - output [5:0] AXI_28_RID; - output AXI_28_RLAST; - output [1:0] AXI_28_RRESP; - output AXI_28_RVALID; - output AXI_28_WREADY; - output AXI_29_ARREADY; - output AXI_29_AWREADY; - output [5:0] AXI_29_BID; - output [1:0] AXI_29_BRESP; - output AXI_29_BVALID; - output [1:0] AXI_29_DFI_AW_AERR_N; - output AXI_29_DFI_CLK_BUF; - output [7:0] AXI_29_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_29_DFI_DW_RDDATA_DBI; - output [7:0] AXI_29_DFI_DW_RDDATA_DERR; - output [1:0] AXI_29_DFI_DW_RDDATA_VALID; - output AXI_29_DFI_INIT_COMPLETE; - output AXI_29_DFI_PHYUPD_REQ; - output AXI_29_DFI_PHY_LP_STATE; - output AXI_29_DFI_RST_N_BUF; - output [255:0] AXI_29_RDATA; - output [31:0] AXI_29_RDATA_PARITY; - output [5:0] AXI_29_RID; - output AXI_29_RLAST; - output [1:0] AXI_29_RRESP; - output AXI_29_RVALID; - output AXI_29_WREADY; - output AXI_30_ARREADY; - output AXI_30_AWREADY; - output [5:0] AXI_30_BID; - output [1:0] AXI_30_BRESP; - output AXI_30_BVALID; - output [1:0] AXI_30_DFI_AW_AERR_N; - output AXI_30_DFI_CLK_BUF; - output [7:0] AXI_30_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_30_DFI_DW_RDDATA_DBI; - output [7:0] AXI_30_DFI_DW_RDDATA_DERR; - output [1:0] AXI_30_DFI_DW_RDDATA_VALID; - output AXI_30_DFI_INIT_COMPLETE; - output AXI_30_DFI_PHYUPD_REQ; - output AXI_30_DFI_PHY_LP_STATE; - output AXI_30_DFI_RST_N_BUF; - output [5:0] AXI_30_MC_STATUS; - output [7:0] AXI_30_PHY_STATUS; - output [255:0] AXI_30_RDATA; - output [31:0] AXI_30_RDATA_PARITY; - output [5:0] AXI_30_RID; - output AXI_30_RLAST; - output [1:0] AXI_30_RRESP; - output AXI_30_RVALID; - output AXI_30_WREADY; - output AXI_31_ARREADY; - output AXI_31_AWREADY; - output [5:0] AXI_31_BID; - output [1:0] AXI_31_BRESP; - output AXI_31_BVALID; - output [1:0] AXI_31_DFI_AW_AERR_N; - output AXI_31_DFI_CLK_BUF; - output [7:0] AXI_31_DFI_DBI_BYTE_DISABLE; - output [20:0] AXI_31_DFI_DW_RDDATA_DBI; - output [7:0] AXI_31_DFI_DW_RDDATA_DERR; - output [1:0] AXI_31_DFI_DW_RDDATA_VALID; - output AXI_31_DFI_INIT_COMPLETE; - output AXI_31_DFI_PHYUPD_REQ; - output AXI_31_DFI_PHY_LP_STATE; - output AXI_31_DFI_RST_N_BUF; - output [255:0] AXI_31_RDATA; - output [31:0] AXI_31_RDATA_PARITY; - output [5:0] AXI_31_RID; - output AXI_31_RLAST; - output [1:0] AXI_31_RRESP; - output AXI_31_RVALID; - output AXI_31_WREADY; - output DRAM_0_STAT_CATTRIP; - output [2:0] DRAM_0_STAT_TEMP; - output DRAM_1_STAT_CATTRIP; - output [2:0] DRAM_1_STAT_TEMP; - input [21:0] APB_0_PADDR; - (* invertible_pin = "IS_APB_0_PCLK_INVERTED" *) - input APB_0_PCLK; - input APB_0_PENABLE; - (* invertible_pin = "IS_APB_0_PRESET_N_INVERTED" *) - input APB_0_PRESET_N; - input APB_0_PSEL; - input [31:0] APB_0_PWDATA; - input APB_0_PWRITE; - input [21:0] APB_1_PADDR; - (* invertible_pin = "IS_APB_1_PCLK_INVERTED" *) - input APB_1_PCLK; - input APB_1_PENABLE; - (* invertible_pin = "IS_APB_1_PRESET_N_INVERTED" *) - input APB_1_PRESET_N; - input APB_1_PSEL; - input [31:0] APB_1_PWDATA; - input APB_1_PWRITE; - (* invertible_pin = "IS_AXI_00_ACLK_INVERTED" *) - input AXI_00_ACLK; - input [36:0] AXI_00_ARADDR; - input [1:0] AXI_00_ARBURST; - (* invertible_pin = "IS_AXI_00_ARESET_N_INVERTED" *) - input AXI_00_ARESET_N; - input [5:0] AXI_00_ARID; - input [3:0] AXI_00_ARLEN; - input [2:0] AXI_00_ARSIZE; - input AXI_00_ARVALID; - input [36:0] AXI_00_AWADDR; - input [1:0] AXI_00_AWBURST; - input [5:0] AXI_00_AWID; - input [3:0] AXI_00_AWLEN; - input [2:0] AXI_00_AWSIZE; - input AXI_00_AWVALID; - input AXI_00_BREADY; - input AXI_00_DFI_LP_PWR_X_REQ; - input AXI_00_RREADY; - input [255:0] AXI_00_WDATA; - input [31:0] AXI_00_WDATA_PARITY; - input AXI_00_WLAST; - input [31:0] AXI_00_WSTRB; - input AXI_00_WVALID; - (* invertible_pin = "IS_AXI_01_ACLK_INVERTED" *) - input AXI_01_ACLK; - input [36:0] AXI_01_ARADDR; - input [1:0] AXI_01_ARBURST; - (* invertible_pin = "IS_AXI_01_ARESET_N_INVERTED" *) - input AXI_01_ARESET_N; - input [5:0] AXI_01_ARID; - input [3:0] AXI_01_ARLEN; - input [2:0] AXI_01_ARSIZE; - input AXI_01_ARVALID; - input [36:0] AXI_01_AWADDR; - input [1:0] AXI_01_AWBURST; - input [5:0] AXI_01_AWID; - input [3:0] AXI_01_AWLEN; - input [2:0] AXI_01_AWSIZE; - input AXI_01_AWVALID; - input AXI_01_BREADY; - input AXI_01_DFI_LP_PWR_X_REQ; - input AXI_01_RREADY; - input [255:0] AXI_01_WDATA; - input [31:0] AXI_01_WDATA_PARITY; - input AXI_01_WLAST; - input [31:0] AXI_01_WSTRB; - input AXI_01_WVALID; - (* invertible_pin = "IS_AXI_02_ACLK_INVERTED" *) - input AXI_02_ACLK; - input [36:0] AXI_02_ARADDR; - input [1:0] AXI_02_ARBURST; - (* invertible_pin = "IS_AXI_02_ARESET_N_INVERTED" *) - input AXI_02_ARESET_N; - input [5:0] AXI_02_ARID; - input [3:0] AXI_02_ARLEN; - input [2:0] AXI_02_ARSIZE; - input AXI_02_ARVALID; - input [36:0] AXI_02_AWADDR; - input [1:0] AXI_02_AWBURST; - input [5:0] AXI_02_AWID; - input [3:0] AXI_02_AWLEN; - input [2:0] AXI_02_AWSIZE; - input AXI_02_AWVALID; - input AXI_02_BREADY; - input AXI_02_DFI_LP_PWR_X_REQ; - input AXI_02_RREADY; - input [255:0] AXI_02_WDATA; - input [31:0] AXI_02_WDATA_PARITY; - input AXI_02_WLAST; - input [31:0] AXI_02_WSTRB; - input AXI_02_WVALID; - (* invertible_pin = "IS_AXI_03_ACLK_INVERTED" *) - input AXI_03_ACLK; - input [36:0] AXI_03_ARADDR; - input [1:0] AXI_03_ARBURST; - (* invertible_pin = "IS_AXI_03_ARESET_N_INVERTED" *) - input AXI_03_ARESET_N; - input [5:0] AXI_03_ARID; - input [3:0] AXI_03_ARLEN; - input [2:0] AXI_03_ARSIZE; - input AXI_03_ARVALID; - input [36:0] AXI_03_AWADDR; - input [1:0] AXI_03_AWBURST; - input [5:0] AXI_03_AWID; - input [3:0] AXI_03_AWLEN; - input [2:0] AXI_03_AWSIZE; - input AXI_03_AWVALID; - input AXI_03_BREADY; - input AXI_03_DFI_LP_PWR_X_REQ; - input AXI_03_RREADY; - input [255:0] AXI_03_WDATA; - input [31:0] AXI_03_WDATA_PARITY; - input AXI_03_WLAST; - input [31:0] AXI_03_WSTRB; - input AXI_03_WVALID; - (* invertible_pin = "IS_AXI_04_ACLK_INVERTED" *) - input AXI_04_ACLK; - input [36:0] AXI_04_ARADDR; - input [1:0] AXI_04_ARBURST; - (* invertible_pin = "IS_AXI_04_ARESET_N_INVERTED" *) - input AXI_04_ARESET_N; - input [5:0] AXI_04_ARID; - input [3:0] AXI_04_ARLEN; - input [2:0] AXI_04_ARSIZE; - input AXI_04_ARVALID; - input [36:0] AXI_04_AWADDR; - input [1:0] AXI_04_AWBURST; - input [5:0] AXI_04_AWID; - input [3:0] AXI_04_AWLEN; - input [2:0] AXI_04_AWSIZE; - input AXI_04_AWVALID; - input AXI_04_BREADY; - input AXI_04_DFI_LP_PWR_X_REQ; - input AXI_04_RREADY; - input [255:0] AXI_04_WDATA; - input [31:0] AXI_04_WDATA_PARITY; - input AXI_04_WLAST; - input [31:0] AXI_04_WSTRB; - input AXI_04_WVALID; - (* invertible_pin = "IS_AXI_05_ACLK_INVERTED" *) - input AXI_05_ACLK; - input [36:0] AXI_05_ARADDR; - input [1:0] AXI_05_ARBURST; - (* invertible_pin = "IS_AXI_05_ARESET_N_INVERTED" *) - input AXI_05_ARESET_N; - input [5:0] AXI_05_ARID; - input [3:0] AXI_05_ARLEN; - input [2:0] AXI_05_ARSIZE; - input AXI_05_ARVALID; - input [36:0] AXI_05_AWADDR; - input [1:0] AXI_05_AWBURST; - input [5:0] AXI_05_AWID; - input [3:0] AXI_05_AWLEN; - input [2:0] AXI_05_AWSIZE; - input AXI_05_AWVALID; - input AXI_05_BREADY; - input AXI_05_DFI_LP_PWR_X_REQ; - input AXI_05_RREADY; - input [255:0] AXI_05_WDATA; - input [31:0] AXI_05_WDATA_PARITY; - input AXI_05_WLAST; - input [31:0] AXI_05_WSTRB; - input AXI_05_WVALID; - (* invertible_pin = "IS_AXI_06_ACLK_INVERTED" *) - input AXI_06_ACLK; - input [36:0] AXI_06_ARADDR; - input [1:0] AXI_06_ARBURST; - (* invertible_pin = "IS_AXI_06_ARESET_N_INVERTED" *) - input AXI_06_ARESET_N; - input [5:0] AXI_06_ARID; - input [3:0] AXI_06_ARLEN; - input [2:0] AXI_06_ARSIZE; - input AXI_06_ARVALID; - input [36:0] AXI_06_AWADDR; - input [1:0] AXI_06_AWBURST; - input [5:0] AXI_06_AWID; - input [3:0] AXI_06_AWLEN; - input [2:0] AXI_06_AWSIZE; - input AXI_06_AWVALID; - input AXI_06_BREADY; - input AXI_06_DFI_LP_PWR_X_REQ; - input AXI_06_RREADY; - input [255:0] AXI_06_WDATA; - input [31:0] AXI_06_WDATA_PARITY; - input AXI_06_WLAST; - input [31:0] AXI_06_WSTRB; - input AXI_06_WVALID; - (* invertible_pin = "IS_AXI_07_ACLK_INVERTED" *) - input AXI_07_ACLK; - input [36:0] AXI_07_ARADDR; - input [1:0] AXI_07_ARBURST; - (* invertible_pin = "IS_AXI_07_ARESET_N_INVERTED" *) - input AXI_07_ARESET_N; - input [5:0] AXI_07_ARID; - input [3:0] AXI_07_ARLEN; - input [2:0] AXI_07_ARSIZE; - input AXI_07_ARVALID; - input [36:0] AXI_07_AWADDR; - input [1:0] AXI_07_AWBURST; - input [5:0] AXI_07_AWID; - input [3:0] AXI_07_AWLEN; - input [2:0] AXI_07_AWSIZE; - input AXI_07_AWVALID; - input AXI_07_BREADY; - input AXI_07_DFI_LP_PWR_X_REQ; - input AXI_07_RREADY; - input [255:0] AXI_07_WDATA; - input [31:0] AXI_07_WDATA_PARITY; - input AXI_07_WLAST; - input [31:0] AXI_07_WSTRB; - input AXI_07_WVALID; - (* invertible_pin = "IS_AXI_08_ACLK_INVERTED" *) - input AXI_08_ACLK; - input [36:0] AXI_08_ARADDR; - input [1:0] AXI_08_ARBURST; - (* invertible_pin = "IS_AXI_08_ARESET_N_INVERTED" *) - input AXI_08_ARESET_N; - input [5:0] AXI_08_ARID; - input [3:0] AXI_08_ARLEN; - input [2:0] AXI_08_ARSIZE; - input AXI_08_ARVALID; - input [36:0] AXI_08_AWADDR; - input [1:0] AXI_08_AWBURST; - input [5:0] AXI_08_AWID; - input [3:0] AXI_08_AWLEN; - input [2:0] AXI_08_AWSIZE; - input AXI_08_AWVALID; - input AXI_08_BREADY; - input AXI_08_DFI_LP_PWR_X_REQ; - input AXI_08_RREADY; - input [255:0] AXI_08_WDATA; - input [31:0] AXI_08_WDATA_PARITY; - input AXI_08_WLAST; - input [31:0] AXI_08_WSTRB; - input AXI_08_WVALID; - (* invertible_pin = "IS_AXI_09_ACLK_INVERTED" *) - input AXI_09_ACLK; - input [36:0] AXI_09_ARADDR; - input [1:0] AXI_09_ARBURST; - (* invertible_pin = "IS_AXI_09_ARESET_N_INVERTED" *) - input AXI_09_ARESET_N; - input [5:0] AXI_09_ARID; - input [3:0] AXI_09_ARLEN; - input [2:0] AXI_09_ARSIZE; - input AXI_09_ARVALID; - input [36:0] AXI_09_AWADDR; - input [1:0] AXI_09_AWBURST; - input [5:0] AXI_09_AWID; - input [3:0] AXI_09_AWLEN; - input [2:0] AXI_09_AWSIZE; - input AXI_09_AWVALID; - input AXI_09_BREADY; - input AXI_09_DFI_LP_PWR_X_REQ; - input AXI_09_RREADY; - input [255:0] AXI_09_WDATA; - input [31:0] AXI_09_WDATA_PARITY; - input AXI_09_WLAST; - input [31:0] AXI_09_WSTRB; - input AXI_09_WVALID; - (* invertible_pin = "IS_AXI_10_ACLK_INVERTED" *) - input AXI_10_ACLK; - input [36:0] AXI_10_ARADDR; - input [1:0] AXI_10_ARBURST; - (* invertible_pin = "IS_AXI_10_ARESET_N_INVERTED" *) - input AXI_10_ARESET_N; - input [5:0] AXI_10_ARID; - input [3:0] AXI_10_ARLEN; - input [2:0] AXI_10_ARSIZE; - input AXI_10_ARVALID; - input [36:0] AXI_10_AWADDR; - input [1:0] AXI_10_AWBURST; - input [5:0] AXI_10_AWID; - input [3:0] AXI_10_AWLEN; - input [2:0] AXI_10_AWSIZE; - input AXI_10_AWVALID; - input AXI_10_BREADY; - input AXI_10_DFI_LP_PWR_X_REQ; - input AXI_10_RREADY; - input [255:0] AXI_10_WDATA; - input [31:0] AXI_10_WDATA_PARITY; - input AXI_10_WLAST; - input [31:0] AXI_10_WSTRB; - input AXI_10_WVALID; - (* invertible_pin = "IS_AXI_11_ACLK_INVERTED" *) - input AXI_11_ACLK; - input [36:0] AXI_11_ARADDR; - input [1:0] AXI_11_ARBURST; - (* invertible_pin = "IS_AXI_11_ARESET_N_INVERTED" *) - input AXI_11_ARESET_N; - input [5:0] AXI_11_ARID; - input [3:0] AXI_11_ARLEN; - input [2:0] AXI_11_ARSIZE; - input AXI_11_ARVALID; - input [36:0] AXI_11_AWADDR; - input [1:0] AXI_11_AWBURST; - input [5:0] AXI_11_AWID; - input [3:0] AXI_11_AWLEN; - input [2:0] AXI_11_AWSIZE; - input AXI_11_AWVALID; - input AXI_11_BREADY; - input AXI_11_DFI_LP_PWR_X_REQ; - input AXI_11_RREADY; - input [255:0] AXI_11_WDATA; - input [31:0] AXI_11_WDATA_PARITY; - input AXI_11_WLAST; - input [31:0] AXI_11_WSTRB; - input AXI_11_WVALID; - (* invertible_pin = "IS_AXI_12_ACLK_INVERTED" *) - input AXI_12_ACLK; - input [36:0] AXI_12_ARADDR; - input [1:0] AXI_12_ARBURST; - (* invertible_pin = "IS_AXI_12_ARESET_N_INVERTED" *) - input AXI_12_ARESET_N; - input [5:0] AXI_12_ARID; - input [3:0] AXI_12_ARLEN; - input [2:0] AXI_12_ARSIZE; - input AXI_12_ARVALID; - input [36:0] AXI_12_AWADDR; - input [1:0] AXI_12_AWBURST; - input [5:0] AXI_12_AWID; - input [3:0] AXI_12_AWLEN; - input [2:0] AXI_12_AWSIZE; - input AXI_12_AWVALID; - input AXI_12_BREADY; - input AXI_12_DFI_LP_PWR_X_REQ; - input AXI_12_RREADY; - input [255:0] AXI_12_WDATA; - input [31:0] AXI_12_WDATA_PARITY; - input AXI_12_WLAST; - input [31:0] AXI_12_WSTRB; - input AXI_12_WVALID; - (* invertible_pin = "IS_AXI_13_ACLK_INVERTED" *) - input AXI_13_ACLK; - input [36:0] AXI_13_ARADDR; - input [1:0] AXI_13_ARBURST; - (* invertible_pin = "IS_AXI_13_ARESET_N_INVERTED" *) - input AXI_13_ARESET_N; - input [5:0] AXI_13_ARID; - input [3:0] AXI_13_ARLEN; - input [2:0] AXI_13_ARSIZE; - input AXI_13_ARVALID; - input [36:0] AXI_13_AWADDR; - input [1:0] AXI_13_AWBURST; - input [5:0] AXI_13_AWID; - input [3:0] AXI_13_AWLEN; - input [2:0] AXI_13_AWSIZE; - input AXI_13_AWVALID; - input AXI_13_BREADY; - input AXI_13_DFI_LP_PWR_X_REQ; - input AXI_13_RREADY; - input [255:0] AXI_13_WDATA; - input [31:0] AXI_13_WDATA_PARITY; - input AXI_13_WLAST; - input [31:0] AXI_13_WSTRB; - input AXI_13_WVALID; - (* invertible_pin = "IS_AXI_14_ACLK_INVERTED" *) - input AXI_14_ACLK; - input [36:0] AXI_14_ARADDR; - input [1:0] AXI_14_ARBURST; - (* invertible_pin = "IS_AXI_14_ARESET_N_INVERTED" *) - input AXI_14_ARESET_N; - input [5:0] AXI_14_ARID; - input [3:0] AXI_14_ARLEN; - input [2:0] AXI_14_ARSIZE; - input AXI_14_ARVALID; - input [36:0] AXI_14_AWADDR; - input [1:0] AXI_14_AWBURST; - input [5:0] AXI_14_AWID; - input [3:0] AXI_14_AWLEN; - input [2:0] AXI_14_AWSIZE; - input AXI_14_AWVALID; - input AXI_14_BREADY; - input AXI_14_DFI_LP_PWR_X_REQ; - input AXI_14_RREADY; - input [255:0] AXI_14_WDATA; - input [31:0] AXI_14_WDATA_PARITY; - input AXI_14_WLAST; - input [31:0] AXI_14_WSTRB; - input AXI_14_WVALID; - (* invertible_pin = "IS_AXI_15_ACLK_INVERTED" *) - input AXI_15_ACLK; - input [36:0] AXI_15_ARADDR; - input [1:0] AXI_15_ARBURST; - (* invertible_pin = "IS_AXI_15_ARESET_N_INVERTED" *) - input AXI_15_ARESET_N; - input [5:0] AXI_15_ARID; - input [3:0] AXI_15_ARLEN; - input [2:0] AXI_15_ARSIZE; - input AXI_15_ARVALID; - input [36:0] AXI_15_AWADDR; - input [1:0] AXI_15_AWBURST; - input [5:0] AXI_15_AWID; - input [3:0] AXI_15_AWLEN; - input [2:0] AXI_15_AWSIZE; - input AXI_15_AWVALID; - input AXI_15_BREADY; - input AXI_15_DFI_LP_PWR_X_REQ; - input AXI_15_RREADY; - input [255:0] AXI_15_WDATA; - input [31:0] AXI_15_WDATA_PARITY; - input AXI_15_WLAST; - input [31:0] AXI_15_WSTRB; - input AXI_15_WVALID; - (* invertible_pin = "IS_AXI_16_ACLK_INVERTED" *) - input AXI_16_ACLK; - input [36:0] AXI_16_ARADDR; - input [1:0] AXI_16_ARBURST; - (* invertible_pin = "IS_AXI_16_ARESET_N_INVERTED" *) - input AXI_16_ARESET_N; - input [5:0] AXI_16_ARID; - input [3:0] AXI_16_ARLEN; - input [2:0] AXI_16_ARSIZE; - input AXI_16_ARVALID; - input [36:0] AXI_16_AWADDR; - input [1:0] AXI_16_AWBURST; - input [5:0] AXI_16_AWID; - input [3:0] AXI_16_AWLEN; - input [2:0] AXI_16_AWSIZE; - input AXI_16_AWVALID; - input AXI_16_BREADY; - input AXI_16_DFI_LP_PWR_X_REQ; - input AXI_16_RREADY; - input [255:0] AXI_16_WDATA; - input [31:0] AXI_16_WDATA_PARITY; - input AXI_16_WLAST; - input [31:0] AXI_16_WSTRB; - input AXI_16_WVALID; - (* invertible_pin = "IS_AXI_17_ACLK_INVERTED" *) - input AXI_17_ACLK; - input [36:0] AXI_17_ARADDR; - input [1:0] AXI_17_ARBURST; - (* invertible_pin = "IS_AXI_17_ARESET_N_INVERTED" *) - input AXI_17_ARESET_N; - input [5:0] AXI_17_ARID; - input [3:0] AXI_17_ARLEN; - input [2:0] AXI_17_ARSIZE; - input AXI_17_ARVALID; - input [36:0] AXI_17_AWADDR; - input [1:0] AXI_17_AWBURST; - input [5:0] AXI_17_AWID; - input [3:0] AXI_17_AWLEN; - input [2:0] AXI_17_AWSIZE; - input AXI_17_AWVALID; - input AXI_17_BREADY; - input AXI_17_DFI_LP_PWR_X_REQ; - input AXI_17_RREADY; - input [255:0] AXI_17_WDATA; - input [31:0] AXI_17_WDATA_PARITY; - input AXI_17_WLAST; - input [31:0] AXI_17_WSTRB; - input AXI_17_WVALID; - (* invertible_pin = "IS_AXI_18_ACLK_INVERTED" *) - input AXI_18_ACLK; - input [36:0] AXI_18_ARADDR; - input [1:0] AXI_18_ARBURST; - (* invertible_pin = "IS_AXI_18_ARESET_N_INVERTED" *) - input AXI_18_ARESET_N; - input [5:0] AXI_18_ARID; - input [3:0] AXI_18_ARLEN; - input [2:0] AXI_18_ARSIZE; - input AXI_18_ARVALID; - input [36:0] AXI_18_AWADDR; - input [1:0] AXI_18_AWBURST; - input [5:0] AXI_18_AWID; - input [3:0] AXI_18_AWLEN; - input [2:0] AXI_18_AWSIZE; - input AXI_18_AWVALID; - input AXI_18_BREADY; - input AXI_18_DFI_LP_PWR_X_REQ; - input AXI_18_RREADY; - input [255:0] AXI_18_WDATA; - input [31:0] AXI_18_WDATA_PARITY; - input AXI_18_WLAST; - input [31:0] AXI_18_WSTRB; - input AXI_18_WVALID; - (* invertible_pin = "IS_AXI_19_ACLK_INVERTED" *) - input AXI_19_ACLK; - input [36:0] AXI_19_ARADDR; - input [1:0] AXI_19_ARBURST; - (* invertible_pin = "IS_AXI_19_ARESET_N_INVERTED" *) - input AXI_19_ARESET_N; - input [5:0] AXI_19_ARID; - input [3:0] AXI_19_ARLEN; - input [2:0] AXI_19_ARSIZE; - input AXI_19_ARVALID; - input [36:0] AXI_19_AWADDR; - input [1:0] AXI_19_AWBURST; - input [5:0] AXI_19_AWID; - input [3:0] AXI_19_AWLEN; - input [2:0] AXI_19_AWSIZE; - input AXI_19_AWVALID; - input AXI_19_BREADY; - input AXI_19_DFI_LP_PWR_X_REQ; - input AXI_19_RREADY; - input [255:0] AXI_19_WDATA; - input [31:0] AXI_19_WDATA_PARITY; - input AXI_19_WLAST; - input [31:0] AXI_19_WSTRB; - input AXI_19_WVALID; - (* invertible_pin = "IS_AXI_20_ACLK_INVERTED" *) - input AXI_20_ACLK; - input [36:0] AXI_20_ARADDR; - input [1:0] AXI_20_ARBURST; - (* invertible_pin = "IS_AXI_20_ARESET_N_INVERTED" *) - input AXI_20_ARESET_N; - input [5:0] AXI_20_ARID; - input [3:0] AXI_20_ARLEN; - input [2:0] AXI_20_ARSIZE; - input AXI_20_ARVALID; - input [36:0] AXI_20_AWADDR; - input [1:0] AXI_20_AWBURST; - input [5:0] AXI_20_AWID; - input [3:0] AXI_20_AWLEN; - input [2:0] AXI_20_AWSIZE; - input AXI_20_AWVALID; - input AXI_20_BREADY; - input AXI_20_DFI_LP_PWR_X_REQ; - input AXI_20_RREADY; - input [255:0] AXI_20_WDATA; - input [31:0] AXI_20_WDATA_PARITY; - input AXI_20_WLAST; - input [31:0] AXI_20_WSTRB; - input AXI_20_WVALID; - (* invertible_pin = "IS_AXI_21_ACLK_INVERTED" *) - input AXI_21_ACLK; - input [36:0] AXI_21_ARADDR; - input [1:0] AXI_21_ARBURST; - (* invertible_pin = "IS_AXI_21_ARESET_N_INVERTED" *) - input AXI_21_ARESET_N; - input [5:0] AXI_21_ARID; - input [3:0] AXI_21_ARLEN; - input [2:0] AXI_21_ARSIZE; - input AXI_21_ARVALID; - input [36:0] AXI_21_AWADDR; - input [1:0] AXI_21_AWBURST; - input [5:0] AXI_21_AWID; - input [3:0] AXI_21_AWLEN; - input [2:0] AXI_21_AWSIZE; - input AXI_21_AWVALID; - input AXI_21_BREADY; - input AXI_21_DFI_LP_PWR_X_REQ; - input AXI_21_RREADY; - input [255:0] AXI_21_WDATA; - input [31:0] AXI_21_WDATA_PARITY; - input AXI_21_WLAST; - input [31:0] AXI_21_WSTRB; - input AXI_21_WVALID; - (* invertible_pin = "IS_AXI_22_ACLK_INVERTED" *) - input AXI_22_ACLK; - input [36:0] AXI_22_ARADDR; - input [1:0] AXI_22_ARBURST; - (* invertible_pin = "IS_AXI_22_ARESET_N_INVERTED" *) - input AXI_22_ARESET_N; - input [5:0] AXI_22_ARID; - input [3:0] AXI_22_ARLEN; - input [2:0] AXI_22_ARSIZE; - input AXI_22_ARVALID; - input [36:0] AXI_22_AWADDR; - input [1:0] AXI_22_AWBURST; - input [5:0] AXI_22_AWID; - input [3:0] AXI_22_AWLEN; - input [2:0] AXI_22_AWSIZE; - input AXI_22_AWVALID; - input AXI_22_BREADY; - input AXI_22_DFI_LP_PWR_X_REQ; - input AXI_22_RREADY; - input [255:0] AXI_22_WDATA; - input [31:0] AXI_22_WDATA_PARITY; - input AXI_22_WLAST; - input [31:0] AXI_22_WSTRB; - input AXI_22_WVALID; - (* invertible_pin = "IS_AXI_23_ACLK_INVERTED" *) - input AXI_23_ACLK; - input [36:0] AXI_23_ARADDR; - input [1:0] AXI_23_ARBURST; - (* invertible_pin = "IS_AXI_23_ARESET_N_INVERTED" *) - input AXI_23_ARESET_N; - input [5:0] AXI_23_ARID; - input [3:0] AXI_23_ARLEN; - input [2:0] AXI_23_ARSIZE; - input AXI_23_ARVALID; - input [36:0] AXI_23_AWADDR; - input [1:0] AXI_23_AWBURST; - input [5:0] AXI_23_AWID; - input [3:0] AXI_23_AWLEN; - input [2:0] AXI_23_AWSIZE; - input AXI_23_AWVALID; - input AXI_23_BREADY; - input AXI_23_DFI_LP_PWR_X_REQ; - input AXI_23_RREADY; - input [255:0] AXI_23_WDATA; - input [31:0] AXI_23_WDATA_PARITY; - input AXI_23_WLAST; - input [31:0] AXI_23_WSTRB; - input AXI_23_WVALID; - (* invertible_pin = "IS_AXI_24_ACLK_INVERTED" *) - input AXI_24_ACLK; - input [36:0] AXI_24_ARADDR; - input [1:0] AXI_24_ARBURST; - (* invertible_pin = "IS_AXI_24_ARESET_N_INVERTED" *) - input AXI_24_ARESET_N; - input [5:0] AXI_24_ARID; - input [3:0] AXI_24_ARLEN; - input [2:0] AXI_24_ARSIZE; - input AXI_24_ARVALID; - input [36:0] AXI_24_AWADDR; - input [1:0] AXI_24_AWBURST; - input [5:0] AXI_24_AWID; - input [3:0] AXI_24_AWLEN; - input [2:0] AXI_24_AWSIZE; - input AXI_24_AWVALID; - input AXI_24_BREADY; - input AXI_24_DFI_LP_PWR_X_REQ; - input AXI_24_RREADY; - input [255:0] AXI_24_WDATA; - input [31:0] AXI_24_WDATA_PARITY; - input AXI_24_WLAST; - input [31:0] AXI_24_WSTRB; - input AXI_24_WVALID; - (* invertible_pin = "IS_AXI_25_ACLK_INVERTED" *) - input AXI_25_ACLK; - input [36:0] AXI_25_ARADDR; - input [1:0] AXI_25_ARBURST; - (* invertible_pin = "IS_AXI_25_ARESET_N_INVERTED" *) - input AXI_25_ARESET_N; - input [5:0] AXI_25_ARID; - input [3:0] AXI_25_ARLEN; - input [2:0] AXI_25_ARSIZE; - input AXI_25_ARVALID; - input [36:0] AXI_25_AWADDR; - input [1:0] AXI_25_AWBURST; - input [5:0] AXI_25_AWID; - input [3:0] AXI_25_AWLEN; - input [2:0] AXI_25_AWSIZE; - input AXI_25_AWVALID; - input AXI_25_BREADY; - input AXI_25_DFI_LP_PWR_X_REQ; - input AXI_25_RREADY; - input [255:0] AXI_25_WDATA; - input [31:0] AXI_25_WDATA_PARITY; - input AXI_25_WLAST; - input [31:0] AXI_25_WSTRB; - input AXI_25_WVALID; - (* invertible_pin = "IS_AXI_26_ACLK_INVERTED" *) - input AXI_26_ACLK; - input [36:0] AXI_26_ARADDR; - input [1:0] AXI_26_ARBURST; - (* invertible_pin = "IS_AXI_26_ARESET_N_INVERTED" *) - input AXI_26_ARESET_N; - input [5:0] AXI_26_ARID; - input [3:0] AXI_26_ARLEN; - input [2:0] AXI_26_ARSIZE; - input AXI_26_ARVALID; - input [36:0] AXI_26_AWADDR; - input [1:0] AXI_26_AWBURST; - input [5:0] AXI_26_AWID; - input [3:0] AXI_26_AWLEN; - input [2:0] AXI_26_AWSIZE; - input AXI_26_AWVALID; - input AXI_26_BREADY; - input AXI_26_DFI_LP_PWR_X_REQ; - input AXI_26_RREADY; - input [255:0] AXI_26_WDATA; - input [31:0] AXI_26_WDATA_PARITY; - input AXI_26_WLAST; - input [31:0] AXI_26_WSTRB; - input AXI_26_WVALID; - (* invertible_pin = "IS_AXI_27_ACLK_INVERTED" *) - input AXI_27_ACLK; - input [36:0] AXI_27_ARADDR; - input [1:0] AXI_27_ARBURST; - (* invertible_pin = "IS_AXI_27_ARESET_N_INVERTED" *) - input AXI_27_ARESET_N; - input [5:0] AXI_27_ARID; - input [3:0] AXI_27_ARLEN; - input [2:0] AXI_27_ARSIZE; - input AXI_27_ARVALID; - input [36:0] AXI_27_AWADDR; - input [1:0] AXI_27_AWBURST; - input [5:0] AXI_27_AWID; - input [3:0] AXI_27_AWLEN; - input [2:0] AXI_27_AWSIZE; - input AXI_27_AWVALID; - input AXI_27_BREADY; - input AXI_27_DFI_LP_PWR_X_REQ; - input AXI_27_RREADY; - input [255:0] AXI_27_WDATA; - input [31:0] AXI_27_WDATA_PARITY; - input AXI_27_WLAST; - input [31:0] AXI_27_WSTRB; - input AXI_27_WVALID; - (* invertible_pin = "IS_AXI_28_ACLK_INVERTED" *) - input AXI_28_ACLK; - input [36:0] AXI_28_ARADDR; - input [1:0] AXI_28_ARBURST; - (* invertible_pin = "IS_AXI_28_ARESET_N_INVERTED" *) - input AXI_28_ARESET_N; - input [5:0] AXI_28_ARID; - input [3:0] AXI_28_ARLEN; - input [2:0] AXI_28_ARSIZE; - input AXI_28_ARVALID; - input [36:0] AXI_28_AWADDR; - input [1:0] AXI_28_AWBURST; - input [5:0] AXI_28_AWID; - input [3:0] AXI_28_AWLEN; - input [2:0] AXI_28_AWSIZE; - input AXI_28_AWVALID; - input AXI_28_BREADY; - input AXI_28_DFI_LP_PWR_X_REQ; - input AXI_28_RREADY; - input [255:0] AXI_28_WDATA; - input [31:0] AXI_28_WDATA_PARITY; - input AXI_28_WLAST; - input [31:0] AXI_28_WSTRB; - input AXI_28_WVALID; - (* invertible_pin = "IS_AXI_29_ACLK_INVERTED" *) - input AXI_29_ACLK; - input [36:0] AXI_29_ARADDR; - input [1:0] AXI_29_ARBURST; - (* invertible_pin = "IS_AXI_29_ARESET_N_INVERTED" *) - input AXI_29_ARESET_N; - input [5:0] AXI_29_ARID; - input [3:0] AXI_29_ARLEN; - input [2:0] AXI_29_ARSIZE; - input AXI_29_ARVALID; - input [36:0] AXI_29_AWADDR; - input [1:0] AXI_29_AWBURST; - input [5:0] AXI_29_AWID; - input [3:0] AXI_29_AWLEN; - input [2:0] AXI_29_AWSIZE; - input AXI_29_AWVALID; - input AXI_29_BREADY; - input AXI_29_DFI_LP_PWR_X_REQ; - input AXI_29_RREADY; - input [255:0] AXI_29_WDATA; - input [31:0] AXI_29_WDATA_PARITY; - input AXI_29_WLAST; - input [31:0] AXI_29_WSTRB; - input AXI_29_WVALID; - (* invertible_pin = "IS_AXI_30_ACLK_INVERTED" *) - input AXI_30_ACLK; - input [36:0] AXI_30_ARADDR; - input [1:0] AXI_30_ARBURST; - (* invertible_pin = "IS_AXI_30_ARESET_N_INVERTED" *) - input AXI_30_ARESET_N; - input [5:0] AXI_30_ARID; - input [3:0] AXI_30_ARLEN; - input [2:0] AXI_30_ARSIZE; - input AXI_30_ARVALID; - input [36:0] AXI_30_AWADDR; - input [1:0] AXI_30_AWBURST; - input [5:0] AXI_30_AWID; - input [3:0] AXI_30_AWLEN; - input [2:0] AXI_30_AWSIZE; - input AXI_30_AWVALID; - input AXI_30_BREADY; - input AXI_30_DFI_LP_PWR_X_REQ; - input AXI_30_RREADY; - input [255:0] AXI_30_WDATA; - input [31:0] AXI_30_WDATA_PARITY; - input AXI_30_WLAST; - input [31:0] AXI_30_WSTRB; - input AXI_30_WVALID; - (* invertible_pin = "IS_AXI_31_ACLK_INVERTED" *) - input AXI_31_ACLK; - input [36:0] AXI_31_ARADDR; - input [1:0] AXI_31_ARBURST; - (* invertible_pin = "IS_AXI_31_ARESET_N_INVERTED" *) - input AXI_31_ARESET_N; - input [5:0] AXI_31_ARID; - input [3:0] AXI_31_ARLEN; - input [2:0] AXI_31_ARSIZE; - input AXI_31_ARVALID; - input [36:0] AXI_31_AWADDR; - input [1:0] AXI_31_AWBURST; - input [5:0] AXI_31_AWID; - input [3:0] AXI_31_AWLEN; - input [2:0] AXI_31_AWSIZE; - input AXI_31_AWVALID; - input AXI_31_BREADY; - input AXI_31_DFI_LP_PWR_X_REQ; - input AXI_31_RREADY; - input [255:0] AXI_31_WDATA; - input [31:0] AXI_31_WDATA_PARITY; - input AXI_31_WLAST; - input [31:0] AXI_31_WSTRB; - input AXI_31_WVALID; - input BSCAN_DRCK_0; - input BSCAN_DRCK_1; - input BSCAN_TCK_0; - input BSCAN_TCK_1; - input HBM_REF_CLK_0; - input HBM_REF_CLK_1; - input MBIST_EN_00; - input MBIST_EN_01; - input MBIST_EN_02; - input MBIST_EN_03; - input MBIST_EN_04; - input MBIST_EN_05; - input MBIST_EN_06; - input MBIST_EN_07; - input MBIST_EN_08; - input MBIST_EN_09; - input MBIST_EN_10; - input MBIST_EN_11; - input MBIST_EN_12; - input MBIST_EN_13; - input MBIST_EN_14; - input MBIST_EN_15; -endmodule - -module PPC405_ADV (...); - parameter in_delay=100; - parameter out_delay=100; - output APUFCMDECODED; - output APUFCMDECUDIVALID; - output APUFCMENDIAN; - output APUFCMFLUSH; - output APUFCMINSTRVALID; - output APUFCMLOADDVALID; - output APUFCMOPERANDVALID; - output APUFCMWRITEBACKOK; - output APUFCMXERCA; - output C405CPMCORESLEEPREQ; - output C405CPMMSRCE; - output C405CPMMSREE; - output C405CPMTIMERIRQ; - output C405CPMTIMERRESETREQ; - output C405DBGLOADDATAONAPUDBUS; - output C405DBGMSRWE; - output C405DBGSTOPACK; - output C405DBGWBCOMPLETE; - output C405DBGWBFULL; - output C405JTGCAPTUREDR; - output C405JTGEXTEST; - output C405JTGPGMOUT; - output C405JTGSHIFTDR; - output C405JTGTDO; - output C405JTGTDOEN; - output C405JTGUPDATEDR; - output C405PLBDCUABORT; - output C405PLBDCUCACHEABLE; - output C405PLBDCUGUARDED; - output C405PLBDCUREQUEST; - output C405PLBDCURNW; - output C405PLBDCUSIZE2; - output C405PLBDCUU0ATTR; - output C405PLBDCUWRITETHRU; - output C405PLBICUABORT; - output C405PLBICUCACHEABLE; - output C405PLBICUREQUEST; - output C405PLBICUU0ATTR; - output C405RSTCHIPRESETREQ; - output C405RSTCORERESETREQ; - output C405RSTSYSRESETREQ; - output C405TRCCYCLE; - output C405TRCTRIGGEREVENTOUT; - output C405XXXMACHINECHECK; - output DCREMACCLK; - output DCREMACENABLER; - output DCREMACREAD; - output DCREMACWRITE; - output DSOCMBRAMEN; - output DSOCMBUSY; - output DSOCMRDADDRVALID; - output DSOCMWRADDRVALID; - output EXTDCRREAD; - output EXTDCRWRITE; - output ISOCMBRAMEN; - output ISOCMBRAMEVENWRITEEN; - output ISOCMBRAMODDWRITEEN; - output ISOCMDCRBRAMEVENEN; - output ISOCMDCRBRAMODDEN; - output ISOCMDCRBRAMRDSELECT; - output [0:10] C405TRCTRIGGEREVENTTYPE; - output [0:1] C405PLBDCUPRIORITY; - output [0:1] C405PLBICUPRIORITY; - output [0:1] C405TRCEVENEXECUTIONSTATUS; - output [0:1] C405TRCODDEXECUTIONSTATUS; - output [0:29] C405DBGWBIAR; - output [0:29] C405PLBICUABUS; - output [0:2] APUFCMDECUDI; - output [0:31] APUFCMINSTRUCTION; - output [0:31] APUFCMLOADDATA; - output [0:31] APUFCMRADATA; - output [0:31] APUFCMRBDATA; - output [0:31] C405PLBDCUABUS; - output [0:31] DCREMACDBUS; - output [0:31] DSOCMBRAMWRDBUS; - output [0:31] EXTDCRDBUSOUT; - output [0:31] ISOCMBRAMWRDBUS; - output [0:3] APUFCMLOADBYTEEN; - output [0:3] C405TRCTRACESTATUS; - output [0:3] DSOCMBRAMBYTEWRITE; - output [0:63] C405PLBDCUWRDBUS; - output [0:7] C405PLBDCUBE; - output [0:9] EXTDCRABUS; - output [2:3] C405PLBICUSIZE; - output [8:28] ISOCMBRAMRDABUS; - output [8:28] ISOCMBRAMWRABUS; - output [8:29] DSOCMBRAMABUS; - output [8:9] DCREMACABUS; - input BRAMDSOCMCLK; - input BRAMISOCMCLK; - input CPMC405CLOCK; - input CPMC405CORECLKINACTIVE; - input CPMC405CPUCLKEN; - input CPMC405JTAGCLKEN; - input CPMC405SYNCBYPASS; - input CPMC405TIMERCLKEN; - input CPMC405TIMERTICK; - input CPMDCRCLK; - input CPMFCMCLK; - input DBGC405DEBUGHALT; - input DBGC405EXTBUSHOLDACK; - input DBGC405UNCONDDEBUGEVENT; - input DSOCMRWCOMPLETE; - input EICC405CRITINPUTIRQ; - input EICC405EXTINPUTIRQ; - input EMACDCRACK; - input EXTDCRACK; - input FCMAPUDCDCREN; - input FCMAPUDCDFORCEALIGN; - input FCMAPUDCDFORCEBESTEERING; - input FCMAPUDCDFPUOP; - input FCMAPUDCDGPRWRITE; - input FCMAPUDCDLDSTBYTE; - input FCMAPUDCDLDSTDW; - input FCMAPUDCDLDSTHW; - input FCMAPUDCDLDSTQW; - input FCMAPUDCDLDSTWD; - input FCMAPUDCDLOAD; - input FCMAPUDCDPRIVOP; - input FCMAPUDCDRAEN; - input FCMAPUDCDRBEN; - input FCMAPUDCDSTORE; - input FCMAPUDCDTRAPBE; - input FCMAPUDCDTRAPLE; - input FCMAPUDCDUPDATE; - input FCMAPUDCDXERCAEN; - input FCMAPUDCDXEROVEN; - input FCMAPUDECODEBUSY; - input FCMAPUDONE; - input FCMAPUEXCEPTION; - input FCMAPUEXEBLOCKINGMCO; - input FCMAPUEXENONBLOCKINGMCO; - input FCMAPUINSTRACK; - input FCMAPULOADWAIT; - input FCMAPURESULTVALID; - input FCMAPUSLEEPNOTREADY; - input FCMAPUXERCA; - input FCMAPUXEROV; - input JTGC405BNDSCANTDO; - input JTGC405TCK; - input JTGC405TDI; - input JTGC405TMS; - input JTGC405TRSTNEG; - input MCBCPUCLKEN; - input MCBJTAGEN; - input MCBTIMEREN; - input MCPPCRST; - input PLBC405DCUADDRACK; - input PLBC405DCUBUSY; - input PLBC405DCUERR; - input PLBC405DCURDDACK; - input PLBC405DCUSSIZE1; - input PLBC405DCUWRDACK; - input PLBC405ICUADDRACK; - input PLBC405ICUBUSY; - input PLBC405ICUERR; - input PLBC405ICURDDACK; - input PLBC405ICUSSIZE1; - input PLBCLK; - input RSTC405RESETCHIP; - input RSTC405RESETCORE; - input RSTC405RESETSYS; - input TIEC405DETERMINISTICMULT; - input TIEC405DISOPERANDFWD; - input TIEC405MMUEN; - input TIEPVRBIT10; - input TIEPVRBIT11; - input TIEPVRBIT28; - input TIEPVRBIT29; - input TIEPVRBIT30; - input TIEPVRBIT31; - input TIEPVRBIT8; - input TIEPVRBIT9; - input TRCC405TRACEDISABLE; - input TRCC405TRIGGEREVENTIN; - input [0:15] TIEAPUCONTROL; - input [0:23] TIEAPUUDI1; - input [0:23] TIEAPUUDI2; - input [0:23] TIEAPUUDI3; - input [0:23] TIEAPUUDI4; - input [0:23] TIEAPUUDI5; - input [0:23] TIEAPUUDI6; - input [0:23] TIEAPUUDI7; - input [0:23] TIEAPUUDI8; - input [0:2] FCMAPUEXECRFIELD; - input [0:31] BRAMDSOCMRDDBUS; - input [0:31] BRAMISOCMDCRRDDBUS; - input [0:31] EMACDCRDBUS; - input [0:31] EXTDCRDBUSIN; - input [0:31] FCMAPURESULT; - input [0:3] FCMAPUCR; - input [0:5] TIEDCRADDR; - input [0:63] BRAMISOCMRDDBUS; - input [0:63] PLBC405DCURDDBUS; - input [0:63] PLBC405ICURDDBUS; - input [0:7] DSARCVALUE; - input [0:7] DSCNTLVALUE; - input [0:7] ISARCVALUE; - input [0:7] ISCNTLVALUE; - input [1:3] PLBC405DCURDWDADDR; - input [1:3] PLBC405ICURDWDADDR; -endmodule - -module PPC440 (...); - parameter CLOCK_DELAY = "FALSE"; - parameter DCR_AUTOLOCK_ENABLE = "TRUE"; - parameter PPCDM_ASYNCMODE = "FALSE"; - parameter PPCDS_ASYNCMODE = "FALSE"; - parameter PPCS0_WIDTH_128N64 = "TRUE"; - parameter PPCS1_WIDTH_128N64 = "TRUE"; - parameter [0:16] APU_CONTROL = 17'h02000; - parameter [0:23] APU_UDI0 = 24'h000000; - parameter [0:23] APU_UDI1 = 24'h000000; - parameter [0:23] APU_UDI10 = 24'h000000; - parameter [0:23] APU_UDI11 = 24'h000000; - parameter [0:23] APU_UDI12 = 24'h000000; - parameter [0:23] APU_UDI13 = 24'h000000; - parameter [0:23] APU_UDI14 = 24'h000000; - parameter [0:23] APU_UDI15 = 24'h000000; - parameter [0:23] APU_UDI2 = 24'h000000; - parameter [0:23] APU_UDI3 = 24'h000000; - parameter [0:23] APU_UDI4 = 24'h000000; - parameter [0:23] APU_UDI5 = 24'h000000; - parameter [0:23] APU_UDI6 = 24'h000000; - parameter [0:23] APU_UDI7 = 24'h000000; - parameter [0:23] APU_UDI8 = 24'h000000; - parameter [0:23] APU_UDI9 = 24'h000000; - parameter [0:31] DMA0_RXCHANNELCTRL = 32'h01010000; - parameter [0:31] DMA0_TXCHANNELCTRL = 32'h01010000; - parameter [0:31] DMA1_RXCHANNELCTRL = 32'h01010000; - parameter [0:31] DMA1_TXCHANNELCTRL = 32'h01010000; - parameter [0:31] DMA2_RXCHANNELCTRL = 32'h01010000; - parameter [0:31] DMA2_TXCHANNELCTRL = 32'h01010000; - parameter [0:31] DMA3_RXCHANNELCTRL = 32'h01010000; - parameter [0:31] DMA3_TXCHANNELCTRL = 32'h01010000; - parameter [0:31] INTERCONNECT_IMASK = 32'hFFFFFFFF; - parameter [0:31] INTERCONNECT_TMPL_SEL = 32'h3FFFFFFF; - parameter [0:31] MI_ARBCONFIG = 32'h00432010; - parameter [0:31] MI_BANKCONFLICT_MASK = 32'h00000000; - parameter [0:31] MI_CONTROL = 32'h0000008F; - parameter [0:31] MI_ROWCONFLICT_MASK = 32'h00000000; - parameter [0:31] PPCM_ARBCONFIG = 32'h00432010; - parameter [0:31] PPCM_CONTROL = 32'h8000019F; - parameter [0:31] PPCM_COUNTER = 32'h00000500; - parameter [0:31] PPCS0_ADDRMAP_TMPL0 = 32'hFFFFFFFF; - parameter [0:31] PPCS0_ADDRMAP_TMPL1 = 32'hFFFFFFFF; - parameter [0:31] PPCS0_ADDRMAP_TMPL2 = 32'hFFFFFFFF; - parameter [0:31] PPCS0_ADDRMAP_TMPL3 = 32'hFFFFFFFF; - parameter [0:31] PPCS0_CONTROL = 32'h8033336C; - parameter [0:31] PPCS1_ADDRMAP_TMPL0 = 32'hFFFFFFFF; - parameter [0:31] PPCS1_ADDRMAP_TMPL1 = 32'hFFFFFFFF; - parameter [0:31] PPCS1_ADDRMAP_TMPL2 = 32'hFFFFFFFF; - parameter [0:31] PPCS1_ADDRMAP_TMPL3 = 32'hFFFFFFFF; - parameter [0:31] PPCS1_CONTROL = 32'h8033336C; - parameter [0:31] XBAR_ADDRMAP_TMPL0 = 32'hFFFF0000; - parameter [0:31] XBAR_ADDRMAP_TMPL1 = 32'h00000000; - parameter [0:31] XBAR_ADDRMAP_TMPL2 = 32'h00000000; - parameter [0:31] XBAR_ADDRMAP_TMPL3 = 32'h00000000; - parameter [0:7] DMA0_CONTROL = 8'h00; - parameter [0:7] DMA1_CONTROL = 8'h00; - parameter [0:7] DMA2_CONTROL = 8'h00; - parameter [0:7] DMA3_CONTROL = 8'h00; - parameter [0:9] DMA0_RXIRQTIMER = 10'h3FF; - parameter [0:9] DMA0_TXIRQTIMER = 10'h3FF; - parameter [0:9] DMA1_RXIRQTIMER = 10'h3FF; - parameter [0:9] DMA1_TXIRQTIMER = 10'h3FF; - parameter [0:9] DMA2_RXIRQTIMER = 10'h3FF; - parameter [0:9] DMA2_TXIRQTIMER = 10'h3FF; - parameter [0:9] DMA3_RXIRQTIMER = 10'h3FF; - parameter [0:9] DMA3_TXIRQTIMER = 10'h3FF; - output APUFCMDECFPUOP; - output APUFCMDECLOAD; - output APUFCMDECNONAUTON; - output APUFCMDECSTORE; - output APUFCMDECUDIVALID; - output APUFCMENDIAN; - output APUFCMFLUSH; - output APUFCMINSTRVALID; - output APUFCMLOADDVALID; - output APUFCMMSRFE0; - output APUFCMMSRFE1; - output APUFCMNEXTINSTRREADY; - output APUFCMOPERANDVALID; - output APUFCMWRITEBACKOK; - output C440CPMCORESLEEPREQ; - output C440CPMDECIRPTREQ; - output C440CPMFITIRPTREQ; - output C440CPMMSRCE; - output C440CPMMSREE; - output C440CPMTIMERRESETREQ; - output C440CPMWDIRPTREQ; - output C440JTGTDO; - output C440JTGTDOEN; - output C440MACHINECHECK; - output C440RSTCHIPRESETREQ; - output C440RSTCORERESETREQ; - output C440RSTSYSTEMRESETREQ; - output C440TRCCYCLE; - output C440TRCTRIGGEREVENTOUT; - output DMA0LLRSTENGINEACK; - output DMA0LLRXDSTRDYN; - output DMA0LLTXEOFN; - output DMA0LLTXEOPN; - output DMA0LLTXSOFN; - output DMA0LLTXSOPN; - output DMA0LLTXSRCRDYN; - output DMA0RXIRQ; - output DMA0TXIRQ; - output DMA1LLRSTENGINEACK; - output DMA1LLRXDSTRDYN; - output DMA1LLTXEOFN; - output DMA1LLTXEOPN; - output DMA1LLTXSOFN; - output DMA1LLTXSOPN; - output DMA1LLTXSRCRDYN; - output DMA1RXIRQ; - output DMA1TXIRQ; - output DMA2LLRSTENGINEACK; - output DMA2LLRXDSTRDYN; - output DMA2LLTXEOFN; - output DMA2LLTXEOPN; - output DMA2LLTXSOFN; - output DMA2LLTXSOPN; - output DMA2LLTXSRCRDYN; - output DMA2RXIRQ; - output DMA2TXIRQ; - output DMA3LLRSTENGINEACK; - output DMA3LLRXDSTRDYN; - output DMA3LLTXEOFN; - output DMA3LLTXEOPN; - output DMA3LLTXSOFN; - output DMA3LLTXSOPN; - output DMA3LLTXSRCRDYN; - output DMA3RXIRQ; - output DMA3TXIRQ; - output MIMCADDRESSVALID; - output MIMCBANKCONFLICT; - output MIMCREADNOTWRITE; - output MIMCROWCONFLICT; - output MIMCWRITEDATAVALID; - output PPCCPMINTERCONNECTBUSY; - output PPCDMDCRREAD; - output PPCDMDCRWRITE; - output PPCDSDCRACK; - output PPCDSDCRTIMEOUTWAIT; - output PPCEICINTERCONNECTIRQ; - output PPCMPLBABORT; - output PPCMPLBBUSLOCK; - output PPCMPLBLOCKERR; - output PPCMPLBRDBURST; - output PPCMPLBREQUEST; - output PPCMPLBRNW; - output PPCMPLBWRBURST; - output PPCS0PLBADDRACK; - output PPCS0PLBRDBTERM; - output PPCS0PLBRDCOMP; - output PPCS0PLBRDDACK; - output PPCS0PLBREARBITRATE; - output PPCS0PLBWAIT; - output PPCS0PLBWRBTERM; - output PPCS0PLBWRCOMP; - output PPCS0PLBWRDACK; - output PPCS1PLBADDRACK; - output PPCS1PLBRDBTERM; - output PPCS1PLBRDCOMP; - output PPCS1PLBRDDACK; - output PPCS1PLBREARBITRATE; - output PPCS1PLBWAIT; - output PPCS1PLBWRBTERM; - output PPCS1PLBWRCOMP; - output PPCS1PLBWRDACK; - output [0:127] APUFCMLOADDATA; - output [0:127] MIMCWRITEDATA; - output [0:127] PPCMPLBWRDBUS; - output [0:127] PPCS0PLBRDDBUS; - output [0:127] PPCS1PLBRDDBUS; - output [0:13] C440TRCTRIGGEREVENTTYPE; - output [0:15] MIMCBYTEENABLE; - output [0:15] PPCMPLBBE; - output [0:15] PPCMPLBTATTRIBUTE; - output [0:1] PPCMPLBPRIORITY; - output [0:1] PPCS0PLBSSIZE; - output [0:1] PPCS1PLBSSIZE; - output [0:2] APUFCMDECLDSTXFERSIZE; - output [0:2] C440TRCBRANCHSTATUS; - output [0:2] PPCMPLBTYPE; - output [0:31] APUFCMINSTRUCTION; - output [0:31] APUFCMRADATA; - output [0:31] APUFCMRBDATA; - output [0:31] DMA0LLTXD; - output [0:31] DMA1LLTXD; - output [0:31] DMA2LLTXD; - output [0:31] DMA3LLTXD; - output [0:31] PPCDMDCRDBUSOUT; - output [0:31] PPCDSDCRDBUSIN; - output [0:31] PPCMPLBABUS; - output [0:35] MIMCADDRESS; - output [0:3] APUFCMDECUDI; - output [0:3] APUFCMLOADBYTEADDR; - output [0:3] DMA0LLTXREM; - output [0:3] DMA1LLTXREM; - output [0:3] DMA2LLTXREM; - output [0:3] DMA3LLTXREM; - output [0:3] PPCMPLBSIZE; - output [0:3] PPCS0PLBMBUSY; - output [0:3] PPCS0PLBMIRQ; - output [0:3] PPCS0PLBMRDERR; - output [0:3] PPCS0PLBMWRERR; - output [0:3] PPCS0PLBRDWDADDR; - output [0:3] PPCS1PLBMBUSY; - output [0:3] PPCS1PLBMIRQ; - output [0:3] PPCS1PLBMRDERR; - output [0:3] PPCS1PLBMWRERR; - output [0:3] PPCS1PLBRDWDADDR; - output [0:4] C440TRCEXECUTIONSTATUS; - output [0:6] C440TRCTRACESTATUS; - output [0:7] C440DBGSYSTEMCONTROL; - output [0:9] PPCDMDCRABUS; - output [20:21] PPCDMDCRUABUS; - output [28:31] PPCMPLBUABUS; - input CPMC440CLK; - input CPMC440CLKEN; - input CPMC440CORECLOCKINACTIVE; - input CPMC440TIMERCLOCK; - input CPMDCRCLK; - input CPMDMA0LLCLK; - input CPMDMA1LLCLK; - input CPMDMA2LLCLK; - input CPMDMA3LLCLK; - input CPMFCMCLK; - input CPMINTERCONNECTCLK; - input CPMINTERCONNECTCLKEN; - input CPMINTERCONNECTCLKNTO1; - input CPMMCCLK; - input CPMPPCMPLBCLK; - input CPMPPCS0PLBCLK; - input CPMPPCS1PLBCLK; - input DBGC440DEBUGHALT; - input DBGC440UNCONDDEBUGEVENT; - input DCRPPCDMACK; - input DCRPPCDMTIMEOUTWAIT; - input DCRPPCDSREAD; - input DCRPPCDSWRITE; - input EICC440CRITIRQ; - input EICC440EXTIRQ; - input FCMAPUCONFIRMINSTR; - input FCMAPUDONE; - input FCMAPUEXCEPTION; - input FCMAPUFPSCRFEX; - input FCMAPURESULTVALID; - input FCMAPUSLEEPNOTREADY; - input JTGC440TCK; - input JTGC440TDI; - input JTGC440TMS; - input JTGC440TRSTNEG; - input LLDMA0RSTENGINEREQ; - input LLDMA0RXEOFN; - input LLDMA0RXEOPN; - input LLDMA0RXSOFN; - input LLDMA0RXSOPN; - input LLDMA0RXSRCRDYN; - input LLDMA0TXDSTRDYN; - input LLDMA1RSTENGINEREQ; - input LLDMA1RXEOFN; - input LLDMA1RXEOPN; - input LLDMA1RXSOFN; - input LLDMA1RXSOPN; - input LLDMA1RXSRCRDYN; - input LLDMA1TXDSTRDYN; - input LLDMA2RSTENGINEREQ; - input LLDMA2RXEOFN; - input LLDMA2RXEOPN; - input LLDMA2RXSOFN; - input LLDMA2RXSOPN; - input LLDMA2RXSRCRDYN; - input LLDMA2TXDSTRDYN; - input LLDMA3RSTENGINEREQ; - input LLDMA3RXEOFN; - input LLDMA3RXEOPN; - input LLDMA3RXSOFN; - input LLDMA3RXSOPN; - input LLDMA3RXSRCRDYN; - input LLDMA3TXDSTRDYN; - input MCMIADDRREADYTOACCEPT; - input MCMIREADDATAERR; - input MCMIREADDATAVALID; - input PLBPPCMADDRACK; - input PLBPPCMMBUSY; - input PLBPPCMMIRQ; - input PLBPPCMMRDERR; - input PLBPPCMMWRERR; - input PLBPPCMRDBTERM; - input PLBPPCMRDDACK; - input PLBPPCMRDPENDREQ; - input PLBPPCMREARBITRATE; - input PLBPPCMTIMEOUT; - input PLBPPCMWRBTERM; - input PLBPPCMWRDACK; - input PLBPPCMWRPENDREQ; - input PLBPPCS0ABORT; - input PLBPPCS0BUSLOCK; - input PLBPPCS0LOCKERR; - input PLBPPCS0PAVALID; - input PLBPPCS0RDBURST; - input PLBPPCS0RDPENDREQ; - input PLBPPCS0RDPRIM; - input PLBPPCS0RNW; - input PLBPPCS0SAVALID; - input PLBPPCS0WRBURST; - input PLBPPCS0WRPENDREQ; - input PLBPPCS0WRPRIM; - input PLBPPCS1ABORT; - input PLBPPCS1BUSLOCK; - input PLBPPCS1LOCKERR; - input PLBPPCS1PAVALID; - input PLBPPCS1RDBURST; - input PLBPPCS1RDPENDREQ; - input PLBPPCS1RDPRIM; - input PLBPPCS1RNW; - input PLBPPCS1SAVALID; - input PLBPPCS1WRBURST; - input PLBPPCS1WRPENDREQ; - input PLBPPCS1WRPRIM; - input RSTC440RESETCHIP; - input RSTC440RESETCORE; - input RSTC440RESETSYSTEM; - input TIEC440ENDIANRESET; - input TRCC440TRACEDISABLE; - input TRCC440TRIGGEREVENTIN; - input [0:127] FCMAPUSTOREDATA; - input [0:127] MCMIREADDATA; - input [0:127] PLBPPCMRDDBUS; - input [0:127] PLBPPCS0WRDBUS; - input [0:127] PLBPPCS1WRDBUS; - input [0:15] PLBPPCS0BE; - input [0:15] PLBPPCS0TATTRIBUTE; - input [0:15] PLBPPCS1BE; - input [0:15] PLBPPCS1TATTRIBUTE; - input [0:1] PLBPPCMRDPENDPRI; - input [0:1] PLBPPCMREQPRI; - input [0:1] PLBPPCMSSIZE; - input [0:1] PLBPPCMWRPENDPRI; - input [0:1] PLBPPCS0MASTERID; - input [0:1] PLBPPCS0MSIZE; - input [0:1] PLBPPCS0RDPENDPRI; - input [0:1] PLBPPCS0REQPRI; - input [0:1] PLBPPCS0WRPENDPRI; - input [0:1] PLBPPCS1MASTERID; - input [0:1] PLBPPCS1MSIZE; - input [0:1] PLBPPCS1RDPENDPRI; - input [0:1] PLBPPCS1REQPRI; - input [0:1] PLBPPCS1WRPENDPRI; - input [0:1] TIEC440DCURDLDCACHEPLBPRIO; - input [0:1] TIEC440DCURDNONCACHEPLBPRIO; - input [0:1] TIEC440DCURDTOUCHPLBPRIO; - input [0:1] TIEC440DCURDURGENTPLBPRIO; - input [0:1] TIEC440DCUWRFLUSHPLBPRIO; - input [0:1] TIEC440DCUWRSTOREPLBPRIO; - input [0:1] TIEC440DCUWRURGENTPLBPRIO; - input [0:1] TIEC440ICURDFETCHPLBPRIO; - input [0:1] TIEC440ICURDSPECPLBPRIO; - input [0:1] TIEC440ICURDTOUCHPLBPRIO; - input [0:1] TIEDCRBASEADDR; - input [0:2] PLBPPCS0TYPE; - input [0:2] PLBPPCS1TYPE; - input [0:31] DCRPPCDMDBUSIN; - input [0:31] DCRPPCDSDBUSOUT; - input [0:31] FCMAPURESULT; - input [0:31] LLDMA0RXD; - input [0:31] LLDMA1RXD; - input [0:31] LLDMA2RXD; - input [0:31] LLDMA3RXD; - input [0:31] PLBPPCS0ABUS; - input [0:31] PLBPPCS1ABUS; - input [0:3] FCMAPUCR; - input [0:3] LLDMA0RXREM; - input [0:3] LLDMA1RXREM; - input [0:3] LLDMA2RXREM; - input [0:3] LLDMA3RXREM; - input [0:3] PLBPPCMRDWDADDR; - input [0:3] PLBPPCS0SIZE; - input [0:3] PLBPPCS1SIZE; - input [0:3] TIEC440ERPNRESET; - input [0:3] TIEC440USERRESET; - input [0:4] DBGC440SYSTEMSTATUS; - input [0:9] DCRPPCDSABUS; - input [28:31] PLBPPCS0UABUS; - input [28:31] PLBPPCS1UABUS; - input [28:31] TIEC440PIR; - input [28:31] TIEC440PVR; -endmodule - -(* keep *) -module PS7 (...); - output DMA0DAVALID; - output DMA0DRREADY; - output DMA0RSTN; - output DMA1DAVALID; - output DMA1DRREADY; - output DMA1RSTN; - output DMA2DAVALID; - output DMA2DRREADY; - output DMA2RSTN; - output DMA3DAVALID; - output DMA3DRREADY; - output DMA3RSTN; - output EMIOCAN0PHYTX; - output EMIOCAN1PHYTX; - output EMIOENET0GMIITXEN; - output EMIOENET0GMIITXER; - output EMIOENET0MDIOMDC; - output EMIOENET0MDIOO; - output EMIOENET0MDIOTN; - output EMIOENET0PTPDELAYREQRX; - output EMIOENET0PTPDELAYREQTX; - output EMIOENET0PTPPDELAYREQRX; - output EMIOENET0PTPPDELAYREQTX; - output EMIOENET0PTPPDELAYRESPRX; - output EMIOENET0PTPPDELAYRESPTX; - output EMIOENET0PTPSYNCFRAMERX; - output EMIOENET0PTPSYNCFRAMETX; - output EMIOENET0SOFRX; - output EMIOENET0SOFTX; - output EMIOENET1GMIITXEN; - output EMIOENET1GMIITXER; - output EMIOENET1MDIOMDC; - output EMIOENET1MDIOO; - output EMIOENET1MDIOTN; - output EMIOENET1PTPDELAYREQRX; - output EMIOENET1PTPDELAYREQTX; - output EMIOENET1PTPPDELAYREQRX; - output EMIOENET1PTPPDELAYREQTX; - output EMIOENET1PTPPDELAYRESPRX; - output EMIOENET1PTPPDELAYRESPTX; - output EMIOENET1PTPSYNCFRAMERX; - output EMIOENET1PTPSYNCFRAMETX; - output EMIOENET1SOFRX; - output EMIOENET1SOFTX; - output EMIOI2C0SCLO; - output EMIOI2C0SCLTN; - output EMIOI2C0SDAO; - output EMIOI2C0SDATN; - output EMIOI2C1SCLO; - output EMIOI2C1SCLTN; - output EMIOI2C1SDAO; - output EMIOI2C1SDATN; - output EMIOPJTAGTDO; - output EMIOPJTAGTDTN; - output EMIOSDIO0BUSPOW; - output EMIOSDIO0CLK; - output EMIOSDIO0CMDO; - output EMIOSDIO0CMDTN; - output EMIOSDIO0LED; - output EMIOSDIO1BUSPOW; - output EMIOSDIO1CLK; - output EMIOSDIO1CMDO; - output EMIOSDIO1CMDTN; - output EMIOSDIO1LED; - output EMIOSPI0MO; - output EMIOSPI0MOTN; - output EMIOSPI0SCLKO; - output EMIOSPI0SCLKTN; - output EMIOSPI0SO; - output EMIOSPI0SSNTN; - output EMIOSPI0STN; - output EMIOSPI1MO; - output EMIOSPI1MOTN; - output EMIOSPI1SCLKO; - output EMIOSPI1SCLKTN; - output EMIOSPI1SO; - output EMIOSPI1SSNTN; - output EMIOSPI1STN; - output EMIOTRACECTL; - output EMIOUART0DTRN; - output EMIOUART0RTSN; - output EMIOUART0TX; - output EMIOUART1DTRN; - output EMIOUART1RTSN; - output EMIOUART1TX; - output EMIOUSB0VBUSPWRSELECT; - output EMIOUSB1VBUSPWRSELECT; - output EMIOWDTRSTO; - output EVENTEVENTO; - output MAXIGP0ARESETN; - output MAXIGP0ARVALID; - output MAXIGP0AWVALID; - output MAXIGP0BREADY; - output MAXIGP0RREADY; - output MAXIGP0WLAST; - output MAXIGP0WVALID; - output MAXIGP1ARESETN; - output MAXIGP1ARVALID; - output MAXIGP1AWVALID; - output MAXIGP1BREADY; - output MAXIGP1RREADY; - output MAXIGP1WLAST; - output MAXIGP1WVALID; - output SAXIACPARESETN; - output SAXIACPARREADY; - output SAXIACPAWREADY; - output SAXIACPBVALID; - output SAXIACPRLAST; - output SAXIACPRVALID; - output SAXIACPWREADY; - output SAXIGP0ARESETN; - output SAXIGP0ARREADY; - output SAXIGP0AWREADY; - output SAXIGP0BVALID; - output SAXIGP0RLAST; - output SAXIGP0RVALID; - output SAXIGP0WREADY; - output SAXIGP1ARESETN; - output SAXIGP1ARREADY; - output SAXIGP1AWREADY; - output SAXIGP1BVALID; - output SAXIGP1RLAST; - output SAXIGP1RVALID; - output SAXIGP1WREADY; - output SAXIHP0ARESETN; - output SAXIHP0ARREADY; - output SAXIHP0AWREADY; - output SAXIHP0BVALID; - output SAXIHP0RLAST; - output SAXIHP0RVALID; - output SAXIHP0WREADY; - output SAXIHP1ARESETN; - output SAXIHP1ARREADY; - output SAXIHP1AWREADY; - output SAXIHP1BVALID; - output SAXIHP1RLAST; - output SAXIHP1RVALID; - output SAXIHP1WREADY; - output SAXIHP2ARESETN; - output SAXIHP2ARREADY; - output SAXIHP2AWREADY; - output SAXIHP2BVALID; - output SAXIHP2RLAST; - output SAXIHP2RVALID; - output SAXIHP2WREADY; - output SAXIHP3ARESETN; - output SAXIHP3ARREADY; - output SAXIHP3AWREADY; - output SAXIHP3BVALID; - output SAXIHP3RLAST; - output SAXIHP3RVALID; - output SAXIHP3WREADY; - output [11:0] MAXIGP0ARID; - output [11:0] MAXIGP0AWID; - output [11:0] MAXIGP0WID; - output [11:0] MAXIGP1ARID; - output [11:0] MAXIGP1AWID; - output [11:0] MAXIGP1WID; - output [1:0] DMA0DATYPE; - output [1:0] DMA1DATYPE; - output [1:0] DMA2DATYPE; - output [1:0] DMA3DATYPE; - output [1:0] EMIOUSB0PORTINDCTL; - output [1:0] EMIOUSB1PORTINDCTL; - output [1:0] EVENTSTANDBYWFE; - output [1:0] EVENTSTANDBYWFI; - output [1:0] MAXIGP0ARBURST; - output [1:0] MAXIGP0ARLOCK; - output [1:0] MAXIGP0ARSIZE; - output [1:0] MAXIGP0AWBURST; - output [1:0] MAXIGP0AWLOCK; - output [1:0] MAXIGP0AWSIZE; - output [1:0] MAXIGP1ARBURST; - output [1:0] MAXIGP1ARLOCK; - output [1:0] MAXIGP1ARSIZE; - output [1:0] MAXIGP1AWBURST; - output [1:0] MAXIGP1AWLOCK; - output [1:0] MAXIGP1AWSIZE; - output [1:0] SAXIACPBRESP; - output [1:0] SAXIACPRRESP; - output [1:0] SAXIGP0BRESP; - output [1:0] SAXIGP0RRESP; - output [1:0] SAXIGP1BRESP; - output [1:0] SAXIGP1RRESP; - output [1:0] SAXIHP0BRESP; - output [1:0] SAXIHP0RRESP; - output [1:0] SAXIHP1BRESP; - output [1:0] SAXIHP1RRESP; - output [1:0] SAXIHP2BRESP; - output [1:0] SAXIHP2RRESP; - output [1:0] SAXIHP3BRESP; - output [1:0] SAXIHP3RRESP; - output [28:0] IRQP2F; - output [2:0] EMIOSDIO0BUSVOLT; - output [2:0] EMIOSDIO1BUSVOLT; - output [2:0] EMIOSPI0SSON; - output [2:0] EMIOSPI1SSON; - output [2:0] EMIOTTC0WAVEO; - output [2:0] EMIOTTC1WAVEO; - output [2:0] MAXIGP0ARPROT; - output [2:0] MAXIGP0AWPROT; - output [2:0] MAXIGP1ARPROT; - output [2:0] MAXIGP1AWPROT; - output [2:0] SAXIACPBID; - output [2:0] SAXIACPRID; - output [2:0] SAXIHP0RACOUNT; - output [2:0] SAXIHP1RACOUNT; - output [2:0] SAXIHP2RACOUNT; - output [2:0] SAXIHP3RACOUNT; - output [31:0] EMIOTRACEDATA; - output [31:0] FTMTP2FDEBUG; - output [31:0] MAXIGP0ARADDR; - output [31:0] MAXIGP0AWADDR; - output [31:0] MAXIGP0WDATA; - output [31:0] MAXIGP1ARADDR; - output [31:0] MAXIGP1AWADDR; - output [31:0] MAXIGP1WDATA; - output [31:0] SAXIGP0RDATA; - output [31:0] SAXIGP1RDATA; - output [3:0] EMIOSDIO0DATAO; - output [3:0] EMIOSDIO0DATATN; - output [3:0] EMIOSDIO1DATAO; - output [3:0] EMIOSDIO1DATATN; - output [3:0] FCLKCLK; - output [3:0] FCLKRESETN; - output [3:0] FTMTF2PTRIGACK; - output [3:0] FTMTP2FTRIG; - output [3:0] MAXIGP0ARCACHE; - output [3:0] MAXIGP0ARLEN; - output [3:0] MAXIGP0ARQOS; - output [3:0] MAXIGP0AWCACHE; - output [3:0] MAXIGP0AWLEN; - output [3:0] MAXIGP0AWQOS; - output [3:0] MAXIGP0WSTRB; - output [3:0] MAXIGP1ARCACHE; - output [3:0] MAXIGP1ARLEN; - output [3:0] MAXIGP1ARQOS; - output [3:0] MAXIGP1AWCACHE; - output [3:0] MAXIGP1AWLEN; - output [3:0] MAXIGP1AWQOS; - output [3:0] MAXIGP1WSTRB; - output [5:0] SAXIGP0BID; - output [5:0] SAXIGP0RID; - output [5:0] SAXIGP1BID; - output [5:0] SAXIGP1RID; - output [5:0] SAXIHP0BID; - output [5:0] SAXIHP0RID; - output [5:0] SAXIHP0WACOUNT; - output [5:0] SAXIHP1BID; - output [5:0] SAXIHP1RID; - output [5:0] SAXIHP1WACOUNT; - output [5:0] SAXIHP2BID; - output [5:0] SAXIHP2RID; - output [5:0] SAXIHP2WACOUNT; - output [5:0] SAXIHP3BID; - output [5:0] SAXIHP3RID; - output [5:0] SAXIHP3WACOUNT; - output [63:0] EMIOGPIOO; - output [63:0] EMIOGPIOTN; - output [63:0] SAXIACPRDATA; - output [63:0] SAXIHP0RDATA; - output [63:0] SAXIHP1RDATA; - output [63:0] SAXIHP2RDATA; - output [63:0] SAXIHP3RDATA; - output [7:0] EMIOENET0GMIITXD; - output [7:0] EMIOENET1GMIITXD; - output [7:0] SAXIHP0RCOUNT; - output [7:0] SAXIHP0WCOUNT; - output [7:0] SAXIHP1RCOUNT; - output [7:0] SAXIHP1WCOUNT; - output [7:0] SAXIHP2RCOUNT; - output [7:0] SAXIHP2WCOUNT; - output [7:0] SAXIHP3RCOUNT; - output [7:0] SAXIHP3WCOUNT; - inout DDRCASB; - inout DDRCKE; - inout DDRCKN; - inout DDRCKP; - inout DDRCSB; - inout DDRDRSTB; - inout DDRODT; - inout DDRRASB; - inout DDRVRN; - inout DDRVRP; - inout DDRWEB; - inout PSCLK; - inout PSPORB; - inout PSSRSTB; - inout [14:0] DDRA; - inout [2:0] DDRBA; - inout [31:0] DDRDQ; - inout [3:0] DDRDM; - inout [3:0] DDRDQSN; - inout [3:0] DDRDQSP; - inout [53:0] MIO; - input DMA0ACLK; - input DMA0DAREADY; - input DMA0DRLAST; - input DMA0DRVALID; - input DMA1ACLK; - input DMA1DAREADY; - input DMA1DRLAST; - input DMA1DRVALID; - input DMA2ACLK; - input DMA2DAREADY; - input DMA2DRLAST; - input DMA2DRVALID; - input DMA3ACLK; - input DMA3DAREADY; - input DMA3DRLAST; - input DMA3DRVALID; - input EMIOCAN0PHYRX; - input EMIOCAN1PHYRX; - input EMIOENET0EXTINTIN; - input EMIOENET0GMIICOL; - input EMIOENET0GMIICRS; - input EMIOENET0GMIIRXCLK; - input EMIOENET0GMIIRXDV; - input EMIOENET0GMIIRXER; - input EMIOENET0GMIITXCLK; - input EMIOENET0MDIOI; - input EMIOENET1EXTINTIN; - input EMIOENET1GMIICOL; - input EMIOENET1GMIICRS; - input EMIOENET1GMIIRXCLK; - input EMIOENET1GMIIRXDV; - input EMIOENET1GMIIRXER; - input EMIOENET1GMIITXCLK; - input EMIOENET1MDIOI; - input EMIOI2C0SCLI; - input EMIOI2C0SDAI; - input EMIOI2C1SCLI; - input EMIOI2C1SDAI; - input EMIOPJTAGTCK; - input EMIOPJTAGTDI; - input EMIOPJTAGTMS; - input EMIOSDIO0CDN; - input EMIOSDIO0CLKFB; - input EMIOSDIO0CMDI; - input EMIOSDIO0WP; - input EMIOSDIO1CDN; - input EMIOSDIO1CLKFB; - input EMIOSDIO1CMDI; - input EMIOSDIO1WP; - input EMIOSPI0MI; - input EMIOSPI0SCLKI; - input EMIOSPI0SI; - input EMIOSPI0SSIN; - input EMIOSPI1MI; - input EMIOSPI1SCLKI; - input EMIOSPI1SI; - input EMIOSPI1SSIN; - input EMIOSRAMINTIN; - input EMIOTRACECLK; - input EMIOUART0CTSN; - input EMIOUART0DCDN; - input EMIOUART0DSRN; - input EMIOUART0RIN; - input EMIOUART0RX; - input EMIOUART1CTSN; - input EMIOUART1DCDN; - input EMIOUART1DSRN; - input EMIOUART1RIN; - input EMIOUART1RX; - input EMIOUSB0VBUSPWRFAULT; - input EMIOUSB1VBUSPWRFAULT; - input EMIOWDTCLKI; - input EVENTEVENTI; - input FPGAIDLEN; - input FTMDTRACEINCLOCK; - input FTMDTRACEINVALID; - input MAXIGP0ACLK; - input MAXIGP0ARREADY; - input MAXIGP0AWREADY; - input MAXIGP0BVALID; - input MAXIGP0RLAST; - input MAXIGP0RVALID; - input MAXIGP0WREADY; - input MAXIGP1ACLK; - input MAXIGP1ARREADY; - input MAXIGP1AWREADY; - input MAXIGP1BVALID; - input MAXIGP1RLAST; - input MAXIGP1RVALID; - input MAXIGP1WREADY; - input SAXIACPACLK; - input SAXIACPARVALID; - input SAXIACPAWVALID; - input SAXIACPBREADY; - input SAXIACPRREADY; - input SAXIACPWLAST; - input SAXIACPWVALID; - input SAXIGP0ACLK; - input SAXIGP0ARVALID; - input SAXIGP0AWVALID; - input SAXIGP0BREADY; - input SAXIGP0RREADY; - input SAXIGP0WLAST; - input SAXIGP0WVALID; - input SAXIGP1ACLK; - input SAXIGP1ARVALID; - input SAXIGP1AWVALID; - input SAXIGP1BREADY; - input SAXIGP1RREADY; - input SAXIGP1WLAST; - input SAXIGP1WVALID; - input SAXIHP0ACLK; - input SAXIHP0ARVALID; - input SAXIHP0AWVALID; - input SAXIHP0BREADY; - input SAXIHP0RDISSUECAP1EN; - input SAXIHP0RREADY; - input SAXIHP0WLAST; - input SAXIHP0WRISSUECAP1EN; - input SAXIHP0WVALID; - input SAXIHP1ACLK; - input SAXIHP1ARVALID; - input SAXIHP1AWVALID; - input SAXIHP1BREADY; - input SAXIHP1RDISSUECAP1EN; - input SAXIHP1RREADY; - input SAXIHP1WLAST; - input SAXIHP1WRISSUECAP1EN; - input SAXIHP1WVALID; - input SAXIHP2ACLK; - input SAXIHP2ARVALID; - input SAXIHP2AWVALID; - input SAXIHP2BREADY; - input SAXIHP2RDISSUECAP1EN; - input SAXIHP2RREADY; - input SAXIHP2WLAST; - input SAXIHP2WRISSUECAP1EN; - input SAXIHP2WVALID; - input SAXIHP3ACLK; - input SAXIHP3ARVALID; - input SAXIHP3AWVALID; - input SAXIHP3BREADY; - input SAXIHP3RDISSUECAP1EN; - input SAXIHP3RREADY; - input SAXIHP3WLAST; - input SAXIHP3WRISSUECAP1EN; - input SAXIHP3WVALID; - input [11:0] MAXIGP0BID; - input [11:0] MAXIGP0RID; - input [11:0] MAXIGP1BID; - input [11:0] MAXIGP1RID; - input [19:0] IRQF2P; - input [1:0] DMA0DRTYPE; - input [1:0] DMA1DRTYPE; - input [1:0] DMA2DRTYPE; - input [1:0] DMA3DRTYPE; - input [1:0] MAXIGP0BRESP; - input [1:0] MAXIGP0RRESP; - input [1:0] MAXIGP1BRESP; - input [1:0] MAXIGP1RRESP; - input [1:0] SAXIACPARBURST; - input [1:0] SAXIACPARLOCK; - input [1:0] SAXIACPARSIZE; - input [1:0] SAXIACPAWBURST; - input [1:0] SAXIACPAWLOCK; - input [1:0] SAXIACPAWSIZE; - input [1:0] SAXIGP0ARBURST; - input [1:0] SAXIGP0ARLOCK; - input [1:0] SAXIGP0ARSIZE; - input [1:0] SAXIGP0AWBURST; - input [1:0] SAXIGP0AWLOCK; - input [1:0] SAXIGP0AWSIZE; - input [1:0] SAXIGP1ARBURST; - input [1:0] SAXIGP1ARLOCK; - input [1:0] SAXIGP1ARSIZE; - input [1:0] SAXIGP1AWBURST; - input [1:0] SAXIGP1AWLOCK; - input [1:0] SAXIGP1AWSIZE; - input [1:0] SAXIHP0ARBURST; - input [1:0] SAXIHP0ARLOCK; - input [1:0] SAXIHP0ARSIZE; - input [1:0] SAXIHP0AWBURST; - input [1:0] SAXIHP0AWLOCK; - input [1:0] SAXIHP0AWSIZE; - input [1:0] SAXIHP1ARBURST; - input [1:0] SAXIHP1ARLOCK; - input [1:0] SAXIHP1ARSIZE; - input [1:0] SAXIHP1AWBURST; - input [1:0] SAXIHP1AWLOCK; - input [1:0] SAXIHP1AWSIZE; - input [1:0] SAXIHP2ARBURST; - input [1:0] SAXIHP2ARLOCK; - input [1:0] SAXIHP2ARSIZE; - input [1:0] SAXIHP2AWBURST; - input [1:0] SAXIHP2AWLOCK; - input [1:0] SAXIHP2AWSIZE; - input [1:0] SAXIHP3ARBURST; - input [1:0] SAXIHP3ARLOCK; - input [1:0] SAXIHP3ARSIZE; - input [1:0] SAXIHP3AWBURST; - input [1:0] SAXIHP3AWLOCK; - input [1:0] SAXIHP3AWSIZE; - input [2:0] EMIOTTC0CLKI; - input [2:0] EMIOTTC1CLKI; - input [2:0] SAXIACPARID; - input [2:0] SAXIACPARPROT; - input [2:0] SAXIACPAWID; - input [2:0] SAXIACPAWPROT; - input [2:0] SAXIACPWID; - input [2:0] SAXIGP0ARPROT; - input [2:0] SAXIGP0AWPROT; - input [2:0] SAXIGP1ARPROT; - input [2:0] SAXIGP1AWPROT; - input [2:0] SAXIHP0ARPROT; - input [2:0] SAXIHP0AWPROT; - input [2:0] SAXIHP1ARPROT; - input [2:0] SAXIHP1AWPROT; - input [2:0] SAXIHP2ARPROT; - input [2:0] SAXIHP2AWPROT; - input [2:0] SAXIHP3ARPROT; - input [2:0] SAXIHP3AWPROT; - input [31:0] FTMDTRACEINDATA; - input [31:0] FTMTF2PDEBUG; - input [31:0] MAXIGP0RDATA; - input [31:0] MAXIGP1RDATA; - input [31:0] SAXIACPARADDR; - input [31:0] SAXIACPAWADDR; - input [31:0] SAXIGP0ARADDR; - input [31:0] SAXIGP0AWADDR; - input [31:0] SAXIGP0WDATA; - input [31:0] SAXIGP1ARADDR; - input [31:0] SAXIGP1AWADDR; - input [31:0] SAXIGP1WDATA; - input [31:0] SAXIHP0ARADDR; - input [31:0] SAXIHP0AWADDR; - input [31:0] SAXIHP1ARADDR; - input [31:0] SAXIHP1AWADDR; - input [31:0] SAXIHP2ARADDR; - input [31:0] SAXIHP2AWADDR; - input [31:0] SAXIHP3ARADDR; - input [31:0] SAXIHP3AWADDR; - input [3:0] DDRARB; - input [3:0] EMIOSDIO0DATAI; - input [3:0] EMIOSDIO1DATAI; - input [3:0] FCLKCLKTRIGN; - input [3:0] FTMDTRACEINATID; - input [3:0] FTMTF2PTRIG; - input [3:0] FTMTP2FTRIGACK; - input [3:0] SAXIACPARCACHE; - input [3:0] SAXIACPARLEN; - input [3:0] SAXIACPARQOS; - input [3:0] SAXIACPAWCACHE; - input [3:0] SAXIACPAWLEN; - input [3:0] SAXIACPAWQOS; - input [3:0] SAXIGP0ARCACHE; - input [3:0] SAXIGP0ARLEN; - input [3:0] SAXIGP0ARQOS; - input [3:0] SAXIGP0AWCACHE; - input [3:0] SAXIGP0AWLEN; - input [3:0] SAXIGP0AWQOS; - input [3:0] SAXIGP0WSTRB; - input [3:0] SAXIGP1ARCACHE; - input [3:0] SAXIGP1ARLEN; - input [3:0] SAXIGP1ARQOS; - input [3:0] SAXIGP1AWCACHE; - input [3:0] SAXIGP1AWLEN; - input [3:0] SAXIGP1AWQOS; - input [3:0] SAXIGP1WSTRB; - input [3:0] SAXIHP0ARCACHE; - input [3:0] SAXIHP0ARLEN; - input [3:0] SAXIHP0ARQOS; - input [3:0] SAXIHP0AWCACHE; - input [3:0] SAXIHP0AWLEN; - input [3:0] SAXIHP0AWQOS; - input [3:0] SAXIHP1ARCACHE; - input [3:0] SAXIHP1ARLEN; - input [3:0] SAXIHP1ARQOS; - input [3:0] SAXIHP1AWCACHE; - input [3:0] SAXIHP1AWLEN; - input [3:0] SAXIHP1AWQOS; - input [3:0] SAXIHP2ARCACHE; - input [3:0] SAXIHP2ARLEN; - input [3:0] SAXIHP2ARQOS; - input [3:0] SAXIHP2AWCACHE; - input [3:0] SAXIHP2AWLEN; - input [3:0] SAXIHP2AWQOS; - input [3:0] SAXIHP3ARCACHE; - input [3:0] SAXIHP3ARLEN; - input [3:0] SAXIHP3ARQOS; - input [3:0] SAXIHP3AWCACHE; - input [3:0] SAXIHP3AWLEN; - input [3:0] SAXIHP3AWQOS; - input [4:0] SAXIACPARUSER; - input [4:0] SAXIACPAWUSER; - input [5:0] SAXIGP0ARID; - input [5:0] SAXIGP0AWID; - input [5:0] SAXIGP0WID; - input [5:0] SAXIGP1ARID; - input [5:0] SAXIGP1AWID; - input [5:0] SAXIGP1WID; - input [5:0] SAXIHP0ARID; - input [5:0] SAXIHP0AWID; - input [5:0] SAXIHP0WID; - input [5:0] SAXIHP1ARID; - input [5:0] SAXIHP1AWID; - input [5:0] SAXIHP1WID; - input [5:0] SAXIHP2ARID; - input [5:0] SAXIHP2AWID; - input [5:0] SAXIHP2WID; - input [5:0] SAXIHP3ARID; - input [5:0] SAXIHP3AWID; - input [5:0] SAXIHP3WID; - input [63:0] EMIOGPIOI; - input [63:0] SAXIACPWDATA; - input [63:0] SAXIHP0WDATA; - input [63:0] SAXIHP1WDATA; - input [63:0] SAXIHP2WDATA; - input [63:0] SAXIHP3WDATA; - input [7:0] EMIOENET0GMIIRXD; - input [7:0] EMIOENET1GMIIRXD; - input [7:0] SAXIACPWSTRB; - input [7:0] SAXIHP0WSTRB; - input [7:0] SAXIHP1WSTRB; - input [7:0] SAXIHP2WSTRB; - input [7:0] SAXIHP3WSTRB; -endmodule - -(* keep *) -module PS8 (...); - output [7:0] ADMA2PLCACK; - output [7:0] ADMA2PLTVLD; - output DPAUDIOREFCLK; - output DPAUXDATAOEN; - output DPAUXDATAOUT; - output DPLIVEVIDEODEOUT; - output [31:0] DPMAXISMIXEDAUDIOTDATA; - output DPMAXISMIXEDAUDIOTID; - output DPMAXISMIXEDAUDIOTVALID; - output DPSAXISAUDIOTREADY; - output DPVIDEOOUTHSYNC; - output [35:0] DPVIDEOOUTPIXEL1; - output DPVIDEOOUTVSYNC; - output DPVIDEOREFCLK; - output EMIOCAN0PHYTX; - output EMIOCAN1PHYTX; - output [1:0] EMIOENET0DMABUSWIDTH; - output EMIOENET0DMATXENDTOG; - output [93:0] EMIOENET0GEMTSUTIMERCNT; - output [7:0] EMIOENET0GMIITXD; - output EMIOENET0GMIITXEN; - output EMIOENET0GMIITXER; - output EMIOENET0MDIOMDC; - output EMIOENET0MDIOO; - output EMIOENET0MDIOTN; - output [7:0] EMIOENET0RXWDATA; - output EMIOENET0RXWEOP; - output EMIOENET0RXWERR; - output EMIOENET0RXWFLUSH; - output EMIOENET0RXWSOP; - output [44:0] EMIOENET0RXWSTATUS; - output EMIOENET0RXWWR; - output [2:0] EMIOENET0SPEEDMODE; - output EMIOENET0TXRRD; - output [3:0] EMIOENET0TXRSTATUS; - output [1:0] EMIOENET1DMABUSWIDTH; - output EMIOENET1DMATXENDTOG; - output [7:0] EMIOENET1GMIITXD; - output EMIOENET1GMIITXEN; - output EMIOENET1GMIITXER; - output EMIOENET1MDIOMDC; - output EMIOENET1MDIOO; - output EMIOENET1MDIOTN; - output [7:0] EMIOENET1RXWDATA; - output EMIOENET1RXWEOP; - output EMIOENET1RXWERR; - output EMIOENET1RXWFLUSH; - output EMIOENET1RXWSOP; - output [44:0] EMIOENET1RXWSTATUS; - output EMIOENET1RXWWR; - output [2:0] EMIOENET1SPEEDMODE; - output EMIOENET1TXRRD; - output [3:0] EMIOENET1TXRSTATUS; - output [1:0] EMIOENET2DMABUSWIDTH; - output EMIOENET2DMATXENDTOG; - output [7:0] EMIOENET2GMIITXD; - output EMIOENET2GMIITXEN; - output EMIOENET2GMIITXER; - output EMIOENET2MDIOMDC; - output EMIOENET2MDIOO; - output EMIOENET2MDIOTN; - output [7:0] EMIOENET2RXWDATA; - output EMIOENET2RXWEOP; - output EMIOENET2RXWERR; - output EMIOENET2RXWFLUSH; - output EMIOENET2RXWSOP; - output [44:0] EMIOENET2RXWSTATUS; - output EMIOENET2RXWWR; - output [2:0] EMIOENET2SPEEDMODE; - output EMIOENET2TXRRD; - output [3:0] EMIOENET2TXRSTATUS; - output [1:0] EMIOENET3DMABUSWIDTH; - output EMIOENET3DMATXENDTOG; - output [7:0] EMIOENET3GMIITXD; - output EMIOENET3GMIITXEN; - output EMIOENET3GMIITXER; - output EMIOENET3MDIOMDC; - output EMIOENET3MDIOO; - output EMIOENET3MDIOTN; - output [7:0] EMIOENET3RXWDATA; - output EMIOENET3RXWEOP; - output EMIOENET3RXWERR; - output EMIOENET3RXWFLUSH; - output EMIOENET3RXWSOP; - output [44:0] EMIOENET3RXWSTATUS; - output EMIOENET3RXWWR; - output [2:0] EMIOENET3SPEEDMODE; - output EMIOENET3TXRRD; - output [3:0] EMIOENET3TXRSTATUS; - output EMIOGEM0DELAYREQRX; - output EMIOGEM0DELAYREQTX; - output EMIOGEM0PDELAYREQRX; - output EMIOGEM0PDELAYREQTX; - output EMIOGEM0PDELAYRESPRX; - output EMIOGEM0PDELAYRESPTX; - output EMIOGEM0RXSOF; - output EMIOGEM0SYNCFRAMERX; - output EMIOGEM0SYNCFRAMETX; - output EMIOGEM0TSUTIMERCMPVAL; - output EMIOGEM0TXRFIXEDLAT; - output EMIOGEM0TXSOF; - output EMIOGEM1DELAYREQRX; - output EMIOGEM1DELAYREQTX; - output EMIOGEM1PDELAYREQRX; - output EMIOGEM1PDELAYREQTX; - output EMIOGEM1PDELAYRESPRX; - output EMIOGEM1PDELAYRESPTX; - output EMIOGEM1RXSOF; - output EMIOGEM1SYNCFRAMERX; - output EMIOGEM1SYNCFRAMETX; - output EMIOGEM1TSUTIMERCMPVAL; - output EMIOGEM1TXRFIXEDLAT; - output EMIOGEM1TXSOF; - output EMIOGEM2DELAYREQRX; - output EMIOGEM2DELAYREQTX; - output EMIOGEM2PDELAYREQRX; - output EMIOGEM2PDELAYREQTX; - output EMIOGEM2PDELAYRESPRX; - output EMIOGEM2PDELAYRESPTX; - output EMIOGEM2RXSOF; - output EMIOGEM2SYNCFRAMERX; - output EMIOGEM2SYNCFRAMETX; - output EMIOGEM2TSUTIMERCMPVAL; - output EMIOGEM2TXRFIXEDLAT; - output EMIOGEM2TXSOF; - output EMIOGEM3DELAYREQRX; - output EMIOGEM3DELAYREQTX; - output EMIOGEM3PDELAYREQRX; - output EMIOGEM3PDELAYREQTX; - output EMIOGEM3PDELAYRESPRX; - output EMIOGEM3PDELAYRESPTX; - output EMIOGEM3RXSOF; - output EMIOGEM3SYNCFRAMERX; - output EMIOGEM3SYNCFRAMETX; - output EMIOGEM3TSUTIMERCMPVAL; - output EMIOGEM3TXRFIXEDLAT; - output EMIOGEM3TXSOF; - output [95:0] EMIOGPIOO; - output [95:0] EMIOGPIOTN; - output EMIOI2C0SCLO; - output EMIOI2C0SCLTN; - output EMIOI2C0SDAO; - output EMIOI2C0SDATN; - output EMIOI2C1SCLO; - output EMIOI2C1SCLTN; - output EMIOI2C1SDAO; - output EMIOI2C1SDATN; - output EMIOSDIO0BUSPOWER; - output [2:0] EMIOSDIO0BUSVOLT; - output EMIOSDIO0CLKOUT; - output EMIOSDIO0CMDENA; - output EMIOSDIO0CMDOUT; - output [7:0] EMIOSDIO0DATAENA; - output [7:0] EMIOSDIO0DATAOUT; - output EMIOSDIO0LEDCONTROL; - output EMIOSDIO1BUSPOWER; - output [2:0] EMIOSDIO1BUSVOLT; - output EMIOSDIO1CLKOUT; - output EMIOSDIO1CMDENA; - output EMIOSDIO1CMDOUT; - output [7:0] EMIOSDIO1DATAENA; - output [7:0] EMIOSDIO1DATAOUT; - output EMIOSDIO1LEDCONTROL; - output EMIOSPI0MO; - output EMIOSPI0MOTN; - output EMIOSPI0SCLKO; - output EMIOSPI0SCLKTN; - output EMIOSPI0SO; - output EMIOSPI0SSNTN; - output [2:0] EMIOSPI0SSON; - output EMIOSPI0STN; - output EMIOSPI1MO; - output EMIOSPI1MOTN; - output EMIOSPI1SCLKO; - output EMIOSPI1SCLKTN; - output EMIOSPI1SO; - output EMIOSPI1SSNTN; - output [2:0] EMIOSPI1SSON; - output EMIOSPI1STN; - output [2:0] EMIOTTC0WAVEO; - output [2:0] EMIOTTC1WAVEO; - output [2:0] EMIOTTC2WAVEO; - output [2:0] EMIOTTC3WAVEO; - output EMIOU2DSPORTVBUSCTRLUSB30; - output EMIOU2DSPORTVBUSCTRLUSB31; - output EMIOU3DSPORTVBUSCTRLUSB30; - output EMIOU3DSPORTVBUSCTRLUSB31; - output EMIOUART0DTRN; - output EMIOUART0RTSN; - output EMIOUART0TX; - output EMIOUART1DTRN; - output EMIOUART1RTSN; - output EMIOUART1TX; - output EMIOWDT0RSTO; - output EMIOWDT1RSTO; - output FMIOGEM0FIFORXCLKTOPLBUFG; - output FMIOGEM0FIFOTXCLKTOPLBUFG; - output FMIOGEM1FIFORXCLKTOPLBUFG; - output FMIOGEM1FIFOTXCLKTOPLBUFG; - output FMIOGEM2FIFORXCLKTOPLBUFG; - output FMIOGEM2FIFOTXCLKTOPLBUFG; - output FMIOGEM3FIFORXCLKTOPLBUFG; - output FMIOGEM3FIFOTXCLKTOPLBUFG; - output FMIOGEMTSUCLKTOPLBUFG; - output [31:0] FTMGPO; - output [7:0] GDMA2PLCACK; - output [7:0] GDMA2PLTVLD; - output [39:0] MAXIGP0ARADDR; - output [1:0] MAXIGP0ARBURST; - output [3:0] MAXIGP0ARCACHE; - output [15:0] MAXIGP0ARID; - output [7:0] MAXIGP0ARLEN; - output MAXIGP0ARLOCK; - output [2:0] MAXIGP0ARPROT; - output [3:0] MAXIGP0ARQOS; - output [2:0] MAXIGP0ARSIZE; - output [15:0] MAXIGP0ARUSER; - output MAXIGP0ARVALID; - output [39:0] MAXIGP0AWADDR; - output [1:0] MAXIGP0AWBURST; - output [3:0] MAXIGP0AWCACHE; - output [15:0] MAXIGP0AWID; - output [7:0] MAXIGP0AWLEN; - output MAXIGP0AWLOCK; - output [2:0] MAXIGP0AWPROT; - output [3:0] MAXIGP0AWQOS; - output [2:0] MAXIGP0AWSIZE; - output [15:0] MAXIGP0AWUSER; - output MAXIGP0AWVALID; - output MAXIGP0BREADY; - output MAXIGP0RREADY; - output [127:0] MAXIGP0WDATA; - output MAXIGP0WLAST; - output [15:0] MAXIGP0WSTRB; - output MAXIGP0WVALID; - output [39:0] MAXIGP1ARADDR; - output [1:0] MAXIGP1ARBURST; - output [3:0] MAXIGP1ARCACHE; - output [15:0] MAXIGP1ARID; - output [7:0] MAXIGP1ARLEN; - output MAXIGP1ARLOCK; - output [2:0] MAXIGP1ARPROT; - output [3:0] MAXIGP1ARQOS; - output [2:0] MAXIGP1ARSIZE; - output [15:0] MAXIGP1ARUSER; - output MAXIGP1ARVALID; - output [39:0] MAXIGP1AWADDR; - output [1:0] MAXIGP1AWBURST; - output [3:0] MAXIGP1AWCACHE; - output [15:0] MAXIGP1AWID; - output [7:0] MAXIGP1AWLEN; - output MAXIGP1AWLOCK; - output [2:0] MAXIGP1AWPROT; - output [3:0] MAXIGP1AWQOS; - output [2:0] MAXIGP1AWSIZE; - output [15:0] MAXIGP1AWUSER; - output MAXIGP1AWVALID; - output MAXIGP1BREADY; - output MAXIGP1RREADY; - output [127:0] MAXIGP1WDATA; - output MAXIGP1WLAST; - output [15:0] MAXIGP1WSTRB; - output MAXIGP1WVALID; - output [39:0] MAXIGP2ARADDR; - output [1:0] MAXIGP2ARBURST; - output [3:0] MAXIGP2ARCACHE; - output [15:0] MAXIGP2ARID; - output [7:0] MAXIGP2ARLEN; - output MAXIGP2ARLOCK; - output [2:0] MAXIGP2ARPROT; - output [3:0] MAXIGP2ARQOS; - output [2:0] MAXIGP2ARSIZE; - output [15:0] MAXIGP2ARUSER; - output MAXIGP2ARVALID; - output [39:0] MAXIGP2AWADDR; - output [1:0] MAXIGP2AWBURST; - output [3:0] MAXIGP2AWCACHE; - output [15:0] MAXIGP2AWID; - output [7:0] MAXIGP2AWLEN; - output MAXIGP2AWLOCK; - output [2:0] MAXIGP2AWPROT; - output [3:0] MAXIGP2AWQOS; - output [2:0] MAXIGP2AWSIZE; - output [15:0] MAXIGP2AWUSER; - output MAXIGP2AWVALID; - output MAXIGP2BREADY; - output MAXIGP2RREADY; - output [127:0] MAXIGP2WDATA; - output MAXIGP2WLAST; - output [15:0] MAXIGP2WSTRB; - output MAXIGP2WVALID; - output OSCRTCCLK; - output [3:0] PLCLK; - output PMUAIBAFIFMFPDREQ; - output PMUAIBAFIFMLPDREQ; - output [46:0] PMUERRORTOPL; - output [31:0] PMUPLGPO; - output PSPLEVENTO; - output [63:0] PSPLIRQFPD; - output [99:0] PSPLIRQLPD; - output [3:0] PSPLSTANDBYWFE; - output [3:0] PSPLSTANDBYWFI; - output PSPLTRACECTL; - output [31:0] PSPLTRACEDATA; - output [3:0] PSPLTRIGACK; - output [3:0] PSPLTRIGGER; - output PSS_ALTO_CORE_PAD_MGTTXN0OUT; - output PSS_ALTO_CORE_PAD_MGTTXN1OUT; - output PSS_ALTO_CORE_PAD_MGTTXN2OUT; - output PSS_ALTO_CORE_PAD_MGTTXN3OUT; - output PSS_ALTO_CORE_PAD_MGTTXP0OUT; - output PSS_ALTO_CORE_PAD_MGTTXP1OUT; - output PSS_ALTO_CORE_PAD_MGTTXP2OUT; - output PSS_ALTO_CORE_PAD_MGTTXP3OUT; - output PSS_ALTO_CORE_PAD_PADO; - output RPUEVENTO0; - output RPUEVENTO1; - output [43:0] SACEFPDACADDR; - output [2:0] SACEFPDACPROT; - output [3:0] SACEFPDACSNOOP; - output SACEFPDACVALID; - output SACEFPDARREADY; - output SACEFPDAWREADY; - output [5:0] SACEFPDBID; - output [1:0] SACEFPDBRESP; - output SACEFPDBUSER; - output SACEFPDBVALID; - output SACEFPDCDREADY; - output SACEFPDCRREADY; - output [127:0] SACEFPDRDATA; - output [5:0] SACEFPDRID; - output SACEFPDRLAST; - output [3:0] SACEFPDRRESP; - output SACEFPDRUSER; - output SACEFPDRVALID; - output SACEFPDWREADY; - output SAXIACPARREADY; - output SAXIACPAWREADY; - output [4:0] SAXIACPBID; - output [1:0] SAXIACPBRESP; - output SAXIACPBVALID; - output [127:0] SAXIACPRDATA; - output [4:0] SAXIACPRID; - output SAXIACPRLAST; - output [1:0] SAXIACPRRESP; - output SAXIACPRVALID; - output SAXIACPWREADY; - output SAXIGP0ARREADY; - output SAXIGP0AWREADY; - output [5:0] SAXIGP0BID; - output [1:0] SAXIGP0BRESP; - output SAXIGP0BVALID; - output [3:0] SAXIGP0RACOUNT; - output [7:0] SAXIGP0RCOUNT; - output [127:0] SAXIGP0RDATA; - output [5:0] SAXIGP0RID; - output SAXIGP0RLAST; - output [1:0] SAXIGP0RRESP; - output SAXIGP0RVALID; - output [3:0] SAXIGP0WACOUNT; - output [7:0] SAXIGP0WCOUNT; - output SAXIGP0WREADY; - output SAXIGP1ARREADY; - output SAXIGP1AWREADY; - output [5:0] SAXIGP1BID; - output [1:0] SAXIGP1BRESP; - output SAXIGP1BVALID; - output [3:0] SAXIGP1RACOUNT; - output [7:0] SAXIGP1RCOUNT; - output [127:0] SAXIGP1RDATA; - output [5:0] SAXIGP1RID; - output SAXIGP1RLAST; - output [1:0] SAXIGP1RRESP; - output SAXIGP1RVALID; - output [3:0] SAXIGP1WACOUNT; - output [7:0] SAXIGP1WCOUNT; - output SAXIGP1WREADY; - output SAXIGP2ARREADY; - output SAXIGP2AWREADY; - output [5:0] SAXIGP2BID; - output [1:0] SAXIGP2BRESP; - output SAXIGP2BVALID; - output [3:0] SAXIGP2RACOUNT; - output [7:0] SAXIGP2RCOUNT; - output [127:0] SAXIGP2RDATA; - output [5:0] SAXIGP2RID; - output SAXIGP2RLAST; - output [1:0] SAXIGP2RRESP; - output SAXIGP2RVALID; - output [3:0] SAXIGP2WACOUNT; - output [7:0] SAXIGP2WCOUNT; - output SAXIGP2WREADY; - output SAXIGP3ARREADY; - output SAXIGP3AWREADY; - output [5:0] SAXIGP3BID; - output [1:0] SAXIGP3BRESP; - output SAXIGP3BVALID; - output [3:0] SAXIGP3RACOUNT; - output [7:0] SAXIGP3RCOUNT; - output [127:0] SAXIGP3RDATA; - output [5:0] SAXIGP3RID; - output SAXIGP3RLAST; - output [1:0] SAXIGP3RRESP; - output SAXIGP3RVALID; - output [3:0] SAXIGP3WACOUNT; - output [7:0] SAXIGP3WCOUNT; - output SAXIGP3WREADY; - output SAXIGP4ARREADY; - output SAXIGP4AWREADY; - output [5:0] SAXIGP4BID; - output [1:0] SAXIGP4BRESP; - output SAXIGP4BVALID; - output [3:0] SAXIGP4RACOUNT; - output [7:0] SAXIGP4RCOUNT; - output [127:0] SAXIGP4RDATA; - output [5:0] SAXIGP4RID; - output SAXIGP4RLAST; - output [1:0] SAXIGP4RRESP; - output SAXIGP4RVALID; - output [3:0] SAXIGP4WACOUNT; - output [7:0] SAXIGP4WCOUNT; - output SAXIGP4WREADY; - output SAXIGP5ARREADY; - output SAXIGP5AWREADY; - output [5:0] SAXIGP5BID; - output [1:0] SAXIGP5BRESP; - output SAXIGP5BVALID; - output [3:0] SAXIGP5RACOUNT; - output [7:0] SAXIGP5RCOUNT; - output [127:0] SAXIGP5RDATA; - output [5:0] SAXIGP5RID; - output SAXIGP5RLAST; - output [1:0] SAXIGP5RRESP; - output SAXIGP5RVALID; - output [3:0] SAXIGP5WACOUNT; - output [7:0] SAXIGP5WCOUNT; - output SAXIGP5WREADY; - output SAXIGP6ARREADY; - output SAXIGP6AWREADY; - output [5:0] SAXIGP6BID; - output [1:0] SAXIGP6BRESP; - output SAXIGP6BVALID; - output [3:0] SAXIGP6RACOUNT; - output [7:0] SAXIGP6RCOUNT; - output [127:0] SAXIGP6RDATA; - output [5:0] SAXIGP6RID; - output SAXIGP6RLAST; - output [1:0] SAXIGP6RRESP; - output SAXIGP6RVALID; - output [3:0] SAXIGP6WACOUNT; - output [7:0] SAXIGP6WCOUNT; - output SAXIGP6WREADY; - inout [3:0] PSS_ALTO_CORE_PAD_BOOTMODE; - inout PSS_ALTO_CORE_PAD_CLK; - inout PSS_ALTO_CORE_PAD_DONEB; - inout [17:0] PSS_ALTO_CORE_PAD_DRAMA; - inout PSS_ALTO_CORE_PAD_DRAMACTN; - inout PSS_ALTO_CORE_PAD_DRAMALERTN; - inout [1:0] PSS_ALTO_CORE_PAD_DRAMBA; - inout [1:0] PSS_ALTO_CORE_PAD_DRAMBG; - inout [1:0] PSS_ALTO_CORE_PAD_DRAMCK; - inout [1:0] PSS_ALTO_CORE_PAD_DRAMCKE; - inout [1:0] PSS_ALTO_CORE_PAD_DRAMCKN; - inout [1:0] PSS_ALTO_CORE_PAD_DRAMCSN; - inout [8:0] PSS_ALTO_CORE_PAD_DRAMDM; - inout [71:0] PSS_ALTO_CORE_PAD_DRAMDQ; - inout [8:0] PSS_ALTO_CORE_PAD_DRAMDQS; - inout [8:0] PSS_ALTO_CORE_PAD_DRAMDQSN; - inout [1:0] PSS_ALTO_CORE_PAD_DRAMODT; - inout PSS_ALTO_CORE_PAD_DRAMPARITY; - inout PSS_ALTO_CORE_PAD_DRAMRAMRSTN; - inout PSS_ALTO_CORE_PAD_ERROROUT; - inout PSS_ALTO_CORE_PAD_ERRORSTATUS; - inout PSS_ALTO_CORE_PAD_INITB; - inout PSS_ALTO_CORE_PAD_JTAGTCK; - inout PSS_ALTO_CORE_PAD_JTAGTDI; - inout PSS_ALTO_CORE_PAD_JTAGTDO; - inout PSS_ALTO_CORE_PAD_JTAGTMS; - inout [77:0] PSS_ALTO_CORE_PAD_MIO; - inout PSS_ALTO_CORE_PAD_PORB; - inout PSS_ALTO_CORE_PAD_PROGB; - inout PSS_ALTO_CORE_PAD_RCALIBINOUT; - inout PSS_ALTO_CORE_PAD_SRSTB; - inout PSS_ALTO_CORE_PAD_ZQ; - input [7:0] ADMAFCICLK; - input AIBPMUAFIFMFPDACK; - input AIBPMUAFIFMLPDACK; - input DDRCEXTREFRESHRANK0REQ; - input DDRCEXTREFRESHRANK1REQ; - input DDRCREFRESHPLCLK; - input DPAUXDATAIN; - input DPEXTERNALCUSTOMEVENT1; - input DPEXTERNALCUSTOMEVENT2; - input DPEXTERNALVSYNCEVENT; - input DPHOTPLUGDETECT; - input [7:0] DPLIVEGFXALPHAIN; - input [35:0] DPLIVEGFXPIXEL1IN; - input DPLIVEVIDEOINDE; - input DPLIVEVIDEOINHSYNC; - input [35:0] DPLIVEVIDEOINPIXEL1; - input DPLIVEVIDEOINVSYNC; - input DPMAXISMIXEDAUDIOTREADY; - input DPSAXISAUDIOCLK; - input [31:0] DPSAXISAUDIOTDATA; - input DPSAXISAUDIOTID; - input DPSAXISAUDIOTVALID; - input DPVIDEOINCLK; - input EMIOCAN0PHYRX; - input EMIOCAN1PHYRX; - input EMIOENET0DMATXSTATUSTOG; - input EMIOENET0EXTINTIN; - input EMIOENET0GMIICOL; - input EMIOENET0GMIICRS; - input EMIOENET0GMIIRXCLK; - input [7:0] EMIOENET0GMIIRXD; - input EMIOENET0GMIIRXDV; - input EMIOENET0GMIIRXER; - input EMIOENET0GMIITXCLK; - input EMIOENET0MDIOI; - input EMIOENET0RXWOVERFLOW; - input EMIOENET0TXRCONTROL; - input [7:0] EMIOENET0TXRDATA; - input EMIOENET0TXRDATARDY; - input EMIOENET0TXREOP; - input EMIOENET0TXRERR; - input EMIOENET0TXRFLUSHED; - input EMIOENET0TXRSOP; - input EMIOENET0TXRUNDERFLOW; - input EMIOENET0TXRVALID; - input EMIOENET1DMATXSTATUSTOG; - input EMIOENET1EXTINTIN; - input EMIOENET1GMIICOL; - input EMIOENET1GMIICRS; - input EMIOENET1GMIIRXCLK; - input [7:0] EMIOENET1GMIIRXD; - input EMIOENET1GMIIRXDV; - input EMIOENET1GMIIRXER; - input EMIOENET1GMIITXCLK; - input EMIOENET1MDIOI; - input EMIOENET1RXWOVERFLOW; - input EMIOENET1TXRCONTROL; - input [7:0] EMIOENET1TXRDATA; - input EMIOENET1TXRDATARDY; - input EMIOENET1TXREOP; - input EMIOENET1TXRERR; - input EMIOENET1TXRFLUSHED; - input EMIOENET1TXRSOP; - input EMIOENET1TXRUNDERFLOW; - input EMIOENET1TXRVALID; - input EMIOENET2DMATXSTATUSTOG; - input EMIOENET2EXTINTIN; - input EMIOENET2GMIICOL; - input EMIOENET2GMIICRS; - input EMIOENET2GMIIRXCLK; - input [7:0] EMIOENET2GMIIRXD; - input EMIOENET2GMIIRXDV; - input EMIOENET2GMIIRXER; - input EMIOENET2GMIITXCLK; - input EMIOENET2MDIOI; - input EMIOENET2RXWOVERFLOW; - input EMIOENET2TXRCONTROL; - input [7:0] EMIOENET2TXRDATA; - input EMIOENET2TXRDATARDY; - input EMIOENET2TXREOP; - input EMIOENET2TXRERR; - input EMIOENET2TXRFLUSHED; - input EMIOENET2TXRSOP; - input EMIOENET2TXRUNDERFLOW; - input EMIOENET2TXRVALID; - input EMIOENET3DMATXSTATUSTOG; - input EMIOENET3EXTINTIN; - input EMIOENET3GMIICOL; - input EMIOENET3GMIICRS; - input EMIOENET3GMIIRXCLK; - input [7:0] EMIOENET3GMIIRXD; - input EMIOENET3GMIIRXDV; - input EMIOENET3GMIIRXER; - input EMIOENET3GMIITXCLK; - input EMIOENET3MDIOI; - input EMIOENET3RXWOVERFLOW; - input EMIOENET3TXRCONTROL; - input [7:0] EMIOENET3TXRDATA; - input EMIOENET3TXRDATARDY; - input EMIOENET3TXREOP; - input EMIOENET3TXRERR; - input EMIOENET3TXRFLUSHED; - input EMIOENET3TXRSOP; - input EMIOENET3TXRUNDERFLOW; - input EMIOENET3TXRVALID; - input EMIOENETTSUCLK; - input [1:0] EMIOGEM0TSUINCCTRL; - input [1:0] EMIOGEM1TSUINCCTRL; - input [1:0] EMIOGEM2TSUINCCTRL; - input [1:0] EMIOGEM3TSUINCCTRL; - input [95:0] EMIOGPIOI; - input EMIOHUBPORTOVERCRNTUSB20; - input EMIOHUBPORTOVERCRNTUSB21; - input EMIOHUBPORTOVERCRNTUSB30; - input EMIOHUBPORTOVERCRNTUSB31; - input EMIOI2C0SCLI; - input EMIOI2C0SDAI; - input EMIOI2C1SCLI; - input EMIOI2C1SDAI; - input EMIOSDIO0CDN; - input EMIOSDIO0CMDIN; - input [7:0] EMIOSDIO0DATAIN; - input EMIOSDIO0FBCLKIN; - input EMIOSDIO0WP; - input EMIOSDIO1CDN; - input EMIOSDIO1CMDIN; - input [7:0] EMIOSDIO1DATAIN; - input EMIOSDIO1FBCLKIN; - input EMIOSDIO1WP; - input EMIOSPI0MI; - input EMIOSPI0SCLKI; - input EMIOSPI0SI; - input EMIOSPI0SSIN; - input EMIOSPI1MI; - input EMIOSPI1SCLKI; - input EMIOSPI1SI; - input EMIOSPI1SSIN; - input [2:0] EMIOTTC0CLKI; - input [2:0] EMIOTTC1CLKI; - input [2:0] EMIOTTC2CLKI; - input [2:0] EMIOTTC3CLKI; - input EMIOUART0CTSN; - input EMIOUART0DCDN; - input EMIOUART0DSRN; - input EMIOUART0RIN; - input EMIOUART0RX; - input EMIOUART1CTSN; - input EMIOUART1DCDN; - input EMIOUART1DSRN; - input EMIOUART1RIN; - input EMIOUART1RX; - input EMIOWDT0CLKI; - input EMIOWDT1CLKI; - input FMIOGEM0FIFORXCLKFROMPL; - input FMIOGEM0FIFOTXCLKFROMPL; - input FMIOGEM0SIGNALDETECT; - input FMIOGEM1FIFORXCLKFROMPL; - input FMIOGEM1FIFOTXCLKFROMPL; - input FMIOGEM1SIGNALDETECT; - input FMIOGEM2FIFORXCLKFROMPL; - input FMIOGEM2FIFOTXCLKFROMPL; - input FMIOGEM2SIGNALDETECT; - input FMIOGEM3FIFORXCLKFROMPL; - input FMIOGEM3FIFOTXCLKFROMPL; - input FMIOGEM3SIGNALDETECT; - input FMIOGEMTSUCLKFROMPL; - input [31:0] FTMGPI; - input [7:0] GDMAFCICLK; - input MAXIGP0ACLK; - input MAXIGP0ARREADY; - input MAXIGP0AWREADY; - input [15:0] MAXIGP0BID; - input [1:0] MAXIGP0BRESP; - input MAXIGP0BVALID; - input [127:0] MAXIGP0RDATA; - input [15:0] MAXIGP0RID; - input MAXIGP0RLAST; - input [1:0] MAXIGP0RRESP; - input MAXIGP0RVALID; - input MAXIGP0WREADY; - input MAXIGP1ACLK; - input MAXIGP1ARREADY; - input MAXIGP1AWREADY; - input [15:0] MAXIGP1BID; - input [1:0] MAXIGP1BRESP; - input MAXIGP1BVALID; - input [127:0] MAXIGP1RDATA; - input [15:0] MAXIGP1RID; - input MAXIGP1RLAST; - input [1:0] MAXIGP1RRESP; - input MAXIGP1RVALID; - input MAXIGP1WREADY; - input MAXIGP2ACLK; - input MAXIGP2ARREADY; - input MAXIGP2AWREADY; - input [15:0] MAXIGP2BID; - input [1:0] MAXIGP2BRESP; - input MAXIGP2BVALID; - input [127:0] MAXIGP2RDATA; - input [15:0] MAXIGP2RID; - input MAXIGP2RLAST; - input [1:0] MAXIGP2RRESP; - input MAXIGP2RVALID; - input MAXIGP2WREADY; - input NFIQ0LPDRPU; - input NFIQ1LPDRPU; - input NIRQ0LPDRPU; - input NIRQ1LPDRPU; - input [7:0] PL2ADMACVLD; - input [7:0] PL2ADMATACK; - input [7:0] PL2GDMACVLD; - input [7:0] PL2GDMATACK; - input PLACECLK; - input PLACPINACT; - input [3:0] PLFPGASTOP; - input [2:0] PLLAUXREFCLKFPD; - input [1:0] PLLAUXREFCLKLPD; - input [31:0] PLPMUGPI; - input [3:0] PLPSAPUGICFIQ; - input [3:0] PLPSAPUGICIRQ; - input PLPSEVENTI; - input [7:0] PLPSIRQ0; - input [7:0] PLPSIRQ1; - input PLPSTRACECLK; - input [3:0] PLPSTRIGACK; - input [3:0] PLPSTRIGGER; - input [3:0] PMUERRORFROMPL; - input PSS_ALTO_CORE_PAD_MGTRXN0IN; - input PSS_ALTO_CORE_PAD_MGTRXN1IN; - input PSS_ALTO_CORE_PAD_MGTRXN2IN; - input PSS_ALTO_CORE_PAD_MGTRXN3IN; - input PSS_ALTO_CORE_PAD_MGTRXP0IN; - input PSS_ALTO_CORE_PAD_MGTRXP1IN; - input PSS_ALTO_CORE_PAD_MGTRXP2IN; - input PSS_ALTO_CORE_PAD_MGTRXP3IN; - input PSS_ALTO_CORE_PAD_PADI; - input PSS_ALTO_CORE_PAD_REFN0IN; - input PSS_ALTO_CORE_PAD_REFN1IN; - input PSS_ALTO_CORE_PAD_REFN2IN; - input PSS_ALTO_CORE_PAD_REFN3IN; - input PSS_ALTO_CORE_PAD_REFP0IN; - input PSS_ALTO_CORE_PAD_REFP1IN; - input PSS_ALTO_CORE_PAD_REFP2IN; - input PSS_ALTO_CORE_PAD_REFP3IN; - input RPUEVENTI0; - input RPUEVENTI1; - input SACEFPDACREADY; - input [43:0] SACEFPDARADDR; - input [1:0] SACEFPDARBAR; - input [1:0] SACEFPDARBURST; - input [3:0] SACEFPDARCACHE; - input [1:0] SACEFPDARDOMAIN; - input [5:0] SACEFPDARID; - input [7:0] SACEFPDARLEN; - input SACEFPDARLOCK; - input [2:0] SACEFPDARPROT; - input [3:0] SACEFPDARQOS; - input [3:0] SACEFPDARREGION; - input [2:0] SACEFPDARSIZE; - input [3:0] SACEFPDARSNOOP; - input [15:0] SACEFPDARUSER; - input SACEFPDARVALID; - input [43:0] SACEFPDAWADDR; - input [1:0] SACEFPDAWBAR; - input [1:0] SACEFPDAWBURST; - input [3:0] SACEFPDAWCACHE; - input [1:0] SACEFPDAWDOMAIN; - input [5:0] SACEFPDAWID; - input [7:0] SACEFPDAWLEN; - input SACEFPDAWLOCK; - input [2:0] SACEFPDAWPROT; - input [3:0] SACEFPDAWQOS; - input [3:0] SACEFPDAWREGION; - input [2:0] SACEFPDAWSIZE; - input [2:0] SACEFPDAWSNOOP; - input [15:0] SACEFPDAWUSER; - input SACEFPDAWVALID; - input SACEFPDBREADY; - input [127:0] SACEFPDCDDATA; - input SACEFPDCDLAST; - input SACEFPDCDVALID; - input [4:0] SACEFPDCRRESP; - input SACEFPDCRVALID; - input SACEFPDRACK; - input SACEFPDRREADY; - input SACEFPDWACK; - input [127:0] SACEFPDWDATA; - input SACEFPDWLAST; - input [15:0] SACEFPDWSTRB; - input SACEFPDWUSER; - input SACEFPDWVALID; - input SAXIACPACLK; - input [39:0] SAXIACPARADDR; - input [1:0] SAXIACPARBURST; - input [3:0] SAXIACPARCACHE; - input [4:0] SAXIACPARID; - input [7:0] SAXIACPARLEN; - input SAXIACPARLOCK; - input [2:0] SAXIACPARPROT; - input [3:0] SAXIACPARQOS; - input [2:0] SAXIACPARSIZE; - input [1:0] SAXIACPARUSER; - input SAXIACPARVALID; - input [39:0] SAXIACPAWADDR; - input [1:0] SAXIACPAWBURST; - input [3:0] SAXIACPAWCACHE; - input [4:0] SAXIACPAWID; - input [7:0] SAXIACPAWLEN; - input SAXIACPAWLOCK; - input [2:0] SAXIACPAWPROT; - input [3:0] SAXIACPAWQOS; - input [2:0] SAXIACPAWSIZE; - input [1:0] SAXIACPAWUSER; - input SAXIACPAWVALID; - input SAXIACPBREADY; - input SAXIACPRREADY; - input [127:0] SAXIACPWDATA; - input SAXIACPWLAST; - input [15:0] SAXIACPWSTRB; - input SAXIACPWVALID; - input [48:0] SAXIGP0ARADDR; - input [1:0] SAXIGP0ARBURST; - input [3:0] SAXIGP0ARCACHE; - input [5:0] SAXIGP0ARID; - input [7:0] SAXIGP0ARLEN; - input SAXIGP0ARLOCK; - input [2:0] SAXIGP0ARPROT; - input [3:0] SAXIGP0ARQOS; - input [2:0] SAXIGP0ARSIZE; - input SAXIGP0ARUSER; - input SAXIGP0ARVALID; - input [48:0] SAXIGP0AWADDR; - input [1:0] SAXIGP0AWBURST; - input [3:0] SAXIGP0AWCACHE; - input [5:0] SAXIGP0AWID; - input [7:0] SAXIGP0AWLEN; - input SAXIGP0AWLOCK; - input [2:0] SAXIGP0AWPROT; - input [3:0] SAXIGP0AWQOS; - input [2:0] SAXIGP0AWSIZE; - input SAXIGP0AWUSER; - input SAXIGP0AWVALID; - input SAXIGP0BREADY; - input SAXIGP0RCLK; - input SAXIGP0RREADY; - input SAXIGP0WCLK; - input [127:0] SAXIGP0WDATA; - input SAXIGP0WLAST; - input [15:0] SAXIGP0WSTRB; - input SAXIGP0WVALID; - input [48:0] SAXIGP1ARADDR; - input [1:0] SAXIGP1ARBURST; - input [3:0] SAXIGP1ARCACHE; - input [5:0] SAXIGP1ARID; - input [7:0] SAXIGP1ARLEN; - input SAXIGP1ARLOCK; - input [2:0] SAXIGP1ARPROT; - input [3:0] SAXIGP1ARQOS; - input [2:0] SAXIGP1ARSIZE; - input SAXIGP1ARUSER; - input SAXIGP1ARVALID; - input [48:0] SAXIGP1AWADDR; - input [1:0] SAXIGP1AWBURST; - input [3:0] SAXIGP1AWCACHE; - input [5:0] SAXIGP1AWID; - input [7:0] SAXIGP1AWLEN; - input SAXIGP1AWLOCK; - input [2:0] SAXIGP1AWPROT; - input [3:0] SAXIGP1AWQOS; - input [2:0] SAXIGP1AWSIZE; - input SAXIGP1AWUSER; - input SAXIGP1AWVALID; - input SAXIGP1BREADY; - input SAXIGP1RCLK; - input SAXIGP1RREADY; - input SAXIGP1WCLK; - input [127:0] SAXIGP1WDATA; - input SAXIGP1WLAST; - input [15:0] SAXIGP1WSTRB; - input SAXIGP1WVALID; - input [48:0] SAXIGP2ARADDR; - input [1:0] SAXIGP2ARBURST; - input [3:0] SAXIGP2ARCACHE; - input [5:0] SAXIGP2ARID; - input [7:0] SAXIGP2ARLEN; - input SAXIGP2ARLOCK; - input [2:0] SAXIGP2ARPROT; - input [3:0] SAXIGP2ARQOS; - input [2:0] SAXIGP2ARSIZE; - input SAXIGP2ARUSER; - input SAXIGP2ARVALID; - input [48:0] SAXIGP2AWADDR; - input [1:0] SAXIGP2AWBURST; - input [3:0] SAXIGP2AWCACHE; - input [5:0] SAXIGP2AWID; - input [7:0] SAXIGP2AWLEN; - input SAXIGP2AWLOCK; - input [2:0] SAXIGP2AWPROT; - input [3:0] SAXIGP2AWQOS; - input [2:0] SAXIGP2AWSIZE; - input SAXIGP2AWUSER; - input SAXIGP2AWVALID; - input SAXIGP2BREADY; - input SAXIGP2RCLK; - input SAXIGP2RREADY; - input SAXIGP2WCLK; - input [127:0] SAXIGP2WDATA; - input SAXIGP2WLAST; - input [15:0] SAXIGP2WSTRB; - input SAXIGP2WVALID; - input [48:0] SAXIGP3ARADDR; - input [1:0] SAXIGP3ARBURST; - input [3:0] SAXIGP3ARCACHE; - input [5:0] SAXIGP3ARID; - input [7:0] SAXIGP3ARLEN; - input SAXIGP3ARLOCK; - input [2:0] SAXIGP3ARPROT; - input [3:0] SAXIGP3ARQOS; - input [2:0] SAXIGP3ARSIZE; - input SAXIGP3ARUSER; - input SAXIGP3ARVALID; - input [48:0] SAXIGP3AWADDR; - input [1:0] SAXIGP3AWBURST; - input [3:0] SAXIGP3AWCACHE; - input [5:0] SAXIGP3AWID; - input [7:0] SAXIGP3AWLEN; - input SAXIGP3AWLOCK; - input [2:0] SAXIGP3AWPROT; - input [3:0] SAXIGP3AWQOS; - input [2:0] SAXIGP3AWSIZE; - input SAXIGP3AWUSER; - input SAXIGP3AWVALID; - input SAXIGP3BREADY; - input SAXIGP3RCLK; - input SAXIGP3RREADY; - input SAXIGP3WCLK; - input [127:0] SAXIGP3WDATA; - input SAXIGP3WLAST; - input [15:0] SAXIGP3WSTRB; - input SAXIGP3WVALID; - input [48:0] SAXIGP4ARADDR; - input [1:0] SAXIGP4ARBURST; - input [3:0] SAXIGP4ARCACHE; - input [5:0] SAXIGP4ARID; - input [7:0] SAXIGP4ARLEN; - input SAXIGP4ARLOCK; - input [2:0] SAXIGP4ARPROT; - input [3:0] SAXIGP4ARQOS; - input [2:0] SAXIGP4ARSIZE; - input SAXIGP4ARUSER; - input SAXIGP4ARVALID; - input [48:0] SAXIGP4AWADDR; - input [1:0] SAXIGP4AWBURST; - input [3:0] SAXIGP4AWCACHE; - input [5:0] SAXIGP4AWID; - input [7:0] SAXIGP4AWLEN; - input SAXIGP4AWLOCK; - input [2:0] SAXIGP4AWPROT; - input [3:0] SAXIGP4AWQOS; - input [2:0] SAXIGP4AWSIZE; - input SAXIGP4AWUSER; - input SAXIGP4AWVALID; - input SAXIGP4BREADY; - input SAXIGP4RCLK; - input SAXIGP4RREADY; - input SAXIGP4WCLK; - input [127:0] SAXIGP4WDATA; - input SAXIGP4WLAST; - input [15:0] SAXIGP4WSTRB; - input SAXIGP4WVALID; - input [48:0] SAXIGP5ARADDR; - input [1:0] SAXIGP5ARBURST; - input [3:0] SAXIGP5ARCACHE; - input [5:0] SAXIGP5ARID; - input [7:0] SAXIGP5ARLEN; - input SAXIGP5ARLOCK; - input [2:0] SAXIGP5ARPROT; - input [3:0] SAXIGP5ARQOS; - input [2:0] SAXIGP5ARSIZE; - input SAXIGP5ARUSER; - input SAXIGP5ARVALID; - input [48:0] SAXIGP5AWADDR; - input [1:0] SAXIGP5AWBURST; - input [3:0] SAXIGP5AWCACHE; - input [5:0] SAXIGP5AWID; - input [7:0] SAXIGP5AWLEN; - input SAXIGP5AWLOCK; - input [2:0] SAXIGP5AWPROT; - input [3:0] SAXIGP5AWQOS; - input [2:0] SAXIGP5AWSIZE; - input SAXIGP5AWUSER; - input SAXIGP5AWVALID; - input SAXIGP5BREADY; - input SAXIGP5RCLK; - input SAXIGP5RREADY; - input SAXIGP5WCLK; - input [127:0] SAXIGP5WDATA; - input SAXIGP5WLAST; - input [15:0] SAXIGP5WSTRB; - input SAXIGP5WVALID; - input [48:0] SAXIGP6ARADDR; - input [1:0] SAXIGP6ARBURST; - input [3:0] SAXIGP6ARCACHE; - input [5:0] SAXIGP6ARID; - input [7:0] SAXIGP6ARLEN; - input SAXIGP6ARLOCK; - input [2:0] SAXIGP6ARPROT; - input [3:0] SAXIGP6ARQOS; - input [2:0] SAXIGP6ARSIZE; - input SAXIGP6ARUSER; - input SAXIGP6ARVALID; - input [48:0] SAXIGP6AWADDR; - input [1:0] SAXIGP6AWBURST; - input [3:0] SAXIGP6AWCACHE; - input [5:0] SAXIGP6AWID; - input [7:0] SAXIGP6AWLEN; - input SAXIGP6AWLOCK; - input [2:0] SAXIGP6AWPROT; - input [3:0] SAXIGP6AWQOS; - input [2:0] SAXIGP6AWSIZE; - input SAXIGP6AWUSER; - input SAXIGP6AWVALID; - input SAXIGP6BREADY; - input SAXIGP6RCLK; - input SAXIGP6RREADY; - input SAXIGP6WCLK; - input [127:0] SAXIGP6WDATA; - input SAXIGP6WLAST; - input [15:0] SAXIGP6WSTRB; - input SAXIGP6WVALID; - input [59:0] STMEVENT; -endmodule - -module ILKN (...); - parameter BYPASS = "FALSE"; - parameter [1:0] CTL_RX_BURSTMAX = 2'h3; - parameter [1:0] CTL_RX_CHAN_EXT = 2'h0; - parameter [3:0] CTL_RX_LAST_LANE = 4'hB; - parameter [15:0] CTL_RX_MFRAMELEN_MINUS1 = 16'h07FF; - parameter CTL_RX_PACKET_MODE = "TRUE"; - parameter [2:0] CTL_RX_RETRANS_MULT = 3'h0; - parameter [3:0] CTL_RX_RETRANS_RETRY = 4'h2; - parameter [15:0] CTL_RX_RETRANS_TIMER1 = 16'h0000; - parameter [15:0] CTL_RX_RETRANS_TIMER2 = 16'h0008; - parameter [11:0] CTL_RX_RETRANS_WDOG = 12'h000; - parameter [7:0] CTL_RX_RETRANS_WRAP_TIMER = 8'h00; - parameter CTL_TEST_MODE_PIN_CHAR = "FALSE"; - parameter [1:0] CTL_TX_BURSTMAX = 2'h3; - parameter [2:0] CTL_TX_BURSTSHORT = 3'h1; - parameter [1:0] CTL_TX_CHAN_EXT = 2'h0; - parameter CTL_TX_DISABLE_SKIPWORD = "TRUE"; - parameter [6:0] CTL_TX_FC_CALLEN = 7'h00; - parameter [3:0] CTL_TX_LAST_LANE = 4'hB; - parameter [15:0] CTL_TX_MFRAMELEN_MINUS1 = 16'h07FF; - parameter [13:0] CTL_TX_RETRANS_DEPTH = 14'h0800; - parameter [2:0] CTL_TX_RETRANS_MULT = 3'h0; - parameter [1:0] CTL_TX_RETRANS_RAM_BANKS = 2'h3; - parameter MODE = "TRUE"; - parameter SIM_VERSION = "2.0"; - parameter TEST_MODE_PIN_CHAR = "FALSE"; - output [15:0] DRP_DO; - output DRP_RDY; - output [65:0] RX_BYPASS_DATAOUT00; - output [65:0] RX_BYPASS_DATAOUT01; - output [65:0] RX_BYPASS_DATAOUT02; - output [65:0] RX_BYPASS_DATAOUT03; - output [65:0] RX_BYPASS_DATAOUT04; - output [65:0] RX_BYPASS_DATAOUT05; - output [65:0] RX_BYPASS_DATAOUT06; - output [65:0] RX_BYPASS_DATAOUT07; - output [65:0] RX_BYPASS_DATAOUT08; - output [65:0] RX_BYPASS_DATAOUT09; - output [65:0] RX_BYPASS_DATAOUT10; - output [65:0] RX_BYPASS_DATAOUT11; - output [11:0] RX_BYPASS_ENAOUT; - output [11:0] RX_BYPASS_IS_AVAILOUT; - output [11:0] RX_BYPASS_IS_BADLYFRAMEDOUT; - output [11:0] RX_BYPASS_IS_OVERFLOWOUT; - output [11:0] RX_BYPASS_IS_SYNCEDOUT; - output [11:0] RX_BYPASS_IS_SYNCWORDOUT; - output [10:0] RX_CHANOUT0; - output [10:0] RX_CHANOUT1; - output [10:0] RX_CHANOUT2; - output [10:0] RX_CHANOUT3; - output [127:0] RX_DATAOUT0; - output [127:0] RX_DATAOUT1; - output [127:0] RX_DATAOUT2; - output [127:0] RX_DATAOUT3; - output RX_ENAOUT0; - output RX_ENAOUT1; - output RX_ENAOUT2; - output RX_ENAOUT3; - output RX_EOPOUT0; - output RX_EOPOUT1; - output RX_EOPOUT2; - output RX_EOPOUT3; - output RX_ERROUT0; - output RX_ERROUT1; - output RX_ERROUT2; - output RX_ERROUT3; - output [3:0] RX_MTYOUT0; - output [3:0] RX_MTYOUT1; - output [3:0] RX_MTYOUT2; - output [3:0] RX_MTYOUT3; - output RX_OVFOUT; - output RX_SOPOUT0; - output RX_SOPOUT1; - output RX_SOPOUT2; - output RX_SOPOUT3; - output STAT_RX_ALIGNED; - output STAT_RX_ALIGNED_ERR; - output [11:0] STAT_RX_BAD_TYPE_ERR; - output STAT_RX_BURSTMAX_ERR; - output STAT_RX_BURST_ERR; - output STAT_RX_CRC24_ERR; - output [11:0] STAT_RX_CRC32_ERR; - output [11:0] STAT_RX_CRC32_VALID; - output [11:0] STAT_RX_DESCRAM_ERR; - output [11:0] STAT_RX_DIAGWORD_INTFSTAT; - output [11:0] STAT_RX_DIAGWORD_LANESTAT; - output [255:0] STAT_RX_FC_STAT; - output [11:0] STAT_RX_FRAMING_ERR; - output STAT_RX_MEOP_ERR; - output [11:0] STAT_RX_MF_ERR; - output [11:0] STAT_RX_MF_LEN_ERR; - output [11:0] STAT_RX_MF_REPEAT_ERR; - output STAT_RX_MISALIGNED; - output STAT_RX_MSOP_ERR; - output [7:0] STAT_RX_MUBITS; - output STAT_RX_MUBITS_UPDATED; - output STAT_RX_OVERFLOW_ERR; - output STAT_RX_RETRANS_CRC24_ERR; - output STAT_RX_RETRANS_DISC; - output [15:0] STAT_RX_RETRANS_LATENCY; - output STAT_RX_RETRANS_REQ; - output STAT_RX_RETRANS_RETRY_ERR; - output [7:0] STAT_RX_RETRANS_SEQ; - output STAT_RX_RETRANS_SEQ_UPDATED; - output [2:0] STAT_RX_RETRANS_STATE; - output [4:0] STAT_RX_RETRANS_SUBSEQ; - output STAT_RX_RETRANS_WDOG_ERR; - output STAT_RX_RETRANS_WRAP_ERR; - output [11:0] STAT_RX_SYNCED; - output [11:0] STAT_RX_SYNCED_ERR; - output [11:0] STAT_RX_WORD_SYNC; - output STAT_TX_BURST_ERR; - output STAT_TX_ERRINJ_BITERR_DONE; - output STAT_TX_OVERFLOW_ERR; - output STAT_TX_RETRANS_BURST_ERR; - output STAT_TX_RETRANS_BUSY; - output STAT_TX_RETRANS_RAM_PERROUT; - output [8:0] STAT_TX_RETRANS_RAM_RADDR; - output STAT_TX_RETRANS_RAM_RD_B0; - output STAT_TX_RETRANS_RAM_RD_B1; - output STAT_TX_RETRANS_RAM_RD_B2; - output STAT_TX_RETRANS_RAM_RD_B3; - output [1:0] STAT_TX_RETRANS_RAM_RSEL; - output [8:0] STAT_TX_RETRANS_RAM_WADDR; - output [643:0] STAT_TX_RETRANS_RAM_WDATA; - output STAT_TX_RETRANS_RAM_WE_B0; - output STAT_TX_RETRANS_RAM_WE_B1; - output STAT_TX_RETRANS_RAM_WE_B2; - output STAT_TX_RETRANS_RAM_WE_B3; - output STAT_TX_UNDERFLOW_ERR; - output TX_OVFOUT; - output TX_RDYOUT; - output [63:0] TX_SERDES_DATA00; - output [63:0] TX_SERDES_DATA01; - output [63:0] TX_SERDES_DATA02; - output [63:0] TX_SERDES_DATA03; - output [63:0] TX_SERDES_DATA04; - output [63:0] TX_SERDES_DATA05; - output [63:0] TX_SERDES_DATA06; - output [63:0] TX_SERDES_DATA07; - output [63:0] TX_SERDES_DATA08; - output [63:0] TX_SERDES_DATA09; - output [63:0] TX_SERDES_DATA10; - output [63:0] TX_SERDES_DATA11; - input CORE_CLK; - input CTL_RX_FORCE_RESYNC; - input CTL_RX_RETRANS_ACK; - input CTL_RX_RETRANS_ENABLE; - input CTL_RX_RETRANS_ERRIN; - input CTL_RX_RETRANS_FORCE_REQ; - input CTL_RX_RETRANS_RESET; - input CTL_RX_RETRANS_RESET_MODE; - input CTL_TX_DIAGWORD_INTFSTAT; - input [11:0] CTL_TX_DIAGWORD_LANESTAT; - input CTL_TX_ENABLE; - input CTL_TX_ERRINJ_BITERR_GO; - input [3:0] CTL_TX_ERRINJ_BITERR_LANE; - input [255:0] CTL_TX_FC_STAT; - input [7:0] CTL_TX_MUBITS; - input CTL_TX_RETRANS_ENABLE; - input CTL_TX_RETRANS_RAM_PERRIN; - input [643:0] CTL_TX_RETRANS_RAM_RDATA; - input CTL_TX_RETRANS_REQ; - input CTL_TX_RETRANS_REQ_VALID; - input [11:0] CTL_TX_RLIM_DELTA; - input CTL_TX_RLIM_ENABLE; - input [7:0] CTL_TX_RLIM_INTV; - input [11:0] CTL_TX_RLIM_MAX; - input [9:0] DRP_ADDR; - input DRP_CLK; - input [15:0] DRP_DI; - input DRP_EN; - input DRP_WE; - input LBUS_CLK; - input RX_BYPASS_FORCE_REALIGNIN; - input RX_BYPASS_RDIN; - input RX_RESET; - input [11:0] RX_SERDES_CLK; - input [63:0] RX_SERDES_DATA00; - input [63:0] RX_SERDES_DATA01; - input [63:0] RX_SERDES_DATA02; - input [63:0] RX_SERDES_DATA03; - input [63:0] RX_SERDES_DATA04; - input [63:0] RX_SERDES_DATA05; - input [63:0] RX_SERDES_DATA06; - input [63:0] RX_SERDES_DATA07; - input [63:0] RX_SERDES_DATA08; - input [63:0] RX_SERDES_DATA09; - input [63:0] RX_SERDES_DATA10; - input [63:0] RX_SERDES_DATA11; - input [11:0] RX_SERDES_RESET; - input TX_BCTLIN0; - input TX_BCTLIN1; - input TX_BCTLIN2; - input TX_BCTLIN3; - input [11:0] TX_BYPASS_CTRLIN; - input [63:0] TX_BYPASS_DATAIN00; - input [63:0] TX_BYPASS_DATAIN01; - input [63:0] TX_BYPASS_DATAIN02; - input [63:0] TX_BYPASS_DATAIN03; - input [63:0] TX_BYPASS_DATAIN04; - input [63:0] TX_BYPASS_DATAIN05; - input [63:0] TX_BYPASS_DATAIN06; - input [63:0] TX_BYPASS_DATAIN07; - input [63:0] TX_BYPASS_DATAIN08; - input [63:0] TX_BYPASS_DATAIN09; - input [63:0] TX_BYPASS_DATAIN10; - input [63:0] TX_BYPASS_DATAIN11; - input TX_BYPASS_ENAIN; - input [7:0] TX_BYPASS_GEARBOX_SEQIN; - input [3:0] TX_BYPASS_MFRAMER_STATEIN; - input [10:0] TX_CHANIN0; - input [10:0] TX_CHANIN1; - input [10:0] TX_CHANIN2; - input [10:0] TX_CHANIN3; - input [127:0] TX_DATAIN0; - input [127:0] TX_DATAIN1; - input [127:0] TX_DATAIN2; - input [127:0] TX_DATAIN3; - input TX_ENAIN0; - input TX_ENAIN1; - input TX_ENAIN2; - input TX_ENAIN3; - input TX_EOPIN0; - input TX_EOPIN1; - input TX_EOPIN2; - input TX_EOPIN3; - input TX_ERRIN0; - input TX_ERRIN1; - input TX_ERRIN2; - input TX_ERRIN3; - input [3:0] TX_MTYIN0; - input [3:0] TX_MTYIN1; - input [3:0] TX_MTYIN2; - input [3:0] TX_MTYIN3; - input TX_RESET; - input TX_SERDES_REFCLK; - input TX_SERDES_REFCLK_RESET; - input TX_SOPIN0; - input TX_SOPIN1; - input TX_SOPIN2; - input TX_SOPIN3; -endmodule - -module ILKNE4 (...); - parameter BYPASS = "FALSE"; - parameter [1:0] CTL_RX_BURSTMAX = 2'h3; - parameter [1:0] CTL_RX_CHAN_EXT = 2'h0; - parameter [3:0] CTL_RX_LAST_LANE = 4'hB; - parameter [15:0] CTL_RX_MFRAMELEN_MINUS1 = 16'h07FF; - parameter CTL_RX_PACKET_MODE = "FALSE"; - parameter [2:0] CTL_RX_RETRANS_MULT = 3'h0; - parameter [3:0] CTL_RX_RETRANS_RETRY = 4'h2; - parameter [15:0] CTL_RX_RETRANS_TIMER1 = 16'h0009; - parameter [15:0] CTL_RX_RETRANS_TIMER2 = 16'h0000; - parameter [11:0] CTL_RX_RETRANS_WDOG = 12'h000; - parameter [7:0] CTL_RX_RETRANS_WRAP_TIMER = 8'h00; - parameter CTL_TEST_MODE_PIN_CHAR = "FALSE"; - parameter [1:0] CTL_TX_BURSTMAX = 2'h3; - parameter [2:0] CTL_TX_BURSTSHORT = 3'h1; - parameter [1:0] CTL_TX_CHAN_EXT = 2'h0; - parameter CTL_TX_DISABLE_SKIPWORD = "FALSE"; - parameter [3:0] CTL_TX_FC_CALLEN = 4'hF; - parameter [3:0] CTL_TX_LAST_LANE = 4'hB; - parameter [15:0] CTL_TX_MFRAMELEN_MINUS1 = 16'h07FF; - parameter [13:0] CTL_TX_RETRANS_DEPTH = 14'h0800; - parameter [2:0] CTL_TX_RETRANS_MULT = 3'h0; - parameter [1:0] CTL_TX_RETRANS_RAM_BANKS = 2'h3; - parameter MODE = "TRUE"; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter TEST_MODE_PIN_CHAR = "FALSE"; - output [15:0] DRP_DO; - output DRP_RDY; - output [65:0] RX_BYPASS_DATAOUT00; - output [65:0] RX_BYPASS_DATAOUT01; - output [65:0] RX_BYPASS_DATAOUT02; - output [65:0] RX_BYPASS_DATAOUT03; - output [65:0] RX_BYPASS_DATAOUT04; - output [65:0] RX_BYPASS_DATAOUT05; - output [65:0] RX_BYPASS_DATAOUT06; - output [65:0] RX_BYPASS_DATAOUT07; - output [65:0] RX_BYPASS_DATAOUT08; - output [65:0] RX_BYPASS_DATAOUT09; - output [65:0] RX_BYPASS_DATAOUT10; - output [65:0] RX_BYPASS_DATAOUT11; - output [11:0] RX_BYPASS_ENAOUT; - output [11:0] RX_BYPASS_IS_AVAILOUT; - output [11:0] RX_BYPASS_IS_BADLYFRAMEDOUT; - output [11:0] RX_BYPASS_IS_OVERFLOWOUT; - output [11:0] RX_BYPASS_IS_SYNCEDOUT; - output [11:0] RX_BYPASS_IS_SYNCWORDOUT; - output [10:0] RX_CHANOUT0; - output [10:0] RX_CHANOUT1; - output [10:0] RX_CHANOUT2; - output [10:0] RX_CHANOUT3; - output [127:0] RX_DATAOUT0; - output [127:0] RX_DATAOUT1; - output [127:0] RX_DATAOUT2; - output [127:0] RX_DATAOUT3; - output RX_ENAOUT0; - output RX_ENAOUT1; - output RX_ENAOUT2; - output RX_ENAOUT3; - output RX_EOPOUT0; - output RX_EOPOUT1; - output RX_EOPOUT2; - output RX_EOPOUT3; - output RX_ERROUT0; - output RX_ERROUT1; - output RX_ERROUT2; - output RX_ERROUT3; - output [3:0] RX_MTYOUT0; - output [3:0] RX_MTYOUT1; - output [3:0] RX_MTYOUT2; - output [3:0] RX_MTYOUT3; - output RX_OVFOUT; - output RX_SOPOUT0; - output RX_SOPOUT1; - output RX_SOPOUT2; - output RX_SOPOUT3; - output STAT_RX_ALIGNED; - output STAT_RX_ALIGNED_ERR; - output [11:0] STAT_RX_BAD_TYPE_ERR; - output STAT_RX_BURSTMAX_ERR; - output STAT_RX_BURST_ERR; - output STAT_RX_CRC24_ERR; - output [11:0] STAT_RX_CRC32_ERR; - output [11:0] STAT_RX_CRC32_VALID; - output [11:0] STAT_RX_DESCRAM_ERR; - output [11:0] STAT_RX_DIAGWORD_INTFSTAT; - output [11:0] STAT_RX_DIAGWORD_LANESTAT; - output [255:0] STAT_RX_FC_STAT; - output [11:0] STAT_RX_FRAMING_ERR; - output STAT_RX_MEOP_ERR; - output [11:0] STAT_RX_MF_ERR; - output [11:0] STAT_RX_MF_LEN_ERR; - output [11:0] STAT_RX_MF_REPEAT_ERR; - output STAT_RX_MISALIGNED; - output STAT_RX_MSOP_ERR; - output [7:0] STAT_RX_MUBITS; - output STAT_RX_MUBITS_UPDATED; - output STAT_RX_OVERFLOW_ERR; - output STAT_RX_RETRANS_CRC24_ERR; - output STAT_RX_RETRANS_DISC; - output [15:0] STAT_RX_RETRANS_LATENCY; - output STAT_RX_RETRANS_REQ; - output STAT_RX_RETRANS_RETRY_ERR; - output [7:0] STAT_RX_RETRANS_SEQ; - output STAT_RX_RETRANS_SEQ_UPDATED; - output [2:0] STAT_RX_RETRANS_STATE; - output [4:0] STAT_RX_RETRANS_SUBSEQ; - output STAT_RX_RETRANS_WDOG_ERR; - output STAT_RX_RETRANS_WRAP_ERR; - output [11:0] STAT_RX_SYNCED; - output [11:0] STAT_RX_SYNCED_ERR; - output [11:0] STAT_RX_WORD_SYNC; - output STAT_TX_BURST_ERR; - output STAT_TX_ERRINJ_BITERR_DONE; - output STAT_TX_OVERFLOW_ERR; - output STAT_TX_RETRANS_BURST_ERR; - output STAT_TX_RETRANS_BUSY; - output STAT_TX_RETRANS_RAM_PERROUT; - output [8:0] STAT_TX_RETRANS_RAM_RADDR; - output STAT_TX_RETRANS_RAM_RD_B0; - output STAT_TX_RETRANS_RAM_RD_B1; - output STAT_TX_RETRANS_RAM_RD_B2; - output STAT_TX_RETRANS_RAM_RD_B3; - output [1:0] STAT_TX_RETRANS_RAM_RSEL; - output [8:0] STAT_TX_RETRANS_RAM_WADDR; - output [643:0] STAT_TX_RETRANS_RAM_WDATA; - output STAT_TX_RETRANS_RAM_WE_B0; - output STAT_TX_RETRANS_RAM_WE_B1; - output STAT_TX_RETRANS_RAM_WE_B2; - output STAT_TX_RETRANS_RAM_WE_B3; - output STAT_TX_UNDERFLOW_ERR; - output TX_OVFOUT; - output TX_RDYOUT; - output [63:0] TX_SERDES_DATA00; - output [63:0] TX_SERDES_DATA01; - output [63:0] TX_SERDES_DATA02; - output [63:0] TX_SERDES_DATA03; - output [63:0] TX_SERDES_DATA04; - output [63:0] TX_SERDES_DATA05; - output [63:0] TX_SERDES_DATA06; - output [63:0] TX_SERDES_DATA07; - output [63:0] TX_SERDES_DATA08; - output [63:0] TX_SERDES_DATA09; - output [63:0] TX_SERDES_DATA10; - output [63:0] TX_SERDES_DATA11; - input CORE_CLK; - input CTL_RX_FORCE_RESYNC; - input CTL_RX_RETRANS_ACK; - input CTL_RX_RETRANS_ENABLE; - input CTL_RX_RETRANS_ERRIN; - input CTL_RX_RETRANS_FORCE_REQ; - input CTL_RX_RETRANS_RESET; - input CTL_RX_RETRANS_RESET_MODE; - input CTL_TX_DIAGWORD_INTFSTAT; - input [11:0] CTL_TX_DIAGWORD_LANESTAT; - input CTL_TX_ENABLE; - input CTL_TX_ERRINJ_BITERR_GO; - input [3:0] CTL_TX_ERRINJ_BITERR_LANE; - input [255:0] CTL_TX_FC_STAT; - input [7:0] CTL_TX_MUBITS; - input CTL_TX_RETRANS_ENABLE; - input CTL_TX_RETRANS_RAM_PERRIN; - input [643:0] CTL_TX_RETRANS_RAM_RDATA; - input CTL_TX_RETRANS_REQ; - input CTL_TX_RETRANS_REQ_VALID; - input [11:0] CTL_TX_RLIM_DELTA; - input CTL_TX_RLIM_ENABLE; - input [7:0] CTL_TX_RLIM_INTV; - input [11:0] CTL_TX_RLIM_MAX; - input [9:0] DRP_ADDR; - input DRP_CLK; - input [15:0] DRP_DI; - input DRP_EN; - input DRP_WE; - input LBUS_CLK; - input RX_BYPASS_FORCE_REALIGNIN; - input RX_BYPASS_RDIN; - input RX_RESET; - input [11:0] RX_SERDES_CLK; - input [63:0] RX_SERDES_DATA00; - input [63:0] RX_SERDES_DATA01; - input [63:0] RX_SERDES_DATA02; - input [63:0] RX_SERDES_DATA03; - input [63:0] RX_SERDES_DATA04; - input [63:0] RX_SERDES_DATA05; - input [63:0] RX_SERDES_DATA06; - input [63:0] RX_SERDES_DATA07; - input [63:0] RX_SERDES_DATA08; - input [63:0] RX_SERDES_DATA09; - input [63:0] RX_SERDES_DATA10; - input [63:0] RX_SERDES_DATA11; - input [11:0] RX_SERDES_RESET; - input TX_BCTLIN0; - input TX_BCTLIN1; - input TX_BCTLIN2; - input TX_BCTLIN3; - input [11:0] TX_BYPASS_CTRLIN; - input [63:0] TX_BYPASS_DATAIN00; - input [63:0] TX_BYPASS_DATAIN01; - input [63:0] TX_BYPASS_DATAIN02; - input [63:0] TX_BYPASS_DATAIN03; - input [63:0] TX_BYPASS_DATAIN04; - input [63:0] TX_BYPASS_DATAIN05; - input [63:0] TX_BYPASS_DATAIN06; - input [63:0] TX_BYPASS_DATAIN07; - input [63:0] TX_BYPASS_DATAIN08; - input [63:0] TX_BYPASS_DATAIN09; - input [63:0] TX_BYPASS_DATAIN10; - input [63:0] TX_BYPASS_DATAIN11; - input TX_BYPASS_ENAIN; - input [7:0] TX_BYPASS_GEARBOX_SEQIN; - input [3:0] TX_BYPASS_MFRAMER_STATEIN; - input [10:0] TX_CHANIN0; - input [10:0] TX_CHANIN1; - input [10:0] TX_CHANIN2; - input [10:0] TX_CHANIN3; - input [127:0] TX_DATAIN0; - input [127:0] TX_DATAIN1; - input [127:0] TX_DATAIN2; - input [127:0] TX_DATAIN3; - input TX_ENAIN0; - input TX_ENAIN1; - input TX_ENAIN2; - input TX_ENAIN3; - input TX_EOPIN0; - input TX_EOPIN1; - input TX_EOPIN2; - input TX_EOPIN3; - input TX_ERRIN0; - input TX_ERRIN1; - input TX_ERRIN2; - input TX_ERRIN3; - input [3:0] TX_MTYIN0; - input [3:0] TX_MTYIN1; - input [3:0] TX_MTYIN2; - input [3:0] TX_MTYIN3; - input TX_RESET; - input TX_SERDES_REFCLK; - input TX_SERDES_REFCLK_RESET; - input TX_SOPIN0; - input TX_SOPIN1; - input TX_SOPIN2; - input TX_SOPIN3; -endmodule - -(* keep *) -module VCU (...); - parameter integer CORECLKREQ = 667; - parameter integer DECHORRESOLUTION = 3840; - parameter DECODERCHROMAFORMAT = "4_2_2"; - parameter DECODERCODING = "H.265"; - parameter integer DECODERCOLORDEPTH = 10; - parameter integer DECODERNUMCORES = 2; - parameter integer DECVERTRESOLUTION = 2160; - parameter ENABLEDECODER = "TRUE"; - parameter ENABLEENCODER = "TRUE"; - parameter integer ENCHORRESOLUTION = 3840; - parameter ENCODERCHROMAFORMAT = "4_2_2"; - parameter ENCODERCODING = "H.265"; - parameter integer ENCODERCOLORDEPTH = 10; - parameter integer ENCODERNUMCORES = 4; - parameter integer ENCVERTRESOLUTION = 2160; - output VCUPLARREADYAXILITEAPB; - output VCUPLAWREADYAXILITEAPB; - output [1:0] VCUPLBRESPAXILITEAPB; - output VCUPLBVALIDAXILITEAPB; - output VCUPLCORESTATUSCLKPLL; - output [43:0] VCUPLDECARADDR0; - output [43:0] VCUPLDECARADDR1; - output [1:0] VCUPLDECARBURST0; - output [1:0] VCUPLDECARBURST1; - output [3:0] VCUPLDECARCACHE0; - output [3:0] VCUPLDECARCACHE1; - output [3:0] VCUPLDECARID0; - output [3:0] VCUPLDECARID1; - output [7:0] VCUPLDECARLEN0; - output [7:0] VCUPLDECARLEN1; - output VCUPLDECARPROT0; - output VCUPLDECARPROT1; - output [3:0] VCUPLDECARQOS0; - output [3:0] VCUPLDECARQOS1; - output [2:0] VCUPLDECARSIZE0; - output [2:0] VCUPLDECARSIZE1; - output VCUPLDECARVALID0; - output VCUPLDECARVALID1; - output [43:0] VCUPLDECAWADDR0; - output [43:0] VCUPLDECAWADDR1; - output [1:0] VCUPLDECAWBURST0; - output [1:0] VCUPLDECAWBURST1; - output [3:0] VCUPLDECAWCACHE0; - output [3:0] VCUPLDECAWCACHE1; - output [3:0] VCUPLDECAWID0; - output [3:0] VCUPLDECAWID1; - output [7:0] VCUPLDECAWLEN0; - output [7:0] VCUPLDECAWLEN1; - output VCUPLDECAWPROT0; - output VCUPLDECAWPROT1; - output [3:0] VCUPLDECAWQOS0; - output [3:0] VCUPLDECAWQOS1; - output [2:0] VCUPLDECAWSIZE0; - output [2:0] VCUPLDECAWSIZE1; - output VCUPLDECAWVALID0; - output VCUPLDECAWVALID1; - output VCUPLDECBREADY0; - output VCUPLDECBREADY1; - output VCUPLDECRREADY0; - output VCUPLDECRREADY1; - output [127:0] VCUPLDECWDATA0; - output [127:0] VCUPLDECWDATA1; - output VCUPLDECWLAST0; - output VCUPLDECWLAST1; - output VCUPLDECWVALID0; - output VCUPLDECWVALID1; - output [16:0] VCUPLENCALL2CADDR; - output VCUPLENCALL2CRVALID; - output [319:0] VCUPLENCALL2CWDATA; - output VCUPLENCALL2CWVALID; - output [43:0] VCUPLENCARADDR0; - output [43:0] VCUPLENCARADDR1; - output [1:0] VCUPLENCARBURST0; - output [1:0] VCUPLENCARBURST1; - output [3:0] VCUPLENCARCACHE0; - output [3:0] VCUPLENCARCACHE1; - output [3:0] VCUPLENCARID0; - output [3:0] VCUPLENCARID1; - output [7:0] VCUPLENCARLEN0; - output [7:0] VCUPLENCARLEN1; - output VCUPLENCARPROT0; - output VCUPLENCARPROT1; - output [3:0] VCUPLENCARQOS0; - output [3:0] VCUPLENCARQOS1; - output [2:0] VCUPLENCARSIZE0; - output [2:0] VCUPLENCARSIZE1; - output VCUPLENCARVALID0; - output VCUPLENCARVALID1; - output [43:0] VCUPLENCAWADDR0; - output [43:0] VCUPLENCAWADDR1; - output [1:0] VCUPLENCAWBURST0; - output [1:0] VCUPLENCAWBURST1; - output [3:0] VCUPLENCAWCACHE0; - output [3:0] VCUPLENCAWCACHE1; - output [3:0] VCUPLENCAWID0; - output [3:0] VCUPLENCAWID1; - output [7:0] VCUPLENCAWLEN0; - output [7:0] VCUPLENCAWLEN1; - output VCUPLENCAWPROT0; - output VCUPLENCAWPROT1; - output [3:0] VCUPLENCAWQOS0; - output [3:0] VCUPLENCAWQOS1; - output [2:0] VCUPLENCAWSIZE0; - output [2:0] VCUPLENCAWSIZE1; - output VCUPLENCAWVALID0; - output VCUPLENCAWVALID1; - output VCUPLENCBREADY0; - output VCUPLENCBREADY1; - output VCUPLENCRREADY0; - output VCUPLENCRREADY1; - output [127:0] VCUPLENCWDATA0; - output [127:0] VCUPLENCWDATA1; - output VCUPLENCWLAST0; - output VCUPLENCWLAST1; - output VCUPLENCWVALID0; - output VCUPLENCWVALID1; - output [43:0] VCUPLMCUMAXIICDCARADDR; - output [1:0] VCUPLMCUMAXIICDCARBURST; - output [3:0] VCUPLMCUMAXIICDCARCACHE; - output [2:0] VCUPLMCUMAXIICDCARID; - output [7:0] VCUPLMCUMAXIICDCARLEN; - output VCUPLMCUMAXIICDCARLOCK; - output [2:0] VCUPLMCUMAXIICDCARPROT; - output [3:0] VCUPLMCUMAXIICDCARQOS; - output [2:0] VCUPLMCUMAXIICDCARSIZE; - output VCUPLMCUMAXIICDCARVALID; - output [43:0] VCUPLMCUMAXIICDCAWADDR; - output [1:0] VCUPLMCUMAXIICDCAWBURST; - output [3:0] VCUPLMCUMAXIICDCAWCACHE; - output [2:0] VCUPLMCUMAXIICDCAWID; - output [7:0] VCUPLMCUMAXIICDCAWLEN; - output VCUPLMCUMAXIICDCAWLOCK; - output [2:0] VCUPLMCUMAXIICDCAWPROT; - output [3:0] VCUPLMCUMAXIICDCAWQOS; - output [2:0] VCUPLMCUMAXIICDCAWSIZE; - output VCUPLMCUMAXIICDCAWVALID; - output VCUPLMCUMAXIICDCBREADY; - output VCUPLMCUMAXIICDCRREADY; - output [31:0] VCUPLMCUMAXIICDCWDATA; - output VCUPLMCUMAXIICDCWLAST; - output [3:0] VCUPLMCUMAXIICDCWSTRB; - output VCUPLMCUMAXIICDCWVALID; - output VCUPLMCUSTATUSCLKPLL; - output VCUPLPINTREQ; - output VCUPLPLLSTATUSPLLLOCK; - output VCUPLPWRSUPPLYSTATUSVCCAUX; - output VCUPLPWRSUPPLYSTATUSVCUINT; - output [31:0] VCUPLRDATAAXILITEAPB; - output [1:0] VCUPLRRESPAXILITEAPB; - output VCUPLRVALIDAXILITEAPB; - output VCUPLWREADYAXILITEAPB; - input INITPLVCUGASKETCLAMPCONTROLLVLSHVCCINTD; - input [19:0] PLVCUARADDRAXILITEAPB; - input [2:0] PLVCUARPROTAXILITEAPB; - input PLVCUARVALIDAXILITEAPB; - input [19:0] PLVCUAWADDRAXILITEAPB; - input [2:0] PLVCUAWPROTAXILITEAPB; - input PLVCUAWVALIDAXILITEAPB; - input PLVCUAXIDECCLK; - input PLVCUAXIENCCLK; - input PLVCUAXILITECLK; - input PLVCUAXIMCUCLK; - input PLVCUBREADYAXILITEAPB; - input PLVCUCORECLK; - input PLVCUDECARREADY0; - input PLVCUDECARREADY1; - input PLVCUDECAWREADY0; - input PLVCUDECAWREADY1; - input [3:0] PLVCUDECBID0; - input [3:0] PLVCUDECBID1; - input [1:0] PLVCUDECBRESP0; - input [1:0] PLVCUDECBRESP1; - input PLVCUDECBVALID0; - input PLVCUDECBVALID1; - input [127:0] PLVCUDECRDATA0; - input [127:0] PLVCUDECRDATA1; - input [3:0] PLVCUDECRID0; - input [3:0] PLVCUDECRID1; - input PLVCUDECRLAST0; - input PLVCUDECRLAST1; - input [1:0] PLVCUDECRRESP0; - input [1:0] PLVCUDECRRESP1; - input PLVCUDECRVALID0; - input PLVCUDECRVALID1; - input PLVCUDECWREADY0; - input PLVCUDECWREADY1; - input [319:0] PLVCUENCALL2CRDATA; - input PLVCUENCALL2CRREADY; - input PLVCUENCARREADY0; - input PLVCUENCARREADY1; - input PLVCUENCAWREADY0; - input PLVCUENCAWREADY1; - input [3:0] PLVCUENCBID0; - input [3:0] PLVCUENCBID1; - input [1:0] PLVCUENCBRESP0; - input [1:0] PLVCUENCBRESP1; - input PLVCUENCBVALID0; - input PLVCUENCBVALID1; - input PLVCUENCL2CCLK; - input [127:0] PLVCUENCRDATA0; - input [127:0] PLVCUENCRDATA1; - input [3:0] PLVCUENCRID0; - input [3:0] PLVCUENCRID1; - input PLVCUENCRLAST0; - input PLVCUENCRLAST1; - input [1:0] PLVCUENCRRESP0; - input [1:0] PLVCUENCRRESP1; - input PLVCUENCRVALID0; - input PLVCUENCRVALID1; - input PLVCUENCWREADY0; - input PLVCUENCWREADY1; - input PLVCUMCUCLK; - input PLVCUMCUMAXIICDCARREADY; - input PLVCUMCUMAXIICDCAWREADY; - input [2:0] PLVCUMCUMAXIICDCBID; - input [1:0] PLVCUMCUMAXIICDCBRESP; - input PLVCUMCUMAXIICDCBVALID; - input [31:0] PLVCUMCUMAXIICDCRDATA; - input [2:0] PLVCUMCUMAXIICDCRID; - input PLVCUMCUMAXIICDCRLAST; - input [1:0] PLVCUMCUMAXIICDCRRESP; - input PLVCUMCUMAXIICDCRVALID; - input PLVCUMCUMAXIICDCWREADY; - input PLVCUPLLREFCLKPL; - input PLVCURAWRSTN; - input PLVCURREADYAXILITEAPB; - input [31:0] PLVCUWDATAAXILITEAPB; - input [3:0] PLVCUWSTRBAXILITEAPB; - input PLVCUWVALIDAXILITEAPB; -endmodule - -module FE (...); - parameter MODE = "TURBO_DECODE"; - parameter real PHYSICAL_UTILIZATION = 100.00; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter STANDARD = "LTE"; - parameter real THROUGHPUT_UTILIZATION = 100.00; - output [399:0] DEBUG_DOUT; - output DEBUG_PHASE; - output INTERRUPT; - output [511:0] M_AXIS_DOUT_TDATA; - output M_AXIS_DOUT_TLAST; - output M_AXIS_DOUT_TVALID; - output [31:0] M_AXIS_STATUS_TDATA; - output M_AXIS_STATUS_TVALID; - output [15:0] SPARE_OUT; - output S_AXIS_CTRL_TREADY; - output S_AXIS_DIN_TREADY; - output S_AXIS_DIN_WORDS_TREADY; - output S_AXIS_DOUT_WORDS_TREADY; - output S_AXI_ARREADY; - output S_AXI_AWREADY; - output S_AXI_BVALID; - output [31:0] S_AXI_RDATA; - output S_AXI_RVALID; - output S_AXI_WREADY; - input CORE_CLK; - input DEBUG_CLK_EN; - input DEBUG_EN; - input [3:0] DEBUG_SEL_IN; - input M_AXIS_DOUT_ACLK; - input M_AXIS_DOUT_TREADY; - input M_AXIS_STATUS_ACLK; - input M_AXIS_STATUS_TREADY; - input RESET_N; - input [15:0] SPARE_IN; - input S_AXIS_CTRL_ACLK; - input [31:0] S_AXIS_CTRL_TDATA; - input S_AXIS_CTRL_TVALID; - input S_AXIS_DIN_ACLK; - input [511:0] S_AXIS_DIN_TDATA; - input S_AXIS_DIN_TLAST; - input S_AXIS_DIN_TVALID; - input S_AXIS_DIN_WORDS_ACLK; - input [31:0] S_AXIS_DIN_WORDS_TDATA; - input S_AXIS_DIN_WORDS_TLAST; - input S_AXIS_DIN_WORDS_TVALID; - input S_AXIS_DOUT_WORDS_ACLK; - input [31:0] S_AXIS_DOUT_WORDS_TDATA; - input S_AXIS_DOUT_WORDS_TLAST; - input S_AXIS_DOUT_WORDS_TVALID; - input S_AXI_ACLK; - input [17:0] S_AXI_ARADDR; - input S_AXI_ARVALID; - input [17:0] S_AXI_AWADDR; - input S_AXI_AWVALID; - input S_AXI_BREADY; - input S_AXI_RREADY; - input [31:0] S_AXI_WDATA; - input S_AXI_WVALID; -endmodule - diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc index 7b18ced35..21075bd97 100644 --- a/techlibs/analogdevices/synth_analogdevices.cc +++ b/techlibs/analogdevices/synth_analogdevices.cc @@ -272,7 +272,6 @@ struct SynthAnalogDevicesPass : public ScriptPass { if (check_label("begin")) { run(stringf("read_verilog -lib -specify %s +/analogdevices/cells_sim.v", tech_param)); - run("read_verilog -lib +/analogdevices/cells_xtra.v"); run(stringf("hierarchy -check %s", top_opt.c_str())); } From 39cb61615f52793eaa0fe4605455bd3c9ff24f21 Mon Sep 17 00:00:00 2001 From: Lofty Date: Thu, 16 Oct 2025 23:33:59 +0100 Subject: [PATCH 269/291] analogdevices: DSP inference --- techlibs/analogdevices/cells_sim.v | 818 ++---------------- techlibs/analogdevices/dsp_map.v | 84 +- techlibs/analogdevices/synth_analogdevices.cc | 4 +- tests/arch/analogdevices/mul.ys | 4 +- 4 files changed, 122 insertions(+), 788 deletions(-) diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v index 39a2d1025..573259472 100644 --- a/techlibs/analogdevices/cells_sim.v +++ b/techlibs/analogdevices/cells_sim.v @@ -1014,758 +1014,82 @@ endmodule // DSP -// Virtex 6, Series 7. +module RBBDSP ( + output [21:0] AO_LOC, + output [21:0] BO_LOC, + output CE_O, + output [1:0] CO_LOC, + output [47:0] DO_LOC, + output [1:0] OPCODE_O, + output [47:0] P, + output [47:0] PO_LOC, + output RST_O, -`ifdef YOSYS -(* abc9_box=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG) -`ifdef ALLOW_WHITEBOX_DSP48E1 - // Do not make DSP48E1 a whitebox for ABC9 even if fully combinatorial, since it is a big complex block - , lib_whitebox=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG || INMODEREG || OPMODEREG || ALUMODEREG || CARRYINREG || CARRYINSELREG) -`endif -*) -`endif -module DSP48E1 ( - output [29:0] ACOUT, - output [17:0] BCOUT, - output reg CARRYCASCOUT, - output reg [3:0] CARRYOUT, - output reg MULTSIGNOUT, - output OVERFLOW, - output reg signed [47:0] P, - output reg PATTERNBDETECT, - output reg PATTERNDETECT, - output [47:0] PCOUT, - output UNDERFLOW, - input signed [29:0] A, - input [29:0] ACIN, - input [3:0] ALUMODE, - input signed [17:0] B, - input [17:0] BCIN, - input [47:0] C, - input CARRYCASCIN, - input CARRYIN, - input [2:0] CARRYINSEL, - input CEA1, - input CEA2, - input CEAD, - input CEALUMODE, - input CEB1, - input CEB2, - input CEC, - input CECARRYIN, - input CECTRL, - input CED, - input CEINMODE, - input CEM, - input CEP, - (* clkbuf_sink *) input CLK, - input [24:0] D, - input [4:0] INMODE, - input MULTSIGNIN, - input [6:0] OPMODE, - input [47:0] PCIN, - input RSTA, - input RSTALLCARRYIN, - input RSTALUMODE, - input RSTB, - input RSTC, - input RSTCTRL, - input RSTD, - input RSTINMODE, - input RSTM, - input RSTP + input [1:0] CI_LOC, + input [1:0] OPCODE, + input [1:0] OPCODE_I, + input [21:0] A, + input [21:0] AI_LOC, + input [21:0] B, + input [21:0] BI_LOC, + input [47:0] D, + input [47:0] DI_LOC, + input [47:0] PI_LOC, + input CE, + input CE_I, + (* clkbuf_sink *) + input CLK, + input CHIP_RST, + input RST_I, + input RST ); - parameter integer ACASCREG = 1; - parameter integer ADREG = 1; - parameter integer ALUMODEREG = 1; - parameter integer AREG = 1; - parameter AUTORESET_PATDET = "NO_RESET"; - parameter A_INPUT = "DIRECT"; - parameter integer BCASCREG = 1; - parameter integer BREG = 1; - parameter B_INPUT = "DIRECT"; - parameter integer CARRYINREG = 1; - parameter integer CARRYINSELREG = 1; - parameter integer CREG = 1; - parameter integer DREG = 1; - parameter integer INMODEREG = 1; - parameter integer MREG = 1; - parameter integer OPMODEREG = 1; - parameter integer PREG = 1; - parameter SEL_MASK = "MASK"; - parameter SEL_PATTERN = "PATTERN"; - parameter USE_DPORT = "FALSE"; - parameter USE_MULT = "MULTIPLY"; - parameter USE_PATTERN_DETECT = "NO_PATDET"; - parameter USE_SIMD = "ONE48"; - parameter [47:0] MASK = 48'h3FFFFFFFFFFF; - parameter [47:0] PATTERN = 48'h000000000000; - parameter [3:0] IS_ALUMODE_INVERTED = 4'b0; - parameter [0:0] IS_CARRYIN_INVERTED = 1'b0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [4:0] IS_INMODE_INVERTED = 5'b0; - parameter [6:0] IS_OPMODE_INVERTED = 7'b0; -`ifdef YOSYS - function integer \A.required ; - begin - if (AREG != 0) \A.required = 254; - else if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin - if (MREG != 0) \A.required = 1416; - else if (PREG != 0) \A.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 3030 : 2739) ; - end - else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin - // Worst-case from ADREG and MREG - if (MREG != 0) \A.required = 2400; - else if (ADREG != 0) \A.required = 1283; - else if (PREG != 0) \A.required = 3723; - else if (PREG != 0) \A.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 4014 : 3723) ; - end - else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin - if (PREG != 0) \A.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1730 : 1441) ; - end - end - endfunction - function integer \B.required ; - begin - if (BREG != 0) \B.required = 324; - else if (MREG != 0) \B.required = 1285; - else if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin - if (PREG != 0) \B.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 2898 : 2608) ; - end - else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin - if (PREG != 0) \B.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 2898 : 2608) ; - end - else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin - if (PREG != 0) \B.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1718 : 1428) ; - end - end - endfunction - function integer \C.required ; - begin - if (CREG != 0) \C.required = 168; - else if (PREG != 0) \C.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1534 : 1244) ; - end - endfunction - function integer \D.required ; - begin - if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin - end - else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin - if (DREG != 0) \D.required = 248; - else if (ADREG != 0) \D.required = 1195; - else if (MREG != 0) \D.required = 2310; - else if (PREG != 0) \D.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 3925 : 3635) ; - end - else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin - end - end - endfunction - function integer \P.arrival ; - begin - if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin - if (PREG != 0) \P.arrival = 329; - // Worst-case from CREG and MREG - else if (CREG != 0) \P.arrival = 1687; - else if (MREG != 0) \P.arrival = 1671; - // Worst-case from AREG and BREG - else if (AREG != 0) \P.arrival = 2952; - else if (BREG != 0) \P.arrival = 2813; - end - else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin - if (PREG != 0) \P.arrival = 329; - // Worst-case from CREG and MREG - else if (CREG != 0) \P.arrival = 1687; - else if (MREG != 0) \P.arrival = 1671; - // Worst-case from AREG, ADREG, BREG, DREG - else if (AREG != 0) \P.arrival = 3935; - else if (DREG != 0) \P.arrival = 3908; - else if (ADREG != 0) \P.arrival = 2958; - else if (BREG != 0) \P.arrival = 2813; - end - else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin - if (PREG != 0) \P.arrival = 329; - // Worst-case from AREG, BREG, CREG - else if (CREG != 0) \P.arrival = 1687; - else if (AREG != 0) \P.arrival = 1632; - else if (BREG != 0) \P.arrival = 1616; - end - end - endfunction - function integer \PCOUT.arrival ; - begin - if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin - if (PREG != 0) \PCOUT.arrival = 435; - // Worst-case from CREG and MREG - else if (CREG != 0) \PCOUT.arrival = 1835; - else if (MREG != 0) \PCOUT.arrival = 1819; - // Worst-case from AREG and BREG - else if (AREG != 0) \PCOUT.arrival = 3098; - else if (BREG != 0) \PCOUT.arrival = 2960; - end - else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin - if (PREG != 0) \PCOUT.arrival = 435; - // Worst-case from CREG and MREG - else if (CREG != 0) \PCOUT.arrival = 1835; - else if (MREG != 0) \PCOUT.arrival = 1819; - // Worst-case from AREG, ADREG, BREG, DREG - else if (AREG != 0) \PCOUT.arrival = 4083; - else if (DREG != 0) \PCOUT.arrival = 4056; - else if (BREG != 0) \PCOUT.arrival = 2960; - else if (ADREG != 0) \PCOUT.arrival = 2859; - end - else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin - if (PREG != 0) \PCOUT.arrival = 435; - // Worst-case from AREG, BREG, CREG - else if (CREG != 0) \PCOUT.arrival = 1835; - else if (AREG != 0) \PCOUT.arrival = 1780; - else if (BREG != 0) \PCOUT.arrival = 1765; - end - end - endfunction - function integer \A.P.comb ; - begin - if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \A.P.comb = 2823; - else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.P.comb = 3806; - else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \A.P.comb = 1523; - end - endfunction - function integer \A.PCOUT.comb ; - begin - if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \A.PCOUT.comb = 2970; - else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.PCOUT.comb = 3954; - else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \A.PCOUT.comb = 1671; - end - endfunction - function integer \B.P.comb ; - begin - if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \B.P.comb = 2690; - else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.P.comb = 2690; - else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \B.P.comb = 1509; - end - endfunction - function integer \B.PCOUT.comb ; - begin - if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \B.PCOUT.comb = 2838; - else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.PCOUT.comb = 2838; - else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \B.PCOUT.comb = 1658; - end - endfunction - function integer \C.P.comb ; - begin - if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \C.P.comb = 1325; - else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.P.comb = 1325; - else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \C.P.comb = 1325; - end - endfunction - function integer \C.PCOUT.comb ; - begin - if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \C.PCOUT.comb = 1474; - else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.PCOUT.comb = 1474; - else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \C.PCOUT.comb = 1474; - end - endfunction - function integer \D.P.comb ; - begin - if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \D.P.comb = 3717; - end - endfunction - function integer \D.PCOUT.comb ; - begin - if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \D.PCOUT.comb = 3700; - end - endfunction +parameter AI_SEL_IN = 1'b0; +parameter [1:0] BC_CI = 2'b00; +parameter BI_SEL = 1'b0; +parameter BI_SEL_IN = 1'b0; +parameter CE_A = 1'b0; +parameter CE_ADD = 1'b0; +parameter CE_B = 1'b0; +parameter CE_C = 1'b0; +parameter CE_CRY = 1'b0; +parameter [1:0] CE_D = 2'b0; +parameter CE_M = 1'b0; +parameter CE_OPCODE = 1'b0; +parameter CE_PADD = 1'b0; +parameter CE_RST = 1'b1; +parameter CE_SEL = 1'b0; +parameter CE_SFT = 1'b0; +parameter [3:0] CI_SEL = 4'b0011; +parameter DI_SEL = 1'b0; +parameter DI_SEL_IN = 1'b0; +parameter OPCODE_SEL = 1'b0; +parameter [9:0] OP_ADD = 10'b0; +parameter OP_CPLX = 1'b0; +parameter [1:0] OP_MULT = 2'b11; +parameter [9:0] OP_PADD = 10'b0; +parameter [5:0] OP_SFT = 6'b0; +parameter [3:0] OP_X = 4'b1010; +parameter [3:0] OP_Y = 4'b0101; +parameter [3:0] OP_Z = 4'b0000; +parameter PO_LOC_SEL = 1'b1; +parameter PO_NWK_SEL = 1'b1; +parameter REG_A = 1'b0; +parameter REG_ADD = 1'b0; +parameter REG_B = 1'b0; +parameter REG_C = 1'b0; +parameter REG_CRY = 1'b0; +parameter [1:0] REG_D = 2'b0; +parameter REG_M = 1'b0; +parameter REG_OPCODE = 1'b0; +parameter REG_PADD = 1'b0; +parameter REG_SFT = 1'b0; +parameter RST_SEL = 1'b0; +parameter FF_SYNC_RST = 1'b0; - generate - if (PREG == 0 && MREG == 0 && AREG == 0 && ADREG == 0) - specify - (A *> P) = \A.P.comb (); - (A *> PCOUT) = \A.PCOUT.comb (); - endspecify - else - specify - $setup(A, posedge CLK &&& !IS_CLK_INVERTED, \A.required () ); - $setup(A, negedge CLK &&& IS_CLK_INVERTED, \A.required () ); - endspecify +// Much of this functionality is TODO. - if (PREG == 0 && MREG == 0 && BREG == 0) - specify - (B *> P) = \B.P.comb (); - (B *> PCOUT) = \B.PCOUT.comb (); - endspecify - else - specify - $setup(B, posedge CLK &&& !IS_CLK_INVERTED, \B.required () ); - $setup(B, negedge CLK &&& IS_CLK_INVERTED, \B.required () ); - endspecify - - if (PREG == 0 && CREG == 0) - specify - (C *> P) = \C.P.comb (); - (C *> PCOUT) = \C.PCOUT.comb (); - endspecify - else - specify - $setup(C, posedge CLK &&& !IS_CLK_INVERTED, \C.required () ); - $setup(C, negedge CLK &&& IS_CLK_INVERTED, \C.required () ); - endspecify - - if (PREG == 0 && MREG == 0 && ADREG == 0 && DREG == 0) - specify - (D *> P) = \D.P.comb (); - (D *> PCOUT) = \D.PCOUT.comb (); - endspecify - else - specify - $setup(D, posedge CLK &&& !IS_CLK_INVERTED, \D.required () ); - $setup(D, negedge CLK &&& IS_CLK_INVERTED, \D.required () ); - endspecify - - if (PREG == 0) - specify - (PCIN *> P) = 1107; - (PCIN *> PCOUT) = 1255; - endspecify - else - specify - $setup(PCIN, posedge CLK &&& !IS_CLK_INVERTED, USE_PATTERN_DETECT != "NO_PATDET" ? 1315 : 1025); - $setup(PCIN, negedge CLK &&& IS_CLK_INVERTED, USE_PATTERN_DETECT != "NO_PATDET" ? 1315 : 1025); - endspecify - - if (PREG || AREG || ADREG || BREG || CREG || DREG || MREG) - specify - if (!IS_CLK_INVERTED && CEP) (posedge CLK => (P : 48'bx)) = \P.arrival () ; - if ( IS_CLK_INVERTED && CEP) (negedge CLK => (P : 48'bx)) = \P.arrival () ; - if (!IS_CLK_INVERTED && CEP) (posedge CLK => (PCOUT : 48'bx)) = \PCOUT.arrival () ; - if ( IS_CLK_INVERTED && CEP) (negedge CLK => (PCOUT : 48'bx)) = \PCOUT.arrival () ; - endspecify - endgenerate -`endif - - initial begin -`ifndef YOSYS - if (AUTORESET_PATDET != "NO_RESET") $fatal(1, "Unsupported AUTORESET_PATDET value"); - if (SEL_MASK != "MASK") $fatal(1, "Unsupported SEL_MASK value"); - if (SEL_PATTERN != "PATTERN") $fatal(1, "Unsupported SEL_PATTERN value"); - if (USE_SIMD != "ONE48" && USE_SIMD != "TWO24" && USE_SIMD != "FOUR12") $fatal(1, "Unsupported USE_SIMD value"); - if (IS_ALUMODE_INVERTED != 4'b0) $fatal(1, "Unsupported IS_ALUMODE_INVERTED value"); - if (IS_CARRYIN_INVERTED != 1'b0) $fatal(1, "Unsupported IS_CARRYIN_INVERTED value"); - if (IS_CLK_INVERTED != 1'b0) $fatal(1, "Unsupported IS_CLK_INVERTED value"); - if (IS_INMODE_INVERTED != 5'b0) $fatal(1, "Unsupported IS_INMODE_INVERTED value"); - if (IS_OPMODE_INVERTED != 7'b0) $fatal(1, "Unsupported IS_OPMODE_INVERTED value"); -`endif - end - - wire signed [29:0] A_muxed; - wire signed [17:0] B_muxed; - - generate - if (A_INPUT == "CASCADE") assign A_muxed = ACIN; - else assign A_muxed = A; - - if (B_INPUT == "CASCADE") assign B_muxed = BCIN; - else assign B_muxed = B; - endgenerate - - reg signed [29:0] Ar1, Ar2; - reg signed [24:0] Dr; - reg signed [17:0] Br1, Br2; - reg signed [47:0] Cr; - reg [4:0] INMODEr; - reg [6:0] OPMODEr; - reg [3:0] ALUMODEr; - reg [2:0] CARRYINSELr; - - generate - // Configurable A register - if (AREG == 2) begin - initial Ar1 = 30'b0; - initial Ar2 = 30'b0; - always @(posedge CLK) - if (RSTA) begin - Ar1 <= 30'b0; - Ar2 <= 30'b0; - end else begin - if (CEA1) Ar1 <= A_muxed; - if (CEA2) Ar2 <= Ar1; - end - end else if (AREG == 1) begin - //initial Ar1 = 30'b0; - initial Ar2 = 30'b0; - always @(posedge CLK) - if (RSTA) begin - Ar1 <= 30'b0; - Ar2 <= 30'b0; - end else begin - if (CEA1) Ar1 <= A_muxed; - if (CEA2) Ar2 <= A_muxed; - end - end else begin - always @* Ar1 <= A_muxed; - always @* Ar2 <= A_muxed; - end - - // Configurable B register - if (BREG == 2) begin - initial Br1 = 25'b0; - initial Br2 = 25'b0; - always @(posedge CLK) - if (RSTB) begin - Br1 <= 18'b0; - Br2 <= 18'b0; - end else begin - if (CEB1) Br1 <= B_muxed; - if (CEB2) Br2 <= Br1; - end - end else if (BREG == 1) begin - //initial Br1 = 18'b0; - initial Br2 = 18'b0; - always @(posedge CLK) - if (RSTB) begin - Br1 <= 18'b0; - Br2 <= 18'b0; - end else begin - if (CEB1) Br1 <= B_muxed; - if (CEB2) Br2 <= B_muxed; - end - end else begin - always @* Br1 <= B_muxed; - always @* Br2 <= B_muxed; - end - - // C and D registers - if (CREG == 1) initial Cr = 48'b0; - if (CREG == 1) begin always @(posedge CLK) if (RSTC) Cr <= 48'b0; else if (CEC) Cr <= C; end - else always @* Cr <= C; - - if (DREG == 1) initial Dr = 25'b0; - if (DREG == 1) begin always @(posedge CLK) if (RSTD) Dr <= 25'b0; else if (CED) Dr <= D; end - else always @* Dr <= D; - - // Control registers - if (INMODEREG == 1) initial INMODEr = 5'b0; - if (INMODEREG == 1) begin always @(posedge CLK) if (RSTINMODE) INMODEr <= 5'b0; else if (CEINMODE) INMODEr <= INMODE; end - else always @* INMODEr <= INMODE; - if (OPMODEREG == 1) initial OPMODEr = 7'b0; - if (OPMODEREG == 1) begin always @(posedge CLK) if (RSTCTRL) OPMODEr <= 7'b0; else if (CECTRL) OPMODEr <= OPMODE; end - else always @* OPMODEr <= OPMODE; - if (ALUMODEREG == 1) initial ALUMODEr = 4'b0; - if (ALUMODEREG == 1) begin always @(posedge CLK) if (RSTALUMODE) ALUMODEr <= 4'b0; else if (CEALUMODE) ALUMODEr <= ALUMODE; end - else always @* ALUMODEr <= ALUMODE; - if (CARRYINSELREG == 1) initial CARRYINSELr = 3'b0; - if (CARRYINSELREG == 1) begin always @(posedge CLK) if (RSTCTRL) CARRYINSELr <= 3'b0; else if (CECTRL) CARRYINSELr <= CARRYINSEL; end - else always @* CARRYINSELr <= CARRYINSEL; - endgenerate - - // A and B cascade - generate - if (ACASCREG == 1 && AREG == 2) assign ACOUT = Ar1; - else assign ACOUT = Ar2; - if (BCASCREG == 1 && BREG == 2) assign BCOUT = Br1; - else assign BCOUT = Br2; - endgenerate - - // A/D input selection and pre-adder - wire signed [24:0] Ar12_muxed = INMODEr[0] ? Ar1 : Ar2; - wire signed [24:0] Ar12_gated = INMODEr[1] ? 25'b0 : Ar12_muxed; - wire signed [24:0] Dr_gated = INMODEr[2] ? Dr : 25'b0; - wire signed [24:0] AD_result = INMODEr[3] ? (Dr_gated - Ar12_gated) : (Dr_gated + Ar12_gated); - reg signed [24:0] ADr; - - generate - if (ADREG == 1) initial ADr = 25'b0; - if (ADREG == 1) begin always @(posedge CLK) if (RSTD) ADr <= 25'b0; else if (CEAD) ADr <= AD_result; end - else always @* ADr <= AD_result; - endgenerate - - // 25x18 multiplier - wire signed [24:0] A_MULT; - wire signed [17:0] B_MULT = INMODEr[4] ? Br1 : Br2; - generate - if (USE_DPORT == "TRUE") assign A_MULT = ADr; - else assign A_MULT = Ar12_gated; - endgenerate - - wire signed [42:0] M = A_MULT * B_MULT; - wire signed [42:0] Mx = (CARRYINSEL == 3'b010) ? 43'bx : M; - reg signed [42:0] Mr = 43'b0; - - // Multiplier result register - generate - if (MREG == 1) begin always @(posedge CLK) if (RSTM) Mr <= 43'b0; else if (CEM) Mr <= Mx; end - else always @* Mr <= Mx; - endgenerate - - wire signed [42:0] Mrx = (CARRYINSELr == 3'b010) ? 43'bx : Mr; - - // X, Y and Z ALU inputs - reg signed [47:0] X, Y, Z; - - always @* begin - // X multiplexer - case (OPMODEr[1:0]) - 2'b00: X = 48'b0; - 2'b01: begin X = $signed(Mrx); -`ifndef YOSYS - if (OPMODEr[3:2] != 2'b01) $fatal(1, "OPMODEr[3:2] must be 2'b01 when OPMODEr[1:0] is 2'b01"); -`endif - end - 2'b10: - if (PREG == 1) - X = P; - else begin - X = 48'bx; -`ifndef YOSYS - $fatal(1, "PREG must be 1 when OPMODEr[1:0] is 2'b10"); -`endif - end - 2'b11: X = $signed({Ar2, Br2}); - default: X = 48'bx; - endcase - - // Y multiplexer - case (OPMODEr[3:2]) - 2'b00: Y = 48'b0; - 2'b01: begin Y = 48'b0; // FIXME: more accurate partial product modelling? -`ifndef YOSYS - if (OPMODEr[1:0] != 2'b01) $fatal(1, "OPMODEr[1:0] must be 2'b01 when OPMODEr[3:2] is 2'b01"); -`endif - end - 2'b10: Y = {48{1'b1}}; - 2'b11: Y = Cr; - default: Y = 48'bx; - endcase - - // Z multiplexer - case (OPMODEr[6:4]) - 3'b000: Z = 48'b0; - 3'b001: Z = PCIN; - 3'b010: - if (PREG == 1) - Z = P; - else begin - Z = 48'bx; -`ifndef YOSYS - $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b010"); -`endif - end - 3'b011: Z = Cr; - 3'b100: - if (PREG == 1 && OPMODEr[3:0] === 4'b1000) - Z = P; - else begin - Z = 48'bx; -`ifndef YOSYS - if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b100"); - if (OPMODEr[3:0] != 4'b1000) $fatal(1, "OPMODEr[3:0] must be 4'b1000 when OPMODEr[6:4] i0s 3'b100"); -`endif - end - 3'b101: Z = $signed(PCIN[47:17]); - 3'b110: - if (PREG == 1) - Z = $signed(P[47:17]); - else begin - Z = 48'bx; -`ifndef YOSYS - $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b110"); -`endif - end - default: Z = 48'bx; - endcase - end - - // Carry in - wire A24_xnor_B17d = A_MULT[24] ~^ B_MULT[17]; - reg CARRYINr, A24_xnor_B17; - generate - if (CARRYINREG == 1) initial CARRYINr = 1'b0; - if (CARRYINREG == 1) begin always @(posedge CLK) if (RSTALLCARRYIN) CARRYINr <= 1'b0; else if (CECARRYIN) CARRYINr <= CARRYIN; end - else always @* CARRYINr = CARRYIN; - - if (MREG == 1) initial A24_xnor_B17 = 1'b0; - if (MREG == 1) begin always @(posedge CLK) if (RSTALLCARRYIN) A24_xnor_B17 <= 1'b0; else if (CEM) A24_xnor_B17 <= A24_xnor_B17d; end - else always @* A24_xnor_B17 = A24_xnor_B17d; - endgenerate - - reg cin_muxed; - - always @(*) begin - case (CARRYINSELr) - 3'b000: cin_muxed = CARRYINr; - 3'b001: cin_muxed = ~PCIN[47]; - 3'b010: cin_muxed = CARRYCASCIN; - 3'b011: cin_muxed = PCIN[47]; - 3'b100: - if (PREG == 1) - cin_muxed = CARRYCASCOUT; - else begin - cin_muxed = 1'bx; -`ifndef YOSYS - $fatal(1, "PREG must be 1 when CARRYINSEL is 3'b100"); -`endif - end - 3'b101: - if (PREG == 1) - cin_muxed = ~P[47]; - else begin - cin_muxed = 1'bx; -`ifndef YOSYS - $fatal(1, "PREG must be 1 when CARRYINSEL is 3'b101"); -`endif - end - 3'b110: cin_muxed = A24_xnor_B17; - 3'b111: - if (PREG == 1) - cin_muxed = P[47]; - else begin - cin_muxed = 1'bx; -`ifndef YOSYS - $fatal(1, "PREG must be 1 when CARRYINSEL is 3'b111"); -`endif - end - default: cin_muxed = 1'bx; - endcase - end - - wire alu_cin = (ALUMODEr[3] || ALUMODEr[2]) ? 1'b0 : cin_muxed; - - // ALU core - wire [47:0] Z_muxinv = ALUMODEr[0] ? ~Z : Z; - wire [47:0] xor_xyz = X ^ Y ^ Z_muxinv; - wire [47:0] maj_xyz = (X & Y) | (X & Z_muxinv) | (Y & Z_muxinv); - - wire [47:0] xor_xyz_muxed = ALUMODEr[3] ? maj_xyz : xor_xyz; - wire [47:0] maj_xyz_gated = ALUMODEr[2] ? 48'b0 : maj_xyz; - - wire [48:0] maj_xyz_simd_gated; - wire [3:0] int_carry_in, int_carry_out, ext_carry_out; - wire [47:0] alu_sum; - assign int_carry_in[0] = 1'b0; - wire [3:0] carryout_reset; - - generate - if (USE_SIMD == "FOUR12") begin - assign maj_xyz_simd_gated = { - maj_xyz_gated[47:36], - 1'b0, maj_xyz_gated[34:24], - 1'b0, maj_xyz_gated[22:12], - 1'b0, maj_xyz_gated[10:0], - alu_cin - }; - assign int_carry_in[3:1] = 3'b000; - assign ext_carry_out = { - int_carry_out[3], - maj_xyz_gated[35] ^ int_carry_out[2], - maj_xyz_gated[23] ^ int_carry_out[1], - maj_xyz_gated[11] ^ int_carry_out[0] - }; - assign carryout_reset = 4'b0000; - end else if (USE_SIMD == "TWO24") begin - assign maj_xyz_simd_gated = { - maj_xyz_gated[47:24], - 1'b0, maj_xyz_gated[22:0], - alu_cin - }; - assign int_carry_in[3:1] = {int_carry_out[2], 1'b0, int_carry_out[0]}; - assign ext_carry_out = { - int_carry_out[3], - 1'bx, - maj_xyz_gated[23] ^ int_carry_out[1], - 1'bx - }; - assign carryout_reset = 4'b0x0x; - end else begin - assign maj_xyz_simd_gated = {maj_xyz_gated, alu_cin}; - assign int_carry_in[3:1] = int_carry_out[2:0]; - assign ext_carry_out = { - int_carry_out[3], - 3'bxxx - }; - assign carryout_reset = 4'b0xxx; - end - - genvar i; - for (i = 0; i < 4; i = i + 1) - assign {int_carry_out[i], alu_sum[i*12 +: 12]} = {1'b0, maj_xyz_simd_gated[i*12 +: ((i == 3) ? 13 : 12)]} - + xor_xyz_muxed[i*12 +: 12] + int_carry_in[i]; - endgenerate - - wire signed [47:0] Pd = ALUMODEr[1] ? ~alu_sum : alu_sum; - wire [3:0] CARRYOUTd = (OPMODEr[3:0] == 4'b0101 || ALUMODEr[3:2] != 2'b00) ? 4'bxxxx : - ((ALUMODEr[0] & ALUMODEr[1]) ? ~ext_carry_out : ext_carry_out); - wire CARRYCASCOUTd = ext_carry_out[3]; - wire MULTSIGNOUTd = Mrx[42]; - - generate - if (PREG == 1) begin - initial P = 48'b0; - initial CARRYOUT = carryout_reset; - initial CARRYCASCOUT = 1'b0; - initial MULTSIGNOUT = 1'b0; - always @(posedge CLK) - if (RSTP) begin - P <= 48'b0; - CARRYOUT <= carryout_reset; - CARRYCASCOUT <= 1'b0; - MULTSIGNOUT <= 1'b0; - end else if (CEP) begin - P <= Pd; - CARRYOUT <= CARRYOUTd; - CARRYCASCOUT <= CARRYCASCOUTd; - MULTSIGNOUT <= MULTSIGNOUTd; - end - end else begin - always @* begin - P = Pd; - CARRYOUT = CARRYOUTd; - CARRYCASCOUT = CARRYCASCOUTd; - MULTSIGNOUT = MULTSIGNOUTd; - end - end - endgenerate - - assign PCOUT = P; - - generate - wire PATTERNDETECTd, PATTERNBDETECTd; - - if (USE_PATTERN_DETECT == "PATDET") begin - // TODO: Support SEL_PATTERN != "PATTERN" and SEL_MASK != "MASK - assign PATTERNDETECTd = &(~(Pd ^ PATTERN) | MASK); - assign PATTERNBDETECTd = &((Pd ^ PATTERN) | MASK); - end else begin - assign PATTERNDETECTd = 1'b1; - assign PATTERNBDETECTd = 1'b1; - end - - if (PREG == 1) begin - reg PATTERNDETECTPAST, PATTERNBDETECTPAST; - initial PATTERNDETECT = 1'b0; - initial PATTERNBDETECT = 1'b0; - initial PATTERNDETECTPAST = 1'b0; - initial PATTERNBDETECTPAST = 1'b0; - always @(posedge CLK) - if (RSTP) begin - PATTERNDETECT <= 1'b0; - PATTERNBDETECT <= 1'b0; - PATTERNDETECTPAST <= 1'b0; - PATTERNBDETECTPAST <= 1'b0; - end else if (CEP) begin - PATTERNDETECT <= PATTERNDETECTd; - PATTERNBDETECT <= PATTERNBDETECTd; - PATTERNDETECTPAST <= PATTERNDETECT; - PATTERNBDETECTPAST <= PATTERNBDETECT; - end - assign OVERFLOW = &{PATTERNDETECTPAST, ~PATTERNBDETECT, ~PATTERNDETECT}; - assign UNDERFLOW = &{PATTERNBDETECTPAST, ~PATTERNBDETECT, ~PATTERNDETECT}; - end else begin - always @* begin - PATTERNDETECT = PATTERNDETECTd; - PATTERNBDETECT = PATTERNBDETECTd; - end - assign OVERFLOW = 1'bx, UNDERFLOW = 1'bx; - end - endgenerate +assign P = $signed(A) * $signed(B); endmodule diff --git a/techlibs/analogdevices/dsp_map.v b/techlibs/analogdevices/dsp_map.v index 58df977ec..6f4b0822b 100644 --- a/techlibs/analogdevices/dsp_map.v +++ b/techlibs/analogdevices/dsp_map.v @@ -1,4 +1,4 @@ -module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); +module \$__MUL22X22 (input [21:0] A, input [21:0] B, output [43:0] Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 0; @@ -6,45 +6,55 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); parameter Y_WIDTH = 0; wire [47:0] P_48; - DSP48E1 #( + RBBDSP #( // Disable all registers - .ACASCREG(0), - .ADREG(0), - .A_INPUT("DIRECT"), - .ALUMODEREG(0), - .AREG(0), - .BCASCREG(0), - .B_INPUT("DIRECT"), - .BREG(0), - .CARRYINREG(0), - .CARRYINSELREG(0), - .CREG(0), - .DREG(0), - .INMODEREG(0), - .MREG(0), - .OPMODEREG(0), - .PREG(0), - .USE_MULT("MULTIPLY"), - .USE_SIMD("ONE48"), - .USE_DPORT("FALSE") + .AI_SEL_IN(1'b0), + .BC_CI(2'b00), + .BI_SEL(1'b0), + .BI_SEL_IN(1'b0), + .CE_A(1'b0), + .CE_ADD(1'b0), + .CE_B(1'b0), + .CE_C(1'b0), + .CE_CRY(1'b0), + .CE_D(2'b0), + .CE_M(1'b0), + .CE_OPCODE(1'b0), + .CE_PADD(1'b0), + .CE_RST(1'b1), + .CE_SEL(1'b0), + .CE_SFT(1'b0), + .CI_SEL(4'd3), + .DI_SEL(1'b0), + .DI_SEL_IN(1'b0), + .OPCODE_SEL(1'b0), + .OP_ADD(10'b0), + .OP_CPLX(1'b0), + .OP_MULT(2'b11), + .OP_PADD(10'b0000000000), + .OP_SFT(6'b000000), + .OP_X(4'b1010), + .OP_Y(4'b0101), + .OP_Z(4'b0000), + .PO_LOC_SEL(1'b1), + .PO_NWK_SEL(1'b1), + .REG_A(1'b0), + .REG_ADD(1'b0), + .REG_B(1'b0), + .REG_C(1'b0), + .REG_CRY(1'b0), + .REG_D(2'b0), + .REG_M(1'b0), + .REG_OPCODE(1'b0), + .REG_PADD(1'b0), + .REG_SFT(1'b0), + .RST_SEL(1'b0), + .FF_SYNC_RST(1'b0), ) _TECHMAP_REPLACE_ ( - //Data path - .A({{5{A[24]}}, A}), - .B(B), - .C(48'b0), - .D(25'b0), - .CARRYIN(1'b0), .P(P_48), - - .INMODE(5'b00000), - .ALUMODE(4'b0000), - .OPMODE(7'b000101), - .CARRYINSEL(3'b000), - - .ACIN(30'b0), - .BCIN(18'b0), - .PCIN(48'b0), - .CARRYIN(1'b0) + .A(A), + .B(B), + .D(48'b0) ); assign Y = P_48; endmodule diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc index 21075bd97..c6514d4aa 100644 --- a/techlibs/analogdevices/synth_analogdevices.cc +++ b/techlibs/analogdevices/synth_analogdevices.cc @@ -316,14 +316,14 @@ struct SynthAnalogDevicesPass : public ScriptPass // NB: Xilinx multipliers are signed only if (help_mode) run("techmap -map +/mul2dsp.v -map +/analogdevices/{family}_dsp_map.v {options}"); - run("techmap -map +/mul2dsp.v -map +/analogdevices/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 " + run("techmap -map +/mul2dsp.v -map +/analogdevices/dsp_map.v -D DSP_A_MAXWIDTH=22 -D DSP_B_MAXWIDTH=22 " "-D DSP_A_MAXWIDTH_PARTIAL=18 " // Partial multipliers are intentionally // limited to 18x18 in order to take // advantage of the (PCOUT << 17) -> PCIN // dedicated cascade chain capability "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller - "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); + "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL22X22"); run("select a:mul2dsp"); run("setattr -unset mul2dsp"); diff --git a/tests/arch/analogdevices/mul.ys b/tests/arch/analogdevices/mul.ys index d20159a12..460bfeb68 100644 --- a/tests/arch/analogdevices/mul.ys +++ b/tests/arch/analogdevices/mul.ys @@ -5,5 +5,5 @@ equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:DSP48E1 -select -assert-none t:DSP48E1 %% t:* %D +select -assert-count 1 t:RBBDSP +select -assert-none t:RBBDSP %% t:* %D From dea8c275ff4ddb3b022d2afd1c02272eacc9257b Mon Sep 17 00:00:00 2001 From: Lofty Date: Sat, 18 Oct 2025 12:10:50 +0100 Subject: [PATCH 270/291] analogdevices: DSP tweaks --- techlibs/analogdevices/cells_sim.v | 13 ++++++++++--- techlibs/analogdevices/synth_analogdevices.cc | 2 +- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v index 573259472..402c421fa 100644 --- a/techlibs/analogdevices/cells_sim.v +++ b/techlibs/analogdevices/cells_sim.v @@ -1014,6 +1014,7 @@ endmodule // DSP +(* abc9_box *) module RBBDSP ( output [21:0] AO_LOC, output [21:0] BO_LOC, @@ -1025,9 +1026,9 @@ module RBBDSP ( output [47:0] PO_LOC, output RST_O, - input [1:0] CI_LOC, - input [1:0] OPCODE, - input [1:0] OPCODE_I, + input [1:0] CI_LOC, + input [1:0] OPCODE, + input [1:0] OPCODE_I, input [21:0] A, input [21:0] AI_LOC, input [21:0] B, @@ -1087,6 +1088,12 @@ parameter REG_SFT = 1'b0; parameter RST_SEL = 1'b0; parameter FF_SYNC_RST = 1'b0; +specify + if (!REG_A) (A *> P) = 1000; + if (!REG_B) (B *> P) = 1000; + if (!REG_D[0]) (D *> P) = 1000; +endspecify + // Much of this functionality is TODO. assign P = $signed(A) * $signed(B); diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc index c6514d4aa..18619de7a 100644 --- a/techlibs/analogdevices/synth_analogdevices.cc +++ b/techlibs/analogdevices/synth_analogdevices.cc @@ -313,7 +313,7 @@ struct SynthAnalogDevicesPass : public ScriptPass if (check_label("map_dsp", "(skip if '-nodsp')")) { if (!nodsp || help_mode) { run("memory_dff"); // xilinx_dsp will merge registers, reserve memory port registers first - // NB: Xilinx multipliers are signed only + // NB: Analog Devices multipliers are signed only if (help_mode) run("techmap -map +/mul2dsp.v -map +/analogdevices/{family}_dsp_map.v {options}"); run("techmap -map +/mul2dsp.v -map +/analogdevices/dsp_map.v -D DSP_A_MAXWIDTH=22 -D DSP_B_MAXWIDTH=22 " From 8a09cc54630dbcf326acf0ecd86225d018d43eb6 Mon Sep 17 00:00:00 2001 From: Lofty Date: Sat, 18 Oct 2025 12:11:18 +0100 Subject: [PATCH 271/291] analogdevices: LUT RAM only on positive edge --- techlibs/analogdevices/lutrams.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/analogdevices/lutrams.txt b/techlibs/analogdevices/lutrams.txt index c342eaede..804b78252 100644 --- a/techlibs/analogdevices/lutrams.txt +++ b/techlibs/analogdevices/lutrams.txt @@ -13,7 +13,7 @@ ram distributed $__ANALOGDEVICES_LUTRAM_SP_ { init no_undef; prune_rom; port arsw "RW" { - clock anyedge; + clock posedge; } } From 95ef0cd788d8e5155895d18ab6f5090fde67039b Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Sat, 18 Oct 2025 12:59:55 +1300 Subject: [PATCH 272/291] analogdevices: Add BRAM options Enable `-force-params`, and tidy up lutram mapping too. --- techlibs/analogdevices/brams.txt | 226 ++++++++++--- techlibs/analogdevices/brams_map.v | 296 +++++++++++++----- techlibs/analogdevices/lutrams.txt | 41 +-- techlibs/analogdevices/lutrams_map.v | 207 ++++++------ techlibs/analogdevices/synth_analogdevices.cc | 3 +- 5 files changed, 527 insertions(+), 246 deletions(-) diff --git a/techlibs/analogdevices/brams.txt b/techlibs/analogdevices/brams.txt index 9a5111490..f5c45aacf 100644 --- a/techlibs/analogdevices/brams.txt +++ b/techlibs/analogdevices/brams.txt @@ -1,56 +1,188 @@ -# family: T16FFC T40LP -# BRAM: RBRAM2 RBRAM -# Supported: SDP_8192x05 SDP_4096x05 -# SDP_4096x10 SDP_2048x10 -# SDP_2048x40 SDP_1024x40 -# Ignored: SDP_4096x09 SDP_2048x09 -# Unimplemented: SP_2048x20 SP_1024x20 -# TDP_4096x09 -# TDP_8192x05 -# TDP_2048x40 -# SP2_2048x09 SP2_1024x09 -# SP2_4096x05 SP2_2048x05 +ifdef IS_T16FFC { + ram block $__ANALOGDEVICES_BLOCKRAM_FULL_ { + option "ERR" "ECC" { + style "ECC"; + option "SIZE" "2048x32" { + abits 11; + width 32; + byte 32; + option "MODE" "TDP" cost 2501; + option "MODE" "SDP" cost 2401; + } + } + option "ERR" "BP" { + style "BP"; + option "SIZE" "2048x36" { + abits 11; + width 36; + byte 9; + option "MODE" "TDP" cost 2504; + option "MODE" "SDP" cost 2404; + } + } + option "ERR" "NONE" { + option "SIZE" "8192x05" { + abits 13; + width 5; + byte 1; + option "MODE" "TDP" cost 2505; + option "MODE" "SDP" cost 2405; + } + option "SIZE" "4096x09" { + abits 12; + width 9; + byte 1; + option "MODE" "TDP" cost 2509; + option "MODE" "SDP" cost 2409; + } + option "SIZE" "4096x10" { + abits 12; + width 10; + byte 1; + option "MODE" "TDP" forbid; + option "MODE" "SDP" cost 2410; + } + option "SIZE" "2048x40" { + abits 11; + width 40; + byte 8; + option "MODE" "TDP" cost 2505; + option "MODE" "SDP" cost 2405; + } + } + # supports any initialization value, but need to export memory files + init any; -# Simple Dual Port - -ram block $__ANALOGDEVICES_BLOCKRAM_SDP_ { - option "ENABLE_WIDTH" "BIT" { - ifdef IS_T40LP { - abits 12; + option "MODE" "TDP" { + port srsw "A" { + clock anyedge; + clken; + rdwr no_change; + } + port srsw "B" { + clock anyedge; + clken; + rdwr no_change; + } } - ifdef IS_T16FFC { - abits 13; + option "MODE" "SDP" { + port sw "A" { + clock anyedge; + clken; + } + port sr "B" { + clock anyedge; + clken; + } } - widths 5 10 global; - byte 1; - cost 1; - } - option "ENABLE_WIDTH" "BYTE" { - ifdef IS_T40LP { - abits 10; - } - ifdef IS_T16FFC { - abits 11; - } - width 40; - byte 8; - cost 4; - } - # Unclear if/how RBRAM is initialized, default SIM_INIT_BEHAVIOUR is UNINITIALIZED - init none; - port sr "R" { - clock anyedge; - clken; - } - port sw "W" { - clock anyedge; - clken; } } -# Single Port +ram block $__ANALOGDEVICES_BLOCKRAM_HALF_ { + option "ERR" "ECC" { + style "ECC"; + option "SIZE" "1024x32" { + abits 10; + width 32; + byte 32; + option "MODE" "SDP" cost 2401; + option "MODE" "SP" cost 2301; + } + } + option "ERR" "BP" { + style "BP"; + option "SIZE" "1024x36" { + abits 10; + width 36; + byte 9; + option "MODE" "SDP" cost 2404; + option "MODE" "SP" cost 2304; + } + } + option "ERR" "NONE" { + option "SIZE" "4096x05" { + abits 12; + width 5; + byte 1; + option "MODE" "SDP" cost 2405; + option "MODE" "SP" cost 2305; + } + option "SIZE" "2048x09" { + abits 11; + width 9; + byte 1; + option "MODE" "SDP" cost 2409; + option "MODE" "SP" cost 2309; + } + option "SIZE" "2048x10" { + abits 11; + width 10; + byte 1; + option "MODE" "SDP" cost 2410; + option "MODE" "SP" cost 2310; + } + option "SIZE" "1024x40" { + abits 10; + width 40; + byte 8; + option "MODE" "SDP" cost 2405; + option "MODE" "SP" cost 2305; + } + } -# True Dual Port + option "MODE" "SDP" { + ifdef IS_T16FFC forbid; + port sw "A" { + clock anyedge; + clken; + } + port sr "B" { + clock anyedge; + clken; + } + } + option "MODE" "SP" { + ifdef IS_T40LP forbid; + port srsw "A" { + clock anyedge; + clken; + rdwr no_change; + } + } +} -# Dual Single Port +ifdef IS_T40LP { + ram block $__ANALOGDEVICES_BLOCKRAM_QUARTER_ { + option "ERR" "BP" { + style "BP"; + option "SIZE" "512x18" { + abits 9; + width 18; + byte 9; + option "MODE" "SP" cost 2202; + } + } + option "ERR" "NONE" { + option "SIZE" "2048x05" { + abits 11; + width 5; + byte 1; + option "MODE" "SP" cost 2205; + } + option "SIZE" "1024x09" { + abits 10; + width 9; + byte 1; + option "MODE" "SP" cost 2209; + } + } + option "MODE" "SP" { + port srsw "A" { + clock anyedge; + clken; + rdwr no_change; + } + } + } +} diff --git a/techlibs/analogdevices/brams_map.v b/techlibs/analogdevices/brams_map.v index b2ba6b77d..c486670e3 100644 --- a/techlibs/analogdevices/brams_map.v +++ b/techlibs/analogdevices/brams_map.v @@ -1,78 +1,234 @@ -module $__ANALOGDEVICES_BLOCKRAM_SDP_ (...); +module $__ANALOGDEVICES_BLOCKRAM_FULL_ (...); + // libmap params + parameter INIT = 0; + parameter OPTION_MODE = "NONE"; + parameter OPTION_SIZE = "NONE"; + parameter OPTION_ERR = "NONE"; + parameter PORT_A_WR_EN_WIDTH = 1; + parameter PORT_A_CLK_POL = 1; + parameter PORT_B_WR_EN_WIDTH = 1; + parameter PORT_B_CLK_POL = 1; -parameter INIT = 0; -parameter OPTION_ENABLE_WIDTH = "BIT"; -parameter WIDTH = 40; + // needs -force-params + parameter WIDTH = 40; + parameter ABITS = 13; + // non libmap params `ifdef IS_T40LP -parameter ABITS = 12; -localparam NODE = "T40LP_Gen2.4"; -localparam BRAM_MODE = WIDTH == 5 ? "SDP_4096x05" : - WIDTH == 10 ? "SDP_2048x10" : "SDP_1024x40"; -`elsif IS_T16FFC -parameter ABITS = 13; -localparam NODE = "T16FFC_Gen2.4"; -localparam BRAM_MODE = WIDTH == 5 ? "SDP_8192x05" : - WIDTH == 10 ? "SDP_4096x10" : "SDP_2048x40"; -`endif - -parameter PORT_W_WR_EN_WIDTH = 5; -parameter PORT_W_CLK_POL = 1; - -parameter PORT_R_CLK_POL = 1; - -input PORT_W_CLK; -input PORT_W_CLK_EN; -input [ABITS-1:0] PORT_W_ADDR; -input [WIDTH-1:0] PORT_W_WR_DATA; -input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN; - -input PORT_R_CLK; -input PORT_R_CLK_EN; -input [ABITS-1:0] PORT_R_ADDR; -output [WIDTH-1:0] PORT_R_RD_DATA; - -`ifdef IS_T40LP -RBRAM + localparam NODE = "T40LP_Gen2.4"; `endif `ifdef IS_T16FFC -RBRAM2 + localparam NODE = "T16FFC_Gen2.4"; `endif -#( - .TARGET_NODE(NODE), - .BRAM_MODE(BRAM_MODE), - .QA_REG(0), - .QB_REG(0), - .CLKA_INV(!PORT_W_CLK_POL), - .CLKB_INV(!PORT_R_CLK_POL), - .DATA_WIDTH(WIDTH), - .ADDR_WIDTH( - WIDTH == 5 ? ABITS : - WIDTH == 10 ? ABITS-1 : ABITS-2 - ), - .WE_WIDTH(OPTION_ENABLE_WIDTH == "BIT" ? WIDTH : PORT_W_WR_EN_WIDTH), - .PERR_WIDTH(1), -) -_TECHMAP_REPLACE_ -( - // .QA(0), - .DA(PORT_W_WR_DATA), - .CEA(PORT_W_CLK_EN), - .WEA(PORT_W_WR_EN), - .AA( - WIDTH == 5 ? PORT_W_ADDR : - WIDTH == 10 ? PORT_W_ADDR[ABITS-1:1] : PORT_W_ADDR[ABITS-1:2] - ), - .CLKA(PORT_W_CLK), - .QB(PORT_R_RD_DATA), - // .DB(0), - .CEB(PORT_R_CLK_EN), - // .WEB(0), - .AB( - WIDTH == 5 ? PORT_R_ADDR : - WIDTH == 10 ? PORT_R_ADDR[ABITS-1:1] : PORT_R_ADDR[ABITS-1:2] - ), - .CLKB(PORT_R_CLK), -); + // localparam BRAM_MODE = "SDP_2048x36_BP"; + localparam BRAM_MODE = (OPTION_ERR!="NONE") ? {OPTION_MODE, "_", OPTION_SIZE, "_", OPTION_ERR} : + {OPTION_MODE, "_", OPTION_SIZE}; + localparam PBITS = (OPTION_ERR=="FP") ? 1 : + (OPTION_ERR=="BP") ? PORT_A_WR_EN_WIDTH : + 0; + + // libmap ports + input PORT_A_CLK; + input PORT_A_CLK_EN; + input [ABITS-1:0] PORT_A_ADDR; + input [WIDTH-1:0] PORT_A_WR_DATA; + output [WIDTH-1:0] PORT_A_RD_DATA; + input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN; + + input PORT_B_CLK; + input PORT_B_CLK_EN; + input [ABITS-1:0] PORT_B_ADDR; + input [WIDTH-1:0] PORT_B_WR_DATA; + output [WIDTH-1:0] PORT_B_RD_DATA; + input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN; + +`ifdef IS_T40LP + RBRAM +`endif +`ifdef IS_T16FFC + RBRAM2 +`endif + #( + .TARGET_NODE(NODE), + .BRAM_MODE(BRAM_MODE), + .QA_REG(0), + .QB_REG(0), + .CLKA_INV(!PORT_A_CLK_POL), + .CLKB_INV(!PORT_B_CLK_POL), + .DATA_WIDTH(WIDTH), + .ADDR_WIDTH(ABITS), + .WE_WIDTH(PORT_A_WR_EN_WIDTH), + .PERR_WIDTH(PBITS), + ) + _TECHMAP_REPLACE_ + ( + .QA(PORT_A_RD_DATA), + .DA(PORT_A_WR_DATA), + .CEA(PORT_A_CLK_EN), + .WEA(PORT_A_WR_EN), + .AA(PORT_A_ADDR), + .CLKA(PORT_A_CLK), + .QB(PORT_B_RD_DATA), + .DB(PORT_B_WR_DATA), + .CEB(PORT_B_CLK_EN), + .WEB(PORT_B_WR_EN), + .AB(PORT_B_ADDR), + .CLKB(PORT_B_CLK), + ); + + // check config + generate + case (BRAM_MODE) + `ifdef IS_T40LP + "SDP_1024x18_FP", + "SDP_1024x16_BP", + "SDP_2048x09", + "SDP_4096x05", + "SDP_1024x32_ECC", + "SDP_1024x40", + "SDP_1024x36_BP", + "SDP_512x32_ECC", + "SDP_512x36_BP", + "SDP_2048x10", + "SP_512x32_ECC", + "SP_512x36_BP", + "SP_1024x20", + "SP2_512x18_BP", + "SP2_1024x09", + "SP2_2048x05": wire _TECHMAP_FAIL_ = 0; + `endif + `ifdef IS_T16FFC + "TDP_2048x18_FP", + "TDP_2048x16_BP", + "TDP_4096x09", + "TDP_8192x05", + "TDP_2048x32_ECC", + "TDP_2048x40", + "TDP_2048x36_BP", + "SDP_2048x18_FP", + "SDP_2048x16_BP", + "SDP_4096x09", + "SDP_8192x05", + "SDP_2048x32_ECC", + "SDP_2048x40", + "SDP_2048x36_BP", + "SDP_1024x32_ECC", + "SDP_1024x36_BP", + "SDP_4096x10", + "SP_1024x32_ECC", + "SP_1024x36_BP", + "SP_2048x20", + "SP2_1024x18_BP", + "SP2_2048x09", + "SP2_4096x05": wire _TECHMAP_FAIL_ = 0; + `endif + default: wire _TECHMAP_FAIL_ = 1; + endcase + endgenerate endmodule + +module $__ANALOGDEVICES_BLOCKRAM_HALF_ (...); + // libmap params + parameter INIT = 0; + parameter OPTION_MODE = "NONE"; + parameter OPTION_SIZE = "NONE"; + parameter OPTION_ERR = "NONE"; + parameter PORT_A_WR_EN_WIDTH = 1; + parameter PORT_A_CLK_POL = 1; + parameter PORT_B_WR_EN_WIDTH = 1; + parameter PORT_B_CLK_POL = 1; + + // needs -force-params + parameter WIDTH = 40; + parameter ABITS = 13; + + // libmap ports + input PORT_A_CLK; + input PORT_A_CLK_EN; + input [ABITS-1:0] PORT_A_ADDR; + input [WIDTH-1:0] PORT_A_WR_DATA; + output [WIDTH-1:0] PORT_A_RD_DATA; + input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN; + + input PORT_B_CLK; + input PORT_B_CLK_EN; + input [ABITS-1:0] PORT_B_ADDR; + input [WIDTH-1:0] PORT_B_WR_DATA; + output [WIDTH-1:0] PORT_B_RD_DATA; + input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN; + + $__ANALOGDEVICES_BLOCKRAM_FULL_ + # ( + .INIT(INIT), + .OPTION_MODE(OPTION_MODE), + .OPTION_SIZE(OPTION_SIZE), + .PORT_A_WR_EN_WIDTH(PORT_A_WR_EN_WIDTH), + .PORT_A_CLK_POL(PORT_A_CLK_POL), + .PORT_B_WR_EN_WIDTH(PORT_B_WR_EN_WIDTH), + .PORT_B_CLK_POL(PORT_B_CLK_POL), + .WIDTH(WIDTH), + .ABITS(ABITS) + ) + _TECHMAP_REPLACE_ + ( + .PORT_A_CLK(PORT_A_CLK), + .PORT_A_CLK_EN(PORT_A_CLK_EN), + .PORT_A_ADDR(PORT_A_ADDR), + .PORT_A_WR_DATA(PORT_A_WR_DATA), + .PORT_A_RD_DATA(PORT_A_RD_DATA), + .PORT_A_WR_EN(PORT_A_WR_EN), + .PORT_B_CLK(PORT_B_CLK), + .PORT_B_CLK_EN(PORT_B_CLK_EN), + .PORT_B_ADDR(PORT_B_ADDR), + .PORT_B_WR_DATA(PORT_B_WR_DATA), + .PORT_B_RD_DATA(PORT_B_RD_DATA), + .PORT_B_WR_EN(PORT_B_WR_EN) + ); +endmodule + +module $__ANALOGDEVICES_BLOCKRAM_QUARTER_ (...); + // libmap params + parameter INIT = 0; + parameter OPTION_MODE = "NONE"; + parameter OPTION_SIZE = "NONE"; + parameter OPTION_ERR = "NONE"; + parameter PORT_A_WR_EN_WIDTH = 1; + parameter PORT_A_CLK_POL = 1; + parameter PORT_B_WR_EN_WIDTH = 1; + parameter PORT_B_CLK_POL = 1; + + // needs -force-params + parameter WIDTH = 40; + parameter ABITS = 13; + + // libmap ports + input PORT_A_CLK; + input PORT_A_CLK_EN; + input [ABITS-1:0] PORT_A_ADDR; + input [WIDTH-1:0] PORT_A_WR_DATA; + output [WIDTH-1:0] PORT_A_RD_DATA; + input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN; + + $__ANALOGDEVICES_BLOCKRAM_FULL_ + # ( + .INIT(INIT), + .OPTION_MODE(OPTION_MODE), + .OPTION_SIZE(OPTION_SIZE), + .PORT_A_WR_EN_WIDTH(PORT_A_WR_EN_WIDTH), + .PORT_A_CLK_POL(PORT_A_CLK_POL), + .PORT_B_WR_EN_WIDTH(PORT_B_WR_EN_WIDTH), + .PORT_B_CLK_POL(PORT_B_CLK_POL), + .WIDTH(WIDTH), + .ABITS(ABITS) + ) + _TECHMAP_REPLACE_ + ( + .PORT_A_CLK(PORT_A_CLK), + .PORT_A_CLK_EN(PORT_A_CLK_EN), + .PORT_A_ADDR(PORT_A_ADDR), + .PORT_A_WR_DATA(PORT_A_WR_DATA), + .PORT_A_RD_DATA(PORT_A_RD_DATA), + .PORT_A_WR_EN(PORT_A_WR_EN), + ); +endmodule diff --git a/techlibs/analogdevices/lutrams.txt b/techlibs/analogdevices/lutrams.txt index 804b78252..a52c28171 100644 --- a/techlibs/analogdevices/lutrams.txt +++ b/techlibs/analogdevices/lutrams.txt @@ -1,39 +1,20 @@ -# Single-port RAMs. - -ram distributed $__ANALOGDEVICES_LUTRAM_SP_ { - option "ABITS" 5 { - cost 1; - abits 5; - } - option "ABITS" 6 { - cost 2; - abits 6; - } +ram distributed $__ANALOGDEVICES_LUTRAM_ { + option "SIZE" 32 abits 5; + option "SIZE" 64 abits 6; width 1; init no_undef; prune_rom; port arsw "RW" { clock posedge; } -} - -# Dual-port RAMs. - -ram distributed $__ANALOGDEVICES_LUTRAM_DP_ { - option "ABITS" 5 { - cost 2; - abits 5; + option "MODE" "SP" { + option "SIZE" 32 cost 1; + option "SIZE" 64 cost 2; } - option "ABITS" 6 { - cost 4; - abits 6; - } - width 1; - init no_undef; - prune_rom; - port arsw "RW" { - clock posedge; - } - port ar "R" { + option "MODE" "DP" { + option "SIZE" 32 cost 2; + option "SIZE" 64 cost 4; + port ar "R" { + } } } diff --git a/techlibs/analogdevices/lutrams_map.v b/techlibs/analogdevices/lutrams_map.v index 7962e616c..18fa93516 100644 --- a/techlibs/analogdevices/lutrams_map.v +++ b/techlibs/analogdevices/lutrams_map.v @@ -1,54 +1,116 @@ -module $__ANALOGDEVICES_LUTRAM_SP_ (...); +module $__ANALOGDEVICES_LUTRAM_ (...); parameter INIT = 0; -parameter OPTION_ABITS = 5; +parameter OPTION_SIZE = 32; +parameter OPTION_MODE = "SP"; +parameter ABITS = 5; +parameter WIDTH = 1; output PORT_RW_RD_DATA; input PORT_RW_WR_DATA; -input [OPTION_ABITS-1:0] PORT_RW_ADDR; +input [ABITS-1:0] PORT_RW_ADDR; input PORT_RW_WR_EN; input PORT_RW_CLK; +output PORT_R_RD_DATA; +input [ABITS-1:0] PORT_R_ADDR; + generate -case(OPTION_ABITS) -5: - RAMS32X1 - #( - .INIT(INIT) - ) - _TECHMAP_REPLACE_ - ( - .O(PORT_RW_RD_DATA), - .A0(PORT_RW_ADDR[0]), - .A1(PORT_RW_ADDR[1]), - .A2(PORT_RW_ADDR[2]), - .A3(PORT_RW_ADDR[3]), - .A4(PORT_RW_ADDR[4]), - .D(PORT_RW_WR_DATA), - .WCLK(PORT_RW_CLK), - .WE(PORT_RW_WR_EN) - ); -6: - RAMS64X1 - #( - .INIT(INIT) - ) - _TECHMAP_REPLACE_ - ( - .O(PORT_RW_RD_DATA), - .A0(PORT_RW_ADDR[0]), - .A1(PORT_RW_ADDR[1]), - .A2(PORT_RW_ADDR[2]), - .A3(PORT_RW_ADDR[3]), - .A4(PORT_RW_ADDR[4]), - .A5(PORT_RW_ADDR[5]), - .D(PORT_RW_WR_DATA), - .WCLK(PORT_RW_CLK), - .WE(PORT_RW_WR_EN) - ); -default: - $error("invalid OPTION_ABITS"); -endcase + if (OPTION_MODE=="SP") + case(OPTION_SIZE) + 32: + RAMS32X1 + #( + .INIT(INIT) + ) + _TECHMAP_REPLACE_ + ( + .O(PORT_RW_RD_DATA), + .A0(PORT_RW_ADDR[0]), + .A1(PORT_RW_ADDR[1]), + .A2(PORT_RW_ADDR[2]), + .A3(PORT_RW_ADDR[3]), + .A4(PORT_RW_ADDR[4]), + .D(PORT_RW_WR_DATA), + .WCLK(PORT_RW_CLK), + .WE(PORT_RW_WR_EN) + ); + 64: + RAMS64X1 + #( + .INIT(INIT) + ) + _TECHMAP_REPLACE_ + ( + .O(PORT_RW_RD_DATA), + .A0(PORT_RW_ADDR[0]), + .A1(PORT_RW_ADDR[1]), + .A2(PORT_RW_ADDR[2]), + .A3(PORT_RW_ADDR[3]), + .A4(PORT_RW_ADDR[4]), + .A5(PORT_RW_ADDR[5]), + .D(PORT_RW_WR_DATA), + .WCLK(PORT_RW_CLK), + .WE(PORT_RW_WR_EN) + ); + default: + $error("invalid SIZE/MODE combination"); + endcase + else if (OPTION_MODE=="DP") + case (OPTION_SIZE) + 32: + RAMD32X1 + #( + .INIT(INIT) + ) + _TECHMAP_REPLACE_ + ( + .DPO(PORT_R_RD_DATA), + .SPO(PORT_RW_RD_DATA), + .A0(PORT_RW_ADDR[0]), + .A1(PORT_RW_ADDR[1]), + .A2(PORT_RW_ADDR[2]), + .A3(PORT_RW_ADDR[3]), + .A4(PORT_RW_ADDR[4]), + .D(PORT_RW_WR_DATA), + .DPRA0(PORT_R_ADDR[0]), + .DPRA1(PORT_R_ADDR[1]), + .DPRA2(PORT_R_ADDR[2]), + .DPRA3(PORT_R_ADDR[3]), + .DPRA4(PORT_R_ADDR[4]), + .WCLK(PORT_RW_CLK), + .WE(PORT_RW_WR_EN) + ); + 64: + RAMD64X1 + #( + .INIT(INIT) + ) + _TECHMAP_REPLACE_ + ( + .DPO(PORT_R_RD_DATA), + .SPO(PORT_RW_RD_DATA), + .A0(PORT_RW_ADDR[0]), + .A1(PORT_RW_ADDR[1]), + .A2(PORT_RW_ADDR[2]), + .A3(PORT_RW_ADDR[3]), + .A4(PORT_RW_ADDR[4]), + .A5(PORT_RW_ADDR[5]), + .D(PORT_RW_WR_DATA), + .DPRA0(PORT_R_ADDR[0]), + .DPRA1(PORT_R_ADDR[1]), + .DPRA2(PORT_R_ADDR[2]), + .DPRA3(PORT_R_ADDR[3]), + .DPRA4(PORT_R_ADDR[4]), + .DPRA5(PORT_R_ADDR[5]), + .WCLK(PORT_RW_CLK), + .WE(PORT_RW_WR_EN) + ); + default: + $error("invalid SIZE/MODE combination"); + endcase + else + wire _TECHMAP_FAIL_ = 1; endgenerate endmodule @@ -57,70 +119,21 @@ endmodule module $__ANALOGDEVICES_LUTRAM_DP_ (...); parameter INIT = 0; -parameter OPTION_ABITS = 5; +parameter OPTION_SIZE = 32; +parameter ABITS = 5; +parameter WIDTH = 1; output PORT_RW_RD_DATA; input PORT_RW_WR_DATA; -input [OPTION_ABITS-1:0] PORT_RW_ADDR; +input [ABITS-1:0] PORT_RW_ADDR; input PORT_RW_WR_EN; input PORT_RW_CLK; output PORT_R_RD_DATA; -input [OPTION_ABITS-1:0] PORT_R_ADDR; +input [ABITS-1:0] PORT_R_ADDR; generate -case (OPTION_ABITS) -5: - RAMD32X1 - #( - .INIT(INIT) - ) - _TECHMAP_REPLACE_ - ( - .DPO(PORT_R_RD_DATA), - .SPO(PORT_RW_RD_DATA), - .A0(PORT_RW_ADDR[0]), - .A1(PORT_RW_ADDR[1]), - .A2(PORT_RW_ADDR[2]), - .A3(PORT_RW_ADDR[3]), - .A4(PORT_RW_ADDR[4]), - .D(PORT_RW_WR_DATA), - .DPRA0(PORT_R_ADDR[0]), - .DPRA1(PORT_R_ADDR[1]), - .DPRA2(PORT_R_ADDR[2]), - .DPRA3(PORT_R_ADDR[3]), - .DPRA4(PORT_R_ADDR[4]), - .WCLK(PORT_RW_CLK), - .WE(PORT_RW_WR_EN) - ); -6: - RAMD64X1 - #( - .INIT(INIT) - ) - _TECHMAP_REPLACE_ - ( - .DPO(PORT_R_RD_DATA), - .SPO(PORT_RW_RD_DATA), - .A0(PORT_RW_ADDR[0]), - .A1(PORT_RW_ADDR[1]), - .A2(PORT_RW_ADDR[2]), - .A3(PORT_RW_ADDR[3]), - .A4(PORT_RW_ADDR[4]), - .A5(PORT_RW_ADDR[5]), - .D(PORT_RW_WR_DATA), - .DPRA0(PORT_R_ADDR[0]), - .DPRA1(PORT_R_ADDR[1]), - .DPRA2(PORT_R_ADDR[2]), - .DPRA3(PORT_R_ADDR[3]), - .DPRA4(PORT_R_ADDR[4]), - .DPRA5(PORT_R_ADDR[5]), - .WCLK(PORT_RW_CLK), - .WE(PORT_RW_WR_EN) - ); -default: - $error("invalid OPTION_ABITS/WIDTH combination"); -endcase + endgenerate endmodule diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc index 18619de7a..8a41408c8 100644 --- a/techlibs/analogdevices/synth_analogdevices.cc +++ b/techlibs/analogdevices/synth_analogdevices.cc @@ -355,10 +355,9 @@ struct SynthAnalogDevicesPass : public ScriptPass params = " [...]"; } else { params += " -logic-cost-rom 0.015625"; + params += " -force-params"; params += " -lib +/analogdevices/lutrams.txt"; - lutrams_map = "+/analogdevices/lutrams_map.v"; params += " -lib +/analogdevices/brams.txt"; - brams_map = "+/analogdevices/brams_map.v"; params += tech_param; brams_map += tech_param; if (nolutram) From f06018306d2d6e73b2a461b99864980363a33c26 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Sat, 18 Oct 2025 17:31:54 +1300 Subject: [PATCH 273/291] analogdevices: Fixing up bram Tested all the accepted configurations in eXpreso, disabling the RBRAM2 configs that fail to place, and increasing the cost for the double site TDP memories. --- techlibs/analogdevices/brams.txt | 129 +++++++++++++++++++++++++---- techlibs/analogdevices/brams_map.v | 30 ++++--- 2 files changed, 130 insertions(+), 29 deletions(-) diff --git a/techlibs/analogdevices/brams.txt b/techlibs/analogdevices/brams.txt index f5c45aacf..10cdadefb 100644 --- a/techlibs/analogdevices/brams.txt +++ b/techlibs/analogdevices/brams.txt @@ -6,8 +6,17 @@ ifdef IS_T16FFC { abits 11; width 32; byte 32; - option "MODE" "TDP" cost 2501; - option "MODE" "SDP" cost 2401; + option "MODE" "TDP" cost 4502; + option "MODE" "SDP" forbid; + option "MODE" "SP" forbid; + } + option "SIZE" "1024x32" { + abits 10; + width 32; + byte 32; + option "MODE" "TDP" forbid; + option "MODE" "SDP" cost 2402; + option "MODE" "SP" forbid; } } option "ERR" "BP" { @@ -16,8 +25,28 @@ ifdef IS_T16FFC { abits 11; width 36; byte 9; - option "MODE" "TDP" cost 2504; + option "MODE" "TDP" cost 4504; + option "MODE" "SDP" forbid; + option "MODE" "SP" forbid; + } + option "SIZE" "1024x36" { + abits 10; + width 36; + byte 9; + option "MODE" "TDP" forbid; option "MODE" "SDP" cost 2404; + option "MODE" "SP" forbid; + } + } + option "ERR" "FP" { + style "FP"; + option "SIZE" "2048x18" { + abits 11; + width 18; + byte 18; + option "MODE" "TDP" cost 2501; + option "MODE" "SDP" cost 2401; + option "MODE" "SP" forbid; } } option "ERR" "NONE" { @@ -26,14 +55,16 @@ ifdef IS_T16FFC { width 5; byte 1; option "MODE" "TDP" cost 2505; - option "MODE" "SDP" cost 2405; + option "MODE" "SDP" forbid; + option "MODE" "SP" forbid; } option "SIZE" "4096x09" { abits 12; width 9; byte 1; option "MODE" "TDP" cost 2509; - option "MODE" "SDP" cost 2409; + option "MODE" "SDP" forbid; + option "MODE" "SP" forbid; } option "SIZE" "4096x10" { abits 12; @@ -41,13 +72,23 @@ ifdef IS_T16FFC { byte 1; option "MODE" "TDP" forbid; option "MODE" "SDP" cost 2410; + option "MODE" "SP" forbid; + } + option "SIZE" "2048x20" { + abits 11; + width 20; + byte 1; + option "MODE" "TDP" forbid; + option "MODE" "SDP" forbid; + option "MODE" "SP" cost 2320; } option "SIZE" "2048x40" { abits 11; width 40; byte 8; - option "MODE" "TDP" cost 2505; - option "MODE" "SDP" cost 2405; + option "MODE" "TDP" cost 4505; + option "MODE" "SDP" forbid; + option "MODE" "SP" forbid; } } @@ -76,6 +117,13 @@ ifdef IS_T16FFC { clken; } } + option "MODE" "SP" { + port srsw "A" { + clock anyedge; + clken; + rdwr no_change; + } + } } } @@ -86,8 +134,17 @@ ram block $__ANALOGDEVICES_BLOCKRAM_HALF_ { abits 10; width 32; byte 32; - option "MODE" "SDP" cost 2401; - option "MODE" "SP" cost 2301; + option "MODE" "SDP" cost 2402; + option "MODE" "SP" forbid; + option "MODE" "SP2" forbid; + } + option "SIZE" "512x32" { + abits 9; + width 32; + byte 32; + option "MODE" "SDP" forbid; + option "MODE" "SP" cost 2302; + option "MODE" "SP2" forbid; } } option "ERR" "BP" { @@ -97,7 +154,27 @@ ram block $__ANALOGDEVICES_BLOCKRAM_HALF_ { width 36; byte 9; option "MODE" "SDP" cost 2404; + option "MODE" "SP" forbid; + option "MODE" "SP2" forbid; + } + option "SIZE" "512x36" { + abits 9; + width 36; + byte 9; + option "MODE" "SDP" forbid; option "MODE" "SP" cost 2304; + option "MODE" "SP2" forbid; + } + } + option "ERR" "FP" { + style "FP"; + option "SIZE" "1024x18" { + abits 10; + width 18; + byte 18; + option "MODE" "SDP" forbid; + option "MODE" "SP" forbid; + option "MODE" "SP2" cost 2301; } } option "ERR" "NONE" { @@ -107,27 +184,39 @@ ram block $__ANALOGDEVICES_BLOCKRAM_HALF_ { byte 1; option "MODE" "SDP" cost 2405; option "MODE" "SP" cost 2305; + option "MODE" "SP2" forbid; } option "SIZE" "2048x09" { abits 11; width 9; byte 1; option "MODE" "SDP" cost 2409; - option "MODE" "SP" cost 2309; + option "MODE" "SP" forbid; + option "MODE" "SP2" cost 2309; } option "SIZE" "2048x10" { abits 11; width 10; byte 1; option "MODE" "SDP" cost 2410; - option "MODE" "SP" cost 2310; + option "MODE" "SP" forbid; + option "MODE" "SP2" forbid; + } + option "SIZE" "1024x20" { + abits 10; + width 20; + byte 1; + option "MODE" "SDP" forbid; + option "MODE" "SP" cost 2320; + option "MODE" "SP2" forbid; } option "SIZE" "1024x40" { abits 10; width 40; byte 8; option "MODE" "SDP" cost 2405; - option "MODE" "SP" cost 2305; + option "MODE" "SP" forbid; + option "MODE" "SP2" forbid; } } @@ -143,6 +232,14 @@ ram block $__ANALOGDEVICES_BLOCKRAM_HALF_ { } } option "MODE" "SP" { + ifdef IS_T16FFC forbid; + port srsw "A" { + clock anyedge; + clken; + rdwr no_change; + } + } + option "MODE" "SP2" { ifdef IS_T40LP forbid; port srsw "A" { clock anyedge; @@ -160,7 +257,7 @@ ifdef IS_T40LP { abits 9; width 18; byte 9; - option "MODE" "SP" cost 2202; + option "MODE" "SP2" cost 2202; } } option "ERR" "NONE" { @@ -168,16 +265,16 @@ ifdef IS_T40LP { abits 11; width 5; byte 1; - option "MODE" "SP" cost 2205; + option "MODE" "SP2" cost 2205; } option "SIZE" "1024x09" { abits 10; width 9; byte 1; - option "MODE" "SP" cost 2209; + option "MODE" "SP2" cost 2209; } } - option "MODE" "SP" { + option "MODE" "SP2" { port srsw "A" { clock anyedge; clken; diff --git a/techlibs/analogdevices/brams_map.v b/techlibs/analogdevices/brams_map.v index c486670e3..f1acaaf78 100644 --- a/techlibs/analogdevices/brams_map.v +++ b/techlibs/analogdevices/brams_map.v @@ -6,7 +6,7 @@ module $__ANALOGDEVICES_BLOCKRAM_FULL_ (...); parameter OPTION_ERR = "NONE"; parameter PORT_A_WR_EN_WIDTH = 1; parameter PORT_A_CLK_POL = 1; - parameter PORT_B_WR_EN_WIDTH = 1; + parameter PORT_B_WR_EN_WIDTH = PORT_A_WR_EN_WIDTH; parameter PORT_B_CLK_POL = 1; // needs -force-params @@ -23,9 +23,7 @@ module $__ANALOGDEVICES_BLOCKRAM_FULL_ (...); // localparam BRAM_MODE = "SDP_2048x36_BP"; localparam BRAM_MODE = (OPTION_ERR!="NONE") ? {OPTION_MODE, "_", OPTION_SIZE, "_", OPTION_ERR} : {OPTION_MODE, "_", OPTION_SIZE}; - localparam PBITS = (OPTION_ERR=="FP") ? 1 : - (OPTION_ERR=="BP") ? PORT_A_WR_EN_WIDTH : - 0; + localparam PBITS = (OPTION_ERR=="BP") ? PORT_A_WR_EN_WIDTH : 1; // libmap ports input PORT_A_CLK; @@ -51,8 +49,8 @@ module $__ANALOGDEVICES_BLOCKRAM_FULL_ (...); #( .TARGET_NODE(NODE), .BRAM_MODE(BRAM_MODE), - .QA_REG(0), - .QB_REG(0), + .QA_REG((OPTION_ERR=="ECC") ? 1 : 0), + .QB_REG((OPTION_ERR=="ECC") ? 1 : 0), .CLKA_INV(!PORT_A_CLK_POL), .CLKB_INV(!PORT_B_CLK_POL), .DATA_WIDTH(WIDTH), @@ -78,6 +76,7 @@ module $__ANALOGDEVICES_BLOCKRAM_FULL_ (...); // check config generate + if (PORT_A_WR_EN_WIDTH == PORT_B_WR_EN_WIDTH) case (BRAM_MODE) `ifdef IS_T40LP "SDP_1024x18_FP", @@ -107,11 +106,12 @@ module $__ANALOGDEVICES_BLOCKRAM_FULL_ (...); "TDP_2048x36_BP", "SDP_2048x18_FP", "SDP_2048x16_BP", - "SDP_4096x09", - "SDP_8192x05", - "SDP_2048x32_ECC", - "SDP_2048x40", - "SDP_2048x36_BP", + // The following are rejected in eXpreso + // "SDP_4096x09", + // "SDP_8192x05", + // "SDP_2048x32_ECC", + // "SDP_2048x40", + // "SDP_2048x36_BP", "SDP_1024x32_ECC", "SDP_1024x36_BP", "SDP_4096x10", @@ -124,6 +124,8 @@ module $__ANALOGDEVICES_BLOCKRAM_FULL_ (...); `endif default: wire _TECHMAP_FAIL_ = 1; endcase + else + wire _TECHMAP_FAIL_ = 1; endgenerate endmodule @@ -136,7 +138,7 @@ module $__ANALOGDEVICES_BLOCKRAM_HALF_ (...); parameter OPTION_ERR = "NONE"; parameter PORT_A_WR_EN_WIDTH = 1; parameter PORT_A_CLK_POL = 1; - parameter PORT_B_WR_EN_WIDTH = 1; + parameter PORT_B_WR_EN_WIDTH = PORT_A_WR_EN_WIDTH; parameter PORT_B_CLK_POL = 1; // needs -force-params @@ -163,6 +165,7 @@ module $__ANALOGDEVICES_BLOCKRAM_HALF_ (...); .INIT(INIT), .OPTION_MODE(OPTION_MODE), .OPTION_SIZE(OPTION_SIZE), + .OPTION_ERR(OPTION_ERR), .PORT_A_WR_EN_WIDTH(PORT_A_WR_EN_WIDTH), .PORT_A_CLK_POL(PORT_A_CLK_POL), .PORT_B_WR_EN_WIDTH(PORT_B_WR_EN_WIDTH), @@ -195,7 +198,7 @@ module $__ANALOGDEVICES_BLOCKRAM_QUARTER_ (...); parameter OPTION_ERR = "NONE"; parameter PORT_A_WR_EN_WIDTH = 1; parameter PORT_A_CLK_POL = 1; - parameter PORT_B_WR_EN_WIDTH = 1; + parameter PORT_B_WR_EN_WIDTH = PORT_A_WR_EN_WIDTH; parameter PORT_B_CLK_POL = 1; // needs -force-params @@ -215,6 +218,7 @@ module $__ANALOGDEVICES_BLOCKRAM_QUARTER_ (...); .INIT(INIT), .OPTION_MODE(OPTION_MODE), .OPTION_SIZE(OPTION_SIZE), + .OPTION_ERR(OPTION_ERR), .PORT_A_WR_EN_WIDTH(PORT_A_WR_EN_WIDTH), .PORT_A_CLK_POL(PORT_A_CLK_POL), .PORT_B_WR_EN_WIDTH(PORT_B_WR_EN_WIDTH), From 5d3ed5a4182b81c00fac5330eb6cb0da560fd56d Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Sat, 18 Oct 2025 17:38:01 +1300 Subject: [PATCH 274/291] analogdevices: Extra tests `mem_gen.py` based on quicklogic tests. Remove BUFG from `lutram.ys`. Extra `sync_ram_sp` models in `arch/common/blockram.v`. Add analogdevices to main makefile tests. Not all the other tests are passing, but that's fine for now. --- Makefile | 1 + tests/arch/analogdevices/.gitignore | 1 + tests/arch/analogdevices/lutram.ys | 18 ++-- tests/arch/analogdevices/mem_gen.py | 121 +++++++++++++++++++++++++++ tests/arch/analogdevices/run-test.sh | 3 +- tests/arch/common/blockram.v | 80 ++++++++++++++++++ 6 files changed, 211 insertions(+), 13 deletions(-) create mode 100644 tests/arch/analogdevices/.gitignore create mode 100644 tests/arch/analogdevices/mem_gen.py diff --git a/Makefile b/Makefile index cf9fe9049..33ff74fa4 100644 --- a/Makefile +++ b/Makefile @@ -920,6 +920,7 @@ endif # Tests that generate .mk with tests/gen-tests-makefile.sh MK_TEST_DIRS = +MK_TEST_DIRS += tests/arch/analogdevices MK_TEST_DIRS += tests/arch/anlogic MK_TEST_DIRS += tests/arch/ecp5 MK_TEST_DIRS += tests/arch/efinix diff --git a/tests/arch/analogdevices/.gitignore b/tests/arch/analogdevices/.gitignore new file mode 100644 index 000000000..fb232f235 --- /dev/null +++ b/tests/arch/analogdevices/.gitignore @@ -0,0 +1 @@ +t_*.ys diff --git a/tests/arch/analogdevices/lutram.ys b/tests/arch/analogdevices/lutram.ys index d3a088bdb..35fc09c86 100644 --- a/tests/arch/analogdevices/lutram.ys +++ b/tests/arch/analogdevices/lutram.ys @@ -12,10 +12,9 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite design -load postopt cd lutram_1w1r -select -assert-count 1 t:BUFG select -assert-count 8 t:FFRE select -assert-count 8 t:RAMS32X1 -select -assert-none t:BUFG t:FFRE t:RAMS32X1 %% t:* %D +select -assert-none t:FFRE t:RAMS32X1 %% t:* %D design -reset @@ -33,10 +32,9 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite design -load postopt cd lutram_1w1r dump -select -assert-count 1 t:BUFG select -assert-count 8 t:FFRE select -assert-count 8 t:RAMS64X1 -select -assert-none t:BUFG t:FFRE t:RAMS64X1 %% t:* %D +select -assert-none t:FFRE t:RAMS64X1 %% t:* %D design -reset @@ -53,10 +51,9 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite design -load postopt cd lutram_1w3r -select -assert-count 1 t:BUFG select -assert-count 24 t:FFRE select -assert-count 16 t:RAMD32X1 -select -assert-none t:BUFG t:FFRE t:RAMD32X1 %% t:* %D +select -assert-none t:FFRE t:RAMD32X1 %% t:* %D design -reset @@ -73,10 +70,9 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite design -load postopt cd lutram_1w3r -select -assert-count 1 t:BUFG select -assert-count 24 t:FFRE select -assert-count 16 t:RAMD64X1 -select -assert-none t:BUFG t:FFRE t:RAMD64X1 %% t:* %D +select -assert-none t:FFRE t:RAMD64X1 %% t:* %D design -reset @@ -93,10 +89,9 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite design -load postopt cd lutram_1w1r -select -assert-count 1 t:BUFG select -assert-count 6 t:FFRE select -assert-count 6 t:RAMS32X1 -select -assert-none t:BUFG t:FFRE t:RAMS32X1 %% t:* %D +select -assert-none t:FFRE t:RAMS32X1 %% t:* %D design -reset @@ -113,7 +108,6 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite design -load postopt cd lutram_1w1r -select -assert-count 1 t:BUFG select -assert-count 6 t:FFRE select -assert-count 6 t:RAMS64X1 -select -assert-none t:BUFG t:FFRE t:RAMS64X1 %% t:* %D +select -assert-none t:FFRE t:RAMS64X1 %% t:* %D diff --git a/tests/arch/analogdevices/mem_gen.py b/tests/arch/analogdevices/mem_gen.py new file mode 100644 index 000000000..b8037b918 --- /dev/null +++ b/tests/arch/analogdevices/mem_gen.py @@ -0,0 +1,121 @@ +from __future__ import annotations + +from dataclasses import dataclass + + +blockram_template = """# ====================================== +log ** GENERATING TEST {top} WITH PARAMS{param_str} +design -reset; read_verilog -defer ../common/blockram.v +chparam{param_str} {top} +hierarchy -top {top} +echo on +debug synth_analogdevices -tech {tech} -top {top} {opts} -run :map_ffram +stat; echo off +""" +inference_tests: "list[tuple[str, list[tuple[str, int]], str, list[str], list[str]]]" = [ + # RBRAM2 has TDP and SDP for 8192x5bit, 4096x9bit, and 2048x40bit + ("t16ffc", [("ADDRESS_WIDTH", 13), ("DATA_WIDTH", 5)], "sync_ram_*dp", ["-assert-count 1 t:RBRAM2"], []), + ("t16ffc", [("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9)], "sync_ram_*dp", ["-assert-count 1 t:RBRAM2"], []), + ("t16ffc", [("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 40)], "sync_ram_*dp", ["-assert-count 1 t:RBRAM2"], []), + # LUTRAM is generally cheaper than BRAM for undersized (SDP) memories + ("t16ffc", [("ADDRESS_WIDTH", 6), ("DATA_WIDTH", 1)], "sync_ram_sdp", ["-assert-count 1 t:RAMD64X1"], []), + ("t16ffc", [("ADDRESS_WIDTH", 6), ("DATA_WIDTH", 8)], "sync_ram_sdp", ["-assert-count 8 t:RAMD64X1"], []), + ("t16ffc", [("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 8)], "sync_ram_sdp", ["-assert-count 128 t:RAMD64X1"], []), + ("t16ffc", [("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 16)], "sync_ram_sdp", ["-assert-count 256 t:RAMD64X1"], []), + # RBRAM is half the depth of RBRAM2, and doesn't have TDP, also LUTRAM is cheaper, so we need to specify not to use it + ("t40lp", [("ADDRESS_WIDTH", 13), ("DATA_WIDTH", 5)], "sync_ram_sdp", ["-assert-count 2 t:RBRAM"], ["-nolutram"]), + ("t40lp", [("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 5)], "sync_ram_sdp", ["-assert-count 1 t:RBRAM"], ["-nolutram"]), + ("t40lp", [("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 9)], "sync_ram_sdp", ["-assert-count 1 t:RBRAM"], ["-nolutram"]), + ("t40lp", [("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 40)], "sync_ram_sdp", ["-assert-count 1 t:RBRAM"], ["-nolutram"]), + # 2048x32 and 2048x36bit are also valid + ("t16ffc", [("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 32)], "sync_ram_*dp", ["-assert-count 1 t:RBRAM2"], []), + ("t16ffc", [("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 1 t:RBRAM2"], []), + ("t40lp", [("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 32)], "sync_ram_sdp", ["-assert-count 1 t:RBRAM"], ["-nolutram"]), + ("t40lp", [("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_sdp", ["-assert-count 1 t:RBRAM"], ["-nolutram"]), + + # 4096x16/18bit can be mapped to a single 2048x32/36bit + ("t16ffc", [("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 16)], "sync_ram_*dp", ["-assert-count 1 t:RBRAM2"], []), + ("t16ffc", [("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 18)], "sync_ram_*dp", ["-assert-count 1 t:RBRAM2"], []), + ("t40lp", [("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16)], "sync_ram_sdp", ["-assert-count 1 t:RBRAM"], ["-nolutram"]), + ("t40lp", [("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_sdp", ["-assert-count 1 t:RBRAM"], ["-nolutram"]), + # same for 8192x8/9bit + ("t16ffc", [("ADDRESS_WIDTH", 13), ("DATA_WIDTH", 8)], "sync_ram_*dp", ["-assert-count 1 t:RBRAM2"], []), + ("t16ffc", [("ADDRESS_WIDTH", 13), ("DATA_WIDTH", 9)], "sync_ram_*dp", ["-assert-count 1 t:RBRAM2"], []), + ("t40lp", [("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8)], "sync_ram_sdp", ["-assert-count 1 t:RBRAM"], ["-nolutram"]), + ("t40lp", [("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9)], "sync_ram_sdp", ["-assert-count 1 t:RBRAM"], ["-nolutram"]), + # but 4096x20bit requires extra memories because 2048x40bit has 8bit byte enables (which doesn't divide 20bit evenly) + ("t16ffc", [("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 20)], "sync_ram_sdp", ["-assert-count 2 t:RBRAM2"], []), + ("t40lp", [("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 20)], "sync_ram_sdp", ["-assert-count 2 t:RBRAM"], ["-nolutram"]), +] + +@dataclass +class TestClass: + params: dict[str, int] + top: str + assertions: list[str] + test_steps: None | list[dict[str, int]] + opts: list[str] + tech: str = "t16ffc" + +sim_tests: list[TestClass] = [] + +for (tech, params, top, assertions, opts) in inference_tests: + sim_test = TestClass( + params=dict(params), + top=top, + assertions=assertions, + test_steps=None, + opts=opts, + tech=tech, + ) + sim_tests.append(sim_test) + +i = 0 +j = 0 +max_j = 16 +f = None +for sim_test in sim_tests: + # format params + param_str = "" + for (key, val) in sim_test.params.items(): + param_str += f" -set {key} {val}" + + # resolve top module wildcards + top_list = [sim_test.top] + if "*dp" in sim_test.top: + top_list += [ + sim_test.top.replace("*dp", dp_sub) for dp_sub in ["sdp", "tdp"] + ] + if "w*r" in sim_test.top: + top_list += [ + sim_test.top.replace("w*r", wr_sub) for wr_sub in ["wwr", "wrr"] + ] + if len(top_list) > 1: + top_list.pop(0) + + # iterate over string substitutions + for top in top_list: + # limit number of tests per file to allow parallel make + if not f: + fn = f"t_mem{i}.ys" + f = open(fn, mode="w") + j = 0 + + # output yosys script test file + print( + blockram_template.format(param_str=param_str, top=top, tech=sim_test.tech, opts=" ".join(sim_test.opts)), + file=f + ) + for assertion in sim_test.assertions: + print(f"log ** CHECKING CELL COUNTS FOR TEST {top} WITH PARAMS{param_str} ON TECH {sim_test.tech}", file=f) + print(f"select {assertion}", file=f) + print("", file=f) + + # increment test counter + j += 1 + if j >= max_j: + f = f.close() + i += 1 + +if f: + f.close() diff --git a/tests/arch/analogdevices/run-test.sh b/tests/arch/analogdevices/run-test.sh index 691b70966..9b5e2f7f4 100755 --- a/tests/arch/analogdevices/run-test.sh +++ b/tests/arch/analogdevices/run-test.sh @@ -1,4 +1,5 @@ #!/usr/bin/env bash set -eu +python3 mem_gen.py source ../../gen-tests-makefile.sh -generate_mk --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'" +generate_mk --yosys-scripts --bash diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v index 4a9d45a6b..4358a4655 100644 --- a/tests/arch/common/blockram.v +++ b/tests/arch/common/blockram.v @@ -22,6 +22,30 @@ module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) endmodule // sync_ram_sp +module sync_ram_sp_nochange #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) + (input wire write_enable, clk, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in] <= data_in; + else + data_out_r <= memory[address_in]; + end + + assign data_out = data_out_r; + +endmodule // sync_ram_sp_nochange + + module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) (input wire clk, write_enable, input wire [DATA_WIDTH-1:0] data_in, @@ -112,6 +136,62 @@ module sync_ram_sdp_wrr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10, SHIFT_VAL=1) endmodule // sync_ram_sdp_wrr +module double_sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10, USE_TDP=0) +( + input wire write_enable_a, clk_a, + input wire [DATA_WIDTH-1:0] data_in_a, + input wire [ADDRESS_WIDTH-1:0] address_in_a, + output wire [DATA_WIDTH-1:0] data_out_a, + + input wire write_enable_b, clk_b, + input wire [DATA_WIDTH-1:0] data_in_b, + input wire [ADDRESS_WIDTH-1:0] address_in_b, + output wire [DATA_WIDTH-1:0] data_out_b +); + + generate + if (USE_TDP) begin + + sync_ram_tdp #( + .DATA_WIDTH(DATA_WIDTH), + .ADDRESS_WIDTH(ADDRESS_WIDTH+1) + ) ram ( + .clk_a(clk_a), .clk_b(clk_b), + .write_enable_a(write_enable_a), .write_enable_b(write_enable_b), + .write_data_a(data_in_a), .write_data_b(data_in_b), + .addr_a({1'b0, address_in_a}), .addr_b({1'b1, address_in_b}), + .read_data_a(data_out_a), .read_data_b(data_out_b) + ); + + end else begin + + sync_ram_sp #( + .DATA_WIDTH(DATA_WIDTH), + .ADDRESS_WIDTH(ADDRESS_WIDTH) + ) a_ram ( + .write_enable(write_enable_a), + .clk(clk_a), + .data_in(data_in_a), + .address_in(address_in_a), + .data_out(data_out_a) + ); + + sync_ram_sp #( + .DATA_WIDTH(DATA_WIDTH), + .ADDRESS_WIDTH(ADDRESS_WIDTH) + ) b_ram ( + .write_enable(write_enable_b), + .clk(clk_b), + .data_in(data_in_b), + .address_in(address_in_b), + .data_out(data_out_b) + ); + end + endgenerate + +endmodule // double_sync_ram_sp + + module double_sync_ram_sdp #(parameter DATA_WIDTH_A=8, ADDRESS_WIDTH_A=10, DATA_WIDTH_B=8, ADDRESS_WIDTH_B=10) ( input wire write_enable_a, clk_a, From 3592d42d3b156f33b6138cb53aaf710209024a68 Mon Sep 17 00:00:00 2001 From: Lofty Date: Mon, 20 Oct 2025 18:23:25 +0100 Subject: [PATCH 275/291] analogdevices: ignore $assert cells --- techlibs/analogdevices/synth_analogdevices.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc index 8a41408c8..abb95ea33 100644 --- a/techlibs/analogdevices/synth_analogdevices.cc +++ b/techlibs/analogdevices/synth_analogdevices.cc @@ -506,7 +506,7 @@ struct SynthAnalogDevicesPass : public ScriptPass if (check_label("edif")) { if (!edif_file.empty() || help_mode) { - run("delete t:$scopeinfo"); + run("delete t:$assert t:$scopeinfo"); run(stringf("write_edif %s", edif_file.c_str())); } } From 241db706e197ef3fa8c5ce6ea9a00769ed98caf2 Mon Sep 17 00:00:00 2001 From: Lofty Date: Tue, 21 Oct 2025 18:04:01 +0100 Subject: [PATCH 276/291] analogdevices: double LUT RAM cost --- techlibs/analogdevices/lutrams.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/techlibs/analogdevices/lutrams.txt b/techlibs/analogdevices/lutrams.txt index a52c28171..c391cdb43 100644 --- a/techlibs/analogdevices/lutrams.txt +++ b/techlibs/analogdevices/lutrams.txt @@ -8,12 +8,12 @@ ram distributed $__ANALOGDEVICES_LUTRAM_ { clock posedge; } option "MODE" "SP" { - option "SIZE" 32 cost 1; + option "SIZE" 32 cost 2; option "SIZE" 64 cost 2; } option "MODE" "DP" { - option "SIZE" 32 cost 2; - option "SIZE" 64 cost 4; + option "SIZE" 32 cost 4; + option "SIZE" 64 cost 8; port ar "R" { } } From cd60dd49120b407f2650d9d1dbf2c5b2a6f787ef Mon Sep 17 00:00:00 2001 From: Lofty Date: Mon, 10 Nov 2025 13:19:12 +0000 Subject: [PATCH 277/291] synth_analogdevices: update timing model and tests --- techlibs/analogdevices/cells_sim.v | 271 ++++++++++-------- tests/arch/analogdevices/abc9_dff.ys | 142 --------- tests/arch/analogdevices/add_sub.ys | 4 +- tests/arch/analogdevices/adffs.ys | 16 +- tests/arch/analogdevices/asym_ram_sdp.ys | 16 +- .../analogdevices/asym_ram_sdp_read_wider.v | 1 + .../analogdevices/asym_ram_sdp_write_wider.v | 1 + tests/arch/analogdevices/attributes_test.ys | 12 +- tests/arch/analogdevices/blockram.ys | 26 +- tests/arch/analogdevices/bug1460.ys | 4 +- tests/arch/analogdevices/bug1605.ys | 19 -- tests/arch/analogdevices/bug3670.v | 13 - tests/arch/analogdevices/bug3670.ys | 3 - tests/arch/analogdevices/counter.ys | 6 +- tests/arch/analogdevices/dffs.ys | 12 +- tests/arch/analogdevices/dsp_abc9.ys | 22 +- tests/arch/analogdevices/fsm.ys | 5 +- tests/arch/analogdevices/logic.ys | 4 +- tests/arch/analogdevices/lutram.ys | 8 +- tests/arch/analogdevices/macc.sh | 6 - tests/arch/analogdevices/macc.v | 84 ------ tests/arch/analogdevices/macc.ys | 32 --- tests/arch/analogdevices/macc_tb.v | 96 ------- tests/arch/analogdevices/mul_unsigned.ys | 7 +- tests/arch/analogdevices/mux.ys | 4 +- tests/arch/analogdevices/shifter.ys | 3 +- tests/arch/analogdevices/tribuf.ys | 13 - 27 files changed, 213 insertions(+), 617 deletions(-) delete mode 100644 tests/arch/analogdevices/abc9_dff.ys delete mode 100644 tests/arch/analogdevices/bug1605.ys delete mode 100644 tests/arch/analogdevices/bug3670.v delete mode 100644 tests/arch/analogdevices/bug3670.ys delete mode 100644 tests/arch/analogdevices/macc.sh delete mode 100644 tests/arch/analogdevices/macc.v delete mode 100644 tests/arch/analogdevices/macc.ys delete mode 100644 tests/arch/analogdevices/macc_tb.v delete mode 100644 tests/arch/analogdevices/tribuf.ys diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v index 402c421fa..505a2e07a 100644 --- a/techlibs/analogdevices/cells_sim.v +++ b/techlibs/analogdevices/cells_sim.v @@ -471,15 +471,15 @@ module FFRE ( input R ); parameter [0:0] INIT = 1'b0; - initial Q <= INIT; + initial Q = INIT; always @(posedge C) if (R) Q <= 1'b0; else if (CE) Q <= D; `ifdef IS_T16FFC specify $setup(D , posedge C, 31); $setup(CE, posedge C, 122); $setup(R , posedge C, 128); - if (R) (posedge C => (Q : 1'b0)) = 280; - if (!R && CE) (posedge C => (Q : D)) = 280; + if (R) (posedge C => (Q : 1'b0)) = 224; + if (!R && CE) (posedge C => (Q : D)) = 224; endspecify `endif `ifdef IS_T40LP @@ -487,10 +487,8 @@ module FFRE ( $setup(D , posedge C, 119); $setup(CE, posedge C, 385); $setup(R , posedge C, 565); - // HACK: no clock-to-Q timings; using FFCE timing - if (R) (posedge C => (Q : 1'b0)) = 689; - // HACK: no clock-to-Q timings; using FFCE timing - if (!R && CE) (posedge C => (Q : D)) = 689; + if (R) (posedge C => (Q : 1'b0)) = 672; + if (!R && CE) (posedge C => (Q : D)) = 672; endspecify `endif endmodule @@ -505,15 +503,15 @@ module FFRE_N ( input R ); parameter [0:0] INIT = 1'b0; - initial Q <= INIT; + initial Q = INIT; always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D; `ifdef IS_T16FFC specify $setup(D , negedge C, 31); $setup(CE, negedge C, 122); $setup(R , negedge C, 128); - if (R) (negedge C => (Q : 1'b0)) = 280; - if (!R && CE) (negedge C => (Q : D)) = 280; + if (R) (negedge C => (Q : 1'b0)) = 224; + if (!R && CE) (negedge C => (Q : D)) = 224; endspecify `endif `ifdef IS_T40LP @@ -521,14 +519,13 @@ module FFRE_N ( $setup(D , negedge C, 119); $setup(CE, negedge C, 385); $setup(R , negedge C, 565); - // HACK: no clock-to-Q timings; using FFCE timing - if (R) (negedge C => (Q : 1'b0)) = 689; - // HACK: no clock-to-Q timings; using FFCE timing - if (!R && CE) (negedge C => (Q : D)) = 689; + if (R) (negedge C => (Q : 1'b0)) = 672; + if (!R && CE) (negedge C => (Q : D)) = 672; endspecify `endif endmodule +(* abc9_flop, lib_whitebox *) module FFSE ( output reg Q, (* clkbuf_sink *) @@ -538,30 +535,29 @@ module FFSE ( input S ); parameter [0:0] INIT = 1'b1; - initial Q <= INIT; + initial Q = INIT; always @(posedge C) if (S) Q <= 1'b1; else if (CE) Q <= D; `ifdef IS_T16FFC specify $setup(D , posedge C, 31); $setup(CE, posedge C, 122); $setup(S , posedge C, 128); - if (S) (negedge C => (Q : 1'b1)) = 280; - if (!S && CE) (posedge C => (Q : D)) = 280; + if (S) (posedge C => (Q : 1'b1)) = 224; + if (!S && CE) (posedge C => (Q : D)) = 224; endspecify `endif `ifdef IS_T40LP specify $setup(D , posedge C, 119); $setup(CE, posedge C, 385); - $setup(S , posedge C, 584); - // HACK: no clock-to-Q timings; using FFCE timing - if (S) (negedge C => (Q : 1'b1)) = 689; - // HACK: no clock-to-Q timings; using FFCE timing - if (!S && CE) (posedge C => (Q : D)) = 689; + $setup(S , posedge C, 565); + if (S) (posedge C => (Q : 1'b1)) = 672; + if (!S && CE) (posedge C => (Q : D)) = 672; endspecify `endif endmodule +(* abc9_flop, lib_whitebox *) module FFSE_N ( output reg Q, (* clkbuf_sink *) @@ -571,30 +567,29 @@ module FFSE_N ( input S ); parameter [0:0] INIT = 1'b1; - initial Q <= INIT; + initial Q = INIT; always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D; `ifdef IS_T16FFC specify $setup(D , negedge C, 31); $setup(CE, negedge C, 122); $setup(S , negedge C, 128); - if (S) (negedge C => (Q : 1'b1)) = 280; - if (!S && CE) (negedge C => (Q : D)) = 280; + if (S) (negedge C => (Q : 1'b1)) = 224; + if (!S && CE) (negedge C => (Q : D)) = 224; endspecify `endif `ifdef IS_T40LP specify $setup(D , negedge C, 119); $setup(CE, negedge C, 385); - $setup(S , negedge C, 584); - // HACK: no clock-to-Q timings; using FFCE timing - if (S) (negedge C => (Q : 1'b1)) = 689; - // HACK: no clock-to-Q timings; using FFCE timing - if (!S && CE) (negedge C => (Q : D)) = 689; + $setup(S , negedge C, 565); + if (S) (negedge C => (Q : 1'b1)) = 672; + if (!S && CE) (negedge C => (Q : D)) = 672; endspecify `endif endmodule +(* abc9_box, lib_whitebox *) module FFCE ( output reg Q, (* clkbuf_sink *) @@ -604,24 +599,33 @@ module FFCE ( input D ); parameter [0:0] INIT = 1'b0; - initial Q <= INIT; + initial Q = INIT; always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D; `ifdef IS_T16FFC specify $setup(D , posedge C, 31); $setup(CE, posedge C, 122); + $setup(CLR, posedge C, 0 /* missing? */); if (!CLR && CE) (posedge C => (Q : D)) = 280; +`ifdef YOSYS + if (CLR) (CLR => Q) = 0 /* missing? */; +`endif endspecify `endif `ifdef IS_T40LP specify $setup(D , posedge C, 119); $setup(CE, posedge C, 385); + $setup(CLR, posedge C, 0 /* missing? */); if (!CLR && CE) (posedge C => (Q : D)) = 689; +`ifdef YOSYS + if (CLR) (CLR => Q) = 0 /* missing? */; +`endif endspecify `endif endmodule +(* abc9_box, lib_whitebox *) module FFCE_N ( output reg Q, (* clkbuf_sink *) @@ -631,20 +635,28 @@ module FFCE_N ( input D ); parameter [0:0] INIT = 1'b0; - initial Q <= INIT; + initial Q = INIT; always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D; `ifdef IS_T16FFC specify - $setup(D , negedge C, 31); - $setup(CE, negedge C, 122); + $setup(D, negedge C, 31); + $setup(CE, negedge C, 122); + $setup(CLR, negedge C, 0 /* missing? */); if (!CLR && CE) (negedge C => (Q : D)) = 280; +`ifdef YOSYS + if (CLR) (CLR => Q) = 0 /* missing? */; +`endif endspecify `endif `ifdef IS_T40LP specify - $setup(D , negedge C, 119); - $setup(CE, negedge C, 385); + $setup(D, negedge C, 119); + $setup(CE, negedge C, 385); + $setup(CLR, negedge C, 0 /* missing? */); if (!CLR && CE) (negedge C => (Q : D)) = 689; +`ifdef YOSYS + if (CLR) (CLR => Q) = 0 /* missing? */; +`endif endspecify `endif endmodule @@ -658,21 +670,28 @@ module FFPE ( input D ); parameter [0:0] INIT = 1'b1; - initial Q <= INIT; + initial Q = INIT; always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D; `ifdef IS_T16FFC specify - $setup(D , posedge C, 31); - $setup(CE, posedge C, 122); - if (!PRE && CE) (posedge C => (Q : D)) = 291; + $setup(D, posedge C, 31); + $setup(CE, posedge C, 122); + $setup(PRE, posedge C, 0 /* missing? */); + if (!PRE && CE) (posedge C => (Q : D)) = 224; +`ifdef YOSYS + if (PRE) (PRE => Q) = 0 /* missing? */; +`endif endspecify `endif `ifdef IS_T40LP specify - $setup(D , posedge C, 119); - $setup(CE, posedge C, 385); - // HACK: no clock-to-Q timings; using FFPE_N timing - if (!PRE && CE) (posedge C => (Q : D)) = 712; + $setup(D, posedge C, 119); + $setup(CE, posedge C, 385); + $setup(PRE, posedge C, 0 /* missing? */); + if (!PRE && CE) (posedge C => (Q : D)) = 672; +`ifdef YOSYS + if (PRE) (PRE => Q) = 0 /* missing? */; +`endif endspecify `endif endmodule @@ -686,22 +705,28 @@ module FFPE_N ( input D ); parameter [0:0] INIT = 1'b1; - initial Q <= INIT; + initial Q = INIT; always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; `ifdef IS_T16FFC specify - $setup(D , negedge C, 31); - $setup(CE , negedge C, 122); + $setup(D, negedge C, 28); + $setup(CE, negedge C, 28); + $setup(PRE, negedge C, 28); if (!PRE && CE) (negedge C => (Q : D)) = 291; +`ifdef YOSYS + if (PRE) (PRE => Q) = 57; +`endif endspecify `endif `ifdef IS_T40LP specify - // HACK: no D setup time; using FFPE timing - $setup(D , negedge C, 119); - // HACK: no CE setup time; using FFPE timing - $setup(CE, negedge C, 385); + $setup(D, negedge C, 84); + $setup(CE, negedge C, 84); + $setup(PRE, negedge C, 84); if (!PRE && CE) (negedge C => (Q : D)) = 712; +`ifdef YOSYS + if (PRE) (PRE => Q) = 57; +`endif endspecify `endif endmodule @@ -726,14 +751,13 @@ module RAMS32X1 ( always @(posedge WCLK) if (WE) mem[a] <= D; `ifdef IS_T16FFC specify - // HACK: no setup timing - $setup(A0, posedge WCLK, 0); - $setup(A1, posedge WCLK, 0); - $setup(A2, posedge WCLK, 0); - $setup(A3, posedge WCLK, 0); - $setup(A4, posedge WCLK, 0); - $setup(D, posedge WCLK, 0); - $setup(WE, posedge WCLK, 0); + $setup(A0, posedge WCLK, 28); + $setup(A1, posedge WCLK, 28); + $setup(A2, posedge WCLK, 28); + $setup(A3, posedge WCLK, 28); + $setup(A4, posedge WCLK, 28); + $setup(D, posedge WCLK, 28); + $setup(WE, posedge WCLK, 28); (A0 => O) = 63; (A1 => O) = 63; (A2 => O) = 63; @@ -744,14 +768,13 @@ module RAMS32X1 ( `endif `ifdef IS_T40LP specify - // HACK: no setup timing - $setup(A0, posedge WCLK, 0); - $setup(A1, posedge WCLK, 0); - $setup(A2, posedge WCLK, 0); - $setup(A3, posedge WCLK, 0); - $setup(A4, posedge WCLK, 0); - $setup(D, posedge WCLK, 0); - $setup(WE, posedge WCLK, 0); + $setup(A0, posedge WCLK, 84); + $setup(A1, posedge WCLK, 84); + $setup(A2, posedge WCLK, 84); + $setup(A3, posedge WCLK, 84); + $setup(A4, posedge WCLK, 84); + $setup(D, posedge WCLK, 84); + $setup(WE, posedge WCLK, 84); (A0 => O) = 168; (A1 => O) = 168; (A2 => O) = 168; @@ -778,15 +801,14 @@ module RAMS64X1 ( always @(posedge WCLK) if (WE) mem[a] <= D; `ifdef IS_T16FFC specify - // HACK: no setup timing - $setup(A0, posedge WCLK, 0); - $setup(A1, posedge WCLK, 0); - $setup(A2, posedge WCLK, 0); - $setup(A3, posedge WCLK, 0); - $setup(A4, posedge WCLK, 0); - $setup(A5, posedge WCLK, 0); - $setup(D, posedge WCLK, 0); - $setup(WE, posedge WCLK, 0); + $setup(A0, posedge WCLK, 28); + $setup(A1, posedge WCLK, 28); + $setup(A2, posedge WCLK, 28); + $setup(A3, posedge WCLK, 28); + $setup(A4, posedge WCLK, 28); + $setup(A5, posedge WCLK, 28); + $setup(D, posedge WCLK, 28); + $setup(WE, posedge WCLK, 28); (A0 => O) = 161; (A1 => O) = 161; (A2 => O) = 161; @@ -798,15 +820,14 @@ module RAMS64X1 ( `endif `ifdef IS_T40LP specify - // HACK: no setup timing - $setup(A0, posedge WCLK, 0); - $setup(A1, posedge WCLK, 0); - $setup(A2, posedge WCLK, 0); - $setup(A3, posedge WCLK, 0); - $setup(A4, posedge WCLK, 0); - $setup(A5, posedge WCLK, 0); - $setup(D, posedge WCLK, 0); - $setup(WE, posedge WCLK, 0); + $setup(A0, posedge WCLK, 84); + $setup(A1, posedge WCLK, 84); + $setup(A2, posedge WCLK, 84); + $setup(A3, posedge WCLK, 84); + $setup(A4, posedge WCLK, 84); + $setup(A5, posedge WCLK, 84); + $setup(D, posedge WCLK, 84); + $setup(WE, posedge WCLK, 84); (A0 => O) = 466; (A1 => O) = 466; (A2 => O) = 466; @@ -832,26 +853,26 @@ module RAMD32X1 ( ); parameter INIT = 32'h0; wire [4:0] a = {A4, A3, A2, A1, A0}; - wire [4:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}; + wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}; reg [31:0] mem = INIT; assign SPO = mem[a]; assign DPO = mem[dpra]; always @(posedge WCLK) if (WE) mem[a] <= D; `ifdef IS_T16FFC specify - // HACK: no setup timing - $setup(A0, posedge WCLK, 0); - $setup(A1, posedge WCLK, 0); - $setup(A2, posedge WCLK, 0); - $setup(A3, posedge WCLK, 0); - $setup(A4, posedge WCLK, 0); + // HACK: partial setup timing + $setup(A0, posedge WCLK, 28); + $setup(A1, posedge WCLK, 28); + $setup(A2, posedge WCLK, 28); + $setup(A3, posedge WCLK, 28); + $setup(A4, posedge WCLK, 28); $setup(DPRA0, posedge WCLK, 0); $setup(DPRA1, posedge WCLK, 0); $setup(DPRA2, posedge WCLK, 0); $setup(DPRA3, posedge WCLK, 0); $setup(DPRA4, posedge WCLK, 0); - $setup(D, posedge WCLK, 0); - $setup(WE, posedge WCLK, 0); + $setup(D, posedge WCLK, 28); + $setup(WE, posedge WCLK, 28); // HACK: No timing arcs for SPO; using ones for DPO // (are we meant to use the single-port timings here?) (A0 => SPO) = 66; @@ -870,19 +891,19 @@ module RAMD32X1 ( `endif `ifdef IS_T40LP specify - // HACK: no setup timing - $setup(A0, posedge WCLK, 0); - $setup(A1, posedge WCLK, 0); - $setup(A2, posedge WCLK, 0); - $setup(A3, posedge WCLK, 0); - $setup(A4, posedge WCLK, 0); + // HACK: partial setup timing + $setup(A0, posedge WCLK, 84); + $setup(A1, posedge WCLK, 84); + $setup(A2, posedge WCLK, 84); + $setup(A3, posedge WCLK, 84); + $setup(A4, posedge WCLK, 84); $setup(DPRA0, posedge WCLK, 0); $setup(DPRA1, posedge WCLK, 0); $setup(DPRA2, posedge WCLK, 0); $setup(DPRA3, posedge WCLK, 0); $setup(DPRA4, posedge WCLK, 0); - $setup(D, posedge WCLK, 0); - $setup(WE, posedge WCLK, 0); + $setup(D, posedge WCLK, 84); + $setup(WE, posedge WCLK, 84); // HACK: No timing arcs for SPO; using ones for DPO // (are we meant to use the single-port timings here?) (A0 => SPO) = 142; @@ -920,21 +941,21 @@ module RAMD64X1 ( always @(posedge WCLK) if (WE) mem[a] <= D; `ifdef IS_T16FFC specify - // HACK: no setup timing - $setup(A0, posedge WCLK, 0); - $setup(A1, posedge WCLK, 0); - $setup(A2, posedge WCLK, 0); - $setup(A3, posedge WCLK, 0); - $setup(A4, posedge WCLK, 0); - $setup(A5, posedge WCLK, 0); + // HACK: partial setup timing + $setup(A0, posedge WCLK, 28); + $setup(A1, posedge WCLK, 28); + $setup(A2, posedge WCLK, 28); + $setup(A3, posedge WCLK, 28); + $setup(A4, posedge WCLK, 28); + $setup(A5, posedge WCLK, 28); $setup(DPRA0, posedge WCLK, 0); $setup(DPRA1, posedge WCLK, 0); $setup(DPRA2, posedge WCLK, 0); $setup(DPRA3, posedge WCLK, 0); $setup(DPRA4, posedge WCLK, 0); $setup(DPRA5, posedge WCLK, 0); - $setup(D, posedge WCLK, 0); - $setup(WE, posedge WCLK, 0); + $setup(D, posedge WCLK, 28); + $setup(WE, posedge WCLK, 28); (A0 => SPO) = 161; (A1 => SPO) = 161; (A2 => SPO) = 161; @@ -953,21 +974,21 @@ module RAMD64X1 ( `endif `ifdef IS_T40LP specify - // HACK: no setup timing - $setup(A0, posedge WCLK, 0); - $setup(A1, posedge WCLK, 0); - $setup(A2, posedge WCLK, 0); - $setup(A3, posedge WCLK, 0); - $setup(A4, posedge WCLK, 0); - $setup(A5, posedge WCLK, 0); + // HACK: partial setup timing + $setup(A0, posedge WCLK, 84); + $setup(A1, posedge WCLK, 84); + $setup(A2, posedge WCLK, 84); + $setup(A3, posedge WCLK, 84); + $setup(A4, posedge WCLK, 84); + $setup(A5, posedge WCLK, 84); $setup(DPRA0, posedge WCLK, 0); $setup(DPRA1, posedge WCLK, 0); $setup(DPRA2, posedge WCLK, 0); $setup(DPRA3, posedge WCLK, 0); $setup(DPRA4, posedge WCLK, 0); $setup(DPRA5, posedge WCLK, 0); - $setup(D, posedge WCLK, 0); - $setup(WE, posedge WCLK, 0); + $setup(D, posedge WCLK, 84); + $setup(WE, posedge WCLK, 84); (A0 => SPO) = 466; (A1 => SPO) = 466; (A2 => SPO) = 466; @@ -1091,7 +1112,7 @@ parameter FF_SYNC_RST = 1'b0; specify if (!REG_A) (A *> P) = 1000; if (!REG_B) (B *> P) = 1000; - if (!REG_D[0]) (D *> P) = 1000; + if (!REG_D) (D *> P) = 1000; endspecify // Much of this functionality is TODO. @@ -1112,7 +1133,7 @@ module RBRAM #( parameter DATA_WIDTH = 40, parameter ADDR_WIDTH = 12, parameter WE_WIDTH = 20, - parameter PERR_WIDTH = 4, + parameter PERR_WIDTH = 4 ) ( output [DATA_WIDTH-1:0] QA, input [DATA_WIDTH-1:0] DA, @@ -1137,7 +1158,7 @@ module RBRAM #( output MBEA, output MBEB, input SLP, - input PD, + input PD ); endmodule @@ -1152,7 +1173,7 @@ module RBRAM2 #( parameter DATA_WIDTH = 40, parameter ADDR_WIDTH = 13, parameter WE_WIDTH = 20, - parameter PERR_WIDTH = 4, + parameter PERR_WIDTH = 4 ) ( output [DATA_WIDTH-1:0] QA, input [DATA_WIDTH-1:0] DA, @@ -1177,7 +1198,7 @@ module RBRAM2 #( output MBEA, output MBEB, input SLP, - input PD, + input PD ); endmodule diff --git a/tests/arch/analogdevices/abc9_dff.ys b/tests/arch/analogdevices/abc9_dff.ys deleted file mode 100644 index 891330726..000000000 --- a/tests/arch/analogdevices/abc9_dff.ys +++ /dev/null @@ -1,142 +0,0 @@ -logger -nowarn "Yosys has only limited support for tri-state logic at the moment\. .*" -logger -nowarn "Ignoring boxed module .*\." - -read_verilog < RAMB18E1 +# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RBRAM2 # w4b | r16b design -reset read_verilog asym_ram_sdp_read_wider.v synth_analogdevices -top asym_ram_sdp_read_wider -noiopad -select -assert-count 1 t:RAMB18E1 +select -assert-count 1 t:RBRAM2 # w8b | r16b design -reset read_verilog asym_ram_sdp_read_wider.v chparam -set WIDTHA 8 -set SIZEA 512 -set ADDRWIDTHA 9 asym_ram_sdp_read_wider synth_analogdevices -top asym_ram_sdp_read_wider -noiopad -select -assert-count 1 t:RAMB18E1 +select -assert-count 1 t:RBRAM2 # w4b | r32b design -reset read_verilog asym_ram_sdp_read_wider.v chparam -set WIDTHB 32 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider synth_analogdevices -top asym_ram_sdp_read_wider -noiopad -select -assert-count 1 t:RAMB18E1 +select -assert-count 2 t:RBRAM2 # w16b | r4b design -reset read_verilog asym_ram_sdp_write_wider.v synth_analogdevices -top asym_ram_sdp_write_wider -noiopad -select -assert-count 1 t:RAMB18E1 +select -assert-count 1 t:RBRAM2 # w16b | r8b design -reset read_verilog asym_ram_sdp_write_wider.v chparam -set WIDTHB 8 -set SIZEB 512 -set ADDRWIDTHB 9 asym_ram_sdp_read_wider synth_analogdevices -top asym_ram_sdp_write_wider -noiopad -select -assert-count 1 t:RAMB18E1 +select -assert-count 1 t:RBRAM2 # w32b | r4b design -reset read_verilog asym_ram_sdp_write_wider.v chparam -set WIDTHA 32 -set SIZEA 128 -set ADDRWIDTHA 7 asym_ram_sdp_read_wider synth_analogdevices -top asym_ram_sdp_write_wider -noiopad -select -assert-count 1 t:RAMB18E1 +select -assert-count 1 t:RBRAM2 # w4b | r24b design -reset @@ -46,5 +46,5 @@ read_verilog asym_ram_sdp_read_wider.v chparam -set SIZEA 768 chparam -set WIDTHB 24 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider synth_analogdevices -top asym_ram_sdp_read_wider -noiopad -select -assert-count 1 t:RAMB18E1 +select -assert-count 2 t:RBRAM2 diff --git a/tests/arch/analogdevices/asym_ram_sdp_read_wider.v b/tests/arch/analogdevices/asym_ram_sdp_read_wider.v index 8743209e3..183b0cf4f 100644 --- a/tests/arch/analogdevices/asym_ram_sdp_read_wider.v +++ b/tests/arch/analogdevices/asym_ram_sdp_read_wider.v @@ -46,6 +46,7 @@ module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA, localparam RATIO = maxWIDTH / minWIDTH; localparam log2RATIO = log2(RATIO); + (* ram_style="block" *) reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; reg [WIDTHB-1:0] readB; diff --git a/tests/arch/analogdevices/asym_ram_sdp_write_wider.v b/tests/arch/analogdevices/asym_ram_sdp_write_wider.v index cd61a3ccc..df817894f 100644 --- a/tests/arch/analogdevices/asym_ram_sdp_write_wider.v +++ b/tests/arch/analogdevices/asym_ram_sdp_write_wider.v @@ -46,6 +46,7 @@ module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA, localparam RATIO = maxWIDTH / minWIDTH; localparam log2RATIO = log2(RATIO); + (* ram_style="block" *) reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; reg [WIDTHB-1:0] readB; diff --git a/tests/arch/analogdevices/attributes_test.ys b/tests/arch/analogdevices/attributes_test.ys index 8d55d96fd..03d6decff 100644 --- a/tests/arch/analogdevices/attributes_test.ys +++ b/tests/arch/analogdevices/attributes_test.ys @@ -3,7 +3,7 @@ read_verilog ../common/memory_attributes/attributes_test.v hierarchy -top block_ram synth_analogdevices -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module -select -assert-count 1 t:RAMB18E1 +# select -assert-count 1 t:RBRAM2 # This currently infers LUTRAM because BRAM is expensive. # Check that distributed memory without parameters is not modified design -reset @@ -11,7 +11,8 @@ read_verilog ../common/memory_attributes/attributes_test.v hierarchy -top distributed_ram synth_analogdevices -top distributed_ram -noiopad cd distributed_ram # Constrain all select calls below inside the top module -select -assert-count 1 t:RAM32M +select -assert-count 8 t:RAMS64X1 +select -assert-count 8 t:FFRE # Set ram_style distributed to blockram memory; will be implemented as distributed design -reset @@ -19,7 +20,8 @@ read_verilog ../common/memory_attributes/attributes_test.v setattr -set ram_style "distributed" block_ram/m:* synth_analogdevices -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module -select -assert-count 64 t:RAM64X1S +select -assert-count 64 t:RAMS64X1 +select -assert-count 4 t:FFRE # Set synthesis, logic_block to blockram memory; will be implemented as distributed design -reset @@ -27,11 +29,11 @@ read_verilog ../common/memory_attributes/attributes_test.v setattr -set logic_block 1 block_ram/m:* synth_analogdevices -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module -select -assert-count 0 t:RAMB18E1 +select -assert-count 0 t:RBRAM2 # Set ram_style block to a distributed memory; will be implemented as blockram design -reset read_verilog ../common/memory_attributes/attributes_test.v synth_analogdevices -top distributed_ram_manual -noiopad cd distributed_ram_manual # Constrain all select calls below inside the top module -select -assert-count 1 t:RAMB18E1 +# select -assert-count 1 t:RBRAM2 # This gets implemented in logic instead diff --git a/tests/arch/analogdevices/blockram.ys b/tests/arch/analogdevices/blockram.ys index 26d5634ba..f6efa5ba8 100644 --- a/tests/arch/analogdevices/blockram.ys +++ b/tests/arch/analogdevices/blockram.ys @@ -1,32 +1,35 @@ ### TODO: Not running equivalence checking because BRAM models does not exists ### currently. Checking instance counts instead. -# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 +# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RBRAM2 read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 12 -set DATA_WIDTH 1 sync_ram_sdp +setattr -set ram_style "block" sync_ram_sdp synth_analogdevices -top sync_ram_sdp -noiopad cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 +select -assert-count 1 t:RBRAM2 design -reset read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp +setattr -set ram_style "block" sync_ram_sdp synth_analogdevices -top sync_ram_sdp -noiopad cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 +select -assert-count 1 t:RBRAM2 design -reset read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp +setattr -set ram_style "block" sync_ram_sdp synth_analogdevices -top sync_ram_sdp -noiopad cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 +select -assert-count 1 t:RBRAM2 design -reset read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp synth_analogdevices -top sync_ram_sdp -noiopad cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 +select -assert-count 1 t:RBRAM2 # Anything memory bits < 1024 -> LUTRAM design -reset @@ -34,8 +37,9 @@ read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp synth_analogdevices -top sync_ram_sdp -noiopad cd sync_ram_sdp -select -assert-count 0 t:RAMB18E1 -select -assert-count 4 t:RAM64M +select -assert-count 0 t:RBRAM2 +select -assert-count 8 t:RAMD64X1 +select -assert-count 2 t:FFRE # More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 design -reset @@ -43,7 +47,7 @@ read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp synth_analogdevices -top sync_ram_sdp -noiopad cd sync_ram_sdp -select -assert-count 1 t:RAMB36E1 +select -assert-count 1 t:RBRAM2 ### With parameters @@ -54,7 +58,7 @@ hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 setattr -set ram_style "block" m:memory synth_analogdevices -top sync_ram_sdp -noiopad cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 +select -assert-count 1 t:RBRAM2 design -reset read_verilog ../common/blockram.v @@ -62,7 +66,7 @@ hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 setattr -set logic_block 1 m:memory synth_analogdevices -top sync_ram_sdp -noiopad cd sync_ram_sdp -select -assert-count 0 t:RAMB18E1 +select -assert-count 0 t:RBRAM2 design -reset read_verilog ../common/blockram.v @@ -70,4 +74,4 @@ hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1 setattr -set ram_style "block" m:memory synth_analogdevices -top sync_ram_sdp -noiopad cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 +select -assert-count 1 t:RBRAM2 diff --git a/tests/arch/analogdevices/bug1460.ys b/tests/arch/analogdevices/bug1460.ys index d00292c19..66fb96a5b 100644 --- a/tests/arch/analogdevices/bug1460.ys +++ b/tests/arch/analogdevices/bug1460.ys @@ -30,5 +30,5 @@ EOT synth_analogdevices -noiopad cd register_file -select -assert-count 33 t:RAM32M -select -assert-none t:* t:BUFG %d t:RAM32M %d +select -assert-count 192 t:RAMD32X1 +select -assert-none t:RAMD32X1 %% t:* %D diff --git a/tests/arch/analogdevices/bug1605.ys b/tests/arch/analogdevices/bug1605.ys deleted file mode 100644 index d3d793718..000000000 --- a/tests/arch/analogdevices/bug1605.ys +++ /dev/null @@ -1,19 +0,0 @@ -read_verilog <= 2**(SIZEOUT-1)) | overflow_reg; - -// Output accumulation result -assign accum_out = overflow ? 2**(SIZEOUT-1)-1 : adder_out; - -endmodule diff --git a/tests/arch/analogdevices/macc.ys b/tests/arch/analogdevices/macc.ys deleted file mode 100644 index 79b330016..000000000 --- a/tests/arch/analogdevices/macc.ys +++ /dev/null @@ -1,32 +0,0 @@ -read_verilog macc.v -design -save read - -hierarchy -top macc -proc -#equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad ### TODO -equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -seq 3 -show-inputs -show-outputs miter -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd macc # Constrain all select calls below inside the top module -select -assert-count 1 t:BUFG -select -assert-count 1 t:FFRE -select -assert-count 1 t:DSP48E1 -select -assert-none t:BUFG t:FFRE t:DSP48E1 %% t:* %D - -design -load read -hierarchy -top macc2 -proc -#equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad ### TODO -equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -seq 4 -show-inputs -show-outputs miter -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd macc2 # Constrain all select calls below inside the top module - -select -assert-count 1 t:BUFG -select -assert-count 1 t:DSP48E1 -select -assert-count 1 t:FFRE -select -assert-count 1 t:LUT2 -select -assert-count 40 t:LUT3 -select -assert-none t:BUFG t:DSP48E1 t:FFRE t:LUT2 t:LUT3 %% t:* %D diff --git a/tests/arch/analogdevices/macc_tb.v b/tests/arch/analogdevices/macc_tb.v deleted file mode 100644 index 64aed05c4..000000000 --- a/tests/arch/analogdevices/macc_tb.v +++ /dev/null @@ -1,96 +0,0 @@ -`timescale 1ns / 1ps - -module testbench; - - parameter SIZEIN = 16, SIZEOUT = 40; - reg clk, ce, rst; - reg signed [SIZEIN-1:0] a, b; - output signed [SIZEOUT-1:0] REF_accum_out, accum_out; - output REF_overflow, overflow; - - integer errcount = 0; - - reg ERROR_FLAG = 0; - - task clkcycle; - begin - #5; - clk = ~clk; - #10; - clk = ~clk; - #2; - ERROR_FLAG = 0; - if (REF_accum_out !== accum_out) begin - $display("ERROR at %1t: REF_accum_out=%b UUT_accum_out=%b DIFF=%b", $time, REF_accum_out, accum_out, REF_accum_out ^ accum_out); - errcount = errcount + 1; - ERROR_FLAG = 1; - end - if (REF_overflow !== overflow) begin - $display("ERROR at %1t: REF_overflow=%b UUT_overflow=%b DIFF=%b", $time, REF_overflow, overflow, REF_overflow ^ overflow); - errcount = errcount + 1; - ERROR_FLAG = 1; - end - #3; - end - endtask - - initial begin - //$dumpfile("test_macc.vcd"); - //$dumpvars(0, testbench); - - #2; - clk = 1'b0; - ce = 1'b0; - a = 0; - b = 0; - - rst = 1'b1; - repeat (10) begin - #10; - clk = 1'b1; - #10; - clk = 1'b0; - #10; - clk = 1'b1; - #10; - clk = 1'b0; - end - rst = 1'b0; - - repeat (10000) begin - clkcycle; - ce = 1; //$urandom & $urandom; - //rst = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom; - a = $urandom & ~(1 << (SIZEIN-1)); - b = $urandom & ~(1 << (SIZEIN-1)); - end - - if (errcount == 0) begin - $display("All tests passed."); - $finish; - end else begin - $display("Caught %1d errors.", errcount); - $stop; - end - end - - macc2 ref ( - .clk(clk), - .ce(ce), - .rst(rst), - .a(a), - .b(b), - .accum_out(REF_accum_out), - .overflow(REF_overflow) - ); - - macc2_uut uut ( - .clk(clk), - .ce(ce), - .rst(rst), - .a(a), - .b(b), - .accum_out(accum_out), - .overflow(overflow) - ); -endmodule diff --git a/tests/arch/analogdevices/mul_unsigned.ys b/tests/arch/analogdevices/mul_unsigned.ys index 99a0a3f0d..5bdbdaac4 100644 --- a/tests/arch/analogdevices/mul_unsigned.ys +++ b/tests/arch/analogdevices/mul_unsigned.ys @@ -5,7 +5,6 @@ proc equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mul_unsigned # Constrain all select calls below inside the top module -select -assert-count 1 t:BUFG -select -assert-count 1 t:DSP48E1 -select -assert-count 30 t:FFRE -select -assert-none t:DSP48E1 t:FFRE t:BUFG %% t:* %D +select -assert-count 1 t:RBBDSP +select -assert-count 75 t:FFRE +select -assert-none t:RBBDSP t:FFRE %% t:* %D diff --git a/tests/arch/analogdevices/mux.ys b/tests/arch/analogdevices/mux.ys index 579519ce5..375ce90f2 100644 --- a/tests/arch/analogdevices/mux.ys +++ b/tests/arch/analogdevices/mux.ys @@ -44,7 +44,7 @@ select -assert-max 2 t:LUT3 select -assert-max 2 t:LUT4 select -assert-min 4 t:LUT6 select -assert-max 7 t:LUT6 -select -assert-max 2 t:MUXF7 +select -assert-max 2 t:LUTMUX7 dump -select -assert-none t:LUT6 t:LUT4 t:LUT3 t:MUXF7 %% t:* %D +select -assert-none t:LUT6 t:LUT4 t:LUT3 t:LUTMUX7 %% t:* %D diff --git a/tests/arch/analogdevices/shifter.ys b/tests/arch/analogdevices/shifter.ys index 6eab4bee5..3cd67cb93 100644 --- a/tests/arch/analogdevices/shifter.ys +++ b/tests/arch/analogdevices/shifter.ys @@ -6,6 +6,5 @@ equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:BUFG select -assert-count 8 t:FFRE -select -assert-none t:BUFG t:FFRE %% t:* %D +select -assert-none t:FFRE %% t:* %D diff --git a/tests/arch/analogdevices/tribuf.ys b/tests/arch/analogdevices/tribuf.ys deleted file mode 100644 index 0be9f8d6f..000000000 --- a/tests/arch/analogdevices/tribuf.ys +++ /dev/null @@ -1,13 +0,0 @@ -read_verilog ../common/tribuf.v -hierarchy -top tristate -proc -tribuf -flatten -synth -equiv_opt -assert -map +/analogdevices/cells_sim.v -map +/simcells.v synth_analogdevices # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd tristate # Constrain all select calls below inside the top module -select -assert-count 2 t:INBUF -select -assert-count 1 t:INV -select -assert-count 1 t:OBUFT -select -assert-none t:INBUF t:INV t:OBUFT %% t:* %D From 709746b184c4ab65b0c8d23d98aaf880fcf5c350 Mon Sep 17 00:00:00 2001 From: Lofty Date: Mon, 5 Jan 2026 10:27:46 +0000 Subject: [PATCH 278/291] analogdevices: update T16FFC timings --- techlibs/analogdevices/cells_sim.v | 441 ++++++++++++++--------------- 1 file changed, 219 insertions(+), 222 deletions(-) diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v index 505a2e07a..bb2e8bd70 100644 --- a/techlibs/analogdevices/cells_sim.v +++ b/techlibs/analogdevices/cells_sim.v @@ -38,7 +38,7 @@ module INBUF( assign O = I; `ifdef IS_T16FFC specify - (I => O) = 22; + (I => O) = 42; endspecify `endif `ifdef IS_T40LP @@ -59,7 +59,7 @@ module OUTBUF( assign O = I; `ifdef IS_T16FFC specify - (I => O) = 22; + (I => O) = 42; endspecify `endif `ifdef IS_T40LP @@ -75,7 +75,7 @@ module LUT1(output O, input I0); assign O = I0 ? INIT[1] : INIT[0]; `ifdef IS_T16FFC specify - (I0 => O) = 22; + (I0 => O) = 42; endspecify `endif `ifdef IS_T40LP @@ -92,8 +92,8 @@ module LUT2(output O, input I0, I1); assign O = I0 ? s1[1] : s1[0]; `ifdef IS_T16FFC specify - (I0 => O) = 22; - (I1 => O) = 22; + (I0 => O) = 42; + (I1 => O) = 39; endspecify `endif `ifdef IS_T40LP @@ -112,9 +112,9 @@ module LUT3(output O, input I0, I1, I2); assign O = I0 ? s1[1] : s1[0]; `ifdef IS_T16FFC specify - (I0 => O) = 22; - (I1 => O) = 22; - (I2 => O) = 22; + (I0 => O) = 54; + (I1 => O) = 51; + (I2 => O) = 48; endspecify `endif `ifdef IS_T40LP @@ -135,10 +135,10 @@ module LUT4(output O, input I0, I1, I2, I3); assign O = I0 ? s1[1] : s1[0]; `ifdef IS_T16FFC specify - (I0 => O) = 22; - (I1 => O) = 22; - (I2 => O) = 22; - (I3 => O) = 22; + (I0 => O) = 96; + (I1 => O) = 87; + (I2 => O) = 79; + (I3 => O) = 71; endspecify `endif `ifdef IS_T40LP @@ -161,11 +161,11 @@ module LUT5(output O, input I0, I1, I2, I3, I4); assign O = I0 ? s1[1] : s1[0]; `ifdef IS_T16FFC specify - (I0 => O) = 22; - (I1 => O) = 22; - (I2 => O) = 22; - (I3 => O) = 22; - (I4 => O) = 22; + (I0 => O) = 99; + (I1 => O) = 90; + (I2 => O) = 82; + (I3 => O) = 74; + (I4 => O) = 66; endspecify `endif `ifdef IS_T40LP @@ -190,12 +190,12 @@ module LUT6(output O, input I0, I1, I2, I3, I4, I5); assign O = I0 ? s1[1] : s1[0]; `ifdef IS_T16FFC specify - (I0 => O) = 22; - (I1 => O) = 22; - (I2 => O) = 22; - (I3 => O) = 22; - (I4 => O) = 22; - (I5 => O) = 22; + (I0 => O) = 42; + (I1 => O) = 39; + (I2 => O) = 36; + (I3 => O) = 33; + (I4 => O) = 30; + (I5 => O) = 28; endspecify `endif `ifdef IS_T40LP @@ -233,13 +233,13 @@ module \$__ABC9_LUT7 (output O, input I0, I1, I2, I3, I4, I5, I6); `ifndef __ICARUS__ `ifdef IS_T16FFC specify - (I0 => O) = 22 + 63 /* LUTMUX7.I1 */; - (I1 => O) = 22 + 63 /* LUTMUX7.I1 */; - (I2 => O) = 22 + 63 /* LUTMUX7.I1 */; - (I3 => O) = 22 + 63 /* LUTMUX7.I1 */; - (I4 => O) = 22 + 63 /* LUTMUX7.I1 */; - (I5 => O) = 22 + 63 /* LUTMUX7.I1 */; - (I6 => O) = 0 + 51 /* LUTMUX7.S */; + (I0 => O) = 42 + 111 /* LUTMUX7.I1 */; + (I1 => O) = 39 + 111 /* LUTMUX7.I1 */; + (I2 => O) = 36 + 111 /* LUTMUX7.I1 */; + (I3 => O) = 33 + 111 /* LUTMUX7.I1 */; + (I4 => O) = 30 + 111 /* LUTMUX7.I1 */; + (I5 => O) = 28 + 111 /* LUTMUX7.I1 */; + (I6 => O) = 0 + 57 /* LUTMUX7.S */; endspecify `endif `ifdef IS_T40LP @@ -263,14 +263,14 @@ module \$__ABC9_LUT8 (output O, input I0, I1, I2, I3, I4, I5, I6, I7); `ifndef __ICARUS__ `ifdef IS_T16FFC specify - (I0 => O) = 22 + 63 /* LUTMUX7.I1 */ + 48 /* LUTMUX8.I0 */; - (I1 => O) = 22 + 63 /* LUTMUX7.I1 */ + 48 /* LUTMUX8.I0 */; - (I2 => O) = 22 + 63 /* LUTMUX7.I1 */ + 48 /* LUTMUX8.I0 */; - (I3 => O) = 22 + 63 /* LUTMUX7.I1 */ + 48 /* LUTMUX8.I0 */; - (I4 => O) = 22 + 63 /* LUTMUX7.I1 */ + 48 /* LUTMUX8.I0 */; - (I5 => O) = 22 + 63 /* LUTMUX7.I1 */ + 48 /* LUTMUX8.I0 */; - (I6 => O) = 0 + 51 /* LUTMUX7.S */ + 48 /* LUTMUX8.I0 */; - (I7 => O) = 0 + 0 + 58 /* LUTMUX8.S */; + (I0 => O) = 42 + 111 /* LUTMUX7.I1 */ + 59 /* LUTMUX8.I0 */; + (I1 => O) = 39 + 111 /* LUTMUX7.I1 */ + 59 /* LUTMUX8.I0 */; + (I2 => O) = 36 + 111 /* LUTMUX7.I1 */ + 59 /* LUTMUX8.I0 */; + (I3 => O) = 33 + 111 /* LUTMUX7.I1 */ + 59 /* LUTMUX8.I0 */; + (I4 => O) = 30 + 111 /* LUTMUX7.I1 */ + 59 /* LUTMUX8.I0 */; + (I5 => O) = 28 + 111 /* LUTMUX7.I1 */ + 59 /* LUTMUX8.I0 */; + (I6 => O) = 0 + 57 /* LUTMUX7.S */ + 59 /* LUTMUX8.I0 */; + (I7 => O) = 0 + 0 + 60 /* LUTMUX8.S */; endspecify `endif `ifdef IS_T40LP @@ -293,9 +293,9 @@ module LUTMUX7(output O, input I0, I1, S); assign O = S ? I1 : I0; `ifdef IS_T16FFC specify - (I0 => O) = 62; - (I1 => O) = 63; - (S => O) = 51; + (I0 => O) = 95; + (I1 => O) = 111; + (S => O) = 57; endspecify `endif `ifdef IS_T40LP @@ -312,9 +312,9 @@ module LUTMUX8(output O, input I0, I1, S); assign O = S ? I1 : I0; `ifdef IS_T16FFC specify - (I0 => O) = 48; - (I1 => O) = 46; - (S => O) = 58; + (I0 => O) = 59; + (I1 => O) = 59; + (S => O) = 60; endspecify `endif `ifdef IS_T40LP @@ -343,50 +343,58 @@ module CRY4( assign CO[3] = S[3] ? CO[2] : DI[3]; `ifdef IS_T16FFC specify - (S[0] => O[0]) = 39; - (CI => O[0]) = 43; - (DI[0] => O[1]) = 81; - (S[0] => O[1]) = 61; - (S[1] => O[1]) = 42; - (CI => O[1]) = 50; - (DI[0] => O[2]) = 98; - (DI[1] => O[2]) = 95; - (S[0] => O[2]) = 70; - (S[1] => O[2]) = 75; - (S[2] => O[2]) = 48; - (CI => O[2]) = 64; - (DI[0] => O[3]) = 101; - (DI[1] => O[3]) = 120; - (DI[2] => O[3]) = 65; - (S[0] => O[3]) = 69; - (S[1] => O[3]) = 91; - (S[2] => O[3]) = 42; - (S[3] => O[3]) = 39; - (CI => O[3]) = 84; - (DI[0] => CO[0]) = 59; - (S[0] => CO[0]) = 43; - (CI => CO[0]) = 50; - (DI[0] => CO[1]) = 87; - (DI[1] => CO[1]) = 64; - (S[0] => CO[1]) = 63; - (S[1] => CO[1]) = 51; - (CI => CO[1]) = 55; - (DI[0] => CO[2]) = 103; - (DI[1] => CO[2]) = 113; - (DI[2] => CO[2]) = 58; - (S[0] => CO[2]) = 68; - (S[1] => CO[2]) = 79; - (S[2] => CO[2]) = 37; - (CI => CO[2]) = 77; - (DI[0] => CO[3]) = 93; - (DI[1] => CO[3]) = 95; - (DI[2] => CO[3]) = 84; - (DI[3] => CO[3]) = 72; - (S[0] => CO[3]) = 91; - (S[1] => CO[3]) = 97; - (S[2] => CO[3]) = 82; - (S[3] => CO[3]) = 81; + (CI => CO[0]) = 69; + (DI[0] => CO[0]) = 74; + (S[0] => CO[0]) = 76; + + (CI => CO[1]) = 76; + (DI[0] => CO[1]) = 109; + (DI[1] => CO[1]) = 69; + (S[0] => CO[1]) = 99; + (S[1] => CO[1]) = 59; + + (CI => CO[2]) = 144; + (DI[0] => CO[2]) = 155; + (DI[1] => CO[2]) = 126; + (DI[2] => CO[2]) = 63; + (S[0] => CO[2]) = 168; + (S[1] => CO[2]) = 117; + (S[2] => CO[2]) = 50; + (CI => CO[3]) = 20; + (DI[0] => CO[3]) = 167; + (DI[1] => CO[3]) = 181; + (DI[2] => CO[3]) = 173; + (DI[3] => CO[3]) = 77; + (S[0] => CO[3]) = 185; + (S[1] => CO[3]) = 182; + (S[2] => CO[3]) = 159; + (S[3] => CO[3]) = 179; + + (CI => O[0]) = 50; + (S[0] => O[0]) = 82; + + (CI => O[1]) = 61; + (DI[0] => O[1]) = 117; + (S[0] => O[1]) = 132; + (S[1] => O[1]) = 49; + + (CI => O[2]) = 148; + (DI[0] => O[2]) = 196; + (DI[1] => O[2]) = 130; + (S[0] => O[2]) = 218; + (S[1] => O[2]) = 145; + (S[2] => O[2]) = 65; + + (CI => O[3]) = 132; + (DI[0] => O[3]) = 208; + (DI[1] => O[3]) = 148; + (DI[2] => O[3]) = 110; + (S[0] => O[3]) = 204; + (S[1] => O[3]) = 160; + (S[2] => O[3]) = 97; + (S[3] => O[3]) = 39; + endspecify `endif `ifdef IS_T40LP @@ -449,7 +457,7 @@ module CRY4INIT( assign CO = CYINIT; `ifdef IS_T16FFC specify - (CYINIT => CO) = 72; + (CYINIT => CO) = 77; endspecify `endif `ifdef IS_T40LP @@ -475,11 +483,11 @@ module FFRE ( always @(posedge C) if (R) Q <= 1'b0; else if (CE) Q <= D; `ifdef IS_T16FFC specify - $setup(D , posedge C, 31); - $setup(CE, posedge C, 122); - $setup(R , posedge C, 128); - if (R) (posedge C => (Q : 1'b0)) = 224; - if (!R && CE) (posedge C => (Q : D)) = 224; + $setup(D , posedge C, 65); + $setup(CE, posedge C, 63); + $setup(R , posedge C, 63); + if (R) (posedge C => (Q : 1'b0)) = 291; + if (!R && CE) (posedge C => (Q : D)) = 291; endspecify `endif `ifdef IS_T40LP @@ -507,11 +515,11 @@ module FFRE_N ( always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D; `ifdef IS_T16FFC specify - $setup(D , negedge C, 31); - $setup(CE, negedge C, 122); - $setup(R , negedge C, 128); - if (R) (negedge C => (Q : 1'b0)) = 224; - if (!R && CE) (negedge C => (Q : D)) = 224; + $setup(D , negedge C, 65); + $setup(CE, negedge C, 63); + $setup(R , negedge C, 63); + if (R) (negedge C => (Q : 1'b0)) = 291; + if (!R && CE) (negedge C => (Q : D)) = 291; endspecify `endif `ifdef IS_T40LP @@ -539,11 +547,11 @@ module FFSE ( always @(posedge C) if (S) Q <= 1'b1; else if (CE) Q <= D; `ifdef IS_T16FFC specify - $setup(D , posedge C, 31); - $setup(CE, posedge C, 122); - $setup(S , posedge C, 128); - if (S) (posedge C => (Q : 1'b1)) = 224; - if (!S && CE) (posedge C => (Q : D)) = 224; + $setup(D , posedge C, 65); + $setup(CE, posedge C, 63); + $setup(S , posedge C, 63); + if (S) (posedge C => (Q : 1'b1)) = 265; + if (!S && CE) (posedge C => (Q : D)) = 265; endspecify `endif `ifdef IS_T40LP @@ -571,11 +579,11 @@ module FFSE_N ( always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D; `ifdef IS_T16FFC specify - $setup(D , negedge C, 31); - $setup(CE, negedge C, 122); - $setup(S , negedge C, 128); - if (S) (negedge C => (Q : 1'b1)) = 224; - if (!S && CE) (negedge C => (Q : D)) = 224; + $setup(D , negedge C, 65); + $setup(CE, negedge C, 63); + $setup(S , negedge C, 63); + if (S) (negedge C => (Q : 1'b1)) = 265; + if (!S && CE) (negedge C => (Q : D)) = 265; endspecify `endif `ifdef IS_T40LP @@ -603,12 +611,12 @@ module FFCE ( always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D; `ifdef IS_T16FFC specify - $setup(D , posedge C, 31); - $setup(CE, posedge C, 122); - $setup(CLR, posedge C, 0 /* missing? */); - if (!CLR && CE) (posedge C => (Q : D)) = 280; + $setup(D , posedge C, 65); + $setup(CE, posedge C, 64); + $setup(CLR, posedge C, 64); + if (!CLR && CE) (posedge C => (Q : D)) = 192; `ifdef YOSYS - if (CLR) (CLR => Q) = 0 /* missing? */; + if (CLR) (CLR => Q) = 192; `endif endspecify `endif @@ -639,12 +647,12 @@ module FFCE_N ( always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D; `ifdef IS_T16FFC specify - $setup(D, negedge C, 31); - $setup(CE, negedge C, 122); - $setup(CLR, negedge C, 0 /* missing? */); - if (!CLR && CE) (negedge C => (Q : D)) = 280; + $setup(D, negedge C, 65); + $setup(CE, negedge C, 64); + $setup(CLR, negedge C, 64); + if (!CLR && CE) (negedge C => (Q : D)) = 192; `ifdef YOSYS - if (CLR) (CLR => Q) = 0 /* missing? */; + if (CLR) (CLR => Q) = 192; `endif endspecify `endif @@ -674,12 +682,12 @@ module FFPE ( always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D; `ifdef IS_T16FFC specify - $setup(D, posedge C, 31); - $setup(CE, posedge C, 122); - $setup(PRE, posedge C, 0 /* missing? */); - if (!PRE && CE) (posedge C => (Q : D)) = 224; + $setup(D, posedge C, 65); + $setup(CE, posedge C, 65); + $setup(PRE, posedge C, 65); + if (!PRE && CE) (posedge C => (Q : D)) = 191; `ifdef YOSYS - if (PRE) (PRE => Q) = 0 /* missing? */; + if (PRE) (PRE => Q) = 191; `endif endspecify `endif @@ -709,12 +717,12 @@ module FFPE_N ( always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; `ifdef IS_T16FFC specify - $setup(D, negedge C, 28); - $setup(CE, negedge C, 28); - $setup(PRE, negedge C, 28); + $setup(D, negedge C, 64); + $setup(CE, negedge C, 64); + $setup(PRE, negedge C, 64); if (!PRE && CE) (negedge C => (Q : D)) = 291; `ifdef YOSYS - if (PRE) (PRE => Q) = 57; + if (PRE) (PRE => Q) = 333; `endif endspecify `endif @@ -751,19 +759,19 @@ module RAMS32X1 ( always @(posedge WCLK) if (WE) mem[a] <= D; `ifdef IS_T16FFC specify - $setup(A0, posedge WCLK, 28); - $setup(A1, posedge WCLK, 28); - $setup(A2, posedge WCLK, 28); - $setup(A3, posedge WCLK, 28); - $setup(A4, posedge WCLK, 28); - $setup(D, posedge WCLK, 28); - $setup(WE, posedge WCLK, 28); - (A0 => O) = 63; - (A1 => O) = 63; - (A2 => O) = 63; - (A3 => O) = 63; - (A4 => O) = 63; - (posedge WCLK => (O : D)) = 813; + $setup(A0, posedge WCLK, 62); + $setup(A1, posedge WCLK, 62); + $setup(A2, posedge WCLK, 62); + $setup(A3, posedge WCLK, 62); + $setup(A4, posedge WCLK, 62); + $setup(D, posedge WCLK, 62); + $setup(WE, posedge WCLK, 62); + (A0 => O) = 100; + (A1 => O) = 91; + (A2 => O) = 83; + (A3 => O) = 75; + (A4 => O) = 67; + (posedge WCLK => (O : D)) = 807; endspecify `endif `ifdef IS_T40LP @@ -801,21 +809,21 @@ module RAMS64X1 ( always @(posedge WCLK) if (WE) mem[a] <= D; `ifdef IS_T16FFC specify - $setup(A0, posedge WCLK, 28); - $setup(A1, posedge WCLK, 28); - $setup(A2, posedge WCLK, 28); - $setup(A3, posedge WCLK, 28); - $setup(A4, posedge WCLK, 28); - $setup(A5, posedge WCLK, 28); - $setup(D, posedge WCLK, 28); - $setup(WE, posedge WCLK, 28); - (A0 => O) = 161; - (A1 => O) = 161; - (A2 => O) = 161; - (A3 => O) = 161; - (A4 => O) = 161; - (A5 => O) = 64; - (posedge WCLK => (O : D)) = 762; + $setup(A0, posedge WCLK, 65); + $setup(A1, posedge WCLK, 65); + $setup(A2, posedge WCLK, 65); + $setup(A3, posedge WCLK, 65); + $setup(A4, posedge WCLK, 65); + $setup(A5, posedge WCLK, 65); + $setup(D, posedge WCLK, 65); + $setup(WE, posedge WCLK, 65); + (A0 => O) = 184; + (A1 => O) = 175; + (A2 => O) = 167; + (A3 => O) = 159; + (A4 => O) = 151; + (A5 => O) = 61; + (posedge WCLK => (O : D)) = 747; endspecify `endif `ifdef IS_T40LP @@ -860,33 +868,25 @@ module RAMD32X1 ( always @(posedge WCLK) if (WE) mem[a] <= D; `ifdef IS_T16FFC specify - // HACK: partial setup timing - $setup(A0, posedge WCLK, 28); - $setup(A1, posedge WCLK, 28); - $setup(A2, posedge WCLK, 28); - $setup(A3, posedge WCLK, 28); - $setup(A4, posedge WCLK, 28); - $setup(DPRA0, posedge WCLK, 0); - $setup(DPRA1, posedge WCLK, 0); - $setup(DPRA2, posedge WCLK, 0); - $setup(DPRA3, posedge WCLK, 0); - $setup(DPRA4, posedge WCLK, 0); - $setup(D, posedge WCLK, 28); - $setup(WE, posedge WCLK, 28); - // HACK: No timing arcs for SPO; using ones for DPO - // (are we meant to use the single-port timings here?) - (A0 => SPO) = 66; - (A1 => SPO) = 66; - (A2 => SPO) = 66; - (A3 => SPO) = 66; - (A4 => SPO) = 66; - (DPRA0 => DPO) = 66; - (DPRA1 => DPO) = 66; - (DPRA2 => DPO) = 66; - (DPRA3 => DPO) = 66; - (DPRA4 => DPO) = 66; - (posedge WCLK => (SPO : D)) = 813; - (posedge WCLK => (DPO : D)) = 813; + $setup(A0, posedge WCLK, 62); + $setup(A1, posedge WCLK, 62); + $setup(A2, posedge WCLK, 62); + $setup(A3, posedge WCLK, 62); + $setup(A4, posedge WCLK, 62); + $setup(D, posedge WCLK, 62); + $setup(WE, posedge WCLK, 62); + (A0 => SPO) = 100; + (A1 => SPO) = 91; + (A2 => SPO) = 83; + (A3 => SPO) = 75; + (A4 => SPO) = 67; + (DPRA0 => DPO) = 101; + (DPRA1 => DPO) = 92; + (DPRA2 => DPO) = 84; + (DPRA3 => DPO) = 76; + (DPRA4 => DPO) = 68; + (posedge WCLK => (SPO : D)) = 807; + (posedge WCLK => (DPO : D)) = 807; endspecify `endif `ifdef IS_T40LP @@ -897,11 +897,6 @@ module RAMD32X1 ( $setup(A2, posedge WCLK, 84); $setup(A3, posedge WCLK, 84); $setup(A4, posedge WCLK, 84); - $setup(DPRA0, posedge WCLK, 0); - $setup(DPRA1, posedge WCLK, 0); - $setup(DPRA2, posedge WCLK, 0); - $setup(DPRA3, posedge WCLK, 0); - $setup(DPRA4, posedge WCLK, 0); $setup(D, posedge WCLK, 84); $setup(WE, posedge WCLK, 84); // HACK: No timing arcs for SPO; using ones for DPO @@ -941,35 +936,28 @@ module RAMD64X1 ( always @(posedge WCLK) if (WE) mem[a] <= D; `ifdef IS_T16FFC specify - // HACK: partial setup timing - $setup(A0, posedge WCLK, 28); - $setup(A1, posedge WCLK, 28); - $setup(A2, posedge WCLK, 28); - $setup(A3, posedge WCLK, 28); - $setup(A4, posedge WCLK, 28); - $setup(A5, posedge WCLK, 28); - $setup(DPRA0, posedge WCLK, 0); - $setup(DPRA1, posedge WCLK, 0); - $setup(DPRA2, posedge WCLK, 0); - $setup(DPRA3, posedge WCLK, 0); - $setup(DPRA4, posedge WCLK, 0); - $setup(DPRA5, posedge WCLK, 0); - $setup(D, posedge WCLK, 28); - $setup(WE, posedge WCLK, 28); - (A0 => SPO) = 161; - (A1 => SPO) = 161; - (A2 => SPO) = 161; - (A3 => SPO) = 161; - (A4 => SPO) = 161; - (A5 => SPO) = 64; - (DPRA0 => DPO) = 118; - (DPRA1 => DPO) = 118; - (DPRA2 => DPO) = 118; - (DPRA3 => DPO) = 118; - (DPRA4 => DPO) = 118; - (DPRA5 => DPO) = 63; - (posedge WCLK => (SPO : D)) = 762; - (posedge WCLK => (DPO : D)) = 737; + $setup(A0, posedge WCLK, 65); + $setup(A1, posedge WCLK, 65); + $setup(A2, posedge WCLK, 65); + $setup(A3, posedge WCLK, 65); + $setup(A4, posedge WCLK, 65); + $setup(A5, posedge WCLK, 65); + $setup(D, posedge WCLK, 65); + $setup(WE, posedge WCLK, 65); + (A0 => SPO) = 184; + (A1 => SPO) = 175; + (A2 => SPO) = 167; + (A3 => SPO) = 159; + (A4 => SPO) = 151; + (A5 => SPO) = 61; + (DPRA0 => DPO) = 164; + (DPRA1 => DPO) = 155; + (DPRA2 => DPO) = 147; + (DPRA3 => DPO) = 139; + (DPRA4 => DPO) = 131; + (DPRA5 => DPO) = 64; + (posedge WCLK => (SPO : D)) = 761; + (posedge WCLK => (DPO : D)) = 733; endspecify `endif `ifdef IS_T40LP @@ -981,12 +969,6 @@ module RAMD64X1 ( $setup(A3, posedge WCLK, 84); $setup(A4, posedge WCLK, 84); $setup(A5, posedge WCLK, 84); - $setup(DPRA0, posedge WCLK, 0); - $setup(DPRA1, posedge WCLK, 0); - $setup(DPRA2, posedge WCLK, 0); - $setup(DPRA3, posedge WCLK, 0); - $setup(DPRA4, posedge WCLK, 0); - $setup(DPRA5, posedge WCLK, 0); $setup(D, posedge WCLK, 84); $setup(WE, posedge WCLK, 84); (A0 => SPO) = 466; @@ -1163,6 +1145,7 @@ module RBRAM #( endmodule +(* lib_whitebox *) module RBRAM2 #( parameter TARGET_NODE = "T16FFC_Gen2.4", parameter BRAM_MODE = "SDP_2048x40", @@ -1201,4 +1184,18 @@ module RBRAM2 #( input PD ); +// Timings simplified for now +specify + $setup(DA, posedge CLKA, 2440); + $setup(CEA, posedge CLKA, 1668); + $setup(AA, posedge CLKA, 2289); + + $setup(DB, posedge CLKB, 2420); + $setup(CEB, posedge CLKB, 1805); + $setup(AB, posedge CLKB, 2170); + + (posedge CLKA => (QA : DA)) = 2227; + (posedge CLKB => (QB : DB)) = 2189; +endspecify + endmodule From 91740645a94944ebc1d1aa323ce9f8afbab9587d Mon Sep 17 00:00:00 2001 From: Lofty Date: Mon, 5 Jan 2026 14:45:54 +0000 Subject: [PATCH 279/291] analogdevices: update T40LP timings --- techlibs/analogdevices/cells_sim.v | 299 +++++++++++++++-------------- 1 file changed, 157 insertions(+), 142 deletions(-) diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v index bb2e8bd70..85ab06b7e 100644 --- a/techlibs/analogdevices/cells_sim.v +++ b/techlibs/analogdevices/cells_sim.v @@ -43,7 +43,7 @@ module INBUF( `endif `ifdef IS_T40LP specify - (I => O) = 121; + (I => O) = 187; endspecify `endif endmodule @@ -64,7 +64,7 @@ module OUTBUF( `endif `ifdef IS_T40LP specify - (I => O) = 121; + (I => O) = 187; endspecify `endif endmodule @@ -394,55 +394,61 @@ module CRY4( (S[1] => O[3]) = 160; (S[2] => O[3]) = 97; (S[3] => O[3]) = 39; - endspecify `endif `ifdef IS_T40LP specify - (S[0] => O[0]) = 128; - (CI => O[0]) = 122; - (DI[0] => O[1]) = 268; - (S[0] => O[1]) = 256; - (S[1] => O[1]) = 141; - (CI => O[1]) = 173; - (DI[0] => O[2]) = 344; - (DI[1] => O[2]) = 320; - (S[0] => O[2]) = 271; - (S[1] => O[2]) = 225; - (S[2] => O[2]) = 129; - (CI => O[2]) = 223; - (DI[0] => O[3]) = 371; - (DI[1] => O[3]) = 383; - (DI[2] => O[3]) = 327; - (S[0] => O[3]) = 342; - (S[1] => O[3]) = 327; - (S[2] => O[3]) = 273; - (S[3] => O[3]) = 145; - (CI => O[3]) = 301; - (DI[0] => CO[0]) = 243; - (S[0] => CO[0]) = 136; - (CI => CO[0]) = 119; - (DI[0] => CO[1]) = 242; - (DI[1] => CO[1]) = 251; - (S[0] => CO[1]) = 220; - (S[1] => CO[1]) = 159; - (CI => CO[1]) = 155; - (DI[0] => CO[2]) = 275; - (DI[1] => CO[2]) = 241; - (DI[2] => CO[2]) = 231; - (S[0] => CO[2]) = 238; - (S[1] => CO[2]) = 197; - (S[2] => CO[2]) = 167; - (CI => CO[2]) = 197; - (DI[0] => CO[3]) = 294; - (DI[1] => CO[3]) = 303; - (DI[2] => CO[3]) = 317; + (CI => CO[0]) = 132; + (DI[0] => CO[0]) = 245; + (S[0] => CO[0]) = 218; + + (CI => CO[1]) = 183; + (DI[0] => CO[1]) = 261; + (DI[1] => CO[1]) = 325; + (S[0] => CO[1]) = 270; + (S[1] => CO[1]) = 199; + + (CI => CO[2]) = 218; + (DI[0] => CO[2]) = 284; + (DI[1] => CO[2]) = 345; + (DI[2] => CO[2]) = 242; + (S[0] => CO[2]) = 334; + (S[1] => CO[2]) = 271; + (S[2] => CO[2]) = 228; + + (CI => CO[3]) = 258; + (DI[0] => CO[3]) = 334; + (DI[1] => CO[3]) = 395; + (DI[2] => CO[3]) = 342; (DI[3] => CO[3]) = 205; - (S[0] => CO[3]) = 250; - (S[1] => CO[3]) = 292; - (S[2] => CO[3]) = 231; - (S[3] => CO[3]) = 178; - (CI => CO[3]) = 229; + (S[0] => CO[3]) = 382; + (S[1] => CO[3]) = 321; + (S[2] => CO[3]) = 324; + (S[3] => CO[3]) = 252; + + (CI => O[0]) = 123; + (S[0] => O[0]) = 150; + + (CI => O[1]) = 265; + (DI[0] => O[1]) = 331; + (S[0] => O[1]) = 292; + (S[1] => O[1]) = 151; + + (CI => O[2]) = 288; + (DI[0] => O[2]) = 371; + (DI[1] => O[2]) = 407; + (S[0] => O[2]) = 391; + (S[1] => O[2]) = 314; + (S[2] => O[2]) = 144; + + (CI => O[3]) = 313; + (DI[0] => O[3]) = 388; + (DI[1] => O[3]) = 432; + (DI[2] => O[3]) = 335; + (S[0] => O[3]) = 418; + (S[1] => O[3]) = 357; + (S[2] => O[3]) = 331; + (S[3] => O[3]) = 145; endspecify `endif endmodule @@ -492,11 +498,11 @@ module FFRE ( `endif `ifdef IS_T40LP specify - $setup(D , posedge C, 119); - $setup(CE, posedge C, 385); - $setup(R , posedge C, 565); - if (R) (posedge C => (Q : 1'b0)) = 672; - if (!R && CE) (posedge C => (Q : D)) = 672; + $setup(D , posedge C, 144); + $setup(CE, posedge C, 412); + $setup(R , posedge C, 667); + if (R) (posedge C => (Q : 1'b0)) = 712; + if (!R && CE) (posedge C => (Q : D)) = 712; endspecify `endif endmodule @@ -524,11 +530,11 @@ module FFRE_N ( `endif `ifdef IS_T40LP specify - $setup(D , negedge C, 119); - $setup(CE, negedge C, 385); - $setup(R , negedge C, 565); - if (R) (negedge C => (Q : 1'b0)) = 672; - if (!R && CE) (negedge C => (Q : D)) = 672; + $setup(D , negedge C, 144); + $setup(CE, negedge C, 412); + $setup(R , negedge C, 667); + if (R) (negedge C => (Q : 1'b0)) = 712; + if (!R && CE) (negedge C => (Q : D)) = 712; endspecify `endif endmodule @@ -622,12 +628,12 @@ module FFCE ( `endif `ifdef IS_T40LP specify - $setup(D , posedge C, 119); - $setup(CE, posedge C, 385); - $setup(CLR, posedge C, 0 /* missing? */); - if (!CLR && CE) (posedge C => (Q : D)) = 689; + $setup(D , posedge C, 140); + $setup(CE, posedge C, 412); + $setup(CLR, posedge C, 6); + if (!CLR && CE) (posedge C => (Q : D)) = 55; `ifdef YOSYS - if (CLR) (CLR => Q) = 0 /* missing? */; + if (CLR) (CLR => Q) = 55; `endif endspecify `endif @@ -658,12 +664,12 @@ module FFCE_N ( `endif `ifdef IS_T40LP specify - $setup(D, negedge C, 119); - $setup(CE, negedge C, 385); - $setup(CLR, negedge C, 0 /* missing? */); - if (!CLR && CE) (negedge C => (Q : D)) = 689; + $setup(D, negedge C, 140); + $setup(CE, negedge C, 412); + $setup(CLR, negedge C, 6); + if (!CLR && CE) (negedge C => (Q : D)) = 55; `ifdef YOSYS - if (CLR) (CLR => Q) = 0 /* missing? */; + if (CLR) (CLR => Q) = 55; `endif endspecify `endif @@ -693,12 +699,12 @@ module FFPE ( `endif `ifdef IS_T40LP specify - $setup(D, posedge C, 119); - $setup(CE, posedge C, 385); - $setup(PRE, posedge C, 0 /* missing? */); - if (!PRE && CE) (posedge C => (Q : D)) = 672; + $setup(D, posedge C, 140); + $setup(CE, posedge C, 412); + $setup(PRE, posedge C, 6); + if (!PRE && CE) (posedge C => (Q : D)) = 55; `ifdef YOSYS - if (PRE) (PRE => Q) = 0 /* missing? */; + if (PRE) (PRE => Q) = 55; `endif endspecify `endif @@ -728,9 +734,9 @@ module FFPE_N ( `endif `ifdef IS_T40LP specify - $setup(D, negedge C, 84); - $setup(CE, negedge C, 84); - $setup(PRE, negedge C, 84); + $setup(D, negedge C, 89); + $setup(CE, negedge C, 89); + $setup(PRE, negedge C, 89); if (!PRE && CE) (negedge C => (Q : D)) = 712; `ifdef YOSYS if (PRE) (PRE => Q) = 57; @@ -776,18 +782,18 @@ module RAMS32X1 ( `endif `ifdef IS_T40LP specify - $setup(A0, posedge WCLK, 84); - $setup(A1, posedge WCLK, 84); - $setup(A2, posedge WCLK, 84); - $setup(A3, posedge WCLK, 84); - $setup(A4, posedge WCLK, 84); - $setup(D, posedge WCLK, 84); - $setup(WE, posedge WCLK, 84); - (A0 => O) = 168; - (A1 => O) = 168; - (A2 => O) = 168; - (A3 => O) = 168; - (A4 => O) = 168; + $setup(A0, posedge WCLK, 198); + $setup(A1, posedge WCLK, 198); + $setup(A2, posedge WCLK, 198); + $setup(A3, posedge WCLK, 198); + $setup(A4, posedge WCLK, 198); + $setup(D, posedge WCLK, 198); + $setup(WE, posedge WCLK, 198); + (A0 => O) = 211; + (A1 => O) = 202; + (A2 => O) = 193; + (A3 => O) = 185; + (A4 => O) = 176; (posedge WCLK => (O : D)) = 1586; endspecify `endif @@ -828,19 +834,19 @@ module RAMS64X1 ( `endif `ifdef IS_T40LP specify - $setup(A0, posedge WCLK, 84); - $setup(A1, posedge WCLK, 84); - $setup(A2, posedge WCLK, 84); - $setup(A3, posedge WCLK, 84); - $setup(A4, posedge WCLK, 84); - $setup(A5, posedge WCLK, 84); - $setup(D, posedge WCLK, 84); - $setup(WE, posedge WCLK, 84); - (A0 => O) = 466; - (A1 => O) = 466; - (A2 => O) = 466; - (A3 => O) = 466; - (A4 => O) = 466; + $setup(A0, posedge WCLK, 224); + $setup(A1, posedge WCLK, 224); + $setup(A2, posedge WCLK, 224); + $setup(A3, posedge WCLK, 224); + $setup(A4, posedge WCLK, 224); + $setup(A5, posedge WCLK, 224); + $setup(D, posedge WCLK, 224); + $setup(WE, posedge WCLK, 224); + (A0 => O) = 509; + (A1 => O) = 500; + (A2 => O) = 491; + (A3 => O) = 483; + (A4 => O) = 474; (A5 => O) = 187; (posedge WCLK => (O : D)) = 1730; endspecify @@ -891,26 +897,23 @@ module RAMD32X1 ( `endif `ifdef IS_T40LP specify - // HACK: partial setup timing - $setup(A0, posedge WCLK, 84); - $setup(A1, posedge WCLK, 84); - $setup(A2, posedge WCLK, 84); - $setup(A3, posedge WCLK, 84); - $setup(A4, posedge WCLK, 84); - $setup(D, posedge WCLK, 84); - $setup(WE, posedge WCLK, 84); - // HACK: No timing arcs for SPO; using ones for DPO - // (are we meant to use the single-port timings here?) - (A0 => SPO) = 142; - (A1 => SPO) = 142; - (A2 => SPO) = 142; - (A3 => SPO) = 142; - (A4 => SPO) = 142; - (DPRA0 => DPO) = 142; - (DPRA1 => DPO) = 142; - (DPRA2 => DPO) = 142; - (DPRA3 => DPO) = 142; - (DPRA4 => DPO) = 142; + $setup(A0, posedge WCLK, 198); + $setup(A1, posedge WCLK, 198); + $setup(A2, posedge WCLK, 198); + $setup(A3, posedge WCLK, 198); + $setup(A4, posedge WCLK, 198); + $setup(D, posedge WCLK, 198); + $setup(WE, posedge WCLK, 198); + (A0 => SPO) = 211; + (A1 => SPO) = 202; + (A2 => SPO) = 193; + (A3 => SPO) = 185; + (A4 => SPO) = 176; + (DPRA0 => DPO) = 185; + (DPRA1 => DPO) = 176; + (DPRA2 => DPO) = 167; + (DPRA3 => DPO) = 159; + (DPRA4 => DPO) = 150; (posedge WCLK => (SPO : D)) = 1586; (posedge WCLK => (DPO : D)) = 1586; endspecify @@ -962,29 +965,28 @@ module RAMD64X1 ( `endif `ifdef IS_T40LP specify - // HACK: partial setup timing - $setup(A0, posedge WCLK, 84); - $setup(A1, posedge WCLK, 84); - $setup(A2, posedge WCLK, 84); - $setup(A3, posedge WCLK, 84); - $setup(A4, posedge WCLK, 84); - $setup(A5, posedge WCLK, 84); - $setup(D, posedge WCLK, 84); - $setup(WE, posedge WCLK, 84); - (A0 => SPO) = 466; - (A1 => SPO) = 466; - (A2 => SPO) = 466; - (A3 => SPO) = 466; - (A4 => SPO) = 466; + $setup(A0, posedge WCLK, 224); + $setup(A1, posedge WCLK, 224); + $setup(A2, posedge WCLK, 224); + $setup(A3, posedge WCLK, 224); + $setup(A4, posedge WCLK, 224); + $setup(A5, posedge WCLK, 224); + $setup(D, posedge WCLK, 224); + $setup(WE, posedge WCLK, 224); + (A0 => SPO) = 509; + (A1 => SPO) = 500; + (A2 => SPO) = 491; + (A3 => SPO) = 483; + (A4 => SPO) = 474; (A5 => SPO) = 187; - (DPRA0 => DPO) = 380; - (DPRA1 => DPO) = 380; - (DPRA2 => DPO) = 380; - (DPRA3 => DPO) = 380; - (DPRA4 => DPO) = 380; - (DPRA5 => DPO) = 195; - (posedge WCLK => (SPO : D)) = 1730; - (posedge WCLK => (DPO : D)) = 1799; + (DPRA0 => DPO) = 531; + (DPRA1 => DPO) = 522; + (DPRA2 => DPO) = 513; + (DPRA3 => DPO) = 505; + (DPRA4 => DPO) = 496; + (DPRA5 => DPO) = 199; + (posedge WCLK => (SPO : D)) = 1798; + (posedge WCLK => (DPO : D)) = 1807; endspecify `endif endmodule @@ -1143,9 +1145,22 @@ module RBRAM #( input PD ); +// Timings simplified for now +specify + $setup(DA, posedge CLKA, 715); + $setup(CEA, posedge CLKA, 414); + $setup(AA, posedge CLKA, 624); + + $setup(DB, posedge CLKB, 744); + $setup(CEB, posedge CLKB, 350); + $setup(AB, posedge CLKB, 643); + + (posedge CLKA => (QA : DA)) = 2380; + (posedge CLKB => (QB : DB)) = 2289; +endspecify + endmodule -(* lib_whitebox *) module RBRAM2 #( parameter TARGET_NODE = "T16FFC_Gen2.4", parameter BRAM_MODE = "SDP_2048x40", From c747466a7a539416090c6b59a7f0ac9dbec8b8b1 Mon Sep 17 00:00:00 2001 From: Lofty Date: Wed, 4 Mar 2026 12:16:35 +0000 Subject: [PATCH 280/291] analogdevices: update missed T40LP timings --- techlibs/analogdevices/cells_sim.v | 104 ++++++++++++++--------------- 1 file changed, 52 insertions(+), 52 deletions(-) diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v index 85ab06b7e..2bf958d8f 100644 --- a/techlibs/analogdevices/cells_sim.v +++ b/techlibs/analogdevices/cells_sim.v @@ -80,7 +80,7 @@ module LUT1(output O, input I0); `endif `ifdef IS_T40LP specify - (I0 => O) = 121; + (I0 => O) = 187; endspecify `endif endmodule @@ -98,8 +98,8 @@ module LUT2(output O, input I0, I1); `endif `ifdef IS_T40LP specify - (I0 => O) = 121; - (I1 => O) = 121; + (I0 => O) = 187; + (I1 => O) = 176; endspecify `endif endmodule @@ -119,9 +119,9 @@ module LUT3(output O, input I0, I1, I2); `endif `ifdef IS_T40LP specify - (I0 => O) = 121; - (I1 => O) = 121; - (I2 => O) = 121; + (I0 => O) = 249; + (I1 => O) = 238; + (I2 => O) = 227; endspecify `endif endmodule @@ -143,10 +143,10 @@ module LUT4(output O, input I0, I1, I2, I3); `endif `ifdef IS_T40LP specify - (I0 => O) = 121; - (I1 => O) = 121; - (I2 => O) = 121; - (I3 => O) = 121; + (I0 => O) = 192; + (I1 => O) = 181; + (I2 => O) = 170; + (I3 => O) = 160; endspecify `endif endmodule @@ -170,11 +170,11 @@ module LUT5(output O, input I0, I1, I2, I3, I4); `endif `ifdef IS_T40LP specify - (I0 => O) = 121; - (I1 => O) = 121; - (I2 => O) = 121; - (I3 => O) = 121; - (I4 => O) = 121; + (I0 => O) = 204; + (I1 => O) = 195; + (I2 => O) = 186; + (I3 => O) = 178; + (I4 => O) = 169; endspecify `endif endmodule @@ -200,12 +200,12 @@ module LUT6(output O, input I0, I1, I2, I3, I4, I5); `endif `ifdef IS_T40LP specify - (I0 => O) = 121; - (I1 => O) = 121; - (I2 => O) = 121; - (I3 => O) = 121; - (I4 => O) = 121; - (I5 => O) = 121; + (I0 => O) = 185; + (I1 => O) = 176; + (I2 => O) = 165; + (I3 => O) = 155; + (I4 => O) = 144; + (I5 => O) = 134; endspecify `endif endmodule @@ -244,13 +244,13 @@ module \$__ABC9_LUT7 (output O, input I0, I1, I2, I3, I4, I5, I6); `endif `ifdef IS_T40LP specify - (I0 => O) = 121 + 140 /* LUTMUX7.I0 */; - (I1 => O) = 121 + 140 /* LUTMUX7.I0 */; - (I2 => O) = 121 + 140 /* LUTMUX7.I0 */; - (I3 => O) = 121 + 140 /* LUTMUX7.I0 */; - (I4 => O) = 121 + 140 /* LUTMUX7.I0 */; - (I5 => O) = 121 + 140 /* LUTMUX7.I0 */; - (I6 => O) = 0 + 162 /* LUTMUX7.S */; + (I0 => O) = 185 + 210 /* LUTMUX7.I0 */; + (I1 => O) = 176 + 210 /* LUTMUX7.I0 */; + (I2 => O) = 165 + 210 /* LUTMUX7.I0 */; + (I3 => O) = 155 + 210 /* LUTMUX7.I0 */; + (I4 => O) = 144 + 210 /* LUTMUX7.I0 */; + (I5 => O) = 134 + 210 /* LUTMUX7.I0 */; + (I6 => O) = 0 + 188 /* LUTMUX7.S */; endspecify `endif `endif @@ -275,14 +275,14 @@ module \$__ABC9_LUT8 (output O, input I0, I1, I2, I3, I4, I5, I6, I7); `endif `ifdef IS_T40LP specify - (I0 => O) = 121 + 140 /* LUTMUX7.I0 */ + 146 /* LUTMUX8.I1 */; - (I1 => O) = 121 + 140 /* LUTMUX7.I0 */ + 146 /* LUTMUX8.I1 */; - (I2 => O) = 121 + 140 /* LUTMUX7.I0 */ + 146 /* LUTMUX8.I1 */; - (I3 => O) = 121 + 140 /* LUTMUX7.I0 */ + 146 /* LUTMUX8.I1 */; - (I4 => O) = 121 + 140 /* LUTMUX7.I0 */ + 146 /* LUTMUX8.I1 */; - (I5 => O) = 121 + 140 /* LUTMUX7.I0 */ + 146 /* LUTMUX8.I1 */; - (I6 => O) = 0 + 162 /* LUTMUX7.S */ + 146 /* LUTMUX8.I1 */; - (I7 => O) = 0 + 0 + 181 /* LUTMUX8.S */; + (I0 => O) = 185 + 210 /* LUTMUX7.I0 */ + 155 /* LUTMUX8.I0 */; + (I1 => O) = 176 + 210 /* LUTMUX7.I0 */ + 155 /* LUTMUX8.I0 */; + (I2 => O) = 165 + 210 /* LUTMUX7.I0 */ + 155 /* LUTMUX8.I0 */; + (I3 => O) = 155 + 210 /* LUTMUX7.I0 */ + 155 /* LUTMUX8.I0 */; + (I4 => O) = 144 + 210 /* LUTMUX7.I0 */ + 155 /* LUTMUX8.I0 */; + (I5 => O) = 134 + 210 /* LUTMUX7.I0 */ + 155 /* LUTMUX8.I0 */; + (I6 => O) = 0 + 188 /* LUTMUX7.S */ + 155 /* LUTMUX8.I0 */; + (I7 => O) = 0 + 0 + 193 /* LUTMUX8.S */; endspecify `endif `endif @@ -300,9 +300,9 @@ module LUTMUX7(output O, input I0, I1, S); `endif `ifdef IS_T40LP specify - (I0 => O) = 140; - (I1 => O) = 140; - (S => O) = 162; + (I0 => O) = 210; + (I1 => O) = 182; + (S => O) = 188; endspecify `endif endmodule @@ -319,9 +319,9 @@ module LUTMUX8(output O, input I0, I1, S); `endif `ifdef IS_T40LP specify - (I0 => O) = 140; - (I1 => O) = 146; - (S => O) = 181; + (I0 => O) = 155; + (I1 => O) = 147; + (S => O) = 193; endspecify `endif endmodule @@ -562,11 +562,11 @@ module FFSE ( `endif `ifdef IS_T40LP specify - $setup(D , posedge C, 119); - $setup(CE, posedge C, 385); - $setup(S , posedge C, 565); - if (S) (posedge C => (Q : 1'b1)) = 672; - if (!S && CE) (posedge C => (Q : D)) = 672; + $setup(D , posedge C, 144); + $setup(CE, posedge C, 412); + $setup(S , posedge C, 689); + if (S) (posedge C => (Q : 1'b1)) = 693; + if (!S && CE) (posedge C => (Q : D)) = 693; endspecify `endif endmodule @@ -594,11 +594,11 @@ module FFSE_N ( `endif `ifdef IS_T40LP specify - $setup(D , negedge C, 119); - $setup(CE, negedge C, 385); - $setup(S , negedge C, 565); - if (S) (negedge C => (Q : 1'b1)) = 672; - if (!S && CE) (negedge C => (Q : D)) = 672; + $setup(D , negedge C, 144); + $setup(CE, negedge C, 412); + $setup(S , negedge C, 689); + if (S) (negedge C => (Q : 1'b1)) = 693; + if (!S && CE) (negedge C => (Q : D)) = 693; endspecify `endif endmodule From e2e8245be9905cf73eb62a3d06ad2668cf9f03b8 Mon Sep 17 00:00:00 2001 From: Lofty Date: Wed, 4 Mar 2026 12:24:13 +0000 Subject: [PATCH 281/291] analogdevices: fix MUXF78 name --- techlibs/analogdevices/abc9_model.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/analogdevices/abc9_model.v b/techlibs/analogdevices/abc9_model.v index 3958a2bf0..a5a15026f 100644 --- a/techlibs/analogdevices/abc9_model.v +++ b/techlibs/analogdevices/abc9_model.v @@ -25,7 +25,7 @@ // ABC cannot optimise just one of the MUXF7 away // and expect to save on its delay (* abc9_box, lib_whitebox *) -module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1); +module \$__ANALOGDEVICES_MUXF78 (output O, input I0, I1, I2, I3, S0, S1); assign O = S1 ? (S0 ? I3 : I2) : (S0 ? I1 : I0); specify From f3efa51b3e1620abb2266ff733328a7be51d92aa Mon Sep 17 00:00:00 2001 From: Lofty Date: Wed, 4 Mar 2026 12:24:53 +0000 Subject: [PATCH 282/291] analogdevices: fix SHREG name --- techlibs/analogdevices/cells_map.v | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/techlibs/analogdevices/cells_map.v b/techlibs/analogdevices/cells_map.v index eb28e6e4b..b8d362e4f 100644 --- a/techlibs/analogdevices/cells_map.v +++ b/techlibs/analogdevices/cells_map.v @@ -24,10 +24,10 @@ module \$__SHREG_ (input C, input D, input E, output Q); parameter CLKPOL = 1; parameter ENPOL = 2; - \$__ANALOGDEVICES_SHREG_ #(.DEPTH(DEPTH), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(DEPTH-1), .E(E), .Q(Q)); + \$__XILINX_SHREG_ #(.DEPTH(DEPTH), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(DEPTH-1), .E(E), .Q(Q)); endmodule -module \$__ANALOGDEVICES_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO); +module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO); parameter DEPTH = 0; parameter [DEPTH-1:0] INIT = 0; parameter CLKPOL = 1; @@ -57,9 +57,9 @@ module \$__ANALOGDEVICES_SHREG_ (input C, input D, input [31:0] L, input E, outp assign CE = 1'b1; if (DEPTH == 1) begin if (CLKPOL) - FDRE #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0)); + FFRE #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0)); else - FDRE_1 #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0)); + FFRE_N #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0)); end else if (DEPTH <= 16) begin SRL16E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A0(L[0]), .A1(L[1]), .A2(L[2]), .A3(L[3]), .CE(CE), .CLK(C), .D(D), .Q(Q)); @@ -70,7 +70,7 @@ module \$__ANALOGDEVICES_SHREG_ (input C, input D, input [31:0] L, input E, outp if (DEPTH > 33 && DEPTH <= 64) begin wire T0, T1, T2; SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1)); - \$__ANALOGDEVICES_SHREG_ #(.DEPTH(DEPTH-32), .INIT(INIT[DEPTH-32-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L), .E(E), .Q(T2)); + \$__XILINX_SHREG_ #(.DEPTH(DEPTH-32), .INIT(INIT[DEPTH-32-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L), .E(E), .Q(T2)); if (&_TECHMAP_CONSTMSK_L_) assign Q = T2; else @@ -80,7 +80,7 @@ module \$__ANALOGDEVICES_SHREG_ (input C, input D, input [31:0] L, input E, outp wire T0, T1, T2, T3, T4, T5, T6; SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1)); SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3)); - \$__ANALOGDEVICES_SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4)); + \$__XILINX_SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4)); if (&_TECHMAP_CONSTMSK_L_) assign Q = T4; else @@ -91,7 +91,7 @@ module \$__ANALOGDEVICES_SHREG_ (input C, input D, input [31:0] L, input E, outp SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1)); SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3)); SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5)); - \$__ANALOGDEVICES_SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6)); + \$__XILINX_SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6)); if (&_TECHMAP_CONSTMSK_L_) assign Q = T6; else @@ -111,12 +111,12 @@ module \$__ANALOGDEVICES_SHREG_ (input C, input D, input [31:0] L, input E, outp // For fixed length, if just 1 over a convenient value, decompose else if (DEPTH <= 129 && &_TECHMAP_CONSTMSK_L_) begin wire T; - \$__ANALOGDEVICES_SHREG_ #(.DEPTH(DEPTH-1), .INIT(INIT[DEPTH-1:1]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl (.C(C), .D(D), .L({32{1'b1}}), .E(E), .Q(T)); - \$__ANALOGDEVICES_SHREG_ #(.DEPTH(1), .INIT(INIT[0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_last (.C(C), .D(T), .L(L), .E(E), .Q(Q)); + \$__XILINX_SHREG_ #(.DEPTH(DEPTH-1), .INIT(INIT[DEPTH-1:1]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl (.C(C), .D(D), .L({32{1'b1}}), .E(E), .Q(T)); + \$__XILINX_SHREG_ #(.DEPTH(1), .INIT(INIT[0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_last (.C(C), .D(T), .L(L), .E(E), .Q(Q)); end // For variable length, if just 1 over a convenient value, then bump up one more else if (DEPTH < 129 && ~&_TECHMAP_CONSTMSK_L_) - \$__ANALOGDEVICES_SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q)); + \$__XILINX_SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q)); else begin localparam depth0 = 128; localparam num_srl128 = DEPTH / depth0; @@ -126,10 +126,10 @@ module \$__ANALOGDEVICES_SHREG_ (input C, input D, input [31:0] L, input E, outp assign S[0] = D; genvar i; for (i = 0; i < num_srl128; i++) - \$__ANALOGDEVICES_SHREG_ #(.DEPTH(depth0), .INIT(INIT[DEPTH-1-i*depth0-:depth0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl (.C(C), .D(S[i]), .L(L[$clog2(depth0)-1:0]), .E(E), .Q(T[i]), .SO(S[i+1])); + \$__XILINX_SHREG_ #(.DEPTH(depth0), .INIT(INIT[DEPTH-1-i*depth0-:depth0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl (.C(C), .D(S[i]), .L(L[$clog2(depth0)-1:0]), .E(E), .Q(T[i]), .SO(S[i+1])); if (depthN > 0) - \$__ANALOGDEVICES_SHREG_ #(.DEPTH(depthN), .INIT(INIT[depthN-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_last (.C(C), .D(S[num_srl128]), .L(L[$clog2(depth0)-1:0]), .E(E), .Q(T[num_srl128])); + \$__XILINX_SHREG_ #(.DEPTH(depthN), .INIT(INIT[depthN-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_last (.C(C), .D(S[num_srl128]), .L(L[$clog2(depth0)-1:0]), .E(E), .Q(T[num_srl128])); if (&_TECHMAP_CONSTMSK_L_) assign Q = T[num_srl128 + (depthN > 0 ? 1 : 0) - 1]; From da83c93673c07cbe5df0ebc4772146e089bb6a04 Mon Sep 17 00:00:00 2001 From: Lofty Date: Wed, 4 Mar 2026 12:25:11 +0000 Subject: [PATCH 283/291] analogdevices: fix SHIFTX name --- techlibs/analogdevices/mux_map.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/analogdevices/mux_map.v b/techlibs/analogdevices/mux_map.v index f49834491..7fa45cb54 100644 --- a/techlibs/analogdevices/mux_map.v +++ b/techlibs/analogdevices/mux_map.v @@ -60,7 +60,7 @@ module \$shiftx (A, B, Y); if (((A_WIDTH + Y_WIDTH - 1) / Y_WIDTH) < `MIN_MUX_INPUTS) wire _TECHMAP_FAIL_ = 1; else - \$__XILINX_SHIFTX #( + \$__ANALOGDEVICES_SHIFTX #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), From 23eb38fe3f2d858fe407d66d9f300d2e0162b901 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 5 Mar 2026 11:59:20 +0100 Subject: [PATCH 284/291] celltypes: include newcelltypes to allow legacy code access to migrated yosys_celltypes --- kernel/celltypes.h | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/celltypes.h b/kernel/celltypes.h index c03cbdcc3..50dee573e 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -21,6 +21,7 @@ #define CELLTYPES_H #include "kernel/yosys.h" +#include "kernel/newcelltypes.h" YOSYS_NAMESPACE_BEGIN From 52533b0d1c6a5b7b2fb8837c0230cfb9ed9cf735 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 6 Mar 2026 09:10:36 +0100 Subject: [PATCH 285/291] Update opt_lut_ins and stat for analogdevices and remove ecp5 --- passes/cmds/stat.cc | 10 +++++----- passes/opt/opt_lut_ins.cc | 13 +++++++------ techlibs/analogdevices/synth_analogdevices.cc | 4 ++-- tests/arch/analogdevices/opt_lut_ins.ys | 2 +- tests/arch/ecp5/opt_lut_ins.ys | 2 +- 5 files changed, 16 insertions(+), 15 deletions(-) diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index 61135e066..9494d6032 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -561,7 +561,7 @@ struct statdata_t { } } - if (tech == "xilinx") { + if (tech == "xilinx" || tech == "analogdevices") { log("\n"); log(" Estimated number of LCs: %10u\n", estimate_xilinx_lc()); } @@ -628,7 +628,7 @@ struct statdata_t { first_line = false; } log("\n }\n"); - if (tech == "xilinx") { + if (tech == "xilinx" || tech == "analogdevices") { log(" \"estimated_num_lc\": %u,\n", estimate_xilinx_lc()); } if (tech == "cmos") { @@ -710,7 +710,7 @@ struct statdata_t { log("\n"); log(" }"); } - if (tech == "xilinx") { + if (tech == "xilinx" || tech == "analogdevices") { log(",\n"); log(" \"estimated_num_lc\": %u", estimate_xilinx_lc()); } @@ -908,7 +908,7 @@ struct StatPass : public Pass { log("\n"); log(" -tech \n"); log(" print area estimate for the specified technology. Currently supported\n"); - log(" values for : xilinx, cmos\n"); + log(" values for : xilinx, analogdevices, cmos\n"); log("\n"); log(" -width\n"); log(" annotate internal cell types with their word width.\n"); @@ -968,7 +968,7 @@ struct StatPass : public Pass { if (!json_mode) log_header(design, "Printing statistics.\n"); - if (techname != "" && techname != "xilinx" && techname != "cmos" && !json_mode) + if (techname != "" && techname != "xilinx" && techname != "analogdevices" && techname != "cmos" && !json_mode) log_cmd_error("Unsupported technology: '%s'\n", techname); if (json_mode) { diff --git a/passes/opt/opt_lut_ins.cc b/passes/opt/opt_lut_ins.cc index fa8eb563b..580853b51 100644 --- a/passes/opt/opt_lut_ins.cc +++ b/passes/opt/opt_lut_ins.cc @@ -39,7 +39,8 @@ struct OptLutInsPass : public Pass { log("\n"); log(" -tech \n"); log(" Instead of generic $lut cells, operate on LUT cells specific\n"); - log(" to the given technology. Valid values are: xilinx, lattice, gowin.\n"); + log(" to the given technology. Valid values are: xilinx, lattice,\n"); + log(" gowin, analogdevices.\n"); log("\n"); } void execute(std::vector args, RTLIL::Design *design) override @@ -58,7 +59,7 @@ struct OptLutInsPass : public Pass { } extra_args(args, argidx, design); - if (techname != "" && techname != "xilinx" && techname != "lattice" && techname != "ecp5" && techname != "gowin") + if (techname != "" && techname != "xilinx" && techname != "lattice" && techname != "analogdevices" && techname != "gowin") log_cmd_error("Unsupported technology: '%s'\n", techname); for (auto module : design->selected_modules()) @@ -81,7 +82,7 @@ struct OptLutInsPass : public Pass { inputs = cell->getPort(ID::A); output = cell->getPort(ID::Y); lut = cell->getParam(ID::LUT); - } else if (techname == "xilinx" || techname == "gowin") { + } else if (techname == "xilinx" || techname == "gowin" || techname == "analogdevices") { if (cell->type == ID(LUT1)) { inputs = { cell->getPort(ID(I0)), @@ -126,11 +127,11 @@ struct OptLutInsPass : public Pass { continue; } lut = cell->getParam(ID::INIT); - if (techname == "xilinx") + if (techname == "xilinx" || techname == "analogdevices") output = cell->getPort(ID::O); else output = cell->getPort(ID::F); - } else if (techname == "lattice" || techname == "ecp5") { + } else if (techname == "lattice") { if (cell->type == ID(LUT4)) { inputs = { cell->getPort(ID::A), @@ -236,7 +237,7 @@ struct OptLutInsPass : public Pass { } else { // xilinx, gowin cell->setParam(ID::INIT, new_lut); - if (techname == "xilinx") + if (techname == "xilinx" || techname == "analogdevices") log_assert(GetSize(new_inputs) <= 6); else log_assert(GetSize(new_inputs) <= 4); diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc index abb95ea33..00d2e18d6 100644 --- a/techlibs/analogdevices/synth_analogdevices.cc +++ b/techlibs/analogdevices/synth_analogdevices.cc @@ -490,7 +490,7 @@ struct SynthAnalogDevicesPass : public ScriptPass techmap_args += " -D LUT_WIDTH=6"; run("techmap " + techmap_args); run("xilinx_dffopt"); - run("opt_lut_ins -tech xilinx"); + run("opt_lut_ins -tech analogdevices"); } if (check_label("finalize")) { @@ -499,7 +499,7 @@ struct SynthAnalogDevicesPass : public ScriptPass if (check_label("check")) { run("hierarchy -check"); - run("stat -tech xilinx"); + run("stat -tech analogdevices"); run("check -noinit"); run("blackbox =A:whitebox"); } diff --git a/tests/arch/analogdevices/opt_lut_ins.ys b/tests/arch/analogdevices/opt_lut_ins.ys index 0f312b4ca..9723ee651 100644 --- a/tests/arch/analogdevices/opt_lut_ins.ys +++ b/tests/arch/analogdevices/opt_lut_ins.ys @@ -19,7 +19,7 @@ end EOF read_verilog -lib +/analogdevices/cells_sim.v -equiv_opt -assert -map +/analogdevices/cells_sim.v opt_lut_ins -tech xilinx +equiv_opt -assert -map +/analogdevices/cells_sim.v opt_lut_ins -tech analogdevices design -load postopt diff --git a/tests/arch/ecp5/opt_lut_ins.ys b/tests/arch/ecp5/opt_lut_ins.ys index 622b5406c..7f9970c69 100644 --- a/tests/arch/ecp5/opt_lut_ins.ys +++ b/tests/arch/ecp5/opt_lut_ins.ys @@ -23,7 +23,7 @@ EOF read_verilog -lib +/ecp5/cells_sim.v -equiv_opt -assert -map +/ecp5/cells_sim.v opt_lut_ins -tech ecp5 +equiv_opt -assert -map +/ecp5/cells_sim.v opt_lut_ins -tech lattice design -load postopt From 602f3fd1a51c14f89a42a13e7335651b2fee2243 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 6 Mar 2026 09:10:55 +0100 Subject: [PATCH 286/291] Add missing EOL --- tests/arch/analogdevices/asym_ram_sdp_read_wider.v | 2 +- tests/arch/analogdevices/asym_ram_sdp_write_wider.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/arch/analogdevices/asym_ram_sdp_read_wider.v b/tests/arch/analogdevices/asym_ram_sdp_read_wider.v index 183b0cf4f..853ba6254 100644 --- a/tests/arch/analogdevices/asym_ram_sdp_read_wider.v +++ b/tests/arch/analogdevices/asym_ram_sdp_read_wider.v @@ -70,4 +70,4 @@ module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA, end end assign doB = readB; -endmodule \ No newline at end of file +endmodule diff --git a/tests/arch/analogdevices/asym_ram_sdp_write_wider.v b/tests/arch/analogdevices/asym_ram_sdp_write_wider.v index df817894f..abffa9fc4 100644 --- a/tests/arch/analogdevices/asym_ram_sdp_write_wider.v +++ b/tests/arch/analogdevices/asym_ram_sdp_write_wider.v @@ -69,4 +69,4 @@ module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA, end end end -endmodule \ No newline at end of file +endmodule From 167c6c45858fa637a872a57cdcdb758cd9e6c77a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Fri, 6 Mar 2026 11:52:17 +0100 Subject: [PATCH 287/291] Replace deprecated Tcl API to fix use-after-free Under Tcl 9.0 the Tcl_SetResult utility is a macro: #define Tcl_SetResult(interp, result, freeProc) \ do { \ const char *__result = result; \ Tcl_FreeProc *__freeProc = freeProc; \ Tcl_SetObjResult(interp, Tcl_NewStringObj(__result, -1)); \ if (__result != NULL && __freeProc != NULL && __freeProc != TCL_VOLATILE) { \ if (__freeProc == TCL_DYNAMIC) { \ Tcl_Free((char *)__result); \ } else { \ (*__freeProc)((char *)__result); \ } \ } \ } while(0) Temporaries constructed as part of the 'result' expression will be dropped before the 'result' pointer is used. What was safe when Tcl_SetResult was a function isn't safe with the macro definition. Transition away from deprecated SetResult to calling SetObjResult/MewStringObj directly. --- kernel/tclapi.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/kernel/tclapi.cc b/kernel/tclapi.cc index ec0483a4a..9866f5c98 100644 --- a/kernel/tclapi.cc +++ b/kernel/tclapi.cc @@ -279,7 +279,7 @@ static int tcl_get_attr(ClientData, Tcl_Interp *interp, int argc, const char *ar ERROR("object not found") if (string_flag) { - Tcl_SetResult(interp, (char *) obj->get_string_attribute(attr_id).c_str(), TCL_VOLATILE); + Tcl_SetObjResult(interp, Tcl_NewStringObj(obj->get_string_attribute(attr_id).c_str(), -1)); } else if (int_flag || uint_flag || sint_flag) { if (!obj->has_attribute(attr_id)) ERROR("attribute missing (required for -int)"); @@ -295,7 +295,7 @@ static int tcl_get_attr(ClientData, Tcl_Interp *interp, int argc, const char *ar if (!obj->has_attribute(attr_id)) ERROR("attribute missing (required unless -bool or -string)") - Tcl_SetResult(interp, (char *) obj->attributes.at(attr_id).as_string().c_str(), TCL_VOLATILE); + Tcl_SetObjResult(interp, Tcl_NewStringObj(obj->attributes.at(attr_id).as_string().c_str(), -1)); } return TCL_OK; @@ -341,7 +341,7 @@ static int tcl_has_attr(ClientData, Tcl_Interp *interp, int argc, const char *ar if (!obj) ERROR("object not found") - Tcl_SetResult(interp, (char *) std::to_string(obj->has_attribute(attr_id)).c_str(), TCL_VOLATILE); + Tcl_SetObjResult(interp, Tcl_NewStringObj(std::to_string(obj->has_attribute(attr_id)).c_str(), -1)); return TCL_OK; } @@ -465,14 +465,14 @@ static int tcl_get_param(ClientData, Tcl_Interp *interp, int argc, const char *a const RTLIL::Const &value = cell->getParam(param_id); if (string_flag) { - Tcl_SetResult(interp, (char *) value.decode_string().c_str(), TCL_VOLATILE); + Tcl_SetObjResult(interp, Tcl_NewStringObj(value.decode_string().c_str(), -1)); } else if (int_flag || uint_flag || sint_flag) { mp_int value_mp; if (!const_to_mp_int(value, &value_mp, sint_flag, uint_flag)) ERROR("bignum manipulation failed"); Tcl_SetObjResult(interp, Tcl_NewBignumObj(&value_mp)); } else { - Tcl_SetResult(interp, (char *) value.as_string().c_str(), TCL_VOLATILE); + Tcl_SetObjResult(interp, Tcl_NewStringObj(value.as_string().c_str(), -1)); } return TCL_OK; } From fea0d18c0a33066c4d98524e94bf93274bcc3433 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 9 Mar 2026 13:04:45 +0100 Subject: [PATCH 288/291] Update ABC as per 2026-03-09 --- abc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/abc b/abc index 8e401543d..b4a657e75 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit 8e401543d3ecf65e3a3631c7a271793a4d356cb0 +Subproject commit b4a657e75b16b68c514a7326642ea074f8460939 From c5c104f560a76c17524e7f56fbe7af308f360bba Mon Sep 17 00:00:00 2001 From: Asherah Connor Date: Wed, 11 Mar 2026 18:35:18 +1100 Subject: [PATCH 289/291] cxxrtl: Suppress un/signed comparison warning; this is positive --- backends/cxxrtl/runtime/cxxrtl/cxxrtl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h index fbbe2373f..eab5bb3d1 100644 --- a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h +++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h @@ -614,7 +614,7 @@ struct value : public expr_base> { int64_t divisor_shift = divisor.ctlz() - dividend.ctlz(); assert(divisor_shift >= 0); divisor = divisor.shl(value{(chunk::type) divisor_shift}); - for (size_t step = 0; step <= divisor_shift; step++) { + for (size_t step = 0; step <= (uint64_t) divisor_shift; step++) { quotient = quotient.shl(value{1u}); if (!dividend.ucmp(divisor)) { dividend = dividend.sub(divisor); From 5c74446e5793088c6dd7155615aa1457b239ddff Mon Sep 17 00:00:00 2001 From: Asherah Connor Date: Wed, 11 Mar 2026 20:40:22 +1100 Subject: [PATCH 290/291] cxxrtl: Suppress another un/signed comparison warning! --- backends/cxxrtl/runtime/cxxrtl/cxxrtl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h index fbbe2373f..641dd1aea 100644 --- a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h +++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h @@ -1119,7 +1119,7 @@ struct fmt_part { case STRING: { buf.reserve(Bits/8); - for (int i = 0; i < Bits; i += 8) { + for (size_t i = 0; i < Bits; i += 8) { char ch = 0; for (int j = 0; j < 8 && i + j < int(Bits); j++) if (val.bit(i + j)) From 53939bd3ba53336c7916cc6b128fc329afbed3e8 Mon Sep 17 00:00:00 2001 From: Lofty Date: Wed, 11 Mar 2026 11:09:31 +0000 Subject: [PATCH 291/291] synth_quicklogic: fix small multiplier inference --- techlibs/quicklogic/synth_quicklogic.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index ade6f944c..1026dc233 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -236,6 +236,7 @@ struct SynthQuickLogicPass : public ScriptPass { run("ql_dsp_macc"); run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=20 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=11 -D DSP_B_MINWIDTH=10 -D DSP_NAME=$__QL_MUL20X18"); + run("chtype -set $mul t:$__soft_mul"); run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=10 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__QL_MUL10X9"); run("chtype -set $mul t:$__soft_mul");