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Cleanup tests

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This commit is contained in:
Eddie Hung 2020-02-15 08:29:10 -08:00
parent 717fb492b3
commit f858219c4e
2 changed files with 1 additions and 1 deletions
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18
tests/arch/xilinx/bug1480.ys Normal file
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read_verilog << EOF
module top(...);
input signed [17:0] A;
input signed [17:0] B;
output X;
output Y;
wire [35:0] P;
assign P = A * B;
assign X = P[0];
assign Y = P[35];
endmodule
EOF
synth_xilinx