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19 lines
203 B
Plaintext
19 lines
203 B
Plaintext
read_verilog << EOF
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module top(...);
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input signed [17:0] A;
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input signed [17:0] B;
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output X;
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output Y;
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wire [35:0] P;
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assign P = A * B;
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assign X = P[0];
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assign Y = P[35];
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endmodule
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EOF
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synth_xilinx
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