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some refactoring

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This commit is contained in:
Artur Swiderski 2020-11-01 16:09:03 +01:00
parent 7a8efe9f1b
commit f7dc93c652
6 changed files with 66 additions and 48 deletions
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7
techlibs/intel_le/synth_intel_le.cc
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@ -43,6 +43,7 @@ struct SynthIntelLEPass : public ScriptPass {
log(" -family <family>\n");
log(" target one of:\n");
log(" \"cycloneiv\" - Cyclone IV (default)\n");
log(" \"cycloneive\" - Cyclone IV E \n");
log("\n");
log(" -vqm <file>\n");
log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n");
@ -144,7 +145,7 @@ struct SynthIntelLEPass : public ScriptPass {
if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n");
if (family_opt == "cycloneiv") {
if (family_opt == "cycloneiv" or family_opt == "cycloneive") {
bram_type = "m9k";
} else {
log_cmd_error("Invalid family specified: '%s'\n", family_opt.c_str());
@ -166,8 +167,8 @@ struct SynthIntelLEPass : public ScriptPass {
}
if (check_label("begin")) {
if (family_opt == "cycloneiv")
run(stringf("read_verilog -sv -lib +/intel_le/%s/cells_sim.v", family_opt.c_str()));
if (family_opt == "cycloneiv" or family_opt == "cycloneive")
run(stringf("read_verilog -sv -lib +/intel_le/cycloneiv/cells_sim.v"));
run(stringf("read_verilog -specify -lib -D %s +/intel_le/common/le_sim.v", family_opt.c_str()));
run(stringf("read_verilog -specify -lib -D %s +/intel_le/common/dff_sim.v", family_opt.c_str()));
run(stringf("read_verilog -specify -lib -D %s +/intel_le/common/mem_sim.v", family_opt.c_str()));