From f7dc93c65239ddadc2dc2d68575550a8ff53e77c Mon Sep 17 00:00:00 2001 From: Artur Swiderski Date: Sun, 1 Nov 2020 16:09:03 +0100 Subject: [PATCH] some refactoring --- techlibs/intel_le/common/arith_le_map.v | 14 ++++--- techlibs/intel_le/common/dff_sim.v | 2 +- techlibs/intel_le/common/le_sim.v | 49 ++++++++++++++++++++--- techlibs/intel_le/common/mem_sim.v | 24 ----------- techlibs/intel_le/common/quartus_rename.v | 18 ++++----- techlibs/intel_le/synth_intel_le.cc | 7 ++-- 6 files changed, 66 insertions(+), 48 deletions(-) diff --git a/techlibs/intel_le/common/arith_le_map.v b/techlibs/intel_le/common/arith_le_map.v index 614e343af..07170c4c0 100644 --- a/techlibs/intel_le/common/arith_le_map.v +++ b/techlibs/intel_le/common/arith_le_map.v @@ -33,27 +33,31 @@ wire [Y_WIDTH-1:0] BX = B_buf; wire [Y_WIDTH-1:0] BTOADDER; wire [Y_WIDTH:0] LE_CARRY; + // Start of carry chain generate if (_TECHMAP_CONSTMSK_CI_ == 1) begin assign LE_CARRY[0] = _TECHMAP_CONSTVAL_CI_; end else begin + /* MISTRAL_ALUT_ARITH #( .LUT(16'b1010_1010_1010_1010), // Q = A - .sum_lutc_input("cin") + ) le_start ( .A(CI), .B(1'b1), .C(1'b1), .D0(1'b1), .D1(1'b1), .CI(1'b0), .SO(), .CO(LE_CARRY[0]) ); + */ + assign LE_CARRY[0] = CI; end endgenerate // Carry chain genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice - + /* MISTRAL_ALUT_ARITH #( .LUT(16'b0110_0110_0110_0110), // Q = A ? ~B : B .sum_lutc_input("cin") @@ -63,14 +67,14 @@ generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice .SO(BTOADDER[i]), .CO() ); - + */ MISTRAL_ALUT_ARITH #( .LUT(16'b1001_0110_1110_1000), // SUM = A xor B xor CI // CARRYi+1 = A and B or A and CI or B and CI - .sum_lutc_input("cin") + ) le_i ( - .A(AA[i]), .B(BTOADDER[i]), .C(1'b1), .D(1'b1), + .A(AA[i]), .B(BB[i]), .C(1'b1), .D(1'b1), .CI(LE_CARRY[i]), .SO(Y[i]), .CO(LE_CARRY[i+1]) diff --git a/techlibs/intel_le/common/dff_sim.v b/techlibs/intel_le/common/dff_sim.v index 05c3dce86..36a929489 100644 --- a/techlibs/intel_le/common/dff_sim.v +++ b/techlibs/intel_le/common/dff_sim.v @@ -75,7 +75,7 @@ specify if (ACLR === 1'b0) (ACLR => Q) = 282; endspecify `endif -`ifdef cyclone10gx +`ifdef cycloneive specify // TODO (long-term): investigate these numbers. // It seems relying on the Quartus Timing Analyzer was not the best idea; it's too fiddly. diff --git a/techlibs/intel_le/common/le_sim.v b/techlibs/intel_le/common/le_sim.v index 95d273c14..4e89aaf2e 100644 --- a/techlibs/intel_le/common/le_sim.v +++ b/techlibs/intel_le/common/le_sim.v @@ -91,6 +91,14 @@ specify (D => Q) = 97; endspecify `endif +`ifdef cycloneive + specify + (A => Q) = 510; + (B => Q) = 512; + (C => Q) = 400; + (D => Q) = 97; + endspecify +`endif assign Q = LUT >> {D, C, B, A}; @@ -103,13 +111,19 @@ module MISTRAL_ALUT3(input A, B, C, output Q); parameter [7:0] LUT = 8'h00; `ifdef cycloneiv -specify +specify (A => Q) = 510; (B => Q) = 400; (C => Q) = 97; endspecify `endif - +`ifdef cycloneive + specify + (A => Q) = 510; + (B => Q) = 400; + (C => Q) = 97; + endspecify +`endif assign Q = LUT >> {C, B, A}; endmodule @@ -126,7 +140,12 @@ specify (B => Q) = 97; endspecify `endif - +`ifdef cycloneive + specify + (A => Q) = 400; + (B => Q) = 97; + endspecify +`endif assign Q = LUT >> {B, A}; endmodule @@ -135,12 +154,16 @@ endmodule (* abc9_lut=1, lib_whitebox *) module MISTRAL_NOT(input A, output Q); -`ifdef cycloneiv +`ifdef cycloneiv specify (A => Q) = 97; endspecify `endif - +`ifdef cycloneive + specify + (A => Q) = 97; + endspecify +`endif assign Q = ~A; endmodule @@ -149,7 +172,7 @@ endmodule module MISTRAL_ALUT_ARITH(input A, B, C, D, (* abc9_carry *) input CI, output SO, (* abc9_carry *) output CO); parameter LUT = 16'h0000; -parameter sum_lutc_input = "cin"; + `ifdef cycloneiv specify (A => SO) = 1342; @@ -165,7 +188,21 @@ specify (CI => CO) = 36; // Divided by 2 to account for there being two ALUT_ARITHs in an ALM) endspecify `endif +`ifdef cycloneive + specify + (A => SO) = 1342; + (B => SO) = 1323; + (C => SO) = 927; + (D => SO) = 887; + (CI => SO) = 368; + (A => CO) = 1082; + (B => CO) = 1062; + (C => CO) = 813; + (D => CO) = 866; + (CI => CO) = 36; // Divided by 2 to account for there being two ALUT_ARITHs in an ALM) + endspecify +`endif wire q0, q1; diff --git a/techlibs/intel_le/common/mem_sim.v b/techlibs/intel_le/common/mem_sim.v index adc5c45cb..66bc4f82c 100644 --- a/techlibs/intel_le/common/mem_sim.v +++ b/techlibs/intel_le/common/mem_sim.v @@ -1,27 +1,3 @@ -// The MLAB -// -------- -// In addition to Logic Array Blocks (LABs) that contain ten Adaptive Logic -// Modules (ALMs, see alm_sim.v), the Cyclone V/10GX also contain -// Memory/Logic Array Blocks (MLABs) that can act as either ten ALMs, or utilise -// the memory the ALM uses to store the look-up table data for general usage, -// producing a 32 address by 20-bit block of memory. MLABs are spread out -// around the chip, so they can be placed near where they are needed, rather than -// being comparatively limited in placement for a deep but narrow memory such as -// the M10K memory block. -// -// MLABs are used mainly for shallow but wide memories, such as CPU register -// files (which have perhaps 32 registers that are comparatively wide (16/32-bit)) -// or shift registers (by using the output of the Nth bit as input for the N+1th -// bit). -// -// Oddly, instead of providing a block 32 address by 20-bit cell, Quartus asks -// synthesis tools to build MLABs out of 32 address by 1-bit cells, and tries -// to put these cells in the same MLAB during cell placement. Because of this -// a MISTRAL_MLAB cell represents one of these 32 address by 1-bit cells, and -// 20 of them represent a physical MLAB. -// - - // The M9K // -------- diff --git a/techlibs/intel_le/common/quartus_rename.v b/techlibs/intel_le/common/quartus_rename.v index 39076206a..2fefd2a79 100644 --- a/techlibs/intel_le/common/quartus_rename.v +++ b/techlibs/intel_le/common/quartus_rename.v @@ -2,7 +2,7 @@ `define LCELL cycloneiv_lcell_comb `define M9K cycloneiv_ram_block `endif -`ifdef cycloneive +`ifdef cycloneive `define LCELL cycloneive_lcell_comb `define M9K cycloneive_ram_block `endif @@ -33,24 +33,24 @@ endmodule module MISTRAL_ALUT4(input A, B, C, D, output Q); parameter [15:0] LUT = 16'h0000; -parameter sum_lutc_input = "datac"; -`LCELL #(.lut_mask(LUT),.sum_lutc_input(sum_lutc_input)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .combout(Q)); + +`LCELL #(.lut_mask(LUT),.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .combout(Q)); endmodule module MISTRAL_ALUT3(input A, B, C, output Q); parameter [7:0] LUT = 8'h00; -parameter sum_lutc_input = "datac"; -`LCELL #(.lut_mask({2{LUT}}),.sum_lutc_input(sum_lutc_input)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .combout(Q)); + +`LCELL #(.lut_mask({2{LUT}}),.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .combout(Q)); endmodule module MISTRAL_ALUT2(input A, B, output Q); parameter [3:0] LUT = 4'h0; -parameter sum_lutc_input = "datac"; -`LCELL #(.lut_mask({4{LUT}}),.sum_lutc_input(sum_lutc_input)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .combout(Q)); + +`LCELL #(.lut_mask({4{LUT}}),.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .combout(Q)); endmodule @@ -64,8 +64,8 @@ endmodule module MISTRAL_ALUT_ARITH(input A, B, C, D, CI, output SO, CO); parameter LUT = 16'h0000; -parameter sum_lutc_input = "datac"; -`LCELL #(.lut_mask({LUT}),.sum_lutc_input(sum_lutc_input)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .cin(CI), .combout(SO), .cout(CO)); + +`LCELL #(.lut_mask({LUT}),.sum_lutc_input("cin")) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .cin(CI), .combout(SO), .cout(CO)); endmodule diff --git a/techlibs/intel_le/synth_intel_le.cc b/techlibs/intel_le/synth_intel_le.cc index 84527fab1..dc3cd8ce8 100644 --- a/techlibs/intel_le/synth_intel_le.cc +++ b/techlibs/intel_le/synth_intel_le.cc @@ -43,6 +43,7 @@ struct SynthIntelLEPass : public ScriptPass { log(" -family \n"); log(" target one of:\n"); log(" \"cycloneiv\" - Cyclone IV (default)\n"); + log(" \"cycloneive\" - Cyclone IV E \n"); log("\n"); log(" -vqm \n"); log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n"); @@ -144,7 +145,7 @@ struct SynthIntelLEPass : public ScriptPass { if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); - if (family_opt == "cycloneiv") { + if (family_opt == "cycloneiv" or family_opt == "cycloneive") { bram_type = "m9k"; } else { log_cmd_error("Invalid family specified: '%s'\n", family_opt.c_str()); @@ -166,8 +167,8 @@ struct SynthIntelLEPass : public ScriptPass { } if (check_label("begin")) { - if (family_opt == "cycloneiv") - run(stringf("read_verilog -sv -lib +/intel_le/%s/cells_sim.v", family_opt.c_str())); + if (family_opt == "cycloneiv" or family_opt == "cycloneive") + run(stringf("read_verilog -sv -lib +/intel_le/cycloneiv/cells_sim.v")); run(stringf("read_verilog -specify -lib -D %s +/intel_le/common/le_sim.v", family_opt.c_str())); run(stringf("read_verilog -specify -lib -D %s +/intel_le/common/dff_sim.v", family_opt.c_str())); run(stringf("read_verilog -specify -lib -D %s +/intel_le/common/mem_sim.v", family_opt.c_str()));