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some refactoring

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This commit is contained in:
Artur Swiderski 2020-11-01 16:09:03 +01:00
parent 7a8efe9f1b
commit f7dc93c652
6 changed files with 66 additions and 48 deletions
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techlibs/intel_le/common/dff_sim.v
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@ -75,7 +75,7 @@ specify
if (ACLR === 1'b0) (ACLR => Q) = 282;
endspecify
`endif
`ifdef cyclone10gx
`ifdef cycloneive
specify
// TODO (long-term): investigate these numbers.
// It seems relying on the Quartus Timing Analyzer was not the best idea; it's too fiddly.