From f7dc45a478fb6d408eb0d6a43ea6742d99461bc3 Mon Sep 17 00:00:00 2001
From: Akash Levy <akash@silimate.com>
Date: Sun, 28 Jun 2026 20:29:09 -0700
Subject: [PATCH] More verbosity in Module::add failure due to duplicate

---
 kernel/rtlil.cc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 15240bc5d..0c49d60e5 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -2895,6 +2895,9 @@ std::vector<RTLIL::NamedObject*> RTLIL::Module::selected_members() const
 void RTLIL::Module::add(RTLIL::Wire *wire)
 {
 	log_assert(!wire->name.empty());
+	if (count_id(wire->name) != 0)
+		log_error("RTLIL::Module::add: duplicate name '%s' in module '%s' (already used by an "
+			  "existing wire/cell/memory/process).\n", log_id(wire->name), log_id(name));
 	log_assert(count_id(wire->name) == 0);
 	log_assert(refcount_wires_ == 0);
 	wires_[wire->name] = wire;