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gowin: Fix LUT RAM inference, add more models.
This commit is contained in:
Marcelina Kościelnicka
parent
ac2bb70b52
commit
f61f2a4078
3 changed files with 244 additions and 45 deletions
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@ -674,51 +674,250 @@ end
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endmodule
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module RAM16S4 (DO, DI, AD, WRE, CLK);
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parameter WIDTH = 4;
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parameter INIT_0 = 16'h0000;
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parameter INIT_1 = 16'h0000;
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parameter INIT_2 = 16'h0000;
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parameter INIT_3 = 16'h0000;
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input [WIDTH-1:0] AD;
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input [WIDTH-1:0] DI;
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output [WIDTH-1:0] DO;
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input CLK;
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input WRE;
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specify
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(AD => DO) = (270, 405);
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module RAM16S1 (DO, DI, AD, WRE, CLK);
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parameter INIT_0 = 16'h0000;
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input [3:0] AD;
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input DI;
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output DO;
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input CLK;
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input WRE;
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specify
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(AD *> DO) = (270, 405);
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$setup(DI, posedge CLK, 62);
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$setup(WRE, posedge CLK, 62);
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$setup(AD, posedge CLK, 62);
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(posedge CLK => (DO : {WIDTH{1'bx}})) = (474, 565);
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endspecify
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(posedge CLK => (DO : 1'bx)) = (474, 565);
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endspecify
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reg [15:0] mem0, mem1, mem2, mem3;
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initial begin
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mem0 = INIT_0;
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mem1 = INIT_1;
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mem2 = INIT_2;
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mem3 = INIT_3;
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end
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assign DO[0] = mem0[AD];
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assign DO[1] = mem1[AD];
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assign DO[2] = mem2[AD];
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assign DO[3] = mem3[AD];
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always @(posedge CLK) begin
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if (WRE) begin
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mem0[AD] <= DI[0];
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mem1[AD] <= DI[1];
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mem2[AD] <= DI[2];
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mem3[AD] <= DI[3];
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end
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end
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endmodule // RAM16S4
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reg [15:0] mem;
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initial begin
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mem = INIT_0;
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end
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assign DO = mem[AD];
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always @(posedge CLK) begin
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if (WRE) begin
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mem[AD] <= DI;
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end
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end
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endmodule
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module RAM16S2 (DO, DI, AD, WRE, CLK);
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parameter INIT_0 = 16'h0000;
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parameter INIT_1 = 16'h0000;
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input [3:0] AD;
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input [1:0] DI;
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output [1:0] DO;
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input CLK;
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input WRE;
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specify
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(AD *> DO) = (270, 405);
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$setup(DI, posedge CLK, 62);
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$setup(WRE, posedge CLK, 62);
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$setup(AD, posedge CLK, 62);
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(posedge CLK => (DO : 2'bx)) = (474, 565);
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endspecify
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reg [15:0] mem0, mem1;
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initial begin
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mem0 = INIT_0;
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mem1 = INIT_1;
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end
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assign DO[0] = mem0[AD];
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assign DO[1] = mem1[AD];
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always @(posedge CLK) begin
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if (WRE) begin
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mem0[AD] <= DI[0];
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mem1[AD] <= DI[1];
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end
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end
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endmodule
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module RAM16S4 (DO, DI, AD, WRE, CLK);
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parameter INIT_0 = 16'h0000;
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parameter INIT_1 = 16'h0000;
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parameter INIT_2 = 16'h0000;
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parameter INIT_3 = 16'h0000;
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input [3:0] AD;
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input [3:0] DI;
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output [3:0] DO;
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input CLK;
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input WRE;
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specify
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(AD *> DO) = (270, 405);
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$setup(DI, posedge CLK, 62);
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$setup(WRE, posedge CLK, 62);
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$setup(AD, posedge CLK, 62);
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(posedge CLK => (DO : 4'bx)) = (474, 565);
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endspecify
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reg [15:0] mem0, mem1, mem2, mem3;
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initial begin
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mem0 = INIT_0;
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mem1 = INIT_1;
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mem2 = INIT_2;
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mem3 = INIT_3;
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end
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assign DO[0] = mem0[AD];
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assign DO[1] = mem1[AD];
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assign DO[2] = mem2[AD];
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assign DO[3] = mem3[AD];
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always @(posedge CLK) begin
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if (WRE) begin
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mem0[AD] <= DI[0];
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mem1[AD] <= DI[1];
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mem2[AD] <= DI[2];
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mem3[AD] <= DI[3];
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end
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end
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endmodule
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module RAM16SDP1 (DO, DI, WAD, RAD, WRE, CLK);
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parameter INIT_0 = 16'h0000;
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input [3:0] WAD;
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input [3:0] RAD;
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input DI;
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output DO;
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input CLK;
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input WRE;
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specify
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(RAD *> DO) = (270, 405);
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$setup(DI, posedge CLK, 62);
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$setup(WRE, posedge CLK, 62);
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$setup(WAD, posedge CLK, 62);
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(posedge CLK => (DO : 1'bx)) = (474, 565);
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endspecify
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reg [15:0] mem;
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initial begin
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mem = INIT_0;
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end
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assign DO = mem[RAD];
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always @(posedge CLK) begin
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if (WRE) begin
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mem[WAD] <= DI;
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end
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end
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endmodule
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module RAM16SDP2 (DO, DI, WAD, RAD, WRE, CLK);
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parameter INIT_0 = 16'h0000;
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parameter INIT_1 = 16'h0000;
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input [3:0] WAD;
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input [3:0] RAD;
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input [1:0] DI;
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output [1:0] DO;
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input CLK;
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input WRE;
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specify
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(RAD *> DO) = (270, 405);
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$setup(DI, posedge CLK, 62);
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$setup(WRE, posedge CLK, 62);
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$setup(WAD, posedge CLK, 62);
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(posedge CLK => (DO : 2'bx)) = (474, 565);
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endspecify
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reg [15:0] mem0, mem1;
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initial begin
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mem0 = INIT_0;
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mem1 = INIT_1;
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end
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assign DO[0] = mem0[RAD];
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assign DO[1] = mem1[RAD];
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always @(posedge CLK) begin
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if (WRE) begin
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mem0[WAD] <= DI[0];
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mem1[WAD] <= DI[1];
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end
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end
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endmodule
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module RAM16SDP4 (DO, DI, WAD, RAD, WRE, CLK);
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parameter INIT_0 = 16'h0000;
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parameter INIT_1 = 16'h0000;
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parameter INIT_2 = 16'h0000;
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parameter INIT_3 = 16'h0000;
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input [3:0] WAD;
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input [3:0] RAD;
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input [3:0] DI;
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output [3:0] DO;
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input CLK;
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input WRE;
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specify
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(RAD *> DO) = (270, 405);
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$setup(DI, posedge CLK, 62);
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$setup(WRE, posedge CLK, 62);
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$setup(WAD, posedge CLK, 62);
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(posedge CLK => (DO : 4'bx)) = (474, 565);
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endspecify
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reg [15:0] mem0, mem1, mem2, mem3;
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initial begin
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mem0 = INIT_0;
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mem1 = INIT_1;
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mem2 = INIT_2;
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mem3 = INIT_3;
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end
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assign DO[0] = mem0[RAD];
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assign DO[1] = mem1[RAD];
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assign DO[2] = mem2[RAD];
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assign DO[3] = mem3[RAD];
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always @(posedge CLK) begin
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if (WRE) begin
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mem0[WAD] <= DI[0];
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mem1[WAD] <= DI[1];
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mem2[WAD] <= DI[2];
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mem3[WAD] <= DI[3];
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end
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end
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endmodule
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(* blackbox *)
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@ -15,13 +15,14 @@ module \$__GW1NR_RAM16S4 (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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`include "brams_init3.vh"
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RAM16S4
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RAM16SDP4
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#(.INIT_0(INIT_0),
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.INIT_1(INIT_1),
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.INIT_2(INIT_2),
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.INIT_3(INIT_3))
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_TECHMAP_REPLACE_
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(.AD(B1ADDR),
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(.WAD(B1ADDR),
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.RAD(A1ADDR),
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.DI(B1DATA),
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.DO(A1DATA),
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.CLK(CLK1),
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@ -7,12 +7,11 @@ memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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#ERROR: Called with -verify and proof did fail!
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#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
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sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
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sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w1r
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select -assert-count 8 t:RAM16S4
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select -assert-count 8 t:RAM16SDP4
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# other logic present that is not simple
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#select -assert-none t:RAM16S4 %% t:* %D
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