3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 00:55:32 +00:00

gowin: Fix LUT RAM inference, add more models.

This commit is contained in:
Marcelina Kościelnicka 2022-02-09 06:13:34 +01:00
parent ac2bb70b52
commit f61f2a4078
3 changed files with 244 additions and 45 deletions

View file

@ -7,12 +7,11 @@ memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#ERROR: Called with -verify and proof did fail!
#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd lutram_1w1r
select -assert-count 8 t:RAM16S4
select -assert-count 8 t:RAM16SDP4
# other logic present that is not simple
#select -assert-none t:RAM16S4 %% t:* %D