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This commit is contained in:
Emil J. Tywoniak 2026-06-10 19:22:53 +02:00
parent 015ab4e45b
commit f592f2f3af
203 changed files with 4575 additions and 4481 deletions
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36
techlibs/xilinx/xilinx_dffopt.cc
View file

@ -146,11 +146,11 @@ struct XilinxDffOptPass : public Pass {
if (cell->get_bool_attribute(ID::keep))
continue;
if (cell->type == ID(INV)) {
SigBit sigout = sigmap(cell->getPort(ID::O));
SigBit sigin = sigmap(cell->getPort(ID::I));
SigBit sigout = sigmap(cell->getPort(TW::O));
SigBit sigin = sigmap(cell->getPort(TW::I));
bit_to_lut[sigout] = make_pair(LutData(Const(1, 2), {sigin}), cell);
} else if (cell->type.in(ID(LUT1), ID(LUT2), ID(LUT3), ID(LUT4), ID(LUT5), ID(LUT6))) {
SigBit sigout = sigmap(cell->getPort(ID::O));
SigBit sigout = sigmap(cell->getPort(TW::O));
const Const &init = cell->getParam(ID::INIT);
std::vector<SigBit> sigin;
sigin.push_back(sigmap(cell->getPort(ID(I0))));
@ -199,7 +199,7 @@ lut_sigin_done:
continue;
// Don't bother if D has more than one use.
SigBit sig_D = sigmap(cell->getPort(ID::D));
SigBit sig_D = sigmap(cell->getPort(TW::D));
if (bit_uses[sig_D] > 2)
continue;
@ -223,7 +223,7 @@ lut_sigin_done:
bool worthy_post_r = false;
// First, unmap CE.
SigBit sig_Q = sigmap(cell->getPort(ID::Q));
SigBit sig_Q = sigmap(cell->getPort(TW::Q));
SigBit sig_CE = sigmap(cell->getPort(ID(CE)));
LutData lut_ce = LutData(Const(2, 2), {sig_CE});
auto it_CE = bit_to_lut.find(sig_CE);
@ -247,7 +247,7 @@ lut_sigin_done:
// Second, unmap S, if any.
lut_d_post_s = lut_d_post_ce;
if (has_s) {
SigBit sig_S = sigmap(cell->getPort(ID::S));
SigBit sig_S = sigmap(cell->getPort(TW::S));
LutData lut_s = LutData(Const(2, 2), {sig_S});
bool inv_s = cell->hasParam(ID(IS_S_INVERTED)) && cell->getParam(ID(IS_S_INVERTED)).as_bool();
auto it_S = bit_to_lut.find(sig_S);
@ -269,7 +269,7 @@ lut_sigin_done:
// Third, unmap R, if any.
lut_d_post_r = lut_d_post_s;
if (has_r) {
SigBit sig_R = sigmap(cell->getPort(ID::R));
SigBit sig_R = sigmap(cell->getPort(TW::R));
LutData lut_r = LutData(Const(2, 2), {sig_R});
bool inv_r = cell->hasParam(ID(IS_R_INVERTED)) && cell->getParam(ID(IS_R_INVERTED)).as_bool();
auto it_R = bit_to_lut.find(sig_R);
@ -310,11 +310,11 @@ unmap:
// Okay, we're doing it. Unmap ports.
if (worthy_post_r) {
cell->unsetParam(ID(IS_R_INVERTED));
cell->setPort(ID::R, Const(0, 1));
cell->setPort(TW::R, Const(0, 1));
}
if (has_s && (worthy_post_r || worthy_post_s)) {
cell->unsetParam(ID(IS_S_INVERTED));
cell->setPort(ID::S, Const(0, 1));
cell->setPort(TW::S, Const(0, 1));
}
cell->setPort(ID(CE), Const(1, 1));
cell->unsetParam(ID(IS_D_INVERTED));
@ -323,31 +323,31 @@ unmap:
Cell *lut_cell = 0;
switch (GetSize(final_lut.second)) {
case 1:
lut_cell = module->addCell(NEW_ID, ID(LUT1));
lut_cell = module->addCell(NEW_TWINE, ID(LUT1));
break;
case 2:
lut_cell = module->addCell(NEW_ID, ID(LUT2));
lut_cell = module->addCell(NEW_TWINE, ID(LUT2));
break;
case 3:
lut_cell = module->addCell(NEW_ID, ID(LUT3));
lut_cell = module->addCell(NEW_TWINE, ID(LUT3));
break;
case 4:
lut_cell = module->addCell(NEW_ID, ID(LUT4));
lut_cell = module->addCell(NEW_TWINE, ID(LUT4));
break;
case 5:
lut_cell = module->addCell(NEW_ID, ID(LUT5));
lut_cell = module->addCell(NEW_TWINE, ID(LUT5));
break;
case 6:
lut_cell = module->addCell(NEW_ID, ID(LUT6));
lut_cell = module->addCell(NEW_TWINE, ID(LUT6));
break;
default:
log_assert(!"unknown lut size");
}
lut_cell->attributes = cell_d->attributes;
Wire *lut_out = module->addWire(NEW_ID);
Wire *lut_out = module->addWire(NEW_TWINE);
lut_cell->setParam(ID::INIT, final_lut.first);
cell->setPort(ID::D, lut_out);
lut_cell->setPort(ID::O, lut_out);
cell->setPort(TW::D, lut_out);
lut_cell->setPort(TW::O, lut_out);
lut_cell->setPort(ID(I0), final_lut.second[0]);
if (GetSize(final_lut.second) >= 2)
lut_cell->setPort(ID(I1), final_lut.second[1]);

150
techlibs/xilinx/xilinx_dsp.cc
View file

@ -31,7 +31,7 @@ PRIVATE_NAMESPACE_BEGIN
#include "techlibs/xilinx/xilinx_dsp_cascade_pm.h"
static Cell* addDsp(Module *module) {
Cell *cell = module->addCell(NEW_ID, ID(DSP48E1));
Cell *cell = module->addCell(NEW_TWINE, ID(DSP48E1));
cell->setParam(ID(ACASCREG), 0);
cell->setParam(ID(ADREG), 0);
cell->setParam(ID(A_INPUT), Const("DIRECT"));
@ -52,7 +52,7 @@ static Cell* addDsp(Module *module) {
cell->setParam(ID(USE_SIMD), Const("ONE48"));
cell->setParam(ID(USE_DPORT), Const("FALSE"));
cell->setPort(ID::D, Const(0, 25));
cell->setPort(TW::D, Const(0, 25));
cell->setPort(ID(INMODE), Const(0, 5));
cell->setPort(ID(ALUMODE), Const(0, 4));
cell->setPort(ID(OPMODE), Const(0, 7));
@ -117,13 +117,13 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
for (auto cell : selected_cells) {
if (!cell->type.in(ID($add), ID($sub)))
continue;
SigSpec Y = cell->getPort(ID::Y);
SigSpec Y = cell->getPort(TW::Y);
if (!is_allowed(Y, simds))
continue;
if (GetSize(Y) > 25)
continue;
SigSpec A = cell->getPort(ID::A);
SigSpec B = cell->getPort(ID::B);
SigSpec A = cell->getPort(TW::A);
SigSpec B = cell->getPort(TW::B);
if (GetSize(Y) <= 13) {
if (GetSize(A) > 12)
continue;
@ -149,15 +149,15 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
}
auto f12 = [module](SigSpec &AB, SigSpec &C, SigSpec &P, SigSpec &CARRYOUT, Cell *lane) {
SigSpec A = lane->getPort(ID::A);
SigSpec B = lane->getPort(ID::B);
SigSpec Y = lane->getPort(ID::Y);
SigSpec A = lane->getPort(TW::A);
SigSpec B = lane->getPort(TW::B);
SigSpec Y = lane->getPort(TW::Y);
A.extend_u0(12, lane->getParam(ID::A_SIGNED).as_bool());
B.extend_u0(12, lane->getParam(ID::B_SIGNED).as_bool());
AB.append(A);
C.append(B);
if (GetSize(Y) < 13)
Y.append(module->addWire(NEW_ID, 13-GetSize(Y)));
Y.append(module->addWire(NEW_TWINE, 13-GetSize(Y)));
else
log_assert(GetSize(Y) == 13);
P.append(Y.extract(0, 12));
@ -203,24 +203,24 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
else {
AB.append(Const(0, 12));
C.append(Const(0, 12));
P.append(module->addWire(NEW_ID, 12));
CARRYOUT.append(module->addWire(NEW_ID, 1));
P.append(module->addWire(NEW_TWINE, 12));
CARRYOUT.append(module->addWire(NEW_TWINE, 1));
}
}
else {
AB.append(Const(0, 24));
C.append(Const(0, 24));
P.append(module->addWire(NEW_ID, 24));
CARRYOUT.append(module->addWire(NEW_ID, 2));
P.append(module->addWire(NEW_TWINE, 24));
CARRYOUT.append(module->addWire(NEW_TWINE, 2));
}
log_assert(GetSize(AB) == 48);
log_assert(GetSize(C) == 48);
log_assert(GetSize(P) == 48);
log_assert(GetSize(CARRYOUT) == 4);
cell->setPort(ID::A, AB.extract(18, 30));
cell->setPort(ID::B, AB.extract(0, 18));
cell->setPort(ID::C, C);
cell->setPort(ID::P, P);
cell->setPort(TW::A, AB.extract(18, 30));
cell->setPort(TW::B, AB.extract(0, 18));
cell->setPort(TW::C, C);
cell->setPort(TW::P, P);
cell->setPort(ID(CARRYOUT), CARRYOUT);
if (lane1->type == ID($sub))
cell->setPort(ID(ALUMODE), Const::from_string("0011"));
@ -237,19 +237,19 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
g12(simd12_sub);
auto f24 = [module](SigSpec &AB, SigSpec &C, SigSpec &P, SigSpec &CARRYOUT, Cell *lane) {
SigSpec A = lane->getPort(ID::A);
SigSpec B = lane->getPort(ID::B);
SigSpec Y = lane->getPort(ID::Y);
SigSpec A = lane->getPort(TW::A);
SigSpec B = lane->getPort(TW::B);
SigSpec Y = lane->getPort(TW::Y);
A.extend_u0(24, lane->getParam(ID::A_SIGNED).as_bool());
B.extend_u0(24, lane->getParam(ID::B_SIGNED).as_bool());
C.append(A);
AB.append(B);
if (GetSize(Y) < 25)
Y.append(module->addWire(NEW_ID, 25-GetSize(Y)));
Y.append(module->addWire(NEW_TWINE, 25-GetSize(Y)));
else
log_assert(GetSize(Y) == 25);
P.append(Y.extract(0, 24));
CARRYOUT.append(module->addWire(NEW_ID)); // TWO24 uses every other bit
CARRYOUT.append(module->addWire(NEW_TWINE)); // TWO24 uses every other bit
CARRYOUT.append(Y[24]);
};
auto g24 = [&f24,module](std::deque<Cell*> &simd24) {
@ -281,10 +281,10 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
log_assert(GetSize(C) == 48);
log_assert(GetSize(P) == 48);
log_assert(GetSize(CARRYOUT) == 4);
cell->setPort(ID::A, AB.extract(18, 30));
cell->setPort(ID::B, AB.extract(0, 18));
cell->setPort(ID::C, C);
cell->setPort(ID::P, P);
cell->setPort(TW::A, AB.extract(18, 30));
cell->setPort(TW::B, AB.extract(0, 18));
cell->setPort(TW::C, C);
cell->setPort(TW::P, P);
cell->setPort(ID(CARRYOUT), CARRYOUT);
if (lane1->type == ID($sub))
cell->setPort(ID(ALUMODE), Const::from_string("0011"));
@ -328,12 +328,12 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
log(" preadder %s (%s)\n", preAdder, preAdder->type.unescape());
bool A_SIGNED = preAdder->getParam(ID::A_SIGNED).as_bool();
bool D_SIGNED = preAdder->getParam(ID::B_SIGNED).as_bool();
if (st.sigA == preAdder->getPort(ID::B))
if (st.sigA == preAdder->getPort(TW::B))
std::swap(A_SIGNED, D_SIGNED);
st.sigA.extend_u0(30, A_SIGNED);
st.sigD.extend_u0(25, D_SIGNED);
cell->setPort(ID::A, st.sigA);
cell->setPort(ID::D, st.sigD);
cell->setPort(TW::A, st.sigA);
cell->setPort(TW::D, st.sigD);
if (preAdder->type == ID($add))
cell->setPort(ID(INMODE), Const::from_string("00100"));
else
@ -342,7 +342,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
if (st.ffAD) {
if (st.ffAD->type.in(ID($dffe), ID($sdffe))) {
bool pol = st.ffAD->getParam(ID::EN_POLARITY).as_bool();
SigSpec S = st.ffAD->getPort(ID::EN);
SigSpec S = st.ffAD->getPort(TW::EN);
cell->setPort(ID(CEAD), pol ? S : pm.module->Not(NEW_ID, S));
}
else
@ -360,7 +360,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
SigSpec &opmode = cell->connections_.at(ID(OPMODE));
if (st.postAddMux) {
log_assert(st.ffP);
opmode[4] = st.postAddMux->getPort(ID::S);
opmode[4] = st.postAddMux->getPort(TW::S);
pm.autoremove(st.postAddMux);
}
else if (st.ffP && st.sigC == st.sigP)
@ -375,7 +375,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
st.sigC.extend_u0(48, st.postAdd->getParam(ID::B_SIGNED).as_bool());
else
st.sigC.extend_u0(48, st.postAdd->getParam(ID::A_SIGNED).as_bool());
cell->setPort(ID::C, st.sigC);
cell->setPort(TW::C, st.sigC);
}
pm.autoremove(st.postAdd);
@ -387,7 +387,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
cell->setParam(ID(SEL_MASK), Const("MASK"));
if (st.overflow->type == ID($ge)) {
Const B = st.overflow->getPort(ID::B).as_const();
Const B = st.overflow->getPort(TW::B).as_const();
log_assert(std::count(B.begin(), B.end(), State::S1) == 1);
// Since B is an exact power of 2, subtract 1
// by inverting all bits up until hitting
@ -402,7 +402,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
cell->setParam(ID(MASK), B);
cell->setParam(ID(PATTERN), Const(0, 48));
cell->setPort(ID(OVERFLOW), st.overflow->getPort(ID::Y));
cell->setPort(ID(OVERFLOW), st.overflow->getPort(TW::Y));
}
else log_abort();
@ -411,16 +411,16 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
if (st.clock != SigBit())
{
cell->setPort(ID::CLK, st.clock);
cell->setPort(TW::CLK, st.clock);
auto f = [&pm,cell](SigSpec &A, Cell* ff, IdString ceport, IdString rstport) {
SigSpec D = ff->getPort(ID::D);
SigSpec Q = (*pm.sigmap)(ff->getPort(ID::Q));
SigSpec D = ff->getPort(TW::D);
SigSpec Q = (*pm.sigmap)(ff->getPort(TW::Q));
if (!A.empty())
A.replace(Q, D);
if (rstport != IdString()) {
if (ff->type.in(ID($sdff), ID($sdffe))) {
SigSpec srst = ff->getPort(ID::SRST);
SigSpec srst = ff->getPort(TW::SRST);
bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool();
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_ID, srst));
} else {
@ -428,7 +428,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
}
}
if (ff->type.in(ID($dffe), ID($sdffe))) {
SigSpec ce = ff->getPort(ID::EN);
SigSpec ce = ff->getPort(TW::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
}
@ -447,7 +447,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
};
if (st.ffA2) {
SigSpec A = cell->getPort(ID::A);
SigSpec A = cell->getPort(TW::A);
f(A, st.ffA2, ID(CEA2), ID(RSTA));
if (st.ffA1) {
f(A, st.ffA1, ID(CEA1), IdString());
@ -459,10 +459,10 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
cell->setParam(ID(ACASCREG), 1);
}
pm.add_siguser(A, cell);
cell->setPort(ID::A, A);
cell->setPort(TW::A, A);
}
if (st.ffB2) {
SigSpec B = cell->getPort(ID::B);
SigSpec B = cell->getPort(TW::B);
f(B, st.ffB2, ID(CEB2), ID(RSTB));
if (st.ffB1) {
f(B, st.ffB1, ID(CEB1), IdString());
@ -474,25 +474,25 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
cell->setParam(ID(BCASCREG), 1);
}
pm.add_siguser(B, cell);
cell->setPort(ID::B, B);
cell->setPort(TW::B, B);
}
if (st.ffD) {
SigSpec D = cell->getPort(ID::D);
SigSpec D = cell->getPort(TW::D);
f(D, st.ffD, ID(CED), ID(RSTD));
pm.add_siguser(D, cell);
cell->setPort(ID::D, D);
cell->setPort(TW::D, D);
cell->setParam(ID(DREG), 1);
}
if (st.ffM) {
SigSpec M; // unused
f(M, st.ffM, ID(CEM), ID(RSTM));
st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_TWINE, GetSize(st.sigM)));
cell->setParam(ID(MREG), State::S1);
}
if (st.ffP) {
SigSpec P; // unused
f(P, st.ffP, ID(CEP), ID(RSTP));
st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_TWINE, GetSize(st.sigP)));
cell->setParam(ID(PREG), State::S1);
}
@ -526,8 +526,8 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
SigSpec P = st.sigP;
if (GetSize(P) < 48)
P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
cell->setPort(ID::P, P);
P.append(pm.module->addWire(NEW_TWINE, 48-GetSize(P)));
cell->setPort(TW::P, P);
pm.blacklist(cell);
}
@ -559,8 +559,8 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
bool B_SIGNED = st.preAdd->getParam(ID::B_SIGNED).as_bool();
st.sigB.extend_u0(18, B_SIGNED);
st.sigD.extend_u0(18, D_SIGNED);
cell->setPort(ID::B, st.sigB);
cell->setPort(ID::D, st.sigD);
cell->setPort(TW::B, st.sigB);
cell->setPort(TW::D, st.sigD);
opmode[4] = State::S1;
if (st.preAdd->type == ID($add))
opmode[6] = State::S0;
@ -576,7 +576,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
if (st.postAddMux) {
log_assert(st.ffP);
opmode[2] = st.postAddMux->getPort(ID::S);
opmode[2] = st.postAddMux->getPort(TW::S);
pm.autoremove(st.postAddMux);
}
else if (st.ffP && st.sigC == st.sigP)
@ -590,7 +590,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
st.sigC.extend_u0(48, st.postAdd->getParam(ID::B_SIGNED).as_bool());
else
st.sigC.extend_u0(48, st.postAdd->getParam(ID::A_SIGNED).as_bool());
cell->setPort(ID::C, st.sigC);
cell->setPort(TW::C, st.sigC);
}
pm.autoremove(st.postAdd);
@ -598,16 +598,16 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
if (st.clock != SigBit())
{
cell->setPort(ID::CLK, st.clock);
cell->setPort(TW::CLK, st.clock);
auto f = [&pm,cell](SigSpec &A, Cell* ff, IdString ceport, IdString rstport) {
SigSpec D = ff->getPort(ID::D);
SigSpec Q = (*pm.sigmap)(ff->getPort(ID::Q));
SigSpec D = ff->getPort(TW::D);
SigSpec Q = (*pm.sigmap)(ff->getPort(TW::Q));
if (!A.empty())
A.replace(Q, D);
if (rstport != IdString()) {
if (ff->type.in(ID($sdff), ID($sdffe))) {
SigSpec srst = ff->getPort(ID::SRST);
SigSpec srst = ff->getPort(TW::SRST);
bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool();
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_ID, srst));
} else {
@ -615,7 +615,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
}
}
if (ff->type.in(ID($dffe), ID($sdffe))) {
SigSpec ce = ff->getPort(ID::EN);
SigSpec ce = ff->getPort(TW::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
}
@ -634,7 +634,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
};
if (st.ffA0 || st.ffA1) {
SigSpec A = cell->getPort(ID::A);
SigSpec A = cell->getPort(TW::A);
if (st.ffA1) {
f(A, st.ffA1, ID(CEA), ID(RSTA));
cell->setParam(ID(A1REG), 1);
@ -644,10 +644,10 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
cell->setParam(ID(A0REG), 1);
}
pm.add_siguser(A, cell);
cell->setPort(ID::A, A);
cell->setPort(TW::A, A);
}
if (st.ffB0 || st.ffB1) {
SigSpec B = cell->getPort(ID::B);
SigSpec B = cell->getPort(TW::B);
if (st.ffB1) {
f(B, st.ffB1, ID(CEB), ID(RSTB));
cell->setParam(ID(B1REG), 1);
@ -657,25 +657,25 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
cell->setParam(ID(B0REG), 1);
}
pm.add_siguser(B, cell);
cell->setPort(ID::B, B);
cell->setPort(TW::B, B);
}
if (st.ffD) {
SigSpec D = cell->getPort(ID::D);
SigSpec D = cell->getPort(TW::D);
f(D, st.ffD, ID(CED), ID(RSTD));
pm.add_siguser(D, cell);
cell->setPort(ID::D, D);
cell->setPort(TW::D, D);
cell->setParam(ID(DREG), 1);
}
if (st.ffM) {
SigSpec M; // unused
f(M, st.ffM, ID(CEM), ID(RSTM));
st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_TWINE, GetSize(st.sigM)));
cell->setParam(ID(MREG), State::S1);
}
if (st.ffP) {
SigSpec P; // unused
f(P, st.ffP, ID(CEP), ID(RSTP));
st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_TWINE, GetSize(st.sigP)));
cell->setParam(ID(PREG), State::S1);
}
@ -704,8 +704,8 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
SigSpec P = st.sigP;
if (GetSize(P) < 48)
P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
cell->setPort(ID::P, P);
P.append(pm.module->addWire(NEW_TWINE, 48-GetSize(P)));
cell->setPort(TW::P, P);
pm.blacklist(cell);
}
@ -721,16 +721,16 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
if (st.clock != SigBit())
{
cell->setPort(ID::CLK, st.clock);
cell->setPort(TW::CLK, st.clock);
auto f = [&pm,cell](SigSpec &A, Cell* ff, IdString ceport, IdString rstport) {
SigSpec D = ff->getPort(ID::D);
SigSpec Q = (*pm.sigmap)(ff->getPort(ID::Q));
SigSpec D = ff->getPort(TW::D);
SigSpec Q = (*pm.sigmap)(ff->getPort(TW::Q));
if (!A.empty())
A.replace(Q, D);
if (rstport != IdString()) {
if (ff->type.in(ID($sdff), ID($sdffe))) {
SigSpec srst = ff->getPort(ID::SRST);
SigSpec srst = ff->getPort(TW::SRST);
bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool();
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_ID, srst));
} else {
@ -738,7 +738,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
}
}
if (ff->type.in(ID($dffe), ID($sdffe))) {
SigSpec ce = ff->getPort(ID::EN);
SigSpec ce = ff->getPort(TW::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
}
@ -757,10 +757,10 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
};
if (st.ffC) {
SigSpec C = cell->getPort(ID::C);
SigSpec C = cell->getPort(TW::C);
f(C, st.ffC, ID(CEC), ID(RSTC));
pm.add_siguser(C, cell);
cell->setPort(ID::C, C);
cell->setPort(TW::C, C);
cell->setParam(ID(CREG), 1);
}

6
techlibs/xilinx/xilinx_dsp_cascade.pmg
View file

@ -89,7 +89,7 @@ finally
if (i % MAX_DSP_CASCADE > 0) {
if (P >= 0) {
Wire *cascade = module->addWire(NEW_ID, 48);
Wire *cascade = module->addWire(NEW_TWINE, 48);
dsp_pcin->setPort(\C, Const(0, 48));
dsp_pcin->setPort(\PCIN, cascade);
dsp->setPort(\PCOUT, cascade);
@ -117,7 +117,7 @@ finally
log_debug("PCOUT -> PCIN cascade for %s -> %s\n", dsp, dsp_pcin);
}
if (AREG >= 0) {
Wire *cascade = module->addWire(NEW_ID, 30);
Wire *cascade = module->addWire(NEW_TWINE, 30);
dsp_pcin->setPort(\A, Const(0, 30));
dsp_pcin->setPort(\ACIN, cascade);
dsp->setPort(\ACOUT, cascade);
@ -131,7 +131,7 @@ finally
log_debug("ACOUT -> ACIN cascade for %s -> %s\n", dsp, dsp_pcin);
}
if (BREG >= 0) {
Wire *cascade = module->addWire(NEW_ID, 18);
Wire *cascade = module->addWire(NEW_TWINE, 18);
if (dsp->type.in(\DSP48A, \DSP48A1)) {
// According to UG389 p9 [https://www.xilinx.com/support/documentation/user_guides/ug389.pdf]
// "The DSP48A1 component uses this input when cascading

38
techlibs/xilinx/xilinx_srl.cc
View file

@ -36,7 +36,7 @@ void run_fixed(xilinx_srl_pm &pm)
for (auto cell : ud.longest_chain) {
log_debug(" %s\n", cell);
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) {
SigBit Q = cell->getPort(ID::Q);
SigBit Q = cell->getPort(TW::Q);
log_assert(Q.wire);
auto it = Q.wire->attributes.find(ID::init);
if (it != Q.wire->attributes.end()) {
@ -59,7 +59,7 @@ void run_fixed(xilinx_srl_pm &pm)
auto first_cell = ud.longest_chain.back();
auto last_cell = ud.longest_chain.front();
Cell *c = pm.module->addCell(NEW_ID, ID($__XILINX_SHREG_));
Cell *c = pm.module->addCell(NEW_TWINE, ID($__XILINX_SHREG_));
pm.module->swap_names(c, first_cell);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) {
@ -84,16 +84,16 @@ void run_fixed(xilinx_srl_pm &pm)
else
c->setParam(ID(ENPOL), 2);
c->setPort(ID::C, first_cell->getPort(ID::C));
c->setPort(ID::D, first_cell->getPort(ID::D));
c->setPort(ID::Q, last_cell->getPort(ID::Q));
c->setPort(ID::L, GetSize(ud.longest_chain)-1);
c->setPort(TW::C, first_cell->getPort(TW::C));
c->setPort(TW::D, first_cell->getPort(TW::D));
c->setPort(TW::Q, last_cell->getPort(TW::Q));
c->setPort(TW::L, GetSize(ud.longest_chain)-1);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
c->setPort(ID::E, State::S1);
c->setPort(TW::E, State::S1);
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
c->setPort(ID::E, first_cell->getPort(ID::E));
c->setPort(TW::E, first_cell->getPort(TW::E));
else if (first_cell->type.in(ID(FDRE), ID(FDRE_1)))
c->setPort(ID::E, first_cell->getPort(ID(CE)));
c->setPort(TW::E, first_cell->getPort(ID(CE)));
else
log_abort();
}
@ -116,7 +116,7 @@ void run_variable(xilinx_srl_pm &pm)
auto slice = i.second;
log_debug(" %s\n", cell);
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
SigBit Q = cell->getPort(ID::Q)[slice];
SigBit Q = cell->getPort(TW::Q)[slice];
log_assert(Q.wire);
auto it = Q.wire->attributes.find(ID::init);
if (it != Q.wire->attributes.end()) {
@ -134,7 +134,7 @@ void run_variable(xilinx_srl_pm &pm)
auto first_cell = ud.chain.back().first;
auto first_slice = ud.chain.back().second;
Cell *c = pm.module->addCell(NEW_ID, ID($__XILINX_SHREG_));
Cell *c = pm.module->addCell(NEW_TWINE, ID($__XILINX_SHREG_));
pm.module->swap_names(c, first_cell);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
@ -161,20 +161,20 @@ void run_variable(xilinx_srl_pm &pm)
c->setParam(ID(ENPOL), enpol);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
c->setPort(ID::C, first_cell->getPort(ID::C));
c->setPort(TW::C, first_cell->getPort(TW::C));
else if (first_cell->type.in(ID($dff), ID($dffe)))
c->setPort(ID::C, first_cell->getPort(ID::CLK));
c->setPort(TW::C, first_cell->getPort(TW::CLK));
else
log_abort();
c->setPort(ID::D, first_cell->getPort(ID::D)[first_slice]);
c->setPort(ID::Q, st.shiftx->getPort(ID::Y));
c->setPort(ID::L, st.shiftx->getPort(ID::B));
c->setPort(TW::D, first_cell->getPort(TW::D)[first_slice]);
c->setPort(TW::Q, st.shiftx->getPort(TW::Y));
c->setPort(TW::L, st.shiftx->getPort(TW::B));
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($dff)))
c->setPort(ID::E, State::S1);
c->setPort(TW::E, State::S1);
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
c->setPort(ID::E, first_cell->getPort(ID::E));
c->setPort(TW::E, first_cell->getPort(TW::E));
else if (first_cell->type.in(ID($dffe)))
c->setPort(ID::E, first_cell->getPort(ID::EN));
c->setPort(TW::E, first_cell->getPort(TW::EN));
else
log_abort();
}

34
techlibs/xilinx/xilinx_srl.pmg
View file

@ -18,22 +18,22 @@ match first
select !first->type.in(\FDRE, \FDRE_1) || port(first, \R, State::S0).is_fully_zero()
filter !non_first_cells.count(first)
generate
SigSpec C = module->addWire(NEW_ID);
SigSpec D = module->addWire(NEW_ID);
SigSpec Q = module->addWire(NEW_ID);
SigSpec C = module->addWire(NEW_TWINE);
SigSpec D = module->addWire(NEW_TWINE);
SigSpec Q = module->addWire(NEW_TWINE);
auto r = rng(8);
Cell* cell;
switch (r)
{
case 0:
case 1:
cell = module->addCell(NEW_ID, \FDRE);
cell = module->addCell(NEW_TWINE, \FDRE);
cell->setPort(\C, C);
cell->setPort(\D, D);
cell->setPort(\Q, Q);
cell->setPort(\CE, module->addWire(NEW_ID));
cell->setPort(\CE, module->addWire(NEW_TWINE));
if (r & 1)
cell->setPort(\R, module->addWire(NEW_ID));
cell->setPort(\R, module->addWire(NEW_TWINE));
else {
if (rng(2) == 0)
cell->setPort(\R, State::S0);
@ -47,7 +47,7 @@ generate
case 5:
case 6:
case 7:
cell = module->addDffeGate(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 2);
cell = module->addDffeGate(NEW_ID, C, module->addWire(NEW_TWINE), D, Q, r & 1, r & 2);
break;
default: log_abort();
}
@ -143,9 +143,9 @@ match next
filter !first->type.in(\FDRE) || param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool()
filter !first->type.in(\FDRE, \FDRE_1) || port(next, \R, State::S0).is_fully_zero()
generate
Cell *cell = module->addCell(NEW_ID, chain.back()->type);
Cell *cell = module->addCell(NEW_TWINE, chain.back()->type);
cell->setPort(\C, chain.back()->getPort(\C));
cell->setPort(\D, module->addWire(NEW_ID));
cell->setPort(\D, module->addWire(NEW_TWINE));
cell->setPort(\Q, chain.back()->getPort(\D));
if (cell->type == \FDRE) {
if (rng(2) == 0)
@ -191,7 +191,7 @@ match shiftx
filter param(shiftx, \A_WIDTH).as_int() >= minlen
generate
minlen = 3;
module->addShiftx(NEW_ID, module->addWire(NEW_ID, rng(6)+minlen), module->addWire(NEW_ID, 3), module->addWire(NEW_ID));
module->addShiftx(NEW_ID, module->addWire(NEW_TWINE, rng(6)+minlen), module->addWire(NEW_TWINE, 3), module->addWire(NEW_TWINE));
endmatch
code shiftx_width
@ -207,10 +207,10 @@ match first
index <SigBit> port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1]
set slice idx
generate
SigSpec C = module->addWire(NEW_ID);
SigSpec C = module->addWire(NEW_TWINE);
auto WIDTH = rng(3)+1;
SigSpec D = module->addWire(NEW_ID, WIDTH);
SigSpec Q = module->addWire(NEW_ID, WIDTH);
SigSpec D = module->addWire(NEW_TWINE, WIDTH);
SigSpec Q = module->addWire(NEW_TWINE, WIDTH);
auto r = rng(8);
Cell *cell = nullptr;
switch (r)
@ -223,7 +223,7 @@ generate
case 3:
case 4:
case 5:
//cell = module->addDffe(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 4);
//cell = module->addDffe(NEW_ID, C, module->addWire(NEW_TWINE), D, Q, r & 1, r & 4);
//break;
case 6:
case 7:
@ -295,7 +295,7 @@ generate
back->connections_.at(\D)[slice] = port(back, \Q)[new_slice];
}
else {
auto D = module->addWire(NEW_ID, WIDTH);
auto D = module->addWire(NEW_TWINE, WIDTH);
if (back->type == $dff)
module->addDff(NEW_ID, port(back, \CLK), D, port(back, \D), param(back, \CLK_POLARITY).as_bool());
else if (back->type == $dffe)
@ -305,9 +305,9 @@ generate
}
}
else if (back->type.begins_with("$_DFF_")) {
Cell *cell = module->addCell(NEW_ID, back->type);
Cell *cell = module->addCell(NEW_TWINE, back->type);
cell->setPort(\C, back->getPort(\C));
cell->setPort(\D, module->addWire(NEW_ID));
cell->setPort(\D, module->addWire(NEW_TWINE));
cell->setPort(\Q, back->getPort(\D));
}
else