From f592f2f3aff563fe9f2211fe3e8ef0bb963e9650 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 10 Jun 2026 19:22:53 +0200 Subject: [PATCH] WIP --- backends/aiger/aiger.cc | 44 +- backends/aiger/xaiger.cc | 24 +- backends/aiger2/aiger.cc | 46 +- backends/blif/blif.cc | 66 +- backends/btor/btor.cc | 118 +- backends/cxxrtl/cxxrtl_backend.cc | 116 +- backends/firrtl/firrtl.cc | 48 +- backends/simplec/simplec.cc | 36 +- backends/smt2/smt2.cc | 94 +- backends/smv/smv.cc | 146 +- backends/verilog/verilog_backend.cc | 150 +- .../source/code_examples/extensions/my_cmd.cc | 2 +- frontends/aiger/aigerparse.cc | 12 +- frontends/ast/genrtlil.cc | 68 +- frontends/ast/simplify.cc | 2 +- frontends/blif/blifparse.cc | 30 +- frontends/json/jsonparse.cc | 2 +- frontends/liberty/liberty.cc | 126 +- frontends/rtlil/rtlil_frontend.cc | 6 +- guidelines/GettingStarted | 4 +- kernel/cellaigs.cc | 38 +- kernel/cellaigs.h | 2 +- kernel/celledges.cc | 80 +- kernel/celltypes.h | 208 +- kernel/consteval.h | 36 +- kernel/cost.cc | 2 +- kernel/ff.cc | 136 +- kernel/ffmerge.cc | 12 +- kernel/macc.h | 16 +- kernel/mem.cc | 130 +- kernel/modtools.h | 18 +- kernel/newcelltypes.h | 4 +- kernel/pmux.h | 2 +- kernel/rtlil.cc | 1934 ++++++++--------- kernel/rtlil.h | 475 ++-- kernel/rtlil_bufnorm.cc | 97 +- kernel/satgen.cc | 356 +-- kernel/sigtools.h | 4 +- kernel/timinginfo.h | 14 +- kernel/twine.h | 126 ++ kernel/unstable/patch.cc | 87 +- kernel/unstable/patch.h | 31 +- kernel/wallace_tree.h | 4 +- kernel/yosys_common.h | 10 + passes/cmds/abstract.cc | 8 +- passes/cmds/add.cc | 8 +- passes/cmds/bugpoint.cc | 2 +- passes/cmds/check.cc | 10 +- passes/cmds/chformal.cc | 60 +- passes/cmds/clean_zerowidth.cc | 16 +- passes/cmds/connect.cc | 2 +- passes/cmds/dft_tag.cc | 94 +- passes/cmds/future.cc | 2 +- passes/cmds/glift.cc | 8 +- passes/cmds/portarcs.cc | 10 +- passes/cmds/scatter.cc | 2 +- passes/cmds/scc.cc | 4 +- passes/cmds/setundef.cc | 4 +- passes/cmds/splice.cc | 18 +- passes/cmds/splitcells.cc | 30 +- passes/cmds/stat.cc | 24 +- passes/cmds/test_patch.cc | 18 +- passes/cmds/trace.cc | 2 +- passes/cmds/xprop.cc | 180 +- passes/equiv/equiv_add.cc | 8 +- passes/equiv/equiv_induct.cc | 16 +- passes/equiv/equiv_make.cc | 6 +- passes/equiv/equiv_mark.cc | 8 +- passes/equiv/equiv_miter.cc | 10 +- passes/equiv/equiv_purge.cc | 14 +- passes/equiv/equiv_remove.cc | 6 +- passes/equiv/equiv_simple.cc | 20 +- passes/equiv/equiv_status.cc | 4 +- passes/equiv/equiv_struct.cc | 12 +- passes/fsm/fsm_detect.cc | 16 +- passes/fsm/fsm_expand.cc | 46 +- passes/fsm/fsm_extract.cc | 34 +- passes/fsm/fsm_map.cc | 74 +- passes/fsm/fsm_opt.cc | 14 +- passes/fsm/fsmdata.h | 4 +- passes/hierarchy/flatten.cc | 2 +- passes/hierarchy/hierarchy.cc | 8 +- passes/hierarchy/submod.cc | 4 +- passes/memory/memory_bmux2rom.cc | 6 +- passes/memory/memory_bram.cc | 6 +- passes/memory/memory_dff.cc | 10 +- passes/memory/memory_libmap.cc | 16 +- passes/memory/memory_map.cc | 34 +- passes/memory/memory_memx.cc | 2 +- passes/memory/memory_share.cc | 12 +- passes/opt/muxpack.cc | 50 +- passes/opt/opt_balance_tree.cc | 26 +- passes/opt/opt_clean/cells_all.cc | 6 +- passes/opt/opt_clean/cells_temp.cc | 18 +- passes/opt/opt_clean/inits.cc | 4 +- passes/opt/opt_clean/wires.cc | 4 +- passes/opt/opt_demorgan.cc | 14 +- passes/opt/opt_dff.cc | 86 +- passes/opt/opt_expr.cc | 74 +- passes/opt/opt_ffinv.cc | 14 +- passes/opt/opt_hier.cc | 4 +- passes/opt/opt_lut.cc | 28 +- passes/opt/opt_lut_ins.cc | 26 +- passes/opt/opt_mem_feedback.cc | 18 +- passes/opt/opt_merge.cc | 2 +- passes/opt/opt_merge_common.h | 50 +- passes/opt/opt_merge_inc.cc | 2 +- passes/opt/opt_muxtree.cc | 28 +- passes/opt/opt_reduce.cc | 128 +- passes/opt/opt_share.cc | 58 +- passes/opt/peepopt_formal_clockgateff.pmg | 2 +- passes/opt/peepopt_shiftmul_left.pmg | 4 +- passes/opt/pmux2shiftx.cc | 44 +- passes/opt/share.cc | 146 +- passes/opt/wreduce.cc | 60 +- passes/pmgen/README.md | 4 +- passes/pmgen/generate.h | 2 +- passes/pmgen/pmgen.py | 4 +- passes/pmgen/test_pmgen.cc | 16 +- passes/pmgen/test_pmgen.pmg | 28 +- passes/proc/proc_arst.cc | 44 +- passes/proc/proc_dff.cc | 18 +- passes/proc/proc_dlatch.cc | 32 +- passes/proc/proc_memwr.cc | 14 +- passes/proc/proc_mux.cc | 32 +- passes/proc/proc_rom.cc | 2 +- passes/sat/assertpmux.cc | 16 +- passes/sat/async2sync.cc | 40 +- passes/sat/clk2fflogic.cc | 34 +- passes/sat/cutpoint.cc | 8 +- passes/sat/expose.cc | 46 +- passes/sat/fmcombine.cc | 4 +- passes/sat/fminit.cc | 4 +- passes/sat/formalff.cc | 44 +- passes/sat/freduce.cc | 12 +- passes/sat/miter.cc | 78 +- passes/sat/mutate.cc | 6 +- passes/sat/qbfsat.cc | 4 +- passes/sat/qbfsat.h | 6 +- passes/sat/sat.cc | 4 +- passes/sat/sim.cc | 34 +- passes/sat/synthprop.cc | 14 +- passes/techmap/abc.cc | 60 +- passes/techmap/abc9_ops.cc | 104 +- passes/techmap/aigmap.cc | 6 +- passes/techmap/alumacc.cc | 54 +- passes/techmap/arith_tree.cc | 28 +- passes/techmap/bmuxmap.cc | 16 +- passes/techmap/booth.cc | 78 +- passes/techmap/bufnorm.cc | 16 +- passes/techmap/bwmuxmap.cc | 8 +- passes/techmap/clkbufmap.cc | 10 +- passes/techmap/clockgate.cc | 4 +- passes/techmap/constmap.cc | 4 +- passes/techmap/demuxmap.cc | 10 +- passes/techmap/dfflegalize.cc | 14 +- passes/techmap/dfflibmap.cc | 10 +- passes/techmap/extract_counter.cc | 72 +- passes/techmap/extract_fa.cc | 38 +- passes/techmap/extract_reduce.cc | 8 +- passes/techmap/extractinv.cc | 4 +- passes/techmap/flowmap.cc | 2 +- passes/techmap/hilomap.cc | 8 +- passes/techmap/insbuf.cc | 2 +- passes/techmap/iopadmap.cc | 6 +- passes/techmap/lut2bmux.cc | 4 +- passes/techmap/lut2mux.cc | 8 +- passes/techmap/maccmap.cc | 56 +- passes/techmap/muxcover.cc | 104 +- passes/techmap/nlutmap.cc | 2 +- passes/techmap/pmuxtree.cc | 10 +- passes/techmap/shregmap.cc | 10 +- passes/techmap/simplemap.cc | 226 +- passes/techmap/techmap.cc | 2 +- passes/techmap/tribuf.cc | 40 +- passes/tests/test_cell.cc | 106 +- pyosys/wrappers_tpl.cc | 2 +- techlibs/anlogic/anlogic_fixcarry.cc | 6 +- techlibs/common/simlib.v | 2 +- techlibs/coolrunner2/coolrunner2_fixup.cc | 46 +- techlibs/coolrunner2/coolrunner2_sop.cc | 14 +- techlibs/efinix/efinix_fixcarry.cc | 18 +- techlibs/gatemate/gatemate_foldinv.cc | 14 +- techlibs/greenpak4/greenpak4_dffinv.cc | 14 +- techlibs/ice40/ice40_dsp.cc | 50 +- techlibs/ice40/ice40_dsp.pmg | 2 +- techlibs/ice40/ice40_opt.cc | 34 +- techlibs/ice40/ice40_wrapcarry.cc | 28 +- techlibs/lattice/lattice_gsr.cc | 2 +- techlibs/microchip/microchip_dffopt.cc | 24 +- techlibs/microchip/microchip_dsp.cc | 54 +- techlibs/microchip/microchip_dsp_cascade.pmg | 2 +- techlibs/nanoxplore/nx_carry.cc | 8 +- techlibs/quicklogic/ql_bram_merge.cc | 2 +- techlibs/quicklogic/ql_dsp_macc.cc | 4 +- techlibs/quicklogic/ql_dsp_simd.cc | 4 +- techlibs/quicklogic/ql_ioff.cc | 28 +- techlibs/xilinx/xilinx_dffopt.cc | 36 +- techlibs/xilinx/xilinx_dsp.cc | 150 +- techlibs/xilinx/xilinx_dsp_cascade.pmg | 6 +- techlibs/xilinx/xilinx_srl.cc | 38 +- techlibs/xilinx/xilinx_srl.pmg | 34 +- tests/unit/kernel/modindexTest.cc | 2 +- 203 files changed, 4575 insertions(+), 4481 deletions(-) diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index a2dc3a4af..1c7bf3f44 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -223,8 +223,8 @@ struct AigerWriter { if (cell->type == ID($_NOT_)) { - SigBit A = sigmap(cell->getPort(ID::A).as_bit()); - SigBit Y = sigmap(cell->getPort(ID::Y).as_bit()); + SigBit A = sigmap(cell->getPort(TW::A).as_bit()); + SigBit Y = sigmap(cell->getPort(TW::Y).as_bit()); unused_bits.erase(A); undriven_bits.erase(Y); not_map[Y] = A; @@ -233,14 +233,14 @@ struct AigerWriter if (cell->type.in(ID($_FF_), ID($_DFF_N_), ID($_DFF_P_))) { - SigBit D = sigmap(cell->getPort(ID::D).as_bit()); - SigBit Q = sigmap(cell->getPort(ID::Q).as_bit()); + SigBit D = sigmap(cell->getPort(TW::D).as_bit()); + SigBit Q = sigmap(cell->getPort(TW::Q).as_bit()); unused_bits.erase(D); undriven_bits.erase(Q); ff_map[Q] = D; if (cell->type != ID($_FF_)) { - auto sig_clk = sigmap(cell->getPort(ID::C).as_bit()); + auto sig_clk = sigmap(cell->getPort(TW::C).as_bit()); ywmap_clocks[sig_clk] |= cell->type == ID($_DFF_N_) ? 2 : 1; } continue; @@ -248,8 +248,8 @@ struct AigerWriter if (cell->type == ID($anyinit)) { - auto sig_d = sigmap(cell->getPort(ID::D)); - auto sig_q = sigmap(cell->getPort(ID::Q)); + auto sig_d = sigmap(cell->getPort(TW::D)); + auto sig_q = sigmap(cell->getPort(TW::Q)); for (int i = 0; i < sig_d.size(); i++) { undriven_bits.erase(sig_q[i]); ff_map[sig_q[i]] = sig_d[i]; @@ -259,9 +259,9 @@ struct AigerWriter if (cell->type == ID($_AND_)) { - SigBit A = sigmap(cell->getPort(ID::A).as_bit()); - SigBit B = sigmap(cell->getPort(ID::B).as_bit()); - SigBit Y = sigmap(cell->getPort(ID::Y).as_bit()); + SigBit A = sigmap(cell->getPort(TW::A).as_bit()); + SigBit B = sigmap(cell->getPort(TW::B).as_bit()); + SigBit Y = sigmap(cell->getPort(TW::Y).as_bit()); unused_bits.erase(A); unused_bits.erase(B); undriven_bits.erase(Y); @@ -271,7 +271,7 @@ struct AigerWriter if (cell->type == ID($initstate)) { - SigBit Y = sigmap(cell->getPort(ID::Y).as_bit()); + SigBit Y = sigmap(cell->getPort(TW::Y).as_bit()); undriven_bits.erase(Y); initstate_bits.insert(Y); continue; @@ -279,8 +279,8 @@ struct AigerWriter if (cell->type == ID($assert)) { - SigBit A = sigmap(cell->getPort(ID::A).as_bit()); - SigBit EN = sigmap(cell->getPort(ID::EN).as_bit()); + SigBit A = sigmap(cell->getPort(TW::A).as_bit()); + SigBit EN = sigmap(cell->getPort(TW::EN).as_bit()); unused_bits.erase(A); unused_bits.erase(EN); asserts.push_back(make_pair(A, EN)); @@ -290,8 +290,8 @@ struct AigerWriter if (cell->type == ID($assume)) { - SigBit A = sigmap(cell->getPort(ID::A).as_bit()); - SigBit EN = sigmap(cell->getPort(ID::EN).as_bit()); + SigBit A = sigmap(cell->getPort(TW::A).as_bit()); + SigBit EN = sigmap(cell->getPort(TW::EN).as_bit()); unused_bits.erase(A); unused_bits.erase(EN); assumes.push_back(make_pair(A, EN)); @@ -301,8 +301,8 @@ struct AigerWriter if (cell->type == ID($live)) { - SigBit A = sigmap(cell->getPort(ID::A).as_bit()); - SigBit EN = sigmap(cell->getPort(ID::EN).as_bit()); + SigBit A = sigmap(cell->getPort(TW::A).as_bit()); + SigBit EN = sigmap(cell->getPort(TW::EN).as_bit()); unused_bits.erase(A); unused_bits.erase(EN); liveness.push_back(make_pair(A, EN)); @@ -311,8 +311,8 @@ struct AigerWriter if (cell->type == ID($fair)) { - SigBit A = sigmap(cell->getPort(ID::A).as_bit()); - SigBit EN = sigmap(cell->getPort(ID::EN).as_bit()); + SigBit A = sigmap(cell->getPort(TW::A).as_bit()); + SigBit EN = sigmap(cell->getPort(TW::EN).as_bit()); unused_bits.erase(A); unused_bits.erase(EN); fairness.push_back(make_pair(A, EN)); @@ -321,7 +321,7 @@ struct AigerWriter if (cell->type == ID($anyconst)) { - for (auto bit : sigmap(cell->getPort(ID::Y))) { + for (auto bit : sigmap(cell->getPort(TW::Y))) { undriven_bits.erase(bit); ff_map[bit] = bit; } @@ -330,7 +330,7 @@ struct AigerWriter if (cell->type == ID($anyseq)) { - for (auto bit : sigmap(cell->getPort(ID::Y))) { + for (auto bit : sigmap(cell->getPort(TW::Y))) { undriven_bits.erase(bit); input_bits.insert(bit); } @@ -780,7 +780,7 @@ struct AigerWriter SigSpec sig = sigmap(sig_qy); if (cell->get_bool_attribute(ID(clk2fflogic))) - sig_qy = cell->getPort(ID::D); // For a clk2fflogic $_FF_ the named signal is the D input not the Q output + sig_qy = cell->getPort(TW::D); // For a clk2fflogic $_FF_ the named signal is the D input not the Q output for (int i = 0; i < GetSize(sig_qy); i++) { if (sig_qy[i].wire == nullptr || sig[i].wire == nullptr) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index e05357fa1..d316f7737 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -193,8 +193,8 @@ struct XAigerWriter if (!cell->has_keep_attr()) { if (cell->type == ID($_NOT_)) { - SigBit A = sigmap(cell->getPort(ID::A).as_bit()); - SigBit Y = sigmap(cell->getPort(ID::Y).as_bit()); + SigBit A = sigmap(cell->getPort(TW::A).as_bit()); + SigBit Y = sigmap(cell->getPort(TW::Y).as_bit()); unused_bits.erase(A); undriven_bits.erase(Y); not_map[Y] = A; @@ -203,9 +203,9 @@ struct XAigerWriter if (cell->type == ID($_AND_)) { - SigBit A = sigmap(cell->getPort(ID::A).as_bit()); - SigBit B = sigmap(cell->getPort(ID::B).as_bit()); - SigBit Y = sigmap(cell->getPort(ID::Y).as_bit()); + SigBit A = sigmap(cell->getPort(TW::A).as_bit()); + SigBit B = sigmap(cell->getPort(TW::B).as_bit()); + SigBit Y = sigmap(cell->getPort(TW::Y).as_bit()); unused_bits.erase(A); unused_bits.erase(B); undriven_bits.erase(Y); @@ -215,8 +215,8 @@ struct XAigerWriter if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep)) { - SigBit D = sigmap(cell->getPort(ID::D).as_bit()); - SigBit Q = sigmap(cell->getPort(ID::Q).as_bit()); + SigBit D = sigmap(cell->getPort(TW::D).as_bit()); + SigBit Q = sigmap(cell->getPort(TW::Q).as_bit()); unused_bits.erase(D); undriven_bits.erase(Q); alias_map[Q] = D; @@ -413,7 +413,7 @@ struct XAigerWriter } for (auto cell : ff_list) { - const SigBit &q = sigmap(cell->getPort(ID::Q)); + const SigBit &q = sigmap(cell->getPort(TW::Q)); aig_m++, aig_i++; log_assert(!aig_map.count(q)); aig_map[q] = 2*aig_m; @@ -461,7 +461,7 @@ struct XAigerWriter } for (auto cell : ff_list) { - const SigBit &d = sigmap(cell->getPort(ID::D)); + const SigBit &d = sigmap(cell->getPort(TW::D)); aig_o++; aig_outputs.push_back(aig_map.at(d)); } @@ -605,10 +605,10 @@ struct XAigerWriter dict clk_to_mergeability; for (const auto cell : ff_list) { - const SigBit &d = sigmap(cell->getPort(ID::D)); - const SigBit &q = sigmap(cell->getPort(ID::Q)); + const SigBit &d = sigmap(cell->getPort(TW::D)); + const SigBit &q = sigmap(cell->getPort(TW::Q)); - SigSpec clk_and_pol{sigmap(cell->getPort(ID::C)), cell->type[6] == 'P' ? State::S1 : State::S0}; + SigSpec clk_and_pol{sigmap(cell->getPort(TW::C)), cell->type[6] == 'P' ? State::S1 : State::S0}; auto r = clk_to_mergeability.insert(std::make_pair(clk_and_pol, clk_to_mergeability.size()+1)); int mergeability = r.first->second; log_assert(mergeability > 0); diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index eb5ac4a64..bf49214f0 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -283,9 +283,9 @@ struct Index { if (cell->type.in(REDUCE_OPS, LOGIC_OPS, CMP_OPS) && obit != 0) { return CFALSE; } else if (cell->type.in(CMP_OPS)) { - SigSpec aport = cell->getPort(ID::A); + SigSpec aport = cell->getPort(TW::A); bool asigned = cell->getParam(ID::A_SIGNED).as_bool(); - SigSpec bport = cell->getPort(ID::B); + SigSpec bport = cell->getPort(TW::B); bool bsigned = cell->getParam(ID::B_SIGNED).as_bool(); int width = std::max(aport.size(), bport.size()) + 1; @@ -318,7 +318,7 @@ struct Index { log_abort(); } } else if (cell->type.in(REDUCE_OPS, ID($logic_not))) { - SigSpec inport = cell->getPort(ID::A); + SigSpec inport = cell->getPort(TW::A); std::vector lits; for (int i = 0; i < inport.size(); i++) { @@ -339,8 +339,8 @@ struct Index { else return NOT(acc); } else if (cell->type.in(ID($logic_and), ID($logic_or))) { - SigSpec aport = cell->getPort(ID::A); - SigSpec bport = cell->getPort(ID::B); + SigSpec aport = cell->getPort(TW::A); + SigSpec bport = cell->getPort(TW::B); log_assert(aport.size() > 0 && bport.size() > 0); // TODO @@ -363,7 +363,7 @@ struct Index { else log_abort(); } else if (cell->type.in(BITWISE_OPS, GATE_OPS, ID($pos))) { - SigSpec aport = cell->getPort(ID::A); + SigSpec aport = cell->getPort(TW::A); Lit a; if (obit < aport.size()) { a = visit(cursor, aport[obit]); @@ -379,7 +379,7 @@ struct Index { } else if (cell->type.in(ID($not), ID($_NOT_))) { return NOT(a); } else { - SigSpec bport = cell->getPort(ID::B); + SigSpec bport = cell->getPort(TW::B); Lit b; if (obit < bport.size()) { b = visit(cursor, bport[obit]); @@ -407,16 +407,16 @@ struct Index { } else if (cell->type.in(ID($_ORNOT_))) { return OR(a, NOT(b)); } else if (cell->type.in(ID($mux), ID($_MUX_))) { - Lit s = visit(cursor, cell->getPort(ID::S)); + Lit s = visit(cursor, cell->getPort(TW::S)); return MUX(a, b, s); } else if (cell->type.in(ID($bwmux))) { - Lit s = visit(cursor, cell->getPort(ID::S)[obit]); + Lit s = visit(cursor, cell->getPort(TW::S)[obit]); return MUX(a, b, s); } else if (cell->type.in(ID($_NMUX_))) { - Lit s = visit(cursor, cell->getPort(ID::S)[obit]); + Lit s = visit(cursor, cell->getPort(TW::S)[obit]); return NOT(MUX(a, b, s)); } else if (cell->type.in(ID($fa))) { - Lit c = visit(cursor, cell->getPort(ID::C)[obit]); + Lit c = visit(cursor, cell->getPort(TW::C)[obit]); Lit ab = XOR(a, b); if (oport == ID::Y) { return XOR(ab, c); @@ -428,9 +428,9 @@ struct Index { } else if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) { Lit c, d; - c = visit(cursor, cell->getPort(ID::C)[obit]); + c = visit(cursor, cell->getPort(TW::C)[obit]); if (/* 4 input types */ cell->type.in(ID($_AOI4_), ID($_OAI4_))) - d = visit(cursor, cell->getPort(ID::D)[obit]); + d = visit(cursor, cell->getPort(TW::D)[obit]); else d = cell->type == ID($_AOI3_) ? CTRUE : CFALSE; @@ -448,9 +448,9 @@ struct Index { } } } else if (cell->type == ID($pmux)) { - SigSpec aport = cell->getPort(ID::A); - SigSpec bport = cell->getPort(ID::B); - SigSpec sport = cell->getPort(ID::S); + SigSpec aport = cell->getPort(TW::A); + SigSpec bport = cell->getPort(TW::B); + SigSpec sport = cell->getPort(TW::S); int width = aport.size(); Lit a = visit(cursor, aport[obit]); @@ -469,8 +469,8 @@ struct Index { return OR(reduce_sels_and_a, reduce_bar); } else if (cell->type == ID($bmux)) { - SigSpec aport = cell->getPort(ID::A); - SigSpec sport = cell->getPort(ID::S); + SigSpec aport = cell->getPort(TW::A); + SigSpec sport = cell->getPort(TW::S); int width = cell->getParam(ID::WIDTH).as_int(); std::vector data; @@ -632,7 +632,7 @@ struct Index { } else { Module *def = cursor.enter(*this, driver); { - IdString portname = bit.wire->driverPort(); + TwineRef portname = bit.wire->driverPort(); Wire *w = def->wire(portname); if (!w) log_error("Output port %s on instance %s of %s doesn't exist\n", @@ -652,7 +652,7 @@ struct Index { // step into the upper module Cell *instance = cursor.exit(*this); { - IdString portname = bit.wire->name; + TwineRef portname = bit.wire->name; if (!instance->hasPort(portname)) log_error("Input port %s on instance %s of %s unconnected\n", portname.unescape(), instance, instance->type); @@ -1134,7 +1134,7 @@ struct XAigerWriter : AigerWriter { for (auto [cursor, box, def] : nonopaque_boxes) { // use `def->name` not `box->type` as we want the derived type - Cell *holes_wb = holes_module->addCell(NEW_ID, def->name); + Cell *holes_wb = holes_module->addCell(NEW_TWINE, def->name); int holes_pi_idx = 0; if (map_file.is_open()) { @@ -1175,7 +1175,7 @@ struct XAigerWriter : AigerWriter { SigSpec in_conn; for (int i = 0; i < port->width; i++) { while (holes_pi_idx >= (int) holes_pis.size()) { - Wire *w = holes_module->addWire(NEW_ID, 1); + Wire *w = holes_module->addWire(NEW_TWINE, 1); w->port_input = true; holes_module->ports.push_back(w->name); holes_pis.push_back(w); @@ -1204,7 +1204,7 @@ struct XAigerWriter : AigerWriter { boxes_ci_num += port->width; // holes - Wire *w = holes_module->addWire(NEW_ID, port->width); + Wire *w = holes_module->addWire(NEW_TWINE, port->width); w->port_output = true; holes_module->ports.push_back(w->name); holes_wb->setPort(port_id, w); diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index ac2e4edde..b2e18faad 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -244,136 +244,136 @@ struct BlifDumper if (!config->icells_mode && cell->type == ID($_NOT_)) { f << stringf(".names %s %s\n0 1\n", - str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::Y)).c_str()); + str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::Y)).c_str()); goto internal_cell; } if (!config->icells_mode && cell->type == ID($_AND_)) { f << stringf(".names %s %s %s\n11 1\n", - str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str()); + str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str()); goto internal_cell; } if (!config->icells_mode && cell->type == ID($_OR_)) { f << stringf(".names %s %s %s\n1- 1\n-1 1\n", - str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str()); + str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str()); goto internal_cell; } if (!config->icells_mode && cell->type == ID($_XOR_)) { f << stringf(".names %s %s %s\n10 1\n01 1\n", - str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str()); + str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str()); goto internal_cell; } if (!config->icells_mode && cell->type == ID($_NAND_)) { f << stringf(".names %s %s %s\n0- 1\n-0 1\n", - str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str()); + str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str()); goto internal_cell; } if (!config->icells_mode && cell->type == ID($_NOR_)) { f << stringf(".names %s %s %s\n00 1\n", - str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str()); + str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str()); goto internal_cell; } if (!config->icells_mode && cell->type == ID($_XNOR_)) { f << stringf(".names %s %s %s\n11 1\n00 1\n", - str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str()); + str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str()); goto internal_cell; } if (!config->icells_mode && cell->type == ID($_ANDNOT_)) { f << stringf(".names %s %s %s\n10 1\n", - str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str()); + str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str()); goto internal_cell; } if (!config->icells_mode && cell->type == ID($_ORNOT_)) { f << stringf(".names %s %s %s\n1- 1\n-0 1\n", - str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str()); + str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str()); goto internal_cell; } if (!config->icells_mode && cell->type == ID($_AOI3_)) { f << stringf(".names %s %s %s %s\n-00 1\n0-0 1\n", - str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::C)).c_str(), str(cell->getPort(ID::Y)).c_str()); + str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::C)).c_str(), str(cell->getPort(TW::Y)).c_str()); goto internal_cell; } if (!config->icells_mode && cell->type == ID($_OAI3_)) { f << stringf(".names %s %s %s %s\n00- 1\n--0 1\n", - str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::C)).c_str(), str(cell->getPort(ID::Y)).c_str()); + str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::C)).c_str(), str(cell->getPort(TW::Y)).c_str()); goto internal_cell; } if (!config->icells_mode && cell->type == ID($_AOI4_)) { f << stringf(".names %s %s %s %s %s\n-0-0 1\n-00- 1\n0--0 1\n0-0- 1\n", - str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), - str(cell->getPort(ID::C)).c_str(), str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Y)).c_str()); + str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), + str(cell->getPort(TW::C)).c_str(), str(cell->getPort(TW::D)).c_str(), str(cell->getPort(TW::Y)).c_str()); goto internal_cell; } if (!config->icells_mode && cell->type == ID($_OAI4_)) { f << stringf(".names %s %s %s %s %s\n00-- 1\n--00 1\n", - str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), - str(cell->getPort(ID::C)).c_str(), str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Y)).c_str()); + str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), + str(cell->getPort(TW::C)).c_str(), str(cell->getPort(TW::D)).c_str(), str(cell->getPort(TW::Y)).c_str()); goto internal_cell; } if (!config->icells_mode && cell->type == ID($_MUX_)) { f << stringf(".names %s %s %s %s\n1-0 1\n-11 1\n", - str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), - str(cell->getPort(ID::S)).c_str(), str(cell->getPort(ID::Y)).c_str()); + str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), + str(cell->getPort(TW::S)).c_str(), str(cell->getPort(TW::Y)).c_str()); goto internal_cell; } if (!config->icells_mode && cell->type == ID($_NMUX_)) { f << stringf(".names %s %s %s %s\n0-0 1\n-01 1\n", - str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), - str(cell->getPort(ID::S)).c_str(), str(cell->getPort(ID::Y)).c_str()); + str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), + str(cell->getPort(TW::S)).c_str(), str(cell->getPort(TW::Y)).c_str()); goto internal_cell; } if (!config->icells_mode && cell->type == ID($_FF_)) { - f << stringf(".latch %s %s%s\n", str(cell->getPort(ID::D)), str(cell->getPort(ID::Q)), - str_init(cell->getPort(ID::Q)).c_str()); + f << stringf(".latch %s %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)), + str_init(cell->getPort(TW::Q)).c_str()); goto internal_cell; } if (!config->icells_mode && cell->type == ID($_DFF_N_)) { - f << stringf(".latch %s %s fe %s%s\n", str(cell->getPort(ID::D)), str(cell->getPort(ID::Q)), - str(cell->getPort(ID::C)).c_str(), str_init(cell->getPort(ID::Q)).c_str()); + f << stringf(".latch %s %s fe %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)), + str(cell->getPort(TW::C)).c_str(), str_init(cell->getPort(TW::Q)).c_str()); goto internal_cell; } if (!config->icells_mode && cell->type == ID($_DFF_P_)) { - f << stringf(".latch %s %s re %s%s\n", str(cell->getPort(ID::D)), str(cell->getPort(ID::Q)), - str(cell->getPort(ID::C)).c_str(), str_init(cell->getPort(ID::Q)).c_str()); + f << stringf(".latch %s %s re %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)), + str(cell->getPort(TW::C)).c_str(), str_init(cell->getPort(TW::Q)).c_str()); goto internal_cell; } if (!config->icells_mode && cell->type == ID($_DLATCH_N_)) { - f << stringf(".latch %s %s al %s%s\n", str(cell->getPort(ID::D)), str(cell->getPort(ID::Q)), - str(cell->getPort(ID::E)).c_str(), str_init(cell->getPort(ID::Q)).c_str()); + f << stringf(".latch %s %s al %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)), + str(cell->getPort(TW::E)).c_str(), str_init(cell->getPort(TW::Q)).c_str()); goto internal_cell; } if (!config->icells_mode && cell->type == ID($_DLATCH_P_)) { - f << stringf(".latch %s %s ah %s%s\n", str(cell->getPort(ID::D)), str(cell->getPort(ID::Q)), - str(cell->getPort(ID::E)).c_str(), str_init(cell->getPort(ID::Q)).c_str()); + f << stringf(".latch %s %s ah %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)), + str(cell->getPort(TW::E)).c_str(), str_init(cell->getPort(TW::Q)).c_str()); goto internal_cell; } if (!config->icells_mode && cell->type == ID($lut)) { f << stringf(".names"); - auto &inputs = cell->getPort(ID::A); + auto &inputs = cell->getPort(TW::A); auto width = cell->parameters.at(ID::WIDTH).as_int(); log_assert(inputs.size() == width); for (int i = width-1; i >= 0; i--) f << stringf(" %s", str(inputs.extract(i, 1))); - auto &output = cell->getPort(ID::Y); + auto &output = cell->getPort(TW::Y); log_assert(output.size() == 1); f << stringf(" %s", str(output)); f << stringf("\n"); @@ -390,7 +390,7 @@ struct BlifDumper if (!config->icells_mode && cell->type == ID($sop)) { f << stringf(".names"); - auto &inputs = cell->getPort(ID::A); + auto &inputs = cell->getPort(TW::A); auto width = cell->parameters.at(ID::WIDTH).as_int(); auto depth = cell->parameters.at(ID::DEPTH).as_int(); vector table = cell->parameters.at(ID::TABLE).to_bits(); @@ -399,7 +399,7 @@ struct BlifDumper log_assert(inputs.size() == width); for (int i = 0; i < width; i++) f << stringf(" %s", str(inputs.extract(i, 1))); - auto &output = cell->getPort(ID::Y); + auto &output = cell->getPort(TW::Y); log_assert(output.size() == 1); f << stringf(" %s", str(output)); f << stringf("\n"); diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index a25510578..fe22fed55 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -271,8 +271,8 @@ struct BtorWorker if (cell->type.in(ID($xnor), ID($_XNOR_))) btor_op = "xnor"; log_assert(!btor_op.empty()); - int width_ay = std::max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::Y))); - int width = std::max(width_ay, GetSize(cell->getPort(ID::B))); + int width_ay = std::max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::Y))); + int width = std::max(width_ay, GetSize(cell->getPort(TW::B))); bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false; bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false; @@ -292,17 +292,17 @@ struct BtorWorker int nid_a; if (cell->type.in(ID($shl), ID($shr), ID($shift), ID($shiftx)) && a_signed && width_ay < width) { // sign-extend A up to the width of Y - int nid_a_padded = get_sig_nid(cell->getPort(ID::A), width_ay, a_signed); + int nid_a_padded = get_sig_nid(cell->getPort(TW::A), width_ay, a_signed); // zero-extend the rest int zeroes = get_sig_nid(Const(0, width-width_ay)); nid_a = next_nid++; btorf("%d concat %d %d %d\n", nid_a, sid, zeroes, nid_a_padded); } else { - nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed); + nid_a = get_sig_nid(cell->getPort(TW::A), width, a_signed); } - int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed); + int nid_b = get_sig_nid(cell->getPort(TW::B), width, b_signed); if (btor_op == "shift") { @@ -329,7 +329,7 @@ struct BtorWorker btorf("%d %s %d %d %d%s\n", nid, btor_op, sid, nid_a, nid_b, getinfo(cell)); } - SigSpec sig = sigmap(cell->getPort(ID::Y)); + SigSpec sig = sigmap(cell->getPort(TW::Y)); if (GetSize(sig) < width) { int sid = get_bv_sid(GetSize(sig)); @@ -358,18 +358,18 @@ struct BtorWorker } log_assert(!btor_op.empty()); - int width = GetSize(cell->getPort(ID::Y)); - width = std::max(width, GetSize(cell->getPort(ID::A))); - width = std::max(width, GetSize(cell->getPort(ID::B))); + int width = GetSize(cell->getPort(TW::Y)); + width = std::max(width, GetSize(cell->getPort(TW::A))); + width = std::max(width, GetSize(cell->getPort(TW::B))); - int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed); - int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed); + int nid_a = get_sig_nid(cell->getPort(TW::A), width, a_signed); + int nid_b = get_sig_nid(cell->getPort(TW::B), width, b_signed); int sid = get_bv_sid(width); int nid = next_nid++; btorf("%d %c%s %d %d %d%s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op, sid, nid_a, nid_b, getinfo(cell)); - SigSpec sig = sigmap(cell->getPort(ID::Y)); + SigSpec sig = sigmap(cell->getPort(TW::Y)); if (GetSize(sig) < width) { int sid = get_bv_sid(GetSize(sig)); @@ -385,8 +385,8 @@ struct BtorWorker if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_))) { int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort(ID::A)); - int nid_b = get_sig_nid(cell->getPort(ID::B)); + int nid_a = get_sig_nid(cell->getPort(TW::A)); + int nid_b = get_sig_nid(cell->getPort(TW::B)); int nid1 = next_nid++; int nid2 = next_nid++; @@ -401,7 +401,7 @@ struct BtorWorker btorf("%d or %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell)); } - SigSpec sig = sigmap(cell->getPort(ID::Y)); + SigSpec sig = sigmap(cell->getPort(TW::Y)); add_nid_sig(nid2, sig); goto okay; } @@ -409,9 +409,9 @@ struct BtorWorker if (cell->type.in(ID($_OAI3_), ID($_AOI3_))) { int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort(ID::A)); - int nid_b = get_sig_nid(cell->getPort(ID::B)); - int nid_c = get_sig_nid(cell->getPort(ID::C)); + int nid_a = get_sig_nid(cell->getPort(TW::A)); + int nid_b = get_sig_nid(cell->getPort(TW::B)); + int nid_c = get_sig_nid(cell->getPort(TW::C)); int nid1 = next_nid++; int nid2 = next_nid++; @@ -429,7 +429,7 @@ struct BtorWorker btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell)); } - SigSpec sig = sigmap(cell->getPort(ID::Y)); + SigSpec sig = sigmap(cell->getPort(TW::Y)); add_nid_sig(nid3, sig); goto okay; } @@ -437,10 +437,10 @@ struct BtorWorker if (cell->type.in(ID($_OAI4_), ID($_AOI4_))) { int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort(ID::A)); - int nid_b = get_sig_nid(cell->getPort(ID::B)); - int nid_c = get_sig_nid(cell->getPort(ID::C)); - int nid_d = get_sig_nid(cell->getPort(ID::D)); + int nid_a = get_sig_nid(cell->getPort(TW::A)); + int nid_b = get_sig_nid(cell->getPort(TW::B)); + int nid_c = get_sig_nid(cell->getPort(TW::C)); + int nid_d = get_sig_nid(cell->getPort(TW::D)); int nid1 = next_nid++; int nid2 = next_nid++; @@ -461,7 +461,7 @@ struct BtorWorker btorf("%d not %d %d%s\n", nid4, sid, nid3, getinfo(cell)); } - SigSpec sig = sigmap(cell->getPort(ID::Y)); + SigSpec sig = sigmap(cell->getPort(TW::Y)); add_nid_sig(nid4, sig); goto okay; } @@ -478,15 +478,15 @@ struct BtorWorker log_assert(!btor_op.empty()); int width = 1; - width = std::max(width, GetSize(cell->getPort(ID::A))); - width = std::max(width, GetSize(cell->getPort(ID::B))); + width = std::max(width, GetSize(cell->getPort(TW::A))); + width = std::max(width, GetSize(cell->getPort(TW::B))); bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false; bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false; int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed); - int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed); + int nid_a = get_sig_nid(cell->getPort(TW::A), width, a_signed); + int nid_b = get_sig_nid(cell->getPort(TW::B), width, b_signed); int nid = next_nid++; if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt))) { @@ -495,7 +495,7 @@ struct BtorWorker btorf("%d %s %d %d %d%s\n", nid, btor_op, sid, nid_a, nid_b, getinfo(cell)); } - SigSpec sig = sigmap(cell->getPort(ID::Y)); + SigSpec sig = sigmap(cell->getPort(TW::Y)); if (GetSize(sig) > 1) { int sid = get_bv_sid(GetSize(sig)); @@ -514,11 +514,11 @@ struct BtorWorker if (cell->type.in(ID($not), ID($_NOT_))) btor_op = "not"; if (cell->type == ID($neg)) btor_op = "neg"; - int width = std::max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::Y))); + int width = std::max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::Y))); bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false; - int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed); - SigSpec sig = sigmap(cell->getPort(ID::Y)); + int nid_a = get_sig_nid(cell->getPort(TW::A), width, a_signed); + SigSpec sig = sigmap(cell->getPort(TW::Y)); // the $pos/$buf cells just pass through, all other cells need an actual operation applied int nid = nid_a; @@ -550,16 +550,16 @@ struct BtorWorker log_assert(!btor_op.empty()); int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort(ID::A)); - int nid_b = btor_op != "not" ? get_sig_nid(cell->getPort(ID::B)) : 0; + int nid_a = get_sig_nid(cell->getPort(TW::A)); + int nid_b = btor_op != "not" ? get_sig_nid(cell->getPort(TW::B)) : 0; - if (GetSize(cell->getPort(ID::A)) > 1) { + if (GetSize(cell->getPort(TW::A)) > 1) { int nid_red_a = next_nid++; btorf("%d redor %d %d\n", nid_red_a, sid, nid_a); nid_a = nid_red_a; } - if (btor_op != "not" && GetSize(cell->getPort(ID::B)) > 1) { + if (btor_op != "not" && GetSize(cell->getPort(TW::B)) > 1) { int nid_red_b = next_nid++; btorf("%d redor %d %d\n", nid_red_b, sid, nid_b); nid_b = nid_red_b; @@ -571,7 +571,7 @@ struct BtorWorker else btorf("%d %s %d %d%s\n", nid, btor_op, sid, nid_a, getinfo(cell)); - SigSpec sig = sigmap(cell->getPort(ID::Y)); + SigSpec sig = sigmap(cell->getPort(TW::Y)); if (GetSize(sig) > 1) { int sid = get_bv_sid(GetSize(sig)); @@ -594,7 +594,7 @@ struct BtorWorker log_assert(!btor_op.empty()); int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort(ID::A)); + int nid_a = get_sig_nid(cell->getPort(TW::A)); int nid = next_nid++; @@ -607,7 +607,7 @@ struct BtorWorker btorf("%d %s %d %d%s\n", nid, btor_op, sid, nid_a, getinfo(cell)); } - SigSpec sig = sigmap(cell->getPort(ID::Y)); + SigSpec sig = sigmap(cell->getPort(TW::Y)); if (GetSize(sig) > 1) { int sid = get_bv_sid(GetSize(sig)); @@ -623,10 +623,10 @@ struct BtorWorker if (cell->type.in(ID($mux), ID($_MUX_), ID($_NMUX_))) { - SigSpec sig_a = sigmap(cell->getPort(ID::A)); - SigSpec sig_b = sigmap(cell->getPort(ID::B)); - SigSpec sig_s = sigmap(cell->getPort(ID::S)); - SigSpec sig_y = sigmap(cell->getPort(ID::Y)); + SigSpec sig_a = sigmap(cell->getPort(TW::A)); + SigSpec sig_b = sigmap(cell->getPort(TW::B)); + SigSpec sig_s = sigmap(cell->getPort(TW::S)); + SigSpec sig_y = sigmap(cell->getPort(TW::Y)); int nid_a = get_sig_nid(sig_a); int nid_b = get_sig_nid(sig_b); @@ -650,10 +650,10 @@ struct BtorWorker if (cell->type == ID($pmux)) { - SigSpec sig_a = sigmap(cell->getPort(ID::A)); - SigSpec sig_b = sigmap(cell->getPort(ID::B)); - SigSpec sig_s = sigmap(cell->getPort(ID::S)); - SigSpec sig_y = sigmap(cell->getPort(ID::Y)); + SigSpec sig_a = sigmap(cell->getPort(TW::A)); + SigSpec sig_b = sigmap(cell->getPort(TW::B)); + SigSpec sig_s = sigmap(cell->getPort(TW::S)); + SigSpec sig_y = sigmap(cell->getPort(TW::Y)); int width = GetSize(sig_a); int sid = get_bv_sid(width); @@ -676,8 +676,8 @@ struct BtorWorker if (cell->type.in(ID($dff), ID($ff), ID($anyinit), ID($_DFF_P_), ID($_DFF_N), ID($_FF_))) { - SigSpec sig_d = sigmap(cell->getPort(ID::D)); - SigSpec sig_q = sigmap(cell->getPort(ID::Q)); + SigSpec sig_d = sigmap(cell->getPort(TW::D)); + SigSpec sig_q = sigmap(cell->getPort(TW::Q)); if ((!info_filename.empty() || ywmap_json.active()) && cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_))) { @@ -730,7 +730,7 @@ struct BtorWorker btorf("%d state %d %s\n", nid, sid, symbol.unescape()); if (cell->get_bool_attribute(ID(clk2fflogic))) - ywmap_state(cell->getPort(ID::D)); // For a clk2fflogic FF the named signal is the D input not the Q output + ywmap_state(cell->getPort(TW::D)); // For a clk2fflogic FF the named signal is the D input not the Q output else ywmap_state(sig_q); @@ -748,7 +748,7 @@ struct BtorWorker if (cell->type.in(ID($anyconst), ID($anyseq))) { - SigSpec sig_y = sigmap(cell->getPort(ID::Y)); + SigSpec sig_y = sigmap(cell->getPort(TW::Y)); int sid = get_bv_sid(GetSize(sig_y)); int nid = next_nid++; @@ -768,7 +768,7 @@ struct BtorWorker if (cell->type == ID($initstate)) { - SigSpec sig_y = sigmap(cell->getPort(ID::Y)); + SigSpec sig_y = sigmap(cell->getPort(TW::Y)); if (initstate_nid < 0) { @@ -1272,8 +1272,8 @@ struct BtorWorker btorf_push(cell->name.unescape()); int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort(ID::A)); - int nid_en = get_sig_nid(cell->getPort(ID::EN)); + int nid_a = get_sig_nid(cell->getPort(TW::A)); + int nid_en = get_sig_nid(cell->getPort(TW::EN)); int nid_not_en = next_nid++; int nid_a_or_not_en = next_nid++; int nid = next_nid++; @@ -1292,8 +1292,8 @@ struct BtorWorker btorf_push(cell->name.unescape()); int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort(ID::A)); - int nid_en = get_sig_nid(cell->getPort(ID::EN)); + int nid_a = get_sig_nid(cell->getPort(TW::A)); + int nid_en = get_sig_nid(cell->getPort(TW::EN)); int nid_not_a = next_nid++; int nid_en_and_not_a = next_nid++; @@ -1321,8 +1321,8 @@ struct BtorWorker btorf_push(cell->name.unescape()); int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort(ID::A)); - int nid_en = get_sig_nid(cell->getPort(ID::EN)); + int nid_a = get_sig_nid(cell->getPort(TW::A)); + int nid_en = get_sig_nid(cell->getPort(TW::EN)); int nid_en_and_a = next_nid++; btorf("%d and %d %d %d\n", nid_en_and_a, sid, nid_en, nid_a); @@ -1372,7 +1372,7 @@ struct BtorWorker btorf_push(stringf("next %s", cell)); - SigSpec sig = sigmap(cell->getPort(ID::D)); + SigSpec sig = sigmap(cell->getPort(TW::D)); int nid_q = get_sig_nid(sig); int sid = get_bv_sid(GetSize(sig)); btorf("%d next %d %d %d%s\n", next_nid++, sid, nid, nid_q, getinfo(cell)); diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index 5fd35e759..c16d5d37c 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -243,7 +243,7 @@ enum class CxxrtlPortType { SYNC = 2, }; -CxxrtlPortType cxxrtl_port_type(RTLIL::Module *module, RTLIL::IdString port) +CxxrtlPortType cxxrtl_port_type(RTLIL::Module *module, TwineRef port) { RTLIL::Wire *output_wire = module->wire(port); log_assert(output_wire != nullptr); @@ -259,7 +259,7 @@ CxxrtlPortType cxxrtl_port_type(RTLIL::Module *module, RTLIL::IdString port) return CxxrtlPortType::UNKNOWN; } -CxxrtlPortType cxxrtl_port_type(const RTLIL::Cell *cell, RTLIL::IdString port) +CxxrtlPortType cxxrtl_port_type(const RTLIL::Cell *cell, TwineRef port) { RTLIL::Module *cell_module = cell->module->design->module(cell->type); if (cell_module == nullptr || !cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) @@ -267,12 +267,12 @@ CxxrtlPortType cxxrtl_port_type(const RTLIL::Cell *cell, RTLIL::IdString port) return cxxrtl_port_type(cell_module, port); } -bool is_cxxrtl_comb_port(const RTLIL::Cell *cell, RTLIL::IdString port) +bool is_cxxrtl_comb_port(const RTLIL::Cell *cell, TwineRef port) { return cxxrtl_port_type(cell, port) == CxxrtlPortType::COMB; } -bool is_cxxrtl_sync_port(const RTLIL::Cell *cell, RTLIL::IdString port) +bool is_cxxrtl_sync_port(const RTLIL::Cell *cell, TwineRef port) { return cxxrtl_port_type(cell, port) == CxxrtlPortType::SYNC; } @@ -1139,7 +1139,7 @@ struct CxxrtlWorker { if (is_extending_cell(cell->type)) f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u'); f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">("; - dump_sigspec_rhs(cell->getPort(ID::A), for_debug); + dump_sigspec_rhs(cell->getPort(TW::A), for_debug); f << ")"; // Binary cells } else if (is_binary_cell(cell->type)) { @@ -1148,18 +1148,18 @@ struct CxxrtlWorker { f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u') << (cell->getParam(ID::B_SIGNED).as_bool() ? 's' : 'u'); f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">("; - dump_sigspec_rhs(cell->getPort(ID::A), for_debug); + dump_sigspec_rhs(cell->getPort(TW::A), for_debug); f << ", "; - dump_sigspec_rhs(cell->getPort(ID::B), for_debug); + dump_sigspec_rhs(cell->getPort(TW::B), for_debug); f << ")"; // Muxes } else if (cell->type == ID($mux)) { f << "("; - dump_sigspec_rhs(cell->getPort(ID::S), for_debug); + dump_sigspec_rhs(cell->getPort(TW::S), for_debug); f << " ? "; - dump_sigspec_rhs(cell->getPort(ID::B), for_debug); + dump_sigspec_rhs(cell->getPort(TW::B), for_debug); f << " : "; - dump_sigspec_rhs(cell->getPort(ID::A), for_debug); + dump_sigspec_rhs(cell->getPort(TW::A), for_debug); f << ")"; // Parallel (one-hot) muxes } else if (cell->type == ID($pmux)) { @@ -1167,48 +1167,48 @@ struct CxxrtlWorker { int s_width = cell->getParam(ID::S_WIDTH).as_int(); for (int part = 0; part < s_width; part++) { f << "("; - dump_sigspec_rhs(cell->getPort(ID::S).extract(part), for_debug); + dump_sigspec_rhs(cell->getPort(TW::S).extract(part), for_debug); f << " ? "; - dump_sigspec_rhs(cell->getPort(ID::B).extract(part * width, width), for_debug); + dump_sigspec_rhs(cell->getPort(TW::B).extract(part * width, width), for_debug); f << " : "; } - dump_sigspec_rhs(cell->getPort(ID::A), for_debug); + dump_sigspec_rhs(cell->getPort(TW::A), for_debug); for (int part = 0; part < s_width; part++) { f << ")"; } // Big muxes } else if (cell->type == ID($bmux)) { - dump_sigspec_rhs(cell->getPort(ID::A), for_debug); + dump_sigspec_rhs(cell->getPort(TW::A), for_debug); f << ".bmux<"; f << cell->getParam(ID::WIDTH).as_int(); f << ">("; - dump_sigspec_rhs(cell->getPort(ID::S), for_debug); + dump_sigspec_rhs(cell->getPort(TW::S), for_debug); f << ").val()"; // Bitwise muxes } else if (cell->type == ID($bwmux)) { - dump_sigspec_rhs(cell->getPort(ID::A), for_debug); + dump_sigspec_rhs(cell->getPort(TW::A), for_debug); f << ".bwmux("; - dump_sigspec_rhs(cell->getPort(ID::B), for_debug); + dump_sigspec_rhs(cell->getPort(TW::B), for_debug); f << ","; - dump_sigspec_rhs(cell->getPort(ID::S), for_debug); + dump_sigspec_rhs(cell->getPort(TW::S), for_debug); f << ").val()"; // Demuxes } else if (cell->type == ID($demux)) { - dump_sigspec_rhs(cell->getPort(ID::A), for_debug); + dump_sigspec_rhs(cell->getPort(TW::A), for_debug); f << ".demux<"; - f << GetSize(cell->getPort(ID::Y)); + f << GetSize(cell->getPort(TW::Y)); f << ">("; - dump_sigspec_rhs(cell->getPort(ID::S), for_debug); + dump_sigspec_rhs(cell->getPort(TW::S), for_debug); f << ").val()"; // Concats } else if (cell->type == ID($concat)) { - dump_sigspec_rhs(cell->getPort(ID::B), for_debug); + dump_sigspec_rhs(cell->getPort(TW::B), for_debug); f << ".concat("; - dump_sigspec_rhs(cell->getPort(ID::A), for_debug); + dump_sigspec_rhs(cell->getPort(TW::A), for_debug); f << ").val()"; // Slices } else if (cell->type == ID($slice)) { - dump_sigspec_rhs(cell->getPort(ID::A), for_debug); + dump_sigspec_rhs(cell->getPort(TW::A), for_debug); f << ".slice<"; f << cell->getParam(ID::OFFSET).as_int() + cell->getParam(ID::Y_WIDTH).as_int() - 1; f << ","; @@ -1225,7 +1225,7 @@ struct CxxrtlWorker { fmt.parse_rtlil(cell); f << indent << "if ("; - dump_sigspec_rhs(cell->getPort(ID::EN)); + dump_sigspec_rhs(cell->getPort(TW::EN)); f << " == value<1>{1u}) {\n"; inc_indent(); dict fmt_args; @@ -1277,7 +1277,7 @@ struct CxxrtlWorker { fmt.parse_rtlil(cell); f << indent << "if ("; - dump_sigspec_rhs(cell->getPort(ID::EN)); + dump_sigspec_rhs(cell->getPort(TW::EN)); f << ") {\n"; inc_indent(); dict fmt_args; @@ -1309,7 +1309,7 @@ struct CxxrtlWorker { } if (cell->hasPort(ID::A)) { f << indent << "bool condition = (bool)"; - dump_sigspec_rhs(cell->getPort(ID::A)); + dump_sigspec_rhs(cell->getPort(TW::A)); f << ";\n"; } f << indent << "if (performer) {\n"; @@ -1366,7 +1366,7 @@ struct CxxrtlWorker { // Elidable cells if (is_inlinable_cell(cell->type)) { f << indent; - dump_sigspec_lhs(cell->getPort(ID::Y), for_debug); + dump_sigspec_lhs(cell->getPort(TW::Y), for_debug); f << " = "; dump_cell_expr(cell, for_debug); f << ";\n"; @@ -1379,12 +1379,12 @@ struct CxxrtlWorker { if (!cell->getParam(ID::TRG_ENABLE).as_bool()) { // async effectful cell f << indent << "auto " << mangle(cell) << "_next = "; - dump_sigspec_rhs(cell->getPort(ID::EN)); + dump_sigspec_rhs(cell->getPort(TW::EN)); f << ".concat("; if (cell->type == ID($print)) - dump_sigspec_rhs(cell->getPort(ID::ARGS)); + dump_sigspec_rhs(cell->getPort(TW::ARGS)); else if (cell->type == ID($check)) - dump_sigspec_rhs(cell->getPort(ID::A)); + dump_sigspec_rhs(cell->getPort(TW::A)); else log_assert(false); f << ").val();\n"; @@ -1406,9 +1406,9 @@ struct CxxrtlWorker { } else if (is_ff_cell(cell->type)) { log_assert(!for_debug); // Clocks might be slices of larger signals but should only ever be single bit - if (cell->hasPort(ID::CLK) && is_valid_clock(cell->getPort(ID::CLK))) { + if (cell->hasPort(ID::CLK) && is_valid_clock(cell->getPort(TW::CLK))) { // Edge-sensitive logic - RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0]; + RTLIL::SigBit clk_bit = cell->getPort(TW::CLK)[0]; clk_bit = sigmaps[clk_bit.wire->module](clk_bit); if (clk_bit.wire) { f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_") @@ -1419,14 +1419,14 @@ struct CxxrtlWorker { inc_indent(); if (cell->hasPort(ID::EN)) { f << indent << "if ("; - dump_sigspec_rhs(cell->getPort(ID::EN)); + dump_sigspec_rhs(cell->getPort(TW::EN)); f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n"; inc_indent(); } f << indent; - dump_sigspec_lhs(cell->getPort(ID::Q)); + dump_sigspec_lhs(cell->getPort(TW::Q)); f << " = "; - dump_sigspec_rhs(cell->getPort(ID::D)); + dump_sigspec_rhs(cell->getPort(TW::D)); f << ";\n"; if (cell->hasPort(ID::EN) && cell->type != ID($sdffce)) { dec_indent(); @@ -1434,11 +1434,11 @@ struct CxxrtlWorker { } if (cell->hasPort(ID::SRST)) { f << indent << "if ("; - dump_sigspec_rhs(cell->getPort(ID::SRST)); + dump_sigspec_rhs(cell->getPort(TW::SRST)); f << " == value<1> {" << cell->getParam(ID::SRST_POLARITY).as_bool() << "u}) {\n"; inc_indent(); f << indent; - dump_sigspec_lhs(cell->getPort(ID::Q)); + dump_sigspec_lhs(cell->getPort(TW::Q)); f << " = "; dump_const(cell->getParam(ID::SRST_VALUE)); f << ";\n"; @@ -1454,13 +1454,13 @@ struct CxxrtlWorker { } else if (cell->hasPort(ID::EN)) { // Level-sensitive logic f << indent << "if ("; - dump_sigspec_rhs(cell->getPort(ID::EN)); + dump_sigspec_rhs(cell->getPort(TW::EN)); f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n"; inc_indent(); f << indent; - dump_sigspec_lhs(cell->getPort(ID::Q)); + dump_sigspec_lhs(cell->getPort(TW::Q)); f << " = "; - dump_sigspec_rhs(cell->getPort(ID::D)); + dump_sigspec_rhs(cell->getPort(TW::D)); f << ";\n"; dec_indent(); f << indent << "}\n"; @@ -1468,11 +1468,11 @@ struct CxxrtlWorker { if (cell->hasPort(ID::ARST)) { // Asynchronous reset (entire coarse cell at once) f << indent << "if ("; - dump_sigspec_rhs(cell->getPort(ID::ARST)); + dump_sigspec_rhs(cell->getPort(TW::ARST)); f << " == value<1> {" << cell->getParam(ID::ARST_POLARITY).as_bool() << "u}) {\n"; inc_indent(); f << indent; - dump_sigspec_lhs(cell->getPort(ID::Q)); + dump_sigspec_lhs(cell->getPort(TW::Q)); f << " = "; dump_const(cell->getParam(ID::ARST_VALUE)); f << ";\n"; @@ -1482,13 +1482,13 @@ struct CxxrtlWorker { if (cell->hasPort(ID::ALOAD)) { // Asynchronous load f << indent << "if ("; - dump_sigspec_rhs(cell->getPort(ID::ALOAD)); + dump_sigspec_rhs(cell->getPort(TW::ALOAD)); f << " == value<1> {" << cell->getParam(ID::ALOAD_POLARITY).as_bool() << "u}) {\n"; inc_indent(); f << indent; - dump_sigspec_lhs(cell->getPort(ID::Q)); + dump_sigspec_lhs(cell->getPort(TW::Q)); f << " = "; - dump_sigspec_rhs(cell->getPort(ID::AD)); + dump_sigspec_rhs(cell->getPort(TW::AD)); f << ";\n"; dec_indent(); f << indent << "}\n"; @@ -1496,25 +1496,25 @@ struct CxxrtlWorker { if (cell->hasPort(ID::SET)) { // Asynchronous set (for individual bits) f << indent; - dump_sigspec_lhs(cell->getPort(ID::Q)); + dump_sigspec_lhs(cell->getPort(TW::Q)); f << " = "; - dump_sigspec_rhs(cell->getPort(ID::Q)); + dump_sigspec_rhs(cell->getPort(TW::Q)); f << ".update("; dump_const(RTLIL::Const(RTLIL::S1, cell->getParam(ID::WIDTH).as_int())); f << ", "; - dump_sigspec_rhs(cell->getPort(ID::SET)); + dump_sigspec_rhs(cell->getPort(TW::SET)); f << (cell->getParam(ID::SET_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n"; } if (cell->hasPort(ID::CLR)) { // Asynchronous clear (for individual bits; priority over set) f << indent; - dump_sigspec_lhs(cell->getPort(ID::Q)); + dump_sigspec_lhs(cell->getPort(TW::Q)); f << " = "; - dump_sigspec_rhs(cell->getPort(ID::Q)); + dump_sigspec_rhs(cell->getPort(TW::Q)); f << ".update("; dump_const(RTLIL::Const(RTLIL::S0, cell->getParam(ID::WIDTH).as_int())); f << ", "; - dump_sigspec_rhs(cell->getPort(ID::CLR)); + dump_sigspec_rhs(cell->getPort(TW::CLR)); f << (cell->getParam(ID::CLR_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n"; } // Internal cells @@ -1788,7 +1788,7 @@ struct CxxrtlWorker { void dump_cell_effect_sync(std::vector &cells) { log_assert(!cells.empty()); - const auto &trg = cells[0]->getPort(ID::TRG); + const auto &trg = cells[0]->getPort(TW::TRG); const auto &trg_polarity = cells[0]->getParam(ID::TRG_POLARITY); f << indent << "if ("; @@ -1813,7 +1813,7 @@ struct CxxrtlWorker { }); for (auto cell : cells) { log_assert(cell->getParam(ID::TRG_ENABLE).as_bool()); - log_assert(cell->getPort(ID::TRG) == trg); + log_assert(cell->getPort(TW::TRG) == trg); log_assert(cell->getParam(ID::TRG_POLARITY) == trg_polarity); std::vector inlined_cells; @@ -2999,15 +2999,15 @@ struct CxxrtlWorker { // Various DFF cells are treated like posedge/negedge processes, see above for details. if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($dffsr), ID($dffsre), ID($sdff), ID($sdffe), ID($sdffce))) { - if (is_valid_clock(cell->getPort(ID::CLK))) - register_edge_signal(sigmap, cell->getPort(ID::CLK), + if (is_valid_clock(cell->getPort(TW::CLK))) + register_edge_signal(sigmap, cell->getPort(TW::CLK), cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn); } // Effectful cells may be triggered on posedge/negedge events. if (is_effectful_cell(cell->type) && cell->getParam(ID::TRG_ENABLE).as_bool()) { for (size_t i = 0; i < (size_t)cell->getParam(ID::TRG_WIDTH).as_int(); i++) { - RTLIL::SigBit trg = cell->getPort(ID::TRG).extract(i, 1); + RTLIL::SigBit trg = cell->getPort(TW::TRG).extract(i, 1); if (is_valid_clock(trg)) register_edge_signal(sigmap, trg, cell->parameters[ID::TRG_POLARITY][i] == RTLIL::S1 ? RTLIL::STp : RTLIL::STn); @@ -3216,7 +3216,7 @@ struct CxxrtlWorker { is_effectful_cell(node->cell->type) && node->cell->getParam(ID::TRG_ENABLE).as_bool() && node->cell->getParam(ID::TRG_WIDTH).as_int() != 0) - effect_sync_cells[make_pair(node->cell->getPort(ID::TRG), node->cell->getParam(ID::TRG_POLARITY))].push_back(node->cell); + effect_sync_cells[make_pair(node->cell->getPort(TW::TRG), node->cell->getParam(ID::TRG_POLARITY))].push_back(node->cell); else schedule[module].push_back(*node); } diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index e3812aa57..77003fcef 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -601,7 +601,7 @@ struct FirrtlWorker if (cell->type.in(ID($not), ID($logic_not), ID($_NOT_), ID($neg), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_bool), ID($reduce_xnor))) { - string a_expr = make_expr(cell->getPort(ID::A)); + string a_expr = make_expr(cell->getPort(TW::A)); wire_decls.push_back(stringf("%swire %s: UInt<%d> %s\n", indent, y_id, y_width, cellFileinfo)); if (a_signed) { @@ -643,7 +643,7 @@ struct FirrtlWorker expr = stringf("asUInt(%s)", expr); cell_exprs.push_back(stringf("%s%s <= %s %s\n", indent, y_id, expr, cellFileinfo)); - register_reverse_wire_map(y_id, cell->getPort(ID::Y)); + register_reverse_wire_map(y_id, cell->getPort(TW::Y)); continue; } @@ -651,8 +651,8 @@ struct FirrtlWorker ID($gt), ID($ge), ID($lt), ID($le), ID($ne), ID($nex), ID($shr), ID($sshr), ID($sshl), ID($shl), ID($logic_and), ID($logic_or), ID($pow))) { - string a_expr = make_expr(cell->getPort(ID::A)); - string b_expr = make_expr(cell->getPort(ID::B)); + string a_expr = make_expr(cell->getPort(TW::A)); + string b_expr = make_expr(cell->getPort(TW::B)); std::string cellFileinfo = getFileinfo(cell); wire_decls.push_back(stringf("%swire %s: UInt<%d> %s\n", indent, y_id, y_width, cellFileinfo)); @@ -690,7 +690,7 @@ struct FirrtlWorker } // Assume the FIRRTL width is the width of "A" firrtl_width = a_width; - auto a_sig = cell->getPort(ID::A); + auto a_sig = cell->getPort(TW::A); if (cell->type == ID($add)) { primop = "add"; @@ -769,7 +769,7 @@ struct FirrtlWorker // We'll need to offset this by extracting the un-widened portion as Verilog would do. extract_y_bits = true; // Is the shift amount constant? - auto b_sig = cell->getPort(ID::B); + auto b_sig = cell->getPort(TW::B); if (b_sig.is_fully_const()) { primop = "shl"; int shift_amount = b_sig.as_int(); @@ -786,7 +786,7 @@ struct FirrtlWorker // We don't need to extract a specific range of bits. extract_y_bits = false; // Is the shift amount constant? - auto b_sig = cell->getPort(ID::B); + auto b_sig = cell->getPort(TW::B); if (b_sig.is_fully_const()) { primop = "shr"; int shift_amount = b_sig.as_int(); @@ -828,7 +828,7 @@ struct FirrtlWorker a_expr = firrtl_is_signed ? "SInt(1)" : "UInt(1)"; extract_y_bits = true; // Is the shift amount constant? - auto b_sig = cell->getPort(ID::B); + auto b_sig = cell->getPort(TW::B); if (b_sig.is_fully_const()) { primop = "shl"; int shiftAmount = b_sig.as_int(); @@ -873,7 +873,7 @@ struct FirrtlWorker expr = stringf("asUInt(%s)", expr); cell_exprs.push_back(stringf("%s%s <= %s %s\n", indent, y_id, expr, cellFileinfo)); - register_reverse_wire_map(y_id, cell->getPort(ID::Y)); + register_reverse_wire_map(y_id, cell->getPort(TW::Y)); continue; } @@ -882,15 +882,15 @@ struct FirrtlWorker { auto it = cell->parameters.find(ID::WIDTH); int width = it == cell->parameters.end()? 1 : it->second.as_int(); - string a_expr = make_expr(cell->getPort(ID::A)); - string b_expr = make_expr(cell->getPort(ID::B)); - string s_expr = make_expr(cell->getPort(ID::S)); + string a_expr = make_expr(cell->getPort(TW::A)); + string b_expr = make_expr(cell->getPort(TW::B)); + string s_expr = make_expr(cell->getPort(TW::S)); wire_decls.push_back(stringf("%swire %s: UInt<%d> %s\n", indent, y_id, width, cellFileinfo)); string expr = stringf("mux(%s, %s, %s)", s_expr, b_expr, a_expr); cell_exprs.push_back(stringf("%s%s <= %s %s\n", indent, y_id, expr, cellFileinfo)); - register_reverse_wire_map(y_id, cell->getPort(ID::Y)); + register_reverse_wire_map(y_id, cell->getPort(TW::Y)); continue; } @@ -908,13 +908,13 @@ struct FirrtlWorker log_error("Negative edge clock on FF %s.%s.\n", module, cell); int width = cell->parameters.at(ID::WIDTH).as_int(); - string expr = make_expr(cell->getPort(ID::D)); - string clk_expr = "asClock(" + make_expr(cell->getPort(ID::CLK)) + ")"; + string expr = make_expr(cell->getPort(TW::D)); + string clk_expr = "asClock(" + make_expr(cell->getPort(TW::CLK)) + ")"; wire_decls.push_back(stringf("%sreg %s: UInt<%d>, %s %s\n", indent, y_id, width, clk_expr, cellFileinfo)); cell_exprs.push_back(stringf("%s%s <= %s %s\n", indent, y_id, expr, cellFileinfo)); - register_reverse_wire_map(y_id, cell->getPort(ID::Q)); + register_reverse_wire_map(y_id, cell->getPort(TW::Q)); continue; } @@ -923,9 +923,9 @@ struct FirrtlWorker // assign y = a[b +: y_width]; // We'll extract the correct bits as part of the primop. - string a_expr = make_expr(cell->getPort(ID::A)); + string a_expr = make_expr(cell->getPort(TW::A)); // Get the initial bit selector - string b_expr = make_expr(cell->getPort(ID::B)); + string b_expr = make_expr(cell->getPort(TW::B)); wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent, y_id, y_width)); if (cell->getParam(ID::B_SIGNED).as_bool()) { @@ -937,15 +937,15 @@ struct FirrtlWorker string expr = stringf("dshr(%s, %s)", a_expr, b_expr); cell_exprs.push_back(stringf("%s%s <= %s\n", indent, y_id, expr)); - register_reverse_wire_map(y_id, cell->getPort(ID::Y)); + register_reverse_wire_map(y_id, cell->getPort(TW::Y)); continue; } if (cell->type == ID($shift)) { // assign y = a >> b; // where b may be negative - string a_expr = make_expr(cell->getPort(ID::A)); - string b_expr = make_expr(cell->getPort(ID::B)); + string a_expr = make_expr(cell->getPort(TW::A)); + string b_expr = make_expr(cell->getPort(TW::B)); auto b_string = b_expr.c_str(); string expr; wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent, y_id, y_width)); @@ -963,13 +963,13 @@ struct FirrtlWorker expr = stringf("dshr(%s, %s)", a_expr, b_string); } cell_exprs.push_back(stringf("%s%s <= %s\n", indent, y_id, expr)); - register_reverse_wire_map(y_id, cell->getPort(ID::Y)); + register_reverse_wire_map(y_id, cell->getPort(TW::Y)); continue; } if (cell->type == ID($pos)) { // assign y = a; // printCell(cell); - string a_expr = make_expr(cell->getPort(ID::A)); + string a_expr = make_expr(cell->getPort(TW::A)); // Verilog appears to treat the result as signed, so if the result is wider than "A", // we need to pad. if (a_width < y_width) { @@ -977,7 +977,7 @@ struct FirrtlWorker } wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent, y_id, y_width)); cell_exprs.push_back(stringf("%s%s <= %s\n", indent, y_id, a_expr)); - register_reverse_wire_map(y_id, cell->getPort(ID::Y)); + register_reverse_wire_map(y_id, cell->getPort(TW::Y)); continue; } diff --git a/backends/simplec/simplec.cc b/backends/simplec/simplec.cc index baf5aa006..b61328a70 100644 --- a/backends/simplec/simplec.cc +++ b/backends/simplec/simplec.cc @@ -380,8 +380,8 @@ struct SimplecWorker { if (cell->type.in(ID($_BUF_), ID($_NOT_))) { - SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A)); - SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y)); + SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A)); + SigBit y = sigmaps.at(work->module)(cell->getPort(TW::Y)); string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0"; string expr; @@ -399,9 +399,9 @@ struct SimplecWorker if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_))) { - SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A)); - SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B)); - SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y)); + SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A)); + SigBit b = sigmaps.at(work->module)(cell->getPort(TW::B)); + SigBit y = sigmaps.at(work->module)(cell->getPort(TW::Y)); string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0"; string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0"; @@ -426,10 +426,10 @@ struct SimplecWorker if (cell->type.in(ID($_AOI3_), ID($_OAI3_))) { - SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A)); - SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B)); - SigBit c = sigmaps.at(work->module)(cell->getPort(ID::C)); - SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y)); + SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A)); + SigBit b = sigmaps.at(work->module)(cell->getPort(TW::B)); + SigBit c = sigmaps.at(work->module)(cell->getPort(TW::C)); + SigBit y = sigmaps.at(work->module)(cell->getPort(TW::Y)); string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0"; string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0"; @@ -449,11 +449,11 @@ struct SimplecWorker if (cell->type.in(ID($_AOI4_), ID($_OAI4_))) { - SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A)); - SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B)); - SigBit c = sigmaps.at(work->module)(cell->getPort(ID::C)); - SigBit d = sigmaps.at(work->module)(cell->getPort(ID::D)); - SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y)); + SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A)); + SigBit b = sigmaps.at(work->module)(cell->getPort(TW::B)); + SigBit c = sigmaps.at(work->module)(cell->getPort(TW::C)); + SigBit d = sigmaps.at(work->module)(cell->getPort(TW::D)); + SigBit y = sigmaps.at(work->module)(cell->getPort(TW::Y)); string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0"; string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0"; @@ -474,10 +474,10 @@ struct SimplecWorker if (cell->type.in(ID($_MUX_), ID($_NMUX_))) { - SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A)); - SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B)); - SigBit s = sigmaps.at(work->module)(cell->getPort(ID::S)); - SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y)); + SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A)); + SigBit b = sigmaps.at(work->module)(cell->getPort(TW::B)); + SigBit s = sigmaps.at(work->module)(cell->getPort(TW::S)); + SigBit y = sigmaps.at(work->module)(cell->getPort(TW::Y)); string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0"; string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0"; diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index 3427e5d19..10a97cd1a 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -435,15 +435,15 @@ struct Smt2Worker void export_gate(RTLIL::Cell *cell, std::string expr) { - RTLIL::SigBit bit = sigmap(cell->getPort(ID::Y).as_bit()); + RTLIL::SigBit bit = sigmap(cell->getPort(TW::Y).as_bit()); std::string processed_expr; for (char ch : expr) { - if (ch == 'A') processed_expr += get_bool(cell->getPort(ID::A)); - else if (ch == 'B') processed_expr += get_bool(cell->getPort(ID::B)); - else if (ch == 'C') processed_expr += get_bool(cell->getPort(ID::C)); - else if (ch == 'D') processed_expr += get_bool(cell->getPort(ID::D)); - else if (ch == 'S') processed_expr += get_bool(cell->getPort(ID::S)); + if (ch == 'A') processed_expr += get_bool(cell->getPort(TW::A)); + else if (ch == 'B') processed_expr += get_bool(cell->getPort(TW::B)); + else if (ch == 'C') processed_expr += get_bool(cell->getPort(TW::C)); + else if (ch == 'D') processed_expr += get_bool(cell->getPort(TW::D)); + else if (ch == 'S') processed_expr += get_bool(cell->getPort(TW::S)); else processed_expr += ch; } @@ -459,26 +459,26 @@ struct Smt2Worker void export_bvop(RTLIL::Cell *cell, std::string expr, char type = 0) { RTLIL::SigSpec sig_a, sig_b; - RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y)); + RTLIL::SigSpec sig_y = sigmap(cell->getPort(TW::Y)); bool is_signed = type == 'U' ? false : cell->getParam(ID::A_SIGNED).as_bool(); int width = GetSize(sig_y); if (type == 's' || type == 'S' || type == 'd' || type == 'b') { if (type == 'b') - width = GetSize(cell->getPort(ID::A)); + width = GetSize(cell->getPort(TW::A)); else - width = max(width, GetSize(cell->getPort(ID::A))); + width = max(width, GetSize(cell->getPort(TW::A))); if (cell->hasPort(ID::B)) - width = max(width, GetSize(cell->getPort(ID::B))); + width = max(width, GetSize(cell->getPort(TW::B))); } if (cell->hasPort(ID::A)) { - sig_a = cell->getPort(ID::A); + sig_a = cell->getPort(TW::A); sig_a.extend_u0(width, is_signed); } if (cell->hasPort(ID::B)) { - sig_b = cell->getPort(ID::B); + sig_b = cell->getPort(TW::B); sig_b.extend_u0(width, (type == 'S') || (is_signed && !(type == 's'))); } @@ -487,8 +487,8 @@ struct Smt2Worker for (char ch : expr) { if (ch == 'A') processed_expr += get_bv(sig_a); else if (ch == 'B') processed_expr += get_bv(sig_b); - else if (ch == 'P') processed_expr += get_bv(cell->getPort(ID::B)); - else if (ch == 'S') processed_expr += get_bv(cell->getPort(ID::S)); + else if (ch == 'P') processed_expr += get_bv(cell->getPort(TW::B)); + else if (ch == 'S') processed_expr += get_bv(cell->getPort(TW::S)); else if (ch == 'L') processed_expr += is_signed ? "a" : "l"; else if (ch == 'U') processed_expr += is_signed ? "s" : "u"; else processed_expr += ch; @@ -515,7 +515,7 @@ struct Smt2Worker void export_reduce(RTLIL::Cell *cell, std::string expr, bool identity_val) { - RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y)); + RTLIL::SigSpec sig_y = sigmap(cell->getPort(TW::Y)); std::string processed_expr; for (char ch : expr) @@ -554,7 +554,7 @@ struct Smt2Worker if (cell->type == ID($initstate)) { - SigBit bit = sigmap(cell->getPort(ID::Y).as_bit()); + SigBit bit = sigmap(cell->getPort(TW::Y).as_bit()); decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool (|%s_is| state)) ; %s\n", get_id(module), idcounter, get_id(module), get_id(module), log_signal(bit))); register_bool(bit, idcounter++); @@ -565,11 +565,11 @@ struct Smt2Worker if (cell->type.in(ID($_FF_), ID($_DFF_P_), ID($_DFF_N_))) { registers.insert(cell); - SigBit q_bit = cell->getPort(ID::Q); + SigBit q_bit = cell->getPort(TW::Q); if (q_bit.is_wire()) decls.push_back(witness_signal("reg", 1, 0, "", idcounter, q_bit.wire)); - makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(cell->getPort(ID::Q))); - register_bool(cell->getPort(ID::Q), idcounter++); + makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(cell->getPort(TW::Q))); + register_bool(cell->getPort(TW::Q), idcounter++); recursive_cells.erase(cell); return; } @@ -599,13 +599,13 @@ struct Smt2Worker { registers.insert(cell); int smtoffset = 0; - for (auto chunk : cell->getPort(ID::Q).chunks()) { + for (auto chunk : cell->getPort(TW::Q).chunks()) { if (chunk.is_wire()) decls.push_back(witness_signal("reg", chunk.width, chunk.offset, "", idcounter, chunk.wire, smtoffset)); smtoffset += chunk.width; } - makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort(ID::Q)), log_signal(cell->getPort(ID::Q))); - register_bv(cell->getPort(ID::Q), idcounter++); + makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort(TW::Q)), log_signal(cell->getPort(TW::Q))); + register_bv(cell->getPort(TW::Q), idcounter++); recursive_cells.erase(cell); return; } @@ -667,7 +667,7 @@ struct Smt2Worker if (cell->getParam(ID::B_SIGNED).as_bool()) { return export_bvop(cell, stringf("(ite (bvsge P #b%0*d) " "(bvlshr A B) (bvshl A (bvneg B)))", - GetSize(cell->getPort(ID::B)), 0), 'S'); // type 'S' sign extends B + GetSize(cell->getPort(TW::B)), 0), 'S'); // type 'S' sign extends B } else { return export_bvop(cell, "(bvlshr A B)", 's'); } @@ -706,8 +706,8 @@ struct Smt2Worker if (cell->type == ID($divfloor)) { if (cell->getParam(ID::A_SIGNED).as_bool()) { // bvsdiv is truncating division, so we can't use it here. - int width = max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::B))); - width = max(width, GetSize(cell->getPort(ID::Y))); + int width = max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::B))); + width = max(width, GetSize(cell->getPort(TW::Y))); auto expr = stringf("(let (" "(a_neg (bvslt A #b%0*d)) " "(b_neg (bvslt B #b%0*d))) " @@ -725,9 +725,9 @@ struct Smt2Worker } if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool)) && - 2*GetSize(cell->getPort(ID::A).chunks()) < GetSize(cell->getPort(ID::A))) { + 2*GetSize(cell->getPort(TW::A).chunks()) < GetSize(cell->getPort(TW::A))) { bool is_and = cell->type == ID($reduce_and); - string bits(GetSize(cell->getPort(ID::A)), is_and ? '1' : '0'); + string bits(GetSize(cell->getPort(TW::A)), is_and ? '1' : '0'); return export_bvop(cell, stringf("(%s A #b%s)", is_and ? "=" : "distinct", bits), 'b'); } @@ -743,11 +743,11 @@ struct Smt2Worker if (cell->type.in(ID($mux), ID($pmux))) { - int width = GetSize(cell->getPort(ID::Y)); - std::string processed_expr = get_bv(cell->getPort(ID::A)); + int width = GetSize(cell->getPort(TW::Y)); + std::string processed_expr = get_bv(cell->getPort(TW::A)); - RTLIL::SigSpec sig_b = cell->getPort(ID::B); - RTLIL::SigSpec sig_s = cell->getPort(ID::S); + RTLIL::SigSpec sig_b = cell->getPort(TW::B); + RTLIL::SigSpec sig_s = cell->getPort(TW::S); get_bv(sig_b); get_bv(sig_s); @@ -758,7 +758,7 @@ struct Smt2Worker if (verbose) log("%*s-> import cell: %s\n", 2+2*GetSize(recursive_cells), "", cell); - RTLIL::SigSpec sig = sigmap(cell->getPort(ID::Y)); + RTLIL::SigSpec sig = sigmap(cell->getPort(TW::Y)); decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n", get_id(module), idcounter, get_id(module), width, processed_expr.c_str(), log_signal(sig))); register_bv(sig, idcounter++); @@ -971,7 +971,7 @@ struct Smt2Worker for (auto cell : module->cells()) if (cell->type.in(ID($ff), ID($dff), ID($_FF_), ID($_DFF_P_), ID($_DFF_N_), ID($anyinit))) { // not using sigmap -- we want the net directly at the dff output - for (auto bit : cell->getPort(ID::Q)) + for (auto bit : cell->getPort(TW::Q)) reg_bits.insert(bit); } @@ -1123,8 +1123,8 @@ struct Smt2Worker cell->type == ID($assume) ? 'u' : cell->type == ID($cover) ? 'c' : 0; - string name_a = get_bool(cell->getPort(ID::A)); - string name_en = get_bool(cell->getPort(ID::EN)); + string name_a = get_bool(cell->getPort(TW::A)); + string name_en = get_bool(cell->getPort(TW::EN)); bool private_name = cell->name[0] == '$'; if (!private_name && cell->has_attribute(ID::hdlname)) { @@ -1211,27 +1211,27 @@ struct Smt2Worker { if (cell->type.in(ID($_FF_), ID($_DFF_P_), ID($_DFF_N_))) { - std::string expr_d = get_bool(cell->getPort(ID::D)); - std::string expr_q = get_bool(cell->getPort(ID::Q), "next_state"); - trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d, expr_q, get_id(cell), log_signal(cell->getPort(ID::Q)))); - ex_state_eq.push_back(stringf("(= %s %s)", get_bool(cell->getPort(ID::Q)), get_bool(cell->getPort(ID::Q), "other_state"))); + std::string expr_d = get_bool(cell->getPort(TW::D)); + std::string expr_q = get_bool(cell->getPort(TW::Q), "next_state"); + trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d, expr_q, get_id(cell), log_signal(cell->getPort(TW::Q)))); + ex_state_eq.push_back(stringf("(= %s %s)", get_bool(cell->getPort(TW::Q)), get_bool(cell->getPort(TW::Q), "other_state"))); } if (cell->type.in(ID($ff), ID($dff), ID($anyinit))) { - std::string expr_d = get_bv(cell->getPort(ID::D)); - std::string expr_q = get_bv(cell->getPort(ID::Q), "next_state"); - trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d, expr_q, get_id(cell), log_signal(cell->getPort(ID::Q)))); - ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(ID::Q)), get_bv(cell->getPort(ID::Q), "other_state"))); + std::string expr_d = get_bv(cell->getPort(TW::D)); + std::string expr_q = get_bv(cell->getPort(TW::Q), "next_state"); + trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d, expr_q, get_id(cell), log_signal(cell->getPort(TW::Q)))); + ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(TW::Q)), get_bv(cell->getPort(TW::Q), "other_state"))); } if (cell->type.in(ID($anyconst), ID($allconst))) { - std::string expr_d = get_bv(cell->getPort(ID::Y)); - std::string expr_q = get_bv(cell->getPort(ID::Y), "next_state"); - trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d, expr_q, get_id(cell), log_signal(cell->getPort(ID::Y)))); + std::string expr_d = get_bv(cell->getPort(TW::Y)); + std::string expr_q = get_bv(cell->getPort(TW::Y), "next_state"); + trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d, expr_q, get_id(cell), log_signal(cell->getPort(TW::Y)))); if (cell->type == ID($anyconst)) - ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(ID::Y)), get_bv(cell->getPort(ID::Y), "other_state"))); + ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(TW::Y)), get_bv(cell->getPort(TW::Y), "other_state"))); } } diff --git a/backends/smv/smv.cc b/backends/smv/smv.cc index 01f95ef45..1f73993ca 100644 --- a/backends/smv/smv.cc +++ b/backends/smv/smv.cc @@ -229,8 +229,8 @@ struct SmvWorker if (cell->type.in(ID($assert))) { - SigSpec sig_a = cell->getPort(ID::A); - SigSpec sig_en = cell->getPort(ID::EN); + SigSpec sig_a = cell->getPort(TW::A); + SigSpec sig_en = cell->getPort(TW::EN); invarspecs.push_back(stringf("!bool(%s) | bool(%s);", rvalue(sig_en), rvalue(sig_a))); @@ -239,10 +239,10 @@ struct SmvWorker if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) { - SigSpec sig_a = cell->getPort(ID::A); - SigSpec sig_b = cell->getPort(ID::B); + SigSpec sig_a = cell->getPort(TW::A); + SigSpec sig_b = cell->getPort(TW::B); - int width_y = GetSize(cell->getPort(ID::Y)); + int width_y = GetSize(cell->getPort(TW::Y)); int shift_b_width = GetSize(sig_b); int width_ay = max(GetSize(sig_a), width_y); int width = width_ay; @@ -303,14 +303,14 @@ struct SmvWorker GetSize(sig_b)-shift_b_width, width_y, expr.c_str()); } - definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort(ID::Y)), expr)); + definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort(TW::Y)), expr)); continue; } if (cell->type.in(ID($not), ID($pos), ID($neg))) { - int width = GetSize(cell->getPort(ID::Y)); + int width = GetSize(cell->getPort(TW::Y)); string expr_a, op; if (cell->type == ID($not)) op = "!"; @@ -319,13 +319,13 @@ struct SmvWorker if (cell->getParam(ID::A_SIGNED).as_bool()) { - definitions.push_back(stringf("%s := unsigned(%s%s);", lvalue(cell->getPort(ID::Y)), - op.c_str(), rvalue_s(cell->getPort(ID::A), width))); + definitions.push_back(stringf("%s := unsigned(%s%s);", lvalue(cell->getPort(TW::Y)), + op.c_str(), rvalue_s(cell->getPort(TW::A), width))); } else { - definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(ID::Y)), - op.c_str(), rvalue_u(cell->getPort(ID::A), width))); + definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(TW::Y)), + op.c_str(), rvalue_u(cell->getPort(TW::A), width))); } continue; @@ -333,7 +333,7 @@ struct SmvWorker if (cell->type.in(ID($add), ID($sub), ID($mul), ID($and), ID($or), ID($xor), ID($xnor))) { - int width = GetSize(cell->getPort(ID::Y)); + int width = GetSize(cell->getPort(TW::Y)); string expr_a, expr_b, op; if (cell->type == ID($add)) op = "+"; @@ -346,13 +346,13 @@ struct SmvWorker if (cell->getParam(ID::A_SIGNED).as_bool()) { - definitions.push_back(stringf("%s := unsigned(%s %s %s);", lvalue(cell->getPort(ID::Y)), - rvalue_s(cell->getPort(ID::A), width), op.c_str(), rvalue_s(cell->getPort(ID::B), width))); + definitions.push_back(stringf("%s := unsigned(%s %s %s);", lvalue(cell->getPort(TW::Y)), + rvalue_s(cell->getPort(TW::A), width), op.c_str(), rvalue_s(cell->getPort(TW::B), width))); } else { - definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort(ID::Y)), - rvalue_u(cell->getPort(ID::A), width), op.c_str(), rvalue_u(cell->getPort(ID::B), width))); + definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort(TW::Y)), + rvalue_u(cell->getPort(TW::A), width), op.c_str(), rvalue_u(cell->getPort(TW::B), width))); } continue; @@ -361,9 +361,9 @@ struct SmvWorker // SMV has a "mod" operator, but its semantics don't seem to be well-defined - to be safe, don't generate it at all if (cell->type.in(ID($div)/*, ID($mod), ID($modfloor)*/)) { - int width_y = GetSize(cell->getPort(ID::Y)); - int width = max(width_y, GetSize(cell->getPort(ID::A))); - width = max(width, GetSize(cell->getPort(ID::B))); + int width_y = GetSize(cell->getPort(TW::Y)); + int width = max(width_y, GetSize(cell->getPort(TW::A))); + width = max(width, GetSize(cell->getPort(TW::B))); string expr_a, expr_b, op; if (cell->type == ID($div)) op = "/"; @@ -371,13 +371,13 @@ struct SmvWorker if (cell->getParam(ID::A_SIGNED).as_bool()) { - definitions.push_back(stringf("%s := resize(unsigned(%s %s %s), %d);", lvalue(cell->getPort(ID::Y)), - rvalue_s(cell->getPort(ID::A), width), op.c_str(), rvalue_s(cell->getPort(ID::B), width), width_y)); + definitions.push_back(stringf("%s := resize(unsigned(%s %s %s), %d);", lvalue(cell->getPort(TW::Y)), + rvalue_s(cell->getPort(TW::A), width), op.c_str(), rvalue_s(cell->getPort(TW::B), width), width_y)); } else { - definitions.push_back(stringf("%s := resize(%s %s %s, %d);", lvalue(cell->getPort(ID::Y)), - rvalue_u(cell->getPort(ID::A), width), op.c_str(), rvalue_u(cell->getPort(ID::B), width), width_y)); + definitions.push_back(stringf("%s := resize(%s %s %s, %d);", lvalue(cell->getPort(TW::Y)), + rvalue_u(cell->getPort(TW::A), width), op.c_str(), rvalue_u(cell->getPort(TW::B), width), width_y)); } continue; @@ -385,7 +385,7 @@ struct SmvWorker if (cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex), ID($lt), ID($le), ID($ge), ID($gt))) { - int width = max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::B))); + int width = max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::B))); string expr_a, expr_b, op; if (cell->type == ID($eq)) op = "="; @@ -399,27 +399,27 @@ struct SmvWorker if (cell->getParam(ID::A_SIGNED).as_bool()) { - expr_a = stringf("resize(signed(%s), %d)", rvalue(cell->getPort(ID::A)), width); - expr_b = stringf("resize(signed(%s), %d)", rvalue(cell->getPort(ID::B)), width); + expr_a = stringf("resize(signed(%s), %d)", rvalue(cell->getPort(TW::A)), width); + expr_b = stringf("resize(signed(%s), %d)", rvalue(cell->getPort(TW::B)), width); } else { - expr_a = stringf("resize(%s, %d)", rvalue(cell->getPort(ID::A)), width); - expr_b = stringf("resize(%s, %d)", rvalue(cell->getPort(ID::B)), width); + expr_a = stringf("resize(%s, %d)", rvalue(cell->getPort(TW::A)), width); + expr_b = stringf("resize(%s, %d)", rvalue(cell->getPort(TW::B)), width); } - definitions.push_back(stringf("%s := resize(word1(%s %s %s), %d);", lvalue(cell->getPort(ID::Y)), - expr_a.c_str(), op.c_str(), expr_b.c_str(), GetSize(cell->getPort(ID::Y)))); + definitions.push_back(stringf("%s := resize(word1(%s %s %s), %d);", lvalue(cell->getPort(TW::Y)), + expr_a.c_str(), op.c_str(), expr_b.c_str(), GetSize(cell->getPort(TW::Y)))); continue; } if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) { - int width_a = GetSize(cell->getPort(ID::A)); - int width_y = GetSize(cell->getPort(ID::Y)); - const char *expr_a = rvalue(cell->getPort(ID::A)); - const char *expr_y = lvalue(cell->getPort(ID::Y)); + int width_a = GetSize(cell->getPort(TW::A)); + int width_y = GetSize(cell->getPort(TW::Y)); + const char *expr_a = rvalue(cell->getPort(TW::A)); + const char *expr_y = lvalue(cell->getPort(TW::Y)); string expr; if (cell->type == ID($reduce_and)) expr = stringf("%s = !0ub%d_0", expr_a, width_a); @@ -432,11 +432,11 @@ struct SmvWorker if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) { - int width_y = GetSize(cell->getPort(ID::Y)); - const char *expr_y = lvalue(cell->getPort(ID::Y)); + int width_y = GetSize(cell->getPort(TW::Y)); + const char *expr_y = lvalue(cell->getPort(TW::Y)); string expr; - for (auto bit : cell->getPort(ID::A)) { + for (auto bit : cell->getPort(TW::A)) { if (!expr.empty()) expr += " xor "; expr += rvalue(bit); @@ -451,13 +451,13 @@ struct SmvWorker if (cell->type.in(ID($logic_and), ID($logic_or))) { - int width_a = GetSize(cell->getPort(ID::A)); - int width_b = GetSize(cell->getPort(ID::B)); - int width_y = GetSize(cell->getPort(ID::Y)); + int width_a = GetSize(cell->getPort(TW::A)); + int width_b = GetSize(cell->getPort(TW::B)); + int width_y = GetSize(cell->getPort(TW::Y)); - string expr_a = stringf("(%s != 0ub%d_0)", rvalue(cell->getPort(ID::A)), width_a); - string expr_b = stringf("(%s != 0ub%d_0)", rvalue(cell->getPort(ID::B)), width_b); - const char *expr_y = lvalue(cell->getPort(ID::Y)); + string expr_a = stringf("(%s != 0ub%d_0)", rvalue(cell->getPort(TW::A)), width_a); + string expr_b = stringf("(%s != 0ub%d_0)", rvalue(cell->getPort(TW::B)), width_b); + const char *expr_y = lvalue(cell->getPort(TW::Y)); string expr; if (cell->type == ID($logic_and)) expr = expr_a + " & " + expr_b; @@ -469,11 +469,11 @@ struct SmvWorker if (cell->type.in(ID($logic_not))) { - int width_a = GetSize(cell->getPort(ID::A)); - int width_y = GetSize(cell->getPort(ID::Y)); + int width_a = GetSize(cell->getPort(TW::A)); + int width_y = GetSize(cell->getPort(TW::Y)); - string expr_a = stringf("(%s = 0ub%d_0)", rvalue(cell->getPort(ID::A)), width_a); - const char *expr_y = lvalue(cell->getPort(ID::Y)); + string expr_a = stringf("(%s = 0ub%d_0)", rvalue(cell->getPort(TW::A)), width_a); + const char *expr_y = lvalue(cell->getPort(TW::Y)); definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr_a, width_y)); continue; @@ -481,31 +481,31 @@ struct SmvWorker if (cell->type.in(ID($mux), ID($pmux))) { - int width = GetSize(cell->getPort(ID::Y)); - SigSpec sig_a = cell->getPort(ID::A); - SigSpec sig_b = cell->getPort(ID::B); - SigSpec sig_s = cell->getPort(ID::S); + int width = GetSize(cell->getPort(TW::Y)); + SigSpec sig_a = cell->getPort(TW::A); + SigSpec sig_b = cell->getPort(TW::B); + SigSpec sig_s = cell->getPort(TW::S); string expr; for (int i = 0; i < GetSize(sig_s); i++) expr += stringf("bool(%s) ? %s : ", rvalue(sig_s[i]), rvalue(sig_b.extract(i*width, width))); expr += rvalue(sig_a); - definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort(ID::Y)), expr)); + definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort(TW::Y)), expr)); continue; } if (cell->type == ID($dff)) { - vars.push_back(stringf("%s : unsigned word[%d]; -- %s", lvalue(cell->getPort(ID::Q)), GetSize(cell->getPort(ID::Q)), log_signal(cell->getPort(ID::Q)))); - assignments.push_back(stringf("next(%s) := %s;", lvalue(cell->getPort(ID::Q)), rvalue(cell->getPort(ID::D)))); + vars.push_back(stringf("%s : unsigned word[%d]; -- %s", lvalue(cell->getPort(TW::Q)), GetSize(cell->getPort(TW::Q)), log_signal(cell->getPort(TW::Q)))); + assignments.push_back(stringf("next(%s) := %s;", lvalue(cell->getPort(TW::Q)), rvalue(cell->getPort(TW::D)))); continue; } if (cell->type.in(ID($_BUF_), ID($_NOT_))) { string op = cell->type == ID($_NOT_) ? "!" : ""; - definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(ID::Y)), op, rvalue(cell->getPort(ID::A)))); + definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(TW::Y)), op, rvalue(cell->getPort(TW::A)))); continue; } @@ -519,57 +519,57 @@ struct SmvWorker if (cell->type.in(ID($_XNOR_))) op = "xnor"; if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_))) - definitions.push_back(stringf("%s := %s %s (!%s);", lvalue(cell->getPort(ID::Y)), - rvalue(cell->getPort(ID::A)), op.c_str(), rvalue(cell->getPort(ID::B)))); + definitions.push_back(stringf("%s := %s %s (!%s);", lvalue(cell->getPort(TW::Y)), + rvalue(cell->getPort(TW::A)), op.c_str(), rvalue(cell->getPort(TW::B)))); else if (cell->type.in(ID($_NAND_), ID($_NOR_))) - definitions.push_back(stringf("%s := !(%s %s %s);", lvalue(cell->getPort(ID::Y)), - rvalue(cell->getPort(ID::A)), op.c_str(), rvalue(cell->getPort(ID::B)))); + definitions.push_back(stringf("%s := !(%s %s %s);", lvalue(cell->getPort(TW::Y)), + rvalue(cell->getPort(TW::A)), op.c_str(), rvalue(cell->getPort(TW::B)))); else - definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort(ID::Y)), - rvalue(cell->getPort(ID::A)), op.c_str(), rvalue(cell->getPort(ID::B)))); + definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort(TW::Y)), + rvalue(cell->getPort(TW::A)), op.c_str(), rvalue(cell->getPort(TW::B)))); continue; } if (cell->type == ID($_MUX_)) { - definitions.push_back(stringf("%s := bool(%s) ? %s : %s;", lvalue(cell->getPort(ID::Y)), - rvalue(cell->getPort(ID::S)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::A)))); + definitions.push_back(stringf("%s := bool(%s) ? %s : %s;", lvalue(cell->getPort(TW::Y)), + rvalue(cell->getPort(TW::S)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::A)))); continue; } if (cell->type == ID($_NMUX_)) { - definitions.push_back(stringf("%s := !(bool(%s) ? %s : %s);", lvalue(cell->getPort(ID::Y)), - rvalue(cell->getPort(ID::S)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::A)))); + definitions.push_back(stringf("%s := !(bool(%s) ? %s : %s);", lvalue(cell->getPort(TW::Y)), + rvalue(cell->getPort(TW::S)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::A)))); continue; } if (cell->type == ID($_AOI3_)) { - definitions.push_back(stringf("%s := !((%s & %s) | %s);", lvalue(cell->getPort(ID::Y)), - rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::C)))); + definitions.push_back(stringf("%s := !((%s & %s) | %s);", lvalue(cell->getPort(TW::Y)), + rvalue(cell->getPort(TW::A)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::C)))); continue; } if (cell->type == ID($_OAI3_)) { - definitions.push_back(stringf("%s := !((%s | %s) & %s);", lvalue(cell->getPort(ID::Y)), - rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::C)))); + definitions.push_back(stringf("%s := !((%s | %s) & %s);", lvalue(cell->getPort(TW::Y)), + rvalue(cell->getPort(TW::A)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::C)))); continue; } if (cell->type == ID($_AOI4_)) { - definitions.push_back(stringf("%s := !((%s & %s) | (%s & %s));", lvalue(cell->getPort(ID::Y)), - rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::C)), rvalue(cell->getPort(ID::D)))); + definitions.push_back(stringf("%s := !((%s & %s) | (%s & %s));", lvalue(cell->getPort(TW::Y)), + rvalue(cell->getPort(TW::A)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::C)), rvalue(cell->getPort(TW::D)))); continue; } if (cell->type == ID($_OAI4_)) { - definitions.push_back(stringf("%s := !((%s | %s) & (%s | %s));", lvalue(cell->getPort(ID::Y)), - rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::C)), rvalue(cell->getPort(ID::D)))); + definitions.push_back(stringf("%s := !((%s | %s) & (%s | %s));", lvalue(cell->getPort(TW::Y)), + rvalue(cell->getPort(TW::A)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::C)), rvalue(cell->getPort(TW::D)))); continue; } diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index d9dbe39b6..55a27d713 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -991,7 +991,7 @@ std::string cellname(RTLIL::Cell *cell) { if (!norename && cell->name[0] == '$' && cell->is_builtin_ff() && cell->hasPort(ID::Q) && !cell->type.in(ID($ff), ID($_FF_))) { - RTLIL::SigSpec sig = cell->getPort(ID::Q); + RTLIL::SigSpec sig = cell->getPort(TW::Q); if (GetSize(sig) != 1 || sig.is_fully_const()) goto no_special_reg_name; @@ -1026,7 +1026,7 @@ no_special_reg_name: void dump_cell_expr_uniop(std::ostream &f, std::string indent, RTLIL::Cell *cell, std::string op) { f << stringf("%s" "assign ", indent); - dump_sigspec(f, cell->getPort(ID::Y)); + dump_sigspec(f, cell->getPort(TW::Y)); f << stringf(" = %s ", op); dump_attributes(f, "", cell->attributes, " "); dump_cell_expr_port(f, cell, "A", true); @@ -1036,7 +1036,7 @@ void dump_cell_expr_uniop(std::ostream &f, std::string indent, RTLIL::Cell *cell void dump_cell_expr_binop(std::ostream &f, std::string indent, RTLIL::Cell *cell, std::string op) { f << stringf("%s" "assign ", indent); - dump_sigspec(f, cell->getPort(ID::Y)); + dump_sigspec(f, cell->getPort(TW::Y)); f << stringf(" = "); dump_cell_expr_port(f, cell, "A", true); f << stringf(" %s ", op); @@ -1100,7 +1100,7 @@ void dump_cell_expr_check(std::ostream &f, std::string indent, const RTLIL::Cell f << stringf("%s" "%s" "cover (", indent, label); else log_abort(); - dump_sigspec(f, cell->getPort(ID::A)); + dump_sigspec(f, cell->getPort(TW::A)); f << stringf(");\n"); } @@ -1108,7 +1108,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) { if (cell->type == ID($_NOT_)) { f << stringf("%s" "assign ", indent); - dump_sigspec(f, cell->getPort(ID::Y)); + dump_sigspec(f, cell->getPort(TW::Y)); f << stringf(" = "); f << stringf("~"); dump_attributes(f, "", cell->attributes, " "); @@ -1118,9 +1118,9 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) } if (cell->type.in(ID($_BUF_), ID($buf))) { - if (cell->type == ID($buf) && cell->getPort(ID::A).has_const(State::Sz)) { - RTLIL::SigSpec a = cell->getPort(ID::A); - RTLIL::SigSpec y = cell->getPort(ID::Y); + if (cell->type == ID($buf) && cell->getPort(TW::A).has_const(State::Sz)) { + RTLIL::SigSpec a = cell->getPort(TW::A); + RTLIL::SigSpec y = cell->getPort(TW::Y); a.extend_u0(GetSize(y)); if (a.has_const(State::Sz)) { @@ -1146,7 +1146,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } f << stringf("%s" "assign ", indent); - dump_sigspec(f, cell->getPort(ID::Y)); + dump_sigspec(f, cell->getPort(TW::Y)); f << stringf(" = "); dump_cell_expr_port(f, cell, "A", false); f << stringf(";\n"); @@ -1155,7 +1155,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_))) { f << stringf("%s" "assign ", indent); - dump_sigspec(f, cell->getPort(ID::Y)); + dump_sigspec(f, cell->getPort(TW::Y)); f << stringf(" = "); if (cell->type.in(ID($_NAND_), ID($_NOR_), ID($_XNOR_))) f << stringf("~("); @@ -1180,7 +1180,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == ID($_MUX_)) { f << stringf("%s" "assign ", indent); - dump_sigspec(f, cell->getPort(ID::Y)); + dump_sigspec(f, cell->getPort(TW::Y)); f << stringf(" = "); dump_cell_expr_port(f, cell, "S", false); f << stringf(" ? "); @@ -1194,7 +1194,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == ID($_NMUX_)) { f << stringf("%s" "assign ", indent); - dump_sigspec(f, cell->getPort(ID::Y)); + dump_sigspec(f, cell->getPort(TW::Y)); f << stringf(" = !("); dump_cell_expr_port(f, cell, "S", false); f << stringf(" ? "); @@ -1208,7 +1208,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type.in(ID($_AOI3_), ID($_OAI3_))) { f << stringf("%s" "assign ", indent); - dump_sigspec(f, cell->getPort(ID::Y)); + dump_sigspec(f, cell->getPort(TW::Y)); f << stringf(" = ~(("); dump_cell_expr_port(f, cell, "A", false); f << (cell->type == ID($_AOI3_) ? " & " : " | "); @@ -1223,7 +1223,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type.in(ID($_AOI4_), ID($_OAI4_))) { f << stringf("%s" "assign ", indent); - dump_sigspec(f, cell->getPort(ID::Y)); + dump_sigspec(f, cell->getPort(TW::Y)); f << stringf(" = ~(("); dump_cell_expr_port(f, cell, "A", false); f << (cell->type == ID($_AOI4_) ? " & " : " | "); @@ -1295,15 +1295,15 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) // assign Y = $signed(_2_) / $signed(_1_); if (cell->getParam(ID::A_SIGNED).as_bool() && cell->getParam(ID::B_SIGNED).as_bool()) { - SigSpec sig_a = cell->getPort(ID::A); - SigSpec sig_b = cell->getPort(ID::B); + SigSpec sig_a = cell->getPort(TW::A); + SigSpec sig_b = cell->getPort(TW::B); std::string buf_a = next_auto_id(); std::string buf_b = next_auto_id(); std::string buf_num = next_auto_id(); int size_a = GetSize(sig_a); int size_b = GetSize(sig_b); - int size_y = GetSize(cell->getPort(ID::Y)); + int size_y = GetSize(cell->getPort(TW::Y)); int size_max = std::max(size_a, std::max(size_b, size_y)); // intentionally one wider than maximum width @@ -1329,7 +1329,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf("%s" "assign ", indent); - dump_sigspec(f, cell->getPort(ID::Y)); + dump_sigspec(f, cell->getPort(TW::Y)); f << stringf(" = $signed(%s) / ", buf_num); dump_attributes(f, "", cell->attributes, " "); f << stringf("$signed(%s);\n", buf_b); @@ -1347,11 +1347,11 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) // assign Y = (A[-1] == B[-1]) || truncated == 0 ? $signed(truncated) : $signed(B) + $signed(truncated); if (cell->getParam(ID::A_SIGNED).as_bool() && cell->getParam(ID::B_SIGNED).as_bool()) { - SigSpec sig_a = cell->getPort(ID::A); - SigSpec sig_b = cell->getPort(ID::B); + SigSpec sig_a = cell->getPort(TW::A); + SigSpec sig_b = cell->getPort(TW::B); std::string temp_id = next_auto_id(); - f << stringf("%s" "wire [%d:0] %s = ", indent, GetSize(cell->getPort(ID::A))-1, temp_id); + f << stringf("%s" "wire [%d:0] %s = ", indent, GetSize(cell->getPort(TW::A))-1, temp_id); dump_cell_expr_port(f, cell, "A", true); f << stringf(" %% "); dump_attributes(f, "", cell->attributes, " "); @@ -1359,7 +1359,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf(";\n"); f << stringf("%s" "assign ", indent); - dump_sigspec(f, cell->getPort(ID::Y)); + dump_sigspec(f, cell->getPort(TW::Y)); f << stringf(" = ("); dump_sigspec(f, sig_a.extract(sig_a.size()-1)); f << stringf(" == "); @@ -1378,7 +1378,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == ID($shift)) { f << stringf("%s" "assign ", indent); - dump_sigspec(f, cell->getPort(ID::Y)); + dump_sigspec(f, cell->getPort(TW::Y)); f << stringf(" = "); if (cell->getParam(ID::B_SIGNED).as_bool()) { @@ -1386,17 +1386,17 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf(" < 0 ? "); dump_cell_expr_port(f, cell, "A", true); f << stringf(" << - "); - dump_sigspec(f, cell->getPort(ID::B)); + dump_sigspec(f, cell->getPort(TW::B)); f << stringf(" : "); dump_cell_expr_port(f, cell, "A", true); f << stringf(" >> "); - dump_sigspec(f, cell->getPort(ID::B)); + dump_sigspec(f, cell->getPort(TW::B)); } else { dump_cell_expr_port(f, cell, "A", true); f << stringf(" >> "); - dump_sigspec(f, cell->getPort(ID::B)); + dump_sigspec(f, cell->getPort(TW::B)); } f << stringf(";\n"); return true; @@ -1405,16 +1405,16 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == ID($shiftx)) { std::string temp_id = next_auto_id(); - f << stringf("%s" "wire [%d:0] %s = ", indent, GetSize(cell->getPort(ID::A))-1, temp_id); - dump_sigspec(f, cell->getPort(ID::A)); + f << stringf("%s" "wire [%d:0] %s = ", indent, GetSize(cell->getPort(TW::A))-1, temp_id); + dump_sigspec(f, cell->getPort(TW::A)); f << stringf(";\n"); f << stringf("%s" "assign ", indent); - dump_sigspec(f, cell->getPort(ID::Y)); + dump_sigspec(f, cell->getPort(TW::Y)); f << stringf(" = %s[", temp_id); if (cell->getParam(ID::B_SIGNED).as_bool()) f << stringf("$signed("); - dump_sigspec(f, cell->getPort(ID::B)); + dump_sigspec(f, cell->getPort(TW::B)); if (cell->getParam(ID::B_SIGNED).as_bool()) f << stringf(")"); f << stringf(" +: %d", cell->getParam(ID::Y_WIDTH).as_int()); @@ -1425,14 +1425,14 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == ID($mux)) { f << stringf("%s" "assign ", indent); - dump_sigspec(f, cell->getPort(ID::Y)); + dump_sigspec(f, cell->getPort(TW::Y)); f << stringf(" = "); - dump_sigspec(f, cell->getPort(ID::S)); + dump_sigspec(f, cell->getPort(TW::S)); f << stringf(" ? "); dump_attributes(f, "", cell->attributes, " "); - dump_sigspec(f, cell->getPort(ID::B)); + dump_sigspec(f, cell->getPort(TW::B)); f << stringf(" : "); - dump_sigspec(f, cell->getPort(ID::A)); + dump_sigspec(f, cell->getPort(TW::A)); f << stringf(";\n"); return true; } @@ -1440,7 +1440,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == ID($pmux)) { int width = cell->parameters[ID::WIDTH].as_int(); - int s_width = cell->getPort(ID::S).size(); + int s_width = cell->getPort(TW::S).size(); std::string func_name = cellname(cell); f << stringf("%s" "function [%d:0] %s;\n", indent, width-1, func_name); @@ -1486,13 +1486,13 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf("%s" "endfunction\n", indent); f << stringf("%s" "assign ", indent); - dump_sigspec(f, cell->getPort(ID::Y)); + dump_sigspec(f, cell->getPort(TW::Y)); f << stringf(" = %s(", func_name); - dump_sigspec(f, cell->getPort(ID::A)); + dump_sigspec(f, cell->getPort(TW::A)); f << stringf(", "); - dump_sigspec(f, cell->getPort(ID::B)); + dump_sigspec(f, cell->getPort(TW::B)); f << stringf(", "); - dump_sigspec(f, cell->getPort(ID::S)); + dump_sigspec(f, cell->getPort(TW::S)); f << stringf(");\n"); return true; } @@ -1500,11 +1500,11 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == ID($tribuf)) { f << stringf("%s" "assign ", indent); - dump_sigspec(f, cell->getPort(ID::Y)); + dump_sigspec(f, cell->getPort(TW::Y)); f << stringf(" = "); - dump_sigspec(f, cell->getPort(ID::EN)); + dump_sigspec(f, cell->getPort(TW::EN)); f << stringf(" ? "); - dump_sigspec(f, cell->getPort(ID::A)); + dump_sigspec(f, cell->getPort(TW::A)); f << stringf(" : %d'bz;\n", cell->parameters.at(ID::WIDTH).as_int()); return true; } @@ -1512,9 +1512,9 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == ID($slice)) { f << stringf("%s" "assign ", indent); - dump_sigspec(f, cell->getPort(ID::Y)); + dump_sigspec(f, cell->getPort(TW::Y)); f << stringf(" = "); - dump_sigspec(f, cell->getPort(ID::A)); + dump_sigspec(f, cell->getPort(TW::A)); f << stringf(" >> %d;\n", cell->parameters.at(ID::OFFSET).as_int()); return true; } @@ -1522,11 +1522,11 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == ID($concat)) { f << stringf("%s" "assign ", indent); - dump_sigspec(f, cell->getPort(ID::Y)); + dump_sigspec(f, cell->getPort(TW::Y)); f << stringf(" = { "); - dump_sigspec(f, cell->getPort(ID::B)); + dump_sigspec(f, cell->getPort(TW::B)); f << stringf(" , "); - dump_sigspec(f, cell->getPort(ID::A)); + dump_sigspec(f, cell->getPort(TW::A)); f << stringf(" };\n"); return true; } @@ -1534,12 +1534,12 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == ID($lut)) { f << stringf("%s" "assign ", indent); - dump_sigspec(f, cell->getPort(ID::Y)); + dump_sigspec(f, cell->getPort(TW::Y)); f << stringf(" = "); dump_const(f, cell->parameters.at(ID::LUT)); f << stringf(" >> "); dump_attributes(f, "", cell->attributes, " "); - dump_sigspec(f, cell->getPort(ID::A)); + dump_sigspec(f, cell->getPort(TW::A)); f << stringf(";\n"); return true; } @@ -1552,16 +1552,16 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) int width = cell->getParam(ID::WIDTH).as_int() ; if (width == 1) { f << stringf("%s" "tran(", indent); - dump_sigspec(f, cell->getPort(ID::A)); + dump_sigspec(f, cell->getPort(TW::A)); f << stringf(", "); - dump_sigspec(f, cell->getPort(ID::B)); + dump_sigspec(f, cell->getPort(TW::B)); f << stringf(");\n"); } else { auto tran_id = next_auto_id(); f << stringf("%s" "tran %s[%d:0](", indent, tran_id, width - 1); - dump_sigspec(f, cell->getPort(ID::A)); + dump_sigspec(f, cell->getPort(TW::A)); f << stringf(", "); - dump_sigspec(f, cell->getPort(ID::B)); + dump_sigspec(f, cell->getPort(TW::B)); f << stringf(");\n"); } return true; @@ -1794,9 +1794,9 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type.in(ID($assert), ID($assume), ID($cover))) { f << stringf("%s" "always%s if (", indent, systemverilog ? "_comb" : " @*"); - dump_sigspec(f, cell->getPort(ID::EN)); + dump_sigspec(f, cell->getPort(TW::EN)); f << stringf(") %s(", cell->type.c_str()+1); - dump_sigspec(f, cell->getPort(ID::A)); + dump_sigspec(f, cell->getPort(TW::A)); f << stringf(");\n"); return true; } @@ -1805,10 +1805,10 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) { f << stringf("%s" "specify\n%s ", indent, indent); - SigSpec en = cell->getPort(ID::EN); + SigSpec en = cell->getPort(TW::EN); if (en != State::S1) { f << stringf("if ("); - dump_sigspec(f, cell->getPort(ID::EN)); + dump_sigspec(f, cell->getPort(TW::EN)); f << stringf(") "); } @@ -1816,7 +1816,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == ID($specify3) && cell->getParam(ID::EDGE_EN).as_bool()) f << (cell->getParam(ID::EDGE_POL).as_bool() ? "posedge ": "negedge "); - dump_sigspec(f, cell->getPort(ID::SRC)); + dump_sigspec(f, cell->getPort(TW::SRC)); f << " "; if (cell->getParam(ID::SRC_DST_PEN).as_bool()) @@ -1825,15 +1825,15 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == ID($specify3)) { f << "("; - dump_sigspec(f, cell->getPort(ID::DST)); + dump_sigspec(f, cell->getPort(TW::DST)); f << " "; if (cell->getParam(ID::DAT_DST_PEN).as_bool()) f << (cell->getParam(ID::DAT_DST_POL).as_bool() ? "+": "-"); f << ": "; - dump_sigspec(f, cell->getPort(ID::DAT)); + dump_sigspec(f, cell->getPort(TW::DAT)); f << ")"; } else { - dump_sigspec(f, cell->getPort(ID::DST)); + dump_sigspec(f, cell->getPort(TW::DST)); } bool bak_decimal = decimal; @@ -1868,21 +1868,21 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->getParam(ID::SRC_PEN).as_bool()) f << (cell->getParam(ID::SRC_POL).as_bool() ? "posedge ": "negedge "); - dump_sigspec(f, cell->getPort(ID::SRC)); + dump_sigspec(f, cell->getPort(TW::SRC)); - if (cell->getPort(ID::SRC_EN) != State::S1) { + if (cell->getPort(TW::SRC_EN) != State::S1) { f << " &&& "; - dump_sigspec(f, cell->getPort(ID::SRC_EN)); + dump_sigspec(f, cell->getPort(TW::SRC_EN)); } f << ", "; if (cell->getParam(ID::DST_PEN).as_bool()) f << (cell->getParam(ID::DST_POL).as_bool() ? "posedge ": "negedge "); - dump_sigspec(f, cell->getPort(ID::DST)); + dump_sigspec(f, cell->getPort(TW::DST)); - if (cell->getPort(ID::DST_EN) != State::S1) { + if (cell->getPort(TW::DST_EN) != State::S1) { f << " &&& "; - dump_sigspec(f, cell->getPort(ID::DST_EN)); + dump_sigspec(f, cell->getPort(TW::DST_EN)); } bool bak_decimal = decimal; @@ -1920,7 +1920,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf("%s" "always @*\n", indent); f << stringf("%s" " if (", indent); - dump_sigspec(f, cell->getPort(ID::EN)); + dump_sigspec(f, cell->getPort(TW::EN)); f << stringf(")\n"); dump_cell_expr_print(f, indent + " ", cell); @@ -1936,7 +1936,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf("%s" "always @*\n", indent); f << stringf("%s" " if (", indent); - dump_sigspec(f, cell->getPort(ID::EN)); + dump_sigspec(f, cell->getPort(TW::EN)); f << stringf(") begin\n"); std::string flavor = cell->getParam(ID::FLAVOR).decode_string(); @@ -1945,7 +1945,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) fmt.parse_rtlil(cell); if (!fmt.parts.empty()) { f << stringf("%s" " if (!", indent); - dump_sigspec(f, cell->getPort(ID::A)); + dump_sigspec(f, cell->getPort(TW::A)); f << stringf(")\n"); dump_cell_expr_print(f, indent + " ", cell); } @@ -2047,7 +2047,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (siminit && cell->is_builtin_ff() && cell->hasPort(ID::Q) && !cell->type.in(ID($ff), ID($_FF_))) { std::stringstream ss; - dump_reg_init(ss, cell->getPort(ID::Q)); + dump_reg_init(ss, cell->getPort(TW::Q)); if (!ss.str().empty()) { f << stringf("%sinitial %s.Q", indent, cell_name); f << ss.str(); @@ -2079,7 +2079,7 @@ void dump_sync_effect(std::ostream &f, std::string indent, const RTLIL::SigSpec }); for (auto cell : cells) { f << stringf("%s" " if (", indent); - dump_sigspec(f, cell->getPort(ID::EN)); + dump_sigspec(f, cell->getPort(TW::EN)); f << stringf(") begin\n"); if (cell->type == ID($print)) { @@ -2091,7 +2091,7 @@ void dump_sync_effect(std::ostream &f, std::string indent, const RTLIL::SigSpec fmt.parse_rtlil(cell); if (!fmt.parts.empty()) { f << stringf("%s" " if (!", indent); - dump_sigspec(f, cell->getPort(ID::A)); + dump_sigspec(f, cell->getPort(TW::A)); f << stringf(")\n"); dump_cell_expr_print(f, indent + " ", cell); } @@ -2402,14 +2402,14 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) for (auto cell : module->cells()) { if (cell->type.in(ID($print), ID($check)) && cell->getParam(ID::TRG_ENABLE).as_bool()) { - sync_effect_cells[make_pair(cell->getPort(ID::TRG), cell->getParam(ID::TRG_POLARITY))].push_back(cell); + sync_effect_cells[make_pair(cell->getPort(TW::TRG), cell->getParam(ID::TRG_POLARITY))].push_back(cell); continue; } if (!cell->is_builtin_ff() || !cell->hasPort(ID::Q) || cell->type.in(ID($ff), ID($_FF_))) continue; - RTLIL::SigSpec sig = cell->getPort(ID::Q); + RTLIL::SigSpec sig = cell->getPort(TW::Q); if (sig.is_chunk()) { RTLIL::SigChunk chunk = sig.as_chunk(); diff --git a/docs/source/code_examples/extensions/my_cmd.cc b/docs/source/code_examples/extensions/my_cmd.cc index 742697b6e..b6aa8d54d 100644 --- a/docs/source/code_examples/extensions/my_cmd.cc +++ b/docs/source/code_examples/extensions/my_cmd.cc @@ -38,7 +38,7 @@ struct Test1Pass : public Pass { y->port_output = true; y->port_id = 2; - RTLIL::Wire *a_inv = module->addWire(NEW_ID, 4); + RTLIL::Wire *a_inv = module->addWire(NEW_TWINE, 4); module->addNeg(NEW_ID, a, a_inv, true); module->addMux(NEW_ID, a, a_inv, RTLIL::SigSpec(a, 3), y); diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 009e1e81c..6cc94177b 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -130,7 +130,7 @@ struct ConstEvalAig sig2deps[output].insert(output); RTLIL::Cell *cell = sig2driver.at(output); - RTLIL::SigBit sig_a = cell->getPort(ID::A); + RTLIL::SigBit sig_a = cell->getPort(TW::A); sig2deps[sig_a].reserve(sig2deps[sig_a].size() + sig2deps[output].size()); // Reserve so that any invalidation // that may occur does so here, and // not mid insertion (below) @@ -139,7 +139,7 @@ struct ConstEvalAig compute_deps(sig_a, inputs); if (cell->type == ID($_AND_)) { - RTLIL::SigSpec sig_b = cell->getPort(ID::B); + RTLIL::SigSpec sig_b = cell->getPort(TW::B); sig2deps[sig_b].reserve(sig2deps[sig_b].size() + sig2deps[output].size()); // Reserve so that any invalidation // that may occur does so here, and // not mid insertion (below) @@ -155,11 +155,11 @@ struct ConstEvalAig bool eval(RTLIL::Cell *cell) { - RTLIL::SigBit sig_y = cell->getPort(ID::Y); + RTLIL::SigBit sig_y = cell->getPort(TW::Y); if (values_map.count(sig_y)) return true; - RTLIL::SigBit sig_a = cell->getPort(ID::A); + RTLIL::SigBit sig_a = cell->getPort(TW::A); if (!eval(sig_a)) return false; @@ -175,7 +175,7 @@ struct ConstEvalAig } { - RTLIL::SigBit sig_b = cell->getPort(ID::B); + RTLIL::SigBit sig_b = cell->getPort(TW::B); if (!eval(sig_b)) return false; if (sig_b == State::S0) { @@ -978,7 +978,7 @@ void AigerReader::post_process() for (auto cell : module->cells().to_vector()) { if (cell->type != ID($lut)) continue; - auto y_port = cell->getPort(ID::Y).as_bit(); + auto y_port = cell->getPort(TW::Y).as_bit(); if (y_port.wire->width == 1) module->rename(cell, stringf("$lut%s", y_port.wire->name)); else diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index e8547f963..123d38e23 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -62,10 +62,10 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width cell->parameters[ID::A_SIGNED] = RTLIL::Const(that->children[0]->is_signed); cell->parameters[ID::A_WIDTH] = RTLIL::Const(arg.size()); - cell->setPort(ID::A, arg); + cell->setPort(TW::A, arg); cell->parameters[ID::Y_WIDTH] = result_width; - cell->setPort(ID::Y, wire); + cell->setPort(TW::Y, wire); return wire; } @@ -94,10 +94,10 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s cell->parameters[ID::A_SIGNED] = RTLIL::Const(is_signed); cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig.size()); - cell->setPort(ID::A, sig); + cell->setPort(TW::A, sig); cell->parameters[ID::Y_WIDTH] = width; - cell->setPort(ID::Y, wire); + cell->setPort(TW::Y, wire); sig = wire; } @@ -124,11 +124,11 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width cell->parameters[ID::A_WIDTH] = RTLIL::Const(left.size()); cell->parameters[ID::B_WIDTH] = RTLIL::Const(right.size()); - cell->setPort(ID::A, left); - cell->setPort(ID::B, right); + cell->setPort(TW::A, left); + cell->setPort(TW::B, right); cell->parameters[ID::Y_WIDTH] = result_width; - cell->setPort(ID::Y, wire); + cell->setPort(TW::Y, wire); return wire; } @@ -155,10 +155,10 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const cell->parameters[ID::WIDTH] = RTLIL::Const(left.size()); - cell->setPort(ID::A, right); - cell->setPort(ID::B, left); - cell->setPort(ID::S, cond); - cell->setPort(ID::Y, wire); + cell->setPort(TW::A, right); + cell->setPort(TW::B, left); + cell->setPort(TW::S, cond); + cell->setPort(TW::Y, wire); return wire; } @@ -842,8 +842,8 @@ struct AST_INTERNAL::ProcessGenerator cell->setParam(ID::TRG_ENABLE, (always->type == AST_INITIAL) || !triggers.empty()); cell->setParam(ID::TRG_POLARITY, polarity); cell->setParam(ID::PRIORITY, --last_effect_priority); - cell->setPort(ID::TRG, triggers); - cell->setPort(ID::EN, en); + cell->setPort(TW::TRG, triggers); + cell->setPort(TW::EN, en); int default_base = 10; if (ast->str.back() == 'b') @@ -947,9 +947,9 @@ struct AST_INTERNAL::ProcessGenerator cell->setParam(ID::TRG_ENABLE, (always->type == AST_INITIAL) || !triggers.empty()); cell->setParam(ID::TRG_POLARITY, polarity); cell->setParam(ID::PRIORITY, --last_effect_priority); - cell->setPort(ID::TRG, triggers); - cell->setPort(ID::EN, en); - cell->setPort(ID::A, check); + cell->setPort(TW::TRG, triggers); + cell->setPort(TW::EN, en); + cell->setPort(TW::A, check); // No message is emitted to ensure Verilog code roundtrips correctly. Fmt fmt; @@ -2058,10 +2058,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::SigSpec addr_sig = children[0]->genRTLIL(); - cell->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::Sx, 1)); - cell->setPort(ID::EN, RTLIL::SigSpec(RTLIL::State::Sx, 1)); - cell->setPort(ID::ADDR, addr_sig); - cell->setPort(ID::DATA, RTLIL::SigSpec(wire)); + cell->setPort(TW::CLK, RTLIL::SigSpec(RTLIL::State::Sx, 1)); + cell->setPort(TW::EN, RTLIL::SigSpec(RTLIL::State::Sx, 1)); + cell->setPort(TW::ADDR, addr_sig); + cell->setPort(TW::DATA, RTLIL::SigSpec(wire)); cell->parameters[ID::MEMID] = RTLIL::Const(str); cell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr_sig)); @@ -2098,9 +2098,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) SigSpec addr_sig = children[0]->genRTLIL(); - cell->setPort(ID::ADDR, addr_sig); - cell->setPort(ID::DATA, children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words, true)); - cell->setPort(ID::EN, en_sig); + cell->setPort(TW::ADDR, addr_sig); + cell->setPort(TW::DATA, children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words, true)); + cell->setPort(TW::EN, en_sig); cell->parameters[ID::MEMID] = RTLIL::Const(str); cell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr_sig)); @@ -2147,9 +2147,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) cell->parameters[ID::TRG_ENABLE] = 0; cell->parameters[ID::TRG_POLARITY] = 0; cell->parameters[ID::PRIORITY] = 0; - cell->setPort(ID::TRG, RTLIL::SigSpec()); - cell->setPort(ID::EN, RTLIL::S1); - cell->setPort(ID::A, check); + cell->setPort(TW::TRG, RTLIL::SigSpec()); + cell->setPort(TW::EN, RTLIL::S1); + cell->setPort(TW::A, check); // No message is emitted to ensure Verilog code roundtrips correctly. Fmt fmt; @@ -2262,8 +2262,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) cell->attributes[attr.first] = attr.second->asAttrConst(); } if (cell->type == ID($specify2)) { - int src_width = GetSize(cell->getPort(ID::SRC)); - int dst_width = GetSize(cell->getPort(ID::DST)); + int src_width = GetSize(cell->getPort(TW::SRC)); + int dst_width = GetSize(cell->getPort(TW::DST)); bool full = cell->getParam(ID::FULL).as_bool(); if (!full && src_width != dst_width) input_error("Parallel specify SRC width does not match DST width.\n"); @@ -2271,17 +2271,17 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) cell->setParam(ID::DST_WIDTH, Const(dst_width)); } else if (cell->type == ID($specify3)) { - int dat_width = GetSize(cell->getPort(ID::DAT)); - int dst_width = GetSize(cell->getPort(ID::DST)); + int dat_width = GetSize(cell->getPort(TW::DAT)); + int dst_width = GetSize(cell->getPort(TW::DST)); if (dat_width != dst_width) input_error("Specify DAT width does not match DST width.\n"); - int src_width = GetSize(cell->getPort(ID::SRC)); + int src_width = GetSize(cell->getPort(TW::SRC)); cell->setParam(ID::SRC_WIDTH, Const(src_width)); cell->setParam(ID::DST_WIDTH, Const(dst_width)); } else if (cell->type == ID($specrule)) { - int src_width = GetSize(cell->getPort(ID::SRC)); - int dst_width = GetSize(cell->getPort(ID::DST)); + int src_width = GetSize(cell->getPort(TW::SRC)); + int dst_width = GetSize(cell->getPort(TW::DST)); cell->setParam(ID::SRC_WIDTH, Const(src_width)); cell->setParam(ID::DST_WIDTH, Const(dst_width)); } @@ -2370,7 +2370,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) Wire *wire = current_module->addWire(myid + "_wire", width); set_src_attr(wire, this); - cell->setPort(ID::Y, wire); + cell->setPort(TW::Y, wire); is_signed = sign_hint; return SigSpec(wire); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 95dca27d8..806c49b97 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1479,7 +1479,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin continue; // determine the full name of port this argument is connected to - RTLIL::IdString port_name; + TwineRef port_name; if (child->str.size()) port_name = child->str; else { diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index 6b67bb99c..710c7ef21 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -226,7 +226,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool for (auto cell : module->cells()) if (cell->type == ID($lut) && cell->getParam(ID::LUT) == buffer_lut) { - module->connect(cell->getPort(ID::Y), cell->getPort(ID::A)); + module->connect(cell->getPort(TW::Y), cell->getPort(TW::A)); remove_cells.push_back(cell); } @@ -376,9 +376,9 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool if (dff_name.empty()) { cell = module->addFfGate(NEW_ID, blif_wire(d), blif_wire(q)); } else { - cell = module->addCell(NEW_ID, dff_name); - cell->setPort(ID::D, blif_wire(d)); - cell->setPort(ID::Q, blif_wire(q)); + cell = module->addCell(NEW_TWINE, dff_name); + cell->setPort(TW::D, blif_wire(d)); + cell->setPort(TW::Q, blif_wire(q)); } } @@ -395,7 +395,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool goto error; IdString celltype = RTLIL::escape_id(p); - RTLIL::Cell *cell = module->addCell(NEW_ID, celltype); + RTLIL::Cell *cell = module->addCell(NEW_TWINE, celltype); RTLIL::Module *cell_mod = design->module(celltype); dict> cell_wideports_cache; @@ -442,7 +442,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool if (it.second.count(idx)) sig.append(it.second.at(idx)); else - sig.append(module->addWire(NEW_ID)); + sig.append(module->addWire(NEW_TWINE)); } cell->setPort(it.first, sig); @@ -539,12 +539,12 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool if (sop_mode) { - sopcell = module->addCell(NEW_ID, ID($sop)); + sopcell = module->addCell(NEW_TWINE, ID($sop)); sopcell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size()); sopcell->parameters[ID::DEPTH] = 0; sopcell->parameters[ID::TABLE] = RTLIL::Const(); - sopcell->setPort(ID::A, input_sig); - sopcell->setPort(ID::Y, output_sig); + sopcell->setPort(TW::A, input_sig); + sopcell->setPort(TW::Y, output_sig); sopmode = -1; lastcell = sopcell; } @@ -555,11 +555,11 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool } else { - RTLIL::Cell *cell = module->addCell(NEW_ID, ID($lut)); + RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($lut)); cell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size()); cell->parameters[ID::LUT] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size()); - cell->setPort(ID::A, input_sig); - cell->setPort(ID::Y, output_sig); + cell->setPort(TW::A, input_sig); + cell->setPort(TW::Y, output_sig); lutptr = &cell->parameters.at(ID::LUT); lut_default_state = RTLIL::State::Sx; lastcell = cell; @@ -607,10 +607,10 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool if (sopmode == -1) { sopmode = (*output == '1'); if (!sopmode) { - SigSpec outnet = sopcell->getPort(ID::Y); - SigSpec tempnet = module->addWire(NEW_ID); + SigSpec outnet = sopcell->getPort(TW::Y); + SigSpec tempnet = module->addWire(NEW_TWINE); module->addNotGate(NEW_ID, tempnet, outnet); - sopcell->setPort(ID::Y, tempnet); + sopcell->setPort(TW::Y, tempnet); } } else log_assert(sopmode == (*output == '1')); diff --git a/frontends/json/jsonparse.cc b/frontends/json/jsonparse.cc index c5ba389ad..4fbcfa5a5 100644 --- a/frontends/json/jsonparse.cc +++ b/frontends/json/jsonparse.cc @@ -572,7 +572,7 @@ void json_import(Design *design, string &modname, JsonNode *node) if (bitval_node->type == 'N') { int bitidx = bitval_node->data_number; if (signal_bits.count(bitidx) == 0) - signal_bits[bitidx] = module->addWire(NEW_ID); + signal_bits[bitidx] = module->addWire(NEW_TWINE); sig.append(signal_bits.at(bitidx)); } else log_error("JSON cells node '%s' connection '%s' has invalid bit value on bit %d.\n", diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index c5f9ca274..f21f1d3a7 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -185,12 +185,12 @@ static RTLIL::SigSpec create_tristate(RTLIL::Module *module, RTLIL::SigSpec func { RTLIL::SigSpec three_state = parse_func_expr(module, three_state_expr); - RTLIL::Cell *cell = module->addCell(NEW_ID, ID($tribuf)); + RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($tribuf)); cell->setParam(ID::WIDTH, GetSize(func)); - cell->setPort(ID::A, func); - cell->setPort(ID::EN, module->NotGate(NEW_ID, three_state)); - cell->setPort(ID::Y, module->addWire(NEW_ID)); - return cell->getPort(ID::Y); + cell->setPort(TW::A, func); + cell->setPort(TW::EN, module->NotGate(NEW_ID, three_state)); + cell->setPort(TW::Y, module->addWire(NEW_TWINE)); + return cell->getPort(TW::Y); } static void create_latch_ff_wires(RTLIL::Module *module, const LibertyAst *node) @@ -243,18 +243,18 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node) rerun_invert_rollback = false; for (auto &it : module->cells_) { - if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clk_sig) { - clk_sig = it.second->getPort(ID::A); + if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == clk_sig) { + clk_sig = it.second->getPort(TW::A); clk_polarity = !clk_polarity; rerun_invert_rollback = true; } - if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clear_sig) { - clear_sig = it.second->getPort(ID::A); + if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == clear_sig) { + clear_sig = it.second->getPort(TW::A); clear_polarity = !clear_polarity; rerun_invert_rollback = true; } - if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == preset_sig) { - preset_sig = it.second->getPort(ID::A); + if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == preset_sig) { + preset_sig = it.second->getPort(TW::A); preset_polarity = !preset_polarity; rerun_invert_rollback = true; } @@ -264,14 +264,14 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node) for (auto& [out_sig, cp_var, neg] : {tuple{iq_sig, clear_preset_var1, false}, {iqn_sig, clear_preset_var2, true}}) { SigSpec q_sig = out_sig; if (neg) { - q_sig = module->addWire(NEW_ID, out_sig.as_wire()); + q_sig = module->addWire(NEW_TWINE, out_sig.as_wire()); module->addNotGate(NEW_ID, q_sig, out_sig); } - RTLIL::Cell* cell = module->addCell(NEW_ID, ""); - cell->setPort(ID::D, data_sig); - cell->setPort(ID::Q, q_sig); - cell->setPort(ID::C, clk_sig); + RTLIL::Cell* cell = module->addCell(NEW_TWINE, ""); + cell->setPort(TW::D, data_sig); + cell->setPort(TW::Q, q_sig); + cell->setPort(TW::C, clk_sig); if (clear_sig.size() == 0 && preset_sig.size() == 0) { cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'); @@ -279,12 +279,12 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node) if (clear_sig.size() == 1 && preset_sig.size() == 0) { cell->type = stringf("$_DFF_%c%c0_", clk_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N'); - cell->setPort(ID::R, clear_sig); + cell->setPort(TW::R, clear_sig); } if (clear_sig.size() == 0 && preset_sig.size() == 1) { cell->type = stringf("$_DFF_%c%c1_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N'); - cell->setPort(ID::R, preset_sig); + cell->setPort(TW::R, preset_sig); } if (clear_sig.size() == 1 && preset_sig.size() == 1) { @@ -313,8 +313,8 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node) log_debug("cell %s variable %d undef c&p behavior\n", name, (int)neg + 1); } - cell->setPort(ID::S, s_sig); - cell->setPort(ID::R, r_sig); + cell->setPort(TW::S, s_sig); + cell->setPort(TW::R, r_sig); } log_assert(!cell->type.empty()); @@ -352,27 +352,27 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla rerun_invert_rollback = false; for (auto &it : module->cells_) { - if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == enable_sig) { - enable_sig = it.second->getPort(ID::A); + if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == enable_sig) { + enable_sig = it.second->getPort(TW::A); enable_polarity = !enable_polarity; rerun_invert_rollback = true; } - if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clear_sig) { - clear_sig = it.second->getPort(ID::A); + if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == clear_sig) { + clear_sig = it.second->getPort(TW::A); clear_polarity = !clear_polarity; rerun_invert_rollback = true; } - if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == preset_sig) { - preset_sig = it.second->getPort(ID::A); + if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == preset_sig) { + preset_sig = it.second->getPort(TW::A); preset_polarity = !preset_polarity; rerun_invert_rollback = true; } } } - RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_)); - cell->setPort(ID::A, iq_sig); - cell->setPort(ID::Y, iqn_sig); + RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($_NOT_)); + cell->setPort(TW::A, iq_sig); + cell->setPort(TW::Y, iqn_sig); if (clear_sig.size() == 1) { @@ -381,25 +381,25 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla if (clear_polarity == true || clear_polarity != enable_polarity) { - RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_)); - inv->setPort(ID::A, clear_sig); - inv->setPort(ID::Y, module->addWire(NEW_ID)); + RTLIL::Cell *inv = module->addCell(NEW_TWINE, ID($_NOT_)); + inv->setPort(TW::A, clear_sig); + inv->setPort(TW::Y, module->addWire(NEW_TWINE)); if (clear_polarity == true) - clear_negative = inv->getPort(ID::Y); + clear_negative = inv->getPort(TW::Y); if (clear_polarity != enable_polarity) - clear_enable = inv->getPort(ID::Y); + clear_enable = inv->getPort(TW::Y); } - RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_AND_)); - data_gate->setPort(ID::A, data_sig); - data_gate->setPort(ID::B, clear_negative); - data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID)); + RTLIL::Cell *data_gate = module->addCell(NEW_TWINE, ID($_AND_)); + data_gate->setPort(TW::A, data_sig); + data_gate->setPort(TW::B, clear_negative); + data_gate->setPort(TW::Y, data_sig = module->addWire(NEW_TWINE)); - RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_)); - enable_gate->setPort(ID::A, enable_sig); - enable_gate->setPort(ID::B, clear_enable); - enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEW_ID)); + RTLIL::Cell *enable_gate = module->addCell(NEW_TWINE, enable_polarity ? ID($_OR_) : ID($_AND_)); + enable_gate->setPort(TW::A, enable_sig); + enable_gate->setPort(TW::B, clear_enable); + enable_gate->setPort(TW::Y, enable_sig = module->addWire(NEW_TWINE)); } if (preset_sig.size() == 1) @@ -409,31 +409,31 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla if (preset_polarity == false || preset_polarity != enable_polarity) { - RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_)); - inv->setPort(ID::A, preset_sig); - inv->setPort(ID::Y, module->addWire(NEW_ID)); + RTLIL::Cell *inv = module->addCell(NEW_TWINE, ID($_NOT_)); + inv->setPort(TW::A, preset_sig); + inv->setPort(TW::Y, module->addWire(NEW_TWINE)); if (preset_polarity == false) - preset_positive = inv->getPort(ID::Y); + preset_positive = inv->getPort(TW::Y); if (preset_polarity != enable_polarity) - preset_enable = inv->getPort(ID::Y); + preset_enable = inv->getPort(TW::Y); } - RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_OR_)); - data_gate->setPort(ID::A, data_sig); - data_gate->setPort(ID::B, preset_positive); - data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID)); + RTLIL::Cell *data_gate = module->addCell(NEW_TWINE, ID($_OR_)); + data_gate->setPort(TW::A, data_sig); + data_gate->setPort(TW::B, preset_positive); + data_gate->setPort(TW::Y, data_sig = module->addWire(NEW_TWINE)); - RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_)); - enable_gate->setPort(ID::A, enable_sig); - enable_gate->setPort(ID::B, preset_enable); - enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEW_ID)); + RTLIL::Cell *enable_gate = module->addCell(NEW_TWINE, enable_polarity ? ID($_OR_) : ID($_AND_)); + enable_gate->setPort(TW::A, enable_sig); + enable_gate->setPort(TW::B, preset_enable); + enable_gate->setPort(TW::Y, enable_sig = module->addWire(NEW_TWINE)); } - cell = module->addCell(NEW_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N')); - cell->setPort(ID::D, data_sig); - cell->setPort(ID::Q, iq_sig); - cell->setPort(ID::E, enable_sig); + cell = module->addCell(NEW_TWINE, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N')); + cell->setPort(TW::D, data_sig); + cell->setPort(TW::Q, iq_sig); + cell->setPort(TW::E, enable_sig); return true; } @@ -793,7 +793,7 @@ struct LibertyFrontend : public Frontend { if (wi->port_input) { for (auto wo : module->wires()) if (wo->port_output) { - RTLIL::Cell *spec = module->addCell(NEW_ID, ID($specify2)); + RTLIL::Cell *spec = module->addCell(NEW_TWINE, ID($specify2)); spec->setParam(ID::SRC_WIDTH, wi->width); spec->setParam(ID::DST_WIDTH, wo->width); spec->setParam(ID::T_FALL_MAX, 1000); @@ -805,9 +805,9 @@ struct LibertyFrontend : public Frontend { spec->setParam(ID::SRC_DST_POL, false); spec->setParam(ID::SRC_DST_PEN, false); spec->setParam(ID::FULL, true); - spec->setPort(ID::EN, Const(1, 1)); - spec->setPort(ID::SRC, wi); - spec->setPort(ID::DST, wo); + spec->setPort(TW::EN, Const(1, 1)); + spec->setPort(TW::SRC, wi); + spec->setPort(TW::DST, wo); } } } diff --git a/frontends/rtlil/rtlil_frontend.cc b/frontends/rtlil/rtlil_frontend.cc index faf5a20bb..1610d721d 100644 --- a/frontends/rtlil/rtlil_frontend.cc +++ b/frontends/rtlil/rtlil_frontend.cc @@ -445,7 +445,7 @@ struct RTLILFrontendWorker { current_module = new RTLIL::Module; current_module->design = design; - current_module->meta_->name_id = module_name; + current_module->meta_->name = module_name; if (delete_current_module) { // Module is about to be discarded — drop its src attribute // rather than push it into a pool we'll never reach. @@ -706,7 +706,7 @@ struct RTLILFrontendWorker { expect_eol(); } - void legalize_width_parameter(RTLIL::Cell *cell, RTLIL::IdString port_name) + void legalize_width_parameter(RTLIL::Cell *cell, TwineRef port_name) { std::string width_param_name = port_name.str() + "_WIDTH"; if (cell->parameters.count(width_param_name) == 0) @@ -763,7 +763,7 @@ struct RTLILFrontendWorker { cell->parameters.insert({std::move(param_name), std::move(val)}); expect_eol(); } else if (try_parse_keyword("connect")) { - RTLIL::IdString port_name = parse_id(); + TwineRef port_name = parse_id(); if (cell->hasPort(port_name)) { if (flag_legalize) log("Legalizing redefinition of cell port %s.", port_name); diff --git a/guidelines/GettingStarted b/guidelines/GettingStarted index ea15df93f..6c663ff3f 100644 --- a/guidelines/GettingStarted +++ b/guidelines/GettingStarted @@ -98,8 +98,8 @@ single signal bit can have multiple valid names. The SigMap object can be used to map SigSpecs or SigBits to unique SigSpecs and SigBits that consistently only use one wire from such a group of connected wires. For example: - SigBit a = module->addWire(NEW_ID); - SigBit b = module->addWire(NEW_ID); + SigBit a = module->addWire(NEW_TWINE); + SigBit b = module->addWire(NEW_TWINE); module->connect(a, b); log("%d\n", a == b); // will print 0 diff --git a/kernel/cellaigs.cc b/kernel/cellaigs.cc index ce351514b..3d6b9a184 100644 --- a/kernel/cellaigs.cc +++ b/kernel/cellaigs.cc @@ -91,7 +91,7 @@ struct AigMaker return node2index(node); } - int inport(IdString portname, int portbit = 0, bool inverter = false) + int inport(TwineRef portname, int portbit = 0, bool inverter = false) { if (portbit >= GetSize(cell->getPort(portname))) { if (cell->parameters.count(portname.str() + "_SIGNED") && cell->getParam(portname.str() + "_SIGNED").as_bool()) @@ -106,7 +106,7 @@ struct AigMaker return node2index(node); } - vector inport_vec(IdString portname, int width) + vector inport_vec(TwineRef portname, int width) { vector vec; for (int i = 0; i < width; i++) @@ -114,7 +114,7 @@ struct AigMaker return vec; } - int not_inport(IdString portname, int portbit = 0) + int not_inport(TwineRef portname, int portbit = 0) { return inport(portname, portbit, true); } @@ -244,20 +244,20 @@ struct AigMaker return Y; } - void outport(int node, IdString portname, int portbit = 0) + void outport(int node, TwineRef portname, int portbit = 0) { if (portbit < GetSize(cell->getPort(portname))) aig->nodes.at(node).outports.push_back(pair(portname, portbit)); } - void outport_bool(int node, IdString portname) + void outport_bool(int node, TwineRef portname) { outport(node, portname); for (int i = 1; i < GetSize(cell->getPort(portname)); i++) outport(bool_node(false), portname, i); } - void outport_vec(const vector &vec, IdString portname) + void outport_vec(const vector &vec, TwineRef portname) { for (int i = 0; i < GetSize(vec); i++) outport(vec.at(i), portname, i); @@ -304,7 +304,7 @@ Aig::Aig(Cell *cell) if (cell->type.in(ID($not), ID($_NOT_), ID($pos), ID($buf), ID($_BUF_))) { - for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) { + for (int i = 0; i < GetSize(cell->getPort(TW::Y)); i++) { int A = mk.inport(ID::A, i); int Y = cell->type.in(ID($not), ID($_NOT_)) ? mk.not_gate(A) : A; mk.outport(Y, ID::Y, i); @@ -314,7 +314,7 @@ Aig::Aig(Cell *cell) if (cell->type.in(ID($and), ID($_AND_), ID($_NAND_), ID($or), ID($_OR_), ID($_NOR_), ID($xor), ID($xnor), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_))) { - for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) { + for (int i = 0; i < GetSize(cell->getPort(TW::Y)); i++) { int A = mk.inport(ID::A, i); int B = mk.inport(ID::B, i); int Y = cell->type.in(ID($and), ID($_AND_)) ? mk.and_gate(A, B) : @@ -333,7 +333,7 @@ Aig::Aig(Cell *cell) if (cell->type.in(ID($mux), ID($_MUX_), ID($_NMUX_))) { int S = mk.inport(ID::S); - for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) { + for (int i = 0; i < GetSize(cell->getPort(TW::Y)); i++) { int A = mk.inport(ID::A, i); int B = mk.inport(ID::B, i); int Y = mk.mux_gate(A, B, S); @@ -347,7 +347,7 @@ Aig::Aig(Cell *cell) if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) { int Y = mk.inport(ID::A, 0); - for (int i = 1; i < GetSize(cell->getPort(ID::A)); i++) { + for (int i = 1; i < GetSize(cell->getPort(TW::A)); i++) { int A = mk.inport(ID::A, i); if (cell->type == ID($reduce_and)) Y = mk.and_gate(A, Y); if (cell->type == ID($reduce_or)) Y = mk.or_gate(A, Y); @@ -358,7 +358,7 @@ Aig::Aig(Cell *cell) if (cell->type == ID($reduce_xnor)) Y = mk.not_gate(Y); mk.outport(Y, ID::Y, 0); - for (int i = 1; i < GetSize(cell->getPort(ID::Y)); i++) + for (int i = 1; i < GetSize(cell->getPort(TW::Y)); i++) mk.outport(mk.bool_node(false), ID::Y, i); goto optimize; } @@ -366,11 +366,11 @@ Aig::Aig(Cell *cell) if (cell->type.in(ID($logic_not), ID($logic_and), ID($logic_or))) { int A = mk.inport(ID::A, 0), Y = -1; - for (int i = 1; i < GetSize(cell->getPort(ID::A)); i++) + for (int i = 1; i < GetSize(cell->getPort(TW::A)); i++) A = mk.or_gate(mk.inport(ID::A, i), A); if (cell->type.in(ID($logic_and), ID($logic_or))) { int B = mk.inport(ID::B, 0); - for (int i = 1; i < GetSize(cell->getPort(ID::B)); i++) + for (int i = 1; i < GetSize(cell->getPort(TW::B)); i++) B = mk.or_gate(mk.inport(ID::B, i), B); if (cell->type == ID($logic_and)) Y = mk.and_gate(A, B); if (cell->type == ID($logic_or)) Y = mk.or_gate(A, B); @@ -383,7 +383,7 @@ Aig::Aig(Cell *cell) if (cell->type.in(ID($add), ID($sub))) { - int width = GetSize(cell->getPort(ID::Y)); + int width = GetSize(cell->getPort(TW::Y)); vector A = mk.inport_vec(ID::A, width); vector B = mk.inport_vec(ID::B, width); int carry = mk.bool_node(false); @@ -399,8 +399,8 @@ Aig::Aig(Cell *cell) if (cell->type.in(ID($lt), ID($gt), ID($le), ID($ge))) { - int width = std::max(GetSize(cell->getPort(ID::A)), - GetSize(cell->getPort(ID::B))) + 1; + int width = std::max(GetSize(cell->getPort(TW::A)), + GetSize(cell->getPort(TW::B))) + 1; vector A = mk.inport_vec(ID::A, width); vector B = mk.inport_vec(ID::B, width); @@ -412,14 +412,14 @@ Aig::Aig(Cell *cell) n = mk.not_gate(n); vector Y = mk.adder(A, B, carry); mk.outport(Y.back(), ID::Y); - for (int i = 1; i < GetSize(cell->getPort(ID::Y)); i++) + for (int i = 1; i < GetSize(cell->getPort(TW::Y)); i++) mk.outport(mk.bool_node(false), ID::Y, i); goto optimize; } if (cell->type == ID($alu)) { - int width = GetSize(cell->getPort(ID::Y)); + int width = GetSize(cell->getPort(TW::Y)); vector A = mk.inport_vec(ID::A, width); vector B = mk.inport_vec(ID::B, width); int carry = mk.inport(ID::CI); @@ -438,7 +438,7 @@ Aig::Aig(Cell *cell) if (cell->type.in(ID($eq), ID($ne))) { - int width = max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::B))); + int width = max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::B))); vector A = mk.inport_vec(ID::A, width); vector B = mk.inport_vec(ID::B, width); int Y = mk.bool_node(false); diff --git a/kernel/cellaigs.h b/kernel/cellaigs.h index f6afcde5e..d2ab20073 100644 --- a/kernel/cellaigs.h +++ b/kernel/cellaigs.h @@ -26,7 +26,7 @@ YOSYS_NAMESPACE_BEGIN struct AigNode { - IdString portname; + TwineRef portname; int portbit; bool inverter; int left_parent, right_parent; diff --git a/kernel/celledges.cc b/kernel/celledges.cc index 195d4b15b..0f7f0b0e6 100644 --- a/kernel/celledges.cc +++ b/kernel/celledges.cc @@ -25,8 +25,8 @@ PRIVATE_NAMESPACE_BEGIN void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { bool is_signed = (cell->type != ID($buf)) && cell->getParam(ID::A_SIGNED).as_bool(); - int a_width = GetSize(cell->getPort(ID::A)); - int y_width = GetSize(cell->getPort(ID::Y)); + int a_width = GetSize(cell->getPort(TW::A)); + int y_width = GetSize(cell->getPort(TW::Y)); for (int i = 0; i < y_width; i++) { @@ -40,9 +40,9 @@ void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); - int a_width = GetSize(cell->getPort(ID::A)); - int b_width = GetSize(cell->getPort(ID::B)); - int y_width = GetSize(cell->getPort(ID::Y)); + int a_width = GetSize(cell->getPort(TW::A)); + int b_width = GetSize(cell->getPort(TW::B)); + int y_width = GetSize(cell->getPort(TW::Y)); if (cell->type == ID($and) && !is_signed) { if (a_width > b_width) @@ -68,8 +68,8 @@ void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void arith_neg_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); - int a_width = GetSize(cell->getPort(ID::A)); - int y_width = GetSize(cell->getPort(ID::Y)); + int a_width = GetSize(cell->getPort(TW::A)); + int y_width = GetSize(cell->getPort(TW::Y)); if (is_signed && a_width == 1) y_width = std::min(y_width, 1); @@ -82,9 +82,9 @@ void arith_neg_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); - int a_width = GetSize(cell->getPort(ID::A)); - int b_width = GetSize(cell->getPort(ID::B)); - int y_width = GetSize(cell->getPort(ID::Y)); + int a_width = GetSize(cell->getPort(TW::A)); + int b_width = GetSize(cell->getPort(TW::B)); + int y_width = GetSize(cell->getPort(TW::Y)); if (!is_signed && cell->type != ID($sub)) { int ab_width = std::max(a_width, b_width); @@ -106,7 +106,7 @@ void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - int a_width = GetSize(cell->getPort(ID::A)); + int a_width = GetSize(cell->getPort(TW::A)); for (int i = 0; i < a_width; i++) db->add_edge(cell, ID::A, i, ID::Y, 0, -1); @@ -114,8 +114,8 @@ void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void logic_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - int a_width = GetSize(cell->getPort(ID::A)); - int b_width = GetSize(cell->getPort(ID::B)); + int a_width = GetSize(cell->getPort(TW::A)); + int b_width = GetSize(cell->getPort(TW::B)); for (int i = 0; i < a_width; i++) db->add_edge(cell, ID::A, i, ID::Y, 0, -1); @@ -125,8 +125,8 @@ void logic_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void concat_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - int a_width = GetSize(cell->getPort(ID::A)); - int b_width = GetSize(cell->getPort(ID::B)); + int a_width = GetSize(cell->getPort(TW::A)); + int b_width = GetSize(cell->getPort(TW::B)); for (int i = 0; i < a_width; i++) db->add_edge(cell, ID::A, i, ID::Y, i, -1); @@ -137,8 +137,8 @@ void concat_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void slice_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { int offset = cell->getParam(ID::OFFSET).as_int(); - int a_width = GetSize(cell->getPort(ID::A)); - int y_width = GetSize(cell->getPort(ID::Y)); + int a_width = GetSize(cell->getPort(TW::A)); + int y_width = GetSize(cell->getPort(TW::Y)); for (int i = 0; i < y_width; i++) { int a_bit = offset + i; @@ -149,8 +149,8 @@ void slice_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - int a_width = GetSize(cell->getPort(ID::A)); - int b_width = GetSize(cell->getPort(ID::B)); + int a_width = GetSize(cell->getPort(TW::A)); + int b_width = GetSize(cell->getPort(TW::B)); for (int i = 0; i < a_width; i++) db->add_edge(cell, ID::A, i, ID::Y, 0, -1); @@ -161,9 +161,9 @@ void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - int a_width = GetSize(cell->getPort(ID::A)); - int b_width = GetSize(cell->getPort(ID::B)); - int s_width = GetSize(cell->getPort(ID::S)); + int a_width = GetSize(cell->getPort(TW::A)); + int b_width = GetSize(cell->getPort(TW::B)); + int s_width = GetSize(cell->getPort(TW::S)); for (int i = 0; i < a_width; i++) { @@ -179,9 +179,9 @@ void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void bmux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - int width = GetSize(cell->getPort(ID::Y)); - int a_width = GetSize(cell->getPort(ID::A)); - int s_width = GetSize(cell->getPort(ID::S)); + int width = GetSize(cell->getPort(TW::Y)); + int a_width = GetSize(cell->getPort(TW::A)); + int s_width = GetSize(cell->getPort(TW::S)); for (int i = 0; i < width; i++) { @@ -195,9 +195,9 @@ void bmux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void demux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - int width = GetSize(cell->getPort(ID::Y)); - int a_width = GetSize(cell->getPort(ID::A)); - int s_width = GetSize(cell->getPort(ID::S)); + int width = GetSize(cell->getPort(TW::Y)); + int a_width = GetSize(cell->getPort(TW::A)); + int s_width = GetSize(cell->getPort(TW::S)); for (int i = 0; i < width; i++) { @@ -211,9 +211,9 @@ void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); bool is_b_signed = cell->getParam(ID::B_SIGNED).as_bool(); - int a_width = GetSize(cell->getPort(ID::A)); - int b_width = GetSize(cell->getPort(ID::B)); - int y_width = GetSize(cell->getPort(ID::Y)); + int a_width = GetSize(cell->getPort(TW::A)); + int b_width = GetSize(cell->getPort(TW::B)); + int y_width = GetSize(cell->getPort(TW::Y)); // Behavior of the different shift cells: // @@ -397,7 +397,7 @@ void mem_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void ff_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - int width = cell->getPort(ID::Q).size(); + int width = cell->getPort(TW::Q).size(); if (cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr))) { for (int k = 0; k < width; k++) { @@ -430,7 +430,7 @@ void full_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) for (auto &conn : cell->connections()) { - RTLIL::IdString port = conn.first; + TwineRef port = conn.first; RTLIL::PortDir dir = cell->port_dir(port); if (cell->input(port) || dir == RTLIL::PortDir::PD_INOUT) input_ports.push_back(port); @@ -455,9 +455,9 @@ void full_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void bweqx_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - int width = GetSize(cell->getPort(ID::Y)); - int a_width = GetSize(cell->getPort(ID::A)); - int b_width = GetSize(cell->getPort(ID::B)); + int width = GetSize(cell->getPort(TW::Y)); + int a_width = GetSize(cell->getPort(TW::A)); + int b_width = GetSize(cell->getPort(TW::B)); int max_width = std::min(width, std::min(a_width, b_width)); for (int i = 0; i < max_width; i++) { @@ -468,10 +468,10 @@ void bweqx_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void bwmux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - int width = GetSize(cell->getPort(ID::Y)); - int a_width = GetSize(cell->getPort(ID::A)); - int b_width = GetSize(cell->getPort(ID::B)); - int s_width = GetSize(cell->getPort(ID::S)); + int width = GetSize(cell->getPort(TW::Y)); + int a_width = GetSize(cell->getPort(TW::A)); + int b_width = GetSize(cell->getPort(TW::B)); + int s_width = GetSize(cell->getPort(TW::S)); int max_width = std::min(width, std::min(a_width, std::min(b_width, s_width))); for (int i = 0; i < max_width; i++) { diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 32cfb727a..77b6857da 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -28,7 +28,7 @@ YOSYS_NAMESPACE_BEGIN struct CellType { RTLIL::IdString type; - pool inputs, outputs; + pool inputs, outputs; bool is_evaluable; bool is_combinatorial; bool is_synthesizable; @@ -59,7 +59,7 @@ struct CellTypes setup_stdcells_mem(); } - void setup_type(RTLIL::IdString type, const pool &inputs, const pool &outputs, bool is_evaluable = false, bool is_combinatorial = false, bool is_synthesizable = false) + void setup_type(RTLIL::IdString type, const pool &inputs, const pool &outputs, bool is_evaluable = false, bool is_combinatorial = false, bool is_synthesizable = false) { CellType ct = {type, inputs, outputs, is_evaluable, is_combinatorial, is_synthesizable}; cell_types[ct.type] = ct; @@ -67,13 +67,13 @@ struct CellTypes void setup_module(RTLIL::Module *module) { - pool inputs, outputs; + pool inputs, outputs; for (auto wire_name : module->ports) { RTLIL::Wire *wire = module->wire(wire_name); if (wire->port_input) - inputs.insert(wire->name); + inputs.insert(wire->meta_->name); if (wire->port_output) - outputs.insert(wire->name); + outputs.insert(wire->meta_->name); } setup_type(module->name, inputs, outputs); } @@ -88,34 +88,34 @@ struct CellTypes { setup_internals_eval(); - setup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y}); + setup_type(ID($tribuf), {TW::A, TW::EN}, {TW::Y}); - setup_type(ID($assert), {ID::A, ID::EN}, pool()); - setup_type(ID($assume), {ID::A, ID::EN}, pool()); - setup_type(ID($live), {ID::A, ID::EN}, pool()); - setup_type(ID($fair), {ID::A, ID::EN}, pool()); - setup_type(ID($cover), {ID::A, ID::EN}, pool()); - setup_type(ID($initstate), pool(), {ID::Y}); - setup_type(ID($anyconst), pool(), {ID::Y}); - setup_type(ID($anyseq), pool(), {ID::Y}); - setup_type(ID($allconst), pool(), {ID::Y}); - setup_type(ID($allseq), pool(), {ID::Y}); - setup_type(ID($equiv), {ID::A, ID::B}, {ID::Y}); - setup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool()); - setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool()); - setup_type(ID($specrule), {ID::SRC_EN, ID::DST_EN, ID::SRC, ID::DST}, pool()); - setup_type(ID($print), {ID::EN, ID::ARGS, ID::TRG}, pool()); - setup_type(ID($check), {ID::A, ID::EN, ID::ARGS, ID::TRG}, pool()); - setup_type(ID($set_tag), {ID::A, ID::SET, ID::CLR}, {ID::Y}); - setup_type(ID($get_tag), {ID::A}, {ID::Y}); - setup_type(ID($overwrite_tag), {ID::A, ID::SET, ID::CLR}, pool()); - setup_type(ID($original_tag), {ID::A}, {ID::Y}); - setup_type(ID($future_ff), {ID::A}, {ID::Y}); + setup_type(ID($assert), {TW::A, TW::EN}, pool()); + setup_type(ID($assume), {TW::A, TW::EN}, pool()); + setup_type(ID($live), {TW::A, TW::EN}, pool()); + setup_type(ID($fair), {TW::A, TW::EN}, pool()); + setup_type(ID($cover), {TW::A, TW::EN}, pool()); + setup_type(ID($initstate), pool(), {TW::Y}); + setup_type(ID($anyconst), pool(), {TW::Y}); + setup_type(ID($anyseq), pool(), {TW::Y}); + setup_type(ID($allconst), pool(), {TW::Y}); + setup_type(ID($allseq), pool(), {TW::Y}); + setup_type(ID($equiv), {TW::A, TW::B}, {TW::Y}); + setup_type(ID($specify2), {TW::EN, TW::SRC, TW::DST}, pool()); + setup_type(ID($specify3), {TW::EN, TW::SRC, TW::DST, TW::DAT}, pool()); + setup_type(ID($specrule), {TW::SRC_EN, TW::DST_EN, TW::SRC, TW::DST}, pool()); + setup_type(ID($print), {TW::EN, TW::ARGS, TW::TRG}, pool()); + setup_type(ID($check), {TW::A, TW::EN, TW::ARGS, TW::TRG}, pool()); + setup_type(ID($set_tag), {TW::A, TW::SET, TW::CLR}, {TW::Y}); + setup_type(ID($get_tag), {TW::A}, {TW::Y}); + setup_type(ID($overwrite_tag), {TW::A, TW::SET, TW::CLR}, pool()); + setup_type(ID($original_tag), {TW::A}, {TW::Y}); + setup_type(ID($future_ff), {TW::A}, {TW::Y}); setup_type(ID($scopeinfo), {}, {}); - setup_type(ID($input_port), {}, {ID::Y}); - setup_type(ID($output_port), {ID::A}, {}); - setup_type(ID($public), {ID::A}, {}); - setup_type(ID($connect), {ID::A, ID::B}, {}); + setup_type(ID($input_port), {}, {TW::Y}); + setup_type(ID($output_port), {TW::A}, {}); + setup_type(ID($public), {TW::A}, {}); + setup_type(ID($connect), {TW::A, TW::B}, {}); } void setup_internals_eval() @@ -136,92 +136,92 @@ struct CellTypes }; for (auto type : unary_ops) - setup_type(type, {ID::A}, {ID::Y}, true); + setup_type(type, {TW::A}, {TW::Y}, true); for (auto type : binary_ops) - setup_type(type, {ID::A, ID::B}, {ID::Y}, true); + setup_type(type, {TW::A, TW::B}, {TW::Y}, true); for (auto type : std::vector({ID($mux), ID($pmux), ID($bwmux)})) - setup_type(type, {ID::A, ID::B, ID::S}, {ID::Y}, true); + setup_type(type, {TW::A, TW::B, TW::S}, {TW::Y}, true); for (auto type : std::vector({ID($bmux), ID($demux)})) - setup_type(type, {ID::A, ID::S}, {ID::Y}, true); + setup_type(type, {TW::A, TW::S}, {TW::Y}, true); - setup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, true); - setup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, true); - setup_type(ID($macc_v2), {ID::A, ID::B, ID::C}, {ID::Y}, true); - setup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, true); + setup_type(ID($lcu), {TW::P, TW::G, TW::CI}, {TW::CO}, true); + setup_type(ID($alu), {TW::A, TW::B, TW::CI, TW::BI}, {TW::X, TW::Y, TW::CO}, true); + setup_type(ID($macc_v2), {TW::A, TW::B, TW::C}, {TW::Y}, true); + setup_type(ID($fa), {TW::A, TW::B, TW::C}, {TW::X, TW::Y}, true); } void setup_internals_ff() { - setup_type(ID($sr), {ID::SET, ID::CLR}, {ID::Q}); - setup_type(ID($ff), {ID::D}, {ID::Q}); - setup_type(ID($dff), {ID::CLK, ID::D}, {ID::Q}); - setup_type(ID($dffe), {ID::CLK, ID::EN, ID::D}, {ID::Q}); - setup_type(ID($dffsr), {ID::CLK, ID::SET, ID::CLR, ID::D}, {ID::Q}); - setup_type(ID($dffsre), {ID::CLK, ID::SET, ID::CLR, ID::D, ID::EN}, {ID::Q}); - setup_type(ID($adff), {ID::CLK, ID::ARST, ID::D}, {ID::Q}); - setup_type(ID($adffe), {ID::CLK, ID::ARST, ID::D, ID::EN}, {ID::Q}); - setup_type(ID($aldff), {ID::CLK, ID::ALOAD, ID::AD, ID::D}, {ID::Q}); - setup_type(ID($aldffe), {ID::CLK, ID::ALOAD, ID::AD, ID::D, ID::EN}, {ID::Q}); - setup_type(ID($sdff), {ID::CLK, ID::SRST, ID::D}, {ID::Q}); - setup_type(ID($sdffe), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q}); - setup_type(ID($sdffce), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q}); - setup_type(ID($dlatch), {ID::EN, ID::D}, {ID::Q}); - setup_type(ID($adlatch), {ID::EN, ID::D, ID::ARST}, {ID::Q}); - setup_type(ID($dlatchsr), {ID::EN, ID::SET, ID::CLR, ID::D}, {ID::Q}); + setup_type(ID($sr), {TW::SET, TW::CLR}, {TW::Q}); + setup_type(ID($ff), {TW::D}, {TW::Q}); + setup_type(ID($dff), {TW::CLK, TW::D}, {TW::Q}); + setup_type(ID($dffe), {TW::CLK, TW::EN, TW::D}, {TW::Q}); + setup_type(ID($dffsr), {TW::CLK, TW::SET, TW::CLR, TW::D}, {TW::Q}); + setup_type(ID($dffsre), {TW::CLK, TW::SET, TW::CLR, TW::D, TW::EN}, {TW::Q}); + setup_type(ID($adff), {TW::CLK, TW::ARST, TW::D}, {TW::Q}); + setup_type(ID($adffe), {TW::CLK, TW::ARST, TW::D, TW::EN}, {TW::Q}); + setup_type(ID($aldff), {TW::CLK, TW::ALOAD, TW::AD, TW::D}, {TW::Q}); + setup_type(ID($aldffe), {TW::CLK, TW::ALOAD, TW::AD, TW::D, TW::EN}, {TW::Q}); + setup_type(ID($sdff), {TW::CLK, TW::SRST, TW::D}, {TW::Q}); + setup_type(ID($sdffe), {TW::CLK, TW::SRST, TW::D, TW::EN}, {TW::Q}); + setup_type(ID($sdffce), {TW::CLK, TW::SRST, TW::D, TW::EN}, {TW::Q}); + setup_type(ID($dlatch), {TW::EN, TW::D}, {TW::Q}); + setup_type(ID($adlatch), {TW::EN, TW::D, TW::ARST}, {TW::Q}); + setup_type(ID($dlatchsr), {TW::EN, TW::SET, TW::CLR, TW::D}, {TW::Q}); } void setup_internals_anyinit() { - setup_type(ID($anyinit), {ID::D}, {ID::Q}); + setup_type(ID($anyinit), {TW::D}, {TW::Q}); } void setup_internals_mem() { setup_internals_ff(); - setup_type(ID($memrd), {ID::CLK, ID::EN, ID::ADDR}, {ID::DATA}); - setup_type(ID($memrd_v2), {ID::CLK, ID::EN, ID::ARST, ID::SRST, ID::ADDR}, {ID::DATA}); - setup_type(ID($memwr), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool()); - setup_type(ID($memwr_v2), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool()); - setup_type(ID($meminit), {ID::ADDR, ID::DATA}, pool()); - setup_type(ID($meminit_v2), {ID::ADDR, ID::DATA, ID::EN}, pool()); - setup_type(ID($mem), {ID::RD_CLK, ID::RD_EN, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA}); - setup_type(ID($mem_v2), {ID::RD_CLK, ID::RD_EN, ID::RD_ARST, ID::RD_SRST, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA}); + setup_type(ID($memrd), {TW::CLK, TW::EN, TW::ADDR}, {TW::DATA}); + setup_type(ID($memrd_v2), {TW::CLK, TW::EN, TW::ARST, TW::SRST, TW::ADDR}, {TW::DATA}); + setup_type(ID($memwr), {TW::CLK, TW::EN, TW::ADDR, TW::DATA}, pool()); + setup_type(ID($memwr_v2), {TW::CLK, TW::EN, TW::ADDR, TW::DATA}, pool()); + setup_type(ID($meminit), {TW::ADDR, TW::DATA}, pool()); + setup_type(ID($meminit_v2), {TW::ADDR, TW::DATA, TW::EN}, pool()); + setup_type(ID($mem), {TW::RD_CLK, TW::RD_EN, TW::RD_ADDR, TW::WR_CLK, TW::WR_EN, TW::WR_ADDR, TW::WR_DATA}, {TW::RD_DATA}); + setup_type(ID($mem_v2), {TW::RD_CLK, TW::RD_EN, TW::RD_ARST, TW::RD_SRST, TW::RD_ADDR, TW::WR_CLK, TW::WR_EN, TW::WR_ADDR, TW::WR_DATA}, {TW::RD_DATA}); - setup_type(ID($fsm), {ID::CLK, ID::ARST, ID::CTRL_IN}, {ID::CTRL_OUT}); + setup_type(ID($fsm), {TW::CLK, TW::ARST, TW::CTRL_IN}, {TW::CTRL_OUT}); } void setup_stdcells() { setup_stdcells_eval(); - setup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y}); + setup_type(ID($_TBUF_), {TW::A, TW::E}, {TW::Y}); } void setup_stdcells_eval() { - setup_type(ID($_BUF_), {ID::A}, {ID::Y}, true); - setup_type(ID($_NOT_), {ID::A}, {ID::Y}, true); - setup_type(ID($_AND_), {ID::A, ID::B}, {ID::Y}, true); - setup_type(ID($_NAND_), {ID::A, ID::B}, {ID::Y}, true); - setup_type(ID($_OR_), {ID::A, ID::B}, {ID::Y}, true); - setup_type(ID($_NOR_), {ID::A, ID::B}, {ID::Y}, true); - setup_type(ID($_XOR_), {ID::A, ID::B}, {ID::Y}, true); - setup_type(ID($_XNOR_), {ID::A, ID::B}, {ID::Y}, true); - setup_type(ID($_ANDNOT_), {ID::A, ID::B}, {ID::Y}, true); - setup_type(ID($_ORNOT_), {ID::A, ID::B}, {ID::Y}, true); - setup_type(ID($_MUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true); - setup_type(ID($_NMUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true); - setup_type(ID($_MUX4_), {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T}, {ID::Y}, true); - setup_type(ID($_MUX8_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U}, {ID::Y}, true); - setup_type(ID($_MUX16_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K, ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V}, {ID::Y}, true); - setup_type(ID($_AOI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true); - setup_type(ID($_OAI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true); - setup_type(ID($_AOI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true); - setup_type(ID($_OAI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true); + setup_type(ID($_BUF_), {TW::A}, {TW::Y}, true); + setup_type(ID($_NOT_), {TW::A}, {TW::Y}, true); + setup_type(ID($_AND_), {TW::A, TW::B}, {TW::Y}, true); + setup_type(ID($_NAND_), {TW::A, TW::B}, {TW::Y}, true); + setup_type(ID($_OR_), {TW::A, TW::B}, {TW::Y}, true); + setup_type(ID($_NOR_), {TW::A, TW::B}, {TW::Y}, true); + setup_type(ID($_XOR_), {TW::A, TW::B}, {TW::Y}, true); + setup_type(ID($_XNOR_), {TW::A, TW::B}, {TW::Y}, true); + setup_type(ID($_ANDNOT_), {TW::A, TW::B}, {TW::Y}, true); + setup_type(ID($_ORNOT_), {TW::A, TW::B}, {TW::Y}, true); + setup_type(ID($_MUX_), {TW::A, TW::B, TW::S}, {TW::Y}, true); + setup_type(ID($_NMUX_), {TW::A, TW::B, TW::S}, {TW::Y}, true); + setup_type(ID($_MUX4_), {TW::A, TW::B, TW::C, TW::D, TW::S, TW::T}, {TW::Y}, true); + setup_type(ID($_MUX8_), {TW::A, TW::B, TW::C, TW::D, TW::E, TW::F, TW::G, TW::H, TW::S, TW::T, TW::U}, {TW::Y}, true); + setup_type(ID($_MUX16_), {TW::A, TW::B, TW::C, TW::D, TW::E, TW::F, TW::G, TW::H, TW::I, TW::J, TW::K, TW::L, TW::M, TW::N, TW::O, TW::P, TW::S, TW::T, TW::U, TW::V}, {TW::Y}, true); + setup_type(ID($_AOI3_), {TW::A, TW::B, TW::C}, {TW::Y}, true); + setup_type(ID($_OAI3_), {TW::A, TW::B, TW::C}, {TW::Y}, true); + setup_type(ID($_AOI4_), {TW::A, TW::B, TW::C, TW::D}, {TW::Y}, true); + setup_type(ID($_OAI4_), {TW::A, TW::B, TW::C, TW::D}, {TW::Y}, true); } void setup_stdcells_mem() @@ -230,77 +230,77 @@ struct CellTypes for (auto c1 : list_np) for (auto c2 : list_np) - setup_type(stringf("$_SR_%c%c_", c1, c2), {ID::S, ID::R}, {ID::Q}); + setup_type(stringf("$_SR_%c%c_", c1, c2), {TW::S, TW::R}, {TW::Q}); - setup_type(ID($_FF_), {ID::D}, {ID::Q}); + setup_type(ID($_FF_), {TW::D}, {TW::Q}); for (auto c1 : list_np) - setup_type(stringf("$_DFF_%c_", c1), {ID::C, ID::D}, {ID::Q}); + setup_type(stringf("$_DFF_%c_", c1), {TW::C, TW::D}, {TW::Q}); for (auto c1 : list_np) for (auto c2 : list_np) - setup_type(stringf("$_DFFE_%c%c_", c1, c2), {ID::C, ID::D, ID::E}, {ID::Q}); + setup_type(stringf("$_DFFE_%c%c_", c1, c2), {TW::C, TW::D, TW::E}, {TW::Q}); for (auto c1 : list_np) for (auto c2 : list_np) for (auto c3 : list_01) - setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q}); + setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {TW::C, TW::R, TW::D}, {TW::Q}); for (auto c1 : list_np) for (auto c2 : list_np) for (auto c3 : list_01) for (auto c4 : list_np) - setup_type(stringf("$_DFFE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}); + setup_type(stringf("$_DFFE_%c%c%c%c_", c1, c2, c3, c4), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}); for (auto c1 : list_np) for (auto c2 : list_np) - setup_type(stringf("$_ALDFF_%c%c_", c1, c2), {ID::C, ID::L, ID::AD, ID::D}, {ID::Q}); + setup_type(stringf("$_ALDFF_%c%c_", c1, c2), {TW::C, TW::L, TW::AD, TW::D}, {TW::Q}); for (auto c1 : list_np) for (auto c2 : list_np) for (auto c3 : list_np) - setup_type(stringf("$_ALDFFE_%c%c%c_", c1, c2, c3), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}); + setup_type(stringf("$_ALDFFE_%c%c%c_", c1, c2, c3), {TW::C, TW::L, TW::AD, TW::D, TW::E}, {TW::Q}); for (auto c1 : list_np) for (auto c2 : list_np) for (auto c3 : list_np) - setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {ID::C, ID::S, ID::R, ID::D}, {ID::Q}); + setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {TW::C, TW::S, TW::R, TW::D}, {TW::Q}); for (auto c1 : list_np) for (auto c2 : list_np) for (auto c3 : list_np) for (auto c4 : list_np) - setup_type(stringf("$_DFFSRE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}); + setup_type(stringf("$_DFFSRE_%c%c%c%c_", c1, c2, c3, c4), {TW::C, TW::S, TW::R, TW::D, TW::E}, {TW::Q}); for (auto c1 : list_np) for (auto c2 : list_np) for (auto c3 : list_01) - setup_type(stringf("$_SDFF_%c%c%c_", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q}); + setup_type(stringf("$_SDFF_%c%c%c_", c1, c2, c3), {TW::C, TW::R, TW::D}, {TW::Q}); for (auto c1 : list_np) for (auto c2 : list_np) for (auto c3 : list_01) for (auto c4 : list_np) - setup_type(stringf("$_SDFFE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}); + setup_type(stringf("$_SDFFE_%c%c%c%c_", c1, c2, c3, c4), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}); for (auto c1 : list_np) for (auto c2 : list_np) for (auto c3 : list_01) for (auto c4 : list_np) - setup_type(stringf("$_SDFFCE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}); + setup_type(stringf("$_SDFFCE_%c%c%c%c_", c1, c2, c3, c4), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}); for (auto c1 : list_np) - setup_type(stringf("$_DLATCH_%c_", c1), {ID::E, ID::D}, {ID::Q}); + setup_type(stringf("$_DLATCH_%c_", c1), {TW::E, TW::D}, {TW::Q}); for (auto c1 : list_np) for (auto c2 : list_np) for (auto c3 : list_01) - setup_type(stringf("$_DLATCH_%c%c%c_", c1, c2, c3), {ID::E, ID::R, ID::D}, {ID::Q}); + setup_type(stringf("$_DLATCH_%c%c%c_", c1, c2, c3), {TW::E, TW::R, TW::D}, {TW::Q}); for (auto c1 : list_np) for (auto c2 : list_np) for (auto c3 : list_np) - setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {ID::E, ID::S, ID::R, ID::D}, {ID::Q}); + setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {TW::E, TW::S, TW::R, TW::D}, {TW::Q}); } void clear() @@ -313,19 +313,19 @@ struct CellTypes return cell_types.count(type) != 0; } - bool cell_output(RTLIL::IdString type, RTLIL::IdString port) const + bool cell_output(RTLIL::IdString type, TwineRef port) const { auto it = cell_types.find(type); return it != cell_types.end() && it->second.outputs.count(port) != 0; } - bool cell_input(RTLIL::IdString type, RTLIL::IdString port) const + bool cell_input(RTLIL::IdString type, TwineRef port) const { auto it = cell_types.find(type); return it != cell_types.end() && it->second.inputs.count(port) != 0; } - RTLIL::PortDir cell_port_dir(RTLIL::IdString type, RTLIL::IdString port) const + RTLIL::PortDir cell_port_dir(RTLIL::IdString type, TwineRef port) const { auto it = cell_types.find(type); if (it == cell_types.end()) diff --git a/kernel/consteval.h b/kernel/consteval.h index d00ae8f33..16e53929f 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -95,10 +95,10 @@ struct ConstEval { if (cell->type == ID($lcu)) { - RTLIL::SigSpec sig_p = cell->getPort(ID::P); - RTLIL::SigSpec sig_g = cell->getPort(ID::G); - RTLIL::SigSpec sig_ci = cell->getPort(ID::CI); - RTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(ID::CO))); + RTLIL::SigSpec sig_p = cell->getPort(TW::P); + RTLIL::SigSpec sig_g = cell->getPort(TW::G); + RTLIL::SigSpec sig_ci = cell->getPort(TW::CI); + RTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(TW::CO))); if (sig_co.is_fully_const()) return true; @@ -133,19 +133,19 @@ struct ConstEval RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y; log_assert(cell->hasPort(ID::Y)); - sig_y = values_map(assign_map(cell->getPort(ID::Y))); + sig_y = values_map(assign_map(cell->getPort(TW::Y))); if (sig_y.is_fully_const()) return true; if (cell->hasPort(ID::S)) { - sig_s = cell->getPort(ID::S); + sig_s = cell->getPort(TW::S); } if (cell->hasPort(ID::A)) - sig_a = cell->getPort(ID::A); + sig_a = cell->getPort(TW::A); if (cell->hasPort(ID::B)) - sig_b = cell->getPort(ID::B); + sig_b = cell->getPort(TW::B); if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_NMUX_))) { @@ -231,8 +231,8 @@ struct ConstEval } else if (cell->type == ID($fa)) { - RTLIL::SigSpec sig_c = cell->getPort(ID::C); - RTLIL::SigSpec sig_x = cell->getPort(ID::X); + RTLIL::SigSpec sig_c = cell->getPort(TW::C); + RTLIL::SigSpec sig_x = cell->getPort(TW::X); int width = GetSize(sig_c); if (!eval(sig_a, undef, cell)) @@ -263,8 +263,8 @@ struct ConstEval bool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool(); bool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool(); - RTLIL::SigSpec sig_ci = cell->getPort(ID::CI); - RTLIL::SigSpec sig_bi = cell->getPort(ID::BI); + RTLIL::SigSpec sig_ci = cell->getPort(TW::CI); + RTLIL::SigSpec sig_bi = cell->getPort(TW::BI); if (!eval(sig_a, undef, cell)) return false; @@ -278,8 +278,8 @@ struct ConstEval if (!eval(sig_bi, undef, cell)) return false; - RTLIL::SigSpec sig_x = cell->getPort(ID::X); - RTLIL::SigSpec sig_co = cell->getPort(ID::CO); + RTLIL::SigSpec sig_x = cell->getPort(TW::X); + RTLIL::SigSpec sig_co = cell->getPort(TW::CO); bool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def()); sig_a.extend_u0(GetSize(sig_y), signed_a); @@ -326,11 +326,11 @@ struct ConstEval return false; } - RTLIL::Const result(0, GetSize(cell->getPort(ID::Y))); + RTLIL::Const result(0, GetSize(cell->getPort(TW::Y))); if (!macc.eval(result)) log_abort(); - set(cell->getPort(ID::Y), result); + set(cell->getPort(TW::Y), result); } else { @@ -338,9 +338,9 @@ struct ConstEval if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) { if (cell->hasPort(ID::C)) - sig_c = cell->getPort(ID::C); + sig_c = cell->getPort(TW::C); if (cell->hasPort(ID::D)) - sig_d = cell->getPort(ID::D); + sig_d = cell->getPort(TW::D); } if (sig_a.size() > 0 && !eval(sig_a, undef, cell)) diff --git a/kernel/cost.cc b/kernel/cost.cc index 230afdeb1..7bfe95819 100644 --- a/kernel/cost.cc +++ b/kernel/cost.cc @@ -124,7 +124,7 @@ unsigned int max_inp_width(RTLIL::Cell *cell) unsigned int port_width_sum(RTLIL::Cell *cell) { unsigned int sum = 0; - RTLIL::IdString port_width_params[] = { + TwineRef port_width_params[] = { ID::WIDTH, ID::A_WIDTH, ID::B_WIDTH, ID::S_WIDTH, ID::Y_WIDTH, }; diff --git a/kernel/ff.cc b/kernel/ff.cc index 8581199aa..4fe2524e1 100644 --- a/kernel/ff.cc +++ b/kernel/ff.cc @@ -36,7 +36,7 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) { type = flop->type; } if constexpr (have_cell) { - info.sig_q = cell->getPort(ID::Q); + info.sig_q = cell->getPort(TW::Q); info.width = GetSize(info.sig_q); info.attributes = cell->attributes; // Carry src across construction → emit() as an owning Twine @@ -58,7 +58,7 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) { if (type.in(ID($anyinit), ID($ff))) { info.has_gclk = true; if constexpr (have_cell) - info.sig_d = cell->getPort(ID::D); + info.sig_d = cell->getPort(TW::D); if (type == ID($anyinit)) { info.is_anyinit = true; if constexpr (have_cell) @@ -69,30 +69,30 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) { } else if (type.in(ID($dlatch), ID($adlatch), ID($dlatchsr))) { info.has_aload = true; if constexpr (have_cell) { - info.sig_aload = cell->getPort(ID::EN); + info.sig_aload = cell->getPort(TW::EN); info.pol_aload = cell->getParam(ID::EN_POLARITY).as_bool(); - info.sig_ad = cell->getPort(ID::D); + info.sig_ad = cell->getPort(TW::D); } } else { info.has_clk = true; if constexpr (have_cell) { - info.sig_clk = cell->getPort(ID::CLK); + info.sig_clk = cell->getPort(TW::CLK); info.pol_clk = cell->getParam(ID::CLK_POLARITY).as_bool(); - info.sig_d = cell->getPort(ID::D); + info.sig_d = cell->getPort(TW::D); } } if (type.in(ID($dffe), ID($dffsre), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce))) { info.has_ce = true; if constexpr (have_cell) { - info.sig_ce = cell->getPort(ID::EN); + info.sig_ce = cell->getPort(TW::EN); info.pol_ce = cell->getParam(ID::EN_POLARITY).as_bool(); } } if (type.in(ID($dffsr), ID($dffsre), ID($dlatchsr), ID($sr))) { info.has_sr = true; if constexpr (have_cell) { - info.sig_clr = cell->getPort(ID::CLR); - info.sig_set = cell->getPort(ID::SET); + info.sig_clr = cell->getPort(TW::CLR); + info.sig_set = cell->getPort(TW::SET); info.pol_clr = cell->getParam(ID::CLR_POLARITY).as_bool(); info.pol_set = cell->getParam(ID::SET_POLARITY).as_bool(); } @@ -100,15 +100,15 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) { if (type.in(ID($aldff), ID($aldffe))) { info.has_aload = true; if constexpr (have_cell) { - info.sig_aload = cell->getPort(ID::ALOAD); + info.sig_aload = cell->getPort(TW::ALOAD); info.pol_aload = cell->getParam(ID::ALOAD_POLARITY).as_bool(); - info.sig_ad = cell->getPort(ID::AD); + info.sig_ad = cell->getPort(TW::AD); } } if (type.in(ID($adff), ID($adffe), ID($adlatch))) { info.has_arst = true; if constexpr (have_cell) { - info.sig_arst = cell->getPort(ID::ARST); + info.sig_arst = cell->getPort(TW::ARST); info.pol_arst = cell->getParam(ID::ARST_POLARITY).as_bool(); info.val_arst = cell->getParam(ID::ARST_VALUE); } @@ -116,7 +116,7 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) { if (type.in(ID($sdff), ID($sdffe), ID($sdffce))) { info.has_srst = true; if constexpr (have_cell) { - info.sig_srst = cell->getPort(ID::SRST); + info.sig_srst = cell->getPort(TW::SRST); info.pol_srst = cell->getParam(ID::SRST_POLARITY).as_bool(); info.val_srst = cell->getParam(ID::SRST_VALUE); } @@ -126,23 +126,23 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) { info.is_fine = true; info.has_gclk = true; if constexpr (have_cell) - info.sig_d = cell->getPort(ID::D); + info.sig_d = cell->getPort(TW::D); } else if (type_str.substr(0, 5) == "$_SR_") { info.is_fine = true; info.has_sr = true; info.pol_set = type_str[5] == 'P'; info.pol_clr = type_str[6] == 'P'; if constexpr (have_cell) { - info.sig_set = cell->getPort(ID::S); - info.sig_clr = cell->getPort(ID::R); + info.sig_set = cell->getPort(TW::S); + info.sig_clr = cell->getPort(TW::R); } } else if (type_str.substr(0, 6) == "$_DFF_" && type_str.size() == 8) { info.is_fine = true; info.has_clk = true; info.pol_clk = type_str[6] == 'P'; if constexpr (have_cell) { - info.sig_d = cell->getPort(ID::D); - info.sig_clk = cell->getPort(ID::C); + info.sig_d = cell->getPort(TW::D); + info.sig_clk = cell->getPort(TW::C); } } else if (type_str.substr(0, 7) == "$_DFFE_" && type_str.size() == 10) { info.is_fine = true; @@ -151,9 +151,9 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) { info.has_ce = true; info.pol_ce = type_str[8] == 'P'; if constexpr (have_cell) { - info.sig_d = cell->getPort(ID::D); - info.sig_clk = cell->getPort(ID::C); - info.sig_ce = cell->getPort(ID::E); + info.sig_d = cell->getPort(TW::D); + info.sig_clk = cell->getPort(TW::C); + info.sig_ce = cell->getPort(TW::E); } } else if (type_str.substr(0, 6) == "$_DFF_" && type_str.size() == 10) { info.is_fine = true; @@ -163,9 +163,9 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) { info.pol_arst = type_str[7] == 'P'; info.val_arst = type_str[8] == '1' ? State::S1 : State::S0; if constexpr (have_cell) { - info.sig_d = cell->getPort(ID::D); - info.sig_clk = cell->getPort(ID::C); - info.sig_arst = cell->getPort(ID::R); + info.sig_d = cell->getPort(TW::D); + info.sig_clk = cell->getPort(TW::C); + info.sig_arst = cell->getPort(TW::R); } } else if (type_str.substr(0, 7) == "$_DFFE_" && type_str.size() == 12) { info.is_fine = true; @@ -177,10 +177,10 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) { info.has_ce = true; info.pol_ce = type_str[10] == 'P'; if constexpr (have_cell) { - info.sig_d = cell->getPort(ID::D); - info.sig_clk = cell->getPort(ID::C); - info.sig_arst = cell->getPort(ID::R); - info.sig_ce = cell->getPort(ID::E); + info.sig_d = cell->getPort(TW::D); + info.sig_clk = cell->getPort(TW::C); + info.sig_arst = cell->getPort(TW::R); + info.sig_ce = cell->getPort(TW::E); } } else if (type_str.substr(0, 8) == "$_ALDFF_" && type_str.size() == 11) { info.is_fine = true; @@ -189,10 +189,10 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) { info.has_aload = true; info.pol_aload = type_str[9] == 'P'; if constexpr (have_cell) { - info.sig_d = cell->getPort(ID::D); - info.sig_clk = cell->getPort(ID::C); - info.sig_aload = cell->getPort(ID::L); - info.sig_ad = cell->getPort(ID::AD); + info.sig_d = cell->getPort(TW::D); + info.sig_clk = cell->getPort(TW::C); + info.sig_aload = cell->getPort(TW::L); + info.sig_ad = cell->getPort(TW::AD); } } else if (type_str.substr(0, 9) == "$_ALDFFE_" && type_str.size() == 13) { info.is_fine = true; @@ -203,11 +203,11 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) { info.has_ce = true; info.pol_ce = type_str[11] == 'P'; if constexpr (have_cell) { - info.sig_d = cell->getPort(ID::D); - info.sig_clk = cell->getPort(ID::C); - info.sig_aload = cell->getPort(ID::L); - info.sig_ad = cell->getPort(ID::AD); - info.sig_ce = cell->getPort(ID::E); + info.sig_d = cell->getPort(TW::D); + info.sig_clk = cell->getPort(TW::C); + info.sig_aload = cell->getPort(TW::L); + info.sig_ad = cell->getPort(TW::AD); + info.sig_ce = cell->getPort(TW::E); } } else if (type_str.substr(0, 8) == "$_DFFSR_" && type_str.size() == 12) { info.is_fine = true; @@ -217,10 +217,10 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) { info.pol_set = type_str[9] == 'P'; info.pol_clr = type_str[10] == 'P'; if constexpr (have_cell) { - info.sig_d = cell->getPort(ID::D); - info.sig_clk = cell->getPort(ID::C); - info.sig_set = cell->getPort(ID::S); - info.sig_clr = cell->getPort(ID::R); + info.sig_d = cell->getPort(TW::D); + info.sig_clk = cell->getPort(TW::C); + info.sig_set = cell->getPort(TW::S); + info.sig_clr = cell->getPort(TW::R); } } else if (type_str.substr(0, 9) == "$_DFFSRE_" && type_str.size() == 14) { info.is_fine = true; @@ -232,11 +232,11 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) { info.has_ce = true; info.pol_ce = type_str[12] == 'P'; if constexpr (have_cell) { - info.sig_d = cell->getPort(ID::D); - info.sig_clk = cell->getPort(ID::C); - info.sig_set = cell->getPort(ID::S); - info.sig_clr = cell->getPort(ID::R); - info.sig_ce = cell->getPort(ID::E); + info.sig_d = cell->getPort(TW::D); + info.sig_clk = cell->getPort(TW::C); + info.sig_set = cell->getPort(TW::S); + info.sig_clr = cell->getPort(TW::R); + info.sig_ce = cell->getPort(TW::E); } } else if (type_str.substr(0, 7) == "$_SDFF_" && type_str.size() == 11) { info.is_fine = true; @@ -246,9 +246,9 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) { info.pol_srst = type_str[8] == 'P'; info.val_srst = type_str[9] == '1' ? State::S1 : State::S0; if constexpr (have_cell) { - info.sig_d = cell->getPort(ID::D); - info.sig_clk = cell->getPort(ID::C); - info.sig_srst = cell->getPort(ID::R); + info.sig_d = cell->getPort(TW::D); + info.sig_clk = cell->getPort(TW::C); + info.sig_srst = cell->getPort(TW::R); } } else if (type_str.substr(0, 8) == "$_SDFFE_" && type_str.size() == 13) { info.is_fine = true; @@ -260,10 +260,10 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) { info.has_ce = true; info.pol_ce = type_str[11] == 'P'; if constexpr (have_cell) { - info.sig_d = cell->getPort(ID::D); - info.sig_clk = cell->getPort(ID::C); - info.sig_srst = cell->getPort(ID::R); - info.sig_ce = cell->getPort(ID::E); + info.sig_d = cell->getPort(TW::D); + info.sig_clk = cell->getPort(TW::C); + info.sig_srst = cell->getPort(TW::R); + info.sig_ce = cell->getPort(TW::E); } } else if (type_str.substr(0, 9) == "$_SDFFCE_" && type_str.size() == 14) { info.is_fine = true; @@ -276,10 +276,10 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) { info.pol_ce = type_str[12] == 'P'; info.ce_over_srst = true; if constexpr (have_cell) { - info.sig_d = cell->getPort(ID::D); - info.sig_clk = cell->getPort(ID::C); - info.sig_srst = cell->getPort(ID::R); - info.sig_ce = cell->getPort(ID::E); + info.sig_d = cell->getPort(TW::D); + info.sig_clk = cell->getPort(TW::C); + info.sig_srst = cell->getPort(TW::R); + info.sig_ce = cell->getPort(TW::E); } } else if (type_str.substr(0, 9) == "$_DLATCH_" && type_str.size() == 11) { info.is_fine = true; @@ -287,8 +287,8 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) { info.has_aload = true; info.pol_aload = type_str[9] == 'P'; if constexpr (have_cell) { - info.sig_ad = cell->getPort(ID::D); - info.sig_aload = cell->getPort(ID::E); + info.sig_ad = cell->getPort(TW::D); + info.sig_aload = cell->getPort(TW::E); } } else if (type_str.substr(0, 9) == "$_DLATCH_" && type_str.size() == 13) { info.is_fine = true; @@ -299,9 +299,9 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) { info.pol_arst = type_str[10] == 'P'; info.val_arst = type_str[11] == '1' ? State::S1 : State::S0; if constexpr (have_cell) { - info.sig_ad = cell->getPort(ID::D); - info.sig_aload = cell->getPort(ID::E); - info.sig_arst = cell->getPort(ID::R); + info.sig_ad = cell->getPort(TW::D); + info.sig_aload = cell->getPort(TW::E); + info.sig_arst = cell->getPort(TW::R); } } else if (type_str.substr(0, 11) == "$_DLATCHSR_" && type_str.size() == 15) { info.is_fine = true; @@ -312,10 +312,10 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) { info.pol_set = type_str[12] == 'P'; info.pol_clr = type_str[13] == 'P'; if constexpr (have_cell) { - info.sig_ad = cell->getPort(ID::D); - info.sig_aload = cell->getPort(ID::E); - info.sig_set = cell->getPort(ID::S); - info.sig_clr = cell->getPort(ID::R); + info.sig_ad = cell->getPort(TW::D); + info.sig_aload = cell->getPort(TW::E); + info.sig_set = cell->getPort(TW::S); + info.sig_clr = cell->getPort(TW::R); } } else { log_assert(0); @@ -780,7 +780,7 @@ Cell *FfData::emit() { } } if (initvals && !is_anyinit) - initvals->set_init(cell->getPort(ID::Q), val_init); + initvals->set_init(cell->getPort(TW::Q), val_init); return cell; } @@ -823,7 +823,7 @@ void FfData::flip_bits(const pool &bits) { flip_rst_bits(bits); - Wire *new_q = module->addWire(NEW_ID, width); + Wire *new_q = module->addWire(NEW_TWINE, width); if (has_sr && cell) { log_warning("Flipping D/Q/init and inserting priority fixup to legalize %s.%s [%s].\n", module->name.unescape(), cell->name.unescape(), cell->type.unescape()); diff --git a/kernel/ffmerge.cc b/kernel/ffmerge.cc index 1a0826086..26f8e35df 100644 --- a/kernel/ffmerge.cc +++ b/kernel/ffmerge.cc @@ -298,12 +298,12 @@ void FfMergeHelper::remove_output_ff(const pool> &bits) { for (auto &it : bits) { Cell *cell = it.first; int idx = it.second; - SigSpec q = cell->getPort(ID::Q); + SigSpec q = cell->getPort(TW::Q); initvals->remove_init(q[idx]); dff_driver.erase((*sigmap)(q[idx])); q[idx] = module->addWire(stringf("$ffmerge_disconnected$%d", autoidx++)); - cell->setPort(ID::Q, q); - initvals->set_init(cell->getPort(ID::Q), (*initvals)(q)); + cell->setPort(TW::Q, q); + initvals->set_init(cell->getPort(TW::Q), (*initvals)(q)); } } @@ -312,7 +312,7 @@ void FfMergeHelper::mark_input_ff(const pool> &bits) { Cell *cell = it.first; int idx = it.second; if (cell->hasPort(ID::D)) { - SigSpec d = cell->getPort(ID::D); + SigSpec d = cell->getPort(TW::D); // The user count was already at least 1 // (for the D port). Bump it as it is now connected // to the merged-to cell as well. This suffices for @@ -338,11 +338,11 @@ void FfMergeHelper::set(FfInitVals *initvals_, RTLIL::Module *module_) for (auto cell : module->cells()) { if (cell->is_builtin_ff()) { if (cell->hasPort(ID::D)) { - SigSpec d = (*sigmap)(cell->getPort(ID::D)); + SigSpec d = (*sigmap)(cell->getPort(TW::D)); for (int i = 0; i < GetSize(d); i++) dff_sink[d[i]].insert(std::make_pair(cell, i)); } - SigSpec q = (*sigmap)(cell->getPort(ID::Q)); + SigSpec q = (*sigmap)(cell->getPort(TW::Q)); for (int i = 0; i < GetSize(q); i++) dff_driver[q[i]] = std::make_pair(cell, i); } diff --git a/kernel/macc.h b/kernel/macc.h index b4c58d20b..0b69b6498 100644 --- a/kernel/macc.h +++ b/kernel/macc.h @@ -84,7 +84,7 @@ struct Macc void from_cell_v1(RTLIL::Cell *cell) { - RTLIL::SigSpec port_a = cell->getPort(ID::A); + RTLIL::SigSpec port_a = cell->getPort(TW::A); terms.clear(); @@ -129,7 +129,7 @@ struct Macc terms.push_back(this_port); } - for (auto bit : cell->getPort(ID::B)) + for (auto bit : cell->getPort(TW::B)) terms.push_back(term_t{{bit}, {}, false, false}); log_assert(config_cursor == config_width); @@ -144,9 +144,9 @@ struct Macc } log_assert(cell->type == ID($macc_v2)); - RTLIL::SigSpec port_a = cell->getPort(ID::A); - RTLIL::SigSpec port_b = cell->getPort(ID::B); - RTLIL::SigSpec port_c = cell->getPort(ID::C); + RTLIL::SigSpec port_a = cell->getPort(TW::A); + RTLIL::SigSpec port_b = cell->getPort(TW::B); + RTLIL::SigSpec port_c = cell->getPort(TW::C); terms.clear(); @@ -255,9 +255,9 @@ struct Macc cell->setParam(ID::A_WIDTHS, a_widths); cell->setParam(ID::B_WIDTHS, b_widths); cell->setParam(ID::C_WIDTHS, c_widths); - cell->setPort(ID::A, a); - cell->setPort(ID::B, b); - cell->setPort(ID::C, c); + cell->setPort(TW::A, a); + cell->setPort(TW::B, b); + cell->setPort(TW::C, c); } bool eval(RTLIL::Const &result) const diff --git a/kernel/mem.cc b/kernel/mem.cc index 740b48809..2a10b92df 100644 --- a/kernel/mem.cc +++ b/kernel/mem.cc @@ -221,12 +221,12 @@ void Mem::emit() { cell->parameters[ID::RD_SRST_VALUE] = rd_srst_value; cell->parameters[ID::RD_INIT_VALUE] = rd_init_value; cell->parameters.erase(ID::RD_TRANSPARENT); - cell->setPort(ID::RD_CLK, rd_clk); - cell->setPort(ID::RD_EN, rd_en); - cell->setPort(ID::RD_ARST, rd_arst); - cell->setPort(ID::RD_SRST, rd_srst); - cell->setPort(ID::RD_ADDR, rd_addr); - cell->setPort(ID::RD_DATA, rd_data); + cell->setPort(TW::RD_CLK, rd_clk); + cell->setPort(TW::RD_EN, rd_en); + cell->setPort(TW::RD_ARST, rd_arst); + cell->setPort(TW::RD_SRST, rd_srst); + cell->setPort(TW::RD_ADDR, rd_addr); + cell->setPort(TW::RD_DATA, rd_data); Const::Builder wr_wide_continuation_builder; Const::Builder wr_clk_enable_builder; Const::Builder wr_clk_polarity_builder; @@ -270,10 +270,10 @@ void Mem::emit() { cell->parameters[ID::WR_CLK_POLARITY] = wr_clk_polarity; cell->parameters[ID::WR_PRIORITY_MASK] = wr_priority_mask; cell->parameters[ID::WR_WIDE_CONTINUATION] = wr_wide_continuation; - cell->setPort(ID::WR_CLK, wr_clk); - cell->setPort(ID::WR_EN, wr_en); - cell->setPort(ID::WR_ADDR, wr_addr); - cell->setPort(ID::WR_DATA, wr_data); + cell->setPort(TW::WR_CLK, wr_clk); + cell->setPort(TW::WR_EN, wr_en); + cell->setPort(TW::WR_ADDR, wr_addr); + cell->setPort(TW::WR_DATA, wr_data); for (auto &init : inits) { for (auto attr: init.attributes) if (!cell->has_attribute(attr.first)) @@ -303,7 +303,7 @@ void Mem::emit() { mem->attributes = attributes; for (auto &port : rd_ports) { if (!port.cell) - port.cell = module->addCell(NEW_ID, ID($memrd_v2)); + port.cell = module->addCell(NEW_TWINE, ID($memrd_v2)); port.cell->type = ID($memrd_v2); port.cell->attributes = port.attributes; port.cell->parameters[ID::MEMID] = memid.str(); @@ -318,17 +318,17 @@ void Mem::emit() { port.cell->parameters[ID::TRANSPARENCY_MASK] = port.transparency_mask; port.cell->parameters[ID::COLLISION_X_MASK] = port.collision_x_mask; port.cell->parameters.erase(ID::TRANSPARENT); - port.cell->setPort(ID::CLK, port.clk); - port.cell->setPort(ID::EN, port.en); - port.cell->setPort(ID::ARST, port.arst); - port.cell->setPort(ID::SRST, port.srst); - port.cell->setPort(ID::ADDR, port.addr); - port.cell->setPort(ID::DATA, port.data); + port.cell->setPort(TW::CLK, port.clk); + port.cell->setPort(TW::EN, port.en); + port.cell->setPort(TW::ARST, port.arst); + port.cell->setPort(TW::SRST, port.srst); + port.cell->setPort(TW::ADDR, port.addr); + port.cell->setPort(TW::DATA, port.data); } int idx = 0; for (auto &port : wr_ports) { if (!port.cell) - port.cell = module->addCell(NEW_ID, ID($memwr_v2)); + port.cell = module->addCell(NEW_TWINE, ID($memwr_v2)); port.cell->type = ID($memwr_v2); port.cell->attributes = port.attributes; if (port.cell->parameters.count(ID::PRIORITY)) @@ -340,19 +340,19 @@ void Mem::emit() { port.cell->parameters[ID::CLK_POLARITY] = port.clk_polarity; port.cell->parameters[ID::PORTID] = idx++; port.cell->parameters[ID::PRIORITY_MASK] = port.priority_mask; - port.cell->setPort(ID::CLK, port.clk); - port.cell->setPort(ID::EN, port.en); - port.cell->setPort(ID::ADDR, port.addr); - port.cell->setPort(ID::DATA, port.data); + port.cell->setPort(TW::CLK, port.clk); + port.cell->setPort(TW::EN, port.en); + port.cell->setPort(TW::ADDR, port.addr); + port.cell->setPort(TW::DATA, port.data); } idx = 0; for (auto &init : inits) { bool v2 = !init.en.is_fully_ones(); if (!init.cell) - init.cell = module->addCell(NEW_ID, v2 ? ID($meminit_v2) : ID($meminit)); + init.cell = module->addCell(NEW_TWINE, v2 ? ID($meminit_v2) : ID($meminit)); else { if (!v2) - init.cell->unsetPort(ID::EN); + init.cell->unsetPort(TW::EN); init.cell->type = v2 ? ID($meminit_v2) : ID($meminit); } init.cell->attributes = init.attributes; @@ -361,10 +361,10 @@ void Mem::emit() { init.cell->parameters[ID::WIDTH] = width; init.cell->parameters[ID::WORDS] = GetSize(init.data) / width; init.cell->parameters[ID::PRIORITY] = idx++; - init.cell->setPort(ID::ADDR, init.addr); - init.cell->setPort(ID::DATA, init.data); + init.cell->setPort(TW::ADDR, init.addr); + init.cell->setPort(TW::DATA, init.data); if (v2) - init.cell->setPort(ID::EN, init.en); + init.cell->setPort(TW::EN, init.en); } } } @@ -576,10 +576,10 @@ namespace { mrd.attributes = cell->attributes; mrd.clk_enable = cell->parameters.at(ID::CLK_ENABLE).as_bool(); mrd.clk_polarity = cell->parameters.at(ID::CLK_POLARITY).as_bool(); - mrd.clk = cell->getPort(ID::CLK); - mrd.en = cell->getPort(ID::EN); - mrd.addr = cell->getPort(ID::ADDR); - mrd.data = cell->getPort(ID::DATA); + mrd.clk = cell->getPort(TW::CLK); + mrd.en = cell->getPort(TW::EN); + mrd.addr = cell->getPort(TW::ADDR); + mrd.data = cell->getPort(TW::DATA); mrd.wide_log2 = ceil_log2(GetSize(mrd.data) / mem->width); bool transparent = false; if (is_compat) { @@ -604,8 +604,8 @@ namespace { mrd.arst_value = cell->parameters.at(ID::ARST_VALUE); mrd.srst_value = cell->parameters.at(ID::SRST_VALUE); mrd.init_value = cell->parameters.at(ID::INIT_VALUE); - mrd.arst = cell->getPort(ID::ARST); - mrd.srst = cell->getPort(ID::SRST); + mrd.arst = cell->getPort(TW::ARST); + mrd.srst = cell->getPort(TW::SRST); } res.rd_ports.push_back(mrd); rd_transparent.push_back(transparent); @@ -620,10 +620,10 @@ namespace { mwr.attributes = cell->attributes; mwr.clk_enable = cell->parameters.at(ID::CLK_ENABLE).as_bool(); mwr.clk_polarity = cell->parameters.at(ID::CLK_POLARITY).as_bool(); - mwr.clk = cell->getPort(ID::CLK); - mwr.en = cell->getPort(ID::EN); - mwr.addr = cell->getPort(ID::ADDR); - mwr.data = cell->getPort(ID::DATA); + mwr.clk = cell->getPort(TW::CLK); + mwr.en = cell->getPort(TW::EN); + mwr.addr = cell->getPort(TW::ADDR); + mwr.data = cell->getPort(TW::DATA); mwr.wide_log2 = ceil_log2(GetSize(mwr.data) / mem->width); ports.push_back(std::make_pair(cell->parameters.at(is_compat ? ID::PRIORITY : ID::PORTID).as_int(), mwr)); } @@ -662,8 +662,8 @@ namespace { MemInit init; init.cell = cell; init.attributes = cell->attributes; - auto addr = cell->getPort(ID::ADDR); - auto data = cell->getPort(ID::DATA); + auto addr = cell->getPort(TW::ADDR); + auto data = cell->getPort(TW::DATA); if (!addr.is_fully_const()) log_error("Non-constant address %s in memory initialization %s.\n", log_signal(addr), cell); if (!data.is_fully_const()) @@ -671,7 +671,7 @@ namespace { init.addr = addr.as_const(); init.data = data.as_const(); if (cell->type == ID($meminit_v2)) { - auto en = cell->getPort(ID::EN); + auto en = cell->getPort(TW::EN); if (!en.is_fully_const()) log_error("Non-constant enable %s in memory initialization %s.\n", log_signal(en), cell); init.en = en.as_const(); @@ -764,10 +764,10 @@ namespace { log_assert(ni - i == (1 << mrd.wide_log2)); mrd.clk_enable = cell->parameters.at(ID::RD_CLK_ENABLE).extract(i, 1).as_bool(); mrd.clk_polarity = cell->parameters.at(ID::RD_CLK_POLARITY).extract(i, 1).as_bool(); - mrd.clk = cell->getPort(ID::RD_CLK).extract(i, 1); - mrd.en = cell->getPort(ID::RD_EN).extract(i, 1); - mrd.addr = cell->getPort(ID::RD_ADDR).extract(i * abits, abits); - mrd.data = cell->getPort(ID::RD_DATA).extract(i * res.width, (ni - i) * res.width); + mrd.clk = cell->getPort(TW::RD_CLK).extract(i, 1); + mrd.en = cell->getPort(TW::RD_EN).extract(i, 1); + mrd.addr = cell->getPort(TW::RD_ADDR).extract(i * abits, abits); + mrd.data = cell->getPort(TW::RD_DATA).extract(i * res.width, (ni - i) * res.width); if (is_compat) { mrd.ce_over_srst = false; mrd.arst_value = Const(State::Sx, res.width << mrd.wide_log2); @@ -780,8 +780,8 @@ namespace { mrd.arst_value = cell->parameters.at(ID::RD_ARST_VALUE).extract(i * res.width, (ni - i) * res.width); mrd.srst_value = cell->parameters.at(ID::RD_SRST_VALUE).extract(i * res.width, (ni - i) * res.width); mrd.init_value = cell->parameters.at(ID::RD_INIT_VALUE).extract(i * res.width, (ni - i) * res.width); - mrd.arst = cell->getPort(ID::RD_ARST).extract(i, 1); - mrd.srst = cell->getPort(ID::RD_SRST).extract(i, 1); + mrd.arst = cell->getPort(TW::RD_ARST).extract(i, 1); + mrd.srst = cell->getPort(TW::RD_SRST).extract(i, 1); } if (!is_compat) { Const transparency_mask = cell->parameters.at(ID::RD_TRANSPARENCY_MASK).extract(i * n_wr_ports, n_wr_ports); @@ -803,10 +803,10 @@ namespace { log_assert(ni - i == (1 << mwr.wide_log2)); mwr.clk_enable = cell->parameters.at(ID::WR_CLK_ENABLE).extract(i, 1).as_bool(); mwr.clk_polarity = cell->parameters.at(ID::WR_CLK_POLARITY).extract(i, 1).as_bool(); - mwr.clk = cell->getPort(ID::WR_CLK).extract(i, 1); - mwr.en = cell->getPort(ID::WR_EN).extract(i * res.width, (ni - i) * res.width); - mwr.addr = cell->getPort(ID::WR_ADDR).extract(i * abits, abits); - mwr.data = cell->getPort(ID::WR_DATA).extract(i * res.width, (ni - i) * res.width); + mwr.clk = cell->getPort(TW::WR_CLK).extract(i, 1); + mwr.en = cell->getPort(TW::WR_EN).extract(i * res.width, (ni - i) * res.width); + mwr.addr = cell->getPort(TW::WR_ADDR).extract(i * abits, abits); + mwr.data = cell->getPort(TW::WR_DATA).extract(i * res.width, (ni - i) * res.width); if (!is_compat) { Const priority_mask = cell->parameters.at(ID::WR_PRIORITY_MASK).extract(i * n_wr_ports, n_wr_ports); for (int j = 0; j < n_wr_ports; j++) @@ -1178,7 +1178,7 @@ void Mem::emulate_transparency(int widx, int ridx, FfInitVals *initvals) { // The write data FF doesn't need full reset/init behavior, as it'll be masked by // the mux whenever this would be relevant. It does, however, need to have the same // clock enable signal as the read port. - SigSpec wdata_q = module->addWire(NEW_ID, GetSize(wport.data)); + SigSpec wdata_q = module->addWire(NEW_TWINE, GetSize(wport.data)); module->addDffe(NEW_ID, rport.clk, rport.en, wport.data, wdata_q, rport.clk_polarity, true); for (int sub = 0; sub < (1 << max_wide_log2); sub += (1 << min_wide_log2)) { SigSpec raddr = rport.addr; @@ -1195,7 +1195,7 @@ void Mem::emulate_transparency(int widx, int ridx, FfInitVals *initvals) { int ewidth = width << min_wide_log2; int wsub = wide_write ? sub : 0; int rsub = wide_write ? 0 : sub; - SigSpec rdata_a = module->addWire(NEW_ID, ewidth); + SigSpec rdata_a = module->addWire(NEW_TWINE, ewidth); while (pos < ewidth) { int epos = pos; while (epos < ewidth && wport.en[epos + wsub * width] == wport.en[pos + wsub * width]) @@ -1205,7 +1205,7 @@ void Mem::emulate_transparency(int widx, int ridx, FfInitVals *initvals) { cond = module->And(NEW_ID, wport.en[pos + wsub * width], addr_eq); else cond = wport.en[pos + wsub * width]; - SigSpec cond_q = module->addWire(NEW_ID); + SigSpec cond_q = module->addWire(NEW_TWINE); // The FF for storing the bypass enable signal must be carefully // constructed to preserve the overall init/reset/enable behavior // of the whole port. @@ -1405,9 +1405,9 @@ void Mem::emulate_rden(int idx, FfInitVals *initvals) { auto &port = rd_ports[idx]; log_assert(port.clk_enable); emulate_rd_ce_over_srst(idx); - Wire *new_data = module->addWire(NEW_ID, GetSize(port.data)); - Wire *prev_data = module->addWire(NEW_ID, GetSize(port.data)); - Wire *sel = module->addWire(NEW_ID); + Wire *new_data = module->addWire(NEW_TWINE, GetSize(port.data)); + Wire *prev_data = module->addWire(NEW_TWINE, GetSize(port.data)); + Wire *sel = module->addWire(NEW_TWINE); FfData ff_sel(module, initvals, NEW_ID); FfData ff_data(module, initvals, NEW_ID); ff_sel.width = 1; @@ -1465,9 +1465,9 @@ void Mem::emulate_rden(int idx, FfInitVals *initvals) { void Mem::emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, FfInitVals *initvals) { auto &port = rd_ports[idx]; if (emu_init && !port.init_value.is_fully_undef()) { - Wire *sel = module->addWire(NEW_ID); + Wire *sel = module->addWire(NEW_TWINE); FfData ff_sel(module, initvals, NEW_ID); - Wire *new_data = module->addWire(NEW_ID, GetSize(port.data)); + Wire *new_data = module->addWire(NEW_TWINE, GetSize(port.data)); ff_sel.width = 1; ff_sel.has_clk = true; ff_sel.sig_clk = port.clk; @@ -1511,9 +1511,9 @@ void Mem::emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, Ff port.init_value = Const(State::Sx, GetSize(port.data)); } if (emu_arst && port.arst != State::S0) { - Wire *sel = module->addWire(NEW_ID); + Wire *sel = module->addWire(NEW_TWINE); FfData ff_sel(module, initvals, NEW_ID); - Wire *new_data = module->addWire(NEW_ID, GetSize(port.data)); + Wire *new_data = module->addWire(NEW_TWINE, GetSize(port.data)); ff_sel.width = 1; ff_sel.has_clk = true; ff_sel.sig_clk = port.clk; @@ -1551,9 +1551,9 @@ void Mem::emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, Ff port.arst = State::S0; } if (emu_srst && port.srst != State::S0) { - Wire *sel = module->addWire(NEW_ID); + Wire *sel = module->addWire(NEW_TWINE); FfData ff_sel(module, initvals, NEW_ID); - Wire *new_data = module->addWire(NEW_ID, GetSize(port.data)); + Wire *new_data = module->addWire(NEW_TWINE, GetSize(port.data)); ff_sel.width = 1; ff_sel.has_clk = true; ff_sel.sig_clk = port.clk; @@ -1652,10 +1652,10 @@ void Mem::emulate_read_first(FfInitVals *initvals) { rd_ports[i].transparency_mask[j] = true; } for (auto &port: wr_ports) { - Wire *new_data = module->addWire(NEW_ID, GetSize(port.data)); - Wire *new_addr = module->addWire(NEW_ID, GetSize(port.addr)); + Wire *new_data = module->addWire(NEW_TWINE, GetSize(port.data)); + Wire *new_addr = module->addWire(NEW_TWINE, GetSize(port.addr)); auto compressed = port.compress_en(); - Wire *new_en = module->addWire(NEW_ID, GetSize(compressed.first)); + Wire *new_en = module->addWire(NEW_TWINE, GetSize(compressed.first)); FfData ff_data(module, initvals, NEW_ID); FfData ff_addr(module, initvals, NEW_ID); FfData ff_en(module, initvals, NEW_ID); diff --git a/kernel/modtools.h b/kernel/modtools.h index bdcb0f108..c6cee0cf8 100644 --- a/kernel/modtools.h +++ b/kernel/modtools.h @@ -47,11 +47,11 @@ struct ModIndex : public RTLIL::Monitor }; struct PortInfo { RTLIL::Cell* cell; - RTLIL::IdString port; + TwineRef port; int offset; PortInfo() : cell(), port(), offset() { } - PortInfo(RTLIL::Cell* _c, RTLIL::IdString _p, int _o) : cell(_c), port(_p), offset(_o) { } + PortInfo(RTLIL::Cell* _c, TwineRef _p, int _o) : cell(_c), port(_p), offset(_o) { } bool operator<(const PortInfo &other) const { if (cell != other.cell) @@ -98,7 +98,7 @@ struct ModIndex : public RTLIL::Monitor int auto_reload_counter; bool auto_reload_module; - void port_add(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig) + void port_add(RTLIL::Cell *cell, TwineRef port, const RTLIL::SigSpec &sig) { for (int i = 0; i < GetSize(sig); i++) { RTLIL::SigBit bit = sigmap(sig[i]); @@ -107,7 +107,7 @@ struct ModIndex : public RTLIL::Monitor } } - void port_del(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig) + void port_del(RTLIL::Cell *cell, TwineRef port, const RTLIL::SigSpec &sig) { for (int i = 0; i < GetSize(sig); i++) { RTLIL::SigBit bit = sigmap(sig[i]); @@ -187,7 +187,7 @@ struct ModIndex : public RTLIL::Monitor log_assert(ok()); } - void notify_connect(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override + void notify_connect(RTLIL::Cell *cell, TwineRef port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override { log_assert(module == cell->module); @@ -321,7 +321,7 @@ struct ModIndex : public RTLIL::Monitor log(" PRIMARY OUTPUT\n"); for (auto &port : it.second.ports) log(" PORT: %s.%s[%d] (%s)\n", port.cell, - port.port.unescape(), port.offset, port.cell->type.unescape()); + module->design->twines.str(port.port), port.offset, port.cell->type.unescape()); } } }; @@ -331,9 +331,9 @@ struct ModWalker struct PortBit { RTLIL::Cell *cell; - RTLIL::IdString port; + TwineRef port; int offset; - PortBit(Cell* c, IdString p, int o) : cell(c), port(p), offset(o) {} + PortBit(Cell* c, TwineRef p, int o) : cell(c), port(p), offset(o) {} bool operator<(const PortBit &other) const { if (cell != other.cell) @@ -384,7 +384,7 @@ struct ModWalker } } - void add_cell_port(RTLIL::Cell *cell, RTLIL::IdString port, std::vector bits, bool is_output, bool is_input) + void add_cell_port(RTLIL::Cell *cell, TwineRef port, std::vector bits, bool is_output, bool is_input) { for (int i = 0; i < int(bits.size()); i++) if (bits[i].wire != NULL) { diff --git a/kernel/newcelltypes.h b/kernel/newcelltypes.h index f255f44b7..5d286b978 100644 --- a/kernel/newcelltypes.h +++ b/kernel/newcelltypes.h @@ -586,9 +586,9 @@ struct NewCellTypes { for (auto wire_name : module->ports) { RTLIL::Wire *wire = module->wire(wire_name); if (wire->port_input) - inputs.insert(wire->meta_->name_id); + inputs.insert(wire->meta_->name); if (wire->port_output) - outputs.insert(wire->meta_->name_id); + outputs.insert(wire->meta_->name); } setup_type(module->name, inputs, outputs); } diff --git a/kernel/pmux.h b/kernel/pmux.h index f40b721ff..6903028ce 100644 --- a/kernel/pmux.h +++ b/kernel/pmux.h @@ -14,7 +14,7 @@ struct PmuxBPortIterator { PmuxBPortIterator(Cell* mux) : cell(mux) { log_assert(mux->type == ID($mux) || mux->type == ID($pmux)); port_idx = 0; - b = mux->getPort(ID::B).to_sigbit_vector(); + b = mux->getPort(TW::B).to_sigbit_vector(); port_count = GetSize(sig_b) / s_width; } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index b20e1d829..71ece2876 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -987,7 +987,7 @@ void RTLIL::Design::obj_set_src_id(RTLIL::AttrObject *obj, TwineRef id) m.src = id; // if (m.src != Twine::Null) // twines.retain(m.src); - if (m.src == Twine::Null && m.name_id == Twine::Null) { + if (m.src == Twine::Null && m.name == Twine::Null) { free_obj_meta(obj->meta_); obj->meta_ = nullptr; } @@ -1002,7 +1002,7 @@ void RTLIL::Design::obj_release_src(RTLIL::AttrObject *obj) // twines.release(m.src); m.src = Twine::Null; } - if (m.name_id == Twine::Null) { + if (m.name == Twine::Null) { free_obj_meta(obj->meta_); obj->meta_ = nullptr; } @@ -1017,87 +1017,62 @@ void RTLIL::Design::obj_release_src(RTLIL::AttrObject *obj) // } // ObjMeta &m = *obj->meta_; // m.name = name; -// if (m.name.empty() && m.src == Twine::Null && m.name_id == Twine::Null) { +// if (m.name.empty() && m.src == Twine::Null && m.name == Twine::Null) { // free_obj_meta(obj->meta_); // obj->meta_ = nullptr; // } // } -void RTLIL::Design::obj_release_name(RTLIL::AttrObject *obj) -{ - if (obj->meta_ == nullptr) - return; - ObjMeta &m = *obj->meta_; - m.name_id = TwineRef(); - if (m.src == Twine::Null && m.name_id == Twine::Null) { - free_obj_meta(obj->meta_); - obj->meta_ = nullptr; - } -} +// void RTLIL::Design::obj_release_name(RTLIL::AttrObject *obj) +// { +// if (obj->meta_ == nullptr) +// return; +// ObjMeta &m = *obj->meta_; +// m.name = Twine::Null; +// if (m.src == Twine::Null && m.name == Twine::Null) { +// free_obj_meta(obj->meta_); +// obj->meta_ = nullptr; +// } +// } -void RTLIL::Design::obj_set_name_id(RTLIL::AttrObject *obj, TwineRef id) -{ - if (obj->meta_ == nullptr) { - if (id == Twine::Null) - return; - obj->meta_ = alloc_obj_meta(); - } - ObjMeta &m = *obj->meta_; - if (m.name_id == id) - return; - // if (m.name_id != Twine::Null) - // twines.release(m.name_id); - m.name_id = id; - // if (m.name_id != Twine::Null) - // twines.retain(m.name_id); - if (m.name_id == Twine::Null && m.src == Twine::Null) { - free_obj_meta(obj->meta_); - obj->meta_ = nullptr; - } -} +// void RTLIL::Design::obj_set_name(RTLIL::AttrObject *obj, TwineRef id) +// { +// if (obj->meta_ == nullptr) { +// if (id == Twine::Null) +// return; +// obj->meta_ = alloc_obj_meta(); +// } +// ObjMeta &m = *obj->meta_; +// if (m.name == id) +// return; +// // if (m.name != Twine::Null) +// // twines.release(m.name); +// m.name = id; +// // if (m.name != Twine::Null) +// // twines.retain(m.name); +// if (m.name == Twine::Null && m.src == Twine::Null) { +// free_obj_meta(obj->meta_); +// obj->meta_ = nullptr; +// } +// } -void RTLIL::Design::obj_release_name_id(RTLIL::AttrObject *obj) -{ - if (obj->meta_ == nullptr) - return; - ObjMeta &m = *obj->meta_; - if (m.name_id != Twine::Null) { - twines.release(m.name_id); - m.name_id = Twine::Null; - } - if (m.src == Twine::Null && m.name_id == Twine::Null) { - free_obj_meta(obj->meta_); - obj->meta_ = nullptr; - } -} +// void RTLIL::Design::obj_release_name(RTLIL::AttrObject *obj) +// { +// if (obj->meta_ == nullptr) +// return; +// ObjMeta &m = *obj->meta_; +// if (m.name != Twine::Null) { +// m.name = Twine::Null; +// } +// if (m.src == Twine::Null && m.name == Twine::Null) { +// free_obj_meta(obj->meta_); +// obj->meta_ = nullptr; +// } +// } -void RTLIL::Design::set_src_attribute(RTLIL::AttrObject *obj, const RTLIL::SrcAttr &src) +void RTLIL::Design::set_src_attribute(RTLIL::AttrObject *obj, TwineRef src) { - if (src.empty()) { - obj_set_src_id(obj, Twine::Null); - return; - } - TwineRef new_id = Twine::Null; - if (src.id != Twine::Null) { - // Direct id form — the caller is responsible for keeping the - // slot alive while we retain. obj_set_src_id handles retain. - log_assert(twines.is_alive(src.id) && "set_src_attribute: SrcAttr id points to dead slot"); - new_id = src.id; - obj_set_src_id(obj, new_id); - } else { - // Literal-string form. "@N" → adopt slot directly. Anything else - // → intern as leaf (returns +1, which we release after the retain - // inside obj_set_src_id balances). - new_id = twines.get_ref(src.literal); - if (new_id != Twine::Null) { - log_assert(twines.is_alive(new_id) && "set_src_attribute: @N ref points to dead slot"); - obj_set_src_id(obj, new_id); - } else { - new_id = twines.intern(src.literal); - obj_set_src_id(obj, new_id); - twines.release(new_id); - } - } + obj_set_src_id(obj, src); } std::string RTLIL::Design::get_src_attribute(const RTLIL::AttrObject *obj) const @@ -1131,7 +1106,7 @@ void RTLIL::Design::absorb_attrs(RTLIL::AttrObject *obj, dictsecond.flags & RTLIL::CONST_FLAG_STRING) - set_src_attribute(obj, it->second.decode_string()); + obj_set_src_id(obj, twines.add(Twine{it->second.decode_string()})); buf.erase(it); } obj->attributes = std::move(buf); @@ -1157,7 +1132,6 @@ namespace { } TwineRef new_id = dst_design->twines.copy_from(src_design->twines, src_id); dst_design->obj_set_src_id(dst, new_id); - dst_design->twines.release(new_id); } } @@ -1177,7 +1151,7 @@ void RTLIL::Design::free_obj_meta(RTLIL::ObjMeta *m) { log_assert(m != nullptr); log_assert(m->src == Twine::Null); - log_assert(m->name_id == Twine::Null); + log_assert(m->name == Twine::Null); obj_meta_free_.push_back(m); } @@ -1196,33 +1170,23 @@ void RTLIL::Design::merge_src(RTLIL::AttrObject *target, const RTLIL::AttrObject return; TwineRef merged = twines.concat(std::span{ids}); obj_set_src_id(target, merged); - twines.release(merged); } void RTLIL::Design::merge_src(RTLIL::AttrObject *target, const pool &leaves) { std::vector ids; - std::vector temp_interns; TwineRef tgt_id = obj_src_id(target); if (tgt_id != Twine::Null) ids.push_back(tgt_id); for (const auto &leaf : leaves) { if (leaf.empty()) continue; - TwineRef leaf_id = twines.get_ref(leaf); - if (leaf_id == Twine::Null) { - leaf_id = twines.intern(leaf); - temp_interns.push_back(leaf_id); - } - ids.push_back(leaf_id); + ids.push_back(twines.add(Twine{leaf})); } if (ids.empty()) return; TwineRef merged = twines.concat(std::span{ids}); obj_set_src_id(target, merged); - twines.release(merged); - for (TwineRef id : temp_interns) - twines.release(id); } namespace { @@ -1261,45 +1225,19 @@ namespace { size_t RTLIL::Design::gc_twines() { - size_t before = twines.size(); - if (before == 0) - return 0; - - // Mark phase: every live src_id on any AttrObject is a root. + // Mark phase: every live name and src_id on any AttrObject is a root. pool live; walk_attr_objects(this, [&](const RTLIL::AttrObject *obj) { - TwineRef id = obj_src_id(obj); - if (id != Twine::Null) - live.insert(id); + TwineRef src = obj->meta_->src; + if (src != Twine::Null) + live.insert(src); + TwineRef name = obj->meta_->name; + if (name != Twine::Null) + live.insert(name); }); - // Sweep + compact: rebuild the pool keeping only reachable nodes, - // receiving an old-id -> new-id remap. - dict remap = twines.gc(live); - - // Rewrite every meta-vector src_id through the remap. The pool was - // rebuilt, so the old ids no longer mean anything — we update the - // vector slots directly (bypassing retain/release, which the rebuilt - // pool already accounts for). - walk_attr_objects(this, [&](RTLIL::AttrObject *obj) { - if (obj->meta_ == nullptr) - return; - ObjMeta &m = *obj->meta_; - if (m.src == Twine::Null) - return; - auto it = remap.find(m.src); - if (it == remap.end()) { - m.src = Twine::Null; - if (m.name_id->is_dead()) { - free_obj_meta(obj->meta_); - obj->meta_ = nullptr; - } - return; - } - m.src = it->second; - }); - - return before - twines.size(); + // Sweep: backing refs are stable, so survivors need no remapping. + return twines.gc(live); } pool RTLIL::Design::src_leaves(const RTLIL::AttrObject *obj) const @@ -1476,7 +1414,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) del_list.clear(); for (auto mod_name : selected_modules) { - if (current_design->modules_.count(mod_name) == 0 || (!selects_boxes && boxed_module(mod_name))) + if (current_design->module(mod_name) == nullptr || (!selects_boxes && boxed_module(mod_name))) del_list.push_back(mod_name); selected_members.erase(mod_name); } @@ -1485,7 +1423,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) del_list.clear(); for (auto &it : selected_members) - if (current_design->modules_.count(it.first) == 0 || (!selects_boxes && boxed_module(it.first))) + if (current_design->module(it.first) == nullptr || (!selects_boxes && boxed_module(it.first))) del_list.push_back(it.first); for (auto mod_name : del_list) selected_members.erase(mod_name); @@ -1493,7 +1431,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) for (auto &it : selected_members) { del_list.clear(); for (auto memb_name : it.second) - if (current_design->modules_[it.first]->count_id(memb_name) == 0) + if (current_design->module(it.first)->count_id(memb_name) == 0) del_list.push_back(memb_name); for (auto memb_name : del_list) it.second.erase(memb_name); @@ -1504,8 +1442,8 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) for (auto &it : selected_members) if (it.second.size() == 0) del_list.push_back(it.first); - else if (it.second.size() == current_design->modules_[it.first]->wires_.size() + current_design->modules_[it.first]->memories.size() + - current_design->modules_[it.first]->cells_.size() + current_design->modules_[it.first]->processes.size()) + else if (it.second.size() == current_design->module(it.first)->wires_.size() + current_design->module(it.first)->memories.size() + + current_design->module(it.first)->cells_.size() + current_design->module(it.first)->processes.size()) add_list.push_back(it.first); for (auto mod_name : del_list) selected_members.erase(mod_name); @@ -1565,28 +1503,20 @@ RTLIL::ObjRange RTLIL::Design::modules() return RTLIL::ObjRange(&modules_, &refcount_modules_); } -// RTLIL::Module *RTLIL::Design::module(IdString id) { -// auto t = twines.lookup(id.c_str()); -// if (t) -// return module(t); -// return nullptr; -// } - -const RTLIL::Module *RTLIL::Design::module(IdString id) const { +const RTLIL::Module *RTLIL::Design::module(TwineRef id) const { return modules_.count(id) ? modules_.at(id) : NULL; } +RTLIL::Module *RTLIL::Design::module(TwineRef id) { + return modules_.count(id) ? modules_.at(id) : NULL; +} +const RTLIL::Module *RTLIL::Design::module(IdString id) const { + TwineRef r = twines.lookup(id.str()); + return r == Twine::Null ? NULL : module(r); +} RTLIL::Module *RTLIL::Design::module(IdString id) { - return modules_.count(id) ? modules_.at(id) : NULL; + TwineRef r = twines.lookup(id.str()); + return r == Twine::Null ? NULL : module(r); } -// RTLIL::Module *RTLIL::Design::module(TwineRef name) -// { -// return modules_.count(name) ? modules_.at(name) : NULL; -// } - -// const RTLIL::Module *RTLIL::Design::module(TwineRef name) const -// { -// return modules_.count(name) ? modules_.at(name) : NULL; -// } RTLIL::Module *RTLIL::Design::top_module() const { @@ -1612,19 +1542,19 @@ void RTLIL::Design::add(RTLIL::Binding *binding) RTLIL::Module *RTLIL::Design::addModule(TwineRef name) { if (modules_.count(name) != 0) - log_error("Attempted to add new module named '%s', but a module by that name already exists\n", name); + log_error("Attempted to add new module named '%s', but a module by that name already exists\n", twines.str(name)); log_assert(refcount_modules_ == 0); RTLIL::Module *module = new RTLIL::Module; modules_[name] = module; module->design = this; - module->meta_->name_id = name; + module->meta_->name = name; for (auto mon : monitors) mon->notify_module_add(module); if (yosys_xtrace) { - log("#X# New Module: %s\n", module); + log("#X# New Module: %s\n", twines.str(name)); log_backtrace("-X- ", yosys_xtrace-1); } @@ -1706,23 +1636,23 @@ void RTLIL::Design::remove(RTLIL::Module *module) log_backtrace("-X- ", yosys_xtrace-1); } - log_assert(modules_.at(module->name) == module); + log_assert(modules_.at(module->meta_->name) == module); log_assert(refcount_modules_ == 0); - modules_.erase(module->name); + modules_.erase(module->meta_->name); delete module; } void RTLIL::Design::rename(RTLIL::Module *module, TwineRef new_name) { - modules_.erase(module->name); - module->meta_->name_id = new_name; + modules_.erase(module->meta_->name); + module->meta_->name = new_name; add(module); } void RTLIL::Design::sort() { scratchpad.sort(); - modules_.sort(sort_by_id_str()); + modules_.sort(); for (auto &it : modules_) it.second->sort(); } @@ -1730,7 +1660,7 @@ void RTLIL::Design::sort() void RTLIL::Design::sort_modules() { scratchpad.sort(); - modules_.sort(sort_by_id_str()); + modules_.sort(); } void check_module(RTLIL::Module *module, ParallelDispatchThreadPool &thread_pool); @@ -1745,7 +1675,7 @@ void RTLIL::Design::check() ParallelDispatchThreadPool thread_pool(pool_size); for (auto &it : modules_) { log_assert(this == it.second->design); - log_assert(it.first == it.second->name); + log_assert(it.first == it.second->meta_->name); // log_assert(!it.first.empty()); check_module(it.second, thread_pool); } @@ -1793,12 +1723,12 @@ bool RTLIL::Design::selected_member(TwineRef mod_name, TwineRef memb_name) const bool RTLIL::Design::selected_module(RTLIL::Module *mod) const { - return selected_module(mod->name); + return selected_module(mod->meta_->name); } bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const { - return selected_whole_module(mod->name); + return selected_whole_module(mod->meta_->name); } void RTLIL::Design::push_selection(RTLIL::Selection sel) @@ -1844,7 +1774,7 @@ std::vector RTLIL::Design::selected_modules(RTLIL::SelectPartial bool ignore_wb = (boxes & RTLIL::SB_INCL_WB) != 0; std::vector result; result.reserve(modules_.size()); - for (auto &it : modules_) + for (auto &it : modules_) { if (selected_whole_module(it.first) || (include_partials && selected_module(it.first))) { if (!(exclude_boxes && it.second->get_blackbox_attribute(ignore_wb))) result.push_back(it.second); @@ -1852,22 +1782,22 @@ std::vector RTLIL::Design::selected_modules(RTLIL::SelectPartial switch (boxes) { case RTLIL::SB_UNBOXED_WARN: - log_warning("Ignoring boxed module %s.\n", it.first->unescape()); + log_warning("Ignoring boxed module %s.\n", twines.str(it.first).c_str()); break; case RTLIL::SB_EXCL_BB_WARN: - log_warning("Ignoring blackbox module %s.\n", it.first->unescape()); + log_warning("Ignoring blackbox module %s.\n", twines.str(it.first).c_str()); break; case RTLIL::SB_UNBOXED_ERR: - log_error("Unsupported boxed module %s.\n", it.first->unescape()); + log_error("Unsupported boxed module %s.\n", twines.str(it.first).c_str()); break; case RTLIL::SB_EXCL_BB_ERR: - log_error("Unsupported blackbox module %s.\n", it.first->unescape()); + log_error("Unsupported blackbox module %s.\n", twines.str(it.first).c_str()); break; case RTLIL::SB_UNBOXED_CMDERR: - log_cmd_error("Unsupported boxed module %s.\n", it.first->unescape()); + log_cmd_error("Unsupported boxed module %s.\n", twines.str(it.first).c_str()); break; case RTLIL::SB_EXCL_BB_CMDERR: - log_cmd_error("Unsupported blackbox module %s.\n", it.first->unescape()); + log_cmd_error("Unsupported blackbox module %s.\n", twines.str(it.first).c_str()); break; default: break; @@ -1876,18 +1806,19 @@ std::vector RTLIL::Design::selected_modules(RTLIL::SelectPartial switch(partials) { case RTLIL::SELECT_WHOLE_WARN: - log_warning("Ignoring partially selected module %s.\n", it.first->unescape()); + log_warning("Ignoring partially selected module %s.\n", twines.str(it.first).c_str()); break; case RTLIL::SELECT_WHOLE_ERR: - log_error("Unsupported partially selected module %s.\n", it.first->unescape()); + log_error("Unsupported partially selected module %s.\n", twines.str(it.first).c_str()); break; case RTLIL::SELECT_WHOLE_CMDERR: - log_cmd_error("Unsupported partially selected module %s.\n", it.first->unescape()); + log_cmd_error("Unsupported partially selected module %s.\n", twines.str(it.first).c_str()); break; default: break; } } + } return result; } @@ -1900,7 +1831,7 @@ RTLIL::Module::Module() design = nullptr; refcount_wires_ = 0; refcount_cells_ = 0; - meta_ = ObjMeta(); + meta_ = nullptr; #ifdef YOSYS_ENABLE_PYTHON RTLIL::Module::get_all_modules()->insert(std::pair(hashidx_, this)); @@ -1945,9 +1876,9 @@ void RTLIL::Module::set_src_id(TwineRef id) design->obj_set_src_id(this, id); } -void RTLIL::Module::set_src_attribute(const RTLIL::SrcAttr &src) +void RTLIL::Module::set_src_attribute(TwineRef src) { - if (src.empty() && meta_ == nullptr) + if (src == Twine::Null && meta_ == nullptr) return; log_assert(design && "Module::set_src_attribute requires the module to be attached to a design"); design->set_src_attribute(this, src); @@ -1965,7 +1896,7 @@ std::string RTLIL::Module::get_src_attribute() const return design->get_src_attribute(this); } -void RTLIL::Module::absorb_attrs(dict &&buf) +void RTLIL::Module::absorb_attrs(dict &&buf) { log_assert(design && "Module::absorb_attrs requires the module to be attached to a design"); design->absorb_attrs(this, std::move(buf)); @@ -2005,7 +1936,7 @@ void RTLIL::Module::makeblackbox() set_bool_attribute(ID::blackbox); } -void RTLIL::Module::expand_interfaces(RTLIL::Design *, const dict &) +void RTLIL::Module::expand_interfaces(RTLIL::Design *, const dict &) { log_error("Class doesn't support expand_interfaces (module: `%s')!\n", name.unescape()); } @@ -2015,28 +1946,25 @@ bool RTLIL::Module::reprocess_if_necessary(RTLIL::Design *) return false; } -TwineRef RTLIL::Module::derive(RTLIL::Design*, const dict &, bool mayfail) +RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict &, bool mayfail) { if (mayfail) - return TwineRef(); + return IdString(); log_error("Module `%s' is used with parameters but is not parametric!\n", name.unescape()); } -TwineRef RTLIL::Module::derive(RTLIL::Design*, const dict &, const dict &, const dict &, bool mayfail) +RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict &, const dict &, const dict &, bool mayfail) { if (mayfail) - return TwineRef(); + return IdString(); log_error("Module `%s' is used with parameters but is not parametric!\n", name.unescape()); } size_t RTLIL::Module::count_id(TwineRef id) { - TwineRef tid = design->twines.lookup(id.str()); - size_t n = memories.count(id) + processes.count(id); - if (tid != Twine::Null) - n += wires_.count(tid) + cells_.count(tid); - return n; + IdString sid(design->twines.str(id)); + return wires_.count(id) + cells_.count(id) + memories.count(sid) + processes.count(sid); } #ifndef NDEBUG @@ -2045,7 +1973,8 @@ namespace { { const RTLIL::Module *module; RTLIL::Cell *cell; - pool expected_params, expected_ports; + pool expected_params; + pool expected_ports; InternalCellChecker(const RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { } @@ -2059,7 +1988,7 @@ namespace { cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str()); } - int param(TwineRef name) + int param(IdString name) { auto it = cell->parameters.find(name); if (it == cell->parameters.end()) @@ -2068,7 +1997,7 @@ namespace { return it->second.as_int(); } - int param_bool(TwineRef name) + int param_bool(IdString name) { int v = param(name); if (GetSize(cell->parameters.at(name)) > 32) @@ -2078,7 +2007,7 @@ namespace { return v; } - int param_bool(TwineRef name, bool expected) + int param_bool(IdString name, bool expected) { int v = param_bool(name); if (v != expected) @@ -2086,14 +2015,14 @@ namespace { return v; } - void param_bits(TwineRef name, int width) + void param_bits(IdString name, int width) { param(name); if (GetSize(cell->parameters.at(name)) != width) error(__LINE__); } - std::string param_string(TwineRef name) + std::string param_string(IdString name) { param(name); return cell->parameters.at(name).decode_string(); @@ -2134,16 +2063,16 @@ namespace { return; if (cell->type == ID($buf)) { - port(ID::A, param(ID::WIDTH)); - port(ID::Y, param(ID::WIDTH)); + port(TW::A, param(ID::WIDTH)); + port(TW::Y, param(ID::WIDTH)); check_expected(); return; } if (cell->type.in(ID($not), ID($pos), ID($neg))) { param_bool(ID::A_SIGNED); - port(ID::A, param(ID::A_WIDTH)); - port(ID::Y, param(ID::Y_WIDTH)); + port(TW::A, param(ID::A_WIDTH)); + port(TW::Y, param(ID::Y_WIDTH)); check_expected(); return; } @@ -2151,17 +2080,17 @@ namespace { if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) { param_bool(ID::A_SIGNED); param_bool(ID::B_SIGNED); - port(ID::A, param(ID::A_WIDTH)); - port(ID::B, param(ID::B_WIDTH)); - port(ID::Y, param(ID::Y_WIDTH)); + port(TW::A, param(ID::A_WIDTH)); + port(TW::B, param(ID::B_WIDTH)); + port(TW::Y, param(ID::Y_WIDTH)); check_expected(true); return; } if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) { param_bool(ID::A_SIGNED); - port(ID::A, param(ID::A_WIDTH)); - port(ID::Y, param(ID::Y_WIDTH)); + port(TW::A, param(ID::A_WIDTH)); + port(TW::Y, param(ID::Y_WIDTH)); check_expected(); return; } @@ -2169,9 +2098,9 @@ namespace { if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) { param_bool(ID::A_SIGNED); param_bool(ID::B_SIGNED, /*expected=*/false); - port(ID::A, param(ID::A_WIDTH)); - port(ID::B, param(ID::B_WIDTH)); - port(ID::Y, param(ID::Y_WIDTH)); + port(TW::A, param(ID::A_WIDTH)); + port(TW::B, param(ID::B_WIDTH)); + port(TW::Y, param(ID::Y_WIDTH)); check_expected(/*check_matched_sign=*/false); return; } @@ -2183,9 +2112,9 @@ namespace { param_bool(ID::A_SIGNED); } param_bool(ID::B_SIGNED); - port(ID::A, param(ID::A_WIDTH)); - port(ID::B, param(ID::B_WIDTH)); - port(ID::Y, param(ID::Y_WIDTH)); + port(TW::A, param(ID::A_WIDTH)); + port(TW::B, param(ID::B_WIDTH)); + port(TW::Y, param(ID::Y_WIDTH)); check_expected(/*check_matched_sign=*/false); return; } @@ -2193,9 +2122,9 @@ namespace { if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) { param_bool(ID::A_SIGNED); param_bool(ID::B_SIGNED); - port(ID::A, param(ID::A_WIDTH)); - port(ID::B, param(ID::B_WIDTH)); - port(ID::Y, param(ID::Y_WIDTH)); + port(TW::A, param(ID::A_WIDTH)); + port(TW::B, param(ID::B_WIDTH)); + port(TW::Y, param(ID::Y_WIDTH)); check_expected(true); return; } @@ -2203,28 +2132,28 @@ namespace { if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow))) { param_bool(ID::A_SIGNED); param_bool(ID::B_SIGNED); - port(ID::A, param(ID::A_WIDTH)); - port(ID::B, param(ID::B_WIDTH)); - port(ID::Y, param(ID::Y_WIDTH)); + port(TW::A, param(ID::A_WIDTH)); + port(TW::B, param(ID::B_WIDTH)); + port(TW::Y, param(ID::Y_WIDTH)); check_expected(cell->type != ID($pow)); return; } if (cell->type == ID($fa)) { - port(ID::A, param(ID::WIDTH)); - port(ID::B, param(ID::WIDTH)); - port(ID::C, param(ID::WIDTH)); - port(ID::X, param(ID::WIDTH)); - port(ID::Y, param(ID::WIDTH)); + port(TW::A, param(ID::WIDTH)); + port(TW::B, param(ID::WIDTH)); + port(TW::C, param(ID::WIDTH)); + port(TW::X, param(ID::WIDTH)); + port(TW::Y, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($lcu)) { - port(ID::P, param(ID::WIDTH)); - port(ID::G, param(ID::WIDTH)); - port(ID::CI, 1); - port(ID::CO, param(ID::WIDTH)); + port(TW::P, param(ID::WIDTH)); + port(TW::G, param(ID::WIDTH)); + port(TW::CI, 1); + port(TW::CO, param(ID::WIDTH)); check_expected(); return; } @@ -2232,13 +2161,13 @@ namespace { if (cell->type == ID($alu)) { param_bool(ID::A_SIGNED); param_bool(ID::B_SIGNED); - port(ID::A, param(ID::A_WIDTH)); - port(ID::B, param(ID::B_WIDTH)); - port(ID::CI, 1); - port(ID::BI, 1); - port(ID::X, param(ID::Y_WIDTH)); - port(ID::Y, param(ID::Y_WIDTH)); - port(ID::CO, param(ID::Y_WIDTH)); + port(TW::A, param(ID::A_WIDTH)); + port(TW::B, param(ID::B_WIDTH)); + port(TW::CI, 1); + port(TW::BI, 1); + port(TW::X, param(ID::Y_WIDTH)); + port(TW::Y, param(ID::Y_WIDTH)); + port(TW::CO, param(ID::Y_WIDTH)); check_expected(true); return; } @@ -2246,9 +2175,9 @@ namespace { if (cell->type == ID($macc)) { param(ID::CONFIG); param(ID::CONFIG_WIDTH); - port(ID::A, param(ID::A_WIDTH)); - port(ID::B, param(ID::B_WIDTH)); - port(ID::Y, param(ID::Y_WIDTH)); + port(TW::A, param(ID::A_WIDTH)); + port(TW::B, param(ID::B_WIDTH)); + port(TW::Y, param(ID::Y_WIDTH)); check_expected(); Macc().from_cell(cell); return; @@ -2280,18 +2209,18 @@ namespace { for (int i = 0; i < param(ID::NADDENDS); i++) { c_width_sum += c_width.extract(16 * i, 16).as_int(false); } - port(ID::A, a_width_sum); - port(ID::B, b_width_sum); - port(ID::C, c_width_sum); - port(ID::Y, param(ID::Y_WIDTH)); + port(TW::A, a_width_sum); + port(TW::B, b_width_sum); + port(TW::C, c_width_sum); + port(TW::Y, param(ID::Y_WIDTH)); check_expected(); return; } if (cell->type == ID($logic_not)) { param_bool(ID::A_SIGNED); - port(ID::A, param(ID::A_WIDTH)); - port(ID::Y, param(ID::Y_WIDTH)); + port(TW::A, param(ID::A_WIDTH)); + port(TW::Y, param(ID::Y_WIDTH)); check_expected(); return; } @@ -2299,17 +2228,17 @@ namespace { if (cell->type.in(ID($logic_and), ID($logic_or))) { param_bool(ID::A_SIGNED); param_bool(ID::B_SIGNED); - port(ID::A, param(ID::A_WIDTH)); - port(ID::B, param(ID::B_WIDTH)); - port(ID::Y, param(ID::Y_WIDTH)); + port(TW::A, param(ID::A_WIDTH)); + port(TW::B, param(ID::B_WIDTH)); + port(TW::Y, param(ID::Y_WIDTH)); check_expected(/*check_matched_sign=*/false); return; } if (cell->type == ID($slice)) { param(ID::OFFSET); - port(ID::A, param(ID::A_WIDTH)); - port(ID::Y, param(ID::Y_WIDTH)); + port(TW::A, param(ID::A_WIDTH)); + port(TW::Y, param(ID::Y_WIDTH)); if (param(ID::OFFSET) + param(ID::Y_WIDTH) > param(ID::A_WIDTH)) error(__LINE__); check_expected(); @@ -2317,51 +2246,51 @@ namespace { } if (cell->type == ID($concat)) { - port(ID::A, param(ID::A_WIDTH)); - port(ID::B, param(ID::B_WIDTH)); - port(ID::Y, param(ID::A_WIDTH) + param(ID::B_WIDTH)); + port(TW::A, param(ID::A_WIDTH)); + port(TW::B, param(ID::B_WIDTH)); + port(TW::Y, param(ID::A_WIDTH) + param(ID::B_WIDTH)); check_expected(); return; } if (cell->type == ID($mux)) { - port(ID::A, param(ID::WIDTH)); - port(ID::B, param(ID::WIDTH)); - port(ID::S, 1); - port(ID::Y, param(ID::WIDTH)); + port(TW::A, param(ID::WIDTH)); + port(TW::B, param(ID::WIDTH)); + port(TW::S, 1); + port(TW::Y, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($pmux)) { - port(ID::A, param(ID::WIDTH)); - port(ID::B, param(ID::WIDTH) * param(ID::S_WIDTH)); - port(ID::S, param(ID::S_WIDTH)); - port(ID::Y, param(ID::WIDTH)); + port(TW::A, param(ID::WIDTH)); + port(TW::B, param(ID::WIDTH) * param(ID::S_WIDTH)); + port(TW::S, param(ID::S_WIDTH)); + port(TW::Y, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($bmux)) { - port(ID::A, param(ID::WIDTH) << param(ID::S_WIDTH)); - port(ID::S, param(ID::S_WIDTH)); - port(ID::Y, param(ID::WIDTH)); + port(TW::A, param(ID::WIDTH) << param(ID::S_WIDTH)); + port(TW::S, param(ID::S_WIDTH)); + port(TW::Y, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($demux)) { - port(ID::A, param(ID::WIDTH)); - port(ID::S, param(ID::S_WIDTH)); - port(ID::Y, param(ID::WIDTH) << param(ID::S_WIDTH)); + port(TW::A, param(ID::WIDTH)); + port(TW::S, param(ID::S_WIDTH)); + port(TW::Y, param(ID::WIDTH) << param(ID::S_WIDTH)); check_expected(); return; } if (cell->type == ID($lut)) { param(ID::LUT); - port(ID::A, param(ID::WIDTH)); - port(ID::Y, 1); + port(TW::A, param(ID::WIDTH)); + port(TW::Y, 1); check_expected(); return; } @@ -2369,8 +2298,8 @@ namespace { if (cell->type == ID($sop)) { param(ID::DEPTH); param(ID::TABLE); - port(ID::A, param(ID::WIDTH)); - port(ID::Y, 1); + port(TW::A, param(ID::WIDTH)); + port(TW::Y, 1); check_expected(); return; } @@ -2378,25 +2307,25 @@ namespace { if (cell->type == ID($sr)) { param_bool(ID::SET_POLARITY); param_bool(ID::CLR_POLARITY); - port(ID::SET, param(ID::WIDTH)); - port(ID::CLR, param(ID::WIDTH)); - port(ID::Q, param(ID::WIDTH)); + port(TW::SET, param(ID::WIDTH)); + port(TW::CLR, param(ID::WIDTH)); + port(TW::Q, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($ff)) { - port(ID::D, param(ID::WIDTH)); - port(ID::Q, param(ID::WIDTH)); + port(TW::D, param(ID::WIDTH)); + port(TW::Q, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($dff)) { param_bool(ID::CLK_POLARITY); - port(ID::CLK, 1); - port(ID::D, param(ID::WIDTH)); - port(ID::Q, param(ID::WIDTH)); + port(TW::CLK, 1); + port(TW::D, param(ID::WIDTH)); + port(TW::Q, param(ID::WIDTH)); check_expected(); return; } @@ -2404,10 +2333,10 @@ namespace { if (cell->type == ID($dffe)) { param_bool(ID::CLK_POLARITY); param_bool(ID::EN_POLARITY); - port(ID::CLK, 1); - port(ID::EN, 1); - port(ID::D, param(ID::WIDTH)); - port(ID::Q, param(ID::WIDTH)); + port(TW::CLK, 1); + port(TW::EN, 1); + port(TW::D, param(ID::WIDTH)); + port(TW::Q, param(ID::WIDTH)); check_expected(); return; } @@ -2416,11 +2345,11 @@ namespace { param_bool(ID::CLK_POLARITY); param_bool(ID::SET_POLARITY); param_bool(ID::CLR_POLARITY); - port(ID::CLK, 1); - port(ID::SET, param(ID::WIDTH)); - port(ID::CLR, param(ID::WIDTH)); - port(ID::D, param(ID::WIDTH)); - port(ID::Q, param(ID::WIDTH)); + port(TW::CLK, 1); + port(TW::SET, param(ID::WIDTH)); + port(TW::CLR, param(ID::WIDTH)); + port(TW::D, param(ID::WIDTH)); + port(TW::Q, param(ID::WIDTH)); check_expected(); return; } @@ -2430,12 +2359,12 @@ namespace { param_bool(ID::SET_POLARITY); param_bool(ID::CLR_POLARITY); param_bool(ID::EN_POLARITY); - port(ID::CLK, 1); - port(ID::EN, 1); - port(ID::SET, param(ID::WIDTH)); - port(ID::CLR, param(ID::WIDTH)); - port(ID::D, param(ID::WIDTH)); - port(ID::Q, param(ID::WIDTH)); + port(TW::CLK, 1); + port(TW::EN, 1); + port(TW::SET, param(ID::WIDTH)); + port(TW::CLR, param(ID::WIDTH)); + port(TW::D, param(ID::WIDTH)); + port(TW::Q, param(ID::WIDTH)); check_expected(); return; } @@ -2444,10 +2373,10 @@ namespace { param_bool(ID::CLK_POLARITY); param_bool(ID::ARST_POLARITY); param_bits(ID::ARST_VALUE, param(ID::WIDTH)); - port(ID::CLK, 1); - port(ID::ARST, 1); - port(ID::D, param(ID::WIDTH)); - port(ID::Q, param(ID::WIDTH)); + port(TW::CLK, 1); + port(TW::ARST, 1); + port(TW::D, param(ID::WIDTH)); + port(TW::Q, param(ID::WIDTH)); check_expected(); return; } @@ -2456,10 +2385,10 @@ namespace { param_bool(ID::CLK_POLARITY); param_bool(ID::SRST_POLARITY); param_bits(ID::SRST_VALUE, param(ID::WIDTH)); - port(ID::CLK, 1); - port(ID::SRST, 1); - port(ID::D, param(ID::WIDTH)); - port(ID::Q, param(ID::WIDTH)); + port(TW::CLK, 1); + port(TW::SRST, 1); + port(TW::D, param(ID::WIDTH)); + port(TW::Q, param(ID::WIDTH)); check_expected(); return; } @@ -2469,11 +2398,11 @@ namespace { param_bool(ID::EN_POLARITY); param_bool(ID::SRST_POLARITY); param_bits(ID::SRST_VALUE, param(ID::WIDTH)); - port(ID::CLK, 1); - port(ID::EN, 1); - port(ID::SRST, 1); - port(ID::D, param(ID::WIDTH)); - port(ID::Q, param(ID::WIDTH)); + port(TW::CLK, 1); + port(TW::EN, 1); + port(TW::SRST, 1); + port(TW::D, param(ID::WIDTH)); + port(TW::Q, param(ID::WIDTH)); check_expected(); return; } @@ -2483,11 +2412,11 @@ namespace { param_bool(ID::EN_POLARITY); param_bool(ID::ARST_POLARITY); param_bits(ID::ARST_VALUE, param(ID::WIDTH)); - port(ID::CLK, 1); - port(ID::EN, 1); - port(ID::ARST, 1); - port(ID::D, param(ID::WIDTH)); - port(ID::Q, param(ID::WIDTH)); + port(TW::CLK, 1); + port(TW::EN, 1); + port(TW::ARST, 1); + port(TW::D, param(ID::WIDTH)); + port(TW::Q, param(ID::WIDTH)); check_expected(); return; } @@ -2495,11 +2424,11 @@ namespace { if (cell->type == ID($aldff)) { param_bool(ID::CLK_POLARITY); param_bool(ID::ALOAD_POLARITY); - port(ID::CLK, 1); - port(ID::ALOAD, 1); - port(ID::D, param(ID::WIDTH)); - port(ID::AD, param(ID::WIDTH)); - port(ID::Q, param(ID::WIDTH)); + port(TW::CLK, 1); + port(TW::ALOAD, 1); + port(TW::D, param(ID::WIDTH)); + port(TW::AD, param(ID::WIDTH)); + port(TW::Q, param(ID::WIDTH)); check_expected(); return; } @@ -2508,21 +2437,21 @@ namespace { param_bool(ID::CLK_POLARITY); param_bool(ID::EN_POLARITY); param_bool(ID::ALOAD_POLARITY); - port(ID::CLK, 1); - port(ID::EN, 1); - port(ID::ALOAD, 1); - port(ID::D, param(ID::WIDTH)); - port(ID::AD, param(ID::WIDTH)); - port(ID::Q, param(ID::WIDTH)); + port(TW::CLK, 1); + port(TW::EN, 1); + port(TW::ALOAD, 1); + port(TW::D, param(ID::WIDTH)); + port(TW::AD, param(ID::WIDTH)); + port(TW::Q, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($dlatch)) { param_bool(ID::EN_POLARITY); - port(ID::EN, 1); - port(ID::D, param(ID::WIDTH)); - port(ID::Q, param(ID::WIDTH)); + port(TW::EN, 1); + port(TW::D, param(ID::WIDTH)); + port(TW::Q, param(ID::WIDTH)); check_expected(); return; } @@ -2531,10 +2460,10 @@ namespace { param_bool(ID::EN_POLARITY); param_bool(ID::ARST_POLARITY); param_bits(ID::ARST_VALUE, param(ID::WIDTH)); - port(ID::EN, 1); - port(ID::ARST, 1); - port(ID::D, param(ID::WIDTH)); - port(ID::Q, param(ID::WIDTH)); + port(TW::EN, 1); + port(TW::ARST, 1); + port(TW::D, param(ID::WIDTH)); + port(TW::Q, param(ID::WIDTH)); check_expected(); return; } @@ -2543,11 +2472,11 @@ namespace { param_bool(ID::EN_POLARITY); param_bool(ID::SET_POLARITY); param_bool(ID::CLR_POLARITY); - port(ID::EN, 1); - port(ID::SET, param(ID::WIDTH)); - port(ID::CLR, param(ID::WIDTH)); - port(ID::D, param(ID::WIDTH)); - port(ID::Q, param(ID::WIDTH)); + port(TW::EN, 1); + port(TW::SET, param(ID::WIDTH)); + port(TW::CLR, param(ID::WIDTH)); + port(TW::D, param(ID::WIDTH)); + port(TW::Q, param(ID::WIDTH)); check_expected(); return; } @@ -2563,10 +2492,10 @@ namespace { param_bits(ID::STATE_TABLE, param(ID::STATE_BITS) * param(ID::STATE_NUM)); param(ID::TRANS_NUM); param_bits(ID::TRANS_TABLE, param(ID::TRANS_NUM) * (2*param(ID::STATE_NUM_LOG2) + param(ID::CTRL_IN_WIDTH) + param(ID::CTRL_OUT_WIDTH))); - port(ID::CLK, 1); - port(ID::ARST, 1); - port(ID::CTRL_IN, param(ID::CTRL_IN_WIDTH)); - port(ID::CTRL_OUT, param(ID::CTRL_OUT_WIDTH)); + port(TW::CLK, 1); + port(TW::ARST, 1); + port(TW::CTRL_IN, param(ID::CTRL_IN_WIDTH)); + port(TW::CTRL_OUT, param(ID::CTRL_OUT_WIDTH)); check_expected(); return; } @@ -2576,10 +2505,10 @@ namespace { param_bool(ID::CLK_ENABLE); param_bool(ID::CLK_POLARITY); param_bool(ID::TRANSPARENT); - port(ID::CLK, 1); - port(ID::EN, 1); - port(ID::ADDR, param(ID::ABITS)); - port(ID::DATA, param(ID::WIDTH)); + port(TW::CLK, 1); + port(TW::EN, 1); + port(TW::ADDR, param(ID::ABITS)); + port(TW::DATA, param(ID::WIDTH)); check_expected(); return; } @@ -2594,12 +2523,12 @@ namespace { param_bits(ID::ARST_VALUE, param(ID::WIDTH)); param_bits(ID::SRST_VALUE, param(ID::WIDTH)); param_bits(ID::INIT_VALUE, param(ID::WIDTH)); - port(ID::CLK, 1); - port(ID::EN, 1); - port(ID::ARST, 1); - port(ID::SRST, 1); - port(ID::ADDR, param(ID::ABITS)); - port(ID::DATA, param(ID::WIDTH)); + port(TW::CLK, 1); + port(TW::EN, 1); + port(TW::ARST, 1); + port(TW::SRST, 1); + port(TW::ADDR, param(ID::ABITS)); + port(TW::DATA, param(ID::WIDTH)); check_expected(); return; } @@ -2609,10 +2538,10 @@ namespace { param_bool(ID::CLK_ENABLE); param_bool(ID::CLK_POLARITY); param(ID::PRIORITY); - port(ID::CLK, 1); - port(ID::EN, param(ID::WIDTH)); - port(ID::ADDR, param(ID::ABITS)); - port(ID::DATA, param(ID::WIDTH)); + port(TW::CLK, 1); + port(TW::EN, param(ID::WIDTH)); + port(TW::ADDR, param(ID::ABITS)); + port(TW::DATA, param(ID::WIDTH)); check_expected(); return; } @@ -2623,10 +2552,10 @@ namespace { param_bool(ID::CLK_POLARITY); param(ID::PORTID); param(ID::PRIORITY_MASK); - port(ID::CLK, 1); - port(ID::EN, param(ID::WIDTH)); - port(ID::ADDR, param(ID::ABITS)); - port(ID::DATA, param(ID::WIDTH)); + port(TW::CLK, 1); + port(TW::EN, param(ID::WIDTH)); + port(TW::ADDR, param(ID::ABITS)); + port(TW::DATA, param(ID::WIDTH)); check_expected(); return; } @@ -2634,8 +2563,8 @@ namespace { if (cell->type == ID($meminit)) { param(ID::MEMID); param(ID::PRIORITY); - port(ID::ADDR, param(ID::ABITS)); - port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS)); + port(TW::ADDR, param(ID::ABITS)); + port(TW::DATA, param(ID::WIDTH) * param(ID::WORDS)); check_expected(); return; } @@ -2643,9 +2572,9 @@ namespace { if (cell->type == ID($meminit_v2)) { param(ID::MEMID); param(ID::PRIORITY); - port(ID::ADDR, param(ID::ABITS)); - port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS)); - port(ID::EN, param(ID::WIDTH)); + port(TW::ADDR, param(ID::ABITS)); + port(TW::DATA, param(ID::WIDTH) * param(ID::WORDS)); + port(TW::EN, param(ID::WIDTH)); check_expected(); return; } @@ -2660,14 +2589,14 @@ namespace { param_bits(ID::RD_TRANSPARENT, max(1, param(ID::RD_PORTS))); param_bits(ID::WR_CLK_ENABLE, max(1, param(ID::WR_PORTS))); param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS))); - port(ID::RD_CLK, param(ID::RD_PORTS)); - port(ID::RD_EN, param(ID::RD_PORTS)); - port(ID::RD_ADDR, param(ID::RD_PORTS) * param(ID::ABITS)); - port(ID::RD_DATA, param(ID::RD_PORTS) * param(ID::WIDTH)); - port(ID::WR_CLK, param(ID::WR_PORTS)); - port(ID::WR_EN, param(ID::WR_PORTS) * param(ID::WIDTH)); - port(ID::WR_ADDR, param(ID::WR_PORTS) * param(ID::ABITS)); - port(ID::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH)); + port(TW::RD_CLK, param(ID::RD_PORTS)); + port(TW::RD_EN, param(ID::RD_PORTS)); + port(TW::RD_ADDR, param(ID::RD_PORTS) * param(ID::ABITS)); + port(TW::RD_DATA, param(ID::RD_PORTS) * param(ID::WIDTH)); + port(TW::WR_CLK, param(ID::WR_PORTS)); + port(TW::WR_EN, param(ID::WR_PORTS) * param(ID::WIDTH)); + port(TW::WR_ADDR, param(ID::WR_PORTS) * param(ID::ABITS)); + port(TW::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH)); check_expected(); return; } @@ -2690,75 +2619,75 @@ namespace { param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS))); param_bits(ID::WR_WIDE_CONTINUATION, max(1, param(ID::WR_PORTS))); param_bits(ID::WR_PRIORITY_MASK, max(1, param(ID::WR_PORTS) * param(ID::WR_PORTS))); - port(ID::RD_CLK, param(ID::RD_PORTS)); - port(ID::RD_EN, param(ID::RD_PORTS)); - port(ID::RD_ARST, param(ID::RD_PORTS)); - port(ID::RD_SRST, param(ID::RD_PORTS)); - port(ID::RD_ADDR, param(ID::RD_PORTS) * param(ID::ABITS)); - port(ID::RD_DATA, param(ID::RD_PORTS) * param(ID::WIDTH)); - port(ID::WR_CLK, param(ID::WR_PORTS)); - port(ID::WR_EN, param(ID::WR_PORTS) * param(ID::WIDTH)); - port(ID::WR_ADDR, param(ID::WR_PORTS) * param(ID::ABITS)); - port(ID::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH)); + port(TW::RD_CLK, param(ID::RD_PORTS)); + port(TW::RD_EN, param(ID::RD_PORTS)); + port(TW::RD_ARST, param(ID::RD_PORTS)); + port(TW::RD_SRST, param(ID::RD_PORTS)); + port(TW::RD_ADDR, param(ID::RD_PORTS) * param(ID::ABITS)); + port(TW::RD_DATA, param(ID::RD_PORTS) * param(ID::WIDTH)); + port(TW::WR_CLK, param(ID::WR_PORTS)); + port(TW::WR_EN, param(ID::WR_PORTS) * param(ID::WIDTH)); + port(TW::WR_ADDR, param(ID::WR_PORTS) * param(ID::ABITS)); + port(TW::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($tribuf)) { - port(ID::A, param(ID::WIDTH)); - port(ID::Y, param(ID::WIDTH)); - port(ID::EN, 1); + port(TW::A, param(ID::WIDTH)); + port(TW::Y, param(ID::WIDTH)); + port(TW::EN, 1); check_expected(); return; } if (cell->type == ID($bweqx)) { - port(ID::A, param(ID::WIDTH)); - port(ID::B, param(ID::WIDTH)); - port(ID::Y, param(ID::WIDTH)); + port(TW::A, param(ID::WIDTH)); + port(TW::B, param(ID::WIDTH)); + port(TW::Y, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($bwmux)) { - port(ID::A, param(ID::WIDTH)); - port(ID::B, param(ID::WIDTH)); - port(ID::S, param(ID::WIDTH)); - port(ID::Y, param(ID::WIDTH)); + port(TW::A, param(ID::WIDTH)); + port(TW::B, param(ID::WIDTH)); + port(TW::S, param(ID::WIDTH)); + port(TW::Y, param(ID::WIDTH)); check_expected(); return; } if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) { - port(ID::A, 1); - port(ID::EN, 1); + port(TW::A, 1); + port(TW::EN, 1); check_expected(); return; } if (cell->type == ID($initstate)) { - port(ID::Y, 1); + port(TW::Y, 1); check_expected(); return; } if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) { - port(ID::Y, param(ID::WIDTH)); + port(TW::Y, param(ID::WIDTH)); check_expected(); return; } if (cell->type.in(ID($anyinit))) { - port(ID::D, param(ID::WIDTH)); - port(ID::Q, param(ID::WIDTH)); + port(TW::D, param(ID::WIDTH)); + port(TW::Q, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($equiv)) { - port(ID::A, 1); - port(ID::B, 1); - port(ID::Y, 1); + port(TW::A, 1); + port(TW::B, 1); + port(TW::Y, 1); check_expected(); return; } @@ -2773,15 +2702,15 @@ namespace { param(ID::T_FALL_MIN); param(ID::T_FALL_TYP); param(ID::T_FALL_MAX); - port(ID::EN, 1); - port(ID::SRC, param(ID::SRC_WIDTH)); - port(ID::DST, param(ID::DST_WIDTH)); + port(TW::EN, 1); + port(TW::SRC, param(ID::SRC_WIDTH)); + port(TW::DST, param(ID::DST_WIDTH)); if (cell->type == ID($specify3)) { param_bool(ID::EDGE_EN); param_bool(ID::EDGE_POL); param_bool(ID::DAT_DST_PEN); param_bool(ID::DAT_DST_POL); - port(ID::DAT, param(ID::DST_WIDTH)); + port(TW::DAT, param(ID::DST_WIDTH)); } check_expected(); return; @@ -2799,10 +2728,10 @@ namespace { param(ID::T_LIMIT2_MIN); param(ID::T_LIMIT2_TYP); param(ID::T_LIMIT2_MAX); - port(ID::SRC_EN, 1); - port(ID::DST_EN, 1); - port(ID::SRC, param(ID::SRC_WIDTH)); - port(ID::DST, param(ID::DST_WIDTH)); + port(TW::SRC_EN, 1); + port(TW::DST_EN, 1); + port(TW::SRC, param(ID::SRC_WIDTH)); + port(TW::DST, param(ID::DST_WIDTH)); check_expected(); return; } @@ -2812,9 +2741,9 @@ namespace { param_bool(ID::TRG_ENABLE); param(ID::TRG_POLARITY); param(ID::PRIORITY); - port(ID::EN, 1); - port(ID::TRG, param(ID::TRG_WIDTH)); - port(ID::ARGS, param(ID::ARGS_WIDTH)); + port(TW::EN, 1); + port(TW::TRG, param(ID::TRG_WIDTH)); + port(TW::ARGS, param(ID::ARGS_WIDTH)); check_expected(); return; } @@ -2827,10 +2756,10 @@ namespace { param_bool(ID::TRG_ENABLE); param(ID::TRG_POLARITY); param(ID::PRIORITY); - port(ID::A, 1); - port(ID::EN, 1); - port(ID::TRG, param(ID::TRG_WIDTH)); - port(ID::ARGS, param(ID::ARGS_WIDTH)); + port(TW::A, 1); + port(TW::EN, 1); + port(TW::TRG, param(ID::TRG_WIDTH)); + port(TW::ARGS, param(ID::ARGS_WIDTH)); check_expected(); return; } @@ -2844,77 +2773,77 @@ namespace { return; } - if (cell->type == ID($_BUF_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_NOT_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_AND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_NAND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_OR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_NOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_XOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_XNOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_ANDNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_ORNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_MUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_NMUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_AOI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_OAI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_AOI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_OAI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_BUF_)) { port(TW::A,1); port(TW::Y,1); check_expected(); return; } + if (cell->type == ID($_NOT_)) { port(TW::A,1); port(TW::Y,1); check_expected(); return; } + if (cell->type == ID($_AND_)) { port(TW::A,1); port(TW::B,1); port(TW::Y,1); check_expected(); return; } + if (cell->type == ID($_NAND_)) { port(TW::A,1); port(TW::B,1); port(TW::Y,1); check_expected(); return; } + if (cell->type == ID($_OR_)) { port(TW::A,1); port(TW::B,1); port(TW::Y,1); check_expected(); return; } + if (cell->type == ID($_NOR_)) { port(TW::A,1); port(TW::B,1); port(TW::Y,1); check_expected(); return; } + if (cell->type == ID($_XOR_)) { port(TW::A,1); port(TW::B,1); port(TW::Y,1); check_expected(); return; } + if (cell->type == ID($_XNOR_)) { port(TW::A,1); port(TW::B,1); port(TW::Y,1); check_expected(); return; } + if (cell->type == ID($_ANDNOT_)) { port(TW::A,1); port(TW::B,1); port(TW::Y,1); check_expected(); return; } + if (cell->type == ID($_ORNOT_)) { port(TW::A,1); port(TW::B,1); port(TW::Y,1); check_expected(); return; } + if (cell->type == ID($_MUX_)) { port(TW::A,1); port(TW::B,1); port(TW::S,1); port(TW::Y,1); check_expected(); return; } + if (cell->type == ID($_NMUX_)) { port(TW::A,1); port(TW::B,1); port(TW::S,1); port(TW::Y,1); check_expected(); return; } + if (cell->type == ID($_AOI3_)) { port(TW::A,1); port(TW::B,1); port(TW::C,1); port(TW::Y,1); check_expected(); return; } + if (cell->type == ID($_OAI3_)) { port(TW::A,1); port(TW::B,1); port(TW::C,1); port(TW::Y,1); check_expected(); return; } + if (cell->type == ID($_AOI4_)) { port(TW::A,1); port(TW::B,1); port(TW::C,1); port(TW::D,1); port(TW::Y,1); check_expected(); return; } + if (cell->type == ID($_OAI4_)) { port(TW::A,1); port(TW::B,1); port(TW::C,1); port(TW::D,1); port(TW::Y,1); check_expected(); return; } - if (cell->type == ID($_TBUF_)) { port(ID::A,1); port(ID::Y,1); port(ID::E,1); check_expected(); return; } + if (cell->type == ID($_TBUF_)) { port(TW::A,1); port(TW::Y,1); port(TW::E,1); check_expected(); return; } - if (cell->type == ID($_MUX4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::S,1); port(ID::T,1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_MUX8_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_MUX16_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::I,1); port(ID::J,1); port(ID::K,1); port(ID::L,1); port(ID::M,1); port(ID::N,1); port(ID::O,1); port(ID::P,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::V,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_MUX4_)) { port(TW::A,1); port(TW::B,1); port(TW::C,1); port(TW::D,1); port(TW::S,1); port(TW::T,1); port(TW::Y,1); check_expected(); return; } + if (cell->type == ID($_MUX8_)) { port(TW::A,1); port(TW::B,1); port(TW::C,1); port(TW::D,1); port(TW::E,1); port(TW::F,1); port(TW::G,1); port(TW::H,1); port(TW::S,1); port(TW::T,1); port(TW::U,1); port(TW::Y,1); check_expected(); return; } + if (cell->type == ID($_MUX16_)) { port(TW::A,1); port(TW::B,1); port(TW::C,1); port(TW::D,1); port(TW::E,1); port(TW::F,1); port(TW::G,1); port(TW::H,1); port(TW::I,1); port(TW::J,1); port(TW::K,1); port(TW::L,1); port(TW::M,1); port(TW::N,1); port(TW::O,1); port(TW::P,1); port(TW::S,1); port(TW::T,1); port(TW::U,1); port(TW::V,1); port(TW::Y,1); check_expected(); return; } if (cell->type.in(ID($_SR_NN_), ID($_SR_NP_), ID($_SR_PN_), ID($_SR_PP_))) - { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; } + { port(TW::S,1); port(TW::R,1); port(TW::Q,1); check_expected(); return; } - if (cell->type == ID($_FF_)) { port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_FF_)) { port(TW::D,1); port(TW::Q,1); check_expected(); return; } if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) - { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; } + { port(TW::D,1); port(TW::Q,1); port(TW::C,1); check_expected(); return; } if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) - { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; } + { port(TW::D,1); port(TW::Q,1); port(TW::C,1); port(TW::E,1); check_expected(); return; } if (cell->type.in( ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_), ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_))) - { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; } + { port(TW::D,1); port(TW::Q,1); port(TW::C,1); port(TW::R,1); check_expected(); return; } if (cell->type.in( ID($_DFFE_NN0N_), ID($_DFFE_NN0P_), ID($_DFFE_NN1N_), ID($_DFFE_NN1P_), ID($_DFFE_NP0N_), ID($_DFFE_NP0P_), ID($_DFFE_NP1N_), ID($_DFFE_NP1P_), ID($_DFFE_PN0N_), ID($_DFFE_PN0P_), ID($_DFFE_PN1N_), ID($_DFFE_PN1P_), ID($_DFFE_PP0N_), ID($_DFFE_PP0P_), ID($_DFFE_PP1N_), ID($_DFFE_PP1P_))) - { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); port(ID::E,1); check_expected(); return; } + { port(TW::D,1); port(TW::Q,1); port(TW::C,1); port(TW::R,1); port(TW::E,1); check_expected(); return; } if (cell->type.in( ID($_ALDFF_NN_), ID($_ALDFF_NP_), ID($_ALDFF_PN_), ID($_ALDFF_PP_))) - { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::L,1); port(ID::AD,1); check_expected(); return; } + { port(TW::D,1); port(TW::Q,1); port(TW::C,1); port(TW::L,1); port(TW::AD,1); check_expected(); return; } if (cell->type.in( ID($_ALDFFE_NNN_), ID($_ALDFFE_NNP_), ID($_ALDFFE_NPN_), ID($_ALDFFE_NPP_), ID($_ALDFFE_PNN_), ID($_ALDFFE_PNP_), ID($_ALDFFE_PPN_), ID($_ALDFFE_PPP_))) - { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::L,1); port(ID::AD,1); port(ID::E,1); check_expected(); return; } + { port(TW::D,1); port(TW::Q,1); port(TW::C,1); port(TW::L,1); port(TW::AD,1); port(TW::E,1); check_expected(); return; } if (cell->type.in( ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_), ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_))) - { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + { port(TW::C,1); port(TW::S,1); port(TW::R,1); port(TW::D,1); port(TW::Q,1); check_expected(); return; } if (cell->type.in( ID($_DFFSRE_NNNN_), ID($_DFFSRE_NNNP_), ID($_DFFSRE_NNPN_), ID($_DFFSRE_NNPP_), ID($_DFFSRE_NPNN_), ID($_DFFSRE_NPNP_), ID($_DFFSRE_NPPN_), ID($_DFFSRE_NPPP_), ID($_DFFSRE_PNNN_), ID($_DFFSRE_PNNP_), ID($_DFFSRE_PNPN_), ID($_DFFSRE_PNPP_), ID($_DFFSRE_PPNN_), ID($_DFFSRE_PPNP_), ID($_DFFSRE_PPPN_), ID($_DFFSRE_PPPP_))) - { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::E,1); port(ID::Q,1); check_expected(); return; } + { port(TW::C,1); port(TW::S,1); port(TW::R,1); port(TW::D,1); port(TW::E,1); port(TW::Q,1); check_expected(); return; } if (cell->type.in( ID($_SDFF_NN0_), ID($_SDFF_NN1_), ID($_SDFF_NP0_), ID($_SDFF_NP1_), ID($_SDFF_PN0_), ID($_SDFF_PN1_), ID($_SDFF_PP0_), ID($_SDFF_PP1_))) - { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; } + { port(TW::D,1); port(TW::Q,1); port(TW::C,1); port(TW::R,1); check_expected(); return; } if (cell->type.in( ID($_SDFFE_NN0N_), ID($_SDFFE_NN0P_), ID($_SDFFE_NN1N_), ID($_SDFFE_NN1P_), @@ -2925,71 +2854,71 @@ namespace { ID($_SDFFCE_NP0N_), ID($_SDFFCE_NP0P_), ID($_SDFFCE_NP1N_), ID($_SDFFCE_NP1P_), ID($_SDFFCE_PN0N_), ID($_SDFFCE_PN0P_), ID($_SDFFCE_PN1N_), ID($_SDFFCE_PN1P_), ID($_SDFFCE_PP0N_), ID($_SDFFCE_PP0P_), ID($_SDFFCE_PP1N_), ID($_SDFFCE_PP1P_))) - { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); port(ID::E,1); check_expected(); return; } + { port(TW::D,1); port(TW::Q,1); port(TW::C,1); port(TW::R,1); port(TW::E,1); check_expected(); return; } if (cell->type.in(ID($_DLATCH_N_), ID($_DLATCH_P_))) - { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + { port(TW::E,1); port(TW::D,1); port(TW::Q,1); check_expected(); return; } if (cell->type.in( ID($_DLATCH_NN0_), ID($_DLATCH_NN1_), ID($_DLATCH_NP0_), ID($_DLATCH_NP1_), ID($_DLATCH_PN0_), ID($_DLATCH_PN1_), ID($_DLATCH_PP0_), ID($_DLATCH_PP1_))) - { port(ID::E,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + { port(TW::E,1); port(TW::R,1); port(TW::D,1); port(TW::Q,1); check_expected(); return; } if (cell->type.in( ID($_DLATCHSR_NNN_), ID($_DLATCHSR_NNP_), ID($_DLATCHSR_NPN_), ID($_DLATCHSR_NPP_), ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_))) - { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + { port(TW::E,1); port(TW::S,1); port(TW::R,1); port(TW::D,1); port(TW::Q,1); check_expected(); return; } if (cell->type.in(ID($set_tag))) { param(ID::WIDTH); param(ID::TAG); - port(ID::A, param(ID::WIDTH)); - port(ID::SET, param(ID::WIDTH)); - port(ID::CLR, param(ID::WIDTH)); - port(ID::Y, param(ID::WIDTH)); + port(TW::A, param(ID::WIDTH)); + port(TW::SET, param(ID::WIDTH)); + port(TW::CLR, param(ID::WIDTH)); + port(TW::Y, param(ID::WIDTH)); check_expected(); return; } if (cell->type.in(ID($get_tag),ID($original_tag))) { param(ID::WIDTH); param(ID::TAG); - port(ID::A, param(ID::WIDTH)); - port(ID::Y, param(ID::WIDTH)); + port(TW::A, param(ID::WIDTH)); + port(TW::Y, param(ID::WIDTH)); check_expected(); return; } if (cell->type.in(ID($overwrite_tag))) { param(ID::WIDTH); param(ID::TAG); - port(ID::A, param(ID::WIDTH)); - port(ID::SET, param(ID::WIDTH)); - port(ID::CLR, param(ID::WIDTH)); + port(TW::A, param(ID::WIDTH)); + port(TW::SET, param(ID::WIDTH)); + port(TW::CLR, param(ID::WIDTH)); check_expected(); return; } if (cell->type.in(ID($future_ff))) { param(ID::WIDTH); - port(ID::A, param(ID::WIDTH)); - port(ID::Y, param(ID::WIDTH)); + port(TW::A, param(ID::WIDTH)); + port(TW::Y, param(ID::WIDTH)); check_expected(); return; } if (cell->type.in(ID($input_port))) { param(ID::WIDTH); - port(ID::Y, param(ID::WIDTH)); + port(TW::Y, param(ID::WIDTH)); check_expected(); return; } if (cell->type.in(ID($output_port), ID($public))) { param(ID::WIDTH); - port(ID::A, param(ID::WIDTH)); + port(TW::A, param(ID::WIDTH)); check_expected(); return; } if (cell->type.in(ID($connect))) { param(ID::WIDTH); - port(ID::A, param(ID::WIDTH)); - port(ID::B, param(ID::WIDTH)); + port(TW::A, param(ID::WIDTH)); + port(TW::B, param(ID::WIDTH)); check_expected(); return; } @@ -3055,11 +2984,11 @@ void check_module(RTLIL::Module *module, ParallelDispatchThreadPool &thread_pool for (int i : ctx.item_range(const_module->cells_size())) { auto it = *const_module->cells_.element(i); log_assert(const_module == it.second->module); - log_assert(it.second->meta_ && it.first == it.second->meta_->name_id); + log_assert(it.second->meta_ && it.first == it.second->meta_->name); log_assert(it.first != Twine::Null); log_assert(!it.second->type.empty()); for (auto &it2 : it.second->connections()) { - log_assert(!it2.first.empty()); + log_assert(it2.first != Twine::Null); it2.second.check(const_module); } for (auto &it2 : it.second->attributes) @@ -3075,7 +3004,7 @@ void check_module(RTLIL::Module *module, ParallelDispatchThreadPool &thread_pool log_assert(!memory_strings.count(memid)); memids.insert(ctx, std::move(memid)); } - auto cell_mod = const_module->design->module(TwineRef(it.second->name)); + auto cell_mod = const_module->design->module(it.second->meta_->name); if (cell_mod != nullptr) { // assertion check below to make sure that there are no // cases where a cell has a blackbox attribute since @@ -3094,7 +3023,7 @@ void check_module(RTLIL::Module *module, ParallelDispatchThreadPool &thread_pool for (int i : ctx.item_range(const_module->wires_size())) { auto it = *const_module->wires_.element(i); log_assert(const_module == it.second->module); - log_assert(it.second->meta_ && it.first == it.second->meta_->name_id); + log_assert(it.second->meta_ && it.first == it.second->meta_->name); log_assert(it.first != Twine::Null); log_assert(it.second->width >= 0); log_assert(it.second->port_id >= 0); @@ -3102,7 +3031,7 @@ void check_module(RTLIL::Module *module, ParallelDispatchThreadPool &thread_pool log_assert(!it2.first.empty()); if (it.second->port_id) { log_assert(GetSize(const_module->ports) >= it.second->port_id); - log_assert(const_module->ports.at(it.second->port_id-1) == TwineRef(it.second->name)); + log_assert(const_module->ports.at(it.second->port_id-1) == it.second->meta_->name); log_assert(it.second->port_input || it.second->port_output); log_assert(it.second->port_id <= GetSize(ports_declared)); bool previously_declared = ports_declared[it.second->port_id-1].set_and_return_old(); @@ -3213,26 +3142,25 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod, bool src_id_verbatim) cons if (src_id_verbatim) { // Per-AttrObject meta clone via dst design's pool. TwineRefs for // src attributes transfer verbatim (twines was wholesale-copied). - // name_id is re-interned by addWire/addCell; copy_meta restores it. + // name is re-interned by addWire/addCell; copy_meta restores it. auto copy_meta = [&](const RTLIL::AttrObject *src_obj, RTLIL::AttrObject *dst_obj) { if (!src_obj->meta_ || !new_mod->design) return; - // Preserve name_id already set by addWire/addCell (in dst's pool). - TwineRef saved_name_id = dst_obj->meta_ ? dst_obj->meta_->name_id : Twine::Null; - // Recycle old meta slot (no field releases — name_id's retain lives on). + // Preserve name already set by addWire/addCell (in dst's pool). + TwineRef saved_name = dst_obj->meta_ ? dst_obj->meta_->name : Twine::Null; + // Recycle old meta slot (no field releases — name's retain lives on). if (dst_obj->meta_) new_mod->design->free_obj_meta(dst_obj->meta_); - // Alloc new meta and struct-copy (src field is valid; name_id from + // Alloc new meta and struct-copy (src field is valid; name from // src pool is stale and will be overwritten). dst_obj->meta_ = new_mod->design->alloc_obj_meta(); *dst_obj->meta_ = *src_obj->meta_; - dst_obj->meta_->name_id = saved_name_id; + dst_obj->meta_->name = saved_name; }; for (auto it = wires_.rbegin(); it != wires_.rend(); ++it) { const RTLIL::Wire *o = it->second; - TwineRef dst_name_id = new_mod->design->twines.copy_from(design->twines, it->first); - RTLIL::Wire *w = new_mod->addWire(dst_name_id, o->width); - new_mod->design->twines.release(dst_name_id); + TwineRef dst_name = new_mod->design->twines.copy_from(design->twines, it->first); + RTLIL::Wire *w = new_mod->addWire(dst_name, o->width); w->start_offset = o->start_offset; w->port_id = o->port_id; w->port_input = o->port_input; @@ -3253,9 +3181,8 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod, bool src_id_verbatim) cons } for (auto it = cells_.rbegin(); it != cells_.rend(); ++it) { const RTLIL::Cell *o = it->second; - TwineRef dst_name_id = new_mod->design->twines.copy_from(design->twines, it->first); - RTLIL::Cell *c = new_mod->addCell(dst_name_id, o->type); - new_mod->design->twines.release(dst_name_id); + TwineRef dst_name = new_mod->design->twines.copy_from(design->twines, it->first); + RTLIL::Cell *c = new_mod->addCell(dst_name, o->type); c->connections_ = o->connections_; c->parameters = o->parameters; c->attributes = o->attributes; @@ -3307,7 +3234,6 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod, bool src_id_verbatim) cons for (auto it = wires_.rbegin(); it != wires_.rend(); ++it) { TwineRef dst_id = new_mod->design->twines.copy_from(design->twines, it->first); new_mod->addWire(dst_id, it->second); - new_mod->design->twines.release(dst_id); } for (auto it = memories.rbegin(); it != memories.rend(); ++it) @@ -3316,7 +3242,6 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod, bool src_id_verbatim) cons for (auto it = cells_.rbegin(); it != cells_.rend(); ++it) { TwineRef dst_id = new_mod->design->twines.copy_from(design->twines, it->first); new_mod->addCell(dst_id, it->second); - new_mod->design->twines.release(dst_id); } for (auto it = processes.rbegin(); it != processes.rend(); ++it) @@ -3332,7 +3257,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod, bool src_id_verbatim) cons // wire points to original module; look up by name in new module. // Use the IdString materialisation path: works for both same-design // and cross-design clones without assuming pool identity. - wire = mod->wire(TwineRef(wire->name)); + wire = mod->wire(wire->meta_->name); }); } }; @@ -3362,7 +3287,7 @@ RTLIL::Module *RTLIL::Module::clone(RTLIL::Design *dst, bool src_id_verbatim) co return new_mod; } -RTLIL::Module *RTLIL::Module::clone(RTLIL::Design *dst, TwineRef target_name, bool src_id_verbatim) const +RTLIL::Module *RTLIL::Module::clone(RTLIL::Design *dst, RTLIL::IdString target_name, bool src_id_verbatim) const { RTLIL::Module *new_mod = new RTLIL::Module; new_mod->design = dst; @@ -3398,12 +3323,12 @@ bool RTLIL::Module::has_processes_warn() const bool RTLIL::Module::is_selected() const { - return design->selected_module(this->name); + return design->selected_module(this->meta_->name); } bool RTLIL::Module::is_selected_whole() const { - return design->selected_whole_module(this->name); + return design->selected_whole_module(this->meta_->name); } std::vector RTLIL::Module::selected_wires() const @@ -3462,8 +3387,8 @@ std::vector RTLIL::Module::selected_members() const void RTLIL::Module::add(RTLIL::Wire *wire) { - log_assert(wire->meta_ && wire->meta_->name_id != Twine::Null); - TwineRef id = wire->meta_->name_id; + log_assert(wire->meta_ && wire->meta_->name != Twine::Null); + TwineRef id = wire->meta_->name; log_assert(wires_.count(id) == 0); log_assert(refcount_wires_ == 0); wires_[id] = wire; @@ -3472,8 +3397,8 @@ void RTLIL::Module::add(RTLIL::Wire *wire) void RTLIL::Module::add(RTLIL::Cell *cell) { - log_assert(cell->meta_ && cell->meta_->name_id != Twine::Null); - TwineRef id = cell->meta_->name_id; + log_assert(cell->meta_ && cell->meta_->name != Twine::Null); + TwineRef id = cell->meta_->name; log_assert(cells_.count(id) == 0); log_assert(refcount_cells_ == 0); cells_[id] = cell; @@ -3483,7 +3408,7 @@ void RTLIL::Module::add(RTLIL::Cell *cell) void RTLIL::Module::add(RTLIL::Process *process) { log_assert(!process->name.empty()); - log_assert(count_id(process->name) == 0); + log_assert(count_id(design->twines.lookup(process->name.str())) == 0); processes[process->name] = process; process->module = this; // Propagate module back-pointer to every CaseRule/SwitchRule in the @@ -3516,7 +3441,7 @@ void RTLIL::Module::remove(const pool &wires) void operator()(RTLIL::SigSpec &sig) { sig.rewrite_wires([this](RTLIL::Wire *&wire) { if (wires_p->count(wire)) - wire = module->addWire(stringf("$delete_wire$%d", autoidx++), wire->width); + wire = module->addWire(Twine{stringf("$delete_wire$%d", (int)autoidx++)}, wire->width); }); } @@ -3541,11 +3466,11 @@ void RTLIL::Module::remove(const pool &wires) } for (auto &it : wires) { - log_assert(it->meta_ && it->meta_->name_id != Twine::Null); - TwineRef id = it->meta_->name_id; + log_assert(it->meta_ && it->meta_->name != Twine::Null); + TwineRef id = it->meta_->name; log_assert(wires_.count(id) != 0); wires_.erase(id); - delete it; // Wire::~Wire releases src and name_id + delete it; // Wire::~Wire releases src and name } } @@ -3565,33 +3490,30 @@ void RTLIL::Module::remove(RTLIL::Process *process) void RTLIL::Module::rename(RTLIL::Wire *wire, TwineRef new_name) { - log_assert(wire->meta_ && wire->meta_->name_id != Twine::Null); - TwineRef old_id = wire->meta_->name_id; + log_assert(wire->meta_ && wire->meta_->name != Twine::Null); + TwineRef old_id = wire->meta_->name; log_assert(wires_[old_id] == wire); log_assert(refcount_wires_ == 0); wires_.erase(old_id); - TwineRef new_id = design->twines.intern(new_name.str()); - design->obj_set_name_id(wire, new_id); - design->twines.release(new_id); + wire->meta_->name = new_name; + // design->obj_set_name(wire, new_name); add(wire); } void RTLIL::Module::rename(RTLIL::Cell *cell, TwineRef new_name) { - log_assert(cell->meta_ && cell->meta_->name_id != Twine::Null); - TwineRef old_id = cell->meta_->name_id; + log_assert(cell->meta_ && cell->meta_->name != Twine::Null); + TwineRef old_id = cell->meta_->name; log_assert(cells_[old_id] == cell); log_assert(refcount_cells_ == 0); cells_.erase(old_id); - TwineRef new_id = design->twines.intern(new_name.str()); - design->obj_set_name_id(cell, new_id); - design->twines.release(new_id); + cell->meta_->name = new_name; add(cell); } void RTLIL::Module::rename(TwineRef old_name, TwineRef new_name) { - TwineRef old_id = design->twines.lookup(old_name.str()); + TwineRef old_id = old_name; if (old_id != Twine::Null && wires_.count(old_id)) rename(wires_.at(old_id), new_name); else if (old_id != Twine::Null && cells_.count(old_id)) @@ -3602,34 +3524,34 @@ void RTLIL::Module::rename(TwineRef old_name, TwineRef new_name) void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2) { - log_assert(w1->meta_ && w1->meta_->name_id != Twine::Null); - log_assert(w2->meta_ && w2->meta_->name_id != Twine::Null); - TwineRef id1 = w1->meta_->name_id; - TwineRef id2 = w2->meta_->name_id; + log_assert(w1->meta_ && w1->meta_->name != Twine::Null); + log_assert(w2->meta_ && w2->meta_->name != Twine::Null); + TwineRef id1 = w1->meta_->name; + TwineRef id2 = w2->meta_->name; log_assert(wires_[id1] == w1); log_assert(wires_[id2] == w2); log_assert(refcount_wires_ == 0); - // Swap dict entries and name_ids; refcounts don't change. + // Swap dict entries and names; refcounts don't change. wires_[id1] = w2; wires_[id2] = w1; - std::swap(w1->meta_->name_id, w2->meta_->name_id); + std::swap(w1->meta_->name, w2->meta_->name); } void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2) { - log_assert(c1->meta_ && c1->meta_->name_id != Twine::Null); - log_assert(c2->meta_ && c2->meta_->name_id != Twine::Null); - TwineRef id1 = c1->meta_->name_id; - TwineRef id2 = c2->meta_->name_id; + log_assert(c1->meta_ && c1->meta_->name != Twine::Null); + log_assert(c2->meta_ && c2->meta_->name != Twine::Null); + TwineRef id1 = c1->meta_->name; + TwineRef id2 = c2->meta_->name; log_assert(cells_[id1] == c1); log_assert(cells_[id2] == c2); log_assert(refcount_cells_ == 0); - // Swap dict entries and name_ids; refcounts don't change. + // Swap dict entries and names; refcounts don't change. cells_[id1] = c2; cells_[id2] = c1; - std::swap(c1->meta_->name_id, c2->meta_->name_id); + std::swap(c1->meta_->name, c2->meta_->name); } TwineRef RTLIL::Module::uniquify(TwineRef name) @@ -3647,7 +3569,7 @@ TwineRef RTLIL::Module::uniquify(TwineRef name, int &index) } while (1) { - TwineRef new_name = stringf("%s_%d", name, index); + TwineRef new_name = design->twines.add(Twine{Twine::Suffix{name, stringf("_%d", index)}}); if (count_id(new_name) == 0) return new_name; index++; @@ -3725,7 +3647,7 @@ void RTLIL::Module::fixup_ports() ports.clear(); for (size_t i = 0; i < all_ports.size(); i++) { - ports.push_back(all_ports[i]->name); + ports.push_back(all_ports[i]->meta_->name); all_ports[i]->port_id = i+1; } } @@ -3735,18 +3657,15 @@ RTLIL::Wire *RTLIL::Module::addWire(TwineRef name, int width) log_assert(design); RTLIL::Wire *wire = new RTLIL::Wire(Wire::ConstructToken{}); wire->width = width; - design->obj_set_name_id(wire, name); + wire->meta_->name = name; add(wire); return wire; } -RTLIL::Wire *RTLIL::Module::addWire(TwineRef name, int width) +RTLIL::Wire *RTLIL::Module::addWire(Twine &&name, int width) { log_assert(design); - TwineRef id = design->twines.intern(name.str()); - RTLIL::Wire *wire = addWire(id, width); - design->twines.release(id); - return wire; + return addWire(design->twines.add(std::move(name)), width); } RTLIL::Wire *RTLIL::Module::addWire(TwineRef name, const RTLIL::Wire *other) @@ -3768,32 +3687,26 @@ RTLIL::Wire *RTLIL::Module::addWire(TwineRef name, const RTLIL::Wire *other) return wire; } -RTLIL::Wire *RTLIL::Module::addWire(TwineRef name, const RTLIL::Wire *other) +RTLIL::Wire *RTLIL::Module::addWire(Twine &&name, const RTLIL::Wire *other) { log_assert(design); - TwineRef id = design->twines.intern(name.str()); - RTLIL::Wire *wire = addWire(id, other); - design->twines.release(id); - return wire; + return addWire(design->twines.add(std::move(name)), other); } -RTLIL::Cell *RTLIL::Module::addCell(TwineRef name, TwineRef type) +RTLIL::Cell *RTLIL::Module::addCell(TwineRef name, IdString type) { log_assert(design); RTLIL::Cell *cell = new RTLIL::Cell(Cell::ConstructToken{}); cell->type = type; - design->obj_set_name_id(cell, name); + cell->meta_->name = name; add(cell); return cell; } -RTLIL::Cell *RTLIL::Module::addCell(TwineRef name, TwineRef type) +RTLIL::Cell *RTLIL::Module::addCell(Twine &&name, IdString type) { log_assert(design); - TwineRef id = design->twines.intern(name.str()); - RTLIL::Cell *cell = addCell(id, type); - design->twines.release(id); - return cell; + return addCell(design->twines.add(std::move(name)), type); } RTLIL::Cell *RTLIL::Module::addCell(TwineRef name, const RTLIL::Cell *other) @@ -3810,16 +3723,13 @@ RTLIL::Cell *RTLIL::Module::addCell(TwineRef name, const RTLIL::Cell *other) return cell; } -RTLIL::Cell *RTLIL::Module::addCell(TwineRef name, const RTLIL::Cell *other) +RTLIL::Cell *RTLIL::Module::addCell(Twine &&name, const RTLIL::Cell *other) { log_assert(design); - TwineRef id = design->twines.intern(name.str()); - RTLIL::Cell *cell = addCell(id, other); - design->twines.release(id); - return cell; + return addCell(design->twines.add(std::move(name)), other); } -RTLIL::Memory *RTLIL::Module::addMemory(TwineRef name) +RTLIL::Memory *RTLIL::Module::addMemory(IdString name) { RTLIL::Memory *mem = new RTLIL::Memory; mem->name = std::move(name); @@ -3828,7 +3738,7 @@ RTLIL::Memory *RTLIL::Module::addMemory(TwineRef name) return mem; } -RTLIL::Memory *RTLIL::Module::addMemory(TwineRef name, const RTLIL::Memory *other) +RTLIL::Memory *RTLIL::Module::addMemory(IdString name, const RTLIL::Memory *other) { RTLIL::Memory *mem = new RTLIL::Memory; mem->name = std::move(name); @@ -3847,7 +3757,7 @@ RTLIL::Memory *RTLIL::Module::addMemory(TwineRef name, const RTLIL::Memory *othe return mem; } -RTLIL::Process *RTLIL::Module::addProcess(TwineRef name) +RTLIL::Process *RTLIL::Module::addProcess(IdString name) { RTLIL::Process *proc = new RTLIL::Process; proc->name = std::move(name); @@ -3896,7 +3806,7 @@ namespace { } } -RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *other) +RTLIL::Process *RTLIL::Module::addProcess(IdString name, const RTLIL::Process *other) { RTLIL::Process *proc = other->clone(); proc->name = std::move(name); @@ -3918,19 +3828,19 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o } #define DEF_METHOD(_func, _y_size, _type) \ - template RTLIL::Cell* CellAdderMixin::add ## _func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const RTLIL::SrcAttr &src) { \ - RTLIL::Cell *cell = static_cast(this)->addCell(name, _type); \ + template RTLIL::Cell* CellAdderMixin::add ## _func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, TwineRef src) { \ + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), _type); \ cell->parameters[ID::A_SIGNED] = is_signed; \ cell->parameters[ID::A_WIDTH] = sig_a.size(); \ cell->parameters[ID::Y_WIDTH] = sig_y.size(); \ - cell->setPort(ID::A, sig_a); \ - cell->setPort(ID::Y, sig_y); \ + cell->setPort(TW::A, sig_a); \ + cell->setPort(TW::Y, sig_y); \ cell->set_src_attribute(src); \ return cell; \ } \ - template RTLIL::SigSpec CellAdderMixin::_func(TwineRef name, const RTLIL::SigSpec &sig_a, bool is_signed, const RTLIL::SrcAttr &src) { \ - RTLIL::SigSpec sig_y = static_cast(this)->addWire(NEW_ID, _y_size); \ - add ## _func(name, sig_a, sig_y, is_signed, src); \ + template RTLIL::SigSpec CellAdderMixin::_func(Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed, TwineRef src) { \ + RTLIL::SigSpec sig_y = static_cast(this)->addWire(NEW_TWINE, _y_size); \ + add ## _func(std::move(name), sig_a, sig_y, is_signed, src); \ return sig_y; \ } DEF_METHOD(Not, sig_a.size(), ID($not)) @@ -3945,39 +3855,39 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o #undef DEF_METHOD #define DEF_METHOD(_func, _y_size, _type) \ - template RTLIL::Cell* CellAdderMixin::add ## _func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool /* is_signed */, const RTLIL::SrcAttr &src) { \ - RTLIL::Cell *cell = static_cast(this)->addCell(name, _type); \ + template RTLIL::Cell* CellAdderMixin::add ## _func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool /* is_signed */, TwineRef src) { \ + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), _type); \ cell->parameters[ID::WIDTH] = sig_a.size(); \ - cell->setPort(ID::A, sig_a); \ - cell->setPort(ID::Y, sig_y); \ + cell->setPort(TW::A, sig_a); \ + cell->setPort(TW::Y, sig_y); \ cell->set_src_attribute(src); \ return cell; \ } \ - template RTLIL::SigSpec CellAdderMixin::_func(TwineRef name, const RTLIL::SigSpec &sig_a, bool is_signed, const RTLIL::SrcAttr &src) { \ - RTLIL::SigSpec sig_y = static_cast(this)->addWire(NEW_ID, _y_size); \ - add ## _func(name, sig_a, sig_y, is_signed, src); \ + template RTLIL::SigSpec CellAdderMixin::_func(Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed, TwineRef src) { \ + RTLIL::SigSpec sig_y = static_cast(this)->addWire(NEW_TWINE, _y_size); \ + add ## _func(std::move(name), sig_a, sig_y, is_signed, src); \ return sig_y; \ } DEF_METHOD(Buf, sig_a.size(), ID($buf)) #undef DEF_METHOD #define DEF_METHOD(_func, _y_size, _type) \ - template RTLIL::Cell* CellAdderMixin::add ## _func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const RTLIL::SrcAttr &src) { \ - RTLIL::Cell *cell = static_cast(this)->addCell(name, _type); \ + template RTLIL::Cell* CellAdderMixin::add ## _func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, TwineRef src) { \ + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), _type); \ cell->parameters[ID::A_SIGNED] = is_signed; \ cell->parameters[ID::B_SIGNED] = is_signed; \ cell->parameters[ID::A_WIDTH] = sig_a.size(); \ cell->parameters[ID::B_WIDTH] = sig_b.size(); \ cell->parameters[ID::Y_WIDTH] = sig_y.size(); \ - cell->setPort(ID::A, sig_a); \ - cell->setPort(ID::B, sig_b); \ - cell->setPort(ID::Y, sig_y); \ + cell->setPort(TW::A, sig_a); \ + cell->setPort(TW::B, sig_b); \ + cell->setPort(TW::Y, sig_y); \ cell->set_src_attribute(src); \ return cell; \ } \ - template RTLIL::SigSpec CellAdderMixin::_func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const RTLIL::SrcAttr &src) { \ - RTLIL::SigSpec sig_y = static_cast(this)->addWire(NEW_ID, _y_size); \ - add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \ + template RTLIL::SigSpec CellAdderMixin::_func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, TwineRef src) { \ + RTLIL::SigSpec sig_y = static_cast(this)->addWire(NEW_TWINE, _y_size); \ + add ## _func(std::move(name), sig_a, sig_b, sig_y, is_signed, src); \ return sig_y; \ } DEF_METHOD(And, max(sig_a.size(), sig_b.size()), ID($and)) @@ -4005,22 +3915,22 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o #undef DEF_METHOD #define DEF_METHOD(_func, _y_size, _type) \ - template RTLIL::Cell* CellAdderMixin::add ## _func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const RTLIL::SrcAttr &src) { \ - RTLIL::Cell *cell = static_cast(this)->addCell(name, _type); \ + template RTLIL::Cell* CellAdderMixin::add ## _func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, TwineRef src) { \ + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), _type); \ cell->parameters[ID::A_SIGNED] = is_signed; \ cell->parameters[ID::B_SIGNED] = false; \ cell->parameters[ID::A_WIDTH] = sig_a.size(); \ cell->parameters[ID::B_WIDTH] = sig_b.size(); \ cell->parameters[ID::Y_WIDTH] = sig_y.size(); \ - cell->setPort(ID::A, sig_a); \ - cell->setPort(ID::B, sig_b); \ - cell->setPort(ID::Y, sig_y); \ + cell->setPort(TW::A, sig_a); \ + cell->setPort(TW::B, sig_b); \ + cell->setPort(TW::Y, sig_y); \ cell->set_src_attribute(src); \ return cell; \ } \ - template RTLIL::SigSpec CellAdderMixin::_func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const RTLIL::SrcAttr &src) { \ - RTLIL::SigSpec sig_y = static_cast(this)->addWire(NEW_ID, _y_size); \ - add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \ + template RTLIL::SigSpec CellAdderMixin::_func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, TwineRef src) { \ + RTLIL::SigSpec sig_y = static_cast(this)->addWire(NEW_TWINE, _y_size); \ + add ## _func(std::move(name), sig_a, sig_b, sig_y, is_signed, src); \ return sig_y; \ } DEF_METHOD(Shl, sig_a.size(), ID($shl)) @@ -4030,42 +3940,42 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o #undef DEF_METHOD #define DEF_METHOD(_func, _y_size, _type) \ - template RTLIL::Cell* CellAdderMixin::add ## _func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const RTLIL::SrcAttr &src) { \ - RTLIL::Cell *cell = static_cast(this)->addCell(name, _type); \ + template RTLIL::Cell* CellAdderMixin::add ## _func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, TwineRef src) { \ + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), _type); \ cell->parameters[ID::A_SIGNED] = false; \ cell->parameters[ID::B_SIGNED] = is_signed; \ cell->parameters[ID::A_WIDTH] = sig_a.size(); \ cell->parameters[ID::B_WIDTH] = sig_b.size(); \ cell->parameters[ID::Y_WIDTH] = sig_y.size(); \ - cell->setPort(ID::A, sig_a); \ - cell->setPort(ID::B, sig_b); \ - cell->setPort(ID::Y, sig_y); \ + cell->setPort(TW::A, sig_a); \ + cell->setPort(TW::B, sig_b); \ + cell->setPort(TW::Y, sig_y); \ cell->set_src_attribute(src); \ return cell; \ } \ - template RTLIL::SigSpec CellAdderMixin::_func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const RTLIL::SrcAttr &src) { \ - RTLIL::SigSpec sig_y = static_cast(this)->addWire(NEW_ID, _y_size); \ - add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \ + template RTLIL::SigSpec CellAdderMixin::_func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, TwineRef src) { \ + RTLIL::SigSpec sig_y = static_cast(this)->addWire(NEW_TWINE, _y_size); \ + add ## _func(std::move(name), sig_a, sig_b, sig_y, is_signed, src); \ return sig_y; \ } DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx)) #undef DEF_METHOD #define DEF_METHOD(_func, _type, _pmux) \ - template RTLIL::Cell* CellAdderMixin::add ## _func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src) { \ - RTLIL::Cell *cell = static_cast(this)->addCell(name, _type); \ + template RTLIL::Cell* CellAdderMixin::add ## _func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src) { \ + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), _type); \ cell->parameters[ID::WIDTH] = sig_a.size(); \ if (_pmux) cell->parameters[ID::S_WIDTH] = sig_s.size(); \ - cell->setPort(ID::A, sig_a); \ - cell->setPort(ID::B, sig_b); \ - cell->setPort(ID::S, sig_s); \ - cell->setPort(ID::Y, sig_y); \ + cell->setPort(TW::A, sig_a); \ + cell->setPort(TW::B, sig_b); \ + cell->setPort(TW::S, sig_s); \ + cell->setPort(TW::Y, sig_y); \ cell->set_src_attribute(src); \ return cell; \ } \ - template RTLIL::SigSpec CellAdderMixin::_func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SrcAttr &src) { \ - RTLIL::SigSpec sig_y = static_cast(this)->addWire(NEW_ID, sig_a.size()); \ - add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \ + template RTLIL::SigSpec CellAdderMixin::_func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, TwineRef src) { \ + RTLIL::SigSpec sig_y = static_cast(this)->addWire(NEW_TWINE, sig_a.size()); \ + add ## _func(std::move(name), sig_a, sig_b, sig_s, sig_y, src); \ return sig_y; \ } DEF_METHOD(Mux, ID($mux), 0) @@ -4074,19 +3984,19 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o #undef DEF_METHOD #define DEF_METHOD(_func, _type, _demux) \ - template RTLIL::Cell* CellAdderMixin::add ## _func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src) { \ - RTLIL::Cell *cell = static_cast(this)->addCell(name, _type); \ + template RTLIL::Cell* CellAdderMixin::add ## _func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src) { \ + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), _type); \ cell->parameters[ID::WIDTH] = _demux ? sig_a.size() : sig_y.size(); \ cell->parameters[ID::S_WIDTH] = sig_s.size(); \ - cell->setPort(ID::A, sig_a); \ - cell->setPort(ID::S, sig_s); \ - cell->setPort(ID::Y, sig_y); \ + cell->setPort(TW::A, sig_a); \ + cell->setPort(TW::S, sig_s); \ + cell->setPort(TW::Y, sig_y); \ cell->set_src_attribute(src); \ return cell; \ } \ - template RTLIL::SigSpec CellAdderMixin::_func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SrcAttr &src) { \ - RTLIL::SigSpec sig_y = static_cast(this)->addWire(NEW_ID, _demux ? sig_a.size() << sig_s.size() : sig_a.size() >> sig_s.size()); \ - add ## _func(name, sig_a, sig_s, sig_y, src); \ + template RTLIL::SigSpec CellAdderMixin::_func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, TwineRef src) { \ + RTLIL::SigSpec sig_y = static_cast(this)->addWire(NEW_TWINE, _demux ? sig_a.size() << sig_s.size() : sig_a.size() >> sig_s.size()); \ + add ## _func(std::move(name), sig_a, sig_s, sig_y, src); \ return sig_y; \ } DEF_METHOD(Bmux, ID($bmux), 0) @@ -4094,79 +4004,79 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o #undef DEF_METHOD #define DEF_METHOD(_func, _type) \ - template RTLIL::Cell* CellAdderMixin::add ## _func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src) { \ - RTLIL::Cell *cell = static_cast(this)->addCell(name, _type); \ + template RTLIL::Cell* CellAdderMixin::add ## _func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, TwineRef src) { \ + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), _type); \ cell->parameters[ID::WIDTH] = sig_a.size(); \ - cell->setPort(ID::A, sig_a); \ - cell->setPort(ID::B, sig_b); \ - cell->setPort(ID::Y, sig_y); \ + cell->setPort(TW::A, sig_a); \ + cell->setPort(TW::B, sig_b); \ + cell->setPort(TW::Y, sig_y); \ cell->set_src_attribute(src); \ return cell; \ } \ - template RTLIL::SigSpec CellAdderMixin::_func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SrcAttr &src) { \ - RTLIL::SigSpec sig_y = static_cast(this)->addWire(NEW_ID, sig_a.size()); \ - add ## _func(name, sig_a, sig_s, sig_y, src); \ + template RTLIL::SigSpec CellAdderMixin::_func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, TwineRef src) { \ + RTLIL::SigSpec sig_y = static_cast(this)->addWire(NEW_TWINE, sig_a.size()); \ + add ## _func(std::move(name), sig_a, sig_s, sig_y, src); \ return sig_y; \ } DEF_METHOD(Bweqx, ID($bweqx)) #undef DEF_METHOD #define DEF_METHOD_2(_func, _type, _P1, _P2) \ - template RTLIL::Cell* CellAdderMixin::add ## _func(TwineRef name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SrcAttr &src) { \ - RTLIL::Cell *cell = static_cast(this)->addCell(name, _type); \ - cell->setPort("\\" #_P1, sig1); \ - cell->setPort("\\" #_P2, sig2); \ + template RTLIL::Cell* CellAdderMixin::add ## _func(Twine &&name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, TwineRef src) { \ + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), _type); \ + cell->setPort(TW::_P1, sig1); \ + cell->setPort(TW::_P2, sig2); \ cell->set_src_attribute(src); \ return cell; \ } \ - template RTLIL::SigBit CellAdderMixin::_func(TwineRef name, const RTLIL::SigBit &sig1, const RTLIL::SrcAttr &src) { \ - RTLIL::SigBit sig2 = static_cast(this)->addWire(NEW_ID); \ - add ## _func(name, sig1, sig2, src); \ + template RTLIL::SigBit CellAdderMixin::_func(Twine &&name, const RTLIL::SigBit &sig1, TwineRef src) { \ + RTLIL::SigBit sig2 = static_cast(this)->addWire(NEW_TWINE); \ + add ## _func(std::move(name), sig1, sig2, src); \ return sig2; \ } #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \ - template RTLIL::Cell* CellAdderMixin::add ## _func(TwineRef name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SrcAttr &src) { \ - RTLIL::Cell *cell = static_cast(this)->addCell(name, _type); \ - cell->setPort("\\" #_P1, sig1); \ - cell->setPort("\\" #_P2, sig2); \ - cell->setPort("\\" #_P3, sig3); \ + template RTLIL::Cell* CellAdderMixin::add ## _func(Twine &&name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, TwineRef src) { \ + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), _type); \ + cell->setPort(TW::_P1, sig1); \ + cell->setPort(TW::_P2, sig2); \ + cell->setPort(TW::_P3, sig3); \ cell->set_src_attribute(src); \ return cell; \ } \ - template RTLIL::SigBit CellAdderMixin::_func(TwineRef name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SrcAttr &src) { \ - RTLIL::SigBit sig3 = static_cast(this)->addWire(NEW_ID); \ - add ## _func(name, sig1, sig2, sig3, src); \ + template RTLIL::SigBit CellAdderMixin::_func(Twine &&name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, TwineRef src) { \ + RTLIL::SigBit sig3 = static_cast(this)->addWire(NEW_TWINE); \ + add ## _func(std::move(name), sig1, sig2, sig3, src); \ return sig3; \ } #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \ - template RTLIL::Cell* CellAdderMixin::add ## _func(TwineRef name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SrcAttr &src) { \ - RTLIL::Cell *cell = static_cast(this)->addCell(name, _type); \ - cell->setPort("\\" #_P1, sig1); \ - cell->setPort("\\" #_P2, sig2); \ - cell->setPort("\\" #_P3, sig3); \ - cell->setPort("\\" #_P4, sig4); \ + template RTLIL::Cell* CellAdderMixin::add ## _func(Twine &&name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, TwineRef src) { \ + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), _type); \ + cell->setPort(TW::_P1, sig1); \ + cell->setPort(TW::_P2, sig2); \ + cell->setPort(TW::_P3, sig3); \ + cell->setPort(TW::_P4, sig4); \ cell->set_src_attribute(src); \ return cell; \ } \ - template RTLIL::SigBit CellAdderMixin::_func(TwineRef name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SrcAttr &src) { \ - RTLIL::SigBit sig4 = static_cast(this)->addWire(NEW_ID); \ - add ## _func(name, sig1, sig2, sig3, sig4, src); \ + template RTLIL::SigBit CellAdderMixin::_func(Twine &&name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, TwineRef src) { \ + RTLIL::SigBit sig4 = static_cast(this)->addWire(NEW_TWINE); \ + add ## _func(std::move(name), sig1, sig2, sig3, sig4, src); \ return sig4; \ } #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \ - template RTLIL::Cell* CellAdderMixin::add ## _func(TwineRef name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, const RTLIL::SrcAttr &src) { \ - RTLIL::Cell *cell = static_cast(this)->addCell(name, _type); \ - cell->setPort("\\" #_P1, sig1); \ - cell->setPort("\\" #_P2, sig2); \ - cell->setPort("\\" #_P3, sig3); \ - cell->setPort("\\" #_P4, sig4); \ - cell->setPort("\\" #_P5, sig5); \ + template RTLIL::Cell* CellAdderMixin::add ## _func(Twine &&name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, TwineRef src) { \ + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), _type); \ + cell->setPort(TW::_P1, sig1); \ + cell->setPort(TW::_P2, sig2); \ + cell->setPort(TW::_P3, sig3); \ + cell->setPort(TW::_P4, sig4); \ + cell->setPort(TW::_P5, sig5); \ cell->set_src_attribute(src); \ return cell; \ } \ - template RTLIL::SigBit CellAdderMixin::_func(TwineRef name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SrcAttr &src) { \ - RTLIL::SigBit sig5 = static_cast(this)->addWire(NEW_ID); \ - add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \ + template RTLIL::SigBit CellAdderMixin::_func(Twine &&name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, TwineRef src) { \ + RTLIL::SigBit sig5 = static_cast(this)->addWire(NEW_TWINE); \ + add ## _func(std::move(name), sig1, sig2, sig3, sig4, sig5, src); \ return sig5; \ } DEF_METHOD_2(BufGate, ID($_BUF_), A, Y) @@ -4190,707 +4100,707 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o #undef DEF_METHOD_4 #undef DEF_METHOD_5 - template RTLIL::Cell* CellAdderMixin::addPow(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed, bool b_signed, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addPow(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed, bool b_signed, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($pow)); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($pow)); cell->parameters[ID::A_SIGNED] = a_signed; cell->parameters[ID::B_SIGNED] = b_signed; cell->parameters[ID::A_WIDTH] = sig_a.size(); cell->parameters[ID::B_WIDTH] = sig_b.size(); cell->parameters[ID::Y_WIDTH] = sig_y.size(); - cell->setPort(ID::A, sig_a); - cell->setPort(ID::B, sig_b); - cell->setPort(ID::Y, sig_y); + cell->setPort(TW::A, sig_a); + cell->setPort(TW::B, sig_b); + cell->setPort(TW::Y, sig_y); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addFa(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addFa(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($fa)); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($fa)); cell->parameters[ID::WIDTH] = sig_a.size(); - cell->setPort(ID::A, sig_a); - cell->setPort(ID::B, sig_b); - cell->setPort(ID::C, sig_c); - cell->setPort(ID::X, sig_x); - cell->setPort(ID::Y, sig_y); + cell->setPort(TW::A, sig_a); + cell->setPort(TW::B, sig_b); + cell->setPort(TW::C, sig_c); + cell->setPort(TW::X, sig_x); + cell->setPort(TW::Y, sig_y); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addSlice(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addSlice(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($slice)); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($slice)); cell->parameters[ID::A_WIDTH] = sig_a.size(); cell->parameters[ID::Y_WIDTH] = sig_y.size(); cell->parameters[ID::OFFSET] = offset; - cell->setPort(ID::A, sig_a); - cell->setPort(ID::Y, sig_y); + cell->setPort(TW::A, sig_a); + cell->setPort(TW::Y, sig_y); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addConcat(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addConcat(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($concat)); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($concat)); cell->parameters[ID::A_WIDTH] = sig_a.size(); cell->parameters[ID::B_WIDTH] = sig_b.size(); - cell->setPort(ID::A, sig_a); - cell->setPort(ID::B, sig_b); - cell->setPort(ID::Y, sig_y); + cell->setPort(TW::A, sig_a); + cell->setPort(TW::B, sig_b); + cell->setPort(TW::Y, sig_y); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addLut(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addLut(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($lut)); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($lut)); cell->parameters[ID::LUT] = lut; cell->parameters[ID::WIDTH] = sig_a.size(); - cell->setPort(ID::A, sig_a); - cell->setPort(ID::Y, sig_y); + cell->setPort(TW::A, sig_a); + cell->setPort(TW::Y, sig_y); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addTribuf(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addTribuf(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($tribuf)); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($tribuf)); cell->parameters[ID::WIDTH] = sig_a.size(); - cell->setPort(ID::A, sig_a); - cell->setPort(ID::EN, sig_en); - cell->setPort(ID::Y, sig_y); + cell->setPort(TW::A, sig_a); + cell->setPort(TW::EN, sig_en); + cell->setPort(TW::Y, sig_y); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addAssert(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addAssert(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($assert)); - cell->setPort(ID::A, sig_a); - cell->setPort(ID::EN, sig_en); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($assert)); + cell->setPort(TW::A, sig_a); + cell->setPort(TW::EN, sig_en); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addAssume(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addAssume(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($assume)); - cell->setPort(ID::A, sig_a); - cell->setPort(ID::EN, sig_en); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($assume)); + cell->setPort(TW::A, sig_a); + cell->setPort(TW::EN, sig_en); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addLive(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addLive(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($live)); - cell->setPort(ID::A, sig_a); - cell->setPort(ID::EN, sig_en); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($live)); + cell->setPort(TW::A, sig_a); + cell->setPort(TW::EN, sig_en); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addFair(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addFair(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($fair)); - cell->setPort(ID::A, sig_a); - cell->setPort(ID::EN, sig_en); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($fair)); + cell->setPort(TW::A, sig_a); + cell->setPort(TW::EN, sig_en); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addCover(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addCover(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($cover)); - cell->setPort(ID::A, sig_a); - cell->setPort(ID::EN, sig_en); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($cover)); + cell->setPort(TW::A, sig_a); + cell->setPort(TW::EN, sig_en); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addEquiv(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addEquiv(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($equiv)); - cell->setPort(ID::A, sig_a); - cell->setPort(ID::B, sig_b); - cell->setPort(ID::Y, sig_y); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($equiv)); + cell->setPort(TW::A, sig_a); + cell->setPort(TW::B, sig_b); + cell->setPort(TW::Y, sig_y); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addSr(TwineRef name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addSr(Twine &&name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($sr)); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($sr)); cell->parameters[ID::SET_POLARITY] = set_polarity; cell->parameters[ID::CLR_POLARITY] = clr_polarity; cell->parameters[ID::WIDTH] = sig_q.size(); - cell->setPort(ID::SET, sig_set); - cell->setPort(ID::CLR, sig_clr); - cell->setPort(ID::Q, sig_q); + cell->setPort(TW::SET, sig_set); + cell->setPort(TW::CLR, sig_clr); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addFf(TwineRef name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addFf(Twine &&name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($ff)); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($ff)); cell->parameters[ID::WIDTH] = sig_q.size(); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addDff(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addDff(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($dff)); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($dff)); cell->parameters[ID::CLK_POLARITY] = clk_polarity; cell->parameters[ID::WIDTH] = sig_q.size(); - cell->setPort(ID::CLK, sig_clk); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + cell->setPort(TW::CLK, sig_clk); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addDffe(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addDffe(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($dffe)); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($dffe)); cell->parameters[ID::CLK_POLARITY] = clk_polarity; cell->parameters[ID::EN_POLARITY] = en_polarity; cell->parameters[ID::WIDTH] = sig_q.size(); - cell->setPort(ID::CLK, sig_clk); - cell->setPort(ID::EN, sig_en); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + cell->setPort(TW::CLK, sig_clk); + cell->setPort(TW::EN, sig_en); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addDffsr(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, - RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addDffsr(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, + RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($dffsr)); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($dffsr)); cell->parameters[ID::CLK_POLARITY] = clk_polarity; cell->parameters[ID::SET_POLARITY] = set_polarity; cell->parameters[ID::CLR_POLARITY] = clr_polarity; cell->parameters[ID::WIDTH] = sig_q.size(); - cell->setPort(ID::CLK, sig_clk); - cell->setPort(ID::SET, sig_set); - cell->setPort(ID::CLR, sig_clr); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + cell->setPort(TW::CLK, sig_clk); + cell->setPort(TW::SET, sig_set); + cell->setPort(TW::CLR, sig_clr); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addDffsre(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, - RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, bool set_polarity, bool clr_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addDffsre(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, + RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, bool set_polarity, bool clr_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($dffsre)); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($dffsre)); cell->parameters[ID::CLK_POLARITY] = clk_polarity; cell->parameters[ID::EN_POLARITY] = en_polarity; cell->parameters[ID::SET_POLARITY] = set_polarity; cell->parameters[ID::CLR_POLARITY] = clr_polarity; cell->parameters[ID::WIDTH] = sig_q.size(); - cell->setPort(ID::CLK, sig_clk); - cell->setPort(ID::EN, sig_en); - cell->setPort(ID::SET, sig_set); - cell->setPort(ID::CLR, sig_clr); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + cell->setPort(TW::CLK, sig_clk); + cell->setPort(TW::EN, sig_en); + cell->setPort(TW::SET, sig_set); + cell->setPort(TW::CLR, sig_clr); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addAdff(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, - RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addAdff(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, + RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($adff)); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($adff)); cell->parameters[ID::CLK_POLARITY] = clk_polarity; cell->parameters[ID::ARST_POLARITY] = arst_polarity; cell->parameters[ID::ARST_VALUE] = arst_value; cell->parameters[ID::WIDTH] = sig_q.size(); - cell->setPort(ID::CLK, sig_clk); - cell->setPort(ID::ARST, sig_arst); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + cell->setPort(TW::CLK, sig_clk); + cell->setPort(TW::ARST, sig_arst); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addAdffe(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, - RTLIL::Const arst_value, bool clk_polarity, bool en_polarity, bool arst_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addAdffe(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, + RTLIL::Const arst_value, bool clk_polarity, bool en_polarity, bool arst_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($adffe)); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($adffe)); cell->parameters[ID::CLK_POLARITY] = clk_polarity; cell->parameters[ID::EN_POLARITY] = en_polarity; cell->parameters[ID::ARST_POLARITY] = arst_polarity; cell->parameters[ID::ARST_VALUE] = arst_value; cell->parameters[ID::WIDTH] = sig_q.size(); - cell->setPort(ID::CLK, sig_clk); - cell->setPort(ID::EN, sig_en); - cell->setPort(ID::ARST, sig_arst); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + cell->setPort(TW::CLK, sig_clk); + cell->setPort(TW::EN, sig_en); + cell->setPort(TW::ARST, sig_arst); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addAldff(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, - const RTLIL::SigSpec &sig_ad, bool clk_polarity, bool aload_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addAldff(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, + const RTLIL::SigSpec &sig_ad, bool clk_polarity, bool aload_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($aldff)); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($aldff)); cell->parameters[ID::CLK_POLARITY] = clk_polarity; cell->parameters[ID::ALOAD_POLARITY] = aload_polarity; cell->parameters[ID::WIDTH] = sig_q.size(); - cell->setPort(ID::CLK, sig_clk); - cell->setPort(ID::ALOAD, sig_aload); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::AD, sig_ad); - cell->setPort(ID::Q, sig_q); + cell->setPort(TW::CLK, sig_clk); + cell->setPort(TW::ALOAD, sig_aload); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::AD, sig_ad); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addAldffe(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, - const RTLIL::SigSpec &sig_ad, bool clk_polarity, bool en_polarity, bool aload_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addAldffe(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, + const RTLIL::SigSpec &sig_ad, bool clk_polarity, bool en_polarity, bool aload_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($aldffe)); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($aldffe)); cell->parameters[ID::CLK_POLARITY] = clk_polarity; cell->parameters[ID::EN_POLARITY] = en_polarity; cell->parameters[ID::ALOAD_POLARITY] = aload_polarity; cell->parameters[ID::WIDTH] = sig_q.size(); - cell->setPort(ID::CLK, sig_clk); - cell->setPort(ID::EN, sig_en); - cell->setPort(ID::ALOAD, sig_aload); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::AD, sig_ad); - cell->setPort(ID::Q, sig_q); + cell->setPort(TW::CLK, sig_clk); + cell->setPort(TW::EN, sig_en); + cell->setPort(TW::ALOAD, sig_aload); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::AD, sig_ad); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addSdff(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, - RTLIL::Const srst_value, bool clk_polarity, bool srst_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addSdff(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, + RTLIL::Const srst_value, bool clk_polarity, bool srst_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($sdff)); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($sdff)); cell->parameters[ID::CLK_POLARITY] = clk_polarity; cell->parameters[ID::SRST_POLARITY] = srst_polarity; cell->parameters[ID::SRST_VALUE] = srst_value; cell->parameters[ID::WIDTH] = sig_q.size(); - cell->setPort(ID::CLK, sig_clk); - cell->setPort(ID::SRST, sig_srst); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + cell->setPort(TW::CLK, sig_clk); + cell->setPort(TW::SRST, sig_srst); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addSdffe(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, - RTLIL::Const srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addSdffe(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, + RTLIL::Const srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($sdffe)); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($sdffe)); cell->parameters[ID::CLK_POLARITY] = clk_polarity; cell->parameters[ID::EN_POLARITY] = en_polarity; cell->parameters[ID::SRST_POLARITY] = srst_polarity; cell->parameters[ID::SRST_VALUE] = srst_value; cell->parameters[ID::WIDTH] = sig_q.size(); - cell->setPort(ID::CLK, sig_clk); - cell->setPort(ID::EN, sig_en); - cell->setPort(ID::SRST, sig_srst); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + cell->setPort(TW::CLK, sig_clk); + cell->setPort(TW::EN, sig_en); + cell->setPort(TW::SRST, sig_srst); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addSdffce(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, - RTLIL::Const srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addSdffce(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, + RTLIL::Const srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($sdffce)); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($sdffce)); cell->parameters[ID::CLK_POLARITY] = clk_polarity; cell->parameters[ID::EN_POLARITY] = en_polarity; cell->parameters[ID::SRST_POLARITY] = srst_polarity; cell->parameters[ID::SRST_VALUE] = srst_value; cell->parameters[ID::WIDTH] = sig_q.size(); - cell->setPort(ID::CLK, sig_clk); - cell->setPort(ID::EN, sig_en); - cell->setPort(ID::SRST, sig_srst); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + cell->setPort(TW::CLK, sig_clk); + cell->setPort(TW::EN, sig_en); + cell->setPort(TW::SRST, sig_srst); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addDlatch(TwineRef name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addDlatch(Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($dlatch)); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($dlatch)); cell->parameters[ID::EN_POLARITY] = en_polarity; cell->parameters[ID::WIDTH] = sig_q.size(); - cell->setPort(ID::EN, sig_en); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + cell->setPort(TW::EN, sig_en); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addAdlatch(TwineRef name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, - RTLIL::Const arst_value, bool en_polarity, bool arst_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addAdlatch(Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, + RTLIL::Const arst_value, bool en_polarity, bool arst_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($adlatch)); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($adlatch)); cell->parameters[ID::EN_POLARITY] = en_polarity; cell->parameters[ID::ARST_POLARITY] = arst_polarity; cell->parameters[ID::ARST_VALUE] = arst_value; cell->parameters[ID::WIDTH] = sig_q.size(); - cell->setPort(ID::EN, sig_en); - cell->setPort(ID::ARST, sig_arst); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + cell->setPort(TW::EN, sig_en); + cell->setPort(TW::ARST, sig_arst); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addDlatchsr(TwineRef name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, - RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addDlatchsr(Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, + RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($dlatchsr)); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($dlatchsr)); cell->parameters[ID::EN_POLARITY] = en_polarity; cell->parameters[ID::SET_POLARITY] = set_polarity; cell->parameters[ID::CLR_POLARITY] = clr_polarity; cell->parameters[ID::WIDTH] = sig_q.size(); - cell->setPort(ID::EN, sig_en); - cell->setPort(ID::SET, sig_set); - cell->setPort(ID::CLR, sig_clr); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + cell->setPort(TW::EN, sig_en); + cell->setPort(TW::SET, sig_set); + cell->setPort(TW::CLR, sig_clr); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addSrGate(TwineRef name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, - const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addSrGate(Twine &&name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, + const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, stringf("$_SR_%c%c_", set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N')); - cell->setPort(ID::S, sig_set); - cell->setPort(ID::R, sig_clr); - cell->setPort(ID::Q, sig_q); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), stringf("$_SR_%c%c_", set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N')); + cell->setPort(TW::S, sig_set); + cell->setPort(TW::R, sig_clr); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addFfGate(TwineRef name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addFfGate(Twine &&name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, ID($_FF_)); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), ID($_FF_)); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addDffGate(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addDffGate(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N')); - cell->setPort(ID::C, sig_clk); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N')); + cell->setPort(TW::C, sig_clk); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addDffeGate(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addDffeGate(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N')); - cell->setPort(ID::C, sig_clk); - cell->setPort(ID::E, sig_en); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N')); + cell->setPort(TW::C, sig_clk); + cell->setPort(TW::E, sig_en); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addDffsrGate(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, - RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addDffsrGate(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, + RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N')); - cell->setPort(ID::C, sig_clk); - cell->setPort(ID::S, sig_set); - cell->setPort(ID::R, sig_clr); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N')); + cell->setPort(TW::C, sig_clk); + cell->setPort(TW::S, sig_set); + cell->setPort(TW::R, sig_clr); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addDffsreGate(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, - RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, bool set_polarity, bool clr_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addDffsreGate(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, + RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, bool set_polarity, bool clr_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, stringf("$_DFFSRE_%c%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N')); - cell->setPort(ID::C, sig_clk); - cell->setPort(ID::S, sig_set); - cell->setPort(ID::R, sig_clr); - cell->setPort(ID::E, sig_en); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), stringf("$_DFFSRE_%c%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N')); + cell->setPort(TW::C, sig_clk); + cell->setPort(TW::S, sig_set); + cell->setPort(TW::R, sig_clr); + cell->setPort(TW::E, sig_en); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addAdffGate(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, - bool arst_value, bool clk_polarity, bool arst_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addAdffGate(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, + bool arst_value, bool clk_polarity, bool arst_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0')); - cell->setPort(ID::C, sig_clk); - cell->setPort(ID::R, sig_arst); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0')); + cell->setPort(TW::C, sig_clk); + cell->setPort(TW::R, sig_arst); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addAdffeGate(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, - bool arst_value, bool clk_polarity, bool en_polarity, bool arst_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addAdffeGate(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, + bool arst_value, bool clk_polarity, bool en_polarity, bool arst_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, stringf("$_DFFE_%c%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0', en_polarity ? 'P' : 'N')); - cell->setPort(ID::C, sig_clk); - cell->setPort(ID::R, sig_arst); - cell->setPort(ID::E, sig_en); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), stringf("$_DFFE_%c%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0', en_polarity ? 'P' : 'N')); + cell->setPort(TW::C, sig_clk); + cell->setPort(TW::R, sig_arst); + cell->setPort(TW::E, sig_en); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addAldffGate(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, - const RTLIL::SigSpec &sig_ad, bool clk_polarity, bool aload_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addAldffGate(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, + const RTLIL::SigSpec &sig_ad, bool clk_polarity, bool aload_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, stringf("$_ALDFF_%c%c_", clk_polarity ? 'P' : 'N', aload_polarity ? 'P' : 'N')); - cell->setPort(ID::C, sig_clk); - cell->setPort(ID::L, sig_aload); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::AD, sig_ad); - cell->setPort(ID::Q, sig_q); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), stringf("$_ALDFF_%c%c_", clk_polarity ? 'P' : 'N', aload_polarity ? 'P' : 'N')); + cell->setPort(TW::C, sig_clk); + cell->setPort(TW::L, sig_aload); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::AD, sig_ad); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addAldffeGate(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, - const RTLIL::SigSpec &sig_ad, bool clk_polarity, bool en_polarity, bool aload_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addAldffeGate(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, + const RTLIL::SigSpec &sig_ad, bool clk_polarity, bool en_polarity, bool aload_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, stringf("$_ALDFFE_%c%c%c_", clk_polarity ? 'P' : 'N', aload_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N')); - cell->setPort(ID::C, sig_clk); - cell->setPort(ID::L, sig_aload); - cell->setPort(ID::E, sig_en); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::AD, sig_ad); - cell->setPort(ID::Q, sig_q); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), stringf("$_ALDFFE_%c%c%c_", clk_polarity ? 'P' : 'N', aload_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N')); + cell->setPort(TW::C, sig_clk); + cell->setPort(TW::L, sig_aload); + cell->setPort(TW::E, sig_en); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::AD, sig_ad); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addSdffGate(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, - bool srst_value, bool clk_polarity, bool srst_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addSdffGate(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, + bool srst_value, bool clk_polarity, bool srst_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, stringf("$_SDFF_%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0')); - cell->setPort(ID::C, sig_clk); - cell->setPort(ID::R, sig_srst); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), stringf("$_SDFF_%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0')); + cell->setPort(TW::C, sig_clk); + cell->setPort(TW::R, sig_srst); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addSdffeGate(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, - bool srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addSdffeGate(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, + bool srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, stringf("$_SDFFE_%c%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0', en_polarity ? 'P' : 'N')); - cell->setPort(ID::C, sig_clk); - cell->setPort(ID::R, sig_srst); - cell->setPort(ID::E, sig_en); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), stringf("$_SDFFE_%c%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0', en_polarity ? 'P' : 'N')); + cell->setPort(TW::C, sig_clk); + cell->setPort(TW::R, sig_srst); + cell->setPort(TW::E, sig_en); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addSdffceGate(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, - bool srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addSdffceGate(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, + bool srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, stringf("$_SDFFCE_%c%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0', en_polarity ? 'P' : 'N')); - cell->setPort(ID::C, sig_clk); - cell->setPort(ID::R, sig_srst); - cell->setPort(ID::E, sig_en); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), stringf("$_SDFFCE_%c%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0', en_polarity ? 'P' : 'N')); + cell->setPort(TW::C, sig_clk); + cell->setPort(TW::R, sig_srst); + cell->setPort(TW::E, sig_en); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addDlatchGate(TwineRef name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addDlatchGate(Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N')); - cell->setPort(ID::E, sig_en); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N')); + cell->setPort(TW::E, sig_en); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addAdlatchGate(TwineRef name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, - bool arst_value, bool en_polarity, bool arst_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addAdlatchGate(Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, + bool arst_value, bool en_polarity, bool arst_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, stringf("$_DLATCH_%c%c%c_", en_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0')); - cell->setPort(ID::E, sig_en); - cell->setPort(ID::R, sig_arst); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), stringf("$_DLATCH_%c%c%c_", en_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0')); + cell->setPort(TW::E, sig_en); + cell->setPort(TW::R, sig_arst); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } - template RTLIL::Cell* CellAdderMixin::addDlatchsrGate(TwineRef name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, - RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const RTLIL::SrcAttr &src) + template RTLIL::Cell* CellAdderMixin::addDlatchsrGate(Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, + RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, TwineRef src) { - RTLIL::Cell *cell = static_cast(this)->addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N')); - cell->setPort(ID::E, sig_en); - cell->setPort(ID::S, sig_set); - cell->setPort(ID::R, sig_clr); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + RTLIL::Cell *cell = static_cast(this)->addCell(std::move(name), stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N')); + cell->setPort(TW::E, sig_en); + cell->setPort(TW::S, sig_set); + cell->setPort(TW::R, sig_clr); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } -RTLIL::Cell* RTLIL::Module::addAnyinit(TwineRef name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SrcAttr &src) +RTLIL::Cell* RTLIL::Module::addAnyinit(IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src) { - RTLIL::Cell *cell = addCell(name, ID($anyinit)); + RTLIL::Cell *cell = addCell(Twine{name.str()}, ID($anyinit)); cell->parameters[ID::WIDTH] = sig_q.size(); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); cell->set_src_attribute(src); return cell; } -RTLIL::SigSpec RTLIL::Module::Anyconst(TwineRef name, int width, const RTLIL::SrcAttr &src) +RTLIL::SigSpec RTLIL::Module::Anyconst(TwineRef name, int width, TwineRef src) { - RTLIL::SigSpec sig = addWire(NEW_ID, width); + RTLIL::SigSpec sig = addWire(NEW_TWINE, width); Cell *cell = addCell(name, ID($anyconst)); cell->setParam(ID::WIDTH, width); - cell->setPort(ID::Y, sig); + cell->setPort(TW::Y, sig); cell->set_src_attribute(src); return sig; } -RTLIL::SigSpec RTLIL::Module::Anyseq(TwineRef name, int width, const RTLIL::SrcAttr &src) +RTLIL::SigSpec RTLIL::Module::Anyseq(TwineRef name, int width, TwineRef src) { - RTLIL::SigSpec sig = addWire(NEW_ID, width); + RTLIL::SigSpec sig = addWire(NEW_TWINE, width); Cell *cell = addCell(name, ID($anyseq)); cell->setParam(ID::WIDTH, width); - cell->setPort(ID::Y, sig); + cell->setPort(TW::Y, sig); cell->set_src_attribute(src); return sig; } -RTLIL::SigSpec RTLIL::Module::Allconst(TwineRef name, int width, const RTLIL::SrcAttr &src) +RTLIL::SigSpec RTLIL::Module::Allconst(TwineRef name, int width, TwineRef src) { - RTLIL::SigSpec sig = addWire(NEW_ID, width); + RTLIL::SigSpec sig = addWire(NEW_TWINE, width); Cell *cell = addCell(name, ID($allconst)); cell->setParam(ID::WIDTH, width); - cell->setPort(ID::Y, sig); + cell->setPort(TW::Y, sig); cell->set_src_attribute(src); return sig; } -RTLIL::SigSpec RTLIL::Module::Allseq(TwineRef name, int width, const RTLIL::SrcAttr &src) +RTLIL::SigSpec RTLIL::Module::Allseq(TwineRef name, int width, TwineRef src) { - RTLIL::SigSpec sig = addWire(NEW_ID, width); + RTLIL::SigSpec sig = addWire(NEW_TWINE, width); Cell *cell = addCell(name, ID($allseq)); cell->setParam(ID::WIDTH, width); - cell->setPort(ID::Y, sig); + cell->setPort(TW::Y, sig); cell->set_src_attribute(src); return sig; } -RTLIL::SigSpec RTLIL::Module::Initstate(TwineRef name, const RTLIL::SrcAttr &src) +RTLIL::SigSpec RTLIL::Module::Initstate(TwineRef name, TwineRef src) { - RTLIL::SigSpec sig = addWire(NEW_ID); + RTLIL::SigSpec sig = addWire(NEW_TWINE); Cell *cell = addCell(name, ID($initstate)); - cell->setPort(ID::Y, sig); + cell->setPort(TW::Y, sig); cell->set_src_attribute(src); return sig; } -RTLIL::SigSpec RTLIL::Module::SetTag(TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SrcAttr &src) +RTLIL::SigSpec RTLIL::Module::SetTag(TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, TwineRef src) { - RTLIL::SigSpec sig = addWire(NEW_ID, sig_a.size()); + RTLIL::SigSpec sig = addWire(NEW_TWINE, sig_a.size()); Cell *cell = addCell(name, ID($set_tag)); cell->parameters[ID::WIDTH] = sig_a.size(); cell->parameters[ID::TAG] = tag; - cell->setPort(ID::A, sig_a); - cell->setPort(ID::SET, sig_s); - cell->setPort(ID::CLR, sig_c); - cell->setPort(ID::Y, sig); + cell->setPort(TW::A, sig_a); + cell->setPort(TW::SET, sig_s); + cell->setPort(TW::CLR, sig_c); + cell->setPort(TW::Y, sig); cell->set_src_attribute(src); return sig; } -RTLIL::Cell* RTLIL::Module::addSetTag(TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src) +RTLIL::Cell* RTLIL::Module::addSetTag(TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, TwineRef src) { Cell *cell = addCell(name, ID($set_tag)); cell->parameters[ID::WIDTH] = sig_a.size(); cell->parameters[ID::TAG] = tag; - cell->setPort(ID::A, sig_a); - cell->setPort(ID::SET, sig_s); - cell->setPort(ID::CLR, sig_c); - cell->setPort(ID::Y, sig_y); + cell->setPort(TW::A, sig_a); + cell->setPort(TW::SET, sig_s); + cell->setPort(TW::CLR, sig_c); + cell->setPort(TW::Y, sig_y); cell->set_src_attribute(src); return cell; } -RTLIL::SigSpec RTLIL::Module::GetTag(TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SrcAttr &src) +RTLIL::SigSpec RTLIL::Module::GetTag(TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, TwineRef src) { - RTLIL::SigSpec sig = addWire(NEW_ID, sig_a.size()); + RTLIL::SigSpec sig = addWire(NEW_TWINE, sig_a.size()); Cell *cell = addCell(name, ID($get_tag)); cell->parameters[ID::WIDTH] = sig_a.size(); cell->parameters[ID::TAG] = tag; - cell->setPort(ID::A, sig_a); - cell->setPort(ID::Y, sig); + cell->setPort(TW::A, sig_a); + cell->setPort(TW::Y, sig); cell->set_src_attribute(src); return sig; } -RTLIL::Cell* RTLIL::Module::addOverwriteTag(TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SrcAttr &src) +RTLIL::Cell* RTLIL::Module::addOverwriteTag(TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, TwineRef src) { RTLIL::Cell *cell = addCell(name, ID($overwrite_tag)); cell->parameters[ID::WIDTH] = sig_a.size(); cell->parameters[ID::TAG] = tag; - cell->setPort(ID::A, sig_a); - cell->setPort(ID::SET, sig_s); - cell->setPort(ID::CLR, sig_c); + cell->setPort(TW::A, sig_a); + cell->setPort(TW::SET, sig_s); + cell->setPort(TW::CLR, sig_c); cell->set_src_attribute(src); return cell; } -RTLIL::SigSpec RTLIL::Module::OriginalTag(TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SrcAttr &src) +RTLIL::SigSpec RTLIL::Module::OriginalTag(TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, TwineRef src) { - RTLIL::SigSpec sig = addWire(NEW_ID, sig_a.size()); + RTLIL::SigSpec sig = addWire(NEW_TWINE, sig_a.size()); Cell *cell = addCell(name, ID($original_tag)); cell->parameters[ID::WIDTH] = sig_a.size(); cell->parameters[ID::TAG] = tag; - cell->setPort(ID::A, sig_a); - cell->setPort(ID::Y, sig); + cell->setPort(TW::A, sig_a); + cell->setPort(TW::Y, sig); cell->set_src_attribute(src); return sig; } -RTLIL::SigSpec RTLIL::Module::FutureFF(TwineRef name, const RTLIL::SigSpec &sig_e, const RTLIL::SrcAttr &src) +RTLIL::SigSpec RTLIL::Module::FutureFF(TwineRef name, const RTLIL::SigSpec &sig_e, TwineRef src) { - RTLIL::SigSpec sig = addWire(NEW_ID, sig_e.size()); + RTLIL::SigSpec sig = addWire(NEW_TWINE, sig_e.size()); Cell *cell = addCell(name, ID($future_ff)); cell->parameters[ID::WIDTH] = sig_e.size(); - cell->setPort(ID::A, sig_e); - cell->setPort(ID::Y, sig); + cell->setPort(TW::A, sig_e); + cell->setPort(TW::Y, sig); cell->set_src_attribute(src); return sig; } @@ -4924,10 +4834,10 @@ RTLIL::Wire::Wire(ConstructToken) RTLIL::Wire::~Wire() { - if (module && module->design) { - module->design->obj_release_src(this); - module->design->obj_release_name_id(this); - } + // if (module && module->design) { + // module->design->obj_release_src(this); + // module->design->obj_release_name(this); + // } #ifdef YOSYS_ENABLE_PYTHON RTLIL::Wire::get_all_wires()->erase(hashidx_); #endif @@ -4946,9 +4856,9 @@ void RTLIL::Wire::set_src_id(TwineRef id) module->design->obj_set_src_id(this, id); } -void RTLIL::Wire::set_src_attribute(const RTLIL::SrcAttr &src) +void RTLIL::Wire::set_src_attribute(TwineRef src) { - if (src.empty() && meta_ == nullptr) + if (src == Twine::Null && meta_ == nullptr) return; log_assert(module && module->design && "Wire::set_src_attribute requires the wire to be attached to a module in a design"); module->design->set_src_attribute(this, src); @@ -4967,7 +4877,7 @@ void RTLIL::Wire::adopt_src_from(const RTLIL::AttrObject *source) module->design->adopt_src_from(this, source); } -void RTLIL::Wire::absorb_attrs(dict &&buf) +void RTLIL::Wire::absorb_attrs(dict &&buf) { log_assert(module && module->design && "Wire::absorb_attrs requires the wire to be attached to a module in a design"); module->design->absorb_attrs(this, std::move(buf)); @@ -5039,10 +4949,10 @@ RTLIL::Cell::Cell(ConstructToken) : module(nullptr) RTLIL::Cell::~Cell() { - if (module && module->design) { - module->design->obj_release_src(this); - module->design->obj_release_name_id(this); - } + // if (module && module->design) { + // module->design->obj_release_src(this); + // module->design->obj_release_name(this); + // } #ifdef YOSYS_ENABLE_PYTHON RTLIL::Cell::get_all_cells()->erase(hashidx_); #endif @@ -5061,7 +4971,7 @@ void RTLIL::Cell::set_src_id(TwineRef id) module->design->obj_set_src_id(this, id); } -void RTLIL::Cell::set_src_attribute(RTLIL::SrcAttr src) +void RTLIL::Cell::set_src_attribute(TwineRef src) { log_assert(module && module->design && "Cell::set_src_attribute requires the cell to be attached to a module in a design"); module->design->set_src_attribute(this, src); @@ -5080,7 +4990,7 @@ void RTLIL::Cell::adopt_src_from(const RTLIL::AttrObject *source) module->design->adopt_src_from(this, source); } -void RTLIL::Cell::absorb_attrs(dict &&buf) +void RTLIL::Cell::absorb_attrs(dict &&buf) { log_assert(module && module->design && "Cell::absorb_attrs requires the cell to be attached to a module in a design"); module->design->absorb_attrs(this, std::move(buf)); @@ -5167,22 +5077,22 @@ RTLIL::PortDir RTLIL::Cell::port_dir(TwineRef portname) const return PortDir::PD_UNKNOWN; } -bool RTLIL::Cell::hasParam(TwineRef paramname) const +bool RTLIL::Cell::hasParam(IdString paramname) const { return parameters.count(paramname) != 0; } -void RTLIL::Cell::unsetParam(TwineRef paramname) +void RTLIL::Cell::unsetParam(IdString paramname) { parameters.erase(paramname); } -void RTLIL::Cell::setParam(TwineRef paramname, RTLIL::Const value) +void RTLIL::Cell::setParam(IdString paramname, RTLIL::Const value) { parameters[paramname] = std::move(value); } -const RTLIL::Const &RTLIL::Cell::getParam(TwineRef paramname) const +const RTLIL::Const &RTLIL::Cell::getParam(IdString paramname) const { const auto &it = parameters.find(paramname); if (it != parameters.end()) @@ -5197,7 +5107,7 @@ const RTLIL::Const &RTLIL::Cell::getParam(TwineRef paramname) const void RTLIL::Cell::sort() { - connections_.sort(sort_by_id_str()); + connections_.sort(); parameters.sort(sort_by_id_str()); attributes.sort(sort_by_id_str()); } @@ -5217,67 +5127,67 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) return; if (type == ID($buf) || type == ID($mux) || type == ID($pmux) || type == ID($bmux) || type == ID($bwmux) || type == ID($bweqx)) { - parameters[ID::WIDTH] = GetSize(connections_[ID::Y]); + parameters[ID::WIDTH] = GetSize(connections_[TW::Y]); if (type.in(ID($pmux), ID($bmux))) - parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]); + parameters[ID::S_WIDTH] = GetSize(connections_[TW::S]); check(); return; } if (type == ID($demux)) { - parameters[ID::WIDTH] = GetSize(connections_[ID::A]); - parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]); + parameters[ID::WIDTH] = GetSize(connections_[TW::A]); + parameters[ID::S_WIDTH] = GetSize(connections_[TW::S]); check(); return; } if (type == ID($lut) || type == ID($sop)) { - parameters[ID::WIDTH] = GetSize(connections_[ID::A]); + parameters[ID::WIDTH] = GetSize(connections_[TW::A]); return; } if (type == ID($fa)) { - parameters[ID::WIDTH] = GetSize(connections_[ID::Y]); + parameters[ID::WIDTH] = GetSize(connections_[TW::Y]); return; } if (type == ID($lcu)) { - parameters[ID::WIDTH] = GetSize(connections_[ID::CO]); + parameters[ID::WIDTH] = GetSize(connections_[TW::CO]); return; } if (type == ID($macc_v2)) { - parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]); + parameters[ID::Y_WIDTH] = GetSize(connections_[TW::Y]); return; } bool signedness_ab = !type.in(ID($slice), ID($concat), ID($macc)); - if (connections_.count(ID::A)) { + if (connections_.count(TW::A)) { if (signedness_ab) { if (set_a_signed) parameters[ID::A_SIGNED] = true; else if (parameters.count(ID::A_SIGNED) == 0) parameters[ID::A_SIGNED] = false; } - parameters[ID::A_WIDTH] = GetSize(connections_[ID::A]); + parameters[ID::A_WIDTH] = GetSize(connections_[TW::A]); } - if (connections_.count(ID::B)) { + if (connections_.count(TW::B)) { if (signedness_ab) { if (set_b_signed) parameters[ID::B_SIGNED] = true; else if (parameters.count(ID::B_SIGNED) == 0) parameters[ID::B_SIGNED] = false; } - parameters[ID::B_WIDTH] = GetSize(connections_[ID::B]); + parameters[ID::B_WIDTH] = GetSize(connections_[TW::B]); } - if (connections_.count(ID::Y) && type != ID($concat)) - parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]); + if (connections_.count(TW::Y) && type != ID($concat)) + parameters[ID::Y_WIDTH] = GetSize(connections_[TW::Y]); - if (connections_.count(ID::Q)) - parameters[ID::WIDTH] = GetSize(connections_[ID::Q]); + if (connections_.count(TW::Q)) + parameters[ID::WIDTH] = GetSize(connections_[TW::Q]); check(); } @@ -5619,7 +5529,7 @@ Hasher::hash_t RTLIL::SigSpec::updhash() const for (auto &v : c.data) h.eat(v); } else { - h.eat(c.wire->meta_ ? c.wire->meta_->name_id : Twine::Null); + h.eat(c.wire->meta_ ? c.wire->meta_->name : Twine::Null); h.eat(c.offset); h.eat(c.width); } @@ -6596,7 +6506,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri return false; } - RTLIL::Wire *wire = module->wire(TwineRef(netname)); + RTLIL::Wire *wire = module->wire(module->design->twines.lookup(netname)); if (!indices.empty()) { std::vector index_tokens; sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':'); @@ -6637,7 +6547,7 @@ bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL sig = RTLIL::SigSpec(); RTLIL::Selection &sel = design->selection_vars.at(str); for (auto &it : module->wires_) - if (sel.selected_member(module->name, TwineRef(it.second->name))) + if (sel.selected_member(module->meta_->name, it.second->meta_->name)) sig.append(it.second); return true; @@ -6806,9 +6716,9 @@ void RTLIL::Process::set_src_id(TwineRef id) module->design->obj_set_src_id(this, id); } -void RTLIL::Process::set_src_attribute(const RTLIL::SrcAttr &src) +void RTLIL::Process::set_src_attribute(TwineRef src) { - if (src.empty() && meta_ == nullptr) + if (src == Twine::Null && meta_ == nullptr) return; log_assert(module && module->design && "Process::set_src_attribute requires the process to be attached to a module in a design"); module->design->set_src_attribute(this, src); @@ -6827,7 +6737,7 @@ void RTLIL::Process::adopt_src_from(const RTLIL::AttrObject *source) module->design->adopt_src_from(this, source); } -void RTLIL::Process::absorb_attrs(dict &&buf) +void RTLIL::Process::absorb_attrs(dict &&buf) { log_assert(module && module->design && "Process::absorb_attrs requires the process to be attached to a module in a design"); module->design->absorb_attrs(this, std::move(buf)); @@ -6875,9 +6785,9 @@ void RTLIL::Memory::set_src_id(TwineRef id) module->design->obj_set_src_id(this, id); } -void RTLIL::Memory::set_src_attribute(const RTLIL::SrcAttr &src) +void RTLIL::Memory::set_src_attribute(TwineRef src) { - if (src.empty() && meta_ == nullptr) + if (src == Twine::Null && meta_ == nullptr) return; log_assert(module && module->design && "Memory::set_src_attribute requires the memory to be attached to a module in a design"); module->design->set_src_attribute(this, src); @@ -6896,7 +6806,7 @@ void RTLIL::Memory::adopt_src_from(const RTLIL::AttrObject *source) module->design->adopt_src_from(this, source); } -void RTLIL::Memory::absorb_attrs(dict &&buf) +void RTLIL::Memory::absorb_attrs(dict &&buf) { log_assert(module && module->design && "Memory::absorb_attrs requires the memory to be attached to a module in a design"); module->design->absorb_attrs(this, std::move(buf)); @@ -6915,9 +6825,9 @@ void RTLIL::CaseRule::set_src_id(TwineRef id) log_assert(module && module->design && "CaseRule::set_src_id requires the case to belong to a module in a design"); module->design->obj_set_src_id(this, id); } -void RTLIL::CaseRule::set_src_attribute(const RTLIL::SrcAttr &src) +void RTLIL::CaseRule::set_src_attribute(TwineRef src) { - if (src.empty() && meta_ == nullptr) + if (src == Twine::Null && meta_ == nullptr) return; log_assert(module && module->design && "CaseRule::set_src_attribute requires the case to belong to a module in a design"); module->design->set_src_attribute(this, src); @@ -6933,7 +6843,7 @@ void RTLIL::CaseRule::adopt_src_from(const RTLIL::AttrObject *source) log_assert(module && module->design && "CaseRule::adopt_src_from requires the case to belong to a module in a design"); module->design->adopt_src_from(this, source); } -void RTLIL::CaseRule::absorb_attrs(dict &&buf) +void RTLIL::CaseRule::absorb_attrs(dict &&buf) { log_assert(module && module->design && "CaseRule::absorb_attrs requires the case to belong to a module in a design"); module->design->absorb_attrs(this, std::move(buf)); @@ -6950,9 +6860,9 @@ void RTLIL::SwitchRule::set_src_id(TwineRef id) log_assert(module && module->design && "SwitchRule::set_src_id requires the switch to belong to a module in a design"); module->design->obj_set_src_id(this, id); } -void RTLIL::SwitchRule::set_src_attribute(const RTLIL::SrcAttr &src) +void RTLIL::SwitchRule::set_src_attribute(TwineRef src) { - if (src.empty() && meta_ == nullptr) + if (src == Twine::Null && meta_ == nullptr) return; log_assert(module && module->design && "SwitchRule::set_src_attribute requires the switch to belong to a module in a design"); module->design->set_src_attribute(this, src); @@ -6968,7 +6878,7 @@ void RTLIL::SwitchRule::adopt_src_from(const RTLIL::AttrObject *source) log_assert(module && module->design && "SwitchRule::adopt_src_from requires the switch to belong to a module in a design"); module->design->adopt_src_from(this, source); } -void RTLIL::SwitchRule::absorb_attrs(dict &&buf) +void RTLIL::SwitchRule::absorb_attrs(dict &&buf) { log_assert(module && module->design && "SwitchRule::absorb_attrs requires the switch to belong to a module in a design"); module->design->absorb_attrs(this, std::move(buf)); @@ -6985,9 +6895,9 @@ void RTLIL::MemWriteAction::set_src_id(TwineRef id) log_assert(module && module->design && "MemWriteAction::set_src_id requires the action to belong to a module in a design"); module->design->obj_set_src_id(this, id); } -void RTLIL::MemWriteAction::set_src_attribute(const RTLIL::SrcAttr &src) +void RTLIL::MemWriteAction::set_src_attribute(TwineRef src) { - if (src.empty() && meta_ == nullptr) + if (src == Twine::Null && meta_ == nullptr) return; log_assert(module && module->design && "MemWriteAction::set_src_attribute requires the action to belong to a module in a design"); module->design->set_src_attribute(this, src); @@ -7003,7 +6913,7 @@ void RTLIL::MemWriteAction::adopt_src_from(const RTLIL::AttrObject *source) log_assert(module && module->design && "MemWriteAction::adopt_src_from requires the action to belong to a module in a design"); module->design->adopt_src_from(this, source); } -void RTLIL::MemWriteAction::absorb_attrs(dict &&buf) +void RTLIL::MemWriteAction::absorb_attrs(dict &&buf) { log_assert(module && module->design && "MemWriteAction::absorb_attrs requires the action to belong to a module in a design"); module->design->absorb_attrs(this, std::move(buf)); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 42d4cd792..53bb54bac 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -129,7 +129,6 @@ namespace RTLIL struct OwningIdString; struct StaticIdString; struct SigNormIndex; - struct SrcAttr; struct ObjMeta; struct ModuleNameMasq; struct WireNameMasq; @@ -139,7 +138,6 @@ namespace RTLIL struct PortBit; }; -using SrcAttr = TwineRef; // TODO clean up? extern int64_t signorm_ns; @@ -806,7 +804,7 @@ namespace RTLIL { return log_id(str); } - template struct sort_by_name_id { + template struct sort_by_name { bool operator()(T *a, T *b) const { return a->name < b->name; } @@ -1285,7 +1283,7 @@ struct RTLIL::ObjMeta { TwineRef src = Twine::Null; // RTLIL::IdString name; // used by Module names - TwineRef name_id = Twine::Null; // used by Wire/Cell names (per-Design twines) + TwineRef name = Twine::Null; // used by Wire/Cell names (per-Design twines) }; struct RTLIL::AttrObject @@ -1942,8 +1940,8 @@ struct RTLIL::Selection // add whole module to this selection template void select(T1 *module) { - if (!selects_all() && selected_modules.count(module->meta_->name_id) == 0) { - TwineRef name = module->meta_->name_id; + if (!selects_all() && selected_modules.count(module->meta_->name) == 0) { + TwineRef name = module->meta_->name; selected_modules.insert(name); selected_members.erase(name); if (module->get_blackbox_attribute()) @@ -1992,7 +1990,7 @@ struct RTLIL::Monitor virtual ~Monitor() { } virtual void notify_module_add(RTLIL::Module*) { } virtual void notify_module_del(RTLIL::Module*) { } - virtual void notify_connect(RTLIL::Cell*, RTLIL::IdString, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { } + virtual void notify_connect(RTLIL::Cell*, TwineRef, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { } virtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { } virtual void notify_connect(RTLIL::Module*, const std::vector&) { } virtual void notify_blackout(RTLIL::Module*) { } @@ -2015,7 +2013,7 @@ struct RTLIL::Design void sigNormalize(bool enable=true); int refcount_modules_; - dict modules_; + dict modules_; std::vector bindings_; TwinePool twines; @@ -2035,22 +2033,22 @@ struct RTLIL::Design void obj_release_src(RTLIL::AttrObject *obj); std::string obj_name(const RTLIL::AttrObject *obj) const { - return (obj->meta_ ? twines.flat_string(obj->meta_->name_id) : std::string()); + return (obj->meta_ ? twines.flat_string(obj->meta_->name) : std::string()); } - void obj_set_name(RTLIL::AttrObject *obj, RTLIL::IdString name); - void obj_release_name(RTLIL::AttrObject *obj); + // void obj_set_name(RTLIL::AttrObject *obj, RTLIL::IdString name); + // void obj_release_name(RTLIL::AttrObject *obj); // Wire/Cell names: stored as TwineRef in twines. - TwineRef obj_name_id(const RTLIL::AttrObject *obj) const { - return (obj->meta_ ? obj->meta_->name_id : Twine::Null); - } - void obj_set_name_id(RTLIL::AttrObject *obj, TwineRef id); - void obj_release_name_id(RTLIL::AttrObject *obj); + // TwineRef obj_name(const RTLIL::AttrObject *obj) const { + // return (obj->meta_ ? obj->meta_->name : Twine::Null); + // } + // void obj_set_name(RTLIL::AttrObject *obj, TwineRef id); + // void obj_release_name(RTLIL::AttrObject *obj); // Replacements for the methods that used to live on AttrObject and // took an explicit TwinePool*. Same semantics; the pool resolves // to this->twines internally. - void set_src_attribute(RTLIL::AttrObject *obj, const RTLIL::SrcAttr &src); + void set_src_attribute(RTLIL::AttrObject *obj, TwineRef src); std::string get_src_attribute(const RTLIL::AttrObject *obj) const; void adopt_src_from(RTLIL::AttrObject *obj, const RTLIL::AttrObject *source); void adopt_src_from(RTLIL::AttrObject *obj, const RTLIL::AttrObject *source, @@ -2097,11 +2095,12 @@ struct RTLIL::Design RTLIL::ObjRange modules(); RTLIL::Module *module(IdString name); - // RTLIL::Module *module(TwineRef name); - // const RTLIL::Module *module(TwineRef name) const; + const RTLIL::Module *module(IdString name) const; + RTLIL::Module *module(TwineRef name); + const RTLIL::Module *module(TwineRef name) const; RTLIL::Module *top_module() const; - bool has(IdString id) const { + bool has(TwineRef id) const { return modules_.count(id) != 0; } @@ -2188,7 +2187,7 @@ struct RTLIL::Design // is the given member of the given module in the current selection template bool selected(T1 *module, T2 *member) const { - return selected_member(module->meta_->name_id, member->meta_->name_id); + return selected_member(module->meta_->name, member->meta_->name); } // add whole module to the current selection @@ -2250,7 +2249,7 @@ namespace RTLIL_BACKEND { void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire, const RTLIL::Design *design, bool resolve_src); } -struct RTLIL::Wire : public RTLIL::NamedObject +struct RTLIL::Wire : public RTLIL::AttrObject { private: struct ConstructToken { explicit ConstructToken() = default; }; @@ -2271,7 +2270,7 @@ public: friend void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire, const RTLIL::Design *design, bool resolve_src); RTLIL::Cell *driverCell_ = nullptr; - RTLIL::IdString driverPort_; + TwineRef driverPort_; // do not simply copy wires Wire(ConstructToken, RTLIL::Wire &other); @@ -2286,7 +2285,7 @@ public: TwineRef src_id() const; TwineRef src_ref() const { return src_id(); } void set_src_id(TwineRef id); - void set_src_attribute(const RTLIL::SrcAttr &src); + void set_src_attribute(TwineRef src); std::string get_src_attribute() const; // Transfer src from `source` verbatim (same pool). Asserts attached // to a design. @@ -2296,7 +2295,7 @@ public: bool known_driver() const { return driverCell_ != nullptr; } RTLIL::Cell *driverCell() const { log_assert(driverCell_); return driverCell_; }; - RTLIL::IdString driverPort() const { log_assert(driverCell_); return driverPort_; }; + TwineRef driverPort() const { log_assert(driverCell_); return driverPort_; }; int from_hdl_index(int hdl_index) { int zero_index = hdl_index - start_offset; @@ -2322,7 +2321,7 @@ inline int GetSize(RTLIL::Wire *wire) { return wire->width; } -struct RTLIL::Memory : public RTLIL::NamedObject +struct RTLIL::Memory : public RTLIL::AttrObject { Hasher::hash_t hashidx_; [[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; } @@ -2341,7 +2340,7 @@ struct RTLIL::Memory : public RTLIL::NamedObject TwineRef src_id() const; TwineRef src_ref() const { return src_id(); } void set_src_id(TwineRef id); - void set_src_attribute(const RTLIL::SrcAttr &src); + void set_src_attribute(TwineRef src); std::string get_src_attribute() const; void adopt_src_from(const RTLIL::AttrObject *source); void absorb_attrs(dict &&buf); @@ -2354,7 +2353,7 @@ struct RTLIL::Memory : public RTLIL::NamedObject std::string to_rtlil_str() const; }; -struct RTLIL::Cell : public RTLIL::NamedObject +struct RTLIL::Cell : public RTLIL::AttrObject { private: struct ConstructToken { explicit ConstructToken() = default; }; @@ -2366,9 +2365,9 @@ private: void initIndex(); // Signorm index helpers (used by setPort/unsetPort/initIndex) - void signorm_index_remove(RTLIL::IdString portname, const RTLIL::SigSpec &old_signal, bool is_input); - void signorm_index_add(RTLIL::IdString portname, const RTLIL::SigSpec &new_signal, bool is_input); - bool bufnorm_handle_setPort(RTLIL::IdString portname, RTLIL::SigSpec &signal, dict::iterator conn_it); + void signorm_index_remove(TwineRef portname, const RTLIL::SigSpec &old_signal, bool is_input); + void signorm_index_add(TwineRef portname, const RTLIL::SigSpec &new_signal, bool is_input); + bool bufnorm_handle_setPort(TwineRef portname, RTLIL::SigSpec &signal, dict::iterator conn_it); public: // Shadows NamedObject::name. Reads materialise via twines; writes // are a compile error — use Module::rename(cell, new_name) instead. @@ -2387,7 +2386,7 @@ public: RTLIL::Module *module; IdString type; - dict connections_; + dict connections_; dict parameters; // Context-aware src helpers. Resolve Design via module->design and @@ -2395,7 +2394,7 @@ public: TwineRef src_id() const; TwineRef src_ref() const { return src_id(); } void set_src_id(TwineRef id); - void set_src_attribute(const RTLIL::SrcAttr &src); + void set_src_attribute(TwineRef src); std::string get_src_attribute() const; void adopt_src_from(const RTLIL::AttrObject *source); void absorb_attrs(dict &&buf); @@ -2467,7 +2466,7 @@ struct RTLIL::CaseRule : public RTLIL::AttrObject TwineRef src_id() const; TwineRef src_ref() const { return src_id(); } void set_src_id(TwineRef id); - void set_src_attribute(const RTLIL::SrcAttr &src); + void set_src_attribute(TwineRef src); std::string get_src_attribute() const; void adopt_src_from(const RTLIL::AttrObject *source); void absorb_attrs(dict &&buf); @@ -2495,7 +2494,7 @@ struct RTLIL::SwitchRule : public RTLIL::AttrObject TwineRef src_id() const; TwineRef src_ref() const { return src_id(); } void set_src_id(TwineRef id); - void set_src_attribute(const RTLIL::SrcAttr &src); + void set_src_attribute(TwineRef src); std::string get_src_attribute() const; void adopt_src_from(const RTLIL::AttrObject *source); void absorb_attrs(dict &&buf); @@ -2520,7 +2519,7 @@ struct RTLIL::MemWriteAction : RTLIL::AttrObject TwineRef src_id() const; TwineRef src_ref() const { return src_id(); } void set_src_id(TwineRef id); - void set_src_attribute(const RTLIL::SrcAttr &src); + void set_src_attribute(TwineRef src); std::string get_src_attribute() const; void adopt_src_from(const RTLIL::AttrObject *source); void absorb_attrs(dict &&buf); @@ -2538,7 +2537,7 @@ struct RTLIL::SyncRule RTLIL::SyncRule *clone() const; }; -struct RTLIL::Process : public RTLIL::NamedObject +struct RTLIL::Process : public RTLIL::AttrObject { friend struct RTLIL::SigNormIndex; friend struct RTLIL::Cell; @@ -2563,7 +2562,7 @@ public: TwineRef src_id() const; TwineRef src_ref() const { return src_id(); } void set_src_id(TwineRef id); - void set_src_attribute(const RTLIL::SrcAttr &src); + void set_src_attribute(TwineRef src); std::string get_src_attribute() const; void adopt_src_from(const RTLIL::AttrObject *source); void absorb_attrs(dict &&buf); @@ -2578,9 +2577,9 @@ public: struct RTLIL::PortBit { RTLIL::Cell *cell; - RTLIL::IdString port; + TwineRef port; int offset; - PortBit(Cell* c, IdString p, int o) : cell(c), port(p), offset(o) {} + PortBit(Cell* c, TwineRef p, int o) : cell(c), port(p), offset(o) {} bool operator<(const PortBit &other) const { if (cell != other.cell) @@ -2640,9 +2639,9 @@ inline Hasher RTLIL::SigBit::hash_into(Hasher h) const { inline Hasher RTLIL::SigBit::hash_top() const { Hasher h; if (wire) { - // Use the wire's name_id (TwineRef) directly — avoids IdString materialisation. - TwineRef name_id = wire->meta_ ? wire->meta_->name_id : Twine::Null; - h.eat(name_id); + // Use the wire's name (TwineRef) directly — avoids IdString materialisation. + TwineRef name = wire->meta_ ? wire->meta_->name : Twine::Null; + h.eat(name); h.eat(offset); return h; } @@ -2670,212 +2669,212 @@ class CellAdderMixin { public: // The add* methods create a cell and return the created cell. All signals must exist in advance. - RTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addBuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addNot (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addPos (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addBuf (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addNeg (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addAnd (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addOr (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addXor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addXnor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addReduceAnd (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addReduceOr (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addReduceXor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addReduceXnor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addReduceBool (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addShl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addShr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addSshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addSshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addShift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addShiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addShl (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addShr (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addSshl (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addSshr (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addShift (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addShiftx (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addLt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addLe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addEq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addNe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addEqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addNex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addGe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addGt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addLt (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addLe (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addEq (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addNe (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addEqx (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addNex (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addGe (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addGt (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addAdd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addSub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addMul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addAdd (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addSub (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addMul (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); // truncating division - RTLIL::Cell* addDiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addDiv (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); // truncating modulo - RTLIL::Cell* addMod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addDivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addMod (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addDivFloor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addModFloor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addPow (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addFa (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addLogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addLogicNot (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addLogicAnd (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::Cell* addLogicOr (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::Cell* addMux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addPmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addBmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addDemux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addMux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addPmux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addBmux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addDemux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addBweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addBwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addBweqx (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addBwmux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addSlice (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, TwineRef src = Twine::Null); - RTLIL::Cell* addConcat (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addLut (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, TwineRef src = Twine::Null); - RTLIL::Cell* addTribuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addAssert (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null); - RTLIL::Cell* addAssume (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null); - RTLIL::Cell* addLive (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null); - RTLIL::Cell* addFair (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null); - RTLIL::Cell* addCover (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null); - RTLIL::Cell* addEquiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addSlice (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, TwineRef src = Twine::Null); + RTLIL::Cell* addConcat (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addLut (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, TwineRef src = Twine::Null); + RTLIL::Cell* addTribuf (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addAssert (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null); + RTLIL::Cell* addAssume (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null); + RTLIL::Cell* addLive (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null); + RTLIL::Cell* addFair (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null); + RTLIL::Cell* addCover (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null); + RTLIL::Cell* addEquiv (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addSr (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addFf (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src = Twine::Null); - RTLIL::Cell* addDff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addDffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addDffsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addDffsre (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addAdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addAdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addAldff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addAldffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addSdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addSdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addSdffce (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addDlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addAdlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null); + RTLIL::Cell* addSr (Twine &&name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null); + RTLIL::Cell* addFf (Twine &&name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src = Twine::Null); + RTLIL::Cell* addDff (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, TwineRef src = Twine::Null); + RTLIL::Cell* addDffe (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, TwineRef src = Twine::Null); + RTLIL::Cell* addDffsr (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null); + RTLIL::Cell* addDffsre (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null); + RTLIL::Cell* addAdff (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null); + RTLIL::Cell* addAdffe (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null); + RTLIL::Cell* addAldff (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, TwineRef src = Twine::Null); + RTLIL::Cell* addAldffe (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, TwineRef src = Twine::Null); + RTLIL::Cell* addSdff (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null); + RTLIL::Cell* addSdffe (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null); + RTLIL::Cell* addSdffce (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null); + RTLIL::Cell* addDlatch (Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, TwineRef src = Twine::Null); + RTLIL::Cell* addAdlatch (Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null); + RTLIL::Cell* addDlatchsr (Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addBufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addNotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addAndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addNandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addOrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addNorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addXorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addXnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addAndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addOrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addMuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addNmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addAoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addOai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addAoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addOai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addBufGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addNotGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addAndGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addNandGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addOrGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addNorGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addXorGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addXnorGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addAndnotGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addOrnotGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addMuxGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addNmuxGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addAoi3Gate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addOai3Gate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addAoi4Gate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); + RTLIL::Cell* addOai4Gate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null); - RTLIL::Cell* addSrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, + RTLIL::Cell* addSrGate (Twine &&name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addFfGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src = Twine::Null); - RTLIL::Cell* addDffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addDffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addDffsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, + RTLIL::Cell* addFfGate (Twine &&name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src = Twine::Null); + RTLIL::Cell* addDffGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, TwineRef src = Twine::Null); + RTLIL::Cell* addDffeGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, TwineRef src = Twine::Null); + RTLIL::Cell* addDffsrGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addDffsreGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, + RTLIL::Cell* addDffsreGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addAdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, + RTLIL::Cell* addAdffGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addAdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, + RTLIL::Cell* addAdffeGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool arst_value = false, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addAldffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, + RTLIL::Cell* addAldffGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addAldffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, + RTLIL::Cell* addAldffeGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addSdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, + RTLIL::Cell* addSdffGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool srst_value = false, bool clk_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addSdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, + RTLIL::Cell* addSdffeGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addSdffceGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, + RTLIL::Cell* addSdffceGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addDlatchGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, + RTLIL::Cell* addDlatchGate (Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, TwineRef src = Twine::Null); + RTLIL::Cell* addAdlatchGate(Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool arst_value = false, bool en_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addDlatchsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, + RTLIL::Cell* addDlatchsrGate (Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null); - RTLIL::Cell* addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src = Twine::Null); + RTLIL::Cell* addAnyinit(Twine &&name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src = Twine::Null); // The methods without the add* prefix create a cell and an output signal. They return the newly created output signal. - RTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Buf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Not (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Pos (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Buf (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Neg (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec And (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Or (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Xor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Xnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec And (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Or (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Xor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Xnor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec ReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec ReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec ReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec ReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec ReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec ReduceAnd (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec ReduceOr (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec ReduceXor (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec ReduceXnor (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec ReduceBool (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Shl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Shr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Sshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Sshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Shift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Shiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Shl (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Shr (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Sshl (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Sshr (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Shift (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Shiftx (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Lt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Le (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Eq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Ne (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Eqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Nex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Ge (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Gt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Lt (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Le (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Eq (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Ne (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Eqx (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Nex (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Ge (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Gt (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Add (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Sub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Mul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Add (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Sub (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Mul (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); // truncating division - RTLIL::SigSpec Div (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Div (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); // truncating modulo - RTLIL::SigSpec Mod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec DivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec ModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Pow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Mod (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec DivFloor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec ModFloor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec Pow (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec LogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec LogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec LogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec LogicNot (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec LogicAnd (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); + RTLIL::SigSpec LogicOr (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null); - RTLIL::SigSpec Mux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null); - RTLIL::SigSpec Pmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null); - RTLIL::SigSpec Bmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null); - RTLIL::SigSpec Demux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null); + RTLIL::SigSpec Mux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null); + RTLIL::SigSpec Pmux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null); + RTLIL::SigSpec Bmux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null); + RTLIL::SigSpec Demux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null); - RTLIL::SigSpec Bweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, TwineRef src = Twine::Null); - RTLIL::SigSpec Bwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null); + RTLIL::SigSpec Bweqx (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, TwineRef src = Twine::Null); + RTLIL::SigSpec Bwmux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null); - RTLIL::SigBit BufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, TwineRef src = Twine::Null); - RTLIL::SigBit NotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, TwineRef src = Twine::Null); - RTLIL::SigBit AndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null); - RTLIL::SigBit NandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null); - RTLIL::SigBit OrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null); - RTLIL::SigBit NorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null); - RTLIL::SigBit XorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null); - RTLIL::SigBit XnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null); - RTLIL::SigBit AndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null); - RTLIL::SigBit OrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null); - RTLIL::SigBit MuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, TwineRef src = Twine::Null); - RTLIL::SigBit NmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, TwineRef src = Twine::Null); - RTLIL::SigBit Aoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, TwineRef src = Twine::Null); - RTLIL::SigBit Oai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, TwineRef src = Twine::Null); - RTLIL::SigBit Aoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, TwineRef src = Twine::Null); - RTLIL::SigBit Oai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, TwineRef src = Twine::Null); + RTLIL::SigBit BufGate (Twine &&name, const RTLIL::SigBit &sig_a, TwineRef src = Twine::Null); + RTLIL::SigBit NotGate (Twine &&name, const RTLIL::SigBit &sig_a, TwineRef src = Twine::Null); + RTLIL::SigBit AndGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null); + RTLIL::SigBit NandGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null); + RTLIL::SigBit OrGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null); + RTLIL::SigBit NorGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null); + RTLIL::SigBit XorGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null); + RTLIL::SigBit XnorGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null); + RTLIL::SigBit AndnotGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null); + RTLIL::SigBit OrnotGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null); + RTLIL::SigBit MuxGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, TwineRef src = Twine::Null); + RTLIL::SigBit NmuxGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, TwineRef src = Twine::Null); + RTLIL::SigBit Aoi3Gate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, TwineRef src = Twine::Null); + RTLIL::SigBit Oai3Gate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, TwineRef src = Twine::Null); + RTLIL::SigBit Aoi4Gate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, TwineRef src = Twine::Null); + RTLIL::SigBit Oai4Gate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, TwineRef src = Twine::Null); }; // Zero-size masquerade for Module::name. Reads/writes route through @@ -2961,7 +2960,7 @@ public: TwineRef src_id() const; TwineRef src_ref() const { return src_id(); } void set_src_id(TwineRef id); - void set_src_attribute(const RTLIL::SrcAttr &src); + void set_src_attribute(TwineRef src); std::string get_src_attribute() const; void adopt_src_from(const RTLIL::AttrObject *source); void absorb_attrs(dict &&buf); @@ -2970,7 +2969,7 @@ public: virtual ~Module(); virtual RTLIL::IdString derive(RTLIL::Design *design, const dict ¶meters, bool mayfail = false); virtual RTLIL::IdString derive(RTLIL::Design *design, const dict ¶meters, const dict &interfaces, const dict &modports, bool mayfail = false); - virtual size_t count_id(Twine* id); + virtual size_t count_id(TwineRef id); virtual void expand_interfaces(RTLIL::Design *design, const dict &local_interfaces); virtual bool reprocess_if_necessary(RTLIL::Design *design); @@ -2992,7 +2991,7 @@ public: void fixup_ports(); pool buf_norm_cell_queue; - pool> buf_norm_cell_port_queue; + pool> buf_norm_cell_port_queue; pool buf_norm_wire_queue; pool pending_deleted_cells; dict> buf_norm_connect_index; @@ -3057,7 +3056,7 @@ public: std::vector selected_members() const; template bool selected(T *member) const { - return design->selected_member(name, member->name); + return design->selected_member(meta_->name, member->meta_->name); } // Primary (fast) overloads — key directly into the dict. @@ -3093,29 +3092,35 @@ public: void remove(RTLIL::Memory *memory); void remove(RTLIL::Process *process); - void rename(RTLIL::Wire *wire, RTLIL::IdString new_name); - void rename(RTLIL::Cell *cell, RTLIL::IdString new_name); - void rename(RTLIL::IdString old_name, RTLIL::IdString new_name); + void rename(RTLIL::Wire *wire, TwineRef new_name); + void rename(RTLIL::Cell *cell, TwineRef new_name); + void rename(TwineRef old_name, TwineRef new_name); void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2); void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2); - RTLIL::IdString uniquify(RTLIL::IdString name); - RTLIL::IdString uniquify(RTLIL::IdString name, int &index); + TwineRef uniquify(TwineRef name); + TwineRef uniquify(TwineRef name, int &index); // Primary overloads: name already interned in design->twines. RTLIL::Wire *addWire(TwineRef name, int width = 1); RTLIL::Wire *addWire(TwineRef name, const RTLIL::Wire *other); - // IdString compatibility: interns name into twines, then dispatches. - RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); - RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other); + // Convenience: adds name into twines, then dispatches. + RTLIL::Wire *addWire(Twine &&name, int width = 1); + RTLIL::Wire *addWire(Twine &&name, const RTLIL::Wire *other); // Primary overloads. RTLIL::Cell *addCell(TwineRef name, RTLIL::IdString type); RTLIL::Cell *addCell(TwineRef name, const RTLIL::Cell *other); - // IdString compatibility. - RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); - RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other); + // Convenience. + RTLIL::Cell *addCell(Twine &&name, RTLIL::IdString type); + RTLIL::Cell *addCell(Twine &&name, const RTLIL::Cell *other); + + // NEW_ID analog for twine names; see NEW_TWINE in yosys_common.h. + TwineRef new_name(const std::string *prefix) { + TwineRef pref = design->twines.add(Twine{*prefix}); + return design->twines.add(Twine{Twine::Suffix{pref, std::to_string(autoidx++)}}); + } RTLIL::Memory *addMemory(RTLIL::IdString name); RTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other); @@ -3129,18 +3134,18 @@ public: // The methods without the add* prefix create a cell and an output signal. They return the newly created output signal. - RTLIL::SigSpec Anyconst (RTLIL::IdString name, int width = 1, TwineRef src = Twine::Null); - RTLIL::SigSpec Anyseq (RTLIL::IdString name, int width = 1, TwineRef src = Twine::Null); - RTLIL::SigSpec Allconst (RTLIL::IdString name, int width = 1, TwineRef src = Twine::Null); - RTLIL::SigSpec Allseq (RTLIL::IdString name, int width = 1, TwineRef src = Twine::Null); - RTLIL::SigSpec Initstate (RTLIL::IdString name, TwineRef src = Twine::Null); + RTLIL::SigSpec Anyconst (TwineRef name, int width = 1, TwineRef src = Twine::Null); + RTLIL::SigSpec Anyseq (TwineRef name, int width = 1, TwineRef src = Twine::Null); + RTLIL::SigSpec Allconst (TwineRef name, int width = 1, TwineRef src = Twine::Null); + RTLIL::SigSpec Allseq (TwineRef name, int width = 1, TwineRef src = Twine::Null); + RTLIL::SigSpec Initstate (TwineRef name, TwineRef src = Twine::Null); - RTLIL::SigSpec SetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, TwineRef src = Twine::Null); - RTLIL::Cell* addSetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null); - RTLIL::SigSpec GetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, TwineRef src = Twine::Null); - RTLIL::Cell* addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, TwineRef src = Twine::Null); - RTLIL::SigSpec OriginalTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, TwineRef src = Twine::Null); - RTLIL::SigSpec FutureFF (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, TwineRef src = Twine::Null); + RTLIL::SigSpec SetTag (TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, TwineRef src = Twine::Null); + RTLIL::Cell* addSetTag (TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null); + RTLIL::SigSpec GetTag (TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, TwineRef src = Twine::Null); + RTLIL::Cell* addOverwriteTag (TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, TwineRef src = Twine::Null); + RTLIL::SigSpec OriginalTag (TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, TwineRef src = Twine::Null); + RTLIL::SigSpec FutureFF (TwineRef name, const RTLIL::SigSpec &sig_e, TwineRef src = Twine::Null); std::string to_rtlil_str() const; #ifdef YOSYS_ENABLE_PYTHON @@ -3276,7 +3281,7 @@ inline RTLIL::WireNameMasq::operator RTLIL::IdString() const { reinterpret_cast(this) - offsetof(RTLIL::Wire, name)); if (!w->module || !w->module->design || !w->meta_) return RTLIL::IdString{}; - TwineRef id = w->meta_->name_id; + TwineRef id = w->meta_->name; if (id == Twine::Null) return RTLIL::IdString{}; return RTLIL::IdString(w->module->design->twines.flat_string(id)); @@ -3287,7 +3292,7 @@ inline RTLIL::CellNameMasq::operator RTLIL::IdString() const { reinterpret_cast(this) - offsetof(RTLIL::Cell, name)); if (!c->module || !c->module->design || !c->meta_) return RTLIL::IdString{}; - TwineRef id = c->meta_->name_id; + TwineRef id = c->meta_->name; if (id == Twine::Null) return RTLIL::IdString{}; return RTLIL::IdString(c->module->design->twines.flat_string(id)); diff --git a/kernel/rtlil_bufnorm.cc b/kernel/rtlil_bufnorm.cc index d549c0344..93176e244 100644 --- a/kernel/rtlil_bufnorm.cc +++ b/kernel/rtlil_bufnorm.cc @@ -20,6 +20,7 @@ #include "kernel/yosys.h" #include "kernel/sigtools.h" #include "kernel/modtools.h" +#include "kernel/yosys_common.h" #include #include @@ -28,7 +29,7 @@ YOSYS_NAMESPACE_BEGIN -typedef std::pair cell_port_t; +typedef std::pair cell_port_t; // Since this is kernel code, we only log with yosys_xtrace set to not get // in the way when using `debug` to debug specific passes.q @@ -83,7 +84,7 @@ struct RTLIL::SigNormIndex if (cell->type != ID($input_port)) continue; - auto const &sig_y = cell->getPort(ID::Y); + auto const &sig_y = cell->getPort(TW::Y); Wire *wire; if (sig_y.is_wire() && (wire = sig_y.as_wire())->port_input && !wire->port_output && !input_port_cells.count(wire)) input_port_cells.emplace(wire, cell); @@ -97,16 +98,16 @@ struct RTLIL::SigNormIndex for (auto portname : module->ports) { Wire *wire = module->wire(portname); if (wire->port_input && !wire->port_output && !input_port_cells.count(wire)) { - Cell *cell = module->addCell(NEW_ID, ID($input_port)); + Cell *cell = module->addCell(NEW_TWINE, ID($input_port)); cell->setParam(ID::WIDTH, GetSize(wire)); - cell->setPort(ID::Y, wire); + cell->setPort(TW::Y, wire); input_port_cells.emplace(wire, cell); } } for (auto [wire, cell] : input_port_cells) { wire->driverCell_ = cell; - wire->driverPort_ = ID::Y; + wire->driverPort_ = TW::Y; } } @@ -130,7 +131,7 @@ struct RTLIL::SigNormIndex } } - Wire *wire = module->addWire(NEW_ID, GetSize(sig)); + Wire *wire = module->addWire(NEW_TWINE, GetSize(sig)); wire->driverCell_ = cell; wire->driverPort_ = port; @@ -194,11 +195,11 @@ struct RTLIL::SigNormIndex } if (!connect_lhs.empty()) { - Cell *cell = module->addCell(NEW_ID, ID($connect)); + Cell *cell = module->addCell(NEW_TWINE, ID($connect)); xlog("add connect (1) %s\n", cell->name); cell->setParam(ID::WIDTH, GetSize(connect_lhs)); - cell->setPort(ID::A, std::move(connect_lhs)); - cell->setPort(ID::B, std::move(connect_rhs)); + cell->setPort(TW::A, std::move(connect_lhs)); + cell->setPort(TW::B, std::move(connect_rhs)); } } @@ -287,7 +288,7 @@ void RTLIL::Design::bufNormalize(bool enable) module->buf_norm_cell_port_queue.clear(); for (auto wire : module->wires()) { wire->driverCell_ = nullptr; - wire->driverPort_ = IdString(); + wire->driverPort_ = Twine::Null; } module->buf_norm_connect_index.clear(); } @@ -348,7 +349,7 @@ void RTLIL::Design::sigNormalize(bool enable) for (auto wire : module->wires()) { wire->driverCell_ = nullptr; - wire->driverPort_ = IdString(); + wire->driverPort_ = Twine::Null; } // TODO inefficient? @@ -520,14 +521,14 @@ void RTLIL::Module::remove(RTLIL::Cell *cell) while (!cell->connections_.empty()) cell->unsetPort(cell->connections_.begin()->first); - log_assert(cell->meta_ && cell->meta_->name_id != Twine::Null); - TwineRef cell_id = cell->meta_->name_id; + log_assert(cell->meta_ && cell->meta_->name != Twine::Null); + TwineRef cell_id = cell->meta_->name; log_assert(cells_.count(cell_id) != 0); log_assert(refcount_cells_ == 0); cells_.erase(cell_id); if (design && design->flagBufferedNormalized && buf_norm_cell_queue.count(cell)) { cell->type.clear(); - design->obj_release_name_id(cell); + // design->obj_release_name(cell); pending_deleted_cells.insert(cell); } else { if (sig_norm_index != nullptr) { @@ -561,12 +562,12 @@ void RTLIL::Module::bufNormalize() if (wire->port_input && !wire->port_output) { if (wire->driverCell_ != nullptr && wire->driverCell_->type != ID($input_port)) { wire->driverCell_ = nullptr; - wire->driverPort_.clear(); + wire->driverPort_ = Twine::Null; } if (wire->driverCell_ == nullptr) { - Cell *input_port_cell = addCell(NEW_ID, ID($input_port)); + Cell *input_port_cell = addCell(NEW_TWINE, ID($input_port)); input_port_cell->setParam(ID::WIDTH, GetSize(wire)); - input_port_cell->setPort(ID::Y, wire); // this hits the fast path that doesn't mutate the queues + input_port_cell->setPort(TW::Y, wire); // this hits the fast path that doesn't mutate the queues } } } @@ -593,19 +594,19 @@ void RTLIL::Module::bufNormalize() // because it's not driving an input port or because there already is // another $input_port driver for the same port, we also delete that // $input_port cell. - dict> direct_driven_wires; + dict> direct_driven_wires; // Set of cell ports that need a fresh intermediate wire. These are all // cell ports that drive non-full-wire sigspecs, cell ports driving // module input ports, and cell ports driving wires that are already // driven. - pool> pending_ports; + pool> pending_ports; // This helper will be called for every output/inout cell port that is // already enqueued or becomes reachable when denormalizing $buf or // $connect cells. - auto enqueue_cell_port = [&](Cell *cell, IdString port) { - xlog("processing cell port %s.%s\n", cell, port.unescape()); + auto enqueue_cell_port = [&](Cell *cell, TwineRef port) { + xlog("processing cell port %s.%s\n", cell, design->twines.str(port)); // An empty cell type means the cell got removed if (cell->type.empty()) @@ -632,8 +633,8 @@ void RTLIL::Module::bufNormalize() // TODO: We could defer removing the $buf cells here, and // re-use them in case we would create a new identical cell // later. - log_assert(port == ID::Y); - SigSpec sig_a = cell->getPort(ID::A); + log_assert(port == TW::Y); + SigSpec sig_a = cell->getPort(TW::A); SigSpec sig_y = sig; for (auto const &s : {sig_a, sig}) @@ -662,7 +663,7 @@ void RTLIL::Module::bufNormalize() buf_norm_wire_queue.clear(); return; } else if (cell->type == ID($input_port)) { - log_assert(port == ID::Y); + log_assert(port == TW::Y); if (sig.is_wire()) { Wire *w = sig.as_wire(); if (w->port_input && !w->port_output) { @@ -733,7 +734,7 @@ void RTLIL::Module::bufNormalize() if (wire->driverCell_) { Cell *cell = wire->driverCell_; - IdString port = wire->driverPort_; + TwineRef port = wire->driverPort_; enqueue_cell_port(cell, port); } @@ -744,8 +745,8 @@ void RTLIL::Module::bufNormalize() while (!found->second.empty()) { Cell *connect_cell = *found->second.begin(); log_assert(connect_cell->type == ID($connect)); - SigSpec const &sig_a = connect_cell->getPort(ID::A); - SigSpec const &sig_b = connect_cell->getPort(ID::B); + SigSpec const &sig_a = connect_cell->getPort(TW::A); + SigSpec const &sig_b = connect_cell->getPort(TW::B); xlog("found $connect cell %s: %s <-> %s\n", connect_cell, log_signal(sig_a), log_signal(sig_b)); for (auto &side : {sig_a, sig_b}) for (auto chunk : side.chunks()) @@ -772,7 +773,7 @@ void RTLIL::Module::bufNormalize() log_assert(!cell->type.empty()); log_assert(!pending_deleted_cells.count(cell)); SigSpec const &sig = cell->getPort(port); - Wire *w = addWire(NEW_ID, GetSize(sig)); + Wire *w = addWire(NEW_TWINE, GetSize(sig)); // We update the module level connections, `direct_driven_wires` // and `direct_driven_wires_conflicts` in such a way that they @@ -792,7 +793,7 @@ void RTLIL::Module::bufNormalize() // to keep track of the wires that we still have to update. for (auto wire : wire_queue_entries) { wire->driverCell_ = nullptr; - wire->driverPort_.clear(); + wire->driverPort_ = Twine::Null; } // For the unique driving cell ports fully connected to a full wire, we @@ -912,7 +913,7 @@ void RTLIL::Module::bufNormalize() if (wire->driverCell_ == nullptr) { xlog("wire %s drivers %s\n", wire, log_signal(wire_drivers)); - addBuf(NEW_ID, wire_drivers, wire); + addBuf(NEW_TWINE, wire_drivers, wire); } } @@ -946,10 +947,10 @@ void RTLIL::Module::bufNormalize() if (sig_a.empty()) return; xlog("connect %s <-> %s\n", log_signal(sig_a), log_signal(sig_b)); - Cell *connect_cell = addCell(NEW_ID, ID($connect)); + Cell *connect_cell = addCell(NEW_TWINE, ID($connect)); connect_cell->setParam(ID::WIDTH, GetSize(sig_a)); - connect_cell->setPort(ID::A, sig_a); - connect_cell->setPort(ID::B, sig_b); + connect_cell->setPort(TW::A, sig_a); + connect_cell->setPort(TW::B, sig_b); sig_a = SigSpec(); sig_b = SigSpec(); }; @@ -985,7 +986,7 @@ void RTLIL::Module::bufNormalize() pending_deleted_cells.clear(); } -void RTLIL::Cell::unsetPort(RTLIL::IdString portname) +void RTLIL::Cell::unsetPort(TwineRef portname) { RTLIL::SigSpec signal; auto conn_it = connections_.find(portname); @@ -1000,7 +1001,7 @@ void RTLIL::Cell::unsetPort(RTLIL::IdString portname) mon->notify_connect(this, conn_it->first, conn_it->second, signal); if (yosys_xtrace) { - log("#X# Unconnect %s.%s.%s\n", this->module, this, portname.unescape()); + log("#X# Unconnect %s.%s.%s\n", module, this, module->design->twines.str(portname)); log_backtrace("-X- ", yosys_xtrace-1); } @@ -1026,14 +1027,14 @@ void RTLIL::Cell::unsetPort(RTLIL::IdString portname) log_assert(w->driverCell_ == this); log_assert(w->driverPort_ == portname); w->driverCell_ = nullptr; - w->driverPort_ = IdString(); + w->driverPort_ = Twine::Null; } // bool clear_fanout = true; // if (conn_it->second.is_wire()) { // Wire *w = conn_it->second.as_wire(); // if (w->driverCell_ == this && w->driverPort_ == portname) { // w->driverCell_ = nullptr; - // w->driverPort_ = IdString(); + // w->driverPort_ = Twine::Null; // clear_fanout = false; // } // } @@ -1058,7 +1059,7 @@ void RTLIL::Cell::unsetPort(RTLIL::IdString portname) Wire *w = conn_it->second.as_wire(); if (w->driverCell_ == this && w->driverPort_ == portname) { w->driverCell_ = nullptr; - w->driverPort_ = IdString(); + w->driverPort_ = Twine::Null; module->buf_norm_wire_queue.insert(w); } else if (w->driverCell_) { log_assert(w->driverCell_->getPort(w->driverPort_) == w); @@ -1099,7 +1100,7 @@ static bool ignored_cell(const RTLIL::IdString& type) return type == ID($specify2) || type == ID($specify3) || type == ID($specrule); } -void RTLIL::Cell::signorm_index_remove(IdString portname, const SigSpec &old_signal, bool is_input) +void RTLIL::Cell::signorm_index_remove(TwineRef portname, const SigSpec &old_signal, bool is_input) { auto &index = *module->sig_norm_index; index.dirty.insert(this); @@ -1121,11 +1122,11 @@ void RTLIL::Cell::signorm_index_remove(IdString portname, const SigSpec &old_sig log_assert(w->driverCell_ == this); log_assert(w->driverPort_ == portname); w->driverCell_ = nullptr; - w->driverPort_ = IdString(); + w->driverPort_ = Twine::Null; } } -void RTLIL::Cell::signorm_index_add(IdString portname, const SigSpec &new_signal, bool is_input) +void RTLIL::Cell::signorm_index_add(TwineRef portname, const SigSpec &new_signal, bool is_input) { auto &index = *module->sig_norm_index; index.dirty.insert(this); @@ -1140,7 +1141,7 @@ void RTLIL::Cell::signorm_index_add(IdString portname, const SigSpec &new_signal } else if (GetSize(new_signal)) { Wire *w = new_signal.as_wire(); log_assert(w->driverCell_ == nullptr); - log_assert(w->driverPort_.empty()); + log_assert(w->driverPort_ == Twine::Null); w->driverCell_ = this; w->driverPort_ = portname; } @@ -1148,14 +1149,14 @@ void RTLIL::Cell::signorm_index_add(IdString portname, const SigSpec &new_signal // Handles the bufnorm part of setPort. Updates conn_it->second and returns true if the // connection was stored (fast path or $connect cell). If false, caller must store signal. -bool RTLIL::Cell::bufnorm_handle_setPort(IdString portname, SigSpec &signal, dict::iterator conn_it) +bool RTLIL::Cell::bufnorm_handle_setPort(TwineRef portname, SigSpec &signal, dict::iterator conn_it) { // Eagerly clear a driver that got disconnected by changing this port connection if (conn_it->second.is_wire()) { Wire *w = conn_it->second.as_wire(); if (w->driverCell_ == this && w->driverPort_ == portname) { w->driverCell_ = nullptr; - w->driverPort_ = IdString(); + w->driverPort_ = Twine::Null; module->buf_norm_wire_queue.insert(w); } } @@ -1260,7 +1261,7 @@ void RTLIL::Cell::setPort(TwineRef portname, RTLIL::SigSpec signal) if (signal.is_wire() && (wire = signal.as_wire())->driverCell_ != nullptr) wire = nullptr; if (wire == nullptr) { - wire = module->addWire(NEW_ID, GetSize(signal)); + wire = module->addWire(NEW_TWINE, GetSize(signal)); module->connect(signal, wire); signal = wire; } @@ -1282,7 +1283,7 @@ void RTLIL::Cell::setPort(TwineRef portname, RTLIL::SigSpec signal) } if (yosys_xtrace) { - log("#X# Connect %s.%s.%s = %s (%d)\n", this->module ? this->module->name.unescape() : "PATCH", this, portname.unescape(), log_signal(signal), GetSize(signal)); + log("#X# Connect %s.%s.%s = %s (%d)\n", module ? module->name.unescape() : "PATCH", this, module->design->twines.str(portname), log_signal(signal), GetSize(signal)); log_backtrace("-X- ", yosys_xtrace-1); } @@ -1302,9 +1303,9 @@ void RTLIL::Cell::setPort(TwineRef portname, RTLIL::SigSpec signal) void RTLIL::Design::add(RTLIL::Module *module) { - log_assert(modules_.count(module->name) == 0); + log_assert(modules_.count(module->meta_->name) == 0); log_assert(refcount_modules_ == 0); - modules_[module->name] = module; + modules_[module->meta_->name] = module; module->design = this; for (auto mon : monitors) diff --git a/kernel/satgen.cc b/kernel/satgen.cc index e9c27cae1..fedcc26f8 100644 --- a/kernel/satgen.cc +++ b/kernel/satgen.cc @@ -30,9 +30,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (model_undef && (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor)) || is_arith_compare)) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep); if (is_arith_compare) extendSignalWidth(undef_a, undef_b, cell, true); else @@ -43,7 +43,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) int undef_y_bit = ez->OR(undef_any_a, undef_any_b); if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) { - std::vector b = importSigSpec(cell->getPort(ID::B), timestep); + std::vector b = importSigSpec(cell->getPort(TW::B), timestep); undef_y_bit = ez->OR(undef_y_bit, ez->NOT(ez->expression(ezSAT::OpOr, b))); } @@ -62,9 +62,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($sub))) { - std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); - std::vector b = importDefSigSpec(cell->getPort(ID::B), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); + std::vector a = importDefSigSpec(cell->getPort(TW::A), timestep); + std::vector b = importDefSigSpec(cell->getPort(TW::B), timestep); + std::vector y = importDefSigSpec(cell->getPort(TW::Y), timestep); extendSignalWidth(a, b, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -92,9 +92,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (model_undef && !arith_undef_handled) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep); extendSignalWidth(undef_a, undef_b, undef_y, cell, false); if (cell->type.in(ID($and), ID($_AND_), ID($_NAND_))) { @@ -133,7 +133,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) } else if (model_undef) { - std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep); undefGating(y, yy, undef_y); } return true; @@ -144,11 +144,11 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) bool aoi_mode = cell->type.in(ID($_AOI3_), ID($_AOI4_)); bool three_mode = cell->type.in(ID($_AOI3_), ID($_OAI3_)); - int a = importDefSigSpec(cell->getPort(ID::A), timestep).at(0); - int b = importDefSigSpec(cell->getPort(ID::B), timestep).at(0); - int c = importDefSigSpec(cell->getPort(ID::C), timestep).at(0); - int d = three_mode ? (aoi_mode ? ez->CONST_TRUE : ez->CONST_FALSE) : importDefSigSpec(cell->getPort(ID::D), timestep).at(0); - int y = importDefSigSpec(cell->getPort(ID::Y), timestep).at(0); + int a = importDefSigSpec(cell->getPort(TW::A), timestep).at(0); + int b = importDefSigSpec(cell->getPort(TW::B), timestep).at(0); + int c = importDefSigSpec(cell->getPort(TW::C), timestep).at(0); + int d = three_mode ? (aoi_mode ? ez->CONST_TRUE : ez->CONST_FALSE) : importDefSigSpec(cell->getPort(TW::D), timestep).at(0); + int y = importDefSigSpec(cell->getPort(TW::Y), timestep).at(0); int yy = model_undef ? ez->literal() : y; if (cell->type.in(ID($_AOI3_), ID($_AOI4_))) @@ -158,11 +158,11 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (model_undef) { - int undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep).at(0); - int undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep).at(0); - int undef_c = importUndefSigSpec(cell->getPort(ID::C), timestep).at(0); - int undef_d = three_mode ? ez->CONST_FALSE : importUndefSigSpec(cell->getPort(ID::D), timestep).at(0); - int undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep).at(0); + int undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep).at(0); + int undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep).at(0); + int undef_c = importUndefSigSpec(cell->getPort(TW::C), timestep).at(0); + int undef_d = three_mode ? ez->CONST_FALSE : importUndefSigSpec(cell->getPort(TW::D), timestep).at(0); + int undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep).at(0); if (aoi_mode) { @@ -207,16 +207,16 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type.in(ID($_NOT_), ID($not))) { - std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); + std::vector a = importDefSigSpec(cell->getPort(TW::A), timestep); + std::vector y = importDefSigSpec(cell->getPort(TW::Y), timestep); extendSignalWidthUnary(a, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; ez->assume(ez->vec_eq(ez->vec_not(a), yy)); if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep); extendSignalWidthUnary(undef_a, undef_y, cell, false); ez->assume(ez->vec_eq(undef_a, undef_y)); undefGating(y, yy, undef_y); @@ -226,17 +226,17 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type == ID($bweqx)) { - std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); - std::vector b = importDefSigSpec(cell->getPort(ID::B), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); + std::vector a = importDefSigSpec(cell->getPort(TW::A), timestep); + std::vector b = importDefSigSpec(cell->getPort(TW::B), timestep); + std::vector y = importDefSigSpec(cell->getPort(TW::Y), timestep); std::vector bweqx = ez->vec_not(ez->vec_xor(a, b)); if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep); std::vector both_undef = ez->vec_and(undef_a, undef_b); std::vector both_def = ez->vec_and(ez->vec_not(undef_a), ez->vec_not(undef_b)); @@ -252,10 +252,10 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type.in(ID($_MUX_), ID($mux), ID($_NMUX_), ID($bwmux))) { - std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); - std::vector b = importDefSigSpec(cell->getPort(ID::B), timestep); - std::vector s = importDefSigSpec(cell->getPort(ID::S), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); + std::vector a = importDefSigSpec(cell->getPort(TW::A), timestep); + std::vector b = importDefSigSpec(cell->getPort(TW::B), timestep); + std::vector s = importDefSigSpec(cell->getPort(TW::S), timestep); + std::vector y = importDefSigSpec(cell->getPort(TW::Y), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; if (cell->type == ID($_NMUX_)) @@ -267,10 +267,10 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); - std::vector undef_s = importUndefSigSpec(cell->getPort(ID::S), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep); + std::vector undef_s = importUndefSigSpec(cell->getPort(TW::S), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep); std::vector unequal_ab = ez->vec_not(ez->vec_iff(a, b)); std::vector undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b)); @@ -287,16 +287,16 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type == ID($bmux)) { - std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); - std::vector s = importDefSigSpec(cell->getPort(ID::S), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); + std::vector a = importDefSigSpec(cell->getPort(TW::A), timestep); + std::vector s = importDefSigSpec(cell->getPort(TW::S), timestep); + std::vector y = importDefSigSpec(cell->getPort(TW::Y), timestep); std::vector undef_a, undef_s, undef_y; if (model_undef) { - undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); - undef_s = importUndefSigSpec(cell->getPort(ID::S), timestep); - undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); + undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep); + undef_s = importUndefSigSpec(cell->getPort(TW::S), timestep); + undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep); } if (GetSize(s) == 0) { @@ -335,17 +335,17 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type == ID($demux)) { - std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); - std::vector s = importDefSigSpec(cell->getPort(ID::S), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); + std::vector a = importDefSigSpec(cell->getPort(TW::A), timestep); + std::vector s = importDefSigSpec(cell->getPort(TW::S), timestep); + std::vector y = importDefSigSpec(cell->getPort(TW::Y), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; std::vector undef_a, undef_s, undef_y; if (model_undef) { - undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); - undef_s = importUndefSigSpec(cell->getPort(ID::S), timestep); - undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); + undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep); + undef_s = importUndefSigSpec(cell->getPort(TW::S), timestep); + undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep); } if (GetSize(s) == 0) { @@ -387,10 +387,10 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type == ID($pmux)) { - std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); - std::vector b = importDefSigSpec(cell->getPort(ID::B), timestep); - std::vector s = importDefSigSpec(cell->getPort(ID::S), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); + std::vector a = importDefSigSpec(cell->getPort(TW::A), timestep); + std::vector b = importDefSigSpec(cell->getPort(TW::B), timestep); + std::vector s = importDefSigSpec(cell->getPort(TW::S), timestep); + std::vector y = importDefSigSpec(cell->getPort(TW::Y), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -403,10 +403,10 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); - std::vector undef_s = importUndefSigSpec(cell->getPort(ID::S), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep); + std::vector undef_s = importUndefSigSpec(cell->getPort(TW::S), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep); int all_undef = ez->CONST_FALSE; int found_active = ez->CONST_FALSE; @@ -433,8 +433,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type.in(ID($pos), ID($buf), ID($neg))) { - std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); + std::vector a = importDefSigSpec(cell->getPort(TW::A), timestep); + std::vector y = importDefSigSpec(cell->getPort(TW::Y), timestep); extendSignalWidthUnary(a, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -448,8 +448,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep); extendSignalWidthUnary(undef_a, undef_y, cell); if (cell->type.in(ID($pos), ID($buf))) { @@ -467,8 +467,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type.in(ID($connect))) { - std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); - std::vector b = importDefSigSpec(cell->getPort(ID::B), timestep); + std::vector a = importDefSigSpec(cell->getPort(TW::A), timestep); + std::vector b = importDefSigSpec(cell->getPort(TW::B), timestep); extendSignalWidthUnary(a, b, cell); std::vector bb = model_undef ? ez->vec_var(b.size()) : b; @@ -476,8 +476,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep); extendSignalWidthUnary(undef_a, undef_b, cell); ez->assume(ez->vec_eq(undef_a, undef_b)); undefGating(b, bb, undef_b); @@ -487,8 +487,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($logic_not))) { - std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); + std::vector a = importDefSigSpec(cell->getPort(TW::A), timestep); + std::vector y = importDefSigSpec(cell->getPort(TW::Y), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -507,8 +507,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep); int aX = ez->expression(ezSAT::OpOr, undef_a); if (cell->type == ID($reduce_and)) { @@ -534,12 +534,12 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type.in(ID($logic_and), ID($logic_or))) { - std::vector vec_a = importDefSigSpec(cell->getPort(ID::A), timestep); - std::vector vec_b = importDefSigSpec(cell->getPort(ID::B), timestep); + std::vector vec_a = importDefSigSpec(cell->getPort(TW::A), timestep); + std::vector vec_b = importDefSigSpec(cell->getPort(TW::B), timestep); int a = ez->expression(ez->OpOr, vec_a); int b = ez->expression(ez->OpOr, vec_b); - std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); + std::vector y = importDefSigSpec(cell->getPort(TW::Y), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -552,9 +552,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep); int a0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_a), ez->expression(ezSAT::OpOr, undef_a))); int b0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_b), ez->expression(ezSAT::OpOr, undef_b))); @@ -581,16 +581,16 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) { bool is_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool(); - std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); - std::vector b = importDefSigSpec(cell->getPort(ID::B), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); + std::vector a = importDefSigSpec(cell->getPort(TW::A), timestep); + std::vector b = importDefSigSpec(cell->getPort(TW::B), timestep); + std::vector y = importDefSigSpec(cell->getPort(TW::Y), timestep); extendSignalWidth(a, b, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; if (model_undef && cell->type.in(ID($eqx), ID($nex))) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep); extendSignalWidth(undef_a, undef_b, cell, true); a = ez->vec_or(a, undef_a); b = ez->vec_or(b, undef_b); @@ -613,9 +613,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (model_undef && cell->type.in(ID($eqx), ID($nex))) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep); extendSignalWidth(undef_a, undef_b, cell, true); if (cell->type == ID($eqx)) @@ -630,9 +630,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) } else if (model_undef && cell->type.in(ID($eq), ID($ne))) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep); extendSignalWidth(undef_a, undef_b, cell, true); int undef_any_a = ez->expression(ezSAT::OpOr, undef_a); @@ -654,7 +654,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) else { if (model_undef) { - std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep); undefGating(y, yy, undef_y); } log_assert(!model_undef || arith_undef_handled); @@ -664,9 +664,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) { - std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); - std::vector b = importDefSigSpec(cell->getPort(ID::B), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); + std::vector a = importDefSigSpec(cell->getPort(TW::A), timestep); + std::vector b = importDefSigSpec(cell->getPort(TW::B), timestep); + std::vector y = importDefSigSpec(cell->getPort(TW::Y), timestep); int extend_bit = ez->CONST_FALSE; @@ -697,9 +697,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep); std::vector undef_a_shifted; extend_bit = cell->type == ID($shiftx) ? ez->CONST_TRUE : ez->CONST_FALSE; @@ -736,9 +736,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type == ID($mul)) { - std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); - std::vector b = importDefSigSpec(cell->getPort(ID::B), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); + std::vector a = importDefSigSpec(cell->getPort(TW::A), timestep); + std::vector b = importDefSigSpec(cell->getPort(TW::B), timestep); + std::vector y = importDefSigSpec(cell->getPort(TW::Y), timestep); extendSignalWidth(a, b, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -755,7 +755,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (model_undef) { log_assert(arith_undef_handled); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep); undefGating(y, yy, undef_y); } return true; @@ -763,8 +763,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type.in(ID($macc), ID($macc_v2))) { - std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); + std::vector a = importDefSigSpec(cell->getPort(TW::A), timestep); + std::vector y = importDefSigSpec(cell->getPort(TW::Y), timestep); Macc macc; macc.from_cell(cell); @@ -807,19 +807,19 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep); std::vector undef_c; if (cell->type == ID($macc_v2)) - undef_c = importUndefSigSpec(cell->getPort(ID::C), timestep); + undef_c = importUndefSigSpec(cell->getPort(TW::C), timestep); int undef_any_a = ez->expression(ezSAT::OpOr, undef_a); int undef_any_b = ez->expression(ezSAT::OpOr, undef_b); int undef_any_c = ez->expression(ezSAT::OpOr, undef_c); int undef_any = ez->OR(undef_any_a, ez->OR(undef_any_b, undef_any_c)); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep); ez->assume(ez->vec_eq(undef_y, std::vector(GetSize(y), undef_any))); undefGating(y, tmp, undef_y); @@ -832,9 +832,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) { - std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); - std::vector b = importDefSigSpec(cell->getPort(ID::B), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); + std::vector a = importDefSigSpec(cell->getPort(TW::A), timestep); + std::vector b = importDefSigSpec(cell->getPort(TW::B), timestep); + std::vector y = importDefSigSpec(cell->getPort(TW::Y), timestep); extendSignalWidth(a, b, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -913,12 +913,12 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) only_first_one.at(0) = ez->CONST_TRUE; div_zero_result = ez->vec_ite(a.back(), only_first_one, all_ones); } else { - div_zero_result.insert(div_zero_result.end(), cell->getPort(ID::A).size(), ez->CONST_TRUE); + div_zero_result.insert(div_zero_result.end(), cell->getPort(TW::A).size(), ez->CONST_TRUE); div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->CONST_FALSE); } } else if (cell->type.in(ID($mod), ID($modfloor))) { // a mod 0 = a - int copy_a_bits = min(cell->getPort(ID::A).size(), cell->getPort(ID::B).size()); + int copy_a_bits = min(cell->getPort(TW::A).size(), cell->getPort(TW::B).size()); div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits); if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool()) div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back()); @@ -930,7 +930,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (model_undef) { log_assert(arith_undef_handled); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep); undefGating(y, yy, undef_y); } return true; @@ -938,8 +938,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type == ID($lut)) { - std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); + std::vector a = importDefSigSpec(cell->getPort(TW::A), timestep); + std::vector y = importDefSigSpec(cell->getPort(TW::Y), timestep); std::vector lut; for (auto bit : cell->getParam(ID::LUT)) @@ -950,7 +950,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep); std::vector t(lut), u(GetSize(t), ez->CONST_FALSE); for (int i = GetSize(a)-1; i >= 0; i--) @@ -968,7 +968,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) log_assert(GetSize(t) == 1); log_assert(GetSize(u) == 1); undefGating(y, t, u); - ez->assume(ez->vec_eq(importUndefSigSpec(cell->getPort(ID::Y), timestep), u)); + ez->assume(ez->vec_eq(importUndefSigSpec(cell->getPort(TW::Y), timestep), u)); } else { @@ -988,8 +988,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type == ID($sop)) { - std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); - int y = importDefSigSpec(cell->getPort(ID::Y), timestep).at(0); + std::vector a = importDefSigSpec(cell->getPort(TW::A), timestep); + int y = importDefSigSpec(cell->getPort(TW::Y), timestep).at(0); int width = cell->getParam(ID::WIDTH).as_int(); int depth = cell->getParam(ID::DEPTH).as_int(); @@ -1017,8 +1017,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (model_undef) { std::vector products, undef_products; - std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); - int undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep).at(0); + std::vector undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep); + int undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep).at(0); for (int i = 0; i < depth; i++) { @@ -1070,11 +1070,11 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type == ID($fa)) { - std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); - std::vector b = importDefSigSpec(cell->getPort(ID::B), timestep); - std::vector c = importDefSigSpec(cell->getPort(ID::C), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); - std::vector x = importDefSigSpec(cell->getPort(ID::X), timestep); + std::vector a = importDefSigSpec(cell->getPort(TW::A), timestep); + std::vector b = importDefSigSpec(cell->getPort(TW::B), timestep); + std::vector c = importDefSigSpec(cell->getPort(TW::C), timestep); + std::vector y = importDefSigSpec(cell->getPort(TW::Y), timestep); + std::vector x = importDefSigSpec(cell->getPort(TW::X), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; std::vector xx = model_undef ? ez->vec_var(x.size()) : x; @@ -1088,12 +1088,12 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); - std::vector undef_c = importUndefSigSpec(cell->getPort(ID::C), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep); + std::vector undef_c = importUndefSigSpec(cell->getPort(TW::C), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); - std::vector undef_x = importUndefSigSpec(cell->getPort(ID::X), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep); + std::vector undef_x = importUndefSigSpec(cell->getPort(TW::X), timestep); ez->assume(ez->vec_eq(undef_y, ez->vec_or(ez->vec_or(undef_a, undef_b), undef_c))); ez->assume(ez->vec_eq(undef_x, undef_y)); @@ -1106,10 +1106,10 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type == ID($lcu)) { - std::vector p = importDefSigSpec(cell->getPort(ID::P), timestep); - std::vector g = importDefSigSpec(cell->getPort(ID::G), timestep); - std::vector ci = importDefSigSpec(cell->getPort(ID::CI), timestep); - std::vector co = importDefSigSpec(cell->getPort(ID::CO), timestep); + std::vector p = importDefSigSpec(cell->getPort(TW::P), timestep); + std::vector g = importDefSigSpec(cell->getPort(TW::G), timestep); + std::vector ci = importDefSigSpec(cell->getPort(TW::CI), timestep); + std::vector co = importDefSigSpec(cell->getPort(TW::CO), timestep); std::vector yy = model_undef ? ez->vec_var(co.size()) : co; @@ -1118,10 +1118,10 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (model_undef) { - std::vector undef_p = importUndefSigSpec(cell->getPort(ID::P), timestep); - std::vector undef_g = importUndefSigSpec(cell->getPort(ID::G), timestep); - std::vector undef_ci = importUndefSigSpec(cell->getPort(ID::CI), timestep); - std::vector undef_co = importUndefSigSpec(cell->getPort(ID::CO), timestep); + std::vector undef_p = importUndefSigSpec(cell->getPort(TW::P), timestep); + std::vector undef_g = importUndefSigSpec(cell->getPort(TW::G), timestep); + std::vector undef_ci = importUndefSigSpec(cell->getPort(TW::CI), timestep); + std::vector undef_co = importUndefSigSpec(cell->getPort(TW::CO), timestep); int undef_any_p = ez->expression(ezSAT::OpOr, undef_p); int undef_any_g = ez->expression(ezSAT::OpOr, undef_g); @@ -1138,13 +1138,13 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type == ID($alu)) { - std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); - std::vector b = importDefSigSpec(cell->getPort(ID::B), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); - std::vector x = importDefSigSpec(cell->getPort(ID::X), timestep); - std::vector ci = importDefSigSpec(cell->getPort(ID::CI), timestep); - std::vector bi = importDefSigSpec(cell->getPort(ID::BI), timestep); - std::vector co = importDefSigSpec(cell->getPort(ID::CO), timestep); + std::vector a = importDefSigSpec(cell->getPort(TW::A), timestep); + std::vector b = importDefSigSpec(cell->getPort(TW::B), timestep); + std::vector y = importDefSigSpec(cell->getPort(TW::Y), timestep); + std::vector x = importDefSigSpec(cell->getPort(TW::X), timestep); + std::vector ci = importDefSigSpec(cell->getPort(TW::CI), timestep); + std::vector bi = importDefSigSpec(cell->getPort(TW::BI), timestep); + std::vector co = importDefSigSpec(cell->getPort(TW::CO), timestep); extendSignalWidth(a, b, y, cell); extendSignalWidth(a, b, x, cell); @@ -1169,14 +1169,14 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); - std::vector undef_ci = importUndefSigSpec(cell->getPort(ID::CI), timestep); - std::vector undef_bi = importUndefSigSpec(cell->getPort(ID::BI), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep); + std::vector undef_ci = importUndefSigSpec(cell->getPort(TW::CI), timestep); + std::vector undef_bi = importUndefSigSpec(cell->getPort(TW::BI), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); - std::vector undef_x = importUndefSigSpec(cell->getPort(ID::X), timestep); - std::vector undef_co = importUndefSigSpec(cell->getPort(ID::CO), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep); + std::vector undef_x = importUndefSigSpec(cell->getPort(TW::X), timestep); + std::vector undef_co = importUndefSigSpec(cell->getPort(TW::CO), timestep); extendSignalWidth(undef_a, undef_b, undef_y, cell); extendSignalWidth(undef_a, undef_b, undef_x, cell); @@ -1204,17 +1204,17 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type == ID($slice)) { - RTLIL::SigSpec a = cell->getPort(ID::A); - RTLIL::SigSpec y = cell->getPort(ID::Y); + RTLIL::SigSpec a = cell->getPort(TW::A); + RTLIL::SigSpec y = cell->getPort(TW::Y); ez->assume(signals_eq(a.extract(cell->parameters.at(ID::OFFSET).as_int(), y.size()), y, timestep)); return true; } if (cell->type == ID($concat)) { - RTLIL::SigSpec a = cell->getPort(ID::A); - RTLIL::SigSpec b = cell->getPort(ID::B); - RTLIL::SigSpec y = cell->getPort(ID::Y); + RTLIL::SigSpec a = cell->getPort(TW::A); + RTLIL::SigSpec b = cell->getPort(TW::B); + RTLIL::SigSpec y = cell->getPort(TW::Y); RTLIL::SigSpec ab = a; ab.append(b); @@ -1233,18 +1233,18 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (timestep == 1) { - initial_state.add((*sigmap)(cell->getPort(ID::Q))); + initial_state.add((*sigmap)(cell->getPort(TW::Q))); if (model_undef && def_formal) { - std::vector undef_q = importUndefSigSpec(cell->getPort(ID::Q), timestep); + std::vector undef_q = importUndefSigSpec(cell->getPort(TW::Q), timestep); ez->assume(ez->NOT(ez->vec_reduce_or(undef_q))); } } else { - std::vector d = importDefSigSpec(cell->getPort(ID::D), timestep-1); + std::vector d = importDefSigSpec(cell->getPort(TW::D), timestep-1); std::vector undef_d; if (model_undef) - undef_d = importUndefSigSpec(cell->getPort(ID::D), timestep-1); + undef_d = importUndefSigSpec(cell->getPort(TW::D), timestep-1); if (ff.has_srst && ff.has_ce && ff.ce_over_srst) { int srst = importDefSigSpec(ff.sig_srst, timestep-1).at(0); std::vector rval = importDefSigSpec(ff.val_srst, timestep-1); @@ -1287,14 +1287,14 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) else std::tie(d, undef_d) = mux(srst, undef_srst, rval, undef_rval, d, undef_d); } - std::vector q = importDefSigSpec(cell->getPort(ID::Q), timestep); + std::vector q = importDefSigSpec(cell->getPort(TW::Q), timestep); std::vector qq = model_undef ? ez->vec_var(q.size()) : q; ez->assume(ez->vec_eq(d, qq)); if (model_undef) { - std::vector undef_q = importUndefSigSpec(cell->getPort(ID::Q), timestep); + std::vector undef_q = importUndefSigSpec(cell->getPort(TW::Q), timestep); ez->assume(ez->vec_eq(undef_d, undef_q)); undefGating(q, qq, undef_q); @@ -1307,22 +1307,22 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) { if (timestep < 2) { if (model_undef && def_formal) { - std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep); ez->assume(ez->NOT(ez->vec_reduce_or(undef_y))); } return true; } - std::vector d = importDefSigSpec(cell->getPort(ID::Y), timestep-1); - std::vector q = importDefSigSpec(cell->getPort(ID::Y), timestep); + std::vector d = importDefSigSpec(cell->getPort(TW::Y), timestep-1); + std::vector q = importDefSigSpec(cell->getPort(TW::Y), timestep); std::vector qq = (model_undef && !def_formal) ? ez->vec_var(q.size()) : q; ez->assume(ez->vec_eq(d, qq)); if (model_undef) { - std::vector undef_d = importUndefSigSpec(cell->getPort(ID::Y), timestep-1); - std::vector undef_q = importUndefSigSpec(cell->getPort(ID::Y), timestep); + std::vector undef_d = importUndefSigSpec(cell->getPort(TW::Y), timestep-1); + std::vector undef_q = importUndefSigSpec(cell->getPort(TW::Y), timestep); if (def_formal) { for (auto &undef_q_bit : undef_q) @@ -1338,7 +1338,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type == ID($anyseq)) { if (model_undef && def_formal) { - std::vector undef_q = importUndefSigSpec(cell->getPort(ID::Y), timestep); + std::vector undef_q = importUndefSigSpec(cell->getPort(TW::Y), timestep); for (auto &undef_q_bit : undef_q) ez->SET(ez->CONST_FALSE, undef_q_bit); } @@ -1347,16 +1347,16 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type.in(ID($_BUF_), ID($equiv))) { - std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); + std::vector a = importDefSigSpec(cell->getPort(TW::A), timestep); + std::vector y = importDefSigSpec(cell->getPort(TW::Y), timestep); extendSignalWidthUnary(a, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; ez->assume(ez->vec_eq(a, yy)); if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep); extendSignalWidthUnary(undef_a, undef_y, cell, false); ez->assume(ez->vec_eq(undef_a, undef_y)); undefGating(y, yy, undef_y); @@ -1370,12 +1370,12 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (initstates.count(key) == 0) initstates[key] = false; - std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); + std::vector y = importDefSigSpec(cell->getPort(TW::Y), timestep); log_assert(GetSize(y) == 1); ez->SET(y[0], initstates[key] ? ez->CONST_TRUE : ez->CONST_FALSE); if (model_undef) { - std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep); log_assert(GetSize(undef_y) == 1); ez->SET(undef_y[0], ez->CONST_FALSE); } @@ -1386,16 +1386,16 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) if (cell->type == ID($assert)) { std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); - asserts_a[pf].append((*sigmap)(cell->getPort(ID::A))); - asserts_en[pf].append((*sigmap)(cell->getPort(ID::EN))); + asserts_a[pf].append((*sigmap)(cell->getPort(TW::A))); + asserts_en[pf].append((*sigmap)(cell->getPort(TW::EN))); return true; } if (cell->type == ID($assume)) { std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); - assumes_a[pf].append((*sigmap)(cell->getPort(ID::A))); - assumes_en[pf].append((*sigmap)(cell->getPort(ID::EN))); + assumes_a[pf].append((*sigmap)(cell->getPort(TW::A))); + assumes_en[pf].append((*sigmap)(cell->getPort(TW::EN))); return true; } diff --git a/kernel/sigtools.h b/kernel/sigtools.h index 7962eaa70..59be817d8 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -233,9 +233,9 @@ struct SigSet template class SigSet::value>::type> : public SigSet> {}; template -using sort_by_name_id_guard = typename std::enable_if::value>::type; +using sort_by_name_guard = typename std::enable_if::value>::type; template -class SigSet> : public SigSet::type>> {}; +class SigSet> : public SigSet::type>> {}; struct SigMapView { diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h index e2e094b62..1d8841832 100644 --- a/kernel/timinginfo.h +++ b/kernel/timinginfo.h @@ -98,11 +98,11 @@ struct TimingInfo for (auto cell : module->cells()) { if (cell->type == ID($specify2)) { - auto en = cell->getPort(ID::EN); + auto en = cell->getPort(TW::EN); if (en.is_fully_const() && !en.as_bool()) continue; - auto src = cell->getPort(ID::SRC); - auto dst = cell->getPort(ID::DST); + auto src = cell->getPort(TW::SRC); + auto dst = cell->getPort(TW::DST); for (const auto &c : src.chunks()) if (!c.wire || !c.wire->port_input) log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", module, cell, log_signal(src)); @@ -136,8 +136,8 @@ struct TimingInfo } } else if (cell->type == ID($specify3)) { - auto src = cell->getPort(ID::SRC).as_bit(); - auto dst = cell->getPort(ID::DST); + auto src = cell->getPort(TW::SRC).as_bit(); + auto dst = cell->getPort(TW::DST); if (!src.wire || !src.wire->port_input) log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", module, cell, log_signal(src)); for (const auto &c : dst.chunks()) @@ -163,8 +163,8 @@ struct TimingInfo IdString type = cell->getParam(ID::TYPE).decode_string(); if (type != ID($setup) && type != ID($setuphold)) continue; - auto src = cell->getPort(ID::SRC); - auto dst = cell->getPort(ID::DST).as_bit(); + auto src = cell->getPort(TW::SRC); + auto dst = cell->getPort(TW::DST).as_bit(); for (const auto &c : src.chunks()) if (!c.wire || !c.wire->port_input) log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", module, cell, log_signal(src)); diff --git a/kernel/twine.h b/kernel/twine.h index 540eff1a7..c59fbc8db 100644 --- a/kernel/twine.h +++ b/kernel/twine.h @@ -23,6 +23,9 @@ struct TwinePool; using TwineRef = size_t; +// Tags TwineChildPool-local refs; never set on refs handed out by TwinePool. +constexpr TwineRef TWINE_LOCAL_BIT = TwineRef(1) << 63; + enum : short { STATIC_TWINE_BEGIN = 0, #define X(N) IDX_##N, @@ -195,6 +198,68 @@ struct TwinePool { return ref; } + size_t size() const { return backing.size(); } + + TwineRef concat(std::span ids) { + if (ids.size() == 1) + return ids[0]; + return add(Twine{std::vector(ids.begin(), ids.end())}); + } + + TwineRef copy_from(const TwinePool& src, TwineRef ref) { + if (ref == Twine::Null || ref < STATIC_TWINE_END) + return ref; + const Twine& t = src[ref]; + if (t.is_leaf()) + return add(Twine{t.leaf()}); + if (t.is_concat()) { + std::vector children; + children.reserve(t.children().size()); + for (TwineRef c : t.children()) + children.push_back(copy_from(src, c)); + return add(Twine{std::move(children)}); + } + if (t.is_suffix()) + return add(Twine{Twine::Suffix{copy_from(src, t.suffix().prefix), t.suffix().tail}}); + return Twine::Null; + } + + // linear deep scan; only for rare by-string lookups + TwineRef lookup(std::string_view sv) const; + + // Erases every backing node not reachable from `roots`; refs to + // surviving nodes stay valid. Returns the number of erased nodes. + template + size_t gc(const Pool& roots) { + std::unordered_set live; + for (TwineRef ref : roots) + mark_live(ref, live); + size_t erased = 0; + for (auto it = backing.begin(); it != backing.end();) { + TwineRef ref = STATIC_TWINE_END + backing.get_index(it); + if (live.count(ref)) { + ++it; + } else { + index.erase(ref); + it = backing.erase(it); + erased++; + } + } + return erased; + } + + void mark_live(TwineRef ref, std::unordered_set& live) const { + if (ref == Twine::Null || ref < STATIC_TWINE_END || !live.insert(ref).second) + return; + const Twine& t = (*this)[ref]; + if (t.is_concat()) { + for (TwineRef c : t.children()) + mark_live(c, live); + } else if (t.is_suffix()) { + mark_live(t.suffix().prefix, live); + } + } + void dump(std::ostream& os = std::cout) const { os << "--- TwinePool Dump (" << backing.size() << " nodes) ---\n"; for (auto it = backing.begin(); it != backing.end(); ++it) { @@ -368,6 +433,67 @@ struct DeepTwineEq { } }; +// Parallel-safe staging while the parent stays read-only; nodes may reference parent refs and earlier local refs +struct TwineChildPool { + const TwinePool* parent; + std::vector local_; + std::vector remap_; + + TwineChildPool(const TwinePool* parent) : parent(parent) {} + + static bool is_local(TwineRef ref) { + return ref != Twine::Null && (ref & TWINE_LOCAL_BIT); + } + + const Twine& operator[] (TwineRef ref) const { + if (is_local(ref)) + return local_[ref & ~TWINE_LOCAL_BIT]; + return (*parent)[ref]; + } + + TwineRef add(Twine t) { + local_.push_back(std::move(t)); + return (local_.size() - 1) | TWINE_LOCAL_BIT; + } + + bool empty() const { return local_.empty(); } + + // serial phase only; dest must be *parent; resolve() covers refs added since the previous commit + void commit_into(TwinePool& dest) { + remap_.clear(); + remap_.reserve(local_.size()); + for (Twine& t : local_) { + if (t.is_concat()) { + for (TwineRef& c : std::get>(t.data)) + c = resolve(c); + } else if (t.is_suffix()) { + std::get(t.data).prefix = resolve(std::get(t.data).prefix); + } + remap_.push_back(dest.add(std::move(t))); + } + local_.clear(); + } + + TwineRef resolve(TwineRef ref) const { + if (!is_local(ref)) + return ref; + return remap_[ref & ~TWINE_LOCAL_BIT]; + } +}; + +inline TwineRef TwinePool::lookup(std::string_view sv) const { + DeepTwineEq eq{this}; + for (TwineRef ref = 0; ref < globals_.size(); ref++) + if (eq(ref, sv)) + return ref; + for (auto it = backing.begin(); it != backing.end(); ++it) { + TwineRef ref = STATIC_TWINE_END + backing.get_index(it); + if (eq(ref, sv)) + return ref; + } + return Twine::Null; +} + struct TwineSearch { TwinePool* pool; std::unordered_set index; diff --git a/kernel/unstable/patch.cc b/kernel/unstable/patch.cc index 1f669a889..aa8adf7d0 100644 --- a/kernel/unstable/patch.cc +++ b/kernel/unstable/patch.cc @@ -10,7 +10,7 @@ using namespace RTLIL; template class CellAdderMixin; -Cell* Patch::addCell(IdString name, IdString type) { +Cell* Patch::addCell(TwineRef name, IdString type) { cells_.push_back(std::make_unique(Cell::ConstructToken{})); Cell* cell = cells_.back().get(); @@ -20,7 +20,11 @@ Cell* Patch::addCell(IdString name, IdString type) { return cell; } -Wire* Patch::addWire(IdString name, int width) { +Cell* Patch::addCell(Twine &&name, IdString type) { + return addCell(twine_staging.add(std::move(name)), type); +} + +Wire* Patch::addWire(TwineRef name, int width) { wires_.push_back(std::make_unique(Wire::ConstructToken{})); Wire* wire = wires_.back().get(); @@ -30,11 +34,15 @@ Wire* Patch::addWire(IdString name, int width) { return wire; } +Wire* Patch::addWire(Twine &&name, int width) { + return addWire(twine_staging.add(std::move(name)), width); +} + // TODO code golf -RTLIL::Wire *RTLIL::Patch::addWire(RTLIL::IdString name, const RTLIL::Wire *other) +RTLIL::Wire *RTLIL::Patch::addWire(TwineRef name, const RTLIL::Wire *other) { - RTLIL::Wire *wire = addWire(std::move(name)); + RTLIL::Wire *wire = addWire(name); wire->width = other->width; wire->start_offset = other->start_offset; wire->port_id = other->port_id; @@ -46,32 +54,44 @@ RTLIL::Wire *RTLIL::Patch::addWire(RTLIL::IdString name, const RTLIL::Wire *othe return wire; } +RTLIL::Wire *RTLIL::Patch::addWire(Twine &&name, const RTLIL::Wire *other) +{ + return addWire(twine_staging.add(std::move(name)), other); +} + +TwineRef Patch::new_name(const std::string *prefix) { + TwineRef pref; + if (auto it = staged_prefix_cache_.find(prefix); it != staged_prefix_cache_.end()) + pref = it->second; + else + pref = staged_prefix_cache_[prefix] = twine_staging.add(Twine{*prefix}); + return twine_staging.add(Twine{Twine::Suffix{pref, std::to_string(autoidx++)}}); +} + Wire* Patch::commit_wire(std::unique_ptr wire) { Wire* raw = wire.release(); - IdString name = staged_wire_names_.at(raw); + TwineRef id = twine_staging.resolve(staged_wire_names_.at(raw)); staged_wire_names_.erase(raw); - TwineRef id = mod->design->twines.intern(name.str()); - mod->design->obj_set_name_id(raw, id); - mod->design->twines.release(id); - mod->wires_[raw->meta_->name_id] = raw; + raw->meta_->name = id; + mod->wires_[raw->meta_->name] = raw; raw->module = mod; return raw; } Cell* Patch::commit_cell(std::unique_ptr cell) { Cell* raw = cell.release(); - IdString name = staged_cell_names_.at(raw); + TwineRef id = twine_staging.resolve(staged_cell_names_.at(raw)); staged_cell_names_.erase(raw); - TwineRef id = mod->design->twines.intern(name.str()); - mod->design->obj_set_name_id(raw, id); - mod->design->twines.release(id); + raw->meta_->name = id; raw->module = mod; - mod->cells_[raw->meta_->name_id] = raw; + mod->cells_[raw->meta_->name] = raw; raw->initIndex(); return raw; } std::vector Patch::commit_staged() { + twine_staging.commit_into(mod->design->twines); + staged_prefix_cache_.clear(); std::vector committed; committed.reserve(cells_.size()); for (auto& cell : cells_) { @@ -86,6 +106,12 @@ std::vector Patch::commit_staged() { } namespace { + std::string port_name(Cell* cell, TwineRef port) { + if (cell->module && cell->module->design) + return cell->module->design->twines.str(port); + return ""; + } + void apply_src(Module* mod, Cell* root, const std::vector& extras, const std::vector& targets, Cell* merge_src_into) { @@ -107,25 +133,24 @@ namespace { push(merge_src_into); if (ids.empty()) return; - TwineRef merged = pool.concat(std::span{ids}); + TwineRef merged = ids.size() == 1 ? ids[0] : pool.add(Twine{std::move(ids)}); if (ys_debug()) { log_debug("twine: merge yields %s (pool size %zu)\n", - pool.format_ref(merged).c_str(), pool.size()); + pool.str(merged).c_str(), pool.backing.size()); if (ys_debug(2)) - pool.dump("twine pool state"); + pool.dump(); } for (Cell* c : targets) c->set_src_id(merged); if (merge_src_into) merge_src_into->set_src_id(merged); - pool.release(merged); } // Verifies via newcelltypes that root_cell has exactly one output port // and that it matches `expected_port`. - void assert_single_output(Cell* root_cell, IdString expected_port) { + void assert_single_output(Cell* root_cell, TwineRef expected_port) { int count = 0; - IdString found; + TwineRef found = Twine::Null; for (auto &[port, sig] : root_cell->connections()) { if (root_cell->output(port)) { found = port; @@ -138,11 +163,11 @@ namespace { if (found != expected_port) log_error("Patch: cell %s of type %s sole output port %s does not match patched port %s\n", log_id(root_cell->name), log_id(root_cell->type), - log_id(found), log_id(expected_port)); + port_name(root_cell, found).c_str(), port_name(root_cell, expected_port).c_str()); } } -void Patch::patch(Cell* root_cell, IdString old_port, SigSpec new_sig, +void Patch::patch(Cell* root_cell, TwineRef old_port, SigSpec new_sig, const std::vector& extras, Cell* merge_src_into) { assert_single_output(root_cell, old_port); @@ -150,11 +175,11 @@ void Patch::patch(Cell* root_cell, IdString old_port, SigSpec new_sig, SigSpec old_sig = root_cell->getPort(old_port); if (old_sig.size() != new_sig.size()) log_error("patch size mismatch on cell %s port %s: old %d (%s) vs new %d (%s)\n", - log_id(root_cell->name), log_id(old_port), + log_id(root_cell->name), port_name(root_cell, old_port).c_str(), old_sig.size(), log_signal(old_sig), new_sig.size(), log_signal(new_sig)); log_debug("patching %s %s which is %s with %s\n", - log_id(root_cell->name), log_id(old_port), + log_id(root_cell->name), port_name(root_cell, old_port).c_str(), log_signal(old_sig), log_signal(new_sig)); std::vector committed = commit_staged(); @@ -174,22 +199,22 @@ void Patch::patch(Cell* root_cell, IdString old_port, SigSpec new_sig, } void Patch::patch_ports(Cell* root_cell, - const std::vector>& port_replacements, + const std::vector>& port_replacements, const std::vector& extras, Cell* merge_src_into) { // Verify each listed port is an output of root_cell and that the // replacements cover every output port of root_cell. - pool listed; + pool listed; std::vector old_sigs; old_sigs.reserve(port_replacements.size()); for (auto &[port, new_sig] : port_replacements) { if (!root_cell->output(port)) log_error("patch_ports: cell %s of type %s port %s is not an output\n", - log_id(root_cell->name), log_id(root_cell->type), log_id(port)); + log_id(root_cell->name), log_id(root_cell->type), port_name(root_cell, port).c_str()); SigSpec old_sig = root_cell->getPort(port); if (old_sig.size() != new_sig.size()) log_error("patch_ports size mismatch on cell %s port %s: old %d (%s) vs new %d (%s)\n", - log_id(root_cell->name), log_id(port), + log_id(root_cell->name), port_name(root_cell, port).c_str(), old_sig.size(), log_signal(old_sig), new_sig.size(), log_signal(new_sig)); listed.insert(port); @@ -198,7 +223,7 @@ void Patch::patch_ports(Cell* root_cell, for (auto &[port, sig] : root_cell->connections()) if (root_cell->output(port) && !listed.count(port)) log_error("patch_ports: cell %s of type %s has output port %s not in port_replacements\n", - log_id(root_cell->name), log_id(root_cell->type), log_id(port)); + log_id(root_cell->name), log_id(root_cell->type), port_name(root_cell, port).c_str()); std::vector committed = commit_staged(); apply_src(mod, root_cell, extras, committed, merge_src_into); @@ -207,7 +232,7 @@ void Patch::patch_ports(Cell* root_cell, // shell before we wire old_sigs to new_sigs. Doing this first ensures // the old port signals are not briefly double-driven by root_cell and // the new connection. - std::vector all_ports; + std::vector all_ports; all_ports.reserve(root_cell->connections().size()); for (auto &[port, sig] : root_cell->connections()) all_ports.push_back(port); @@ -226,6 +251,8 @@ void Patch::patch_ports(Cell* root_cell, } void Patch::commit_inheriting_src(Cell* src_source) { + twine_staging.commit_into(mod->design->twines); + staged_prefix_cache_.clear(); for (auto& cell : cells_) { cell->fixup_parameters(); Cell *committed = commit_cell(std::move(cell)); diff --git a/kernel/unstable/patch.h b/kernel/unstable/patch.h index 029c02c53..5d3c1ab50 100644 --- a/kernel/unstable/patch.h +++ b/kernel/unstable/patch.h @@ -26,8 +26,10 @@ public: SigMap* map; vector> wires_ = {}; vector> cells_ = {}; - dict staged_cell_names_; - dict staged_wire_names_; + TwineChildPool twine_staging; + dict staged_cell_names_; + dict staged_wire_names_; + dict staged_prefix_cache_; void connect(const RTLIL::SigSig &conn); void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); @@ -64,16 +66,29 @@ public: // tracking carries through transparently). Pass nullptr for src_source // if the staged helpers have no natural ancestor. void commit_inheriting_src(Cell* src_source); - RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); - RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other); - RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); - RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other); + // Primary overloads: name is a design ref or a twine_staging-local ref. + RTLIL::Wire *addWire(TwineRef name, int width = 1); + RTLIL::Wire *addWire(TwineRef name, const RTLIL::Wire *other); + // Convenience: stages name into twine_staging, then dispatches. + RTLIL::Wire *addWire(Twine &&name, int width = 1); + RTLIL::Wire *addWire(Twine &&name, const RTLIL::Wire *other); - RTLIL::Cell* addDffsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, + RTLIL::Cell *addCell(TwineRef name, RTLIL::IdString type); + RTLIL::Cell *addCell(TwineRef name, const RTLIL::Cell *other); + RTLIL::Cell *addCell(Twine &&name, RTLIL::IdString type); + RTLIL::Cell *addCell(Twine &&name, const RTLIL::Cell *other); + + // NEW_ID analog for twine names; see NEW_TWINE in yosys_common.h. + // Returned refs are twine_staging-local and die at the next commit. + TwineRef new_name(const std::string *prefix); + + RTLIL::Cell* addDffsr(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src); - Patch(Module* mod, SigMap* map = nullptr) : mod(mod), map(map) {} + Patch(Module* mod, SigMap* map = nullptr) : + mod(mod), map(map), + twine_staging(mod && mod->design ? &mod->design->twines : nullptr) {} }; YOSYS_NAMESPACE_END diff --git a/kernel/wallace_tree.h b/kernel/wallace_tree.h index eb3513803..7da7ed04a 100644 --- a/kernel/wallace_tree.h +++ b/kernel/wallace_tree.h @@ -21,8 +21,8 @@ YOSYS_NAMESPACE_BEGIN inline std::pair emit_fa(Module *module, SigSpec a, SigSpec b, SigSpec c, int width) { - SigSpec sum = module->addWire(NEW_ID, width); - SigSpec cout = module->addWire(NEW_ID, width); + SigSpec sum = module->addWire(NEW_TWINE, width); + SigSpec cout = module->addWire(NEW_TWINE, width); module->addFa(NEW_ID, a, b, c, cout, sum); diff --git a/kernel/yosys_common.h b/kernel/yosys_common.h index 062036dba..11197052d 100644 --- a/kernel/yosys_common.h +++ b/kernel/yosys_common.h @@ -304,6 +304,16 @@ RTLIL::IdString new_id_suffix(std::string_view file, int line, std::string_view }(__FUNCTION__)) #define NEW_ID_SUFFIX(suffix) \ YOSYS_NAMESPACE_PREFIX new_id_suffix(__FILE__, __LINE__, __FUNCTION__, suffix) +#define NEW_TWINE \ + YOSYS_NAMESPACE_PREFIX Twine{*[](std::string_view func) -> const std::string * { \ + static std::unique_ptr prefix(YOSYS_NAMESPACE_PREFIX create_id_prefix(__FILE__, __LINE__, func)); \ + return prefix.get(); \ + }(__FUNCTION__) + std::to_string(YOSYS_NAMESPACE_PREFIX autoidx++)} +#define NEW_TWINE_SUFFIX(suffix) \ + YOSYS_NAMESPACE_PREFIX Twine{*[](std::string_view func) -> const std::string * { \ + static std::unique_ptr prefix(YOSYS_NAMESPACE_PREFIX create_id_prefix(__FILE__, __LINE__, func)); \ + return prefix.get(); \ + }(__FUNCTION__) + std::string(suffix) + "$" + std::to_string(YOSYS_NAMESPACE_PREFIX autoidx++)} namespace ID = RTLIL::ID; diff --git a/passes/cmds/abstract.cc b/passes/cmds/abstract.cc index c4840fefc..0016302b3 100644 --- a/passes/cmds/abstract.cc +++ b/passes/cmds/abstract.cc @@ -102,7 +102,7 @@ void emit_mux_anyseq(Module* mod, const SigSpec& mux_input, const SigSpec& mux_o } bool abstract_state_port(FfData& ff, SigSpec& port_sig, std::set offsets, EnableLogic enable) { - Wire* abstracted = ff.module->addWire(NEW_ID, offsets.size()); + Wire* abstracted = ff.module->addWire(NEW_TWINE, offsets.size()); SigSpec mux_input; int abstracted_idx = 0; for (int d_idx = 0; d_idx < ff.width; d_idx++) { @@ -213,7 +213,7 @@ unsigned int abstract_state(Module* mod, EnableLogic enable, const std::vector offsets, IdString port_name, EnableLogic enable) { - Wire* to_abstract = mod->addWire(NEW_ID, offsets.size()); + Wire* to_abstract = mod->addWire(NEW_TWINE, offsets.size()); SigSpec mux_input; SigSpec mux_output; const SigSpec& old_port = cell->getPort(port_name); @@ -235,7 +235,7 @@ bool abstract_value_cell_port(Module* mod, Cell* cell, std::set offsets, Id } bool abstract_value_mod_port(Module* mod, Wire* wire, std::set offsets, EnableLogic enable) { - Wire* to_abstract = mod->addWire(NEW_ID, wire); + Wire* to_abstract = mod->addWire(NEW_TWINE, wire); to_abstract->port_input = true; to_abstract->port_id = wire->port_id; wire->port_input = false; @@ -507,7 +507,7 @@ struct AbstractPass : public Pass { case Enable::Initstates: { SigBit in_init_states = mod->Initstate(NEW_ID); for (int i = 1; i < initstates; i++) { - Wire *in_init_states_q = mod->addWire(NEW_ID); + Wire *in_init_states_q = mod->addWire(NEW_TWINE); mod->addFf(NEW_ID, in_init_states, in_init_states_q); in_init_states_q->attributes[ID::init] = State::S1; in_init_states = in_init_states_q; diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 1011a093c..8e5165cf8 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -41,10 +41,10 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const log_error("Could not find wire with name \"%s\".\n", name); } else { - RTLIL::Cell *formal_cell = module->addCell(NEW_ID, "$" + celltype); - formal_cell->setPort(ID::A, wire); + RTLIL::Cell *formal_cell = module->addCell(NEW_TWINE, "$" + celltype); + formal_cell->setPort(TW::A, wire); if(enable_name == "") { - formal_cell->setPort(ID::EN, State::S1); + formal_cell->setPort(TW::EN, State::S1); log("Added $%s cell for wire \"%s.%s\"\n", celltype, module->name.str(), name); } else { @@ -52,7 +52,7 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const if(enable_wire == nullptr) log_error("Could not find enable wire with name \"%s\".\n", enable_name); - formal_cell->setPort(ID::EN, enable_wire); + formal_cell->setPort(TW::EN, enable_wire); log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype, module->name.str(), name, module->name.str(), enable_name); } } diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc index 4f6589fc3..085c15940 100644 --- a/passes/cmds/bugpoint.cc +++ b/passes/cmds/bugpoint.cc @@ -306,7 +306,7 @@ struct BugpointPass : public Pass { if (!stage2 && (cell->input(it.first) || cell->output(it.first)) && index++ == seed) { log_header(design, "Trying to expose cell port %s.%s.%s as module port.\n", mod, cell, it.first.unescape()); - RTLIL::Wire *wire = mod->addWire(NEW_ID, port.size()); + RTLIL::Wire *wire = mod->addWire(NEW_TWINE, port.size()); wire->set_bool_attribute(ID($bugpoint)); wire->port_input = cell->input(it.first); wire->port_output = cell->output(it.first); diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index fd0d91aac..89656abcf 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -304,8 +304,8 @@ struct CheckPass : public Pass { if (cell->type.in(ID($pmux), ID($bmux))) { // We're skipping inputs A and B, since each of their bits contributes only one edge - in_widths = GetSize(cell->getPort(ID::S)); - out_widths = GetSize(cell->getPort(ID::Y)); + in_widths = GetSize(cell->getPort(TW::S)); + out_widths = GetSize(cell->getPort(TW::Y)); } else { for (auto &conn : cell->connections()) { if (cell->input(conn.first)) @@ -370,8 +370,8 @@ struct CheckPass : public Pass { if (cell->type == ID($connect)) { // Inefficient, but rare case in sane design - auto sig_a = cell->getPort(ID::A); - auto sig_b = cell->getPort(ID::B); + auto sig_a = cell->getPort(TW::A); + auto sig_b = cell->getPort(TW::B); for (int i = 0; i < sig_a.size(); i++) { int count_a = wire_drivers_count[sig_a[i]]; int count_b = wire_drivers_count[sig_b[i]]; @@ -561,7 +561,7 @@ struct CheckPass : public Pass { if (cell->is_builtin_ff() == 0) continue; - for (auto bit : sigmap(cell->getPort(ID::Q))) + for (auto bit : sigmap(cell->getPort(TW::Q))) init_bits.erase(bit); } diff --git a/passes/cmds/chformal.cc b/passes/cmds/chformal.cc index 946c55358..0239b1f69 100644 --- a/passes/cmds/chformal.cc +++ b/passes/cmds/chformal.cc @@ -275,15 +275,15 @@ struct ChformalPass : public Pass { for (auto cell : module->selected_cells()) { if (cell->type == ID($ff)) { - SigSpec D = sigmap(cell->getPort(ID::D)); - SigSpec Q = sigmap(cell->getPort(ID::Q)); + SigSpec D = sigmap(cell->getPort(TW::D)); + SigSpec Q = sigmap(cell->getPort(TW::Q)); for (int i = 0; i < GetSize(D); i++) ffmap[Q[i]] = make_pair(D[i], make_pair(State::Sm, false)); } if (cell->type == ID($dff)) { - SigSpec D = sigmap(cell->getPort(ID::D)); - SigSpec Q = sigmap(cell->getPort(ID::Q)); - SigSpec C = sigmap(cell->getPort(ID::CLK)); + SigSpec D = sigmap(cell->getPort(TW::D)); + SigSpec Q = sigmap(cell->getPort(TW::Q)); + SigSpec C = sigmap(cell->getPort(TW::CLK)); bool clockpol = cell->getParam(ID::CLK_POLARITY).as_bool(); for (int i = 0; i < GetSize(D); i++) ffmap[Q[i]] = make_pair(D[i], make_pair(C, clockpol)); @@ -295,7 +295,7 @@ struct ChformalPass : public Pass { if (is_triggered_check_cell(cell)) { if (cell->getParam(ID::TRG_WIDTH).as_int() != 1) continue; - cell->setPort(ID::TRG, SigSpec()); + cell->setPort(TW::TRG, SigSpec()); cell->setParam(ID::TRG_ENABLE, false); cell->setParam(ID::TRG_WIDTH, 0); cell->setParam(ID::TRG_POLARITY, false); @@ -305,8 +305,8 @@ struct ChformalPass : public Pass { while (true) { - SigSpec A = sigmap(cell->getPort(ID::A)); - SigSpec EN = sigmap(cell->getPort(ID::EN)); + SigSpec A = sigmap(cell->getPort(TW::A)); + SigSpec EN = sigmap(cell->getPort(TW::EN)); if (ffmap.count(A) == 0 || ffmap.count(EN) == 0) break; @@ -322,8 +322,8 @@ struct ChformalPass : public Pass { if (A_map.second != EN_map.second) break; - cell->setPort(ID::A, A_map.first); - cell->setPort(ID::EN, EN_map.first); + cell->setPort(TW::A, A_map.first); + cell->setPort(TW::EN, EN_map.first); } } } @@ -337,18 +337,18 @@ struct ChformalPass : public Pass { for (int i = 0; i < mode_arg; i++) { - SigSpec orig_a = cell->getPort(ID::A); - SigSpec orig_en = cell->getPort(ID::EN); + SigSpec orig_a = cell->getPort(TW::A); + SigSpec orig_en = cell->getPort(TW::EN); - Wire *new_a = module->addWire(NEW_ID); - Wire *new_en = module->addWire(NEW_ID); + Wire *new_a = module->addWire(NEW_TWINE); + Wire *new_en = module->addWire(NEW_TWINE); new_en->attributes[ID::init] = State::S0; module->addFf(NEW_ID, orig_a, new_a); module->addFf(NEW_ID, orig_en, new_en); - cell->setPort(ID::A, new_a); - cell->setPort(ID::EN, new_en); + cell->setPort(TW::A, new_a); + cell->setPort(TW::EN, new_en); } } } @@ -358,14 +358,14 @@ struct ChformalPass : public Pass { SigSpec en = State::S1; for (int i = 0; i < mode_arg; i++) { - Wire *w = module->addWire(NEW_ID); + Wire *w = module->addWire(NEW_TWINE); w->attributes[ID::init] = State::S0; module->addFf(NEW_ID, en, w); en = w; } for (auto cell : constr_cells) - cell->setPort(ID::EN, module->LogicAnd(NEW_ID, en, cell->getPort(ID::EN))); + cell->setPort(TW::EN, module->LogicAnd(NEW_ID, en, cell->getPort(TW::EN))); } else if (mode =='p') @@ -373,7 +373,7 @@ struct ChformalPass : public Pass { for (auto cell : constr_cells) { if (cell->type == ID($check)) { - Cell *cover = module->addCell(NEW_ID_SUFFIX("coverenable"), ID($check)); + Cell *cover = module->addCell(NEW_TWINE_SUFFIX("coverenable"), ID($check)); cover->attributes = cell->attributes; if (cell->src_id() != Twine::Null && module->design) cover->set_src_id(cell->src_id()); @@ -383,11 +383,11 @@ struct ChformalPass : public Pass { for (auto const &conn : cell->connections()) if (!conn.first.in(ID::A, ID::EN)) cover->setPort(conn.first, conn.second); - cover->setPort(ID::A, cell->getPort(ID::EN)); - cover->setPort(ID::EN, State::S1); + cover->setPort(TW::A, cell->getPort(TW::EN)); + cover->setPort(TW::EN, State::S1); } else { module->addCover(NEW_ID_SUFFIX("coverenable"), - cell->getPort(ID::EN), State::S1, cell->get_src_attribute()); + cell->getPort(TW::EN), State::S1, cell->get_src_attribute()); } } } @@ -419,17 +419,17 @@ struct ChformalPass : public Pass { log_error("Cannot lower edge triggered $check cell %s, run async2sync or clk2fflogic first.\n", cell); - Cell *plain_cell = module->addCell(NEW_ID, formal_flavor(cell)); + Cell *plain_cell = module->addCell(NEW_TWINE, formal_flavor(cell)); plain_cell->attributes = cell->attributes; if (cell->src_id() != Twine::Null && module->design) plain_cell->set_src_id(cell->src_id()); - SigBit sig_a = cell->getPort(ID::A); - SigBit sig_en = cell->getPort(ID::EN); + SigBit sig_a = cell->getPort(TW::A); + SigBit sig_en = cell->getPort(TW::EN); - plain_cell->setPort(ID::A, sig_a); - plain_cell->setPort(ID::EN, sig_en); + plain_cell->setPort(TW::A, sig_a); + plain_cell->setPort(TW::EN, sig_en); if (plain_cell->type.in(ID($assert), ID($assume))) sig_a = module->Not(NEW_ID, sig_a); @@ -438,12 +438,12 @@ struct ChformalPass : public Pass { module->swap_names(cell, plain_cell); - if (cell->getPort(ID::ARGS).empty()) { + if (cell->getPort(TW::ARGS).empty()) { module->remove(cell); } else { cell->type = ID($print); - cell->setPort(ID::EN, combined_en); - cell->unsetPort(ID::A); + cell->setPort(TW::EN, combined_en); + cell->unsetPort(TW::A); cell->unsetParam(ID(FLAVOR)); } } diff --git a/passes/cmds/clean_zerowidth.cc b/passes/cmds/clean_zerowidth.cc index d48d3a958..615daf437 100644 --- a/passes/cmds/clean_zerowidth.cc +++ b/passes/cmds/clean_zerowidth.cc @@ -77,7 +77,7 @@ struct CleanZeroWidthPass : public Pass { // Coarse FF cells: remove if WIDTH == 0 (no outputs). // This will also trigger on fine cells, so use the Q port // width instead of actual WIDTH parameter. - if (GetSize(cell->getPort(ID::Q)) == 0) { + if (GetSize(cell->getPort(TW::Q)) == 0) { module->remove(cell); } } else if (cell->type.in(ID($pmux), ID($bmux), ID($demux))) { @@ -87,17 +87,17 @@ struct CleanZeroWidthPass : public Pass { module->remove(cell); } if (cell->getParam(ID::S_WIDTH).as_int() == 0) { - module->connect(cell->getPort(ID::Y), cell->getPort(ID::A)); + module->connect(cell->getPort(TW::Y), cell->getPort(TW::A)); module->remove(cell); } } else if (cell->type == ID($concat)) { // If a concat has a zero-width input: replace with direct // connection to the other input. if (cell->getParam(ID::A_WIDTH).as_int() == 0) { - module->connect(cell->getPort(ID::Y), cell->getPort(ID::B)); + module->connect(cell->getPort(TW::Y), cell->getPort(TW::B)); module->remove(cell); } else if (cell->getParam(ID::B_WIDTH).as_int() == 0) { - module->connect(cell->getPort(ID::Y), cell->getPort(ID::A)); + module->connect(cell->getPort(TW::Y), cell->getPort(TW::A)); module->remove(cell); } } else if (cell->type == ID($fsm)) { @@ -107,7 +107,7 @@ struct CleanZeroWidthPass : public Pass { } else if (cell->type == ID($lut)) { // Zero-width LUT is just a const driver. if (cell->getParam(ID::WIDTH).as_int() == 0) { - module->connect(cell->getPort(ID::Y), cell->getParam(ID::LUT)[0]); + module->connect(cell->getPort(TW::Y), cell->getParam(ID::LUT)[0]); module->remove(cell); } } else if (cell->type == ID($sop)) { @@ -115,7 +115,7 @@ struct CleanZeroWidthPass : public Pass { if (cell->getParam(ID::WIDTH).as_int() == 0) { // The value is 1 iff DEPTH is non-0. bool val = cell->getParam(ID::DEPTH).as_int() != 0; - module->connect(cell->getPort(ID::Y), val); + module->connect(cell->getPort(TW::Y), val); module->remove(cell); } } else if (cell->hasParam(ID::WIDTH)) { @@ -132,11 +132,11 @@ struct CleanZeroWidthPass : public Pass { // TODO: fixing zero-width A and B not supported. } else { if (cell->getParam(ID::A_WIDTH).as_int() == 0) { - cell->setPort(ID::A, State::S0); + cell->setPort(TW::A, State::S0); cell->setParam(ID::A_WIDTH, 1); } if (cell->hasParam(ID::B_WIDTH) && cell->getParam(ID::B_WIDTH).as_int() == 0) { - cell->setPort(ID::B, State::S0); + cell->setPort(TW::B, State::S0); cell->setParam(ID::B_WIDTH, 1); } } diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index 2f5ec9ed5..e2d4044e0 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -30,7 +30,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap & { CellTypes ct(design); - RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size()); + RTLIL::Wire *dummy_wire = module->addWire(NEW_TWINE, sig.size()); // (void)module->connections(); // trigger signorm flush diff --git a/passes/cmds/dft_tag.cc b/passes/cmds/dft_tag.cc index 216f66b2c..3e8bd77ab 100644 --- a/passes/cmds/dft_tag.cc +++ b/passes/cmds/dft_tag.cc @@ -98,10 +98,10 @@ struct DftTagWorker { } for (auto cell : overwrite_cells) { - log_debug("Applying $overwrite_tag %s for signal %s\n", cell->name.unescape(), log_signal(cell->getPort(ID::A))); - SigSpec orig_signal = cell->getPort(ID::A); + log_debug("Applying $overwrite_tag %s for signal %s\n", cell->name.unescape(), log_signal(cell->getPort(TW::A))); + SigSpec orig_signal = cell->getPort(TW::A); SigSpec interposed_signal = divert_users(orig_signal); - auto *set_tag_cell = module->addSetTag(NEW_ID, cell->getParam(ID::TAG).decode_string(), orig_signal, cell->getPort(ID::SET), cell->getPort(ID::CLR), interposed_signal); + auto *set_tag_cell = module->addSetTag(NEW_ID, cell->getParam(ID::TAG).decode_string(), orig_signal, cell->getPort(TW::SET), cell->getPort(TW::CLR), interposed_signal); modwalker.add_cell(set_tag_cell); // Make sure the next $overwrite_tag sees the new connections design_changed = true; } @@ -123,7 +123,7 @@ struct DftTagWorker { signal_mapped.sort_and_unify(); if (GetSize(signal_mapped) < GetSize(signal)) log_warning("Detected $overwrite_tag on signal %s which contains repeated bits, this can result in unexpected behavior.\n", log_signal(signal)); - SigSpec new_wire = module->addWire(NEW_ID, GetSize(signal)); + SigSpec new_wire = module->addWire(NEW_TWINE, GetSize(signal)); for (int i = 0; i < GetSize(new_wire); ++i) divert_users(signal[i], new_wire[i]); return new_wire; @@ -359,7 +359,7 @@ struct DftTagWorker { // when the outer call for this tag/cell returns for (auto &conn : cell->connections()) if (cell->output(conn.first)) - emit_tag_signal(tag, conn.second, module->addWire(NEW_ID, GetSize(conn.second))); + emit_tag_signal(tag, conn.second, module->addWire(NEW_TWINE, GetSize(conn.second))); return; } @@ -380,8 +380,8 @@ struct DftTagWorker { group_of_tag[tag] = tag_group; } - auto &sig_y = cell->getPort(ID::Y); - auto &sig_a = cell->getPort(ID::A); + auto &sig_y = cell->getPort(TW::Y); + auto &sig_a = cell->getPort(TW::A); // TODO handle constant set/clr masks add_tags(sig_y, singleton(tag)); forward_tags(sig_y, sig_a); @@ -393,8 +393,8 @@ struct DftTagWorker { } if (cell->type.in(ID($not), ID($pos))) { - auto &sig_y = cell->getPort(ID::Y); - auto sig_a = cell->getPort(ID::A); + auto &sig_y = cell->getPort(TW::Y); + auto sig_a = cell->getPort(TW::A); if (cell->type.in(ID($not), ID($or))) { sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool()); } @@ -403,9 +403,9 @@ struct DftTagWorker { } if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($bweqx))) { - auto &sig_y = cell->getPort(ID::Y); - auto sig_a = cell->getPort(ID::A); - auto sig_b = cell->getPort(ID::B); + auto &sig_y = cell->getPort(TW::Y); + auto sig_a = cell->getPort(TW::A); + auto sig_b = cell->getPort(TW::B); if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) { sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool()); sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool()); @@ -416,10 +416,10 @@ struct DftTagWorker { } if (cell->type.in(ID($mux), ID($bwmux))) { - auto &sig_y = cell->getPort(ID::Y); - auto &sig_a = cell->getPort(ID::A); - auto &sig_b = cell->getPort(ID::B); - auto sig_s = cell->getPort(ID::S); + auto &sig_y = cell->getPort(TW::Y); + auto &sig_a = cell->getPort(TW::A); + auto &sig_b = cell->getPort(TW::B); + auto sig_s = cell->getPort(TW::S); if (cell->type == ID($mux)) sig_s = SigSpec(sig_s[0], GetSize(sig_y)); @@ -445,7 +445,7 @@ struct DftTagWorker { ID($reduce_bool), ID($logic_not), ID($logic_or), ID($logic_and), ID($eq), ID($ne) )) { - auto &sig_y = cell->getPort(ID::Y); + auto &sig_y = cell->getPort(TW::Y); add_tags(sig_y[0], tags(cell)); return; @@ -480,12 +480,12 @@ struct DftTagWorker { if (cell->type == ID($set_tag)) { IdString cell_tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string()); - auto tag_sig_a = tag_signal(tag, cell->getPort(ID::A)); - auto &sig_y = cell->getPort(ID::Y); + auto tag_sig_a = tag_signal(tag, cell->getPort(TW::A)); + auto &sig_y = cell->getPort(TW::Y); if (cell_tag == tag) { - auto &sig_set = cell->getPort(ID::SET); - auto &sig_clr = cell->getPort(ID::CLR); + auto &sig_set = cell->getPort(TW::SET); + auto &sig_clr = cell->getPort(TW::CLR); tag_sig_a = autoAnd(NEW_ID, tag_sig_a, autoNot(NEW_ID, sig_clr)); tag_sig_a = autoOr(NEW_ID, tag_sig_a, sig_set); } @@ -499,8 +499,8 @@ struct DftTagWorker { } if (cell->type.in(ID($not), ID($pos), ID($_NOT_), ID($_BUF_))) { - auto &sig_y = cell->getPort(ID::Y); - auto sig_a = cell->getPort(ID::A); + auto &sig_y = cell->getPort(TW::Y); + auto sig_a = cell->getPort(TW::A); if (cell->type.in(ID($not), ID($or))) { sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool()); } @@ -512,9 +512,9 @@ struct DftTagWorker { ID($and), ID($or), ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_) )) { - auto &sig_y = cell->getPort(ID::Y); - auto sig_a = cell->getPort(ID::A); - auto sig_b = cell->getPort(ID::B); + auto &sig_y = cell->getPort(TW::Y); + auto sig_a = cell->getPort(TW::A); + auto sig_b = cell->getPort(TW::B); if (cell->type.in(ID($and), ID($or))) { sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool()); sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool()); @@ -555,9 +555,9 @@ struct DftTagWorker { } if (cell->type.in(ID($xor), ID($xnor), ID($bweqx), ID($_XOR_), ID($_XNOR_))) { - auto &sig_y = cell->getPort(ID::Y); - auto sig_a = cell->getPort(ID::A); - auto sig_b = cell->getPort(ID::B); + auto &sig_y = cell->getPort(TW::Y); + auto sig_a = cell->getPort(TW::A); + auto sig_b = cell->getPort(TW::B); if (cell->type.in(ID($xor), ID($xnor))) { sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool()); sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool()); @@ -573,10 +573,10 @@ struct DftTagWorker { if (cell->type.in(ID($_MUX_), ID($mux), ID($bwmux))) { - auto &sig_y = cell->getPort(ID::Y); - auto &sig_a = cell->getPort(ID::A); - auto &sig_b = cell->getPort(ID::B); - auto sig_s = cell->getPort(ID::S); + auto &sig_y = cell->getPort(TW::Y); + auto &sig_a = cell->getPort(TW::A); + auto &sig_b = cell->getPort(TW::B); + auto sig_s = cell->getPort(TW::S); if (cell->type == ID($mux)) sig_s = SigSpec(sig_s[0], GetSize(sig_y)); @@ -607,9 +607,9 @@ struct DftTagWorker { } if (cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex))) { - auto &sig_y = cell->getPort(ID::Y); - auto sig_a = cell->getPort(ID::A); - auto sig_b = cell->getPort(ID::B); + auto &sig_y = cell->getPort(TW::Y); + auto sig_a = cell->getPort(TW::A); + auto sig_b = cell->getPort(TW::B); int width = std::max(GetSize(sig_a), GetSize(sig_b)); sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool()); sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool()); @@ -636,9 +636,9 @@ struct DftTagWorker { if (cell->type.in(ID($lt), ID($gt), ID($le), ID($ge))) { - auto &sig_y = cell->getPort(ID::Y); - auto sig_a = cell->getPort(ID::A); - auto sig_b = cell->getPort(ID::B); + auto &sig_y = cell->getPort(TW::Y); + auto sig_a = cell->getPort(TW::A); + auto sig_b = cell->getPort(TW::B); int width = std::max(GetSize(sig_a), GetSize(sig_b)); sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool()); sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool()); @@ -667,8 +667,8 @@ struct DftTagWorker { } if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($logic_not))) { - auto &sig_y = cell->getPort(ID::Y); - auto sig_a = cell->getPort(ID::A); + auto &sig_y = cell->getPort(TW::Y); + auto sig_a = cell->getPort(TW::A); auto group_sig_a = tag_group_signal(tag, sig_a); auto tag_sig_a = tag_signal(tag, sig_a); @@ -701,7 +701,7 @@ struct DftTagWorker { ff.name = NEW_ID; ff.cell = nullptr; ff.sig_d = tag_signal(tag, ff.sig_d); - ff.sig_q = module->addWire(NEW_ID, width); + ff.sig_q = module->addWire(NEW_TWINE, width); ff.is_anyinit = false; ff.val_init = Const(0, width); ff.emit(); @@ -751,7 +751,7 @@ struct DftTagWorker { get_tag_cells.push_back(cell); for (auto cell : get_tag_cells) { - auto &sig_a = cell->getPort(ID::A); + auto &sig_a = cell->getPort(TW::A); IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string()); tag_signal(tag, sig_a); @@ -808,15 +808,15 @@ struct DftTagWorker { } for (auto cell : set_tag_cells) { - auto &sig_a = cell->getPort(ID::A); - auto &sig_y = cell->getPort(ID::Y); + auto &sig_a = cell->getPort(TW::A); + auto &sig_y = cell->getPort(TW::Y); module->connect(sig_y, sig_a); module->remove(cell); } for (auto cell : get_tag_cells) { - auto &sig_a = cell->getPort(ID::A); - auto &sig_y = cell->getPort(ID::Y); + auto &sig_a = cell->getPort(TW::A); + auto &sig_y = cell->getPort(TW::Y); IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string()); auto tag_sig = tag_signal(tag, sig_a); diff --git a/passes/cmds/future.cc b/passes/cmds/future.cc index 15f4b8bd1..cecc6d2e3 100644 --- a/passes/cmds/future.cc +++ b/passes/cmds/future.cc @@ -53,7 +53,7 @@ struct FutureWorker { if (cell->type != ID($future_ff)) continue; - module->connect(cell->getPort(ID::Y), future_ff(cell->getPort(ID::A))); + module->connect(cell->getPort(TW::Y), future_ff(cell->getPort(TW::A))); replaced_cells.push_back(cell); } diff --git a/passes/cmds/glift.cc b/passes/cmds/glift.cc index ebdaa6fc3..f922a1b76 100644 --- a/passes/cmds/glift.cc +++ b/passes/cmds/glift.cc @@ -189,7 +189,7 @@ private: if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_))) { const unsigned int A = 0, B = 1, Y = 2; const unsigned int NUM_PORTS = 3; - RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(ID::A), cell->getPort(ID::B), cell->getPort(ID::Y)}; + RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::B), cell->getPort(TW::Y)}; RTLIL::SigSpec port_taints[NUM_PORTS]; if (ports[A].size() != 1 || ports[B].size() != 1 || ports[Y].size() != 1) @@ -254,7 +254,7 @@ private: else if (cell->type.in(ID($_XOR_), ID($_XNOR_))) { const unsigned int A = 0, B = 1, Y = 2; const unsigned int NUM_PORTS = 3; - RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(ID::A), cell->getPort(ID::B), cell->getPort(ID::Y)}; + RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::B), cell->getPort(TW::Y)}; RTLIL::SigSpec port_taints[NUM_PORTS]; if (ports[A].size() != 1 || ports[B].size() != 1 || ports[Y].size() != 1) @@ -310,7 +310,7 @@ private: else if (cell->type.in(ID($_MUX_), ID($_NMUX_))) { const unsigned int A = 0, B = 1, S = 2, Y = 3; const unsigned int NUM_PORTS = 4; - RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(ID::A), cell->getPort(ID::B), cell->getPort(ID::S), cell->getPort(ID::Y)}; + RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::B), cell->getPort(TW::S), cell->getPort(TW::Y)}; RTLIL::SigSpec port_taints[NUM_PORTS]; if (ports[A].size() != 1 || ports[B].size() != 1 || ports[S].size() != 1 || ports[Y].size() != 1) @@ -323,7 +323,7 @@ private: else if (cell->type.in(ID($_NOT_))) { const unsigned int A = 0, Y = 1; const unsigned int NUM_PORTS = 2; - RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(ID::A), cell->getPort(ID::Y)}; + RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::Y)}; RTLIL::SigSpec port_taints[NUM_PORTS]; if (ports[A].size() != 1 || ports[Y].size() != 1) diff --git a/passes/cmds/portarcs.cc b/passes/cmds/portarcs.cc index 0644719d7..ebb3055b2 100644 --- a/passes/cmds/portarcs.cc +++ b/passes/cmds/portarcs.cc @@ -32,7 +32,7 @@ static RTLIL::SigBit canonical_bit(RTLIL::SigBit bit) RTLIL::Wire *w; while ((w = bit.wire) != NULL && !w->port_input && w->driverCell()->type.in(ID($buf), ID($_BUF_))) { - bit = w->driverCell()->getPort(ID::A)[bit.offset]; + bit = w->driverCell()->getPort(TW::A)[bit.offset]; } return bit; } @@ -292,7 +292,7 @@ struct PortarcsPass : Pass { int *p = annotations.at(canonical_bit(bit)); for (auto i = 0; i < inputs.size(); i++) { if (p[i] >= 0) { - Cell *spec = m->addCell(NEW_ID, ID($specify2)); + Cell *spec = m->addCell(NEW_TWINE, ID($specify2)); spec->setParam(ID::SRC_WIDTH, 1); spec->setParam(ID::DST_WIDTH, 1); spec->setParam(ID::T_FALL_MAX, p[i]); @@ -304,9 +304,9 @@ struct PortarcsPass : Pass { spec->setParam(ID::SRC_DST_POL, false); spec->setParam(ID::SRC_DST_PEN, false); spec->setParam(ID::FULL, false); - spec->setPort(ID::EN, Const(1, 1)); - spec->setPort(ID::SRC, inputs[i]); - spec->setPort(ID::DST, bit); + spec->setPort(TW::EN, Const(1, 1)); + spec->setPort(TW::SRC, inputs[i]); + spec->setPort(TW::DST, bit); } } } diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc index 017600a46..3657eb3a4 100644 --- a/passes/cmds/scatter.cc +++ b/passes/cmds/scatter.cc @@ -51,7 +51,7 @@ struct ScatterPass : public Pass { for (auto cell : module->cells()) { dict new_connections; for (auto conn : cell->connections()) - new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEW_ID, GetSize(conn.second)))); + new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEW_TWINE, GetSize(conn.second)))); for (auto &it : new_connections) { if (ct.cell_output(cell->type, it.first)) module->connect(RTLIL::SigSig(it.second.first, it.second.second)); diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index 198b73224..2abcc857a 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -152,14 +152,14 @@ struct SccWorker if (subcell->type != ID($specify2)) continue; - for (auto bit : subcell->getPort(ID::SRC)) + for (auto bit : subcell->getPort(TW::SRC)) { if (!bit.wire || !cell->hasPort(bit.wire->name)) continue; inputSignals.append(sigmap(cell->getPort(bit.wire->name))); } - for (auto bit : subcell->getPort(ID::DST)) + for (auto bit : subcell->getPort(TW::DST)) { if (!bit.wire || !cell->hasPort(bit.wire->name)) continue; diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 99a223bdc..5fc72a1ae 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -371,13 +371,13 @@ struct SetundefPass : public Pass { bool cell_selected = design->selected(module, cell); bool wire_selected = false; - for (auto bit : sigmap(cell->getPort(ID::Q))) + for (auto bit : sigmap(cell->getPort(TW::Q))) if (bit.wire && design->selected(module, bit.wire)) wire_selected = true; if (!cell_selected && !wire_selected) continue; - for (auto bit : sigmap(cell->getPort(ID::Q))) + for (auto bit : sigmap(cell->getPort(TW::Q))) ffbits.insert(bit); } diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 9439a3a2e..3e57a91ae 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -75,13 +75,13 @@ struct SpliceWorker RTLIL::SigSpec new_sig = sig; if (sig_a.size() != sig.size()) { - RTLIL::Cell *cell = module->addCell(NEW_ID, ID($slice)); + RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($slice)); cell->parameters[ID::OFFSET] = offset; cell->parameters[ID::A_WIDTH] = sig_a.size(); cell->parameters[ID::Y_WIDTH] = sig.size(); - cell->setPort(ID::A, sig_a); - cell->setPort(ID::Y, module->addWire(NEW_ID, sig.size())); - new_sig = cell->getPort(ID::Y); + cell->setPort(TW::A, sig_a); + cell->setPort(TW::Y, module->addWire(NEW_TWINE, sig.size())); + new_sig = cell->getPort(TW::Y); } sliced_signals_cache[sig] = new_sig; @@ -132,13 +132,13 @@ struct SpliceWorker RTLIL::SigSpec new_sig = get_sliced_signal(chunks.front()); for (size_t i = 1; i < chunks.size(); i++) { RTLIL::SigSpec sig2 = get_sliced_signal(chunks[i]); - RTLIL::Cell *cell = module->addCell(NEW_ID, ID($concat)); + RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($concat)); cell->parameters[ID::A_WIDTH] = new_sig.size(); cell->parameters[ID::B_WIDTH] = sig2.size(); - cell->setPort(ID::A, new_sig); - cell->setPort(ID::B, sig2); - cell->setPort(ID::Y, module->addWire(NEW_ID, new_sig.size() + sig2.size())); - new_sig = cell->getPort(ID::Y); + cell->setPort(TW::A, new_sig); + cell->setPort(TW::B, sig2); + cell->setPort(TW::Y, module->addWire(NEW_TWINE, new_sig.size() + sig2.size())); + new_sig = cell->getPort(TW::Y); } spliced_signals_cache[sig] = new_sig; diff --git a/passes/cmds/splitcells.cc b/passes/cmds/splitcells.cc index a99e4d268..c7515725b 100644 --- a/passes/cmds/splitcells.cc +++ b/passes/cmds/splitcells.cc @@ -70,16 +70,16 @@ struct SplitcellsWorker { if (cell->type.in("$and", "$mux", "$not", "$or", "$pmux", "$xnor", "$xor")) { - SigSpec outsig = sigmap(cell->getPort(ID::Y)); + SigSpec outsig = sigmap(cell->getPort(TW::Y)); if (GetSize(outsig) <= 1) return 0; std::vector slices; slices.push_back(0); int width = GetSize(outsig); - width = std::min(width, GetSize(cell->getPort(ID::A))); + width = std::min(width, GetSize(cell->getPort(TW::A))); if (cell->hasPort(ID::B)) - width = std::min(width, GetSize(cell->getPort(ID::B))); + width = std::min(width, GetSize(cell->getPort(TW::B))); for (int i = 1; i < width; i++) { auto &last_users = bit_users_db[outsig[slices.back()]]; @@ -110,23 +110,23 @@ struct SplitcellsWorker return new_sig; }; - slice->setPort(ID::A, slice_signal(slice->getPort(ID::A))); + slice->setPort(TW::A, slice_signal(slice->getPort(TW::A))); if (slice->hasParam(ID::A_WIDTH)) - slice->setParam(ID::A_WIDTH, GetSize(slice->getPort(ID::A))); + slice->setParam(ID::A_WIDTH, GetSize(slice->getPort(TW::A))); if (slice->hasPort(ID::B)) { - slice->setPort(ID::B, slice_signal(slice->getPort(ID::B))); + slice->setPort(TW::B, slice_signal(slice->getPort(TW::B))); if (slice->hasParam(ID::B_WIDTH)) - slice->setParam(ID::B_WIDTH, GetSize(slice->getPort(ID::B))); + slice->setParam(ID::B_WIDTH, GetSize(slice->getPort(TW::B))); } - slice->setPort(ID::Y, slice_signal(slice->getPort(ID::Y))); + slice->setPort(TW::Y, slice_signal(slice->getPort(TW::Y))); if (slice->hasParam(ID::Y_WIDTH)) - slice->setParam(ID::Y_WIDTH, GetSize(slice->getPort(ID::Y))); + slice->setParam(ID::Y_WIDTH, GetSize(slice->getPort(TW::Y))); if (slice->hasParam(ID::WIDTH)) - slice->setParam(ID::WIDTH, GetSize(slice->getPort(ID::Y))); + slice->setParam(ID::WIDTH, GetSize(slice->getPort(TW::Y))); - log(" slice %d: %s => %s\n", i, slice_name, log_signal(slice->getPort(ID::Y))); + log(" slice %d: %s => %s\n", i, slice_name, log_signal(slice->getPort(TW::Y))); } module->remove(cell); @@ -139,7 +139,7 @@ struct SplitcellsWorker auto splitports = {ID::D, ID::Q, ID::AD, ID::SET, ID::CLR}; auto splitparams = {ID::ARST_VALUE, ID::SRST_VALUE}; - SigSpec outsig = sigmap(cell->getPort(ID::Q)); + SigSpec outsig = sigmap(cell->getPort(TW::Q)); if (GetSize(outsig) <= 1) return 0; int width = GetSize(outsig); @@ -167,7 +167,7 @@ struct SplitcellsWorker Cell *slice = module->addCell(slice_name, cell); - for (IdString portname : splitports) { + for (TwineRef portname : splitports) { if (slice->hasPort(portname)) { SigSpec sig = slice->getPort(portname); sig = sig.extract(slice_lsb, slice_msb-slice_lsb+1); @@ -183,9 +183,9 @@ struct SplitcellsWorker } } - slice->setParam(ID::WIDTH, GetSize(slice->getPort(ID::Q))); + slice->setParam(ID::WIDTH, GetSize(slice->getPort(TW::Q))); - log(" slice %d: %s => %s\n", i, slice_name.unescape(), log_signal(slice->getPort(ID::Q))); + log(" slice %d: %s => %s\n", i, slice_name.unescape(), log_signal(slice->getPort(TW::Q))); } module->remove(cell); diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index de767b96a..020b5ffbb 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -190,22 +190,22 @@ struct statdata_t { ID($xor), ID($xnor), ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx), ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt), ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow), ID($alu))) { - int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(ID::A)) : 0; - int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(ID::B)) : 0; - int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(ID::Y)) : 0; + int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(TW::A)) : 0; + int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(TW::B)) : 0; + int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(TW::Y)) : 0; cell_type = stringf("%s_%d", cell_type, max({width_a, width_b, width_y})); } else if (cell_type.in(ID($mux))) - cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(ID::Y))); + cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Y))); else if (cell_type.in(ID($bmux), ID($pmux))) cell_type = - stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(ID::Y)), GetSize(cell->getPort(ID::S))); + stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(TW::Y)), GetSize(cell->getPort(TW::S))); else if (cell_type == ID($demux)) cell_type = - stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::S))); + stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::S))); else if (cell_type.in(ID($sr), ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($aldff), ID($aldffe), ID($dlatch), ID($adlatch), ID($dlatchsr))) - cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(ID::Q))); + cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Q))); } if (!cell_area.empty()) { @@ -215,10 +215,10 @@ struct statdata_t { if (cell_data.single_parameter_area.size() > 0) { // assume that we just take the max of the A,B,Y ports - int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(ID::A)) : 0; - int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(ID::B)) : 0; - int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(ID::Y)) : 0; - int width_q = cell->hasPort(ID::Q) ? GetSize(cell->getPort(ID::Q)) : 0; + int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(TW::A)) : 0; + int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(TW::B)) : 0; + int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(TW::Y)) : 0; + int width_q = cell->hasPort(ID::Q) ? GetSize(cell->getPort(TW::Q)) : 0; int max_width = max({width_a, width_b, width_y, width_q}); if (!cell_area.count(cell_type)) { cell_area[cell_type] = cell_data; @@ -237,7 +237,7 @@ struct statdata_t { vector widths; if (cell_data.parameter_names.size() > 0) { for (auto &it : cell_data.parameter_names) { - RTLIL::IdString port_name; + TwineRef port_name; if (it == "A") { port_name = ID::A; } else if (it == "B") { diff --git a/passes/cmds/test_patch.cc b/passes/cmds/test_patch.cc index 6d2dee5fe..d7fae5d03 100644 --- a/passes/cmds/test_patch.cc +++ b/passes/cmds/test_patch.cc @@ -19,18 +19,18 @@ struct TestPatchPass : public Pass { for (auto cell : module->selected_cells()) { if (cell->type == ID($add)) { Cell* add = cell; - log_assert(add->getPort(ID::B).is_wire()); - log_assert(add->getPort(ID::B).known_driver()); - auto neg = add->getPort(ID::B)[0].wire->driverCell(); + log_assert(add->getPort(TW::B).is_wire()); + log_assert(add->getPort(TW::B).known_driver()); + auto neg = add->getPort(TW::B)[0].wire->driverCell(); log_assert(neg->type == ID($not)); RTLIL::Patch patcher(module, nullptr); - int width = cell->getPort(ID::A).size(); + int width = cell->getPort(TW::A).size(); auto sub = patcher.addSub(NEW_ID, - neg->getPort(ID::A), - add->getPort(ID::A), - patcher.addWire(NEW_ID, width)); - auto new_out_wire = patcher.addWire(NEW_ID, width); - auto new_cell = patcher.addNeg(NEW_ID, sub->getPort(ID::Y), new_out_wire); + neg->getPort(TW::A), + add->getPort(TW::A), + patcher.addWire(NEW_TWINE, width)); + auto new_out_wire = patcher.addWire(NEW_TWINE, width); + auto new_cell = patcher.addNeg(NEW_ID, sub->getPort(TW::Y), new_out_wire); log_cell(new_cell); patcher.patch(add, ID::Y, new_out_wire); } diff --git a/passes/cmds/trace.cc b/passes/cmds/trace.cc index 37f7da89b..e64459cba 100644 --- a/passes/cmds/trace.cc +++ b/passes/cmds/trace.cc @@ -36,7 +36,7 @@ struct TraceMonitor : public RTLIL::Monitor log("#TRACE# Module delete: %s\n", module); } - void notify_connect(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override + void notify_connect(RTLIL::Cell *cell, TwineRef port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override { log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", cell->module, cell, port.unescape(), log_signal(sig), log_signal(old_sig)); } diff --git a/passes/cmds/xprop.cc b/passes/cmds/xprop.cc index cc11040c2..330046cf0 100644 --- a/passes/cmds/xprop.cc +++ b/passes/cmds/xprop.cc @@ -202,9 +202,9 @@ struct XpropWorker EncodedSig new_sigs; if (new_bits > 0) { - new_sigs.is_0 = module->addWire(NEW_ID, new_bits); - new_sigs.is_1 = module->addWire(NEW_ID, new_bits); - new_sigs.is_x = module->addWire(NEW_ID, new_bits); + new_sigs.is_0 = module->addWire(NEW_TWINE, new_bits); + new_sigs.is_1 = module->addWire(NEW_TWINE, new_bits); + new_sigs.is_x = module->addWire(NEW_TWINE, new_bits); } int invert_pos = 0; @@ -319,8 +319,8 @@ struct XpropWorker } if (cell->type == ID($not)) { - auto &sig_y = cell->getPort(ID::Y); - auto sig_a = cell->getPort(ID::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool()); + auto &sig_y = cell->getPort(TW::Y); + auto sig_a = cell->getPort(TW::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool()); for (int i = 0; i < GetSize(sig_y); i++) if (maybe_x(sig_a[i])) mark_maybe_x(sig_y[i]); @@ -328,9 +328,9 @@ struct XpropWorker } if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) { - auto &sig_y = cell->getPort(ID::Y); - auto sig_a = cell->getPort(ID::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool()); - auto sig_b = cell->getPort(ID::B); sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool()); + auto &sig_y = cell->getPort(TW::Y); + auto sig_a = cell->getPort(TW::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool()); + auto sig_b = cell->getPort(TW::B); sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool()); for (int i = 0; i < GetSize(sig_y); i++) if (maybe_x(sig_a[i]) || maybe_x(sig_b[i])) mark_maybe_x(sig_y[i]); @@ -338,10 +338,10 @@ struct XpropWorker } if (cell->type.in(ID($bwmux))) { - auto &sig_y = cell->getPort(ID::Y); - auto &sig_a = cell->getPort(ID::A); - auto &sig_b = cell->getPort(ID::B); - auto &sig_s = cell->getPort(ID::S); + auto &sig_y = cell->getPort(TW::Y); + auto &sig_a = cell->getPort(TW::A); + auto &sig_b = cell->getPort(TW::B); + auto &sig_s = cell->getPort(TW::S); for (int i = 0; i < GetSize(sig_y); i++) if (maybe_x(sig_a[i]) || maybe_x(sig_b[i]) || maybe_x(sig_s[i])) mark_maybe_x(sig_y[i]); @@ -349,10 +349,10 @@ struct XpropWorker } if (cell->type.in(ID($_MUX_), ID($mux), ID($bmux))) { - auto &sig_y = cell->getPort(ID::Y); - auto &sig_a = cell->getPort(ID::A); - auto &sig_b = cell->getPort(ID::B); - auto &sig_s = cell->getPort(ID::S); + auto &sig_y = cell->getPort(TW::Y); + auto &sig_a = cell->getPort(TW::A); + auto &sig_b = cell->getPort(TW::B); + auto &sig_s = cell->getPort(TW::S); if (maybe_x(sig_s)) { mark_maybe_x(sig_y); return; @@ -373,9 +373,9 @@ struct XpropWorker } if (cell->type.in(ID($demux))) { - auto &sig_y = cell->getPort(ID::Y); - auto &sig_a = cell->getPort(ID::A); - auto &sig_s = cell->getPort(ID::S); + auto &sig_y = cell->getPort(TW::Y); + auto &sig_a = cell->getPort(TW::A); + auto &sig_s = cell->getPort(TW::S); if (maybe_x(sig_s)) { mark_maybe_x(sig_y); return; @@ -388,15 +388,15 @@ struct XpropWorker } if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift))) { - auto &sig_b = cell->getPort(ID::B); - auto &sig_y = cell->getPort(ID::Y); + auto &sig_b = cell->getPort(TW::B); + auto &sig_y = cell->getPort(TW::Y); if (maybe_x(sig_b)) { mark_maybe_x(sig_y); return; } - auto &sig_a = cell->getPort(ID::A); + auto &sig_a = cell->getPort(TW::A); if (maybe_x(sig_a)) { // We could be more precise for shifts, but that's not required @@ -408,15 +408,15 @@ struct XpropWorker } if (cell->type.in(ID($shiftx))) { - auto &sig_b = cell->getPort(ID::B); - auto &sig_y = cell->getPort(ID::Y); + auto &sig_b = cell->getPort(TW::B); + auto &sig_y = cell->getPort(TW::Y); if (cell->getParam(ID::B_SIGNED).as_bool() || GetSize(sig_b) >= 30) { mark_maybe_x(sig_y); } else { int max_shift = (1 << GetSize(sig_b)) - 1; - auto &sig_a = cell->getPort(ID::A); + auto &sig_a = cell->getPort(TW::A); for (int i = 0; i < GetSize(sig_y); i++) if (i + max_shift >= GetSize(sig_a)) @@ -428,7 +428,7 @@ struct XpropWorker return; } - auto &sig_a = cell->getPort(ID::A); + auto &sig_a = cell->getPort(TW::A); if (maybe_x(sig_a)) { // We could be more precise for shifts, but that's not required // for correctness, so let's keep it simple @@ -457,7 +457,7 @@ struct XpropWorker ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_ANDNOT_), ID($_OR_), ID($_NOR_), ID($_ORNOT_), ID($_XOR_), ID($_XNOR_) )) { - auto &sig_y = cell->getPort(ID::Y); + auto &sig_y = cell->getPort(TW::Y); if (inputs_maybe_x(cell)) mark_maybe_x(sig_y[0]); return; @@ -482,9 +482,9 @@ struct XpropWorker if (!ports_maybe_x(cell)) { if (cell->type == ID($bweq)) { - auto sig_y = cell->getPort(ID::Y); - auto sig_a = cell->getPort(ID::A); - auto sig_b = cell->getPort(ID::B); + auto sig_y = cell->getPort(TW::Y); + auto sig_a = cell->getPort(TW::A); + auto sig_b = cell->getPort(TW::B); RTLIL::IdString name(cell->name); module->remove(cell); @@ -493,9 +493,9 @@ struct XpropWorker } if (cell->type.in(ID($nex), ID($eqx))) { - auto sig_y = cell->getPort(ID::Y); - auto sig_a = cell->getPort(ID::A); - auto sig_b = cell->getPort(ID::B); + auto sig_y = cell->getPort(TW::Y); + auto sig_a = cell->getPort(TW::A); + auto sig_b = cell->getPort(TW::B); RTLIL::IdString name(cell->name); auto type = cell->type; @@ -511,8 +511,8 @@ struct XpropWorker } if (cell->type.in(ID($not), ID($_NOT_))) { - auto &sig_y = cell->getPort(ID::Y); - auto sig_a = cell->getPort(ID::A); + auto &sig_y = cell->getPort(TW::Y); + auto sig_a = cell->getPort(TW::A); if (cell->type == ID($not)) sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool()); @@ -528,9 +528,9 @@ struct XpropWorker } if (cell->type.in(ID($and), ID($or), ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_))) { - auto &sig_y = cell->getPort(ID::Y); - auto sig_a = cell->getPort(ID::A); - auto sig_b = cell->getPort(ID::B); + auto &sig_y = cell->getPort(TW::Y); + auto sig_a = cell->getPort(TW::A); + auto sig_b = cell->getPort(TW::B); if (cell->type.in(ID($and), ID($or))) { sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool()); sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool()); @@ -555,8 +555,8 @@ struct XpropWorker } if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($logic_not))) { - auto &sig_y = cell->getPort(ID::Y); - auto &sig_a = cell->getPort(ID::A); + auto &sig_y = cell->getPort(TW::Y); + auto &sig_a = cell->getPort(TW::A); auto enc_a = encoded(sig_a); auto enc_y = encoded(sig_y, true); @@ -577,8 +577,8 @@ struct XpropWorker } if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) { - auto &sig_y = cell->getPort(ID::Y); - auto &sig_a = cell->getPort(ID::A); + auto &sig_y = cell->getPort(TW::Y); + auto &sig_a = cell->getPort(TW::A); auto enc_a = encoded(sig_a); auto enc_y = encoded(sig_y, true); @@ -597,9 +597,9 @@ struct XpropWorker } if (cell->type.in(ID($logic_and), ID($logic_or))) { - auto &sig_y = cell->getPort(ID::Y); - auto &sig_a = cell->getPort(ID::A); - auto &sig_b = cell->getPort(ID::B); + auto &sig_y = cell->getPort(TW::Y); + auto &sig_a = cell->getPort(TW::A); + auto &sig_b = cell->getPort(TW::B); auto enc_a = encoded(sig_a); auto enc_b = encoded(sig_b); @@ -623,9 +623,9 @@ struct XpropWorker } if (cell->type.in(ID($xor), ID($xnor), ID($_XOR_), ID($_XNOR_))) { - auto &sig_y = cell->getPort(ID::Y); - auto sig_a = cell->getPort(ID::A); - auto sig_b = cell->getPort(ID::B); + auto &sig_y = cell->getPort(TW::Y); + auto sig_a = cell->getPort(TW::A); + auto sig_b = cell->getPort(TW::B); if (cell->type.in(ID($xor), ID($xnor))) { sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool()); sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool()); @@ -646,9 +646,9 @@ struct XpropWorker } if (cell->type.in(ID($eq), ID($ne))) { - auto &sig_y = cell->getPort(ID::Y); - auto sig_a = cell->getPort(ID::A); - auto sig_b = cell->getPort(ID::B); + auto &sig_y = cell->getPort(TW::Y); + auto sig_a = cell->getPort(TW::A); + auto sig_b = cell->getPort(TW::B); int width = std::max(GetSize(sig_a), GetSize(sig_b)); sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool()); sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool()); @@ -672,9 +672,9 @@ struct XpropWorker } if (cell->type.in(ID($eqx), ID($nex))) { - auto &sig_y = cell->getPort(ID::Y); - auto sig_a = cell->getPort(ID::A); - auto sig_b = cell->getPort(ID::B); + auto &sig_y = cell->getPort(TW::Y); + auto sig_a = cell->getPort(TW::A); + auto sig_b = cell->getPort(TW::B); int width = std::max(GetSize(sig_a), GetSize(sig_b)); sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool()); sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool()); @@ -697,9 +697,9 @@ struct XpropWorker } if (cell->type.in(ID($bweqx))) { - auto &sig_y = cell->getPort(ID::Y); - auto &sig_a = cell->getPort(ID::A); - auto &sig_b = cell->getPort(ID::B); + auto &sig_y = cell->getPort(TW::Y); + auto &sig_a = cell->getPort(TW::A); + auto &sig_b = cell->getPort(TW::B); auto enc_a = encoded(sig_a); auto enc_b = encoded(sig_b); @@ -712,10 +712,10 @@ struct XpropWorker } if (cell->type.in(ID($_MUX_), ID($mux), ID($bwmux))) { - auto &sig_y = cell->getPort(ID::Y); - auto &sig_a = cell->getPort(ID::A); - auto &sig_b = cell->getPort(ID::B); - auto sig_s = cell->getPort(ID::S); + auto &sig_y = cell->getPort(TW::Y); + auto &sig_a = cell->getPort(TW::A); + auto &sig_b = cell->getPort(TW::B); + auto sig_s = cell->getPort(TW::S); if (cell->type == ID($mux)) sig_s = SigSpec(sig_s[0], GetSize(sig_y)); @@ -737,10 +737,10 @@ struct XpropWorker } if (cell->type.in(ID($pmux))) { - auto &sig_y = cell->getPort(ID::Y); - auto &sig_a = cell->getPort(ID::A); - auto &sig_b = cell->getPort(ID::B); - auto &sig_s = cell->getPort(ID::S); + auto &sig_y = cell->getPort(TW::Y); + auto &sig_a = cell->getPort(TW::A); + auto &sig_b = cell->getPort(TW::B); + auto &sig_s = cell->getPort(TW::S); auto enc_a = encoded(sig_a); auto enc_b = encoded(sig_b); @@ -772,9 +772,9 @@ struct XpropWorker } if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) { - auto &sig_y = cell->getPort(ID::Y); - auto &sig_a = cell->getPort(ID::A); - auto &sig_b = cell->getPort(ID::B); + auto &sig_y = cell->getPort(TW::Y); + auto &sig_a = cell->getPort(TW::A); + auto &sig_b = cell->getPort(TW::B); auto enc_a = encoded(sig_a); auto enc_b = encoded(sig_b); @@ -783,9 +783,9 @@ struct XpropWorker auto all_x = module->ReduceOr(NEW_ID, enc_b.is_x)[0]; auto not_all_x = module->Not(NEW_ID, all_x)[0]; - SigSpec y_not_0 = module->addWire(NEW_ID, GetSize(sig_y)); - SigSpec y_1 = module->addWire(NEW_ID, GetSize(sig_y)); - SigSpec y_x = module->addWire(NEW_ID, GetSize(sig_y)); + SigSpec y_not_0 = module->addWire(NEW_TWINE, GetSize(sig_y)); + SigSpec y_1 = module->addWire(NEW_TWINE, GetSize(sig_y)); + SigSpec y_x = module->addWire(NEW_TWINE, GetSize(sig_y)); auto encoded_type = cell->type == ID($shiftx) ? ID($shift) : cell->type; @@ -793,23 +793,23 @@ struct XpropWorker std::swap(enc_a.is_0, enc_a.is_x); } - auto shift_0 = module->addCell(NEW_ID, encoded_type); + auto shift_0 = module->addCell(NEW_TWINE, encoded_type); shift_0->parameters = cell->parameters; - shift_0->setPort(ID::A, module->Not(NEW_ID, enc_a.is_0)); - shift_0->setPort(ID::B, enc_b.is_1); - shift_0->setPort(ID::Y, y_not_0); + shift_0->setPort(TW::A, module->Not(NEW_ID, enc_a.is_0)); + shift_0->setPort(TW::B, enc_b.is_1); + shift_0->setPort(TW::Y, y_not_0); - auto shift_1 = module->addCell(NEW_ID, encoded_type); + auto shift_1 = module->addCell(NEW_TWINE, encoded_type); shift_1->parameters = cell->parameters; - shift_1->setPort(ID::A, enc_a.is_1); - shift_1->setPort(ID::B, enc_b.is_1); - shift_1->setPort(ID::Y, y_1); + shift_1->setPort(TW::A, enc_a.is_1); + shift_1->setPort(TW::B, enc_b.is_1); + shift_1->setPort(TW::Y, y_1); - auto shift_x = module->addCell(NEW_ID, encoded_type); + auto shift_x = module->addCell(NEW_TWINE, encoded_type); shift_x->parameters = cell->parameters; - shift_x->setPort(ID::A, enc_a.is_x); - shift_x->setPort(ID::B, enc_b.is_1); - shift_x->setPort(ID::Y, y_x); + shift_x->setPort(TW::A, enc_a.is_x); + shift_x->setPort(TW::B, enc_b.is_1); + shift_x->setPort(TW::Y, y_x); SigSpec y_0 = module->Not(NEW_ID, y_not_0); @@ -825,8 +825,8 @@ struct XpropWorker } if (cell->type.in(ID($ff))) { - auto &sig_d = cell->getPort(ID::D); - auto &sig_q = cell->getPort(ID::Q); + auto &sig_d = cell->getPort(TW::D); + auto &sig_q = cell->getPort(TW::Q); auto init_q = initvals(sig_q); auto init_q_is_1 = init_q; @@ -842,7 +842,7 @@ struct XpropWorker auto enc_d = encoded(sig_d); auto enc_q = encoded(sig_q, true); - auto data_q = module->addWire(NEW_ID, GetSize(sig_q)); + auto data_q = module->addWire(NEW_TWINE, GetSize(sig_q)); module->addFf(NEW_ID, enc_d.is_1, data_q); module->addFf(NEW_ID, enc_d.is_x, enc_q.is_x); @@ -885,7 +885,7 @@ struct XpropWorker auto enc_d = encoded(ff.sig_d); auto enc_q = encoded(ff.sig_q, true); - auto data_q = module->addWire(NEW_ID, GetSize(ff.sig_q)); + auto data_q = module->addWire(NEW_TWINE, GetSize(ff.sig_q)); ff.sig_d = enc_d.is_1; ff.sig_q = data_q; @@ -928,11 +928,11 @@ struct XpropWorker } if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) { - auto sig_b = cell->getPort(ID::B); + auto sig_b = cell->getPort(TW::B); auto invalid = module->LogicNot(NEW_ID, sig_b); inbits_x.append(invalid); sig_b[0] = module->Or(NEW_ID, sig_b[0], invalid); - cell->setPort(ID::B, sig_b); + cell->setPort(TW::B, sig_b); } SigBit outbits_x = (GetSize(inbits_x) == 1 ? inbits_x : module->ReduceOr(NEW_ID, inbits_x)); @@ -945,7 +945,7 @@ struct XpropWorker if (bool_out) enc_port.connect_as_bool(); - SigSpec new_output = module->addWire(NEW_ID, GetSize(conn.second)); + SigSpec new_output = module->addWire(NEW_TWINE, GetSize(conn.second)); enc_port.connect_1_under_x(bool_out ? new_output.extract(0) : new_output); enc_port.connect_x(SigSpec(outbits_x, GetSize(enc_port))); diff --git a/passes/equiv/equiv_add.cc b/passes/equiv/equiv_add.cc index b3c97fa80..d15f6f21a 100644 --- a/passes/equiv/equiv_add.cc +++ b/passes/equiv/equiv_add.cc @@ -84,7 +84,7 @@ struct EquivAddPass : public Pass { if (gold_cell->input(port) && gate_cell->input(port)) { - SigSpec combined_sig = module->addWire(NEW_ID, width); + SigSpec combined_sig = module->addWire(NEW_TWINE, width); for (int i = 0; i < width; i++) { module->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], combined_sig[i]); @@ -98,8 +98,8 @@ struct EquivAddPass : public Pass { if (gold_cell->output(port) && gate_cell->output(port)) { - SigSpec new_gold_wire = module->addWire(NEW_ID, width); - SigSpec new_gate_wire = module->addWire(NEW_ID, width); + SigSpec new_gold_wire = module->addWire(NEW_TWINE, width); + SigSpec new_gate_wire = module->addWire(NEW_TWINE, width); SigSig gg_conn; for (int i = 0; i < width; i++) { @@ -141,7 +141,7 @@ struct EquivAddPass : public Pass { } log_assert(GetSize(gold_signal) == GetSize(gate_signal)); - SigSpec equiv_signal = module->addWire(NEW_ID, GetSize(gold_signal)); + SigSpec equiv_signal = module->addWire(NEW_TWINE, GetSize(gold_signal)); SigMap sigmap(module); sigmap.apply(gold_signal); diff --git a/passes/equiv/equiv_induct.cc b/passes/equiv/equiv_induct.cc index c2308462e..bd325e7ea 100644 --- a/passes/equiv/equiv_induct.cc +++ b/passes/equiv/equiv_induct.cc @@ -48,8 +48,8 @@ struct EquivInductWorker : public EquivWorker<> report_missing_model(cfg.ignore_unknown_cells, cell); } if (cell->type == ID($equiv)) { - SigBit bit_a = sigmap(cell->getPort(ID::A)).as_bit(); - SigBit bit_b = sigmap(cell->getPort(ID::B)).as_bit(); + SigBit bit_a = sigmap(cell->getPort(TW::A)).as_bit(); + SigBit bit_b = sigmap(cell->getPort(TW::B)).as_bit(); if (bit_a != bit_b) { int ez_a = satgen.importSigBit(bit_a, step); int ez_b = satgen.importSigBit(bit_b, step); @@ -126,7 +126,7 @@ struct EquivInductWorker : public EquivWorker<> if (!ez->solve(new_step_not_consistent)) { log(" Proof for induction step holds. Entire workset of %d cells proven!\n", GetSize(workset)); for (auto cell : workset) - cell->setPort(ID::B, cell->getPort(ID::A)); + cell->setPort(TW::B, cell->getPort(TW::A)); success_counter += GetSize(workset); return; } @@ -138,10 +138,10 @@ struct EquivInductWorker : public EquivWorker<> for (auto cell : workset) { - SigBit bit_a = sigmap(cell->getPort(ID::A)).as_bit(); - SigBit bit_b = sigmap(cell->getPort(ID::B)).as_bit(); + SigBit bit_a = sigmap(cell->getPort(TW::A)).as_bit(); + SigBit bit_b = sigmap(cell->getPort(TW::B)).as_bit(); - log(" Trying to prove $equiv for %s:", log_signal(sigmap(cell->getPort(ID::Y)))); + log(" Trying to prove $equiv for %s:", log_signal(sigmap(cell->getPort(TW::Y)))); int ez_a = satgen.importSigBit(bit_a, cfg.max_seq+1); int ez_b = satgen.importSigBit(bit_b, cfg.max_seq+1); @@ -152,7 +152,7 @@ struct EquivInductWorker : public EquivWorker<> if (!ez->solve(cond)) { log(" success!\n"); - cell->setPort(ID::B, cell->getPort(ID::A)); + cell->setPort(TW::B, cell->getPort(TW::A)); success_counter++; } else { log(" failed.\n"); @@ -212,7 +212,7 @@ struct EquivInductPass : public Pass { for (auto cell : module->selected_cells()) if (cell->type == ID($equiv)) { - if (cell->getPort(ID::A) != cell->getPort(ID::B)) + if (cell->getPort(TW::A) != cell->getPort(TW::B)) unproven_equiv_cells.insert(cell); } diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index 7d5ede9b6..ad911ad87 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -210,8 +210,8 @@ struct EquivMakeWorker for (auto &bit : enc_result) if (bit != State::S1) bit = State::S0; - SigSpec dec_eq = equiv_mod->addWire(NEW_ID); - SigSpec enc_eq = equiv_mod->addWire(NEW_ID); + SigSpec dec_eq = equiv_mod->addWire(NEW_TWINE); + SigSpec enc_eq = equiv_mod->addWire(NEW_TWINE); equiv_mod->addEq(NEW_ID, reduced_dec_sig, reduced_dec_pat, dec_eq); cells_list.push_back(equiv_mod->addEq(NEW_ID, reduced_enc_sig, reduced_enc_pat, enc_eq)); @@ -370,7 +370,7 @@ struct EquivMakeWorker { for (int i = 0; i < GetSize(gold_sig); i++) if (gold_sig[i] != gate_sig[i]) { - Wire *w = equiv_mod->addWire(NEW_ID); + Wire *w = equiv_mod->addWire(NEW_TWINE); equiv_mod->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], w); gold_sig[i] = w; } diff --git a/passes/equiv/equiv_mark.cc b/passes/equiv/equiv_mark.cc index 0f355af4e..8e67a36d6 100644 --- a/passes/equiv/equiv_mark.cc +++ b/passes/equiv/equiv_mark.cc @@ -122,8 +122,8 @@ struct EquivMarkWorker { auto cell = module->cell(cell_name); - SigSpec sig_a = sigmap(cell->getPort(ID::A)); - SigSpec sig_b = sigmap(cell->getPort(ID::B)); + SigSpec sig_a = sigmap(cell->getPort(TW::A)); + SigSpec sig_b = sigmap(cell->getPort(TW::B)); if (sig_a == sig_b) { for (auto bit : sig_a) @@ -142,8 +142,8 @@ struct EquivMarkWorker if (cell_regions.count(cell->name) || cell->type != ID($equiv)) continue; - SigSpec sig_a = sigmap(cell->getPort(ID::A)); - SigSpec sig_b = sigmap(cell->getPort(ID::B)); + SigSpec sig_a = sigmap(cell->getPort(TW::A)); + SigSpec sig_b = sigmap(cell->getPort(TW::B)); log_assert(sig_a != sig_b); diff --git a/passes/equiv/equiv_miter.cc b/passes/equiv/equiv_miter.cc index 95eaac33d..fc42e41c3 100644 --- a/passes/equiv/equiv_miter.cc +++ b/passes/equiv/equiv_miter.cc @@ -214,18 +214,18 @@ struct EquivMiterWorker vector equiv_cells; for (auto c : miter_module->cells()) - if (c->type == ID($equiv) && c->getPort(ID::A) != c->getPort(ID::B)) + if (c->type == ID($equiv) && c->getPort(TW::A) != c->getPort(TW::B)) equiv_cells.push_back(c); for (auto c : equiv_cells) { SigSpec cmp = mode_undef ? - miter_module->LogicOr(NEW_ID, miter_module->Eqx(NEW_ID, c->getPort(ID::A), State::Sx), - miter_module->Eqx(NEW_ID, c->getPort(ID::A), c->getPort(ID::B))) : - miter_module->Eq(NEW_ID, c->getPort(ID::A), c->getPort(ID::B)); + miter_module->LogicOr(NEW_ID, miter_module->Eqx(NEW_ID, c->getPort(TW::A), State::Sx), + miter_module->Eqx(NEW_ID, c->getPort(TW::A), c->getPort(TW::B))) : + miter_module->Eq(NEW_ID, c->getPort(TW::A), c->getPort(TW::B)); if (mode_cmp) { - string cmp_name = stringf("\\cmp%s", log_signal(c->getPort(ID::Y))); + string cmp_name = stringf("\\cmp%s", log_signal(c->getPort(TW::Y))); for (int i = 1; i < GetSize(cmp_name); i++) if (cmp_name[i] == '\\') cmp_name[i] = '_'; diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc index 4062161bb..8d0d1899e 100644 --- a/passes/equiv/equiv_purge.cc +++ b/passes/equiv/equiv_purge.cc @@ -67,7 +67,7 @@ struct EquivPurgeWorker log(" Module input: %s\n", log_signal(wire)); wire->port_input = true; } - return module->addWire(NEW_ID, GetSize(sig)); + return module->addWire(NEW_TWINE, GetSize(sig)); } } @@ -81,7 +81,7 @@ struct EquivPurgeWorker wire->port_input = true; module->connect(sig, wire); log(" Module input: %s (%s)\n", log_signal(wire), log_signal(sig)); - return module->addWire(NEW_ID, GetSize(sig)); + return module->addWire(NEW_TWINE, GetSize(sig)); } } @@ -114,9 +114,9 @@ struct EquivPurgeWorker continue; } - SigSpec sig_a = sigmap(cell->getPort(ID::A)); - SigSpec sig_b = sigmap(cell->getPort(ID::B)); - SigSpec sig_y = sigmap(cell->getPort(ID::Y)); + SigSpec sig_a = sigmap(cell->getPort(TW::A)); + SigSpec sig_b = sigmap(cell->getPort(TW::B)); + SigSpec sig_y = sigmap(cell->getPort(TW::Y)); if (sig_a == sig_b) continue; @@ -130,7 +130,7 @@ struct EquivPurgeWorker for (auto bit : sig_y) visited.insert(bit); - cell->setPort(ID::Y, make_output(sig_y, cell->name)); + cell->setPort(TW::Y, make_output(sig_y, cell->name)); } SigSpec srcsig; @@ -168,7 +168,7 @@ struct EquivPurgeWorker for (auto cell : module->cells()) if (cell->type == ID($equiv)) - cell->setPort(ID::Y, rewrite_sigmap(sigmap(cell->getPort(ID::Y)))); + cell->setPort(TW::Y, rewrite_sigmap(sigmap(cell->getPort(TW::Y)))); module->fixup_ports(); } diff --git a/passes/equiv/equiv_remove.cc b/passes/equiv/equiv_remove.cc index c871cd9ef..0926e2492 100644 --- a/passes/equiv/equiv_remove.cc +++ b/passes/equiv/equiv_remove.cc @@ -68,9 +68,9 @@ struct EquivRemovePass : public Pass { for (auto module : design->selected_modules()) { for (auto cell : module->selected_cells()) - if (cell->type == ID($equiv) && (mode_gold || mode_gate || cell->getPort(ID::A) == cell->getPort(ID::B))) { - log("Removing $equiv cell %s.%s (%s).\n", module, cell, log_signal(cell->getPort(ID::Y))); - module->connect(cell->getPort(ID::Y), mode_gate ? cell->getPort(ID::B) : cell->getPort(ID::A)); + if (cell->type == ID($equiv) && (mode_gold || mode_gate || cell->getPort(TW::A) == cell->getPort(TW::B))) { + log("Removing $equiv cell %s.%s (%s).\n", module, cell, log_signal(cell->getPort(TW::Y))); + module->connect(cell->getPort(TW::Y), mode_gate ? cell->getPort(TW::B) : cell->getPort(TW::A)); module->remove(cell); remove_count++; } diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc index 6f3c9dc71..4750e1301 100644 --- a/passes/equiv/equiv_simple.cc +++ b/passes/equiv/equiv_simple.cc @@ -230,8 +230,8 @@ struct EquivSimpleWorker : public EquivWorker pool extra_problem_cells; for (auto assume : assume_cells) { pool assume_seed, dummy_next_seed, overlap_bits; - assume_seed.insert(model.sigmap(assume->getPort(ID::A)).as_bit()); - assume_seed.insert(model.sigmap(assume->getPort(ID::EN)).as_bit()); + assume_seed.insert(model.sigmap(assume->getPort(TW::A)).as_bit()); + assume_seed.insert(model.sigmap(assume->getPort(TW::EN)).as_bit()); for (auto& cone : {cone_a, cone_b}) { Cone assume_cone; @@ -292,8 +292,8 @@ struct EquivSimpleWorker : public EquivWorker bool prove_equiv_cell(Cell* cell) { - SigBit bit_a = model.sigmap(cell->getPort(ID::A)).as_bit(); - SigBit bit_b = model.sigmap(cell->getPort(ID::B)).as_bit(); + SigBit bit_a = model.sigmap(cell->getPort(TW::A)).as_bit(); + SigBit bit_b = model.sigmap(cell->getPort(TW::B)).as_bit(); int ez_context = ez->frozen_literal(); prepare_ezsat(ez_context, bit_a, bit_b); @@ -306,9 +306,9 @@ struct EquivSimpleWorker : public EquivWorker if (cfg.verbose) { log(" Trying to prove $equiv cell %s:\n", cell); - log(" A = %s, B = %s, Y = %s\n", log_signal(bit_a), log_signal(bit_b), log_signal(cell->getPort(ID::Y))); + log(" A = %s, B = %s, Y = %s\n", log_signal(bit_a), log_signal(bit_b), log_signal(cell->getPort(TW::Y))); } else { - log(" Trying to prove $equiv for %s:", log_signal(cell->getPort(ID::Y))); + log(" Trying to prove $equiv for %s:", log_signal(cell->getPort(TW::Y))); } int step = cfg.max_seq; @@ -347,7 +347,7 @@ struct EquivSimpleWorker : public EquivWorker if (!ez->solve(ez_context)) { log("%s", cfg.verbose ? " Proved equivalence! Marking $equiv cell as proven.\n" : " success!\n"); // Replace $equiv cell with a short - cell->setPort(ID::B, cell->getPort(ID::A)); + cell->setPort(TW::B, cell->getPort(TW::A)); ez->assume(ez->NOT(ez_context)); return true; } @@ -404,7 +404,7 @@ struct EquivSimpleWorker : public EquivWorker if (GetSize(equiv_cells) > 1) { SigSpec sig; for (auto c : equiv_cells) - sig.append(model.sigmap(c->getPort(ID::Y))); + sig.append(model.sigmap(c->getPort(TW::Y))); log(" Grouping SAT models for %s:\n", log_signal(sig)); } @@ -461,8 +461,8 @@ struct EquivSimplePass : public Pass { int unproven_cells_counter = 0; for (auto cell : module->selected_cells()) { - if (cell->type == ID($equiv) && cell->getPort(ID::A) != cell->getPort(ID::B)) { - auto bit = sigmap(cell->getPort(ID::Y).as_bit()); + if (cell->type == ID($equiv) && cell->getPort(TW::A) != cell->getPort(TW::B)) { + auto bit = sigmap(cell->getPort(TW::Y).as_bit()); auto bit_group = bit; if (cfg.group && bit_group.wire) bit_group.offset = 0; diff --git a/passes/equiv/equiv_status.cc b/passes/equiv/equiv_status.cc index da53c60a2..aabc03b1f 100644 --- a/passes/equiv/equiv_status.cc +++ b/passes/equiv/equiv_status.cc @@ -60,7 +60,7 @@ struct EquivStatusPass : public Pass { for (auto cell : module->selected_cells()) if (cell->type == ID($equiv)) { - if (cell->getPort(ID::A) != cell->getPort(ID::B)) + if (cell->getPort(TW::A) != cell->getPort(TW::B)) unproven_equiv_cells.push_back(cell); else proven_equiv_cells++; @@ -77,7 +77,7 @@ struct EquivStatusPass : public Pass { log(" Equivalence successfully proven!\n"); } else { for (auto cell : unproven_equiv_cells) - log(" Unproven $equiv %s: %s %s\n", cell, log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B))); + log(" Unproven $equiv %s: %s %s\n", cell, log_signal(cell->getPort(TW::A)), log_signal(cell->getPort(TW::B))); } unproven_count += GetSize(unproven_equiv_cells); diff --git a/passes/equiv/equiv_struct.cc b/passes/equiv/equiv_struct.cc index 7f8d8d282..eab6ac314 100644 --- a/passes/equiv/equiv_struct.cc +++ b/passes/equiv/equiv_struct.cc @@ -85,7 +85,7 @@ struct EquivStructWorker for (int i = 0; i < GetSize(inputs_a); i++) { SigBit bit_a = inputs_a[i], bit_b = inputs_b[i]; - SigBit bit_y = module->addWire(NEW_ID); + SigBit bit_y = module->addWire(NEW_TWINE); log(" New $equiv for input %s: A: %s, B: %s, Y: %s\n", input_names[i].c_str(), log_signal(bit_a), log_signal(bit_b), log_signal(bit_y)); module->addEquiv(NEW_ID, bit_a, bit_b, bit_y); @@ -127,8 +127,8 @@ struct EquivStructWorker for (auto cell : module->selected_cells()) if (cell->type == ID($equiv)) { - SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit()); - SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit()); + SigBit sig_a = sigmap(cell->getPort(TW::A).as_bit()); + SigBit sig_b = sigmap(cell->getPort(TW::B).as_bit()); equiv_bits.add(sig_b, sig_a); equiv_inputs.insert(sig_a); equiv_inputs.insert(sig_b); @@ -140,9 +140,9 @@ struct EquivStructWorker for (auto cell : module->selected_cells()) if (cell->type == ID($equiv)) { - SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit()); - SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit()); - SigBit sig_y = sigmap(cell->getPort(ID::Y).as_bit()); + SigBit sig_a = sigmap(cell->getPort(TW::A).as_bit()); + SigBit sig_b = sigmap(cell->getPort(TW::B).as_bit()); + SigBit sig_y = sigmap(cell->getPort(TW::Y).as_bit()); if (sig_a == sig_b && equiv_inputs.count(sig_y)) { log(" Purging redundant $equiv cell %s.\n", cell); module->connect(sig_y, sig_a); diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index ad53ba187..94d30ce50 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -67,8 +67,8 @@ ret_false: recursion_monitor.insert(cellport.first); - RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort(ID::A)); - RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort(ID::B)); + RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort(TW::A)); + RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort(TW::B)); if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor, mux_tree_cache)) { recursion_monitor.erase(cellport.first); @@ -101,7 +101,7 @@ static bool check_state_users(RTLIL::SigSpec sig) continue; if (cell->type.in(ID($input_port), ID($output_port), ID($public))) continue; - if (cell->type == ID($logic_not) && assign_map(cell->getPort(ID::A)) == sig) + if (cell->type == ID($logic_not) && assign_map(cell->getPort(TW::A)) == sig) continue; if (cellport.second != ID::A && cellport.second != ID::B) return false; @@ -110,9 +110,9 @@ static bool check_state_users(RTLIL::SigSpec sig) for (auto &port_it : cell->connections()) if (port_it.first != ID::A && port_it.first != ID::B && port_it.first != ID::Y) return false; - if (assign_map(cell->getPort(ID::A)) == sig && cell->getPort(ID::B).is_fully_const()) + if (assign_map(cell->getPort(TW::A)) == sig && cell->getPort(TW::B).is_fully_const()) continue; - if (assign_map(cell->getPort(ID::B)) == sig && cell->getPort(ID::A).is_fully_const()) + if (assign_map(cell->getPort(TW::B)) == sig && cell->getPort(TW::A).is_fully_const()) continue; return false; } @@ -150,8 +150,8 @@ static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false) muxtree_cells.clear(); pool recursion_monitor; - RTLIL::SigSpec sig_q = assign_map(cellport.first->getPort(ID::Q)); - RTLIL::SigSpec sig_d = assign_map(cellport.first->getPort(ID::D)); + RTLIL::SigSpec sig_q = assign_map(cellport.first->getPort(TW::Q)); + RTLIL::SigSpec sig_d = assign_map(cellport.first->getPort(TW::D)); dict mux_tree_cache; if (sig_q != assign_map(wire)) @@ -203,7 +203,7 @@ static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false) SigSpec sig_y = sig_d, sig_undef; if (!ignore_self_reset) { if (cellport.first->type == ID($adff)) { - SigSpec sig_arst = assign_map(cellport.first->getPort(ID::ARST)); + SigSpec sig_arst = assign_map(cellport.first->getPort(TW::ARST)); if (ce.eval(sig_arst, sig_undef)) is_self_resetting = true; } diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index 40c1d9904..dc7b3f96c 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -35,12 +35,12 @@ struct FsmExpand bool full_mode; SigMap assign_map; - SigSet> sig2driver, sig2user; + SigSet> sig2driver, sig2user; CellTypes ct; - std::set> merged_set; - std::set> current_set; - std::set> no_candidate_set; + std::set> merged_set; + std::set> current_set; + std::set> no_candidate_set; bool already_optimized; int limit_transitions; @@ -51,38 +51,38 @@ struct FsmExpand return true; if (cell->type.in(ID($mux), ID($pmux))) - if (cell->getPort(ID::A).size() < 2) + if (cell->getPort(TW::A).size() < 2) return true; int in_bits = 0; RTLIL::SigSpec new_signals; if (cell->hasPort(ID::A)) { - in_bits += GetSize(cell->getPort(ID::A)); - new_signals.append(assign_map(cell->getPort(ID::A))); + in_bits += GetSize(cell->getPort(TW::A)); + new_signals.append(assign_map(cell->getPort(TW::A))); } if (cell->hasPort(ID::B)) { - in_bits += GetSize(cell->getPort(ID::B)); - new_signals.append(assign_map(cell->getPort(ID::B))); + in_bits += GetSize(cell->getPort(TW::B)); + new_signals.append(assign_map(cell->getPort(TW::B))); } if (cell->hasPort(ID::S)) { - in_bits += GetSize(cell->getPort(ID::S)); - new_signals.append(assign_map(cell->getPort(ID::S))); + in_bits += GetSize(cell->getPort(TW::S)); + new_signals.append(assign_map(cell->getPort(TW::S))); } if (in_bits > 8) return false; if (cell->hasPort(ID::Y)) - new_signals.append(assign_map(cell->getPort(ID::Y))); + new_signals.append(assign_map(cell->getPort(TW::Y))); new_signals.sort_and_unify(); new_signals.remove_const(); - new_signals.remove(assign_map(fsm_cell->getPort(ID::CTRL_IN))); - new_signals.remove(assign_map(fsm_cell->getPort(ID::CTRL_OUT))); + new_signals.remove(assign_map(fsm_cell->getPort(TW::CTRL_IN))); + new_signals.remove(assign_map(fsm_cell->getPort(TW::CTRL_OUT))); if (new_signals.size() > 3) return false; @@ -94,10 +94,10 @@ struct FsmExpand { std::vector cell_list; - for (auto c : sig2driver.find(assign_map(fsm_cell->getPort(ID::CTRL_IN)))) + for (auto c : sig2driver.find(assign_map(fsm_cell->getPort(TW::CTRL_IN)))) cell_list.push_back(c); - for (auto c : sig2user.find(assign_map(fsm_cell->getPort(ID::CTRL_OUT)))) + for (auto c : sig2user.find(assign_map(fsm_cell->getPort(TW::CTRL_OUT)))) cell_list.push_back(c); current_set.clear(); @@ -160,11 +160,11 @@ struct FsmExpand RTLIL::Const in_val(i, input_sig.size()); RTLIL::SigSpec A, B, S; if (cell->hasPort(ID::A)) - A = assign_map(cell->getPort(ID::A)); + A = assign_map(cell->getPort(TW::A)); if (cell->hasPort(ID::B)) - B = assign_map(cell->getPort(ID::B)); + B = assign_map(cell->getPort(TW::B)); if (cell->hasPort(ID::S)) - S = assign_map(cell->getPort(ID::S)); + S = assign_map(cell->getPort(TW::S)); A.replace(input_sig, RTLIL::SigSpec(in_val)); B.replace(input_sig, RTLIL::SigSpec(in_val)); S.replace(input_sig, RTLIL::SigSpec(in_val)); @@ -178,14 +178,14 @@ struct FsmExpand fsm_data.copy_from_cell(fsm_cell); fsm_data.num_inputs += input_sig.size(); - RTLIL::SigSpec new_ctrl_in = fsm_cell->getPort(ID::CTRL_IN); + RTLIL::SigSpec new_ctrl_in = fsm_cell->getPort(TW::CTRL_IN); new_ctrl_in.append(input_sig); - fsm_cell->setPort(ID::CTRL_IN, new_ctrl_in); + fsm_cell->setPort(TW::CTRL_IN, new_ctrl_in); fsm_data.num_outputs += output_sig.size(); - RTLIL::SigSpec new_ctrl_out = fsm_cell->getPort(ID::CTRL_OUT); + RTLIL::SigSpec new_ctrl_out = fsm_cell->getPort(TW::CTRL_OUT); new_ctrl_out.append(output_sig); - fsm_cell->setPort(ID::CTRL_OUT, new_ctrl_out); + fsm_cell->setPort(TW::CTRL_OUT, new_ctrl_out); if (GetSize(input_sig) > 10) log_warning("Cell %s.%s (%s) has %d input bits, merging into FSM %s.%s might be problematic.\n", diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index bed58bc40..af59be206 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -75,10 +75,10 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL return false; } - RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); - RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B)); - RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S)); - RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y)); + RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A)); + RTLIL::SigSpec sig_b = assign_map(cell->getPort(TW::B)); + RTLIL::SigSpec sig_s = assign_map(cell->getPort(TW::S)); + RTLIL::SigSpec sig_y = assign_map(cell->getPort(TW::Y)); RTLIL::SigSpec sig_aa = sig; sig_aa.replace(sig_y, sig_a); @@ -275,12 +275,12 @@ static void extract_fsm(RTLIL::Wire *wire) if ((cell->type != ID($dff) && cell->type != ID($adff)) || cellport.second != ID::Q) continue; log(" found %s cell for state register: %s\n", cell->type, cell->name); - RTLIL::SigSpec sig_q = assign_map(cell->getPort(ID::Q)); - RTLIL::SigSpec sig_d = assign_map(cell->getPort(ID::D)); - clk = cell->getPort(ID::CLK); + RTLIL::SigSpec sig_q = assign_map(cell->getPort(TW::Q)); + RTLIL::SigSpec sig_d = assign_map(cell->getPort(TW::D)); + clk = cell->getPort(TW::CLK); clk_polarity = cell->parameters[ID::CLK_POLARITY].as_bool(); if (cell->type == ID($adff)) { - arst = cell->getPort(ID::ARST); + arst = cell->getPort(TW::ARST); arst_polarity = cell->parameters[ID::ARST_POLARITY].as_bool(); reset_state = cell->parameters[ID::ARST_VALUE]; } @@ -320,11 +320,11 @@ static void extract_fsm(RTLIL::Wire *wire) sig2trigger.find(dff_out, cellport_list); for (auto &cellport : cellport_list) { RTLIL::Cell *cell = module->cell(cellport.first); - RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); + RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A)); RTLIL::SigSpec sig_b; if (cell->hasPort(ID::B)) - sig_b = assign_map(cell->getPort(ID::B)); - RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y)); + sig_b = assign_map(cell->getPort(TW::B)); + RTLIL::SigSpec sig_y = assign_map(cell->getPort(TW::Y)); if (cellport.second == ID::A && !sig_b.is_fully_const()) continue; if (cellport.second == ID::B && !sig_a.is_fully_const()) @@ -369,12 +369,12 @@ static void extract_fsm(RTLIL::Wire *wire) // create fsm cell RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name, autoidx++), ID($fsm)); - fsm_cell->setPort(ID::CLK, clk); - fsm_cell->setPort(ID::ARST, arst); + fsm_cell->setPort(TW::CLK, clk); + fsm_cell->setPort(TW::ARST, arst); fsm_cell->parameters[ID::CLK_POLARITY] = clk_polarity ? State::S1 : State::S0; fsm_cell->parameters[ID::ARST_POLARITY] = arst_polarity ? State::S1 : State::S0; - fsm_cell->setPort(ID::CTRL_IN, ctrl_in); - fsm_cell->setPort(ID::CTRL_OUT, ctrl_out); + fsm_cell->setPort(TW::CTRL_IN, ctrl_in); + fsm_cell->setPort(TW::CTRL_OUT, ctrl_out); fsm_cell->parameters[ID::NAME] = RTLIL::Const(wire->name.str()); fsm_cell->attributes = wire->attributes; if(fsm_cell->attributes.count(ID::hdlname)) { @@ -452,14 +452,14 @@ struct FsmExtractPass : public Pass { sig2driver.insert(sig, sig2driver_entry_t(cell->name, conn_it.first)); } if (ct.cell_input(cell->type, conn_it.first) && cell->hasPort(ID::Y) && - cell->getPort(ID::Y).size() == 1 && (conn_it.first == ID::A || conn_it.first == ID::B)) { + cell->getPort(TW::Y).size() == 1 && (conn_it.first == ID::A || conn_it.first == ID::B)) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); sig2trigger.insert(sig, sig2driver_entry_t(cell->name, conn_it.first)); } } if (cell->type == ID($pmux)) { - RTLIL::SigSpec sel_sig = assign_map(cell->getPort(ID::S)); + RTLIL::SigSpec sel_sig = assign_map(cell->getPort(TW::S)); for (auto &bit1 : sel_sig) for (auto &bit2 : sel_sig) if (bit1 != bit2) diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index c19edcc88..595cc3232 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -71,13 +71,13 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map 0) { - RTLIL::Wire *eq_wire = module->addWire(NEW_ID); + RTLIL::Wire *eq_wire = module->addWire(NEW_TWINE); and_sig.append(RTLIL::SigSpec(eq_wire)); - RTLIL::Cell *eq_cell = module->addCell(NEW_ID, ID($eq)); - eq_cell->setPort(ID::A, eq_sig_a); - eq_cell->setPort(ID::B, eq_sig_b); - eq_cell->setPort(ID::Y, RTLIL::SigSpec(eq_wire)); + RTLIL::Cell *eq_cell = module->addCell(NEW_TWINE, ID($eq)); + eq_cell->setPort(TW::A, eq_sig_a); + eq_cell->setPort(TW::B, eq_sig_b); + eq_cell->setPort(TW::Y, RTLIL::SigSpec(eq_wire)); eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false); eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(false); eq_cell->parameters[ID::A_WIDTH] = RTLIL::Const(eq_sig_a.size()); @@ -99,12 +99,12 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapaddWire(NEW_ID); + RTLIL::Wire *or_wire = module->addWire(NEW_TWINE); and_sig.append(RTLIL::SigSpec(or_wire)); - RTLIL::Cell *or_cell = module->addCell(NEW_ID, ID($reduce_or)); - or_cell->setPort(ID::A, or_sig); - or_cell->setPort(ID::Y, RTLIL::SigSpec(or_wire)); + RTLIL::Cell *or_cell = module->addCell(NEW_TWINE, ID($reduce_or)); + or_cell->setPort(TW::A, or_sig); + or_cell->setPort(TW::Y, RTLIL::SigSpec(or_wire)); or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false); or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(or_sig.size()); or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1); @@ -115,13 +115,13 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapaddWire(NEW_ID); + RTLIL::Wire *and_wire = module->addWire(NEW_TWINE); cases_vector.append(RTLIL::SigSpec(and_wire)); - RTLIL::Cell *and_cell = module->addCell(NEW_ID, ID($and)); - and_cell->setPort(ID::A, and_sig.extract(0, 1)); - and_cell->setPort(ID::B, and_sig.extract(1, 1)); - and_cell->setPort(ID::Y, RTLIL::SigSpec(and_wire)); + RTLIL::Cell *and_cell = module->addCell(NEW_TWINE, ID($and)); + and_cell->setPort(TW::A, and_sig.extract(0, 1)); + and_cell->setPort(TW::B, and_sig.extract(1, 1)); + and_cell->setPort(TW::Y, RTLIL::SigSpec(and_wire)); and_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false); and_cell->parameters[ID::B_SIGNED] = RTLIL::Const(false); and_cell->parameters[ID::A_WIDTH] = RTLIL::Const(1); @@ -141,9 +141,9 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map 1) { - RTLIL::Cell *or_cell = module->addCell(NEW_ID, ID($reduce_or)); - or_cell->setPort(ID::A, cases_vector); - or_cell->setPort(ID::Y, output); + RTLIL::Cell *or_cell = module->addCell(NEW_TWINE, ID($reduce_or)); + or_cell->setPort(TW::A, cases_vector); + or_cell->setPort(TW::Y, output); or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false); or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(cases_vector.size()); or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1); @@ -161,16 +161,16 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) FsmData fsm_data; fsm_data.copy_from_cell(fsm_cell); - RTLIL::SigSpec ctrl_in = fsm_cell->getPort(ID::CTRL_IN); - RTLIL::SigSpec ctrl_out = fsm_cell->getPort(ID::CTRL_OUT); + RTLIL::SigSpec ctrl_in = fsm_cell->getPort(TW::CTRL_IN); + RTLIL::SigSpec ctrl_out = fsm_cell->getPort(TW::CTRL_OUT); // create state register RTLIL::Wire *state_wire = module->addWire(module->uniquify(fsm_cell->parameters[ID::NAME].decode_string()), fsm_data.state_bits); - RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits); + RTLIL::Wire *next_state_wire = module->addWire(NEW_TWINE, fsm_data.state_bits); - RTLIL::Cell *state_dff = module->addCell(NEW_ID, ""); - if (fsm_cell->getPort(ID::ARST).is_fully_const()) { + RTLIL::Cell *state_dff = module->addCell(NEW_TWINE, ""); + if (fsm_cell->getPort(TW::ARST).is_fully_const()) { state_dff->type = ID($dff); } else { state_dff->type = ID($adff); @@ -179,19 +179,19 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) for (auto bit : state_dff->parameters[ID::ARST_VALUE]) if (bit != RTLIL::State::S1) bit = RTLIL::State::S0; - state_dff->setPort(ID::ARST, fsm_cell->getPort(ID::ARST)); + state_dff->setPort(TW::ARST, fsm_cell->getPort(TW::ARST)); } state_dff->parameters[ID::WIDTH] = RTLIL::Const(fsm_data.state_bits); state_dff->parameters[ID::CLK_POLARITY] = fsm_cell->parameters[ID::CLK_POLARITY]; - state_dff->setPort(ID::CLK, fsm_cell->getPort(ID::CLK)); - state_dff->setPort(ID::D, RTLIL::SigSpec(next_state_wire)); - state_dff->setPort(ID::Q, RTLIL::SigSpec(state_wire)); + state_dff->setPort(TW::CLK, fsm_cell->getPort(TW::CLK)); + state_dff->setPort(TW::D, RTLIL::SigSpec(next_state_wire)); + state_dff->setPort(TW::Q, RTLIL::SigSpec(state_wire)); // decode state register bool encoding_is_onehot = true; - RTLIL::Wire *state_onehot = module->addWire(NEW_ID, fsm_data.state_table.size()); + RTLIL::Wire *state_onehot = module->addWire(NEW_TWINE, fsm_data.state_table.size()); for (size_t i = 0; i < fsm_data.state_table.size(); i++) { @@ -212,10 +212,10 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) { encoding_is_onehot = false; - RTLIL::Cell *eq_cell = module->addCell(NEW_ID, ID($eq)); - eq_cell->setPort(ID::A, sig_a); - eq_cell->setPort(ID::B, sig_b); - eq_cell->setPort(ID::Y, RTLIL::SigSpec(state_onehot, i)); + RTLIL::Cell *eq_cell = module->addCell(NEW_TWINE, ID($eq)); + eq_cell->setPort(TW::A, sig_a); + eq_cell->setPort(TW::B, sig_b); + eq_cell->setPort(TW::Y, RTLIL::SigSpec(state_onehot, i)); eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false); eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(false); eq_cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig_a.size()); @@ -235,7 +235,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) } else { - RTLIL::Wire *next_state_onehot = module->addWire(NEW_ID, fsm_data.state_table.size()); + RTLIL::Wire *next_state_onehot = module->addWire(NEW_TWINE, fsm_data.state_table.size()); for (size_t i = 0; i < fsm_data.state_table.size(); i++) { @@ -285,11 +285,11 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) } } - RTLIL::Cell *mux_cell = module->addCell(NEW_ID, ID($pmux)); - mux_cell->setPort(ID::A, sig_a); - mux_cell->setPort(ID::B, sig_b); - mux_cell->setPort(ID::S, sig_s); - mux_cell->setPort(ID::Y, RTLIL::SigSpec(next_state_wire)); + RTLIL::Cell *mux_cell = module->addCell(NEW_TWINE, ID($pmux)); + mux_cell->setPort(TW::A, sig_a); + mux_cell->setPort(TW::B, sig_b); + mux_cell->setPort(TW::S, sig_s); + mux_cell->setPort(TW::Y, RTLIL::SigSpec(next_state_wire)); mux_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_a.size()); mux_cell->parameters[ID::S_WIDTH] = RTLIL::Const(sig_s.size()); } diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index b61dec890..d66150ac2 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -98,7 +98,7 @@ struct FsmOpt void opt_const_and_unused_inputs() { - RTLIL::SigSpec ctrl_in = cell->getPort(ID::CTRL_IN); + RTLIL::SigSpec ctrl_in = cell->getPort(TW::CTRL_IN); std::vector ctrl_in_used(ctrl_in.size()); std::vector new_transition_table; @@ -119,15 +119,15 @@ struct FsmOpt for (int i = int(ctrl_in_used.size())-1; i >= 0; i--) { if (!ctrl_in_used[i]) { - log(" Removing unused input signal %s.\n", log_signal(cell->getPort(ID::CTRL_IN).extract(i, 1))); + log(" Removing unused input signal %s.\n", log_signal(cell->getPort(TW::CTRL_IN).extract(i, 1))); for (auto &tr : new_transition_table) { RTLIL::SigSpec tmp(tr.ctrl_in); tmp.remove(i, 1); tr.ctrl_in = tmp.as_const(); } - RTLIL::SigSpec new_ctrl_in = cell->getPort(ID::CTRL_IN); + RTLIL::SigSpec new_ctrl_in = cell->getPort(TW::CTRL_IN); new_ctrl_in.remove(i, 1); - cell->setPort(ID::CTRL_IN, new_ctrl_in); + cell->setPort(TW::CTRL_IN, new_ctrl_in); fsm_data.num_inputs--; } } @@ -139,12 +139,12 @@ struct FsmOpt void opt_unused_outputs() { for (int i = 0; i < fsm_data.num_outputs; i++) { - RTLIL::SigSpec sig = cell->getPort(ID::CTRL_OUT).extract(i, 1); + RTLIL::SigSpec sig = cell->getPort(TW::CTRL_OUT).extract(i, 1); if (signal_is_unused(sig)) { log(" Removing unused output signal %s.\n", log_signal(sig)); - RTLIL::SigSpec new_ctrl_out = cell->getPort(ID::CTRL_OUT); + RTLIL::SigSpec new_ctrl_out = cell->getPort(TW::CTRL_OUT); new_ctrl_out.remove(i, 1); - cell->setPort(ID::CTRL_OUT, new_ctrl_out); + cell->setPort(TW::CTRL_OUT, new_ctrl_out); for (auto &tr : fsm_data.transition_table) { RTLIL::SigSpec tmp(tr.ctrl_out); tmp.remove(i, 1); diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h index 4d824e136..8bffbc2ea 100644 --- a/passes/fsm/fsmdata.h +++ b/passes/fsm/fsmdata.h @@ -127,13 +127,13 @@ struct FsmData log("\n"); log(" Input signals:\n"); - RTLIL::SigSpec sig_in = cell->getPort(ID::CTRL_IN); + RTLIL::SigSpec sig_in = cell->getPort(TW::CTRL_IN); for (int i = 0; i < GetSize(sig_in); i++) log(" %3d: %s\n", i, log_signal(sig_in[i])); log("\n"); log(" Output signals:\n"); - RTLIL::SigSpec sig_out = cell->getPort(ID::CTRL_OUT); + RTLIL::SigSpec sig_out = cell->getPort(TW::CTRL_OUT); for (int i = 0; i < GetSize(sig_out); i++) log(" %3d: %s\n", i, log_signal(sig_out[i])); diff --git a/passes/hierarchy/flatten.cc b/passes/hierarchy/flatten.cc index ce63bcc4b..601730c88 100644 --- a/passes/hierarchy/flatten.cc +++ b/passes/hierarchy/flatten.cc @@ -275,7 +275,7 @@ struct FlattenWorker if (create_scopeinfo && cell_name.isPublic()) { // The $scopeinfo's name will be changed below after removing the flattened cell - scopeinfo = module->addCell(NEW_ID, ID($scopeinfo)); + scopeinfo = module->addCell(NEW_TWINE, ID($scopeinfo)); scopeinfo->setParam(ID::TYPE, RTLIL::Const("module")); for (auto const &attr : cell->attributes) diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 728bdf485..7d8e2302a 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -98,7 +98,7 @@ void generate(RTLIL::Design *design, const std::vector &celltypes, } while (portnames.size() > 0) { - RTLIL::IdString portname = *portnames.begin(); + TwineRef portname = *portnames.begin(); for (auto &decl : portdecls) if (decl.index == 0 && patmatch(decl.portname.c_str(), portname.unescape().c_str())) { generate_port_decl_t d = decl; @@ -604,7 +604,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check for (auto &conn : cell->connections_) { int conn_size = conn.second.size(); - RTLIL::IdString portname = conn.first; + TwineRef portname = conn.first; if (portname.begins_with("$")) { int port_id = atoi(portname.substr(1).c_str()); for (auto wire : mod->wires()) @@ -1421,7 +1421,7 @@ struct HierarchyPass : public Pass { continue; } - Wire *t = module->addWire(NEW_ID, GetSize(c)); + Wire *t = module->addWire(NEW_TWINE, GetSize(c)); new_sig.append(t); update_port = true; @@ -1524,7 +1524,7 @@ struct HierarchyPass : public Pass { if (w->port_input && !w->port_output) sig.extend_u0(GetSize(w), sig.is_wire() && sig.as_wire()->is_signed); else - sig.append(module->addWire(NEW_ID, n)); + sig.append(module->addWire(NEW_TWINE, n)); } if (!conn.second.is_fully_const() || !w->port_input || w->port_output) diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 885af5388..7854a5ba6 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -233,10 +233,10 @@ struct SubmodWorker auto &b = old_sig[i]; // Prevents "ERROR: Mismatch in directionality ..." when flattening if (!b.wire) - b = module->addWire(NEW_ID); + b = module->addWire(NEW_TWINE); // Prevents "Warning: multiple conflicting drivers ..." else if (!it.second.is_int_driven[i]) - b = module->addWire(NEW_ID); + b = module->addWire(NEW_TWINE); } new_cell->setPort(new_wire->name, old_sig); } diff --git a/passes/memory/memory_bmux2rom.cc b/passes/memory/memory_bmux2rom.cc index a3fc5a7fc..105afd392 100644 --- a/passes/memory/memory_bmux2rom.cc +++ b/passes/memory/memory_bmux2rom.cc @@ -50,7 +50,7 @@ struct MemoryBmux2RomPass : public Pass { if (cell->type != ID($bmux)) continue; - SigSpec sig_a = cell->getPort(ID::A); + SigSpec sig_a = cell->getPort(TW::A); if (!sig_a.is_fully_const()) continue; @@ -70,8 +70,8 @@ struct MemoryBmux2RomPass : public Pass { mem.inits.push_back(std::move(init)); MemRd rd; - rd.addr = cell->getPort(ID::S); - rd.data = cell->getPort(ID::Y); + rd.addr = cell->getPort(TW::S); + rd.data = cell->getPort(TW::Y); rd.init_value = Const(State::Sx, width); rd.arst_value = Const(State::Sx, width); rd.srst_value = Const(State::Sx, width); diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index aab28b75d..094a4e637 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -903,7 +903,7 @@ grow_read_ports:; // Swizzle read ports. for (auto &port : mem.rd_ports) { - SigSpec new_data = module->addWire(NEW_ID, mem.width); + SigSpec new_data = module->addWire(NEW_TWINE, mem.width); Const new_init_value = Const(State::Sx, mem.width); Const new_arst_value = Const(State::Sx, mem.width); Const new_srst_value = Const(State::Sx, mem.width); @@ -1023,12 +1023,12 @@ grow_read_ports:; auto &port = mem.rd_ports[pi.mapped_port]; SigSpec sig_data = port.data.extract(grid_d * bram.dbits, bram.dbits); - SigSpec bram_dout = module->addWire(NEW_ID, bram.dbits); + SigSpec bram_dout = module->addWire(NEW_TWINE, bram.dbits); c->setPort(stringf("\\%sDATA", pf), bram_dout); SigSpec addr_ok_q = addr_ok; if (port.clk_enable && !addr_ok.empty()) { - addr_ok_q = module->addWire(NEW_ID); + addr_ok_q = module->addWire(NEW_TWINE); module->addDffe(NEW_ID, port.clk, port.en, addr_ok, addr_ok_q, port.clk_polarity); } diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 916b21233..12b8d2ad6 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -177,7 +177,7 @@ struct MemQueryCache if (!driver.cell->type.in(ID($mux), ID($pmux))) return false; log_assert(driver.port == ID::Y); - SigSpec sig_s = driver.cell->getPort(ID::S); + SigSpec sig_s = driver.cell->getPort(TW::S); int sel_sat = qcsat.importSigBit(sel); if (neg_sel) sel_sat = qcsat.ez->NOT(sel_sat); @@ -187,14 +187,14 @@ struct MemQueryCache int sbit = qcsat.importSigBit(sig_s[i]); qcsat.prepare(); if (!qcsat.ez->solve(port_ren, sel_sat, qcsat.ez->NOT(sbit))) { - bit = driver.cell->getPort(ID::B)[i * width + driver.offset]; + bit = driver.cell->getPort(TW::B)[i * width + driver.offset]; return true; } if (qcsat.ez->solve(port_ren, sel_sat, sbit)) all_0 = false; } if (all_0) { - bit = driver.cell->getPort(ID::A)[driver.offset]; + bit = driver.cell->getPort(TW::A)[driver.offset]; return true; } return false; @@ -264,7 +264,7 @@ struct MemoryDffWorker } else { continue; } - SigSpec y = consumer.cell->getPort(ID::Y); + SigSpec y = consumer.cell->getPort(TW::Y); int mux_width = GetSize(y); SigBit ybit = y.extract(consumer.offset); if (prev_cell != consumer.cell || prev_idx+1 != i || prev_is_b != is_b) { @@ -272,7 +272,7 @@ struct MemoryDffWorker md.base_idx = i; md.size = 0; md.is_b = is_b; - md.sig_s = consumer.cell->getPort(ID::S); + md.sig_s = consumer.cell->getPort(TW::S); md.sig_other.resize(GetSize(md.sig_s)); prev_cell = consumer.cell; prev_is_b = is_b; diff --git a/passes/memory/memory_libmap.cc b/passes/memory/memory_libmap.cc index a7be16577..6239c2478 100644 --- a/passes/memory/memory_libmap.cc +++ b/passes/memory/memory_libmap.cc @@ -142,13 +142,13 @@ struct MapWorker { { if (cell->type == ID($mux)) { - RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A)); - RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(ID::B)); + RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(TW::A)); + RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(TW::B)); if (sig_a.is_fully_undef()) - sigmap_xmux.add(cell->getPort(ID::Y), sig_b); + sigmap_xmux.add(cell->getPort(TW::Y), sig_b); else if (sig_b.is_fully_undef()) - sigmap_xmux.add(cell->getPort(ID::Y), sig_a); + sigmap_xmux.add(cell->getPort(TW::Y), sig_a); } } } @@ -1665,14 +1665,14 @@ std::vector generate_mux(Mem &mem, int rpidx, const Swizzle &swz) { return {port.data}; } if (port.clk_enable) { - SigSpec new_sig_s = mem.module->addWire(NEW_ID, GetSize(sig_s)); + SigSpec new_sig_s = mem.module->addWire(NEW_TWINE, GetSize(sig_s)); mem.module->addDffe(NEW_ID, port.clk, port.en, sig_s, new_sig_s, port.clk_polarity); sig_s = new_sig_s; } SigSpec sig_a = Const(State::Sx, GetSize(port.data) << hi_bits << GetSize(swz.addr_mux_bits)); for (int i = 0; i < ((swz.addr_end - swz.addr_start) >> swz.addr_shift); i++) { for (int j = 0; j < (1 << GetSize(swz.addr_mux_bits)); j++) { - SigSpec sig = mem.module->addWire(NEW_ID, GetSize(port.data)); + SigSpec sig = mem.module->addWire(NEW_TWINE, GetSize(port.data)); int hi = ((swz.addr_start >> swz.addr_shift) + i) & ((1 << hi_bits) - 1); int pos = (hi << GetSize(swz.addr_mux_bits) | j) * GetSize(port.data); for (int k = 0; k < GetSize(port.data); k++) @@ -1948,7 +1948,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector &cells, cons cell->setParam(stringf("\\PORT_%s_RD_SRST_VALUE", name), hw_val); } } - SigSpec hw_rdata = mem.module->addWire(NEW_ID, width); + SigSpec hw_rdata = mem.module->addWire(NEW_TWINE, width); cell->setPort(stringf("\\PORT_%s_RD_DATA", name), hw_rdata); SigSpec lhs; SigSpec rhs; @@ -1983,7 +1983,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector &cells, cons else if (pdef.rdsrstval == ResetValKind::NoUndef) cell->setParam(stringf("\\PORT_%s_RD_SRST_VALUE", name), Const(State::S0, width)); } - SigSpec hw_rdata = mem.module->addWire(NEW_ID, width); + SigSpec hw_rdata = mem.module->addWire(NEW_TWINE, width); cell->setPort(stringf("\\PORT_%s_RD_DATA", name), hw_rdata); } } diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 04299d570..1ef4ade28 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -241,7 +241,7 @@ struct MemoryMapWorker } else { c = module->addCell(ff_id, ID($dff)); c->parameters[ID::CLK_POLARITY] = RTLIL::Const(RTLIL::State::S1); - c->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::S0)); + c->setPort(TW::CLK, RTLIL::SigSpec(RTLIL::State::S0)); } } else if (async_wr) { log_assert(formal); // General async write not implemented yet, checked against above @@ -249,14 +249,14 @@ struct MemoryMapWorker } else { c = module->addCell(ff_id, ID($dff)); c->parameters[ID::CLK_POLARITY] = RTLIL::Const(refclock_pol); - c->setPort(ID::CLK, refclock); + c->setPort(TW::CLK, refclock); } c->set_src_attribute(mem_src); c->parameters[ID::WIDTH] = mem.width; RTLIL::Wire *w_in = module->addWire(genid(mem.memid, "", addr, "$d"), mem.width); data_reg_in[idx] = w_in; - c->setPort(ID::D, w_in); + c->setPort(TW::D, w_in); std::string w_out_name = stringf("%s[%d]", mem.memid, addr); if (module->wire(RTLIL::IdString(w_out_name)) != nullptr) @@ -276,7 +276,7 @@ struct MemoryMapWorker w_out->attributes[ID::init] = w_init.as_const(); data_reg_out[idx] = w_out; - c->setPort(ID::Q, w_out); + c->setPort(TW::Q, w_out); if (static_only) module->connect(RTLIL::SigSig(w_in, w_out)); @@ -308,15 +308,15 @@ struct MemoryMapWorker RTLIL::Cell *c = module->addCell(genid(mem.memid, "$rdmux", i, "", j, "", k), ID($mux)); c->set_src_attribute(mem_src); c->parameters[ID::WIDTH] = GetSize(port.data); - c->setPort(ID::Y, rd_signals[k]); - c->setPort(ID::S, rd_addr.extract(abits-j-1, 1)); + c->setPort(TW::Y, rd_signals[k]); + c->setPort(TW::S, rd_addr.extract(abits-j-1, 1)); count_mux++; - c->setPort(ID::A, module->addWire(genid(mem.memid, "$rdmux", i, "", j, "", k, "$a"), GetSize(port.data))); - c->setPort(ID::B, module->addWire(genid(mem.memid, "$rdmux", i, "", j, "", k, "$b"), GetSize(port.data))); + c->setPort(TW::A, module->addWire(genid(mem.memid, "$rdmux", i, "", j, "", k, "$a"), GetSize(port.data))); + c->setPort(TW::B, module->addWire(genid(mem.memid, "$rdmux", i, "", j, "", k, "$b"), GetSize(port.data))); - next_rd_signals.push_back(c->getPort(ID::A)); - next_rd_signals.push_back(c->getPort(ID::B)); + next_rd_signals.push_back(c->getPort(TW::A)); + next_rd_signals.push_back(c->getPort(TW::B)); } next_rd_signals.swap(rd_signals); @@ -372,22 +372,22 @@ struct MemoryMapWorker c->parameters[ID::A_WIDTH] = RTLIL::Const(1); c->parameters[ID::B_WIDTH] = RTLIL::Const(1); c->parameters[ID::Y_WIDTH] = RTLIL::Const(1); - c->setPort(ID::A, w); - c->setPort(ID::B, wr_bit); + c->setPort(TW::A, w); + c->setPort(TW::B, wr_bit); w = module->addWire(genid(mem.memid, "$wren", addr, "", j, "", wr_offset, "$y")); - c->setPort(ID::Y, RTLIL::SigSpec(w)); + c->setPort(TW::Y, RTLIL::SigSpec(w)); } RTLIL::Cell *c = module->addCell(genid(mem.memid, "$wrmux", addr, "", j, "", wr_offset), ID($mux)); c->set_src_attribute(mem_src); c->parameters[ID::WIDTH] = wr_width; - c->setPort(ID::A, sig.extract(wr_offset, wr_width)); - c->setPort(ID::B, port.data.extract(wr_offset + sub * mem.width, wr_width)); - c->setPort(ID::S, RTLIL::SigSpec(w)); + c->setPort(TW::A, sig.extract(wr_offset, wr_width)); + c->setPort(TW::B, port.data.extract(wr_offset + sub * mem.width, wr_width)); + c->setPort(TW::S, RTLIL::SigSpec(w)); w = module->addWire(genid(mem.memid, "$wrmux", addr, "", j, "", wr_offset, "$y"), wr_width); - c->setPort(ID::Y, w); + c->setPort(TW::Y, w); sig.replace(wr_offset, w); wr_offset += wr_width; diff --git a/passes/memory/memory_memx.cc b/passes/memory/memory_memx.cc index 54c71a0e8..29ccbe61f 100644 --- a/passes/memory/memory_memx.cc +++ b/passes/memory/memory_memx.cc @@ -63,7 +63,7 @@ struct MemoryMemxPass : public Pass { module, mem.memid.unescape()); SigSpec addr_ok = make_addr_check(mem, port.addr); - Wire *raw_rdata = module->addWire(NEW_ID, GetSize(port.data)); + Wire *raw_rdata = module->addWire(NEW_TWINE, GetSize(port.data)); module->addMux(NEW_ID, SigSpec(State::Sx, GetSize(port.data)), raw_rdata, addr_ok, port.data); port.data = raw_rdata; } diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index fbe41431a..adfe6ddaa 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -164,7 +164,7 @@ struct MemoryShareWorker port2.addr = addr2; mem.prepare_rd_merge(i, j, &initvals); mem.widen_prep(wide_log2); - SigSpec new_data = module->addWire(NEW_ID, mem.width << wide_log2); + SigSpec new_data = module->addWire(NEW_TWINE, mem.width << wide_log2); module->connect(port1.data, new_data.extract(sub1 * mem.width, mem.width << port1.wide_log2)); module->connect(port2.data, new_data.extract(sub2 * mem.width, mem.width << port2.wide_log2)); for (int k = 0; k < wide_log2; k++) @@ -438,7 +438,7 @@ struct MemoryShareWorker std::map, int> groups_en; RTLIL::SigSpec grouped_last_en, grouped_this_en, en; - RTLIL::Wire *grouped_en = module->addWire(NEW_ID, 0); + RTLIL::Wire *grouped_en = module->addWire(NEW_TWINE, 0); for (int j = 0; j < int(this_en.size()); j++) { std::pair key(last_en[j], this_en[j]); @@ -484,13 +484,13 @@ struct MemoryShareWorker { if (cell->type == ID($mux)) { - RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A)); - RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(ID::B)); + RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(TW::A)); + RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(TW::B)); if (sig_a.is_fully_undef()) - sigmap_xmux.add(cell->getPort(ID::Y), sig_b); + sigmap_xmux.add(cell->getPort(TW::Y), sig_b); else if (sig_b.is_fully_undef()) - sigmap_xmux.add(cell->getPort(ID::Y), sig_a); + sigmap_xmux.add(cell->getPort(TW::Y), sig_a); } } diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc index 773bbfde9..86417b748 100644 --- a/passes/opt/muxpack.cc +++ b/passes/opt/muxpack.cc @@ -38,11 +38,11 @@ struct ExclusiveDatabase pool reduce_or; for (auto cell : module->cells()) { if (cell->type == ID($eq)) { - SigSpec y_sig = sigmap(cell->getPort(ID::Y)); + SigSpec y_sig = sigmap(cell->getPort(TW::Y)); if (GetSize(y_sig) == 0) continue; - nonconst_sig = sigmap(cell->getPort(ID::A)); - const_sig = sigmap(cell->getPort(ID::B)); + nonconst_sig = sigmap(cell->getPort(TW::A)); + const_sig = sigmap(cell->getPort(TW::B)); if (!const_sig.is_fully_const()) { if (!nonconst_sig.is_fully_const()) continue; @@ -51,10 +51,10 @@ struct ExclusiveDatabase y_port = y_sig[0]; } else if (cell->type == ID($logic_not)) { - SigSpec y_sig = sigmap(cell->getPort(ID::Y)); + SigSpec y_sig = sigmap(cell->getPort(TW::Y)); if (GetSize(y_sig) == 0) continue; - nonconst_sig = sigmap(cell->getPort(ID::A)); + nonconst_sig = sigmap(cell->getPort(TW::A)); const_sig = Const(State::S0, GetSize(nonconst_sig)); y_port = y_sig[0]; } @@ -72,7 +72,7 @@ struct ExclusiveDatabase for (auto cell : reduce_or) { nonconst_sig = SigSpec(); std::vector values; - SigSpec a_port = sigmap(cell->getPort(ID::A)); + SigSpec a_port = sigmap(cell->getPort(TW::A)); for (auto bit : a_port) { auto it = sig_cmp_prev.find(bit); if (it == sig_cmp_prev.end()) { @@ -90,7 +90,7 @@ struct ExclusiveDatabase } if (nonconst_sig.empty()) continue; - SigSpec y_sig = sigmap(cell->getPort(ID::Y)); + SigSpec y_sig = sigmap(cell->getPort(TW::Y)); if (GetSize(y_sig) == 0) continue; y_port = y_sig[0]; @@ -154,11 +154,11 @@ struct MuxpackWorker { if (cell->type.in(ID($mux), ID($pmux)) && !cell->get_bool_attribute(ID::keep)) { - SigSpec a_sig = sigmap(cell->getPort(ID::A)); + SigSpec a_sig = sigmap(cell->getPort(TW::A)); SigSpec b_sig; if (cell->type == ID($mux)) - b_sig = sigmap(cell->getPort(ID::B)); - SigSpec y_sig = sigmap(cell->getPort(ID::Y)); + b_sig = sigmap(cell->getPort(TW::B)); + SigSpec y_sig = sigmap(cell->getPort(TW::Y)); if (sig_chain_next.count(a_sig)) for (auto a_bit : a_sig) @@ -195,9 +195,9 @@ struct MuxpackWorker { log_debug("Considering %s (%s)\n", cell, cell->type.unescape()); - SigSpec a_sig = sigmap(cell->getPort(ID::A)); + SigSpec a_sig = sigmap(cell->getPort(TW::A)); if (cell->type == ID($mux)) { - SigSpec b_sig = sigmap(cell->getPort(ID::B)); + SigSpec b_sig = sigmap(cell->getPort(TW::B)); if (sig_chain_prev.count(a_sig) + sig_chain_prev.count(b_sig) != 1) goto start_cell; @@ -217,8 +217,8 @@ struct MuxpackWorker { Cell *prev_cell = sig_chain_prev.at(a_sig); log_assert(prev_cell); - SigSpec s_sig = sigmap(cell->getPort(ID::S)); - s_sig.append(sigmap(prev_cell->getPort(ID::S))); + SigSpec s_sig = sigmap(cell->getPort(TW::S)); + s_sig.append(sigmap(prev_cell->getPort(TW::S))); if (!excl_db.query(s_sig)) goto start_cell; } @@ -239,7 +239,7 @@ struct MuxpackWorker { chain.push_back(c); - SigSpec y_sig = sigmap(c->getPort(ID::Y)); + SigSpec y_sig = sigmap(c->getPort(TW::Y)); if (sig_chain_next.count(y_sig) == 0) break; @@ -278,28 +278,28 @@ struct MuxpackWorker pmux_count += 1; first_cell->type = ID($pmux); - SigSpec b_sig = first_cell->getPort(ID::B); - SigSpec s_sig = first_cell->getPort(ID::S); + SigSpec b_sig = first_cell->getPort(TW::B); + SigSpec s_sig = first_cell->getPort(TW::S); for (int i = 1; i < cases; i++) { Cell* prev_cell = chain[cursor+i-1]; Cell* cursor_cell = chain[cursor+i]; - if (sigmap(prev_cell->getPort(ID::Y)) == sigmap(cursor_cell->getPort(ID::A))) { - b_sig.append(cursor_cell->getPort(ID::B)); - s_sig.append(cursor_cell->getPort(ID::S)); + if (sigmap(prev_cell->getPort(TW::Y)) == sigmap(cursor_cell->getPort(TW::A))) { + b_sig.append(cursor_cell->getPort(TW::B)); + s_sig.append(cursor_cell->getPort(TW::S)); } else { log_assert(cursor_cell->type == ID($mux)); - b_sig.append(cursor_cell->getPort(ID::A)); - s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(ID::S))); + b_sig.append(cursor_cell->getPort(TW::A)); + s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(TW::S))); } remove_cells.insert(cursor_cell); } - first_cell->setPort(ID::B, b_sig); - first_cell->setPort(ID::S, s_sig); + first_cell->setPort(TW::B, b_sig); + first_cell->setPort(TW::S, s_sig); first_cell->setParam(ID::S_WIDTH, GetSize(s_sig)); - first_cell->setPort(ID::Y, last_cell->getPort(ID::Y)); + first_cell->setPort(TW::Y, last_cell->getPort(TW::Y)); cursor += cases; } diff --git a/passes/opt/opt_balance_tree.cc b/passes/opt/opt_balance_tree.cc index 98d5b9928..bdf603837 100644 --- a/passes/opt/opt_balance_tree.cc +++ b/passes/opt/opt_balance_tree.cc @@ -77,7 +77,7 @@ struct OptBalanceTreeWorker { // Base case: if we have two sources, create a single cell if (sources.size() == 2) { // Create a new cell of the same type - Cell* new_cell = module->addCell(NEW_ID, cell_type); + Cell* new_cell = module->addCell(NEW_TWINE, cell_type); // Copy attributes from reference cell new_cell->attributes = cell->attributes; @@ -88,12 +88,12 @@ struct OptBalanceTreeWorker { out_width = max(sources[0].size(), sources[1].size()) + 1; else if (cell_type == ID($mul)) out_width = sources[0].size() + sources[1].size(); - Wire* out_wire = module->addWire(NEW_ID, out_width); + Wire* out_wire = module->addWire(NEW_TWINE, out_width); // Connect ports and fix up parameters - new_cell->setPort(ID::A, sources[0]); - new_cell->setPort(ID::B, sources[1]); - new_cell->setPort(ID::Y, out_wire); + new_cell->setPort(TW::A, sources[0]); + new_cell->setPort(TW::B, sources[1]); + new_cell->setPort(TW::Y, out_wire); new_cell->fixup_parameters(); new_cell->setParam(ID::A_SIGNED, cell->getParam(ID::A_SIGNED)); new_cell->setParam(ID::B_SIGNED, cell->getParam(ID::B_SIGNED)); @@ -112,7 +112,7 @@ struct OptBalanceTreeWorker { SigSpec right_tree = create_balanced_tree(right_sources, cell_type, cell); // Create a cell to combine the two subtrees - Cell* new_cell = module->addCell(NEW_ID, cell_type); + Cell* new_cell = module->addCell(NEW_TWINE, cell_type); // Copy attributes from reference cell new_cell->attributes = cell->attributes; @@ -123,12 +123,12 @@ struct OptBalanceTreeWorker { out_width = max(left_tree.size(), right_tree.size()) + 1; else if (cell_type == ID($mul)) out_width = left_tree.size() + right_tree.size(); - Wire* out_wire = module->addWire(NEW_ID, out_width); + Wire* out_wire = module->addWire(NEW_TWINE, out_width); // Connect ports and fix up parameters - new_cell->setPort(ID::A, left_tree); - new_cell->setPort(ID::B, right_tree); - new_cell->setPort(ID::Y, out_wire); + new_cell->setPort(TW::A, left_tree); + new_cell->setPort(TW::B, right_tree); + new_cell->setPort(TW::Y, out_wire); new_cell->fixup_parameters(); new_cell->setParam(ID::A_SIGNED, cell->getParam(ID::A_SIGNED)); new_cell->setParam(ID::B_SIGNED, cell->getParam(ID::B_SIGNED)); @@ -185,7 +185,7 @@ struct OptBalanceTreeWorker { // BFS, following all chains until they hit a cell of a different type // Pick the longest one - auto y = sigmap(cell->getPort(ID::Y)); + auto y = sigmap(cell->getPort(TW::Y)); pool sinks; pool current_loads = sig_to_sink[y]; pool next_loads; @@ -202,7 +202,7 @@ struct OptBalanceTreeWorker { continue; } - auto xy = sigmap(x->getPort(ID::Y)); + auto xy = sigmap(x->getPort(TW::Y)); // If this signal drives a port, add it to the sinks // (even though it may not be the end of a chain) @@ -300,7 +300,7 @@ struct OptBalanceTreeWorker { SigSpec tree_output = create_balanced_tree(source_signals, cell_type, head_cell); // Connect the tree output to the head cell's output - SigSpec head_output = sigmap(head_cell->getPort(ID::Y)); + SigSpec head_output = sigmap(head_cell->getPort(TW::Y)); int connect_width = std::min(head_output.size(), tree_output.size()); module->connect(head_output.extract(0, connect_width), tree_output.extract(0, connect_width)); if (head_output.size() > tree_output.size()) { diff --git a/passes/opt/opt_clean/cells_all.cc b/passes/opt/opt_clean/cells_all.cc index aa97851e3..d9d3f8b61 100644 --- a/passes/opt/opt_clean/cells_all.cc +++ b/passes/opt/opt_clean/cells_all.cc @@ -202,7 +202,7 @@ ConflictLogs explore(CellAnalysis& analysis, CellTraversal& traversal, const Sig if (bit.wire == nullptr && clean_ctx.ct_all.cell_known(cell->type)) { std::string msg = stringf("Driver-driver conflict " "for %s between cell %s.%s and constant %s in %s: Resolved using constant.", - log_signal(raw_bit), cell->name.unescape(), it2.first.unescape(), log_signal(bit), actx.mod->name.unescape()); + log_signal(raw_bit), cell->name.unescape(), actx.mod->design->twines.str(it2.first), log_signal(bit), actx.mod->name); logs.logs.insert(ctx, {wire_map(raw_bit), msg}); } if (bit.wire != nullptr) @@ -304,7 +304,7 @@ pool all_unused_cells(const Module *mod, const CellAnalysis& analysis, Wi }); for (int cell_index : sharded_unused_cells) unused_cells.insert(mod->cell_at(cell_index)); - unused_cells.sort(RTLIL::sort_by_name_id()); + unused_cells.sort(RTLIL::sort_by_name()); return unused_cells; } @@ -314,7 +314,7 @@ void remove_cells(RTLIL::Module* mod, FfInitVals& ffinit, const pool& cel log_debug(" removing unused `%s' cell `%s'.\n", cell->type, cell->name); mod->design->scratchpad_set_bool("opt.did_something", true); if (cell->is_builtin_ff()) - ffinit.remove_init(cell->getPort(ID::Q)); + ffinit.remove_init(cell->getPort(TW::Q)); mod->remove(cell); stats.count_rm_cells++; } diff --git a/passes/opt/opt_clean/cells_temp.cc b/passes/opt/opt_clean/cells_temp.cc index 693cfa096..56611de61 100644 --- a/passes/opt/opt_clean/cells_temp.cc +++ b/passes/opt/opt_clean/cells_temp.cc @@ -27,8 +27,8 @@ bool is_signed(RTLIL::Cell* cell) { } bool trim_buf(RTLIL::Cell* cell, ShardedVector& new_connections, const ParallelDispatchThreadPool::RunCtx &ctx) { - RTLIL::SigSpec a = cell->getPort(ID::A); - RTLIL::SigSpec y = cell->getPort(ID::Y); + RTLIL::SigSpec a = cell->getPort(TW::A); + RTLIL::SigSpec y = cell->getPort(TW::Y); a.extend_u0(GetSize(y), is_signed(cell)); if (a.has_const(State::Sz)) { @@ -58,20 +58,20 @@ bool remove(ShardedVector& cells, RTLIL::Module* mod, bool verbose if (verbose) { if (cell->type == ID($connect)) { log_debug(" removing connect cell `%s': %s <-> %s\n", cell->name, - log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B))); + log_signal(cell->getPort(TW::A)), log_signal(cell->getPort(TW::B))); } else if (cell->type == ID($input_port)) { log_debug(" removing input port marker cell `%s': %s\n", cell->name, - log_signal(cell->getPort(ID::Y))); + log_signal(cell->getPort(TW::Y))); } else if (cell->type == ID($output_port)) { log_debug(" removing output port marker cell `%s': %s\n", cell->name, - log_signal(cell->getPort(ID::A))); + log_signal(cell->getPort(TW::A))); } else if (cell->type == ID($public)) { log_debug(" removing public wire marker cell `%s': %s\n", cell->name, - log_signal(cell->getPort(ID::A))); + log_signal(cell->getPort(TW::A))); } else { did_something = true; log_debug(" removing buffer cell `%s': %s = %s\n", cell->name, - log_signal(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::A))); + log_signal(cell->getPort(TW::Y)), log_signal(cell->getPort(TW::A))); } } mod->remove(cell); @@ -93,8 +93,8 @@ void remove_temporary_cells(RTLIL::Module *module, ParallelDispatchThreadPool::S if (trim_buf(cell, new_connections, ctx)) delcells.insert(ctx, cell); } else if (cell->type.in(ID($connect)) && !cell->has_keep_attr()) { - RTLIL::SigSpec a = cell->getPort(ID::A); - RTLIL::SigSpec b = cell->getPort(ID::B); + RTLIL::SigSpec a = cell->getPort(TW::A); + RTLIL::SigSpec b = cell->getPort(TW::B); if (a.has_const() && !b.has_const()) std::swap(a, b); new_connections.insert(ctx, {a, b}); diff --git a/passes/opt/opt_clean/inits.cc b/passes/opt/opt_clean/inits.cc index 0618e739a..4e94f1957 100644 --- a/passes/opt/opt_clean/inits.cc +++ b/passes/opt/opt_clean/inits.cc @@ -27,9 +27,9 @@ ShardedVector> build_inits(AnalysisContext& actx) { actx.subpool.run([&results, &actx](const ParallelDispatchThreadPool::RunCtx &ctx) { for (int i : ctx.item_range(actx.mod->cells_size())) { RTLIL::Cell *cell = actx.mod->cell_at(i); - if (StaticCellTypes::Compat::internals_mem_ff(cell->type) && cell->hasPort(ID::Q)) + if (StaticCellTypes::Compat::internals_mem_ff(cell->type) && cell->hasPort(TW::Q)) { - SigSpec sig = cell->getPort(ID::Q); + SigSpec sig = cell->getPort(TW::Q); for (int i = 0; i < GetSize(sig); i++) { diff --git a/passes/opt/opt_clean/wires.cc b/passes/opt/opt_clean/wires.cc index e24691034..944552f81 100644 --- a/passes/opt/opt_clean/wires.cc +++ b/passes/opt/opt_clean/wires.cc @@ -178,7 +178,7 @@ bool check_all(const ShardedSigPool &sigs, const RTLIL::SigSpec &spec) { struct UpdateConnection { RTLIL::Cell *cell; - RTLIL::IdString port; + TwineRef port; RTLIL::SigSpec spec; }; void fixup_cell_ports(ShardedVector &update_connections) @@ -256,7 +256,7 @@ struct SigConnKinds { // see commit message e36c71b5 bool clk2fflogic = cell->get_bool_attribute(ID::clk2fflogic); for (auto &[port, sig] : cell->connections()) - if (clk2fflogic ? port == ID::D : clean_ctx.ct_all.cell_output(cell->type, port)) + if (clk2fflogic ? port == TW::D : clean_ctx.ct_all.cell_output(cell->type, port)) add_spec(raw_register_builder, ctx, sig); } for (auto &[_, sig] : cell->connections()) diff --git a/passes/opt/opt_demorgan.cc b/passes/opt/opt_demorgan.cc index b9aab1850..b1d938134 100644 --- a/passes/opt/opt_demorgan.cc +++ b/passes/opt/opt_demorgan.cc @@ -38,7 +38,7 @@ void demorgan_worker( if( (cell->type != ID($reduce_and)) && (cell->type != ID($reduce_or)) ) return; - auto insig = sigmap(cell->getPort(ID::A)); + auto insig = sigmap(cell->getPort(TW::A)); if (GetSize(insig) < 1) return; @@ -99,7 +99,7 @@ void demorgan_worker( //We are NOT inverted! Add an inverter if(!srcinv) { - auto inverted_b = m->addWire(NEW_ID); + auto inverted_b = m->addWire(NEW_TWINE); m->addNot(NEW_ID, RTLIL::SigSpec(b), RTLIL::SigSpec(inverted_b)); insig[i] = inverted_b; } @@ -107,7 +107,7 @@ void demorgan_worker( //We ARE inverted - bypass it //Don't automatically delete the inverter since other stuff might still use it else - insig[i] = srcinv->getPort(ID::A); + insig[i] = srcinv->getPort(TW::A); } //Cosmetic fixup: If our input is just a scrambled version of one bus, rearrange it @@ -155,7 +155,7 @@ void demorgan_worker( } //Push the new input signal back to the reduction (after bypassing/adding inverters) - cell->setPort(ID::A, insig); + cell->setPort(TW::A, insig); //Change the cell type if(cell->type == ID($reduce_and)) @@ -165,10 +165,10 @@ void demorgan_worker( //don't change XOR //Add an inverter to the output - auto inverted_output = cell->getPort(ID::Y); - auto uninverted_output = m->addWire(NEW_ID); + auto inverted_output = cell->getPort(TW::Y); + auto uninverted_output = m->addWire(NEW_TWINE); m->addNot(NEW_ID, RTLIL::SigSpec(uninverted_output), inverted_output); - cell->setPort(ID::Y, uninverted_output); + cell->setPort(TW::Y, uninverted_output); } struct OptDemorganPass : public Pass { diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index b2b7e3445..9ae4a4ac3 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -77,29 +77,29 @@ struct OptDffWorker SigSpec create_not(SigSpec a, bool is_fine) { if (is_fine) - return module->NotGate(NEW_ID, a); + return module->NotGate(NEW_TWINE, a); else - return module->Not(NEW_ID, a); + return module->Not(NEW_TWINE, a); } SigSpec create_and(SigSpec a, SigSpec b, bool is_fine) { if (is_fine) - return module->AndGate(NEW_ID, a, b); + return module->AndGate(NEW_TWINE, a, b); else - return module->And(NEW_ID, a, b); + return module->And(NEW_TWINE, a, b); } void create_mux_to_output(SigSpec a, SigSpec b, SigSpec sel, SigSpec y, bool pol, bool is_fine) { if (is_fine) { if (pol) - module->addMuxGate(NEW_ID, a, b, sel, y); + module->addMuxGate(NEW_TWINE, a, b, sel, y); else - module->addMuxGate(NEW_ID, b, a, sel, y); + module->addMuxGate(NEW_TWINE, b, a, sel, y); } else { if (pol) - module->addMux(NEW_ID, a, b, sel, y); + module->addMux(NEW_TWINE, a, b, sel, y); else - module->addMux(NEW_ID, b, a, sel, y); + module->addMux(NEW_TWINE, b, a, sel, y); } } @@ -124,7 +124,7 @@ struct OptDffWorker for (auto cell : module->cells()) { if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_))) { - RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y)); + RTLIL::SigSpec sig_y = sigmap(cell->getPort(TW::Y)); for (int i = 0; i < GetSize(sig_y); i++) bit2mux[sig_y[i]] = cell_int_t(cell, i); } @@ -163,9 +163,9 @@ struct OptDffWorker return ret; // D not driven by MUX / MUX drives multiple loads cell_int_t mbit = bit2mux.at(d); - RTLIL::SigSpec sig_a = sigmap(mbit.first->getPort(ID::A)); - RTLIL::SigSpec sig_b = sigmap(mbit.first->getPort(ID::B)); - RTLIL::SigSpec sig_s = sigmap(mbit.first->getPort(ID::S)); + RTLIL::SigSpec sig_a = sigmap(mbit.first->getPort(TW::A)); + RTLIL::SigSpec sig_b = sigmap(mbit.first->getPort(TW::B)); + RTLIL::SigSpec sig_s = sigmap(mbit.first->getPort(TW::S)); int width = GetSize(sig_a), index = mbit.second; // Traverse MUX tree @@ -173,9 +173,9 @@ struct OptDffWorker if (path.count(sig_s[i]) && path.at(sig_s[i])) { ret = find_muxtree_feedback_patterns(sig_b[i*width + index], q, path); if (sig_b[i*width + index] == q) { - RTLIL::SigSpec s = sigmap(mbit.first->getPort(ID::B)); + RTLIL::SigSpec s = sigmap(mbit.first->getPort(TW::B)); s[i*width + index] = RTLIL::Sx; - mbit.first->setPort(ID::B, s); + mbit.first->setPort(TW::B, s); } return ret; @@ -197,9 +197,9 @@ struct OptDffWorker ret.insert(pat); if (sig_b[i*width + index] == q) { - RTLIL::SigSpec s = sigmap(mbit.first->getPort(ID::B)); + RTLIL::SigSpec s = sigmap(mbit.first->getPort(TW::B)); s[i*width + index] = RTLIL::Sx; - mbit.first->setPort(ID::B, s); + mbit.first->setPort(TW::B, s); } } @@ -208,9 +208,9 @@ struct OptDffWorker ret.insert(pat); if (sig_a[index] == q) { - RTLIL::SigSpec s = sigmap(mbit.first->getPort(ID::A)); + RTLIL::SigSpec s = sigmap(mbit.first->getPort(TW::A)); s[index] = RTLIL::Sx; - mbit.first->setPort(ID::A, s); + mbit.first->setPort(TW::A, s); } return ret; @@ -232,8 +232,8 @@ struct OptDffWorker s2.append(it.second); } - RTLIL::SigSpec y = module->addWire(NEW_ID); - RTLIL::Cell *c = module->addNe(NEW_ID, s1, s2, y); + RTLIL::SigSpec y = module->addWire(NEW_TWINE); + RTLIL::Cell *c = module->addNe(NEW_TWINE, s1, s2, y); maybe_simplemap(c, make_gates); or_input.append(y); } @@ -249,8 +249,8 @@ struct OptDffWorker if (GetSize(or_input) == 0) return ctrl_t(State::S1, true); if (GetSize(or_input) == 1) return ctrl_t(or_input, true); - RTLIL::SigSpec y = module->addWire(NEW_ID); - RTLIL::Cell *c = module->addReduceAnd(NEW_ID, or_input, y); + RTLIL::SigSpec y = module->addWire(NEW_TWINE); + RTLIL::Cell *c = module->addReduceAnd(NEW_TWINE, or_input, y); maybe_simplemap(c, make_gates); return ctrl_t(y, true); } @@ -273,10 +273,10 @@ struct OptDffWorker or_input.append(create_not(item.first, make_gates)); } - RTLIL::SigSpec y = module->addWire(NEW_ID); + RTLIL::SigSpec y = module->addWire(NEW_TWINE); RTLIL::Cell *c = final_pol - ? module->addReduceOr(NEW_ID, or_input, y) - : module->addReduceAnd(NEW_ID, or_input, y); + ? module->addReduceOr(NEW_TWINE, or_input, y) + : module->addReduceAnd(NEW_TWINE, or_input, y); maybe_simplemap(c, make_gates); return ctrl_t(y, final_pol); } @@ -309,9 +309,9 @@ struct OptDffWorker if (!ff.pol_clr) module->connect(ff.sig_q[i], ff.sig_clr[i]); else if (ff.is_fine) - module->addNotGate(NEW_ID, ff.sig_clr[i], ff.sig_q[i]); + module->addNotGate(NEW_TWINE, ff.sig_clr[i], ff.sig_q[i]); else - module->addNot(NEW_ID, ff.sig_clr[i], ff.sig_q[i]); + module->addNot(NEW_TWINE, ff.sig_clr[i], ff.sig_q[i]); log("Handling always-active SET at position %d on %s (%s) from module %s (changing to combinatorial circuit).\n", i, cell, cell->type.unescape(), module); sr_removed = true; @@ -406,22 +406,22 @@ struct OptDffWorker SigSpec tmp; if (ff.is_fine) { tmp = ff.pol_set - ? module->MuxGate(NEW_ID, ff.sig_ad, State::S1, ff.sig_set) - : module->MuxGate(NEW_ID, State::S1, ff.sig_ad, ff.sig_set); + ? module->MuxGate(NEW_TWINE, ff.sig_ad, State::S1, ff.sig_set) + : module->MuxGate(NEW_TWINE, State::S1, ff.sig_ad, ff.sig_set); if (ff.pol_clr) - module->addMuxGate(NEW_ID, tmp, State::S0, ff.sig_clr, ff.sig_q); + module->addMuxGate(NEW_TWINE, tmp, State::S0, ff.sig_clr, ff.sig_q); else - module->addMuxGate(NEW_ID, State::S0, tmp, ff.sig_clr, ff.sig_q); + module->addMuxGate(NEW_TWINE, State::S0, tmp, ff.sig_clr, ff.sig_q); } else { tmp = ff.pol_set - ? module->Or(NEW_ID, ff.sig_ad, ff.sig_set) - : module->Or(NEW_ID, ff.sig_ad, module->Not(NEW_ID, ff.sig_set)); + ? module->Or(NEW_TWINE, ff.sig_ad, ff.sig_set) + : module->Or(NEW_TWINE, ff.sig_ad, module->Not(NEW_TWINE, ff.sig_set)); if (ff.pol_clr) - module->addAnd(NEW_ID, tmp, module->Not(NEW_ID, ff.sig_clr), ff.sig_q); + module->addAnd(NEW_TWINE, tmp, module->Not(NEW_TWINE, ff.sig_clr), ff.sig_q); else - module->addAnd(NEW_ID, tmp, ff.sig_clr, ff.sig_q); + module->addAnd(NEW_TWINE, tmp, ff.sig_clr, ff.sig_q); } } else if (ff.has_arst) { create_mux_to_output(ff.sig_ad, ff.val_arst, ff.sig_arst, ff.sig_q, ff.pol_arst, ff.is_fine); @@ -566,12 +566,12 @@ struct OptDffWorker while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) { cell_int_t mbit = bit2mux.at(ff.sig_d[i]); - if (GetSize(mbit.first->getPort(ID::S)) != 1) + if (GetSize(mbit.first->getPort(TW::S)) != 1) break; - SigBit s = sigmap(mbit.first->getPort(ID::S)); - SigBit a = sigmap(mbit.first->getPort(ID::A)[mbit.second]); - SigBit b = sigmap(mbit.first->getPort(ID::B)[mbit.second]); + SigBit s = sigmap(mbit.first->getPort(TW::S)); + SigBit a = sigmap(mbit.first->getPort(TW::A)[mbit.second]); + SigBit b = sigmap(mbit.first->getPort(TW::B)[mbit.second]); if ((a == State::S0 || a == State::S1) && (b == State::S0 || b == State::S1)) break; @@ -649,12 +649,12 @@ struct OptDffWorker while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) { cell_int_t mbit = bit2mux.at(ff.sig_d[i]); - if (GetSize(mbit.first->getPort(ID::S)) != 1) + if (GetSize(mbit.first->getPort(TW::S)) != 1) break; - SigBit s = sigmap(mbit.first->getPort(ID::S)); - SigBit a = sigmap(mbit.first->getPort(ID::A)[mbit.second]); - SigBit b = sigmap(mbit.first->getPort(ID::B)[mbit.second]); + SigBit s = sigmap(mbit.first->getPort(TW::S)); + SigBit a = sigmap(mbit.first->getPort(TW::A)[mbit.second]); + SigBit b = sigmap(mbit.first->getPort(TW::B)[mbit.second]); if (a == ff.sig_q[i]) { enables.insert(ctrl_t(s, true)); diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index f96be6654..2a28e04a4 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -243,7 +243,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ continue; int group_size = GetSize(per_kind[kind]); - RTLIL::SigSpec new_y = patcher.addWire(NEW_ID, group_size); + RTLIL::SigSpec new_y = patcher.addWire(NEW_TWINE, group_size); RTLIL::SigSpec new_a, new_b; int slot = 0; @@ -295,9 +295,9 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ else if (new_a[j] == State::S0 || new_a[j] == State::S1) { undef_a.append(new_a[j]); if (cell->type == ID($xor)) - undef_b.append(new_a[j] == State::S1 ? patcher.Not(NEW_ID, new_b[j]).as_bit() : new_b[j]); + undef_b.append(new_a[j] == State::S1 ? patcher.Not(NEW_TWINE, new_b[j]).as_bit() : new_b[j]); else if (cell->type == ID($xnor)) - undef_b.append(new_a[j] == State::S1 ? new_b[j] : patcher.Not(NEW_ID, new_b[j]).as_bit()); + undef_b.append(new_a[j] == State::S1 ? new_b[j] : patcher.Not(NEW_TWINE, new_b[j]).as_bit()); else log_abort(); undef_y.append(new_y[j]); } @@ -324,7 +324,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ new_y = std::move(def_y); } - RTLIL::Cell *c = patcher.addCell(NEW_ID, cell->type); + RTLIL::Cell *c = patcher.addCell(NEW_TWINE, cell->type); c->setPort(TW::A, new_a); c->parameters[ID::A_WIDTH] = new_a.size(); @@ -687,7 +687,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons sig_y.append(RTLIL::Const(State::S0, width-1)); patcher.patch(cell, TW::Y, sig_y, "xor_buffer"); } else { - SigSpec sig_y = is_gate ? (SigSpec)patcher.NotGate(NEW_ID, sig_a) : patcher.Not(NEW_ID, sig_a); + SigSpec sig_y = is_gate ? (SigSpec)patcher.NotGate(NEW_TWINE, sig_a) : patcher.Not(NEW_TWINE, sig_a); sig_y.append(RTLIL::Const(State::S0, width-1)); patcher.patch(cell, TW::Y, sig_y, "xor_buffer"); } @@ -699,7 +699,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons sig_y.append(RTLIL::Const(State::S1, width-1)); patcher.patch(cell, TW::Y, sig_y, "xnor_buffer"); } else { - SigSpec sig_y = is_gate ? (SigSpec)patcher.NotGate(NEW_ID, sig_a) : patcher.Not(NEW_ID, sig_a); + SigSpec sig_y = is_gate ? (SigSpec)patcher.NotGate(NEW_TWINE, sig_a) : patcher.Not(NEW_TWINE, sig_a); sig_y.append(RTLIL::Const(State::S1, width-1)); patcher.patch(cell, TW::Y, sig_y, "xnor_buffer"); } @@ -771,7 +771,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (!b_group_1.empty()) y_new_1 = b_group_1; if (!b_group_x.empty()) { if (keepdc) - y_new_x = patcher.And(NEW_ID, Const(State::Sx, GetSize(b_group_x)), b_group_x); + y_new_x = patcher.And(NEW_TWINE, Const(State::Sx, GetSize(b_group_x)), b_group_x); else y_new_x = Const(State::S0, GetSize(b_group_x)); } @@ -780,16 +780,16 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (!b_group_1.empty()) y_new_1 = Const(State::S1, GetSize(b_group_1)); if (!b_group_x.empty()) { if (keepdc) - y_new_x = patcher.Or(NEW_ID, Const(State::Sx, GetSize(b_group_x)), b_group_x); + y_new_x = patcher.Or(NEW_TWINE, Const(State::Sx, GetSize(b_group_x)), b_group_x); else y_new_x = Const(State::S1, GetSize(b_group_x)); } } else if (cell->type.in(ID($xor), ID($xnor))) { if (!b_group_0.empty()) y_new_0 = b_group_0; - if (!b_group_1.empty()) y_new_1 = patcher.Not(NEW_ID, b_group_1); + if (!b_group_1.empty()) y_new_1 = patcher.Not(NEW_TWINE, b_group_1); if (!b_group_x.empty()) { if (keepdc) - y_new_x = patcher.Xor(NEW_ID, Const(State::Sx, GetSize(b_group_x)), b_group_x); + y_new_x = patcher.Xor(NEW_TWINE, Const(State::Sx, GetSize(b_group_x)), b_group_x); else // This should be fine even with keepdc, but opt_expr_xor.ys wants to keep the xor y_new_x = Const(State::Sx, GetSize(b_group_x)); } @@ -849,11 +849,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons RTLIL::SigSpec y_new_0, y_new_1; if (flip) { - if (!b_group_0.empty()) y_new_0 = patcher.And(NEW_ID, b_group_0, patcher.Not(NEW_ID, s_group_0)); - if (!b_group_1.empty()) y_new_1 = patcher.Or(NEW_ID, b_group_1, s_group_1); + if (!b_group_0.empty()) y_new_0 = patcher.And(NEW_TWINE, b_group_0, patcher.Not(NEW_TWINE, s_group_0)); + if (!b_group_1.empty()) y_new_1 = patcher.Or(NEW_TWINE, b_group_1, s_group_1); } else { - if (!b_group_0.empty()) y_new_0 = patcher.And(NEW_ID, b_group_0, s_group_0); - if (!b_group_1.empty()) y_new_1 = patcher.Or(NEW_ID, b_group_1, patcher.Not(NEW_ID, s_group_1)); + if (!b_group_0.empty()) y_new_0 = patcher.And(NEW_TWINE, b_group_0, s_group_0); + if (!b_group_1.empty()) y_new_1 = patcher.Or(NEW_TWINE, b_group_1, patcher.Not(NEW_TWINE, s_group_1)); } RTLIL::SigSpec new_sig_y(width); @@ -1059,12 +1059,12 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons RTLIL::SigBit a = sig_a[i]; if (b == ((bi ^ ci) ? State::S1 : State::S0)) { module->connect(sig_y[i], a); - module->connect(sig_x[i], ci ? module->Not(NEW_ID, a).as_bit() : a); + module->connect(sig_x[i], ci ? module->Not(NEW_TWINE, a).as_bit() : a); module->connect(sig_co[i], ci ? State::S1 : State::S0); } else if (a == (ci ? State::S1 : State::S0)) { - module->connect(sig_y[i], bi ? module->Not(NEW_ID, b).as_bit() : b); - module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEW_ID, b).as_bit() : b); + module->connect(sig_y[i], bi ? module->Not(NEW_TWINE, b).as_bit() : b); + module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEW_TWINE, b).as_bit() : b); module->connect(sig_co[i], ci ? State::S1 : State::S0); } else @@ -1486,7 +1486,7 @@ skip_fine_alu: /* sub, b is 0 */ RTLIL::SigSpec a = cell->getPort(TW::A); a.extend_u0(y_width, is_signed); - new_x = patcher.Not(NEW_ID, a); + new_x = patcher.Not(NEW_TWINE, a); new_co = RTLIL::Const(State::S1, y_width); a_port = cell->getPort(TW::A); a_port_signed = a_signed; @@ -1503,8 +1503,8 @@ skip_fine_alu: } IdString new_type = arith_inverse ? ID($neg) : ID($pos); - SigSpec new_y = patcher.addWire(NEW_ID, y_width); - Cell *new_cell = patcher.addCell(NEW_ID, new_type); + SigSpec new_y = patcher.addWire(NEW_TWINE, y_width); + Cell *new_cell = patcher.addCell(NEW_TWINE, new_type); new_cell->setPort(TW::A, a_port); new_cell->setPort(TW::Y, new_y); new_cell->setParam(ID::A_WIDTH, a_port_width); @@ -1805,8 +1805,8 @@ skip_identity: OptExprPatcher patcher(module, &assign_map); int a_width = cell->parameters[ID::A_WIDTH].as_int(); - SigSpec y_wire = patcher.addWire(NEW_ID, y_size); - Cell *mul = patcher.addCell(NEW_ID, ID($mul)); + SigSpec y_wire = patcher.addWire(NEW_TWINE, y_size); + Cell *mul = patcher.addCell(NEW_TWINE, ID($mul)); mul->setPort(TW::A, Const(bit_idx, a_width)); mul->setPort(TW::B, cell->getPort(TW::B)); mul->setPort(TW::Y, y_wire); @@ -1816,8 +1816,8 @@ skip_identity: mul->parameters[ID::B_SIGNED] = cell->parameters[ID::B_SIGNED]; mul->parameters[ID::Y_WIDTH] = y_size; - SigSpec new_y = patcher.addWire(NEW_ID, y_size); - patcher.addShl(NEW_ID, Const(State::S1, 1), y_wire, new_y); + SigSpec new_y = patcher.addWire(NEW_TWINE, y_size); + patcher.addShl(NEW_TWINE, Const(State::S1, 1), y_wire, new_y); patcher.patch(cell, TW::Y, new_y, "pow_to_mul_shl"); goto next_cell; @@ -1954,13 +1954,13 @@ skip_identity: // Truncating division is the same as flooring division, except when // the result is negative and there is a remainder - then trunc = floor + 1 if (is_truncating && a_signed && GetSize(sig_a) != 0 && exp != 0) { - Wire *flooring = module->addWire(NEW_ID, sig_y.size()); + Wire *flooring = module->addWire(NEW_TWINE, sig_y.size()); cell->setPort(TW::Y, flooring); SigSpec a_sign = sig_a[sig_a.size()-1]; - SigSpec rem_nonzero = module->ReduceOr(NEW_ID, sig_a.extract(0, exp)); - SigSpec should_add = module->And(NEW_ID, a_sign, rem_nonzero); - module->addAdd(NEW_ID, flooring, should_add, sig_y); + SigSpec rem_nonzero = module->ReduceOr(NEW_TWINE, sig_a.extract(0, exp)); + SigSpec should_add = module->And(NEW_TWINE, a_sign, rem_nonzero); + module->addAdd(NEW_TWINE, flooring, should_add, sig_y); } cell->check(); @@ -1980,8 +1980,8 @@ skip_identity: SigSpec truncating = sig_a.extract(0, exp); SigSpec a_sign = sig_a[sig_a.size()-1]; - SigSpec rem_nonzero = patcher.ReduceOr(NEW_ID, sig_a.extract(0, exp)); - SigSpec extend_bit = patcher.And(NEW_ID, a_sign, rem_nonzero); + SigSpec rem_nonzero = patcher.ReduceOr(NEW_TWINE, sig_a.extract(0, exp)); + SigSpec extend_bit = patcher.And(NEW_TWINE, a_sign, rem_nonzero); truncating.append(extend_bit); SigSpec new_y = truncating; @@ -2071,11 +2071,11 @@ skip_identity: int sz = cur - prev; bool last = cur == GetSize(sig_y); - SigSpec slice_y = patcher.addWire(NEW_ID, sz); - SigSpec slice_x = patcher.addWire(NEW_ID, sz); - SigSpec slice_co = patcher.addWire(NEW_ID, sz); + SigSpec slice_y = patcher.addWire(NEW_TWINE, sz); + SigSpec slice_x = patcher.addWire(NEW_TWINE, sz); + SigSpec slice_co = patcher.addWire(NEW_TWINE, sz); - RTLIL::Cell *c = patcher.addCell(NEW_ID, cell->type); + RTLIL::Cell *c = patcher.addCell(NEW_TWINE, cell->type); c->setPort(TW::A, sig_a.extract(prev, sz)); c->setPort(TW::B, sig_b.extract(prev, sz)); c->setPort(TW::BI, sig_bi); @@ -2248,14 +2248,14 @@ skip_alu_split: { condition = stringf("unsigned X<%s", log_signal(const_sig)); replacement = stringf("!X[%d:%d]", var_width - 1, const_bit_hot); - replace_sig[0] = patcher.LogicNot(NEW_ID, var_high_sig).as_bit(); + replace_sig[0] = patcher.LogicNot(NEW_TWINE, var_high_sig).as_bit(); replace = true; } if (cmp_type == ID($ge)) { condition = stringf("unsigned X>=%s", log_signal(const_sig)); replacement = stringf("|X[%d:%d]", var_width - 1, const_bit_hot); - replace_sig[0] = patcher.ReduceOr(NEW_ID, var_high_sig).as_bit(); + replace_sig[0] = patcher.ReduceOr(NEW_TWINE, var_high_sig).as_bit(); replace = true; } } @@ -2297,7 +2297,7 @@ skip_alu_split: { condition = "signed X>=0"; replacement = stringf("X[%d]", var_width - 1); - replace_sig[0] = patcher.LogicNot(NEW_ID, var_sig[var_width - 1]).as_bit(); + replace_sig[0] = patcher.LogicNot(NEW_TWINE, var_sig[var_width - 1]).as_bit(); replace = true; } } diff --git a/passes/opt/opt_ffinv.cc b/passes/opt/opt_ffinv.cc index 42d6da49b..216ebce4d 100644 --- a/passes/opt/opt_ffinv.cc +++ b/passes/opt/opt_ffinv.cc @@ -84,12 +84,12 @@ struct OptFfInvWorker } ff.flip_rst_bits({0}); - ff.sig_d = d_inv->getPort(ID::A); + ff.sig_d = d_inv->getPort(TW::A); for (Cell *lut: q_luts) { if (lut->type == ID($lut)) { int flip_mask = 0; - SigSpec sig_a = lut->getPort(ID::A); + SigSpec sig_a = lut->getPort(TW::A); for (int i = 0; i < GetSize(sig_a); i++) { if (index.sigmap(sig_a[i]) == index.sigmap(ff.sig_q[0])) { flip_mask |= 1 << i; @@ -101,14 +101,14 @@ struct OptFfInvWorker new_mask_builder.push_back(mask[j ^ flip_mask]); Const new_mask = new_mask_builder.build(); if (GetSize(sig_a) == 1 && new_mask.as_int() == 2) { - module->connect(lut->getPort(ID::Y), ff.sig_q); + module->connect(lut->getPort(TW::Y), ff.sig_q); module->remove(lut); } else { lut->setParam(ID::LUT, new_mask); } } else { // it was an inverter - module->connect(lut->getPort(ID::Y), ff.sig_q); + module->connect(lut->getPort(TW::Y), ff.sig_q); module->remove(lut); } } @@ -173,7 +173,7 @@ struct OptFfInvWorker if (!q_inv) return false; ff.flip_rst_bits({0}); - ff.sig_q = q_inv->getPort(ID::Y); + ff.sig_q = q_inv->getPort(TW::Y); module->remove(q_inv); if (d_lut->type == ID($lut)) { @@ -188,12 +188,12 @@ struct OptFfInvWorker Const new_mask = new_mask_builder.build(); d_lut->setParam(ID::LUT, new_mask); if (d_lut->getParam(ID::WIDTH) == 1 && new_mask.as_int() == 2) { - module->connect(ff.sig_d, d_lut->getPort(ID::A)); + module->connect(ff.sig_d, d_lut->getPort(TW::A)); module->remove(d_lut); } } else { // it was an inverter - module->connect(ff.sig_d, d_lut->getPort(ID::A)); + module->connect(ff.sig_d, d_lut->getPort(TW::A)); module->remove(d_lut); } diff --git a/passes/opt/opt_hier.cc b/passes/opt/opt_hier.cc index 563161685..b53673695 100644 --- a/passes/opt/opt_hier.cc +++ b/passes/opt/opt_hier.cc @@ -137,7 +137,7 @@ struct ModuleIndex { rhs.replace(constant_outputs); log_assert(rhs.is_fully_const()); parent.module->connect(value.extract(chunk.offset, chunk.width), rhs); - SigSpec dummy = parent.module->addWire(NEW_ID_SUFFIX("const_output"), chunk.width); + SigSpec dummy = parent.module->addWire(NEW_TWINE_SUFFIX("const_output"), chunk.width); for (int i = 0; i < chunk.width; i++) value[chunk.offset + i] = dummy[i]; } @@ -182,7 +182,7 @@ struct ModuleIndex { severed_port_bits.sort_and_unify(); for (auto chunk : severed_port_bits.chunks()) { SigSpec &value = instantiation->connections_.at(chunk.wire->name); - SigSpec dummy = parent.module->addWire(NEW_ID_SUFFIX("tie_together"), chunk.width); + SigSpec dummy = parent.module->addWire(NEW_TWINE_SUFFIX("tie_together"), chunk.width); for (int i = 0; i < chunk.width; i++) value[chunk.offset + i] = dummy[i]; } diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc index 72c465ead..27180a1d2 100644 --- a/passes/opt/opt_lut.cc +++ b/passes/opt/opt_lut.cc @@ -50,7 +50,7 @@ struct OptLutWorker bool evaluate_lut(RTLIL::Cell *lut, dict inputs) { - SigSpec lut_input = sigmap(lut->getPort(ID::A)); + SigSpec lut_input = sigmap(lut->getPort(TW::A)); int lut_width = lut->getParam(ID::WIDTH).as_int(); Const lut_table = lut->getParam(ID::LUT); int lut_index = 0; @@ -113,12 +113,12 @@ struct OptLutWorker { if (cell->has_keep_attr()) continue; - SigBit lut_output = cell->getPort(ID::Y); + SigBit lut_output = cell->getPort(TW::Y); if (lut_output.wire->get_bool_attribute(ID::keep)) continue; int lut_width = cell->getParam(ID::WIDTH).as_int(); - SigSpec lut_input = cell->getPort(ID::A); + SigSpec lut_input = cell->getPort(TW::A); int lut_arity = 0; log_debug("Found $lut\\WIDTH=%d cell %s.%s.\n", lut_width, module, cell); @@ -218,7 +218,7 @@ struct OptLutWorker } auto lut = worklist.pop(); - SigSpec lut_input = sigmap(lut->getPort(ID::A)); + SigSpec lut_input = sigmap(lut->getPort(TW::A)); pool &lut_dlogic_inputs = luts_dlogic_inputs[lut]; vector lut_inputs; @@ -280,7 +280,7 @@ struct OptLutWorker log_debug(" Not eliminating cell (connected to dedicated logic).\n"); else { - SigSpec lut_output = lut->getPort(ID::Y); + SigSpec lut_output = lut->getPort(TW::Y); for (auto &port : index.query_ports(lut_output)) { if (port.cell != lut && luts.count(port.cell)) @@ -317,13 +317,13 @@ struct OptLutWorker } auto lutA = worklist.pop(); - SigSpec lutA_input = sigmap(lutA->getPort(ID::A)); - SigBit lutA_output = sigmap(lutA->getPort(ID::Y)[0]); + SigSpec lutA_input = sigmap(lutA->getPort(TW::A)); + SigBit lutA_output = sigmap(lutA->getPort(TW::Y)[0]); int lutA_width = lutA->getParam(ID::WIDTH).as_int(); int lutA_arity = luts_arity[lutA]; pool &lutA_dlogic_inputs = luts_dlogic_inputs[lutA]; - auto lutA_output_ports = index.query_ports(lutA->getPort(ID::Y)); + auto lutA_output_ports = index.query_ports(lutA->getPort(TW::Y)); if (lutA_output_ports.size() != 2) continue; @@ -335,15 +335,15 @@ struct OptLutWorker if (luts.count(port.cell)) { auto lutB = port.cell; - SigSpec lutB_input = sigmap(lutB->getPort(ID::A)); - SigSpec lutB_output = sigmap(lutB->getPort(ID::Y)[0]); + SigSpec lutB_input = sigmap(lutB->getPort(TW::A)); + SigSpec lutB_output = sigmap(lutB->getPort(TW::Y)[0]); int lutB_width = lutB->getParam(ID::WIDTH).as_int(); int lutB_arity = luts_arity[lutB]; pool &lutB_dlogic_inputs = luts_dlogic_inputs[lutB]; log_debug("Found %s.%s (cell A) feeding %s.%s (cell B).\n", module, lutA, module, lutB); - if (index.query_is_output(lutA->getPort(ID::Y))) + if (index.query_is_output(lutA->getPort(TW::Y))) { log_debug(" Not combining LUTs (cascade connection feeds module output).\n"); continue; @@ -453,7 +453,7 @@ struct OptLutWorker } int lutM_width = lutM->getParam(ID::WIDTH).as_int(); - SigSpec lutM_input = sigmap(lutM->getPort(ID::A)); + SigSpec lutM_input = sigmap(lutM->getPort(TW::A)); std::vector lutM_new_inputs; for (int i = 0; i < lutM_width; i++) { @@ -499,8 +499,8 @@ struct OptLutWorker log_debug(" Merged truth table: %s.\n", lutM_new_table.as_string()); lutM->setParam(ID::LUT, lutM_new_table); - lutM->setPort(ID::A, lutM_new_inputs); - lutM->setPort(ID::Y, lutB_output); + lutM->setPort(TW::A, lutM_new_inputs); + lutM->setPort(TW::Y, lutB_output); luts_arity[lutM] = lutM_arity; luts.erase(lutR); diff --git a/passes/opt/opt_lut_ins.cc b/passes/opt/opt_lut_ins.cc index c1355da25..7881b5d75 100644 --- a/passes/opt/opt_lut_ins.cc +++ b/passes/opt/opt_lut_ins.cc @@ -79,8 +79,8 @@ struct OptLutInsPass : public Pass { if (techname == "") { if (cell->type != ID($lut)) continue; - inputs = cell->getPort(ID::A); - output = cell->getPort(ID::Y); + inputs = cell->getPort(TW::A); + output = cell->getPort(TW::Y); lut = cell->getParam(ID::LUT); } else if (techname == "xilinx" || techname == "gowin" || techname == "analogdevices") { if (cell->type == ID(LUT1)) { @@ -128,16 +128,16 @@ struct OptLutInsPass : public Pass { } lut = cell->getParam(ID::INIT); if (techname == "xilinx" || techname == "analogdevices") - output = cell->getPort(ID::O); + output = cell->getPort(TW::O); else - output = cell->getPort(ID::F); + output = cell->getPort(TW::F); } else if (techname == "lattice") { if (cell->type == ID(LUT4)) { inputs = { - cell->getPort(ID::A), - cell->getPort(ID::B), - cell->getPort(ID::C), - cell->getPort(ID::D), + cell->getPort(TW::A), + cell->getPort(TW::B), + cell->getPort(TW::C), + cell->getPort(TW::D), }; lut = cell->getParam(ID::INIT); output = cell->getPort(ID(Z)); @@ -226,14 +226,14 @@ struct OptLutInsPass : public Pass { if (techname == "") { cell->setParam(ID::LUT, new_lut); cell->setParam(ID::WIDTH, GetSize(new_inputs)); - cell->setPort(ID::A, new_inputs); + cell->setPort(TW::A, new_inputs); } else if (techname == "lattice" || techname == "ecp5") { log_assert(GetSize(new_inputs) == 4); cell->setParam(ID::INIT, new_lut); - cell->setPort(ID::A, new_inputs[0]); - cell->setPort(ID::B, new_inputs[1]); - cell->setPort(ID::C, new_inputs[2]); - cell->setPort(ID::D, new_inputs[3]); + cell->setPort(TW::A, new_inputs[0]); + cell->setPort(TW::B, new_inputs[1]); + cell->setPort(TW::C, new_inputs[2]); + cell->setPort(TW::D, new_inputs[3]); } else { // xilinx, gowin cell->setParam(ID::INIT, new_lut); diff --git a/passes/opt/opt_mem_feedback.cc b/passes/opt/opt_mem_feedback.cc index fe5157934..f7648be0b 100644 --- a/passes/opt/opt_mem_feedback.cc +++ b/passes/opt/opt_mem_feedback.cc @@ -75,10 +75,10 @@ struct OptMemFeedbackWorker RTLIL::Cell *cell = sig_to_mux.at(sig).first; int bit_idx = sig_to_mux.at(sig).second; - std::vector sig_a = sigmap(cell->getPort(ID::A)); - std::vector sig_b = sigmap(cell->getPort(ID::B)); - std::vector sig_s = sigmap(cell->getPort(ID::S)); - std::vector sig_y = sigmap(cell->getPort(ID::Y)); + std::vector sig_a = sigmap(cell->getPort(TW::A)); + std::vector sig_b = sigmap(cell->getPort(TW::B)); + std::vector sig_s = sigmap(cell->getPort(TW::S)); + std::vector sig_y = sigmap(cell->getPort(TW::Y)); log_assert(sig_y.at(bit_idx) == sig); for (int i = 0; i < GetSize(sig_s); i++) @@ -295,18 +295,18 @@ struct OptMemFeedbackWorker { if (cell->type == ID($mux)) { - RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A)); - RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(ID::B)); + RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(TW::A)); + RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(TW::B)); if (sig_a.is_fully_undef()) - sigmap_xmux.add(cell->getPort(ID::Y), sig_b); + sigmap_xmux.add(cell->getPort(TW::Y), sig_b); else if (sig_b.is_fully_undef()) - sigmap_xmux.add(cell->getPort(ID::Y), sig_a); + sigmap_xmux.add(cell->getPort(TW::Y), sig_a); } if (cell->type.in(ID($mux), ID($pmux))) { - std::vector sig_y = sigmap(cell->getPort(ID::Y)); + std::vector sig_y = sigmap(cell->getPort(TW::Y)); for (int i = 0; i < int(sig_y.size()); i++) sig_to_mux[sig_y[i]] = std::pair(cell, i); } diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index 00360aa46..de8278bc5 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -298,7 +298,7 @@ struct OptMergeWorker for (auto [remove_cell, keep_cell] : cell_ptrs) { log_debug(" Cell `%s' is identical to cell `%s'.\n", remove_cell->name, keep_cell->name); - std::vector> port_replacements; + std::vector> port_replacements; for (auto &it : remove_cell->connections()) { if (remove_cell->output(it.first)) { RTLIL::SigSpec keep_sig = keep_cell->getPort(it.first); diff --git a/passes/opt/opt_merge_common.h b/passes/opt/opt_merge_common.h index 41dfb6b3c..3e6975994 100644 --- a/passes/opt/opt_merge_common.h +++ b/passes/opt/opt_merge_common.h @@ -64,10 +64,10 @@ struct CellHasher return comm.hash_into(h); } - static void sort_pmux_conn(dict &conn) + static void sort_pmux_conn(dict &conn) { - const SigSpec &sig_s = conn.at(ID::S); - const SigSpec &sig_b = conn.at(ID::B); + const SigSpec &sig_s = conn.at(TW::S); + const SigSpec &sig_b = conn.at(TW::B); int s_width = GetSize(sig_s); int width = GetSize(sig_b) / s_width; @@ -78,12 +78,12 @@ struct CellHasher std::sort(sb_pairs.begin(), sb_pairs.end()); - conn[ID::S] = SigSpec(); - conn[ID::B] = SigSpec(); + conn[TW::S] = SigSpec(); + conn[TW::B] = SigSpec(); for (auto &it : sb_pairs) { - conn[ID::S].append(it.first); - conn[ID::B].append(it.second); + conn[TW::S].append(it.first); + conn[TW::B].append(it.second); } } @@ -94,22 +94,22 @@ struct CellHasher if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul), ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) { hashlib::commutative_hash comm; - comm.eat(map_sig(cell->getPort(ID::A))); - comm.eat(map_sig(cell->getPort(ID::B))); + comm.eat(map_sig(cell->getPort(TW::A))); + comm.eat(map_sig(cell->getPort(TW::B))); h = comm.hash_into(h); } else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) { - SigSpec a = map_sig(cell->getPort(ID::A)); + SigSpec a = map_sig(cell->getPort(TW::A)); a.sort(); h = a.hash_into(h); } else if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) { - SigSpec a = map_sig(cell->getPort(ID::A)); + SigSpec a = map_sig(cell->getPort(TW::A)); a.sort_and_unify(); h = a.hash_into(h); } else if (cell->type == ID($pmux)) { - SigSpec sig_s = map_sig(cell->getPort(ID::S)); - SigSpec sig_b = map_sig(cell->getPort(ID::B)); + SigSpec sig_s = map_sig(cell->getPort(TW::S)); + SigSpec sig_b = map_sig(cell->getPort(TW::B)); h = hash_pmux_in(sig_s, sig_b, h); - h = map_sig(cell->getPort(ID::A)).hash_into(h); + h = map_sig(cell->getPort(TW::A)).hash_into(h); } else { hashlib::commutative_hash comm; for (const auto& [port, sig] : cell->connections()) { @@ -119,7 +119,7 @@ struct CellHasher } h = comm.hash_into(h); if (cell->is_builtin_ff()) - h = initvals(cell->getPort(ID::Q)).hash_into(h); + h = initvals(cell->getPort(TW::Q)).hash_into(h); } return h; } @@ -160,7 +160,7 @@ struct CellHasher for (const auto &it : cell1->connections_) { if (cell1->output(it.first)) { - if (it.first == ID::Q && cell1->is_builtin_ff()) { + if (it.first == TW::Q && cell1->is_builtin_ff()) { // For the 'Q' output of state elements, // use the (* init *) attribute value conn1[it.first] = initvals(it.second); @@ -179,20 +179,20 @@ struct CellHasher if (cell1->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul), ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) { - if (conn1.at(ID::A) < conn1.at(ID::B)) { - std::swap(conn1[ID::A], conn1[ID::B]); + if (conn1.at(TW::A) < conn1.at(TW::B)) { + std::swap(conn1[TW::A], conn1[TW::B]); } - if (conn2.at(ID::A) < conn2.at(ID::B)) { - std::swap(conn2[ID::A], conn2[ID::B]); + if (conn2.at(TW::A) < conn2.at(TW::B)) { + std::swap(conn2[TW::A], conn2[TW::B]); } } else if (cell1->type.in(ID($reduce_xor), ID($reduce_xnor))) { - conn1[ID::A].sort(); - conn2[ID::A].sort(); + conn1[TW::A].sort(); + conn2[TW::A].sort(); } else if (cell1->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) { - conn1[ID::A].sort_and_unify(); - conn2[ID::A].sort_and_unify(); + conn1[TW::A].sort_and_unify(); + conn2[TW::A].sort_and_unify(); } else if (cell1->type == ID($pmux)) { sort_pmux_conn(conn1); @@ -207,7 +207,7 @@ struct CellHasher if (!cell->is_builtin_ff()) return false; - return !initvals(cell->getPort(ID::Q)).is_fully_def(); + return !initvals(cell->getPort(TW::Q)).is_fully_def(); } }; diff --git a/passes/opt/opt_merge_inc.cc b/passes/opt/opt_merge_inc.cc index ffdce708c..fa4d16ae7 100644 --- a/passes/opt/opt_merge_inc.cc +++ b/passes/opt/opt_merge_inc.cc @@ -268,7 +268,7 @@ struct OptMergeIncWorker did_something = true; log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name, other_cell->name); - std::vector> port_replacements; + std::vector> port_replacements; for (auto &[port, sig] : cell->connections()) { if (cell->output(port)) { // TODO why was this removed before? diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index c62252896..85d1fbf7f 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -113,10 +113,10 @@ struct OptMuxtreeWorker // .input_sigs // .const_activated // .const_deactivated - RTLIL::SigSpec sig_a = cell->getPort(ID::A); - RTLIL::SigSpec sig_b = cell->getPort(ID::B); - RTLIL::SigSpec sig_s = cell->getPort(ID::S); - RTLIL::SigSpec sig_y = cell->getPort(ID::Y); + RTLIL::SigSpec sig_a = cell->getPort(TW::A); + RTLIL::SigSpec sig_b = cell->getPort(TW::B); + RTLIL::SigSpec sig_s = cell->getPort(TW::S); + RTLIL::SigSpec sig_y = cell->getPort(TW::Y); muxinfo_t muxinfo; muxinfo.cell = cell; @@ -300,10 +300,10 @@ struct OptMuxtreeWorker continue; } - RTLIL::SigSpec sig_a = mi.cell->getPort(ID::A); - RTLIL::SigSpec sig_b = mi.cell->getPort(ID::B); - RTLIL::SigSpec sig_s = mi.cell->getPort(ID::S); - RTLIL::SigSpec sig_y = mi.cell->getPort(ID::Y); + RTLIL::SigSpec sig_a = mi.cell->getPort(TW::A); + RTLIL::SigSpec sig_b = mi.cell->getPort(TW::B); + RTLIL::SigSpec sig_s = mi.cell->getPort(TW::S); + RTLIL::SigSpec sig_y = mi.cell->getPort(TW::Y); RTLIL::SigSpec sig_ports = sig_b; sig_ports.append(sig_a); @@ -328,9 +328,9 @@ struct OptMuxtreeWorker } } - mi.cell->setPort(ID::A, new_sig_a); - mi.cell->setPort(ID::B, new_sig_b); - mi.cell->setPort(ID::S, new_sig_s); + mi.cell->setPort(TW::A, new_sig_a); + mi.cell->setPort(TW::B, new_sig_b); + mi.cell->setPort(TW::S, new_sig_s); if (GetSize(new_sig_s) == 1) { mi.cell->type = ID($mux); mi.cell->parameters.erase(ID::S_WIDTH); @@ -465,7 +465,7 @@ struct OptMuxtreeWorker deactivate_port(knowledge, port_idx, muxinfo); } - void replace_known(knowledge_t &knowledge, muxinfo_t &muxinfo, IdString portname) + void replace_known(knowledge_t &knowledge, muxinfo_t &muxinfo, TwineRef portname) { SigSpec sig = muxinfo.cell->getPort(portname); bool did_something = false; @@ -473,8 +473,8 @@ struct OptMuxtreeWorker int width_if_b = 0; idict ctrl_bits; if (portname == ID::B) - width_if_b = GetSize(muxinfo.cell->getPort(ID::A)); - for (int bit : sig2bits(muxinfo.cell->getPort(ID::S), false)) + width_if_b = GetSize(muxinfo.cell->getPort(TW::A)); + for (int bit : sig2bits(muxinfo.cell->getPort(TW::S), false)) ctrl_bits(bit); int slice_idx = 0, slice_off = 0; diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index b4592038b..4c073c0a5 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -43,7 +43,7 @@ struct OptReduceWorker return; cells.erase(cell); - RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); + RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A)); sig_a.sort_and_unify(); pool new_sig_a_bits; @@ -74,8 +74,8 @@ struct OptReduceWorker for (auto child_cell : drivers.find(bit)) { if (child_cell->type == cell->type) { opt_reduce(cells, drivers, child_cell); - if (child_cell->getPort(ID::Y)[0] == bit) { - pool child_sig_a_bits = assign_map(child_cell->getPort(ID::A)).to_sigbit_pool(); + if (child_cell->getPort(TW::Y)[0] == bit) { + pool child_sig_a_bits = assign_map(child_cell->getPort(TW::A)).to_sigbit_pool(); new_sig_a_bits.insert(child_sig_a_bits.begin(), child_sig_a_bits.end()); } else new_sig_a_bits.insert(RTLIL::State::S0); @@ -92,22 +92,22 @@ struct OptReduceWorker if (GetSize(new_sig_a) == 0) new_sig_a = (cell->type == ID($reduce_or)) ? State::S0 : State::S1; - if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) { + if (new_sig_a != sig_a || sig_a.size() != cell->getPort(TW::A).size()) { log(" New input vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_a)); did_something = true; total_count++; } - cell->setPort(ID::A, new_sig_a); + cell->setPort(TW::A, new_sig_a); cell->parameters[ID::A_WIDTH] = RTLIL::Const(new_sig_a.size()); return; } void opt_pmux(RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); - RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B)); - RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S)); + RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A)); + RTLIL::SigSpec sig_b = assign_map(cell->getPort(TW::B)); + RTLIL::SigSpec sig_s = assign_map(cell->getPort(TW::S)); RTLIL::SigSpec new_sig_b, new_sig_s; dict> grouped_b_to_s; @@ -126,15 +126,15 @@ struct OptReduceWorker RTLIL::SigSpec this_s{this_s_bit}; if (this_s.size() > 1) { - RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, ID($reduce_or)); - reduce_or_cell->setPort(ID::A, this_s); + RTLIL::Cell *reduce_or_cell = module->addCell(NEW_TWINE, ID($reduce_or)); + reduce_or_cell->setPort(TW::A, this_s); reduce_or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0); reduce_or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(this_s.size()); reduce_or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1); - RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID); + RTLIL::Wire *reduce_or_wire = module->addWire(NEW_TWINE); this_s = RTLIL::SigSpec(reduce_or_wire); - reduce_or_cell->setPort(ID::Y, this_s); + reduce_or_cell->setPort(TW::Y, this_s); } new_sig_b.append(this_b); @@ -143,8 +143,8 @@ struct OptReduceWorker if (new_sig_s.size() == 0) { - module->connect(cell->getPort(ID::Y), cell->getPort(ID::A)); - assign_map.add(cell->getPort(ID::Y), cell->getPort(ID::A)); + module->connect(cell->getPort(TW::Y), cell->getPort(TW::A)); + assign_map.add(cell->getPort(TW::Y), cell->getPort(TW::A)); module->remove(cell); did_something = true; total_count++; @@ -155,8 +155,8 @@ struct OptReduceWorker log(" New ctrl vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_s)); did_something = true; total_count++; - cell->setPort(ID::B, new_sig_b); - cell->setPort(ID::S, new_sig_s); + cell->setPort(TW::B, new_sig_b); + cell->setPort(TW::S, new_sig_s); if (new_sig_s.size() > 1) { cell->parameters[ID::S_WIDTH] = RTLIL::Const(new_sig_s.size()); } else { @@ -168,8 +168,8 @@ struct OptReduceWorker void opt_bmux(RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); - RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S)); + RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A)); + RTLIL::SigSpec sig_s = assign_map(cell->getPort(TW::S)); int width = cell->getParam(ID::WIDTH).as_int(); RTLIL::SigSpec new_sig_a, new_sig_s; @@ -218,8 +218,8 @@ struct OptReduceWorker if (new_sig_s.size() == 0) { - module->connect(cell->getPort(ID::Y), new_sig_a); - assign_map.add(cell->getPort(ID::Y), new_sig_a); + module->connect(cell->getPort(TW::Y), new_sig_a); + assign_map.add(cell->getPort(TW::Y), new_sig_a); module->remove(cell); did_something = true; total_count++; @@ -229,9 +229,9 @@ struct OptReduceWorker if (new_sig_s.size() == 1) { cell->type = ID($mux); - cell->setPort(ID::A, new_sig_a.extract(0, width)); - cell->setPort(ID::B, new_sig_a.extract(width, width)); - cell->setPort(ID::S, new_sig_s); + cell->setPort(TW::A, new_sig_a.extract(0, width)); + cell->setPort(TW::B, new_sig_a.extract(width, width)); + cell->setPort(TW::S, new_sig_s); cell->parameters.erase(ID::S_WIDTH); did_something = true; total_count++; @@ -242,16 +242,16 @@ struct OptReduceWorker log(" New ctrl vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_s)); did_something = true; total_count++; - cell->setPort(ID::A, new_sig_a); - cell->setPort(ID::S, new_sig_s); + cell->setPort(TW::A, new_sig_a); + cell->setPort(TW::S, new_sig_s); cell->parameters[ID::S_WIDTH] = RTLIL::Const(new_sig_s.size()); } } void opt_demux(RTLIL::Cell *cell) { - RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y)); - RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S)); + RTLIL::SigSpec sig_y = assign_map(cell->getPort(TW::Y)); + RTLIL::SigSpec sig_s = assign_map(cell->getPort(TW::S)); int width = cell->getParam(ID::WIDTH).as_int(); RTLIL::SigSpec new_sig_y, new_sig_s; @@ -319,27 +319,27 @@ struct OptReduceWorker if (new_sig_s.size() == 0) { - module->connect(new_sig_y, cell->getPort(ID::A)); - assign_map.add(new_sig_y, cell->getPort(ID::A)); + module->connect(new_sig_y, cell->getPort(TW::A)); + assign_map.add(new_sig_y, cell->getPort(TW::A)); module->remove(cell); } else { - cell->setPort(ID::S, new_sig_s); - cell->setPort(ID::Y, new_sig_y); + cell->setPort(TW::S, new_sig_s); + cell->setPort(TW::Y, new_sig_y); cell->parameters[ID::S_WIDTH] = RTLIL::Const(new_sig_s.size()); } } bool opt_mux_bits(RTLIL::Cell *cell) { - SigSpec sig_a = assign_map(cell->getPort(ID::A)); + SigSpec sig_a = assign_map(cell->getPort(TW::A)); SigSpec sig_b; - SigSpec sig_y = assign_map(cell->getPort(ID::Y)); + SigSpec sig_y = assign_map(cell->getPort(TW::Y)); int width = GetSize(sig_y); if (cell->type != ID($bmux)) - sig_b = assign_map(cell->getPort(ID::B)); + sig_b = assign_map(cell->getPort(TW::B)); RTLIL::SigSig old_sig_conn; @@ -387,11 +387,11 @@ struct OptReduceWorker { log(" Consolidated identical input bits for %s cell %s:\n", cell->type, cell->name); if (cell->type != ID($bmux)) { - log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), - log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y))); + log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(TW::A)), + log_signal(cell->getPort(TW::B)), log_signal(cell->getPort(TW::Y))); } else { - log(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), - log_signal(cell->getPort(ID::Y))); + log(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(TW::A)), + log_signal(cell->getPort(TW::Y))); } if (swizzle.empty()) { @@ -401,29 +401,29 @@ struct OptReduceWorker for (int i = 0; i < GetSize(sig_a); i += width) for (int j: swizzle) new_sig_a.append(sig_a[i+j]); - cell->setPort(ID::A, new_sig_a); + cell->setPort(TW::A, new_sig_a); if (cell->type != ID($bmux)) { SigSpec new_sig_b; for (int i = 0; i < GetSize(sig_b); i += width) for (int j: swizzle) new_sig_b.append(sig_b[i+j]); - cell->setPort(ID::B, new_sig_b); + cell->setPort(TW::B, new_sig_b); } SigSpec new_sig_y; for (int j: swizzle) new_sig_y.append(sig_y[j]); - cell->setPort(ID::Y, new_sig_y); + cell->setPort(TW::Y, new_sig_y); cell->parameters[ID::WIDTH] = RTLIL::Const(GetSize(swizzle)); if (cell->type != ID($bmux)) { - log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), - log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y))); + log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(TW::A)), + log_signal(cell->getPort(TW::B)), log_signal(cell->getPort(TW::Y))); } else { - log(" New ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), - log_signal(cell->getPort(ID::Y))); + log(" New ports: A=%s, Y=%s\n", log_signal(cell->getPort(TW::A)), + log_signal(cell->getPort(TW::Y))); } } @@ -437,8 +437,8 @@ struct OptReduceWorker } bool opt_demux_bits(RTLIL::Cell *cell) { - SigSpec sig_a = assign_map(cell->getPort(ID::A)); - SigSpec sig_y = assign_map(cell->getPort(ID::Y)); + SigSpec sig_a = assign_map(cell->getPort(TW::A)); + SigSpec sig_y = assign_map(cell->getPort(TW::Y)); int width = GetSize(sig_a); RTLIL::SigSig old_sig_conn; @@ -477,8 +477,8 @@ struct OptReduceWorker if (GetSize(swizzle) != width) { log(" Consolidated identical input bits for %s cell %s:\n", cell->type, cell->name); - log(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), - log_signal(cell->getPort(ID::Y))); + log(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(TW::A)), + log_signal(cell->getPort(TW::Y))); if (swizzle.empty()) { module->remove(cell); @@ -486,18 +486,18 @@ struct OptReduceWorker SigSpec new_sig_a; for (int j: swizzle) new_sig_a.append(sig_a[j]); - cell->setPort(ID::A, new_sig_a); + cell->setPort(TW::A, new_sig_a); SigSpec new_sig_y; for (int i = 0; i < GetSize(sig_y); i += width) for (int j: swizzle) new_sig_y.append(sig_y[i+j]); - cell->setPort(ID::Y, new_sig_y); + cell->setPort(TW::Y, new_sig_y); cell->parameters[ID::WIDTH] = RTLIL::Const(GetSize(swizzle)); - log(" New ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), - log_signal(cell->getPort(ID::Y))); + log(" New ports: A=%s, Y=%s\n", log_signal(cell->getPort(TW::A)), + log_signal(cell->getPort(TW::Y))); } log(" New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second)); @@ -521,14 +521,14 @@ struct OptReduceWorker for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; if (cell->type.in(ID($mem), ID($mem_v2))) - mem_wren_sigs.add(assign_map(cell->getPort(ID::WR_EN))); + mem_wren_sigs.add(assign_map(cell->getPort(TW::WR_EN))); if (cell->type.in(ID($memwr), ID($memwr_v2))) - mem_wren_sigs.add(assign_map(cell->getPort(ID::EN))); + mem_wren_sigs.add(assign_map(cell->getPort(TW::EN))); } for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; - if (cell->type == ID($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(ID::Q)))) - mem_wren_sigs.add(assign_map(cell->getPort(ID::D))); + if (cell->type == ID($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(TW::Q)))) + mem_wren_sigs.add(assign_map(cell->getPort(TW::D))); } bool keep_expanding_mem_wren_sigs = true; @@ -536,12 +536,12 @@ struct OptReduceWorker keep_expanding_mem_wren_sigs = false; for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; - if (cell->type == ID($mux) && mem_wren_sigs.check_any(assign_map(cell->getPort(ID::Y)))) { - if (!mem_wren_sigs.check_all(assign_map(cell->getPort(ID::A))) || - !mem_wren_sigs.check_all(assign_map(cell->getPort(ID::B)))) + if (cell->type == ID($mux) && mem_wren_sigs.check_any(assign_map(cell->getPort(TW::Y)))) { + if (!mem_wren_sigs.check_all(assign_map(cell->getPort(TW::A))) || + !mem_wren_sigs.check_all(assign_map(cell->getPort(TW::B)))) keep_expanding_mem_wren_sigs = true; - mem_wren_sigs.add(assign_map(cell->getPort(ID::A))); - mem_wren_sigs.add(assign_map(cell->getPort(ID::B))); + mem_wren_sigs.add(assign_map(cell->getPort(TW::A))); + mem_wren_sigs.add(assign_map(cell->getPort(TW::B))); } } } @@ -563,7 +563,7 @@ struct OptReduceWorker RTLIL::Cell *cell = cell_it.second; if (cell->type != type || !design->selected(module, cell)) continue; - drivers.insert(assign_map(cell->getPort(ID::Y)), cell); + drivers.insert(assign_map(cell->getPort(TW::Y)), cell); cells.insert(cell); } @@ -582,7 +582,7 @@ struct OptReduceWorker // this optimization is to aggressive for most coarse-grain applications. // but we always want it for multiplexers driving write enable ports. - if (do_fine || mem_wren_sigs.check_any(assign_map(cell->getPort(ID::Y)))) { + if (do_fine || mem_wren_sigs.check_any(assign_map(cell->getPort(TW::Y)))) { if (cell->type == ID($demux)) { if (opt_demux_bits(cell)) continue; diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index 11740e134..c485c807c 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -96,8 +96,8 @@ struct ExtSigSpec { bool cell_supported(RTLIL::Cell *cell) { if (cell->type.in(ID($alu))) { - RTLIL::SigSpec sig_bi = cell->getPort(ID::BI); - RTLIL::SigSpec sig_ci = cell->getPort(ID::CI); + RTLIL::SigSpec sig_bi = cell->getPort(TW::BI); + RTLIL::SigSpec sig_ci = cell->getPort(TW::CI); if (sig_bi.is_fully_const() && sig_ci.is_fully_const() && sig_bi == sig_ci) return true; @@ -126,7 +126,7 @@ bool mergeable(RTLIL::Cell *a, RTLIL::Cell *b) return a_type == b_type; } -RTLIL::IdString decode_port_semantics(RTLIL::Cell *cell, RTLIL::IdString port_name) +RTLIL::IdString decode_port_semantics(RTLIL::Cell *cell, TwineRef port_name) { if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($concat), SHIFT_OPS) && port_name == ID::B) return port_name; @@ -137,17 +137,17 @@ RTLIL::IdString decode_port_semantics(RTLIL::Cell *cell, RTLIL::IdString port_na return ""; } -RTLIL::SigSpec decode_port_sign(RTLIL::Cell *cell, RTLIL::IdString port_name) { +RTLIL::SigSpec decode_port_sign(RTLIL::Cell *cell, TwineRef port_name) { if (cell->type == ID($alu) && port_name == ID::B) - return cell->getPort(ID::BI); + return cell->getPort(TW::BI); else if (cell->type == ID($sub) && port_name == ID::B) return RTLIL::Const(1, 1); return RTLIL::Const(0, 1); } -bool decode_port_signed(RTLIL::Cell *cell, RTLIL::IdString port_name) +bool decode_port_signed(RTLIL::Cell *cell, TwineRef port_name) { if (cell->type.in(BITWISE_OPS, LOGICAL_OPS)) return false; @@ -158,7 +158,7 @@ bool decode_port_signed(RTLIL::Cell *cell, RTLIL::IdString port_name) return false; } -ExtSigSpec decode_port(RTLIL::Cell *cell, RTLIL::IdString port_name, const SigMap &sigmap) +ExtSigSpec decode_port(RTLIL::Cell *cell, TwineRef port_name, const SigMap &sigmap) { auto sig = sigmap(cell->getPort(port_name)); @@ -206,9 +206,9 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< module->remove(op); } - RTLIL::SigSpec mux_a = mux->getPort(ID::A); - RTLIL::SigSpec mux_b = mux->getPort(ID::B); - RTLIL::SigSpec mux_s = mux->getPort(ID::S); + RTLIL::SigSpec mux_a = mux->getPort(TW::A); + RTLIL::SigSpec mux_b = mux->getPort(TW::B); + RTLIL::SigSpec mux_s = mux->getPort(TW::S); int conn_width = ports[0].sig.size(); int conn_mux_offset = ports[0].mux_port_offset; @@ -219,7 +219,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< RTLIL::SigSpec shared_pmux_s; // Make a new wire to avoid false equivalence with whatever the former shared output was connected to. - Wire *new_out = module->addWire(NEW_ID, conn_op_offset + conn_width); + Wire *new_out = module->addWire(NEW_TWINE, conn_op_offset + conn_width); SigSpec new_sig_out = SigSpec(new_out, conn_op_offset, conn_width); for (int i = 0; i < GetSize(ports); i++) { @@ -235,9 +235,9 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< } } - mux->setPort(ID::A, mux_a); - mux->setPort(ID::B, mux_b); - mux->setPort(ID::S, mux_s); + mux->setPort(TW::A, mux_a); + mux->setPort(TW::B, mux_b); + mux->setPort(TW::S, mux_s); SigSpec mux_to_oper; if (GetSize(shared_pmux_s) == 1) { @@ -247,22 +247,22 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< } if (shared_op->type.in(ID($alu))) { - shared_op->setPort(ID::X, module->addWire(NEW_ID, GetSize(new_out))); - shared_op->setPort(ID::CO, module->addWire(NEW_ID, GetSize(new_out))); + shared_op->setPort(TW::X, module->addWire(NEW_TWINE, GetSize(new_out))); + shared_op->setPort(TW::CO, module->addWire(NEW_TWINE, GetSize(new_out))); } bool is_fine = shared_op->type.in(FINE_BITWISE_OPS); - shared_op->setPort(ID::Y, new_out); + shared_op->setPort(TW::Y, new_out); if (!is_fine) shared_op->setParam(ID::Y_WIDTH, GetSize(new_out)); if (decode_port(shared_op, ID::A, sigmap) == operand) { - shared_op->setPort(ID::B, mux_to_oper); + shared_op->setPort(TW::B, mux_to_oper); if (!is_fine) shared_op->setParam(ID::B_WIDTH, max_width); } else { - shared_op->setPort(ID::A, mux_to_oper); + shared_op->setPort(TW::A, mux_to_oper); if (!is_fine) shared_op->setParam(ID::A_WIDTH, max_width); } @@ -313,7 +313,7 @@ ExtSigSpec find_shared_operand(const OpMuxConn* seed, std::vectorop; - for (RTLIL::IdString port_name : {ID::A, ID::B}) { + for (TwineRef port_name : {ID::A, ID::B}) { oper = decode_port(op_a, port_name, sigmap); auto operand_users = operand_to_users.at(oper); @@ -386,7 +386,7 @@ struct OptSharePass : public Pass { bool skip = false; if (cell->type == ID($alu)) { - for (RTLIL::IdString port_name : {ID::X, ID::CO}) { + for (TwineRef port_name : {ID::X, ID::CO}) { for (auto outbit : sigmap(cell->getPort(port_name))) if (bit_users[outbit] > 1) skip = true; @@ -396,11 +396,11 @@ struct OptSharePass : public Pass { if (skip) continue; - auto mux_insig = sigmap(cell->getPort(ID::Y)); + auto mux_insig = sigmap(cell->getPort(TW::Y)); for (int i = 0; i < GetSize(mux_insig); i++) op_outbit_to_outsig[mux_insig[i]] = std::make_pair(cell, i); - for (RTLIL::IdString port_name : {ID::A, ID::B}) { + for (TwineRef port_name : {ID::A, ID::B}) { auto op_insig = decode_port(cell, port_name, sigmap); operand_to_users[op_insig].insert(cell); if (operand_to_users[op_insig].size() > 1) @@ -419,19 +419,19 @@ struct OptSharePass : public Pass { if (!mux->type.in(ID($mux), ID($_MUX_), ID($pmux))) continue; - int mux_port_size = GetSize(mux->getPort(ID::A)); - int mux_port_num = GetSize(mux->getPort(ID::S)) + 1; + int mux_port_size = GetSize(mux->getPort(TW::A)); + int mux_port_num = GetSize(mux->getPort(TW::S)) + 1; - RTLIL::SigSpec mux_insig = sigmap(RTLIL::SigSpec{mux->getPort(ID::B), mux->getPort(ID::A)}); + RTLIL::SigSpec mux_insig = sigmap(RTLIL::SigSpec{mux->getPort(TW::B), mux->getPort(TW::A)}); std::vector> mux_port_conns(mux_port_num); int found = 0; for (int mux_port_id = 0; mux_port_id < mux_port_num; mux_port_id++) { SigSpec mux_insig; if (mux_port_id == mux_port_num - 1) { - mux_insig = sigmap(mux->getPort(ID::A)); + mux_insig = sigmap(mux->getPort(TW::A)); } else { - mux_insig = sigmap(mux->getPort(ID::B).extract(mux_port_id * mux_port_size, mux_port_size)); + mux_insig = sigmap(mux->getPort(TW::B).extract(mux_port_id * mux_port_size, mux_port_size)); } for (int mux_port_offset = 0; mux_port_offset < mux_port_size; ++mux_port_offset) { @@ -441,7 +441,7 @@ struct OptSharePass : public Pass { RTLIL::Cell *cell; int op_outsig_offset; std::tie(cell, op_outsig_offset) = op_outbit_to_outsig.at(mux_insig[mux_port_offset]); - SigSpec op_outsig = sigmap(cell->getPort(ID::Y)); + SigSpec op_outsig = sigmap(cell->getPort(TW::Y)); int op_outsig_size = GetSize(op_outsig); int op_conn_width = 0; diff --git a/passes/opt/peepopt_formal_clockgateff.pmg b/passes/opt/peepopt_formal_clockgateff.pmg index 2b6358b8d..8b4ad28ff 100644 --- a/passes/opt/peepopt_formal_clockgateff.pmg +++ b/passes/opt/peepopt_formal_clockgateff.pmg @@ -50,7 +50,7 @@ code // instead of the latch. We don't delete the latch in case its output is // used to drive other nodes. If it isn't, it will be trivially removed by // clean - SigSpec flopped_en = module->addWire(NEW_ID); + SigSpec flopped_en = module->addWire(NEW_TWINE); module->addDff(NEW_ID, clk, en, flopped_en, true, latch->src_ref()); and_gate->setPort(latched_en_port_name, flopped_en); did_something = true; diff --git a/passes/opt/peepopt_shiftmul_left.pmg b/passes/opt/peepopt_shiftmul_left.pmg index 383222195..4778be874 100644 --- a/passes/opt/peepopt_shiftmul_left.pmg +++ b/passes/opt/peepopt_shiftmul_left.pmg @@ -129,7 +129,7 @@ code if (bit == SigBit(State::Sm)) padbits++; - SigSpec padwire = module->addWire(NEW_ID, padbits); + SigSpec padwire = module->addWire(NEW_TWINE, padbits); for (int i = new_y.size() - 1; i >= 0; i--) if (new_y[i] == SigBit(State::Sm)) { @@ -148,7 +148,7 @@ code shift->setPort(\B, new_b); shift->setParam(\B_WIDTH, GetSize(new_b)); } else { - SigSpec b_neg = module->addWire(NEW_ID, GetSize(new_b) + 1); + SigSpec b_neg = module->addWire(NEW_TWINE, GetSize(new_b) + 1); module->addNeg(NEW_ID, new_b, b_neg); shift->setPort(\B, b_neg); shift->setParam(\B_WIDTH, GetSize(b_neg)); diff --git a/passes/opt/pmux2shiftx.cc b/passes/opt/pmux2shiftx.cc index 029a2bf10..97e09851c 100644 --- a/passes/opt/pmux2shiftx.cc +++ b/passes/opt/pmux2shiftx.cc @@ -56,19 +56,19 @@ struct OnehotDatabase if (cell->type.in(ID($adff), ID($adffe), ID($dff), ID($dffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch), ID($ff))) { - output = cell->getPort(ID::Q); + output = cell->getPort(TW::Q); if (cell->type.in(ID($adff), ID($adffe), ID($adlatch))) inputs.push_back(cell->getParam(ID::ARST_VALUE)); if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce))) inputs.push_back(cell->getParam(ID::SRST_VALUE)); - inputs.push_back(cell->getPort(ID::D)); + inputs.push_back(cell->getPort(TW::D)); } if (cell->type.in(ID($mux), ID($pmux))) { - output = cell->getPort(ID::Y); - inputs.push_back(cell->getPort(ID::A)); - SigSpec B = cell->getPort(ID::B); + output = cell->getPort(TW::Y); + inputs.push_back(cell->getPort(TW::A)); + SigSpec B = cell->getPort(TW::B); for (int i = 0; i < GetSize(B); i += GetSize(output)) inputs.push_back(B.extract(i, GetSize(output))); } @@ -289,8 +289,8 @@ struct Pmux2ShiftxPass : public Pass { { dict bits; - SigSpec A = sigmap(cell->getPort(ID::A)); - SigSpec B = sigmap(cell->getPort(ID::B)); + SigSpec A = sigmap(cell->getPort(TW::A)); + SigSpec B = sigmap(cell->getPort(TW::B)); int a_width = cell->getParam(ID::A_WIDTH).as_int(); int b_width = cell->getParam(ID::B_WIDTH).as_int(); @@ -329,7 +329,7 @@ struct Pmux2ShiftxPass : public Pass { } entry.second = entry_bits_builder.build(); - eqdb[sigmap(cell->getPort(ID::Y)[0])] = entry; + eqdb[sigmap(cell->getPort(TW::Y)[0])] = entry; goto next_cell; } @@ -337,7 +337,7 @@ struct Pmux2ShiftxPass : public Pass { { dict bits; - SigSpec A = sigmap(cell->getPort(ID::A)); + SigSpec A = sigmap(cell->getPort(TW::A)); for (int i = 0; i < GetSize(A); i++) bits[A[i]] = State::S0; @@ -351,7 +351,7 @@ struct Pmux2ShiftxPass : public Pass { } entry.second = entry_bits_builder.build(); - eqdb[sigmap(cell->getPort(ID::Y)[0])] = entry; + eqdb[sigmap(cell->getPort(TW::Y)[0])] = entry; goto next_cell; } next_cell:; @@ -372,9 +372,9 @@ struct Pmux2ShiftxPass : public Pass { dict> seldb; - SigSpec A = cell->getPort(ID::A); - SigSpec B = cell->getPort(ID::B); - SigSpec S = sigmap(cell->getPort(ID::S)); + SigSpec A = cell->getPort(TW::A); + SigSpec B = cell->getPort(TW::B); + SigSpec S = sigmap(cell->getPort(TW::S)); for (int i = 0; i < GetSize(S); i++) { if (!eqdb.count(S[i])) @@ -395,8 +395,8 @@ struct Pmux2ShiftxPass : public Pass { log(" data width: %d (next power-of-2 = %d, log2 = %d)\n", width, extwidth, width_bits); } - SigSpec updated_S = cell->getPort(ID::S); - SigSpec updated_B = cell->getPort(ID::B); + SigSpec updated_S = cell->getPort(TW::S); + SigSpec updated_B = cell->getPort(TW::B); while (!seldb.empty()) { @@ -691,7 +691,7 @@ struct Pmux2ShiftxPass : public Pass { Const enable_mask(State::S0, max_choice+1); for (auto &it : perm_choices) enable_mask.set(it.first.as_int(), State::S1); - en = module->addWire(NEW_ID); + en = module->addWire(NEW_TWINE); module->addShift(NEW_ID, enable_mask, cmp, en, false, src); } @@ -711,7 +711,7 @@ struct Pmux2ShiftxPass : public Pass { // create shiftx cell SigSpec shifted_cmp = {cmp, SigSpec(State::S0, width_bits)}; - SigSpec outsig = module->addWire(NEW_ID, width); + SigSpec outsig = module->addWire(NEW_TWINE, width); Cell *c = module->addShiftx(NEW_ID, data, shifted_cmp, outsig, false, src); updated_S.append(en); updated_B.append(outsig); @@ -722,8 +722,8 @@ struct Pmux2ShiftxPass : public Pass { } // update $pmux cell - cell->setPort(ID::S, updated_S); - cell->setPort(ID::B, updated_B); + cell->setPort(TW::S, updated_S); + cell->setPort(TW::B, updated_B); cell->setParam(ID::S_WIDTH, GetSize(updated_S)); } } @@ -780,8 +780,8 @@ struct OnehotPass : public Pass { if (cell->type != ID($eq)) continue; - SigSpec A = sigmap(cell->getPort(ID::A)); - SigSpec B = sigmap(cell->getPort(ID::B)); + SigSpec A = sigmap(cell->getPort(TW::A)); + SigSpec B = sigmap(cell->getPort(TW::B)); int a_width = cell->getParam(ID::A_WIDTH).as_int(); int b_width = cell->getParam(ID::B_WIDTH).as_int(); @@ -828,7 +828,7 @@ struct OnehotPass : public Pass { continue; } - SigSpec Y = cell->getPort(ID::Y); + SigSpec Y = cell->getPort(TW::Y); SigSpec replacement; if (not_onehot) diff --git a/passes/opt/share.cc b/passes/opt/share.cc index 119243d48..69bac1dcb 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -89,7 +89,7 @@ struct ShareWorker for (auto &pbit : portbits) { if ((pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) && visited_cells.count(pbit.cell) == 0) { - pool bits = modwalker.sigmap(pbit.cell->getPort(ID::S)).to_sigbit_pool(); + pool bits = modwalker.sigmap(pbit.cell->getPort(TW::S)).to_sigbit_pool(); terminal_bits.insert(bits.begin(), bits.end()); queue_bits.insert(bits.begin(), bits.end()); visited_cells.insert(pbit.cell); @@ -127,7 +127,7 @@ struct ShareWorker static int bits_macc(RTLIL::Cell *c) { Macc m(c); - int width = GetSize(c->getPort(ID::Y)); + int width = GetSize(c->getPort(TW::Y)); return bits_macc(m, width); } @@ -206,12 +206,12 @@ struct ShareWorker sig_b2.extend_u0(GetSize(sig_b), p2.is_signed); if (supercell_aux && GetSize(sig_a)) { - sig_a = module->addWire(NEW_ID, GetSize(sig_a)); + sig_a = module->addWire(NEW_TWINE, GetSize(sig_a)); supercell_aux->insert(module->addMux(NEW_ID, sig_a2, sig_a1, act, sig_a)); } if (supercell_aux && GetSize(sig_b)) { - sig_b = module->addWire(NEW_ID, GetSize(sig_b)); + sig_b = module->addWire(NEW_TWINE, GetSize(sig_b)); supercell_aux->insert(module->addMux(NEW_ID, sig_b2, sig_b1, act, sig_b)); } @@ -241,7 +241,7 @@ struct ShareWorker { Macc m1(c1), m2(c2), supermacc; - int w1 = GetSize(c1->getPort(ID::Y)), w2 = GetSize(c2->getPort(ID::Y)); + int w1 = GetSize(c1->getPort(TW::Y)), w2 = GetSize(c2->getPort(TW::Y)); int width = max(w1, w2); m1.optimize(w1); @@ -283,12 +283,12 @@ struct ShareWorker RTLIL::SigSpec sig_b = m1.terms[i].in_b; if (supercell_aux && GetSize(sig_a)) { - sig_a = module->addWire(NEW_ID, GetSize(sig_a)); + sig_a = module->addWire(NEW_TWINE, GetSize(sig_a)); supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(sig_a)), m1.terms[i].in_a, act, sig_a)); } if (supercell_aux && GetSize(sig_b)) { - sig_b = module->addWire(NEW_ID, GetSize(sig_b)); + sig_b = module->addWire(NEW_TWINE, GetSize(sig_b)); supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(sig_b)), m1.terms[i].in_b, act, sig_b)); } @@ -306,12 +306,12 @@ struct ShareWorker RTLIL::SigSpec sig_b = m2.terms[i].in_b; if (supercell_aux && GetSize(sig_a)) { - sig_a = module->addWire(NEW_ID, GetSize(sig_a)); + sig_a = module->addWire(NEW_TWINE, GetSize(sig_a)); supercell_aux->insert(module->addMux(NEW_ID, m2.terms[i].in_a, RTLIL::SigSpec(0, GetSize(sig_a)), act, sig_a)); } if (supercell_aux && GetSize(sig_b)) { - sig_b = module->addWire(NEW_ID, GetSize(sig_b)); + sig_b = module->addWire(NEW_TWINE, GetSize(sig_b)); supercell_aux->insert(module->addMux(NEW_ID, m2.terms[i].in_b, RTLIL::SigSpec(0, GetSize(sig_b)), act, sig_b)); } @@ -325,13 +325,13 @@ struct ShareWorker if (supercell) { - RTLIL::SigSpec sig_y = module->addWire(NEW_ID, width); + RTLIL::SigSpec sig_y = module->addWire(NEW_TWINE, width); - supercell_aux->insert(module->addPos(NEW_ID, sig_y, c1->getPort(ID::Y))); - supercell_aux->insert(module->addPos(NEW_ID, sig_y, c2->getPort(ID::Y))); + supercell_aux->insert(module->addPos(NEW_ID, sig_y, c1->getPort(TW::Y))); + supercell_aux->insert(module->addPos(NEW_ID, sig_y, c2->getPort(TW::Y))); supercell->setParam(ID::Y_WIDTH, width); - supercell->setPort(ID::Y, sig_y); + supercell->setPort(TW::Y, sig_y); supermacc.optimize(width); supermacc.to_cell(supercell); @@ -365,7 +365,7 @@ struct ShareWorker if (cell->type.in(ID($memrd), ID($memrd_v2))) { if (cell->parameters.at(ID::CLK_ENABLE).as_bool()) continue; - if (config.opt_aggressive || !modwalker.sigmap(cell->getPort(ID::ADDR)).is_fully_const()) + if (config.opt_aggressive || !modwalker.sigmap(cell->getPort(TW::ADDR)).is_fully_const()) shareable_cells.insert(cell); continue; } @@ -510,11 +510,11 @@ struct ShareWorker if (c1->parameters.at(ID::A_SIGNED).as_bool() != c2->parameters.at(ID::A_SIGNED).as_bool()) { RTLIL::Cell *unsigned_cell = c1->parameters.at(ID::A_SIGNED).as_bool() ? c2 : c1; - if (unsigned_cell->getPort(ID::A).to_sigbit_vector().back() != RTLIL::State::S0) { + if (unsigned_cell->getPort(TW::A).to_sigbit_vector().back() != RTLIL::State::S0) { unsigned_cell->parameters.at(ID::A_WIDTH) = unsigned_cell->parameters.at(ID::A_WIDTH).as_int() + 1; - RTLIL::SigSpec new_a = unsigned_cell->getPort(ID::A); + RTLIL::SigSpec new_a = unsigned_cell->getPort(TW::A); new_a.append(RTLIL::State::S0); - unsigned_cell->setPort(ID::A, new_a); + unsigned_cell->setPort(TW::A, new_a); } unsigned_cell->parameters.at(ID::A_SIGNED) = true; unsigned_cell->check(); @@ -523,11 +523,11 @@ struct ShareWorker bool a_signed = c1->parameters.at(ID::A_SIGNED).as_bool(); log_assert(a_signed == c2->parameters.at(ID::A_SIGNED).as_bool()); - RTLIL::SigSpec a1 = c1->getPort(ID::A); - RTLIL::SigSpec y1 = c1->getPort(ID::Y); + RTLIL::SigSpec a1 = c1->getPort(TW::A); + RTLIL::SigSpec y1 = c1->getPort(TW::Y); - RTLIL::SigSpec a2 = c2->getPort(ID::A); - RTLIL::SigSpec y2 = c2->getPort(ID::Y); + RTLIL::SigSpec a2 = c2->getPort(TW::A); + RTLIL::SigSpec y2 = c2->getPort(TW::Y); int a_width = max(a1.size(), a2.size()); int y_width = max(y1.size(), y2.size()); @@ -535,17 +535,17 @@ struct ShareWorker a1.extend_u0(a_width, a_signed); a2.extend_u0(a_width, a_signed); - RTLIL::SigSpec a = module->addWire(NEW_ID, a_width); + RTLIL::SigSpec a = module->addWire(NEW_TWINE, a_width); supercell_aux.insert(module->addMux(NEW_ID, a2, a1, act, a)); - RTLIL::Wire *y = module->addWire(NEW_ID, y_width); + RTLIL::Wire *y = module->addWire(NEW_TWINE, y_width); - RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type); + RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type); supercell->parameters[ID::A_SIGNED] = a_signed; supercell->parameters[ID::A_WIDTH] = a_width; supercell->parameters[ID::Y_WIDTH] = y_width; - supercell->setPort(ID::A, a); - supercell->setPort(ID::Y, y); + supercell->setPort(TW::A, a); + supercell->setPort(TW::Y, y); supercell_aux.insert(module->addPos(NEW_ID, y, y1)); supercell_aux.insert(module->addPos(NEW_ID, y, y2)); @@ -568,9 +568,9 @@ struct ShareWorker if (score_flipped < score_unflipped) { - RTLIL::SigSpec tmp = c2->getPort(ID::A); - c2->setPort(ID::A, c2->getPort(ID::B)); - c2->setPort(ID::B, tmp); + RTLIL::SigSpec tmp = c2->getPort(TW::A); + c2->setPort(TW::A, c2->getPort(TW::B)); + c2->setPort(TW::B, tmp); std::swap(c2->parameters.at(ID::A_WIDTH), c2->parameters.at(ID::B_WIDTH)); std::swap(c2->parameters.at(ID::A_SIGNED), c2->parameters.at(ID::B_SIGNED)); @@ -582,11 +582,11 @@ struct ShareWorker { RTLIL::Cell *unsigned_cell = c1->parameters.at(ID::A_SIGNED).as_bool() ? c2 : c1; - if (unsigned_cell->getPort(ID::A).to_sigbit_vector().back() != RTLIL::State::S0) { + if (unsigned_cell->getPort(TW::A).to_sigbit_vector().back() != RTLIL::State::S0) { unsigned_cell->parameters.at(ID::A_WIDTH) = unsigned_cell->parameters.at(ID::A_WIDTH).as_int() + 1; - RTLIL::SigSpec new_a = unsigned_cell->getPort(ID::A); + RTLIL::SigSpec new_a = unsigned_cell->getPort(TW::A); new_a.append(RTLIL::State::S0); - unsigned_cell->setPort(ID::A, new_a); + unsigned_cell->setPort(TW::A, new_a); } unsigned_cell->parameters.at(ID::A_SIGNED) = true; modified_src_cells = true; @@ -595,11 +595,11 @@ struct ShareWorker if (c1->parameters.at(ID::B_SIGNED).as_bool() != c2->parameters.at(ID::B_SIGNED).as_bool()) { RTLIL::Cell *unsigned_cell = c1->parameters.at(ID::B_SIGNED).as_bool() ? c2 : c1; - if (unsigned_cell->getPort(ID::B).to_sigbit_vector().back() != RTLIL::State::S0) { + if (unsigned_cell->getPort(TW::B).to_sigbit_vector().back() != RTLIL::State::S0) { unsigned_cell->parameters.at(ID::B_WIDTH) = unsigned_cell->parameters.at(ID::B_WIDTH).as_int() + 1; - RTLIL::SigSpec new_b = unsigned_cell->getPort(ID::B); + RTLIL::SigSpec new_b = unsigned_cell->getPort(TW::B); new_b.append(RTLIL::State::S0); - unsigned_cell->setPort(ID::B, new_b); + unsigned_cell->setPort(TW::B, new_b); } unsigned_cell->parameters.at(ID::B_SIGNED) = true; modified_src_cells = true; @@ -619,13 +619,13 @@ struct ShareWorker if (c1->type == ID($shl) || c1->type == ID($shr) || c1->type == ID($sshl) || c1->type == ID($sshr)) b_signed = false; - RTLIL::SigSpec a1 = c1->getPort(ID::A); - RTLIL::SigSpec b1 = c1->getPort(ID::B); - RTLIL::SigSpec y1 = c1->getPort(ID::Y); + RTLIL::SigSpec a1 = c1->getPort(TW::A); + RTLIL::SigSpec b1 = c1->getPort(TW::B); + RTLIL::SigSpec y1 = c1->getPort(TW::Y); - RTLIL::SigSpec a2 = c2->getPort(ID::A); - RTLIL::SigSpec b2 = c2->getPort(ID::B); - RTLIL::SigSpec y2 = c2->getPort(ID::Y); + RTLIL::SigSpec a2 = c2->getPort(TW::A); + RTLIL::SigSpec b2 = c2->getPort(TW::B); + RTLIL::SigSpec y2 = c2->getPort(TW::Y); int a_width = max(a1.size(), a2.size()); int b_width = max(b1.size(), b2.size()); @@ -650,43 +650,43 @@ struct ShareWorker b1.extend_u0(b_width, b_signed); b2.extend_u0(b_width, b_signed); - RTLIL::SigSpec a = module->addWire(NEW_ID, a_width); - RTLIL::SigSpec b = module->addWire(NEW_ID, b_width); + RTLIL::SigSpec a = module->addWire(NEW_TWINE, a_width); + RTLIL::SigSpec b = module->addWire(NEW_TWINE, b_width); supercell_aux.insert(module->addMux(NEW_ID, a2, a1, act, a)); supercell_aux.insert(module->addMux(NEW_ID, b2, b1, act, b)); - RTLIL::Wire *y = module->addWire(NEW_ID, y_width); - RTLIL::Wire *x = c1->type == ID($alu) ? module->addWire(NEW_ID, y_width) : nullptr; - RTLIL::Wire *co = c1->type == ID($alu) ? module->addWire(NEW_ID, y_width) : nullptr; + RTLIL::Wire *y = module->addWire(NEW_TWINE, y_width); + RTLIL::Wire *x = c1->type == ID($alu) ? module->addWire(NEW_TWINE, y_width) : nullptr; + RTLIL::Wire *co = c1->type == ID($alu) ? module->addWire(NEW_TWINE, y_width) : nullptr; - RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type); + RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type); supercell->parameters[ID::A_SIGNED] = a_signed; supercell->parameters[ID::B_SIGNED] = b_signed; supercell->parameters[ID::A_WIDTH] = a_width; supercell->parameters[ID::B_WIDTH] = b_width; supercell->parameters[ID::Y_WIDTH] = y_width; - supercell->setPort(ID::A, a); - supercell->setPort(ID::B, b); - supercell->setPort(ID::Y, y); + supercell->setPort(TW::A, a); + supercell->setPort(TW::B, b); + supercell->setPort(TW::Y, y); if (c1->type == ID($alu)) { - RTLIL::Wire *ci = module->addWire(NEW_ID), *bi = module->addWire(NEW_ID); - supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID::CI), c1->getPort(ID::CI), act, ci)); - supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID::BI), c1->getPort(ID::BI), act, bi)); - supercell->setPort(ID::CI, ci); - supercell->setPort(ID::BI, bi); - supercell->setPort(ID::CO, co); - supercell->setPort(ID::X, x); + RTLIL::Wire *ci = module->addWire(NEW_TWINE), *bi = module->addWire(NEW_TWINE); + supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(TW::CI), c1->getPort(TW::CI), act, ci)); + supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(TW::BI), c1->getPort(TW::BI), act, bi)); + supercell->setPort(TW::CI, ci); + supercell->setPort(TW::BI, bi); + supercell->setPort(TW::CO, co); + supercell->setPort(TW::X, x); } supercell->check(); supercell_aux.insert(module->addPos(NEW_ID, y, y1)); supercell_aux.insert(module->addPos(NEW_ID, y, y2)); if (c1->type == ID($alu)) { - supercell_aux.insert(module->addPos(NEW_ID, co, c1->getPort(ID::CO))); - supercell_aux.insert(module->addPos(NEW_ID, co, c2->getPort(ID::CO))); - supercell_aux.insert(module->addPos(NEW_ID, x, c1->getPort(ID::X))); - supercell_aux.insert(module->addPos(NEW_ID, x, c2->getPort(ID::X))); + supercell_aux.insert(module->addPos(NEW_ID, co, c1->getPort(TW::CO))); + supercell_aux.insert(module->addPos(NEW_ID, co, c2->getPort(TW::CO))); + supercell_aux.insert(module->addPos(NEW_ID, x, c1->getPort(TW::X))); + supercell_aux.insert(module->addPos(NEW_ID, x, c2->getPort(TW::X))); } supercell_aux.insert(supercell); @@ -695,7 +695,7 @@ struct ShareWorker if (c1->type == ID($macc)) { - RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type); + RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type); supercell_aux.insert(supercell); share_macc(c1, c2, act, supercell, &supercell_aux); supercell->check(); @@ -704,16 +704,16 @@ struct ShareWorker if (c1->type.in(ID($memrd), ID($memrd_v2))) { - RTLIL::Cell *supercell = module->addCell(NEW_ID, c1); - RTLIL::SigSpec addr1 = c1->getPort(ID::ADDR); - RTLIL::SigSpec addr2 = c2->getPort(ID::ADDR); + RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1); + RTLIL::SigSpec addr1 = c1->getPort(TW::ADDR); + RTLIL::SigSpec addr2 = c2->getPort(TW::ADDR); if (GetSize(addr1) < GetSize(addr2)) addr1.extend_u0(GetSize(addr2)); else addr2.extend_u0(GetSize(addr1)); - supercell->setPort(ID::ADDR, addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1); + supercell->setPort(TW::ADDR, addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1); supercell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr1)); - supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort(ID::DATA), c2->getPort(ID::DATA))); + supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort(TW::DATA), c2->getPort(TW::DATA))); supercell_aux.insert(supercell); return supercell; } @@ -745,7 +745,7 @@ struct ShareWorker for (auto &bit : pbits) { if ((bit.cell->type == ID($mux) || bit.cell->type == ID($pmux)) && bit.port == ID::S) - forbidden_controls_cache[cell].insert(bit.cell->getPort(ID::S).extract(bit.offset, 1)); + forbidden_controls_cache[cell].insert(bit.cell->getPort(TW::S).extract(bit.offset, 1)); consumer_cells.insert(bit.cell); } @@ -909,9 +909,9 @@ struct ShareWorker std::set used_in_b_parts; int width = c->parameters.at(ID::WIDTH).as_int(); - std::vector sig_a = modwalker.sigmap(c->getPort(ID::A)); - std::vector sig_b = modwalker.sigmap(c->getPort(ID::B)); - std::vector sig_s = modwalker.sigmap(c->getPort(ID::S)); + std::vector sig_a = modwalker.sigmap(c->getPort(TW::A)); + std::vector sig_b = modwalker.sigmap(c->getPort(TW::B)); + std::vector sig_s = modwalker.sigmap(c->getPort(TW::S)); for (auto &bit : sig_a) if (cell_out_bits.count(bit)) @@ -1059,7 +1059,7 @@ struct ShareWorker RTLIL::SigSpec make_cell_activation_logic(const pool &activation_patterns, pool &supercell_aux) { - RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0); + RTLIL::Wire *all_cases_wire = module->addWire(NEW_TWINE, 0); for (auto &p : activation_patterns) { all_cases_wire->width++; @@ -1069,7 +1069,7 @@ struct ShareWorker if (all_cases_wire->width == 1) return all_cases_wire; - RTLIL::Wire *result_wire = module->addWire(NEW_ID); + RTLIL::Wire *result_wire = module->addWire(NEW_TWINE); supercell_aux.insert(module->addReduceOr(NEW_ID, all_cases_wire, result_wire)); return result_wire; } diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 057a7f765..0a8fab2dc 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -66,10 +66,10 @@ struct WreduceWorker { // Reduce size of MUX if inputs agree on a value for a bit or a output bit is unused - SigSpec sig_a = mi.sigmap(cell->getPort(ID::A)); - SigSpec sig_b = mi.sigmap(cell->getPort(ID::B)); - SigSpec sig_s = mi.sigmap(cell->getPort(ID::S)); - SigSpec sig_y = mi.sigmap(cell->getPort(ID::Y)); + SigSpec sig_a = mi.sigmap(cell->getPort(TW::A)); + SigSpec sig_b = mi.sigmap(cell->getPort(TW::B)); + SigSpec sig_s = mi.sigmap(cell->getPort(TW::S)); + SigSpec sig_y = mi.sigmap(cell->getPort(TW::Y)); std::vector bits_removed; if (sig_y.has_const()) @@ -132,9 +132,9 @@ struct WreduceWorker for (auto bit : new_work_queue_bits) work_queue_bits.insert(bit); - cell->setPort(ID::A, new_sig_a); - cell->setPort(ID::B, new_sig_b); - cell->setPort(ID::Y, new_sig_y); + cell->setPort(TW::A, new_sig_a); + cell->setPort(TW::B, new_sig_b); + cell->setPort(TW::Y, new_sig_y); cell->fixup_parameters(); module->connect(sig_y.extract(n_kept, n_removed), sig_removed); @@ -144,8 +144,8 @@ struct WreduceWorker { // Reduce size of FF if inputs are just sign/zero extended or output bit is not used - SigSpec sig_d = mi.sigmap(cell->getPort(ID::D)); - SigSpec sig_q = mi.sigmap(cell->getPort(ID::Q)); + SigSpec sig_d = mi.sigmap(cell->getPort(TW::D)); + SigSpec sig_q = mi.sigmap(cell->getPort(TW::Q)); bool has_reset = false; Const rst_value; std::vector initval = initvals(sig_q).to_bits(); @@ -234,9 +234,9 @@ struct WreduceWorker cell->setParam(ID::SRST_VALUE, rst_value); } - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); - initvals.set_init(cell->getPort(ID::Q), initval); + cell->setPort(TW::D, sig_d); + cell->setPort(TW::Q, sig_q); + initvals.set_init(cell->getPort(TW::Q), initval); cell->fixup_parameters(); } @@ -298,7 +298,7 @@ struct WreduceWorker if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch))) return run_cell_dff(cell); - SigSpec sig = mi.sigmap(cell->getPort(ID::Y)); + SigSpec sig = mi.sigmap(cell->getPort(TW::Y)); if (sig.has_const()) return; @@ -306,8 +306,8 @@ struct WreduceWorker // Reduce size of ports A and B based on constant input bits and size of output port - int max_port_a_size = cell->hasPort(ID::A) ? GetSize(cell->getPort(ID::A)) : -1; - int max_port_b_size = cell->hasPort(ID::B) ? GetSize(cell->getPort(ID::B)) : -1; + int max_port_a_size = cell->hasPort(ID::A) ? GetSize(cell->getPort(TW::A)) : -1; + int max_port_b_size = cell->hasPort(ID::B) ? GetSize(cell->getPort(TW::B)) : -1; if (cell->type.in(ID($not), ID($pos), ID($neg), ID($and), ID($or), ID($xor), ID($add), ID($sub))) { max_port_a_size = min(max_port_a_size, GetSize(sig)); @@ -322,7 +322,7 @@ struct WreduceWorker if (cell->type.in(ID($mul), ID($add), ID($sub)) && max_port_a_size == GetSize(sig) && max_port_b_size == GetSize(sig)) { - SigSpec sig_a = mi.sigmap(cell->getPort(ID::A)), sig_b = mi.sigmap(cell->getPort(ID::B)); + SigSpec sig_a = mi.sigmap(cell->getPort(TW::A)), sig_b = mi.sigmap(cell->getPort(TW::B)); // Remove top bits from sig_a and sig_b which are not visible on the output sig_a.extend_u0(max_port_a_size); @@ -363,7 +363,7 @@ struct WreduceWorker run_reduce_inport(cell, 'B', max_port_b_size, port_b_signed, did_something); if (cell->hasPort(ID::A) && cell->hasPort(ID::B) && port_a_signed && port_b_signed) { - SigSpec sig_a = mi.sigmap(cell->getPort(ID::A)), sig_b = mi.sigmap(cell->getPort(ID::B)); + SigSpec sig_a = mi.sigmap(cell->getPort(TW::A)), sig_b = mi.sigmap(cell->getPort(TW::B)); if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0 && GetSize(sig_b) > 0 && sig_b[GetSize(sig_b)-1] == State::S0) { log("Converting cell %s.%s (%s) from signed to unsigned.\n", @@ -377,7 +377,7 @@ struct WreduceWorker } if (cell->hasPort(ID::A) && !cell->hasPort(ID::B) && port_a_signed) { - SigSpec sig_a = mi.sigmap(cell->getPort(ID::A)); + SigSpec sig_a = mi.sigmap(cell->getPort(TW::A)); if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0) { log("Converting cell %s.%s (%s) from signed to unsigned.\n", module, cell, cell->type.unescape()); @@ -414,8 +414,8 @@ struct WreduceWorker bool is_signed = cell->getParam(ID::A_SIGNED).as_bool() || cell->type == ID($sub); int a_size = 0, b_size = 0; - if (cell->hasPort(ID::A)) a_size = GetSize(cell->getPort(ID::A)); - if (cell->hasPort(ID::B)) b_size = GetSize(cell->getPort(ID::B)); + if (cell->hasPort(ID::A)) a_size = GetSize(cell->getPort(TW::A)); + if (cell->hasPort(ID::B)) b_size = GetSize(cell->getPort(TW::B)); int max_y_size = max(a_size, b_size); @@ -447,7 +447,7 @@ struct WreduceWorker if (bits_removed) { log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n", bits_removed, GetSize(sig) + bits_removed, module, cell, cell->type.unescape()); - cell->setPort(ID::Y, sig); + cell->setPort(TW::Y, sig); did_something = true; } @@ -519,7 +519,7 @@ struct WreduceWorker continue; log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), module, w); - Wire *nw = module->addWire(NEW_ID, GetSize(w) - unused_top_bits); + Wire *nw = module->addWire(NEW_TWINE, GetSize(w) - unused_top_bits); module->connect(nw, SigSpec(w).extract(0, GetSize(nw))); module->swap_names(w, nw); } @@ -591,10 +591,10 @@ struct WreducePass : public Pass { { if (c->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt), - ID($logic_not), ID($logic_and), ID($logic_or)) && GetSize(c->getPort(ID::Y)) > 1) { - SigSpec sig = c->getPort(ID::Y); + ID($logic_not), ID($logic_and), ID($logic_or)) && GetSize(c->getPort(TW::Y)) > 1) { + SigSpec sig = c->getPort(TW::Y); if (!sig.has_const()) { - c->setPort(ID::Y, sig[0]); + c->setPort(TW::Y, sig[0]); c->setParam(ID::Y_WIDTH, 1); sig.remove(0); module->connect(sig, Const(0, GetSize(sig))); @@ -603,7 +603,7 @@ struct WreducePass : public Pass { if (c->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow))) { - SigSpec A = c->getPort(ID::A); + SigSpec A = c->getPort(TW::A); int original_a_width = GetSize(A); if (c->getParam(ID::A_SIGNED).as_bool()) { while (GetSize(A) > 1 && A[GetSize(A)-1] == State::S0 && A[GetSize(A)-2] == State::S0) @@ -615,11 +615,11 @@ struct WreducePass : public Pass { if (original_a_width != GetSize(A)) { log("Removed top %d bits (of %d) from port A of cell %s.%s (%s).\n", original_a_width-GetSize(A), original_a_width, module, c, c->type.unescape()); - c->setPort(ID::A, A); + c->setPort(TW::A, A); c->setParam(ID::A_WIDTH, GetSize(A)); } - SigSpec B = c->getPort(ID::B); + SigSpec B = c->getPort(TW::B); int original_b_width = GetSize(B); if (c->getParam(ID::B_SIGNED).as_bool()) { while (GetSize(B) > 1 && B[GetSize(B)-1] == State::S0 && B[GetSize(B)-2] == State::S0) @@ -631,7 +631,7 @@ struct WreducePass : public Pass { if (original_b_width != GetSize(B)) { log("Removed top %d bits (of %d) from port B of cell %s.%s (%s).\n", original_b_width-GetSize(B), original_b_width, module, c, c->type.unescape()); - c->setPort(ID::B, B); + c->setPort(TW::B, B); c->setParam(ID::B_WIDTH, GetSize(B)); } } @@ -648,7 +648,7 @@ struct WreducePass : public Pass { c->type == ID($memrd) ? "read" : c->type == ID($memwr) ? "write" : "init", module, c, memid.unescape()); c->setParam(ID::ABITS, max_addrbits); - c->setPort(ID::ADDR, c->getPort(ID::ADDR).extract(0, max_addrbits)); + c->setPort(TW::ADDR, c->getPort(TW::ADDR).extract(0, max_addrbits)); } } } diff --git a/passes/pmgen/README.md b/passes/pmgen/README.md index 15b4f79a1..da6c0e960 100644 --- a/passes/pmgen/README.md +++ b/passes/pmgen/README.md @@ -367,8 +367,8 @@ test-case generation. For example: ... generate 10 0 SigSpec Y = port(ff, \D); - SigSpec A = module->addWire(NEW_ID, GetSize(Y) - rng(GetSize(Y)/2)); - SigSpec B = module->addWire(NEW_ID, GetSize(Y) - rng(GetSize(Y)/2)); + SigSpec A = module->addWire(NEW_TWINE, GetSize(Y) - rng(GetSize(Y)/2)); + SigSpec B = module->addWire(NEW_TWINE, GetSize(Y) - rng(GetSize(Y)/2)); module->addMul(NEW_ID, A, B, Y, rng(2)); endmatch diff --git a/passes/pmgen/generate.h b/passes/pmgen/generate.h index bee56fd34..45bc53bce 100644 --- a/passes/pmgen/generate.h +++ b/passes/pmgen/generate.h @@ -131,7 +131,7 @@ void generate_pattern(std::function)> run, const for (auto mod : mods) { Cell *c = m->addCell(mod->name, mod->name); for (auto port : mod->ports) { - Wire *w = m->addWire(NEW_ID, GetSize(mod->wire(port))); + Wire *w = m->addWire(NEW_TWINE, GetSize(mod->wire(port))); c->setPort(port, w); } } diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py index 38772964d..3ecb85fe0 100644 --- a/passes/pmgen/pmgen.py +++ b/passes/pmgen/pmgen.py @@ -451,13 +451,13 @@ with open(outfile, "w") as f: current_pattern = None - print(" SigSpec port(Cell *cell, IdString portname) {", file=f) + print(" SigSpec port(Cell *cell, TwineRef portname) {", file=f) print(" try {", file=f) print(" return (*sigmap)(cell->getPort(portname));", file=f) print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing port %s\\n\",portname); }", file=f) print(" }", file=f) print("", file=f) - print(" SigSpec port(Cell *cell, IdString portname, const SigSpec& defval) {", file=f) + print(" SigSpec port(Cell *cell, TwineRef portname, const SigSpec& defval) {", file=f) print(" return (*sigmap)(cell->connections_.at(portname, defval));", file=f) print(" }", file=f) print("", file=f) diff --git a/passes/pmgen/test_pmgen.cc b/passes/pmgen/test_pmgen.cc index 24512fc6b..e11341f4e 100644 --- a/passes/pmgen/test_pmgen.cc +++ b/passes/pmgen/test_pmgen.cc @@ -40,14 +40,14 @@ void reduce_chain(test_pmgen_pm &pm) log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), st.first->type.unescape()); SigSpec A; - SigSpec Y = ud.longest_chain.front().first->getPort(ID::Y); + SigSpec Y = ud.longest_chain.front().first->getPort(TW::Y); auto last_cell = ud.longest_chain.back().first; for (auto it : ud.longest_chain) { auto cell = it.first; if (cell == last_cell) { - A.append(cell->getPort(ID::A)); - A.append(cell->getPort(ID::B)); + A.append(cell->getPort(TW::A)); + A.append(cell->getPort(TW::B)); } else { A.append(cell->getPort(it.second == ID::A ? ID::B : ID::A)); } @@ -78,7 +78,7 @@ void reduce_tree(test_pmgen_pm &pm) return; SigSpec A = ud.leaves; - SigSpec Y = st.first->getPort(ID::Y); + SigSpec Y = st.first->getPort(TW::Y); pm.autoremove(st.first); log("Found %s tree with %d leaves for %s (%s).\n", st.first->type.unescape(), @@ -102,17 +102,17 @@ void opt_eqpmux(test_pmgen_pm &pm) { auto &st = pm.st_eqpmux; - SigSpec Y = st.pmux->getPort(ID::Y); + SigSpec Y = st.pmux->getPort(TW::Y); int width = GetSize(Y); - SigSpec EQ = st.pmux->getPort(ID::B).extract(st.pmux_slice_eq*width, width); - SigSpec NE = st.pmux->getPort(ID::B).extract(st.pmux_slice_ne*width, width); + SigSpec EQ = st.pmux->getPort(TW::B).extract(st.pmux_slice_eq*width, width); + SigSpec NE = st.pmux->getPort(TW::B).extract(st.pmux_slice_ne*width, width); log("Found eqpmux circuit driving %s (eq=%s, ne=%s, pmux=%s).\n", log_signal(Y), st.eq, st.ne, st.pmux); pm.autoremove(st.pmux); - Cell *c = pm.module->addMux(NEW_ID, NE, EQ, st.eq->getPort(ID::Y), Y); + Cell *c = pm.module->addMux(NEW_ID, NE, EQ, st.eq->getPort(TW::Y), Y); log(" -> %s (%s)\n", c, c->type.unescape()); } diff --git a/passes/pmgen/test_pmgen.pmg b/passes/pmgen/test_pmgen.pmg index 287ed97d8..e7f16644b 100644 --- a/passes/pmgen/test_pmgen.pmg +++ b/passes/pmgen/test_pmgen.pmg @@ -14,9 +14,9 @@ match first select first->type.in($_AND_, $_OR_, $_XOR_) filter !non_first_cells.count(first) generate - SigSpec A = module->addWire(NEW_ID); - SigSpec B = module->addWire(NEW_ID); - SigSpec Y = module->addWire(NEW_ID); + SigSpec A = module->addWire(NEW_TWINE); + SigSpec B = module->addWire(NEW_TWINE); + SigSpec Y = module->addWire(NEW_TWINE); switch (rng(3)) { case 0: @@ -82,8 +82,8 @@ match next index next->type === chain.back().first->type index port(next, \Y) === port(chain.back().first, chain.back().second) generate 10 - SigSpec A = module->addWire(NEW_ID); - SigSpec B = module->addWire(NEW_ID); + SigSpec A = module->addWire(NEW_TWINE); + SigSpec B = module->addWire(NEW_TWINE); SigSpec Y = port(chain.back().first, chain.back().second); Cell *c = module->addAndGate(NEW_ID, A, B, Y); c->type = chain.back().first->type; @@ -121,9 +121,9 @@ match eq set eq_inB port(eq, \B) set eq_ne_signed param(eq, \A_SIGNED).as_bool() generate 100 10 - SigSpec A = module->addWire(NEW_ID, rng(7)+1); - SigSpec B = module->addWire(NEW_ID, rng(7)+1); - SigSpec Y = module->addWire(NEW_ID); + SigSpec A = module->addWire(NEW_TWINE, rng(7)+1); + SigSpec B = module->addWire(NEW_TWINE, rng(7)+1); + SigSpec Y = module->addWire(NEW_TWINE); module->addEq(NEW_ID, A, B, Y, rng(2)); endmatch @@ -137,13 +137,13 @@ generate 100 10 int numsel = rng(4) + 1; int idx = rng(numsel); - SigSpec A = module->addWire(NEW_ID, width); - SigSpec Y = module->addWire(NEW_ID, width); + SigSpec A = module->addWire(NEW_TWINE, width); + SigSpec Y = module->addWire(NEW_TWINE, width); SigSpec B, S; for (int i = 0; i < numsel; i++) { - B.append(module->addWire(NEW_ID, width)); - S.append(i == idx ? port(eq, \Y) : module->addWire(NEW_ID)); + B.append(module->addWire(NEW_TWINE, width)); + S.append(i == idx ? port(eq, \Y) : module->addWire(NEW_TWINE)); } module->addPmux(NEW_ID, A, B, S, Y); @@ -169,9 +169,9 @@ generate 100 10 if (GetSize(Y)) Y = Y[rng(GetSize(Y))]; else - Y = module->addWire(NEW_ID); + Y = module->addWire(NEW_TWINE); } else { - Y = module->addWire(NEW_ID); + Y = module->addWire(NEW_TWINE); } module->addNe(NEW_ID, A, B, Y, rng(2)); endmatch diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index f754bc948..7963a68a3 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -39,45 +39,45 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref, for (auto cell : mod->cells()) { - if (cell->type == ID($reduce_or) && cell->getPort(ID::Y) == signal) - return check_signal(mod, cell->getPort(ID::A), ref, polarity); + if (cell->type == ID($reduce_or) && cell->getPort(TW::Y) == signal) + return check_signal(mod, cell->getPort(TW::A), ref, polarity); - if (cell->type == ID($reduce_bool) && cell->getPort(ID::Y) == signal) - return check_signal(mod, cell->getPort(ID::A), ref, polarity); + if (cell->type == ID($reduce_bool) && cell->getPort(TW::Y) == signal) + return check_signal(mod, cell->getPort(TW::A), ref, polarity); - if (cell->type == ID($logic_not) && cell->getPort(ID::Y) == signal) { + if (cell->type == ID($logic_not) && cell->getPort(TW::Y) == signal) { polarity = !polarity; - return check_signal(mod, cell->getPort(ID::A), ref, polarity); + return check_signal(mod, cell->getPort(TW::A), ref, polarity); } - if (cell->type == ID($not) && cell->getPort(ID::Y) == signal) { + if (cell->type == ID($not) && cell->getPort(TW::Y) == signal) { polarity = !polarity; - return check_signal(mod, cell->getPort(ID::A), ref, polarity); + return check_signal(mod, cell->getPort(TW::A), ref, polarity); } - if (cell->type.in(ID($eq), ID($eqx)) && cell->getPort(ID::Y) == signal) { - if (cell->getPort(ID::A).is_fully_const()) { - if (!cell->getPort(ID::A).as_bool()) + if (cell->type.in(ID($eq), ID($eqx)) && cell->getPort(TW::Y) == signal) { + if (cell->getPort(TW::A).is_fully_const()) { + if (!cell->getPort(TW::A).as_bool()) polarity = !polarity; - return check_signal(mod, cell->getPort(ID::B), ref, polarity); + return check_signal(mod, cell->getPort(TW::B), ref, polarity); } - if (cell->getPort(ID::B).is_fully_const()) { - if (!cell->getPort(ID::B).as_bool()) + if (cell->getPort(TW::B).is_fully_const()) { + if (!cell->getPort(TW::B).as_bool()) polarity = !polarity; - return check_signal(mod, cell->getPort(ID::A), ref, polarity); + return check_signal(mod, cell->getPort(TW::A), ref, polarity); } } - if (cell->type.in(ID($ne), ID($nex)) && cell->getPort(ID::Y) == signal) { - if (cell->getPort(ID::A).is_fully_const()) { - if (cell->getPort(ID::A).as_bool()) + if (cell->type.in(ID($ne), ID($nex)) && cell->getPort(TW::Y) == signal) { + if (cell->getPort(TW::A).is_fully_const()) { + if (cell->getPort(TW::A).as_bool()) polarity = !polarity; - return check_signal(mod, cell->getPort(ID::B), ref, polarity); + return check_signal(mod, cell->getPort(TW::B), ref, polarity); } - if (cell->getPort(ID::B).is_fully_const()) { - if (cell->getPort(ID::B).as_bool()) + if (cell->getPort(TW::B).is_fully_const()) { + if (cell->getPort(TW::B).as_bool()) polarity = !polarity; - return check_signal(mod, cell->getPort(ID::A), ref, polarity); + return check_signal(mod, cell->getPort(TW::A), ref, polarity); } } } diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 06c740a88..d6ffb3eec 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -100,11 +100,11 @@ void gen_aldff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size()); cell->parameters[ID::ALOAD_POLARITY] = RTLIL::Const(set_polarity, 1); cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1); - cell->setPort(ID::D, sig_in); - cell->setPort(ID::Q, sig_out); - cell->setPort(ID::AD, sig_set); - cell->setPort(ID::CLK, clk); - cell->setPort(ID::ALOAD, set); + cell->setPort(TW::D, sig_in); + cell->setPort(TW::Q, sig_out); + cell->setPort(TW::AD, sig_set); + cell->setPort(TW::CLK, clk); + cell->setPort(TW::ALOAD, set); log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type, cell->name, clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative"); @@ -128,12 +128,12 @@ void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RT cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1); } - cell->setPort(ID::D, sig_in); - cell->setPort(ID::Q, sig_out); + cell->setPort(TW::D, sig_in); + cell->setPort(TW::Q, sig_out); if (arst) - cell->setPort(ID::ARST, *arst); + cell->setPort(TW::ARST, *arst); if (!clk.empty()) - cell->setPort(ID::CLK, clk); + cell->setPort(TW::CLK, clk); if (!clk.empty()) log(" created %s cell `%s' with %s edge clock", cell->type, cell->name, clk_polarity ? "positive" : "negative"); diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc index 5e07dbcb0..c759bec1b 100644 --- a/passes/proc/proc_dlatch.cc +++ b/passes/proc/proc_dlatch.cc @@ -48,14 +48,14 @@ struct proc_dlatch_db_t { if (cell->type.in(ID($mux), ID($pmux), ID($bwmux))) { - auto sig_y = sigmap(cell->getPort(ID::Y)); + auto sig_y = sigmap(cell->getPort(TW::Y)); for (int i = 0; i < GetSize(sig_y); i++) mux_drivers[sig_y[i]] = pair(cell, i); pool mux_srcbits_pool; - for (auto bit : sigmap(cell->getPort(ID::A))) + for (auto bit : sigmap(cell->getPort(TW::A))) mux_srcbits_pool.insert(bit); - for (auto bit : sigmap(cell->getPort(ID::B))) + for (auto bit : sigmap(cell->getPort(TW::B))) mux_srcbits_pool.insert(bit); vector mux_srcbits_vec; @@ -187,9 +187,9 @@ struct proc_dlatch_db_t log_assert(cell->type.in(ID($mux), ID($pmux), ID($bwmux))); bool is_bwmux = (cell->type == ID($bwmux)); - SigSpec sig_a = sigmap(cell->getPort(ID::A)); - SigSpec sig_b = sigmap(cell->getPort(ID::B)); - SigSpec sig_s = sigmap(cell->getPort(ID::S)); + SigSpec sig_a = sigmap(cell->getPort(TW::A)); + SigSpec sig_b = sigmap(cell->getPort(TW::B)); + SigSpec sig_s = sigmap(cell->getPort(TW::S)); int width = GetSize(sig_a); pool children; @@ -197,9 +197,9 @@ struct proc_dlatch_db_t int n = find_mux_feedback(sig_a[index], needle, set_undef); if (n != false_node) { if (set_undef && sig_a[index] == needle) { - SigSpec sig = cell->getPort(ID::A); + SigSpec sig = cell->getPort(TW::A); sig[index] = State::Sx; - cell->setPort(ID::A, sig); + cell->setPort(TW::A, sig); } if (!is_bwmux) { for (int i = 0; i < GetSize(sig_s); i++) @@ -214,9 +214,9 @@ struct proc_dlatch_db_t n = find_mux_feedback(sig_b[i*width + index], needle, set_undef); if (n != false_node) { if (set_undef && sig_b[i*width + index] == needle) { - SigSpec sig = cell->getPort(ID::B); + SigSpec sig = cell->getPort(TW::B); sig[i*width + index] = State::Sx; - cell->setPort(ID::B, sig); + cell->setPort(TW::B, sig); } children.insert(make_inner(sig_s[is_bwmux ? index : i], State::S1, n)); } @@ -268,9 +268,9 @@ struct proc_dlatch_db_t void fixup_mux(Cell *cell) { - SigSpec sig_a = cell->getPort(ID::A); - SigSpec sig_b = cell->getPort(ID::B); - SigSpec sig_s = cell->getPort(ID::S); + SigSpec sig_a = cell->getPort(TW::A); + SigSpec sig_b = cell->getPort(TW::B); + SigSpec sig_s = cell->getPort(TW::S); SigSpec sig_any_valid_b; SigSpec sig_new_b, sig_new_s; @@ -289,7 +289,7 @@ struct proc_dlatch_db_t } if (sig_a.is_fully_undef() && !sig_any_valid_b.empty()) - cell->setPort(ID::A, sig_any_valid_b); + cell->setPort(TW::A, sig_any_valid_b); if (GetSize(sig_new_s) == 1) { cell->type = ID($mux); @@ -299,8 +299,8 @@ struct proc_dlatch_db_t cell->setParam(ID::S_WIDTH, GetSize(sig_new_s)); } - cell->setPort(ID::B, sig_new_b); - cell->setPort(ID::S, sig_new_s); + cell->setPort(TW::B, sig_new_b); + cell->setPort(TW::S, sig_new_s); } void fixup_muxes() diff --git a/passes/proc/proc_memwr.cc b/passes/proc/proc_memwr.cc index e79d24e96..a39db73fe 100644 --- a/passes/proc/proc_memwr.cc +++ b/passes/proc/proc_memwr.cc @@ -42,15 +42,15 @@ void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict &n priority_mask.set(prev_port_ids[i], State::S1); prev_port_ids.push_back(port_id); - RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($memwr_v2)); + RTLIL::Cell *cell = mod->addCell(NEW_TWINE, ID($memwr_v2)); cell->attributes = memwr.attributes; cell->setParam(ID::MEMID, Const(memwr.memid.str())); cell->setParam(ID::ABITS, GetSize(memwr.address)); cell->setParam(ID::WIDTH, GetSize(memwr.data)); cell->setParam(ID::PORTID, port_id); cell->setParam(ID::PRIORITY_MASK, priority_mask); - cell->setPort(ID::ADDR, memwr.address); - cell->setPort(ID::DATA, memwr.data); + cell->setPort(TW::ADDR, memwr.address); + cell->setPort(TW::DATA, memwr.data); SigSpec enable = memwr.enable; for (auto sr2 : proc->syncs) { if (sr2->type == RTLIL::SyncType::ST0) { @@ -61,17 +61,17 @@ void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict &n enable = mod->Mux(NEW_ID, enable, Const(State::S0, GetSize(enable)), sr2->signal); } } - cell->setPort(ID::EN, enable); + cell->setPort(TW::EN, enable); if (sr->type == RTLIL::SyncType::STa) { - cell->setPort(ID::CLK, State::Sx); + cell->setPort(TW::CLK, State::Sx); cell->setParam(ID::CLK_ENABLE, State::S0); cell->setParam(ID::CLK_POLARITY, State::Sx); } else if (sr->type == RTLIL::SyncType::STp) { - cell->setPort(ID::CLK, sr->signal); + cell->setPort(TW::CLK, sr->signal); cell->setParam(ID::CLK_ENABLE, State::S1); cell->setParam(ID::CLK_POLARITY, State::S1); } else if (sr->type == RTLIL::SyncType::STn) { - cell->setPort(ID::CLK, sr->signal); + cell->setPort(TW::CLK, sr->signal); cell->setParam(ID::CLK_ENABLE, State::S1); cell->setParam(ID::CLK_POLARITY, State::S0); } else { diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 33d7d40dc..2ace54222 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -188,9 +188,9 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s eq_cell->parameters[ID::B_WIDTH] = RTLIL::Const(comp.size()); eq_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1); - eq_cell->setPort(ID::A, sig); - eq_cell->setPort(ID::B, comp); - eq_cell->setPort(ID::Y, RTLIL::SigSpec(cmp_wire, cmp_wire->width++)); + eq_cell->setPort(TW::A, sig); + eq_cell->setPort(TW::B, comp); + eq_cell->setPort(TW::Y, RTLIL::SigSpec(cmp_wire, cmp_wire->width++)); } } @@ -211,8 +211,8 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s any_cell->parameters[ID::A_WIDTH] = RTLIL::Const(cmp_wire->width); any_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1); - any_cell->setPort(ID::A, cmp_wire); - any_cell->setPort(ID::Y, RTLIL::SigSpec(ctrl_wire)); + any_cell->setPort(TW::A, cmp_wire); + any_cell->setPort(TW::Y, RTLIL::SigSpec(ctrl_wire)); } return RTLIL::SigSpec(ctrl_wire); @@ -243,10 +243,10 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s apply_attrs(mux_cell, sw, cs); mux_cell->parameters[ID::WIDTH] = RTLIL::Const(when_signal.size()); - mux_cell->setPort(ID::A, else_signal); - mux_cell->setPort(ID::B, when_signal); - mux_cell->setPort(ID::S, ctrl_sig); - mux_cell->setPort(ID::Y, RTLIL::SigSpec(result_wire)); + mux_cell->setPort(TW::A, else_signal); + mux_cell->setPort(TW::B, when_signal); + mux_cell->setPort(TW::S, ctrl_sig); + mux_cell->setPort(TW::Y, RTLIL::SigSpec(result_wire)); last_mux_cell = mux_cell; return RTLIL::SigSpec(result_wire); @@ -255,24 +255,24 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode) { log_assert(last_mux_cell != NULL); - log_assert(when_signal.size() == last_mux_cell->getPort(ID::A).size()); + log_assert(when_signal.size() == last_mux_cell->getPort(TW::A).size()); - if (when_signal == last_mux_cell->getPort(ID::A)) + if (when_signal == last_mux_cell->getPort(TW::A)) return; RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, cs, ifxmode); log_assert(ctrl_sig.size() == 1); last_mux_cell->type = ID($pmux); - RTLIL::SigSpec new_s = last_mux_cell->getPort(ID::S); + RTLIL::SigSpec new_s = last_mux_cell->getPort(TW::S); new_s.append(ctrl_sig); - last_mux_cell->setPort(ID::S, new_s); + last_mux_cell->setPort(TW::S, new_s); - RTLIL::SigSpec new_b = last_mux_cell->getPort(ID::B); + RTLIL::SigSpec new_b = last_mux_cell->getPort(TW::B); new_b.append(when_signal); - last_mux_cell->setPort(ID::B, new_b); + last_mux_cell->setPort(TW::B, new_b); - last_mux_cell->parameters[ID::S_WIDTH] = last_mux_cell->getPort(ID::S).size(); + last_mux_cell->parameters[ID::S_WIDTH] = last_mux_cell->getPort(TW::S).size(); } const pool &get_full_case_bits(SnippetSwCache &swcache, RTLIL::SwitchRule *sw) diff --git a/passes/proc/proc_rom.cc b/passes/proc/proc_rom.cc index 52a72cdf0..13fc984c9 100644 --- a/passes/proc/proc_rom.cc +++ b/passes/proc/proc_rom.cc @@ -151,7 +151,7 @@ struct RomWorker } // Ok, let's do it. - SigSpec rdata = module->addWire(NEW_ID, GetSize(lhs)); + SigSpec rdata = module->addWire(NEW_TWINE, GetSize(lhs)); Mem mem(module, NEW_ID, GetSize(lhs), 0, 1 << abits); mem.attributes = sw->attributes; diff --git a/passes/sat/assertpmux.cc b/passes/sat/assertpmux.cc index 9bd08ecd1..c352027e3 100644 --- a/passes/sat/assertpmux.cc +++ b/passes/sat/assertpmux.cc @@ -59,9 +59,9 @@ struct AssertpmuxWorker int width = cell->getParam(ID::WIDTH).as_int(); int numports = cell->type == ID($mux) ? 2 : cell->getParam(ID::S_WIDTH).as_int() + 1; - SigSpec sig_a = sigmap(cell->getPort(ID::A)); - SigSpec sig_b = sigmap(cell->getPort(ID::B)); - SigSpec sig_s = sigmap(cell->getPort(ID::S)); + SigSpec sig_a = sigmap(cell->getPort(TW::A)); + SigSpec sig_b = sigmap(cell->getPort(TW::B)); + SigSpec sig_s = sigmap(cell->getPort(TW::S)); for (int i = 0; i < numports; i++) { SigSpec bits = i == 0 ? sig_a : sig_b.extract(width*(i-1), width); @@ -100,12 +100,12 @@ struct AssertpmuxWorker if (muxport_actsignal.count(muxport) == 0) { if (portidx == 0) - muxport_actsignal[muxport] = module->LogicNot(NEW_ID, cell->getPort(ID::S)); + muxport_actsignal[muxport] = module->LogicNot(NEW_ID, cell->getPort(TW::S)); else - muxport_actsignal[muxport] = cell->getPort(ID::S)[portidx-1]; + muxport_actsignal[muxport] = cell->getPort(TW::S)[portidx-1]; } - output.append(module->LogicAnd(NEW_ID, muxport_actsignal.at(muxport), get_bit_activation(cell->getPort(ID::Y)[bitidx]))); + output.append(module->LogicAnd(NEW_ID, muxport_actsignal.at(muxport), get_bit_activation(cell->getPort(TW::Y)[bitidx]))); } output.sort_and_unify(); @@ -153,7 +153,7 @@ struct AssertpmuxWorker int swidth = pmux->getParam(ID::S_WIDTH).as_int(); int cntbits = ceil_log2(swidth+1); - SigSpec sel = pmux->getPort(ID::S); + SigSpec sel = pmux->getPort(TW::S); SigSpec cnt(State::S0, cntbits); for (int i = 0; i < swidth; i++) @@ -166,7 +166,7 @@ struct AssertpmuxWorker assert_en.append(module->LogicNot(NEW_ID, module->Initstate(NEW_ID))); if (!flag_always) - assert_en.append(get_activation(pmux->getPort(ID::Y))); + assert_en.append(get_activation(pmux->getPort(TW::Y))); if (GetSize(assert_en) == 0) assert_en = State::S1; diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc index 224d0a0a1..c7960b7f6 100644 --- a/passes/sat/async2sync.cc +++ b/passes/sat/async2sync.cc @@ -97,30 +97,30 @@ struct Async2syncPass : public Pass { if (initstate == State::S0) initstate = module->Initstate(NEW_ID); - SigBit sig_en = cell->getPort(ID::EN); - cell->setPort(ID::EN, module->And(NEW_ID, sig_en, initstate)); + SigBit sig_en = cell->getPort(TW::EN); + cell->setPort(TW::EN, module->And(NEW_ID, sig_en, initstate)); } else { - SigBit sig_en = cell->getPort(ID::EN); - SigSpec sig_args = cell->getPort(ID::ARGS); + SigBit sig_en = cell->getPort(TW::EN); + SigSpec sig_args = cell->getPort(TW::ARGS); bool trg_polarity = cell->getParam(ID(TRG_POLARITY)).as_bool(); - SigBit sig_trg = cell->getPort(ID::TRG); - Wire *sig_en_q = module->addWire(NEW_ID); - Wire *sig_args_q = module->addWire(NEW_ID, GetSize(sig_args)); + SigBit sig_trg = cell->getPort(TW::TRG); + Wire *sig_en_q = module->addWire(NEW_TWINE); + Wire *sig_args_q = module->addWire(NEW_TWINE, GetSize(sig_args)); sig_en_q->attributes.emplace(ID::init, State::S0); module->addDff(NEW_ID, sig_trg, sig_en, sig_en_q, trg_polarity, cell->src_ref()); module->addDff(NEW_ID, sig_trg, sig_args, sig_args_q, trg_polarity, cell->src_ref()); - cell->setPort(ID::EN, sig_en_q); - cell->setPort(ID::ARGS, sig_args_q); + cell->setPort(TW::EN, sig_en_q); + cell->setPort(TW::ARGS, sig_args_q); if (cell->type == ID($check)) { - SigBit sig_a = cell->getPort(ID::A); - Wire *sig_a_q = module->addWire(NEW_ID); + SigBit sig_a = cell->getPort(TW::A); + Wire *sig_a_q = module->addWire(NEW_TWINE); sig_a_q->attributes.emplace(ID::init, State::S1); module->addDff(NEW_ID, sig_trg, sig_a, sig_a_q, trg_polarity, cell->src_ref()); - cell->setPort(ID::A, sig_a_q); + cell->setPort(TW::A, sig_a_q); } } - cell->setPort(ID::TRG, SigSpec()); + cell->setPort(TW::TRG, SigSpec()); cell->setParam(ID::TRG_ENABLE, false); cell->setParam(ID::TRG_WIDTH, 0); @@ -152,8 +152,8 @@ struct Async2syncPass : public Pass { initvals.remove_init(ff.sig_q); - Wire *new_d = module->addWire(NEW_ID, ff.width); - Wire *new_q = module->addWire(NEW_ID, ff.width); + Wire *new_d = module->addWire(NEW_TWINE, ff.width); + Wire *new_q = module->addWire(NEW_TWINE, ff.width); SigSpec sig_set = ff.sig_set; SigSpec sig_clr = ff.sig_clr; @@ -217,8 +217,8 @@ struct Async2syncPass : public Pass { initvals.remove_init(ff.sig_q); - Wire *new_d = module->addWire(NEW_ID, ff.width); - Wire *new_q = module->addWire(NEW_ID, ff.width); + Wire *new_d = module->addWire(NEW_TWINE, ff.width); + Wire *new_q = module->addWire(NEW_TWINE, ff.width); if (ff.pol_aload) { if (!ff.is_fine) { @@ -250,7 +250,7 @@ struct Async2syncPass : public Pass { initvals.remove_init(ff.sig_q); - Wire *new_q = module->addWire(NEW_ID, ff.width); + Wire *new_q = module->addWire(NEW_TWINE, ff.width); if (ff.pol_arst) { if (!ff.is_fine) @@ -284,11 +284,11 @@ struct Async2syncPass : public Pass { initvals.remove_init(ff.sig_q); - Wire *new_q = module->addWire(NEW_ID, ff.width); + Wire *new_q = module->addWire(NEW_TWINE, ff.width); Wire *new_d; if (ff.has_aload) { - new_d = module->addWire(NEW_ID, ff.width); + new_d = module->addWire(NEW_TWINE, ff.width); if (ff.pol_aload) { if (!ff.is_fine) module->addMux(NEW_ID, new_q, ff.sig_ad, ff.sig_aload, new_d); diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index 0b928ddf6..e295b4dea 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -72,7 +72,7 @@ struct Clk2fflogicPass : public Pass { } std::string sig_str = log_signal(sig); sig_str.erase(std::remove(sig_str.begin(), sig_str.end(), ' '), sig_str.end()); - Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig)); + Wire *sampled_sig = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig)); sampled_sig->attributes[ID::init] = RTLIL::Const(State::S0, GetSize(sig)); if (is_fine) module->addFfGate(NEW_ID, sig, sampled_sig); @@ -84,7 +84,7 @@ struct Clk2fflogicPass : public Pass { SigSpec sample_control_edge(Module *module, SigSpec sig, bool polarity, bool is_fine) { std::string sig_str = log_signal(sig); sig_str.erase(std::remove(sig_str.begin(), sig_str.end(), ' '), sig_str.end()); - Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig)); + Wire *sampled_sig = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig)); sampled_sig->attributes[ID::init] = RTLIL::Const(polarity ? State::S1 : State::S0, GetSize(sig)); if (is_fine) module->addFfGate(NEW_ID, sig, sampled_sig); @@ -98,7 +98,7 @@ struct Clk2fflogicPass : public Pass { sig_str.erase(std::remove(sig_str.begin(), sig_str.end(), ' '), sig_str.end()); - Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig)); + Wire *sampled_sig = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig)); sampled_sig->attributes[ID::init] = init; Cell *cell; @@ -187,7 +187,7 @@ struct Clk2fflogicPass : public Pass { i, module, mem.memid.unescape(), log_signal(port.clk), log_signal(port.addr), log_signal(port.data)); - Wire *past_clk = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#past_clk#%s", mem.memid.unescape(), i, log_signal(port.clk)))); + Wire *past_clk = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#past_clk#%s", mem.memid.unescape(), i, log_signal(port.clk)))); past_clk->attributes[ID::init] = port.clk_polarity ? State::S1 : State::S0; module->addFf(NEW_ID, port.clk, past_clk); @@ -203,13 +203,13 @@ struct Clk2fflogicPass : public Pass { SigSpec clock_edge = module->Eqx(NEW_ID, {port.clk, SigSpec(past_clk)}, clock_edge_pattern); - SigSpec en_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#en_q", mem.memid.unescape(), i)), GetSize(port.en)); + SigSpec en_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#en_q", mem.memid.unescape(), i)), GetSize(port.en)); module->addFf(NEW_ID, port.en, en_q); - SigSpec addr_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#addr_q", mem.memid.unescape(), i)), GetSize(port.addr)); + SigSpec addr_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#addr_q", mem.memid.unescape(), i)), GetSize(port.addr)); module->addFf(NEW_ID, port.addr, addr_q); - SigSpec data_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#data_q", mem.memid.unescape(), i)), GetSize(port.data)); + SigSpec data_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#data_q", mem.memid.unescape(), i)), GetSize(port.data)); module->addFf(NEW_ID, port.data, data_q); port.clk = State::S0; @@ -243,13 +243,13 @@ struct Clk2fflogicPass : public Pass { if (initstate == State::S0) initstate = module->Initstate(NEW_ID); - SigBit sig_en = cell->getPort(ID::EN); - cell->setPort(ID::EN, module->And(NEW_ID, sig_en, initstate)); + SigBit sig_en = cell->getPort(TW::EN); + cell->setPort(TW::EN, module->And(NEW_ID, sig_en, initstate)); } else { - SigBit sig_en = cell->getPort(ID::EN); - SigSpec sig_args = cell->getPort(ID::ARGS); + SigBit sig_en = cell->getPort(TW::EN); + SigSpec sig_args = cell->getPort(TW::ARGS); Const trg_polarity = cell->getParam(ID(TRG_POLARITY)); - SigSpec sig_trg = cell->getPort(ID::TRG); + SigSpec sig_trg = cell->getPort(TW::TRG); SigSpec sig_trg_sampled; @@ -260,16 +260,16 @@ struct Clk2fflogicPass : public Pass { SigBit sig_trg_combined = module->ReduceOr(NEW_ID, sig_trg_sampled); - cell->setPort(ID::EN, module->And(NEW_ID, sig_en_sampled, sig_trg_combined)); - cell->setPort(ID::ARGS, sig_args_sampled); + cell->setPort(TW::EN, module->And(NEW_ID, sig_en_sampled, sig_trg_combined)); + cell->setPort(TW::ARGS, sig_args_sampled); if (cell->type == ID($check)) { - SigBit sig_a = cell->getPort(ID::A); + SigBit sig_a = cell->getPort(TW::A); SigBit sig_a_sampled = sample_data(module, sig_a, State::S1, false, false).sampled; - cell->setPort(ID::A, sig_a_sampled); + cell->setPort(TW::A, sig_a_sampled); } } - cell->setPort(ID::TRG, SigSpec()); + cell->setPort(TW::TRG, SigSpec()); cell->setParam(ID::TRG_ENABLE, false); cell->setParam(ID::TRG_WIDTH, 0); diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc index f0582dc69..24876aeec 100644 --- a/passes/sat/cutpoint.cc +++ b/passes/sat/cutpoint.cc @@ -154,7 +154,7 @@ struct CutpointPass : public Pass { RTLIL::Cell *scopeinfo = nullptr; RTLIL::IdString cell_name(cell->name); if (flag_scopeinfo && cell_name.isPublic()) { - auto scopeinfo = module->addCell(NEW_ID, ID($scopeinfo)); + auto scopeinfo = module->addCell(NEW_TWINE, ID($scopeinfo)); scopeinfo->setParam(ID::TYPE, RTLIL::Const("blackbox")); for (auto const &attr : cell->attributes) @@ -175,7 +175,7 @@ struct CutpointPass : public Pass { for (auto wire : module->selected_wires()) { if (wire->port_output) { log("Making output wire %s.%s a cutpoint.\n", module, wire); - Wire *new_wire = module->addWire(NEW_ID, wire); + Wire *new_wire = module->addWire(NEW_TWINE, wire); module->swap_names(wire, new_wire); module->connect(new_wire, flag_undef ? Const(State::Sx, GetSize(new_wire)) : module->Anyseq(NEW_ID, GetSize(new_wire))); wire->port_id = 0; @@ -202,7 +202,7 @@ struct CutpointPass : public Pass { } if (bit_count == 0) continue; - SigSpec dummy = module->addWire(NEW_ID, bit_count); + SigSpec dummy = module->addWire(NEW_TWINE, bit_count); bit_count = 0; for (auto &bit : sig) { if (cutpoint_bits.count(bit)) @@ -226,7 +226,7 @@ struct CutpointPass : public Pass { } for (auto wire : rewrite_wires) { - Wire *new_wire = module->addWire(NEW_ID, wire); + Wire *new_wire = module->addWire(NEW_TWINE, wire); SigSpec lhs, rhs, sig = sigmap(wire); for (int i = 0; i < GetSize(sig); i++) if (!cutpoint_bits.count(sig[i])) { diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index e84bd9e89..04e6d4a6a 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -86,7 +86,7 @@ void find_dff_wires(std::set &dff_wires, RTLIL::Module *module) for (auto cell : module->cells()) { if (ct.cell_known(cell->type) && cell->hasPort(ID::Q)) - dffsignals.add(sigmap(cell->getPort(ID::Q))); + dffsignals.add(sigmap(cell->getPort(TW::Q))); } for (auto w : module->wires()) { @@ -112,10 +112,10 @@ void create_dff_dq_map(std::map &map, RTLIL::Mo info.cell = cell; if (info.cell->type == ID($dff)) { - info.bit_clk = sigmap(info.cell->getPort(ID::CLK)).as_bit(); + info.bit_clk = sigmap(info.cell->getPort(TW::CLK)).as_bit(); info.clk_polarity = info.cell->parameters.at(ID::CLK_POLARITY).as_bool(); - std::vector sig_d = sigmap(info.cell->getPort(ID::D)).to_sigbit_vector(); - std::vector sig_q = sigmap(info.cell->getPort(ID::Q)).to_sigbit_vector(); + std::vector sig_d = sigmap(info.cell->getPort(TW::D)).to_sigbit_vector(); + std::vector sig_q = sigmap(info.cell->getPort(TW::Q)).to_sigbit_vector(); for (size_t i = 0; i < sig_d.size(); i++) { info.bit_d = sig_d.at(i); bit_info[sig_q.at(i)] = info; @@ -124,12 +124,12 @@ void create_dff_dq_map(std::map &map, RTLIL::Mo } if (info.cell->type == ID($adff)) { - info.bit_clk = sigmap(info.cell->getPort(ID::CLK)).as_bit(); - info.bit_arst = sigmap(info.cell->getPort(ID::ARST)).as_bit(); + info.bit_clk = sigmap(info.cell->getPort(TW::CLK)).as_bit(); + info.bit_arst = sigmap(info.cell->getPort(TW::ARST)).as_bit(); info.clk_polarity = info.cell->parameters.at(ID::CLK_POLARITY).as_bool(); info.arst_polarity = info.cell->parameters.at(ID::ARST_POLARITY).as_bool(); - std::vector sig_d = sigmap(info.cell->getPort(ID::D)).to_sigbit_vector(); - std::vector sig_q = sigmap(info.cell->getPort(ID::Q)).to_sigbit_vector(); + std::vector sig_d = sigmap(info.cell->getPort(TW::D)).to_sigbit_vector(); + std::vector sig_q = sigmap(info.cell->getPort(TW::Q)).to_sigbit_vector(); std::vector arst_value = info.cell->parameters.at(ID::ARST_VALUE).to_bits(); for (size_t i = 0; i < sig_d.size(); i++) { info.bit_d = sig_d.at(i); @@ -140,21 +140,21 @@ void create_dff_dq_map(std::map &map, RTLIL::Mo } if (info.cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) { - info.bit_clk = sigmap(info.cell->getPort(ID::C)).as_bit(); + info.bit_clk = sigmap(info.cell->getPort(TW::C)).as_bit(); info.clk_polarity = info.cell->type == ID($_DFF_P_); - info.bit_d = sigmap(info.cell->getPort(ID::D)).as_bit(); - bit_info[sigmap(info.cell->getPort(ID::Q)).as_bit()] = info; + info.bit_d = sigmap(info.cell->getPort(TW::D)).as_bit(); + bit_info[sigmap(info.cell->getPort(TW::Q)).as_bit()] = info; continue; } if (info.cell->type.size() == 10 && info.cell->type.begins_with("$_DFF_")) { - info.bit_clk = sigmap(info.cell->getPort(ID::C)).as_bit(); - info.bit_arst = sigmap(info.cell->getPort(ID::R)).as_bit(); + info.bit_clk = sigmap(info.cell->getPort(TW::C)).as_bit(); + info.bit_arst = sigmap(info.cell->getPort(TW::R)).as_bit(); info.clk_polarity = info.cell->type[6] == 'P'; info.arst_polarity = info.cell->type[7] == 'P'; info.arst_value = info.cell->type[0] == '1' ? RTLIL::State::S1 : RTLIL::State::S0; - info.bit_d = sigmap(info.cell->getPort(ID::D)).as_bit(); - bit_info[sigmap(info.cell->getPort(ID::Q)).as_bit()] = info; + info.bit_d = sigmap(info.cell->getPort(TW::D)).as_bit(); + bit_info[sigmap(info.cell->getPort(TW::Q)).as_bit()] = info; continue; } } @@ -546,11 +546,11 @@ struct ExposePass : public Pass { for (auto &cell_name : info.cells) { RTLIL::Cell *cell = module->cell(cell_name); - std::vector cell_q_bits = sigmap(cell->getPort(ID::Q)).to_sigbit_vector(); + std::vector cell_q_bits = sigmap(cell->getPort(TW::Q)).to_sigbit_vector(); for (auto &bit : cell_q_bits) if (wire_bits_set.count(bit)) bit = RTLIL::SigBit(wire_dummy_q, wire_dummy_q->width++); - cell->setPort(ID::Q, cell_q_bits); + cell->setPort(TW::Q, cell_q_bits); } RTLIL::Wire *wire_q = add_new_wire(module, wire->name.str() + sep + "q", wire->width); @@ -578,12 +578,12 @@ struct ExposePass : public Pass { if (info.clk_polarity) { module->connect(RTLIL::SigSig(wire_c, info.sig_clk)); } else { - RTLIL::Cell *c = module->addCell(NEW_ID, ID($not)); + RTLIL::Cell *c = module->addCell(NEW_TWINE, ID($not)); c->parameters[ID::A_SIGNED] = 0; c->parameters[ID::A_WIDTH] = 1; c->parameters[ID::Y_WIDTH] = 1; - c->setPort(ID::A, info.sig_clk); - c->setPort(ID::Y, wire_c); + c->setPort(TW::A, info.sig_clk); + c->setPort(TW::Y, wire_c); } if (info.sig_arst != RTLIL::State::Sm) @@ -594,12 +594,12 @@ struct ExposePass : public Pass { if (info.arst_polarity) { module->connect(RTLIL::SigSig(wire_r, info.sig_arst)); } else { - RTLIL::Cell *c = module->addCell(NEW_ID, ID($not)); + RTLIL::Cell *c = module->addCell(NEW_TWINE, ID($not)); c->parameters[ID::A_SIGNED] = 0; c->parameters[ID::A_WIDTH] = 1; c->parameters[ID::Y_WIDTH] = 1; - c->setPort(ID::A, info.sig_arst); - c->setPort(ID::Y, wire_r); + c->setPort(TW::A, info.sig_arst); + c->setPort(TW::Y, wire_r); } RTLIL::Wire *wire_v = add_new_wire(module, wire->name.str() + sep + "v", wire->width); diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc index 08c35a667..d3550f7eb 100644 --- a/passes/sat/fmcombine.cc +++ b/passes/sat/fmcombine.cc @@ -119,8 +119,8 @@ struct FmcombineWorker Cell *gate = import_prim_cell(cell, "_gate"); if (opts.initeq) { if (cell->is_builtin_ff()) { - SigSpec gold_q = gold->getPort(ID::Q); - SigSpec gate_q = gate->getPort(ID::Q); + SigSpec gold_q = gold->getPort(TW::Q); + SigSpec gate_q = gate->getPort(TW::Q); SigSpec en = module->Initstate(NEW_ID); SigSpec eq = module->Eq(NEW_ID, gold_q, gate_q); module->addAssume(NEW_ID, eq, en); diff --git a/passes/sat/fminit.cc b/passes/sat/fminit.cc index 4627a6c96..e9cfc2f23 100644 --- a/passes/sat/fminit.cc +++ b/passes/sat/fminit.cc @@ -152,7 +152,7 @@ struct FminitPass : public Pass { { SigSpec insig = i > 0 ? ctrlsig.at(i-1) : State::S0; - Wire *outwire = module->addWire(NEW_ID); + Wire *outwire = module->addWire(NEW_TWINE); outwire->attributes[ID::init] = i > 0 ? State::S0 : State::S1; if (clksig.empty()) @@ -166,7 +166,7 @@ struct FminitPass : public Pass { if (i+1 == GetSize(it.second) && ctrlsig_latched[i].empty()) { - Wire *ffwire = module->addWire(NEW_ID); + Wire *ffwire = module->addWire(NEW_TWINE); ffwire->attributes[ID::init] = State::S0; SigSpec outsig = module->Or(NEW_ID, ffwire, ctrlsig[i]); diff --git a/passes/sat/formalff.cc b/passes/sat/formalff.cc index a2500bde4..fefd5dc51 100644 --- a/passes/sat/formalff.cc +++ b/passes/sat/formalff.cc @@ -53,7 +53,7 @@ struct InitValWorker } // Sign/Zero-extended indexing of individual port bits - static SigBit bit_in_port(RTLIL::Cell *cell, RTLIL::IdString port, RTLIL::IdString sign, int index) + static SigBit bit_in_port(RTLIL::Cell *cell, TwineRef port, RTLIL::IdString sign, int index) { auto sig_port = cell->getPort(port); if (index < GetSize(sig_port)) @@ -114,17 +114,17 @@ struct InitValWorker { if (cell->type == ID($mux)) { - SigBit sig_s = sigmap(cell->getPort(ID::S)); + SigBit sig_s = sigmap(cell->getPort(TW::S)); State init_s = initconst(sig_s); State init_y; if (init_s == State::S0) { - init_y = initconst(cell->getPort(ID::A)[portbit.offset]); + init_y = initconst(cell->getPort(TW::A)[portbit.offset]); } else if (init_s == State::S1) { - init_y = initconst(cell->getPort(ID::B)[portbit.offset]); + init_y = initconst(cell->getPort(TW::B)[portbit.offset]); } else { - State init_a = initconst(cell->getPort(ID::A)[portbit.offset]); - State init_b = initconst(cell->getPort(ID::B)[portbit.offset]); + State init_a = initconst(cell->getPort(TW::A)[portbit.offset]); + State init_b = initconst(cell->getPort(TW::B)[portbit.offset]); init_y = init_a == init_b ? init_a : State::Sx; } initconst_bits[bit] = init_y; @@ -156,8 +156,8 @@ struct InitValWorker return State::S0; } - SigSpec sig_a = cell->getPort(ID::A); - SigSpec sig_b = cell->getPort(ID::B); + SigSpec sig_a = cell->getPort(TW::A); + SigSpec sig_b = cell->getPort(TW::B); State init_y = State::S1; @@ -246,21 +246,21 @@ struct InitValWorker } else if (cell->type == ID($mux)) { - State init_s = initconst(cell->getPort(ID::S).as_bit()); + State init_s = initconst(cell->getPort(TW::S).as_bit()); if (init_s == State::S0 && portbit.port == ID::B) continue; if (init_s == State::S1 && portbit.port == ID::A) continue; - auto sig_y = cell->getPort(ID::Y); + auto sig_y = cell->getPort(TW::Y); if (is_initval_used(sig_y[portbit.offset])) return true; } else if (cell->type.in(ID($and), ID($or))) { - auto sig_a = cell->getPort(ID::A); - auto sig_b = cell->getPort(ID::B); - auto sig_y = cell->getPort(ID::Y); + auto sig_a = cell->getPort(TW::A); + auto sig_b = cell->getPort(TW::B); + auto sig_y = cell->getPort(TW::Y); if (GetSize(sig_y) != GetSize(sig_a) || GetSize(sig_y) != GetSize(sig_b)) return true; // TODO handle more of this State absorbing = cell->type == ID($and) ? State::S0 : State::S1; @@ -282,13 +282,13 @@ struct InitValWorker if (portbit.port == ID::WR_DATA) { - if (initconst(cell->getPort(ID::WR_EN)[portbit.offset]) == State::S0) + if (initconst(cell->getPort(TW::WR_EN)[portbit.offset]) == State::S0) continue; } else if (portbit.port == ID::WR_ADDR) { int port = portbit.offset / cell->getParam(ID::ABITS).as_int(); - auto sig_en = cell->getPort(ID::WR_EN); + auto sig_en = cell->getPort(TW::WR_EN); int width = cell->getParam(ID::WIDTH).as_int(); for (int i = port * width; i < (port + 1) * width; i++) @@ -300,7 +300,7 @@ struct InitValWorker else if (portbit.port == ID::RD_ADDR) { int port = portbit.offset / cell->getParam(ID::ABITS).as_int(); - auto sig_en = cell->getPort(ID::RD_EN); + auto sig_en = cell->getPort(TW::RD_EN); if (initconst(sig_en[port]) != State::S0) return true; @@ -369,8 +369,8 @@ struct PropagateWorker for (auto cell : module->cells()) { if (cell->type.in(ID($not), ID($_NOT_))) { - auto sig_a = cell->getPort(ID::A); - auto &sig_y = cell->getPort(ID::Y); + auto sig_a = cell->getPort(TW::A); + auto &sig_y = cell->getPort(TW::Y); sig_a.extend_u0(GetSize(sig_y), cell->hasParam(ID::A_SIGNED) && cell->parameters.at(ID::A_SIGNED).as_bool()); for (int i = 0; i < GetSize(sig_a); i++) @@ -445,7 +445,7 @@ struct PropagateWorker if (add_attribute) { Wire *clk_wire = bit.wire; if (bit.offset != 0 || GetSize(bit.wire) != 1) { - clk_wire = module->addWire(NEW_ID); + clk_wire = module->addWire(NEW_TWINE); module->connect(RTLIL::SigBit(clk_wire), bit); } clk_wire->attributes[ID::replaced_by_gclk] = polarity ? State::S1 : State::S0; @@ -717,8 +717,8 @@ struct FormalFfPass : public Pass { continue; } - SigBit gate_clock = sigmap(driver.cell->getPort(ID::A)[driver.offset]); - SigBit gate_enable = sigmap(driver.cell->getPort(ID::B)[driver.offset]); + SigBit gate_clock = sigmap(driver.cell->getPort(TW::A)[driver.offset]); + SigBit gate_enable = sigmap(driver.cell->getPort(TW::B)[driver.offset]); std::swap(gate_clock, gate_enable); for (int i = 0; i < 2; i++) { @@ -900,7 +900,7 @@ struct FormalFfPass : public Pass { auto clk_wire = ff.sig_clk.is_wire() ? ff.sig_clk.as_wire() : nullptr; if (clk_wire == nullptr) { - clk_wire = module->addWire(NEW_ID); + clk_wire = module->addWire(NEW_TWINE); module->connect(RTLIL::SigBit(clk_wire), ff.sig_clk); } diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index a76a57fc8..2f7f66293 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -632,7 +632,7 @@ struct FreduceWorker bits_full_total += outputs.size(); } if (inv_mode && cell->type == ID($_NOT_)) - inv_pairs.insert(std::pair(sigmap(cell->getPort(ID::A)), sigmap(cell->getPort(ID::Y)))); + inv_pairs.insert(std::pair(sigmap(cell->getPort(TW::A)), sigmap(cell->getPort(TW::Y)))); } int bits_count = 0; @@ -716,7 +716,7 @@ struct FreduceWorker log(" Connect slave%s: %s\n", grp[i].inverted ? " using inverter" : "", log_signal(grp[i].bit)); RTLIL::Cell *drv = drivers.at(grp[i].bit).first; - RTLIL::Wire *dummy_wire = module->addWire(NEW_ID); + RTLIL::Wire *dummy_wire = module->addWire(NEW_TWINE); for (auto &port : drv->connections_) if (ct.cell_output(drv->type, port.first)) sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second); @@ -725,11 +725,11 @@ struct FreduceWorker { if (inv_sig.size() == 0) { - inv_sig = module->addWire(NEW_ID); + inv_sig = module->addWire(NEW_TWINE); - RTLIL::Cell *inv_cell = module->addCell(NEW_ID, ID($_NOT_)); - inv_cell->setPort(ID::A, grp[0].bit); - inv_cell->setPort(ID::Y, inv_sig); + RTLIL::Cell *inv_cell = module->addCell(NEW_TWINE, ID($_NOT_)); + inv_cell->setPort(TW::A, grp[0].bit); + inv_cell->setPort(TW::Y, inv_sig); } module->connect(RTLIL::SigSig(grp[i].bit, inv_sig)); diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 411032f56..522fb6205 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -147,7 +147,7 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: SigSpec w = miter_module->addWire("\\cross_" + gold_wire->name.unescape(), gold_wire->width); gold_cell->setPort(gold_wire->name, w); if (flag_ignore_gold_x) { - RTLIL::SigSpec w_x = miter_module->addWire(NEW_ID, GetSize(w)); + RTLIL::SigSpec w_x = miter_module->addWire(NEW_TWINE, GetSize(w)); for (int i = 0; i < GetSize(w); i++) miter_module->addEqx(NEW_ID, w[i], State::Sx, w_x[i]); RTLIL::SigSpec w_any = miter_module->And(NEW_ID, miter_module->Anyseq(NEW_ID, GetSize(w)), w_x); @@ -182,65 +182,65 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: if (flag_ignore_gold_x) { - RTLIL::SigSpec gold_x = miter_module->addWire(NEW_ID, w_gold->width); + RTLIL::SigSpec gold_x = miter_module->addWire(NEW_TWINE, w_gold->width); for (int i = 0; i < w_gold->width; i++) { - RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_ID, ID($eqx)); + RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_TWINE, ID($eqx)); eqx_cell->parameters[ID::A_WIDTH] = 1; eqx_cell->parameters[ID::B_WIDTH] = 1; eqx_cell->parameters[ID::Y_WIDTH] = 1; eqx_cell->parameters[ID::A_SIGNED] = 0; eqx_cell->parameters[ID::B_SIGNED] = 0; - eqx_cell->setPort(ID::A, RTLIL::SigSpec(w_gold, i)); - eqx_cell->setPort(ID::B, RTLIL::State::Sx); - eqx_cell->setPort(ID::Y, gold_x.extract(i, 1)); + eqx_cell->setPort(TW::A, RTLIL::SigSpec(w_gold, i)); + eqx_cell->setPort(TW::B, RTLIL::State::Sx); + eqx_cell->setPort(TW::Y, gold_x.extract(i, 1)); } - RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w_gold->width); - RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_ID, w_gate->width); + RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_TWINE, w_gold->width); + RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_TWINE, w_gate->width); - RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_ID, ID($or)); + RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_TWINE, ID($or)); or_gold_cell->parameters[ID::A_WIDTH] = w_gold->width; or_gold_cell->parameters[ID::B_WIDTH] = w_gold->width; or_gold_cell->parameters[ID::Y_WIDTH] = w_gold->width; or_gold_cell->parameters[ID::A_SIGNED] = 0; or_gold_cell->parameters[ID::B_SIGNED] = 0; - or_gold_cell->setPort(ID::A, w_gold); - or_gold_cell->setPort(ID::B, gold_x); - or_gold_cell->setPort(ID::Y, gold_masked); + or_gold_cell->setPort(TW::A, w_gold); + or_gold_cell->setPort(TW::B, gold_x); + or_gold_cell->setPort(TW::Y, gold_masked); - RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, ID($or)); + RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_TWINE, ID($or)); or_gate_cell->parameters[ID::A_WIDTH] = w_gate->width; or_gate_cell->parameters[ID::B_WIDTH] = w_gate->width; or_gate_cell->parameters[ID::Y_WIDTH] = w_gate->width; or_gate_cell->parameters[ID::A_SIGNED] = 0; or_gate_cell->parameters[ID::B_SIGNED] = 0; - or_gate_cell->setPort(ID::A, w_gate); - or_gate_cell->setPort(ID::B, gold_x); - or_gate_cell->setPort(ID::Y, gate_masked); + or_gate_cell->setPort(TW::A, w_gate); + or_gate_cell->setPort(TW::B, gold_x); + or_gate_cell->setPort(TW::Y, gate_masked); - RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, ID($eqx)); + RTLIL::Cell *eq_cell = miter_module->addCell(NEW_TWINE, ID($eqx)); eq_cell->parameters[ID::A_WIDTH] = w_gold->width; eq_cell->parameters[ID::B_WIDTH] = w_gate->width; eq_cell->parameters[ID::Y_WIDTH] = 1; eq_cell->parameters[ID::A_SIGNED] = 0; eq_cell->parameters[ID::B_SIGNED] = 0; - eq_cell->setPort(ID::A, gold_masked); - eq_cell->setPort(ID::B, gate_masked); - eq_cell->setPort(ID::Y, miter_module->addWire(NEW_ID)); - this_condition = eq_cell->getPort(ID::Y); + eq_cell->setPort(TW::A, gold_masked); + eq_cell->setPort(TW::B, gate_masked); + eq_cell->setPort(TW::Y, miter_module->addWire(NEW_TWINE)); + this_condition = eq_cell->getPort(TW::Y); } else { - RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, ID($eqx)); + RTLIL::Cell *eq_cell = miter_module->addCell(NEW_TWINE, ID($eqx)); eq_cell->parameters[ID::A_WIDTH] = w_gold->width; eq_cell->parameters[ID::B_WIDTH] = w_gate->width; eq_cell->parameters[ID::Y_WIDTH] = 1; eq_cell->parameters[ID::A_SIGNED] = 0; eq_cell->parameters[ID::B_SIGNED] = 0; - eq_cell->setPort(ID::A, w_gold); - eq_cell->setPort(ID::B, w_gate); - eq_cell->setPort(ID::Y, miter_module->addWire(NEW_ID)); - this_condition = eq_cell->getPort(ID::Y); + eq_cell->setPort(TW::A, w_gold); + eq_cell->setPort(TW::B, w_gate); + eq_cell->setPort(TW::Y, miter_module->addWire(NEW_TWINE)); + this_condition = eq_cell->getPort(TW::Y); } if (flag_make_outcmp) @@ -261,31 +261,31 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: } if (all_conditions.size() != 1) { - RTLIL::Cell *reduce_cell = miter_module->addCell(NEW_ID, ID($reduce_and)); + RTLIL::Cell *reduce_cell = miter_module->addCell(NEW_TWINE, ID($reduce_and)); reduce_cell->parameters[ID::A_WIDTH] = all_conditions.size(); reduce_cell->parameters[ID::Y_WIDTH] = 1; reduce_cell->parameters[ID::A_SIGNED] = 0; - reduce_cell->setPort(ID::A, all_conditions); - reduce_cell->setPort(ID::Y, miter_module->addWire(NEW_ID)); - all_conditions = reduce_cell->getPort(ID::Y); + reduce_cell->setPort(TW::A, all_conditions); + reduce_cell->setPort(TW::Y, miter_module->addWire(NEW_TWINE)); + all_conditions = reduce_cell->getPort(TW::Y); } if (flag_make_assert) { - RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, ID($assert)); - assert_cell->setPort(ID::A, all_conditions); - assert_cell->setPort(ID::EN, State::S1); + RTLIL::Cell *assert_cell = miter_module->addCell(NEW_TWINE, ID($assert)); + assert_cell->setPort(TW::A, all_conditions); + assert_cell->setPort(TW::EN, State::S1); } RTLIL::Wire *w_trigger = miter_module->addWire(ID(trigger)); w_trigger->port_output = true; - RTLIL::Cell *not_cell = miter_module->addCell(NEW_ID, ID($not)); + RTLIL::Cell *not_cell = miter_module->addCell(NEW_TWINE, ID($not)); not_cell->parameters[ID::A_WIDTH] = all_conditions.size(); not_cell->parameters[ID::A_WIDTH] = all_conditions.size(); not_cell->parameters[ID::Y_WIDTH] = w_trigger->width; not_cell->parameters[ID::A_SIGNED] = 0; - not_cell->setPort(ID::A, all_conditions); - not_cell->setPort(ID::Y, w_trigger); + not_cell->setPort(TW::A, all_conditions); + not_cell->setPort(TW::Y, w_trigger); miter_module->fixup_ports(); @@ -356,8 +356,8 @@ void create_miter_assert(struct Pass *that, std::vector args, RTLIL if (!cell->type.in(ID($assert), ID($assume))) continue; - SigBit is_active = module->Nex(NEW_ID, cell->getPort(ID::A), State::S1); - SigBit is_enabled = module->Eqx(NEW_ID, cell->getPort(ID::EN), State::S1); + SigBit is_active = module->Nex(NEW_ID, cell->getPort(TW::A), State::S1); + SigBit is_enabled = module->Eqx(NEW_ID, cell->getPort(TW::EN), State::S1); if (cell->type == ID($assert)) { assert_signals.append(module->And(NEW_ID, is_active, is_enabled)); @@ -374,7 +374,7 @@ void create_miter_assert(struct Pass *that, std::vector args, RTLIL } else { - Wire *assume_q = module->addWire(NEW_ID); + Wire *assume_q = module->addWire(NEW_TWINE); assume_q->attributes[ID::init] = State::S0; assume_signals.append(assume_q); diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc index 687b035fd..eef56e7e1 100644 --- a/passes/sat/mutate.cc +++ b/passes/sat/mutate.cc @@ -659,7 +659,7 @@ void mutate_inv(Design *design, const mutate_opts_t &opts) else { log("Add output inverter at %s.%s.%s[%d].\n", module, cell, opts.port.unescape(), opts.portbit); - SigBit inbit = module->addWire(NEW_ID); + SigBit inbit = module->addWire(NEW_TWINE); SigBit outbit = module->Not(NEW_ID, inbit); module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit)); bit = inbit; @@ -687,7 +687,7 @@ void mutate_const(Design *design, const mutate_opts_t &opts, bool one) else { log("Add output constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit); - SigBit inbit = module->addWire(NEW_ID); + SigBit inbit = module->addWire(NEW_TWINE); SigBit outbit = one ? State::S1 : State::S0; module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit)); bit = inbit; @@ -716,7 +716,7 @@ void mutate_cnot(Design *design, const mutate_opts_t &opts, bool one) else { log("Add output cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit, opts.ctrlbit); - SigBit inbit = module->addWire(NEW_ID); + SigBit inbit = module->addWire(NEW_TWINE); SigBit outbit = one ? module->Xor(NEW_ID, inbit, ctrl) : module->Xnor(NEW_ID, inbit, ctrl); module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit)); bit = inbit; diff --git a/passes/sat/qbfsat.cc b/passes/sat/qbfsat.cc index f9619869b..e3d3cc59a 100644 --- a/passes/sat/qbfsat.cc +++ b/passes/sat/qbfsat.cc @@ -111,7 +111,7 @@ void specialize_from_file(RTLIL::Module *module, const std::string &file) { log_cmd_error("cannot find matching wire name or $anyconst cell location for hole spec \"%s\"\n", buf); RTLIL::Cell *hole_cell = hole_cell_it->second; - hole_sigbit = hole_cell->getPort(ID::Y)[hole_bit]; + hole_sigbit = hole_cell->getPort(TW::Y)[hole_bit]; } hole_assignments[hole_sigbit] = hole_value; } @@ -165,7 +165,7 @@ void allconstify_inputs(RTLIL::Module *module, const pool &input_wi RTLIL::Cell *allconst = module->addCell("$allconst$" + n, "$allconst"); allconst->setParam(ID(WIDTH), input->width); - allconst->setPort(ID::Y, input); + allconst->setPort(TW::Y, input); allconst->adopt_src_from(input); input->port_input = false; log("Replaced input %s with $allconst cell.\n", n); diff --git a/passes/sat/qbfsat.h b/passes/sat/qbfsat.h index 4045fec22..e456bfc7c 100644 --- a/passes/sat/qbfsat.h +++ b/passes/sat/qbfsat.h @@ -69,7 +69,7 @@ struct QbfSolutionType { pool cell_src = module->design->src_leaves(cell); auto pos = hole_to_value.find(cell_src); if (pos != hole_to_value.end() && cell->type.in("$anyconst", "$anyseq")) { - RTLIL::SigSpec port_y = cell->getPort(ID::Y); + RTLIL::SigSpec port_y = cell->getPort(TW::Y); for (int i = GetSize(port_y) - 1; i >= 0; --i) { hole_loc_idx_to_sigbit[std::make_pair(pos->first, i)] = port_y[i]; anyconst_sigbits.insert(port_y[i]); @@ -125,7 +125,7 @@ struct QbfSolutionType { //There is a question here: How exactly shall we identify holes? //There are at least two reasonable options: //1. By the source location of the $anyconst cells - //2. By the name(s) of the wire(s) connected to each SigBit of the $anyconst cell->getPort(ID::Y) SigSpec. + //2. By the name(s) of the wire(s) connected to each SigBit of the $anyconst cell->getPort(TW::Y) SigSpec. // //Option 1 has the benefit of being very precise. There is very limited potential for confusion, as long //as the source attribute has been set. However, if the source attribute is not set, this won't work. @@ -143,7 +143,7 @@ struct QbfSolutionType { // //where '[', ']', and '=' are literal symbols, "location" is the $anyconst cell source location attribute, //"bit" is the index of the $anyconst cell, "name" is the `wire->name` field of the SigBit corresponding - //to the current bit of the $anyconst cell->getPort(ID::Y), "offset" is the `offset` field of that same + //to the current bit of the $anyconst cell->getPort(TW::Y), "offset" is the `offset` field of that same //SigBit, and "value", which is either '0' or '1', represents the assignment for that bit. auto hole_loc_idx_to_sigbit = get_hole_loc_idx_sigbit_map(module); for (auto &x : hole_to_value) { diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index b1826dc85..8236cfea0 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -268,7 +268,7 @@ struct SatHelper if (set_init_undef && satgen.def_formal) for (auto cell : module->cells()) if (cell->type == ID($anyinit)) - forced_def.append(sigmap(cell->getPort(ID::Q))); + forced_def.append(sigmap(cell->getPort(TW::Q))); for (auto wire : module->wires()) { @@ -1409,7 +1409,7 @@ struct SatPass : public Pass { pool reg_wires; for (auto cell : module->cells()) { if (cell->type == ID($dff) || cell->type.begins_with("$_DFF_")) - for (auto bit : cell->getPort(ID::Q)) + for (auto bit : cell->getPort(TW::Q)) if (bit.wire) reg_wires.insert(bit.wire); } diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 19712a23d..10efe497b 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -208,7 +208,7 @@ struct SimInstance { return std::make_tuple( cell->getParam(ID::TRG_ENABLE).as_bool(), // Group by trigger - cell->getPort(ID::TRG), + cell->getPort(TW::TRG), cell->getParam(ID::TRG_POLARITY), -cell->getParam(ID::PRIORITY).as_int(), // Then sort by descending PRIORITY cell @@ -365,8 +365,8 @@ struct SimInstance auto &print = print_database.back(); print.cell = cell; print.fmt.parse_rtlil(cell); - print.past_trg = Const(State::Sx, cell->getPort(ID::TRG).size()); - print.past_args = Const(State::Sx, cell->getPort(ID::ARGS).size()); + print.past_trg = Const(State::Sx, cell->getPort(TW::TRG).size()); + print.past_args = Const(State::Sx, cell->getPort(TW::ARGS).size()); print.past_en = State::Sx; print.initial_done = false; } @@ -565,12 +565,12 @@ struct SimInstance has_s = cell->hasPort(ID::S); has_y = cell->hasPort(ID::Y); - if (has_a) sig_a = cell->getPort(ID::A); - if (has_b) sig_b = cell->getPort(ID::B); - if (has_c) sig_c = cell->getPort(ID::C); - if (has_d) sig_d = cell->getPort(ID::D); - if (has_s) sig_s = cell->getPort(ID::S); - if (has_y) sig_y = cell->getPort(ID::Y); + if (has_a) sig_a = cell->getPort(TW::A); + if (has_b) sig_b = cell->getPort(TW::B); + if (has_c) sig_c = cell->getPort(TW::C); + if (has_d) sig_d = cell->getPort(TW::D); + if (has_s) sig_s = cell->getPort(TW::S); + if (has_y) sig_y = cell->getPort(TW::Y); if (shared->debug) log("[%s] eval %s (%s)\n", hiername(), cell, cell->type.unescape()); @@ -875,10 +875,10 @@ struct SimInstance Cell *cell = print.cell; bool triggered = false; - Const trg = get_state(cell->getPort(ID::TRG)); + Const trg = get_state(cell->getPort(TW::TRG)); bool trg_en = cell->getParam(ID::TRG_ENABLE).as_bool(); - Const en = get_state(cell->getPort(ID::EN)); - Const args = get_state(cell->getPort(ID::ARGS)); + Const en = get_state(cell->getPort(TW::EN)); + Const args = get_state(cell->getPort(TW::ARGS)); bool sampled = trg_en && trg.size() > 0; @@ -934,8 +934,8 @@ struct SimInstance if (cell->has_attribute(ID::src)) label = cell->get_src_attribute(); - State a = get_state(cell->getPort(ID::A))[0]; - State en = get_state(cell->getPort(ID::EN))[0]; + State a = get_state(cell->getPort(TW::A))[0]; + State en = get_state(cell->getPort(TW::EN))[0]; if (en == State::S1 && (cell->type == ID($cover) ? a == State::S1 : a != State::S1)) { shared->triggered_assertions.emplace_back(shared->step, this, cell); @@ -964,7 +964,7 @@ struct SimInstance void set_initstate_outputs(State state) { for (auto cell : initstate_database) - set_state(cell->getPort(ID::Y), state); + set_state(cell->getPort(TW::Y), state); for (auto child : children) child.second->set_initstate_outputs(state); } @@ -1200,7 +1200,7 @@ struct SimInstance for (auto cell : module->cells()) { if (cell->type.in(ID($anyseq))) { - SigSpec sig_y = sigmap(cell->getPort(ID::Y)); + SigSpec sig_y = sigmap(cell->getPort(TW::Y)); if (sig_y.is_wire()) { bool found = false; for(auto &item : fst_handles) { @@ -1834,7 +1834,7 @@ struct SimWorker : SimShared if (!c) log_warning("Wire/cell %s not present in module %s\n",escaped_s.unescape(),topmod); else if (c->type.in(ID($anyconst), ID($anyseq))) { - SigSpec sig_y= c->getPort(ID::Y); + SigSpec sig_y= c->getPort(TW::Y); if ((int)parts[1].size() != GetSize(sig_y)) log_error("Size of wire %s is different than provided data.\n", log_signal(sig_y)); top->set_state(sig_y, Const::from_string(parts[1])); diff --git a/passes/sat/synthprop.cc b/passes/sat/synthprop.cc index a54eef199..e41582c23 100644 --- a/passes/sat/synthprop.cc +++ b/passes/sat/synthprop.cc @@ -107,16 +107,16 @@ void SynthPropWorker::run() int num = 0; RTLIL::Wire *port_wire = data.first->wire(port_name); if (!reset_name.empty() && data.first == module) { - port_wire = data.first->addWire(NEW_ID, data.second.names.size()); + port_wire = data.first->addWire(NEW_TWINE, data.second.names.size()); output = port_wire; } pool connected; for (auto cell : data.second.assertion_cells) { if (cell->type == ID($assert)) { - RTLIL::Wire *neg_wire = data.first->addWire(NEW_ID); - RTLIL::Wire *result_wire = data.first->addWire(NEW_ID); - data.first->addNot(NEW_ID, cell->getPort(ID::A), neg_wire); - data.first->addAnd(NEW_ID, cell->getPort(ID::EN), neg_wire, result_wire); + RTLIL::Wire *neg_wire = data.first->addWire(NEW_TWINE); + RTLIL::Wire *result_wire = data.first->addWire(NEW_TWINE); + data.first->addNot(NEW_ID, cell->getPort(TW::A), neg_wire); + data.first->addAnd(NEW_ID, cell->getPort(TW::EN), neg_wire, result_wire); if (!or_outputs) { data.first->connect(SigBit(port_wire,num), result_wire); } else { @@ -132,7 +132,7 @@ void SynthPropWorker::run() if (!or_outputs) { cell->setPort(port_name, SigChunk(port_wire, num, tracing_data[submod].names.size())); } else { - RTLIL::Wire *result_wire = data.first->addWire(NEW_ID); + RTLIL::Wire *result_wire = data.first->addWire(NEW_TWINE); cell->setPort(port_name, result_wire); connected.emplace(result_wire); } @@ -146,7 +146,7 @@ void SynthPropWorker::run() if (!prev_wire) { prev_wire = wire; } else { - RTLIL::Wire *result = data.first->addWire(NEW_ID); + RTLIL::Wire *result = data.first->addWire(NEW_TWINE); data.first->addOr(NEW_ID, prev_wire, wire, result); prev_wire = result; } diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index d45586642..b4085f17e 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -476,8 +476,8 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo if (cell->type.in(ID($_BUF_), ID($_NOT_))) { - RTLIL::SigSpec sig_a = cell->getPort(ID::A); - RTLIL::SigSpec sig_y = cell->getPort(ID::Y); + RTLIL::SigSpec sig_a = cell->getPort(TW::A); + RTLIL::SigSpec sig_y = cell->getPort(TW::Y); assign_map.apply(sig_a); assign_map.apply(sig_y); @@ -490,9 +490,9 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_))) { - RTLIL::SigSpec sig_a = cell->getPort(ID::A); - RTLIL::SigSpec sig_b = cell->getPort(ID::B); - RTLIL::SigSpec sig_y = cell->getPort(ID::Y); + RTLIL::SigSpec sig_a = cell->getPort(TW::A); + RTLIL::SigSpec sig_b = cell->getPort(TW::B); + RTLIL::SigSpec sig_y = cell->getPort(TW::Y); assign_map.apply(sig_a); assign_map.apply(sig_b); @@ -526,10 +526,10 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo if (cell->type.in(ID($_MUX_), ID($_NMUX_))) { - RTLIL::SigSpec sig_a = cell->getPort(ID::A); - RTLIL::SigSpec sig_b = cell->getPort(ID::B); - RTLIL::SigSpec sig_s = cell->getPort(ID::S); - RTLIL::SigSpec sig_y = cell->getPort(ID::Y); + RTLIL::SigSpec sig_a = cell->getPort(TW::A); + RTLIL::SigSpec sig_b = cell->getPort(TW::B); + RTLIL::SigSpec sig_s = cell->getPort(TW::S); + RTLIL::SigSpec sig_y = cell->getPort(TW::Y); assign_map.apply(sig_a); assign_map.apply(sig_b); @@ -548,10 +548,10 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo if (cell->type.in(ID($_AOI3_), ID($_OAI3_))) { - RTLIL::SigSpec sig_a = cell->getPort(ID::A); - RTLIL::SigSpec sig_b = cell->getPort(ID::B); - RTLIL::SigSpec sig_c = cell->getPort(ID::C); - RTLIL::SigSpec sig_y = cell->getPort(ID::Y); + RTLIL::SigSpec sig_a = cell->getPort(TW::A); + RTLIL::SigSpec sig_b = cell->getPort(TW::B); + RTLIL::SigSpec sig_c = cell->getPort(TW::C); + RTLIL::SigSpec sig_y = cell->getPort(TW::Y); assign_map.apply(sig_a); assign_map.apply(sig_b); @@ -570,11 +570,11 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo if (cell->type.in(ID($_AOI4_), ID($_OAI4_))) { - RTLIL::SigSpec sig_a = cell->getPort(ID::A); - RTLIL::SigSpec sig_b = cell->getPort(ID::B); - RTLIL::SigSpec sig_c = cell->getPort(ID::C); - RTLIL::SigSpec sig_d = cell->getPort(ID::D); - RTLIL::SigSpec sig_y = cell->getPort(ID::Y); + RTLIL::SigSpec sig_a = cell->getPort(TW::A); + RTLIL::SigSpec sig_b = cell->getPort(TW::B); + RTLIL::SigSpec sig_c = cell->getPort(TW::C); + RTLIL::SigSpec sig_d = cell->getPort(TW::D); + RTLIL::SigSpec sig_y = cell->getPort(TW::Y); assign_map.apply(sig_a); assign_map.apply(sig_b); @@ -1568,7 +1568,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL cell_stats[c->type.unescape()]++; if (c->type.in(ID(ZERO), ID(ONE))) { RTLIL::SigSig conn; - RTLIL::IdString name_y = remap_name(c->getPort(ID::Y).as_wire()->name); + RTLIL::IdString name_y = remap_name(c->getPort(TW::Y).as_wire()->name); conn.first = module->wire(name_y); conn.second = RTLIL::SigSpec(c->type == ID(ZERO) ? 0 : 1, 1); connect(assign_map, module, conn); @@ -1576,8 +1576,8 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL } if (c->type == ID(BUF)) { RTLIL::SigSig conn; - RTLIL::IdString name_y = remap_name(c->getPort(ID::Y).as_wire()->name); - RTLIL::IdString name_a = remap_name(c->getPort(ID::A).as_wire()->name); + RTLIL::IdString name_y = remap_name(c->getPort(TW::Y).as_wire()->name); + RTLIL::IdString name_a = remap_name(c->getPort(TW::A).as_wire()->name); conn.first = module->wire(name_y); conn.second = module->wire(name_a); connect(assign_map, module, conn); @@ -1678,7 +1678,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL ff.pol_ce = en_polarity; ff.sig_ce = en_sig; } - RTLIL::Const init = mapped_initvals(c->getPort(ID::Q)); + RTLIL::Const init = mapped_initvals(c->getPort(TW::Q)); if (had_init) ff.val_init = init; else @@ -1697,8 +1697,8 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL ff.sig_srst = srst_sig; ff.val_srst = init; } - ff.sig_d = module->wire(remap_name(c->getPort(ID::D).as_wire()->name)); - ff.sig_q = module->wire(remap_name(c->getPort(ID::Q).as_wire()->name)); + ff.sig_d = module->wire(remap_name(c->getPort(TW::D).as_wire()->name)); + ff.sig_q = module->wire(remap_name(c->getPort(TW::Q).as_wire()->name)); RTLIL::Cell *cell = ff.emit(); if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx; design->select(module, cell); @@ -1729,7 +1729,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL ff.pol_ce = en_polarity; ff.sig_ce = en_sig; } - RTLIL::Const init = mapped_initvals(c->getPort(ID::Q)); + RTLIL::Const init = mapped_initvals(c->getPort(TW::Q)); if (had_init) ff.val_init = init; else @@ -1746,17 +1746,17 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL ff.sig_srst = srst_sig; ff.val_srst = init; } - ff.sig_d = module->wire(remap_name(c->getPort(ID::D).as_wire()->name)); - ff.sig_q = module->wire(remap_name(c->getPort(ID::Q).as_wire()->name)); + ff.sig_d = module->wire(remap_name(c->getPort(TW::D).as_wire()->name)); + ff.sig_q = module->wire(remap_name(c->getPort(TW::Q).as_wire()->name)); RTLIL::Cell *cell = ff.emit(); if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx; design->select(module, cell); continue; } - if (c->type == ID($lut) && GetSize(c->getPort(ID::A)) == 1 && c->getParam(ID::LUT).as_int() == 2) { - SigSpec my_a = module->wire(remap_name(c->getPort(ID::A).as_wire()->name)); - SigSpec my_y = module->wire(remap_name(c->getPort(ID::Y).as_wire()->name)); + if (c->type == ID($lut) && GetSize(c->getPort(TW::A)) == 1 && c->getParam(ID::LUT).as_int() == 2) { + SigSpec my_a = module->wire(remap_name(c->getPort(TW::A).as_wire()->name)); + SigSpec my_y = module->wire(remap_name(c->getPort(TW::Y).as_wire()->name)); connect(assign_map, module, RTLIL::SigSig(my_a, my_y)); continue; } diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 0dd208307..2eef5936c 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -132,7 +132,7 @@ void check(RTLIL::Design *design, bool dff_mode) log_error("Whitebox '%s' with (* abc9_flop *) contains more than one $_DFF_[NP]_ cell.\n", derived_module); found = true; - SigBit Q = derived_cell->getPort(ID::Q); + SigBit Q = derived_cell->getPort(TW::Q); log_assert(GetSize(Q.wire) == 1); if (!Q.wire->port_output) @@ -209,7 +209,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode) if (derived_module->get_bool_attribute(ID::abc9_flop)) { for (auto derived_cell : derived_module->cells()) if (derived_cell->type.in(ID($dff), ID($_DFF_N_), ID($_DFF_P_))) { - SigBit Q = derived_cell->getPort(ID::Q); + SigBit Q = derived_cell->getPort(TW::Q); Const init = Q.wire->attributes.at(ID::init, State::Sx); log_assert(GetSize(init) == 1); @@ -344,10 +344,10 @@ void prep_bypass(RTLIL::Design *design) // For these new input ports driven by the replaced // cell, then create a new simple-path specify entry: // (input => output) = 0 - auto specify = bypass_module->addCell(NEW_ID, ID($specify2)); - specify->setPort(ID::EN, State::S1); - specify->setPort(ID::SRC, src); - specify->setPort(ID::DST, dst); + auto specify = bypass_module->addCell(NEW_TWINE, ID($specify2)); + specify->setPort(TW::EN, State::S1); + specify->setPort(TW::SRC, src); + specify->setPort(TW::DST, dst); specify->setParam(ID::FULL, 0); specify->setParam(ID::SRC_WIDTH, GetSize(src)); specify->setParam(ID::DST_WIDTH, GetSize(dst)); @@ -371,11 +371,11 @@ void prep_bypass(RTLIL::Design *design) for (auto cell : inst_module->cells()) { if (cell->type != ID($specify2)) continue; - auto EN = cell->getPort(ID::EN).as_bit(); + auto EN = cell->getPort(TW::EN).as_bit(); SigBit newEN; if (!EN.wire && EN != State::S1) continue; - auto SRC = cell->getPort(ID::SRC); + auto SRC = cell->getPort(TW::SRC); for (const auto &c : SRC.chunks()) if (c.wire && !c.wire->port_input) { SRC = SigSpec(); @@ -383,7 +383,7 @@ void prep_bypass(RTLIL::Design *design) } if (SRC.empty()) continue; - auto DST = cell->getPort(ID::DST); + auto DST = cell->getPort(TW::DST); for (const auto &c : DST.chunks()) if (c.wire && !c.wire->port_output) { DST = SigSpec(); @@ -405,7 +405,7 @@ void prep_bypass(RTLIL::Design *design) } sig = std::move(new_sig); }; - auto specify = bypass_module->addCell(NEW_ID, cell); + auto specify = bypass_module->addCell(NEW_TWINE, cell); specify->rewrite_sigspecs(rw); } bypass_module->fixup_ports(); @@ -415,7 +415,7 @@ void prep_bypass(RTLIL::Design *design) // original cell, but with additional inputs taken from the // replaced cell auto replace_cell = map_module->addCell(ID::_TECHMAP_REPLACE_, cell->type); - auto bypass_cell = map_module->addCell(NEW_ID, cell->type.str() + "_$abc9_byp"); + auto bypass_cell = map_module->addCell(NEW_TWINE, cell->type.str() + "_$abc9_byp"); for (const auto &conn : cell->connections()) { auto port = map_module->wire(conn.first); if (cell->input(conn.first)) { @@ -493,7 +493,7 @@ void prep_dff_submod(RTLIL::Design *design) if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) { log_assert(!dff_cell); dff_cell = cell; - Q = cell->getPort(ID::Q); + Q = cell->getPort(TW::Q); log_assert(GetSize(Q.wire) == 1); } else if (cell->type.in(ID($specify3), ID($specrule))) @@ -503,17 +503,17 @@ void prep_dff_submod(RTLIL::Design *design) // Add an always-enabled CE mux that drives $_DFF_[NP]_.D so that: // (a) flop box will have an output // (b) $_DFF_[NP]_.Q will be present as an input - SigBit D = module->addWire(NEW_ID); - module->addMuxGate(NEW_ID, dff_cell->getPort(ID::D), Q, State::S0, D); - dff_cell->setPort(ID::D, D); + SigBit D = module->addWire(NEW_TWINE); + module->addMuxGate(NEW_ID, dff_cell->getPort(TW::D), Q, State::S0, D); + dff_cell->setPort(TW::D, D); // Rewrite $specify cells that end with $_DFF_[NP]_.Q // to $_DFF_[NP]_.D since it will be moved into // the submodule for (auto cell : specify_cells) { - auto DST = cell->getPort(ID::DST); + auto DST = cell->getPort(TW::DST); DST.replace(Q, D); - cell->setPort(ID::DST, DST); + cell->setPort(TW::DST, DST); } design->scratchpad_set_bool("abc9_ops.prep_dff_submod.did_something", true); @@ -593,7 +593,7 @@ void break_scc(RTLIL::Module *module) for (auto &c : cell->connections_) { if (c.second.is_fully_const()) continue; if (cell->output(c.first)) { - Wire *w = module->addWire(NEW_ID, GetSize(c.second)); + Wire *w = module->addWire(NEW_TWINE, GetSize(c.second)); I.append(w); O.append(c.second); c.second = w; @@ -603,11 +603,11 @@ void break_scc(RTLIL::Module *module) if (!I.empty()) { - auto cell = module->addCell(NEW_ID, ID($__ABC9_SCC_BREAKER)); + auto cell = module->addCell(NEW_TWINE, ID($__ABC9_SCC_BREAKER)); log_assert(GetSize(I) == GetSize(O)); cell->setParam(ID::WIDTH, GetSize(I)); - cell->setPort(ID::I, std::move(I)); - cell->setPort(ID::O, std::move(O)); + cell->setPort(TW::I, std::move(I)); + cell->setPort(TW::O, std::move(O)); } } @@ -681,7 +681,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode) auto rhs = cell->getPort(i.first.name); if (offset >= rhs.size()) continue; - auto O = module->addWire(NEW_ID); + auto O = module->addWire(NEW_TWINE); #ifndef NDEBUG if (ys_debug(1)) { @@ -695,9 +695,9 @@ void prep_delays(RTLIL::Design *design, bool dff_mode) r.first->second = delay_module->derive(design, {{ID::DELAY, d}}); log_assert(r.first->second.begins_with("$paramod$__ABC9_DELAY\\DELAY=")); } - auto box = module->addCell(NEW_ID, r.first->second); - box->setPort(ID::I, rhs[offset]); - box->setPort(ID::O, O); + auto box = module->addCell(NEW_TWINE, r.first->second); + box->setPort(TW::I, rhs[offset]); + box->setPort(TW::O, O); rhs[offset] = O; cell->setPort(i.first.name, rhs); } @@ -819,7 +819,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff) for (auto &c : cell->connections_) { if (c.second.is_fully_const()) continue; if (cell->output(c.first)) { - Wire *w = module->addWire(NEW_ID, GetSize(c.second)); + Wire *w = module->addWire(NEW_TWINE, GetSize(c.second)); I.append(w); O.append(c.second); c.second = w; @@ -828,11 +828,11 @@ void prep_xaiger(RTLIL::Module *module, bool dff) } if (!I.empty()) { - auto cell = module->addCell(NEW_ID, ID($__ABC9_SCC_BREAKER)); + auto cell = module->addCell(NEW_TWINE, ID($__ABC9_SCC_BREAKER)); log_assert(GetSize(I) == GetSize(O)); cell->setParam(ID::WIDTH, GetSize(I)); - cell->setPort(ID::I, std::move(I)); - cell->setPort(ID::O, std::move(O)); + cell->setPort(TW::I, std::move(I)); + cell->setPort(TW::O, std::move(O)); // Rebuild topo ordering after inserting the additional breakers. toposort.emplace(); @@ -891,7 +891,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff) auto &holes_cell = r.first->second; if (r.second) { if (box_module->get_bool_attribute(ID::whitebox)) { - holes_cell = holes_module->addCell(NEW_ID, cell->type); + holes_cell = holes_module->addCell(NEW_TWINE, cell->type); if (box_module->has_processes()) Pass::call_on_module(design, box_module, "proc -noopt"); @@ -1270,8 +1270,8 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) // $_DFF_[NP]_ cells since flop box already has all the information // we need to reconstruct them if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep)) { - SigBit Q = cell->getPort(ID::Q); - module->connect(Q, cell->getPort(ID::D)); + SigBit Q = cell->getPort(TW::Q); + module->connect(Q, cell->getPort(TW::D)); module->remove(cell); auto Qi = initmap(Q); auto it = Qi.wire->attributes.find(ID::init); @@ -1295,8 +1295,8 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) // Short out $_FF_ cells since the flop box already has // all the information we need to reconstruct cell if (dff_mode && mapped_cell->type == ID($_FF_)) { - SigBit D = mapped_cell->getPort(ID::D); - SigBit Q = mapped_cell->getPort(ID::Q); + SigBit D = mapped_cell->getPort(TW::D); + SigBit Q = mapped_cell->getPort(TW::Q); if (D.wire) D.wire = module->wire(remap_name(D.wire->name)); Q.wire = module->wire(remap_name(Q.wire->name)); @@ -1308,15 +1308,15 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) toposort.node(mapped_cell->name); if (mapped_cell->type == ID($_NOT_)) { - RTLIL::SigBit a_bit = mapped_cell->getPort(ID::A); - RTLIL::SigBit y_bit = mapped_cell->getPort(ID::Y); + RTLIL::SigBit a_bit = mapped_cell->getPort(TW::A); + RTLIL::SigBit y_bit = mapped_cell->getPort(TW::Y); bit_users[a_bit].insert(mapped_cell->name); // Ignore inouts for topo ordering if (y_bit.wire && !(y_bit.wire->port_input && y_bit.wire->port_output)) bit_drivers[y_bit].insert(mapped_cell->name); if (!a_bit.wire) { - mapped_cell->setPort(ID::Y, module->addWire(NEW_ID)); + mapped_cell->setPort(TW::Y, module->addWire(NEW_TWINE)); RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name)); log_assert(wire); module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1); @@ -1344,7 +1344,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) RTLIL::SigBit(module->wire(remap_name(a_bit.wire->name)), a_bit.offset), RTLIL::SigBit(module->wire(remap_name(y_bit.wire->name)), y_bit.offset), RTLIL::Const::from_string("01")); - bit2sinks[cell->getPort(ID::A)].push_back(cell); + bit2sinks[cell->getPort(TW::A)].push_back(cell); cell_stats[ID($lut)]++; } else @@ -1560,8 +1560,8 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) if (it == not2drivers.end()) continue; RTLIL::Cell *driver_lut = it->second; - RTLIL::SigBit a_bit = not_cell->getPort(ID::A); - RTLIL::SigBit y_bit = not_cell->getPort(ID::Y); + RTLIL::SigBit a_bit = not_cell->getPort(TW::A); + RTLIL::SigBit y_bit = not_cell->getPort(TW::Y); RTLIL::Const driver_mask; a_bit.wire = module->wire(remap_name(a_bit.wire->name)); @@ -1577,7 +1577,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) // Push downstream LUTs past inverter for (auto sink_cell : jt->second) { - SigSpec A = sink_cell->getPort(ID::A); + SigSpec A = sink_cell->getPort(TW::A); RTLIL::Const mask = sink_cell->getParam(ID::LUT); int index = 0; for (; index < GetSize(A); index++) @@ -1594,7 +1594,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) i += 1 << (index+1); } A[index] = y_bit; - sink_cell->setPort(ID::A, A); + sink_cell->setPort(TW::A, A); sink_cell->setParam(ID::LUT, mask); } @@ -1610,7 +1610,7 @@ clone_lut: else if (b == RTLIL::State::S1) b = RTLIL::State::S0; } auto cell = module->addLut(NEW_ID, - driver_lut->getPort(ID::A), + driver_lut->getPort(TW::A), y_bit, driver_mask); for (auto &bit : cell->connections_.at(ID::A)) { @@ -1636,7 +1636,7 @@ static void replace_zbufs(Design *design) for (auto cell : mod->cells()) { if (cell->type != ID($buf)) continue; - auto &sig = cell->getPort(ID::A); + auto &sig = cell->getPort(TW::A); for (int i = 0; i < GetSize(sig); ++i) { if (sig[i] == State::Sz) { zbufs.push_back(cell); @@ -1646,20 +1646,20 @@ static void replace_zbufs(Design *design) } for (auto cell : zbufs) { - auto sig = cell->getPort(ID::A); + auto sig = cell->getPort(TW::A); for (int i = 0; i < GetSize(sig); ++i) { if (sig[i] == State::Sz) { - Wire *w = mod->addWire(NEW_ID); - Cell *ud = mod->addCell(NEW_ID, ID($tribuf)); + Wire *w = mod->addWire(NEW_TWINE); + Cell *ud = mod->addCell(NEW_TWINE, ID($tribuf)); ud->set_bool_attribute(ID::aiger2_zbuf); ud->setParam(ID::WIDTH, 1); - ud->setPort(ID::Y, w); - ud->setPort(ID::EN, State::S0); - ud->setPort(ID::A, State::S0); + ud->setPort(TW::Y, w); + ud->setPort(TW::EN, State::S0); + ud->setPort(TW::A, State::S0); sig[i] = w; } } - cell->setPort(ID::A, sig); + cell->setPort(TW::A, sig); } mod->bufNormalize(); @@ -1680,7 +1680,7 @@ static void restore_zbufs(Design *design) to_remove.push_back(cell); for (auto cell : to_remove) { - SigSpec sig_y = cell->getPort(ID::Y); + SigSpec sig_y = cell->getPort(TW::Y); mod->addBuf(NEW_ID, Const(State::Sz, GetSize(sig_y)), sig_y); mod->remove(cell); } diff --git a/passes/techmap/aigmap.cc b/passes/techmap/aigmap.cc index 6b7e0c377..11ea76e3a 100644 --- a/passes/techmap/aigmap.cc +++ b/passes/techmap/aigmap.cc @@ -108,7 +108,7 @@ struct AigmapPass : public Pass { SigBit A = sigs.at(node.left_parent); SigBit B = sigs.at(node.right_parent); if (nand_mode && node.inverter) { - bit = module->addWire(NEW_ID); + bit = module->addWire(NEW_TWINE); auto gate = module->addNandGate(NEW_ID, A, B, bit); if (select_mode) new_sel.insert(gate->name); @@ -119,7 +119,7 @@ struct AigmapPass : public Pass { if (and_cache.count(key)) bit = and_cache.at(key); else { - bit = module->addWire(NEW_ID); + bit = module->addWire(NEW_TWINE); auto gate = module->addAndGate(NEW_ID, A, B, bit); if (select_mode) new_sel.insert(gate->name); @@ -128,7 +128,7 @@ struct AigmapPass : public Pass { } if (node.inverter) { - SigBit new_bit = module->addWire(NEW_ID); + SigBit new_bit = module->addWire(NEW_TWINE); auto gate = module->addNotGate(NEW_ID, bit, new_bit); bit = new_bit; if (select_mode) diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc index e3a96b622..d81bd98b6 100644 --- a/passes/techmap/alumacc.cc +++ b/passes/techmap/alumacc.cc @@ -89,7 +89,7 @@ struct AlumaccWorker RTLIL::SigSpec get_eq() { if (GetSize(cached_eq) == 0) - cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort(ID::X), false, alu_cell->src_ref()); + cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort(TW::X), false, alu_cell->src_ref()); return cached_eq; } @@ -101,7 +101,7 @@ struct AlumaccWorker RTLIL::SigSpec get_cf() { if (GetSize(cached_cf) == 0) { - cached_cf = alu_cell->getPort(ID::CO); + cached_cf = alu_cell->getPort(TW::CO); log_assert(GetSize(cached_cf) >= 1); cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->src_ref()); } @@ -110,7 +110,7 @@ struct AlumaccWorker RTLIL::SigSpec get_of() { if (GetSize(cached_of) == 0) { - cached_of = {alu_cell->getPort(ID::CO), alu_cell->getPort(ID::CI)}; + cached_of = {alu_cell->getPort(TW::CO), alu_cell->getPort(TW::CI)}; log_assert(GetSize(cached_of) >= 2); cached_of = alu_cell->module->Xor(NEW_ID, cached_of[GetSize(cached_of)-1], cached_of[GetSize(cached_of)-2]); } @@ -119,7 +119,7 @@ struct AlumaccWorker RTLIL::SigSpec get_sf() { if (GetSize(cached_sf) == 0) { - cached_sf = alu_cell->getPort(ID::Y); + cached_sf = alu_cell->getPort(TW::Y); cached_sf = cached_sf[GetSize(cached_sf)-1]; } return cached_sf; @@ -162,7 +162,7 @@ struct AlumaccWorker Macc::term_t new_term; n->cell = cell; - n->y = sigmap(cell->getPort(ID::Y)); + n->y = sigmap(cell->getPort(TW::Y)); n->users = 0; for (auto bit : n->y) @@ -170,7 +170,7 @@ struct AlumaccWorker if (cell->type.in(ID($pos), ID($neg))) { - new_term.in_a = sigmap(cell->getPort(ID::A)); + new_term.in_a = sigmap(cell->getPort(TW::A)); new_term.is_signed = cell->getParam(ID::A_SIGNED).as_bool(); new_term.do_subtract = cell->type == ID($neg); n->macc.terms.push_back(new_term); @@ -178,12 +178,12 @@ struct AlumaccWorker if (cell->type.in(ID($add), ID($sub))) { - new_term.in_a = sigmap(cell->getPort(ID::A)); + new_term.in_a = sigmap(cell->getPort(TW::A)); new_term.is_signed = cell->getParam(ID::A_SIGNED).as_bool(); new_term.do_subtract = false; n->macc.terms.push_back(new_term); - new_term.in_a = sigmap(cell->getPort(ID::B)); + new_term.in_a = sigmap(cell->getPort(TW::B)); new_term.is_signed = cell->getParam(ID::B_SIGNED).as_bool(); new_term.do_subtract = cell->type == ID($sub); n->macc.terms.push_back(new_term); @@ -191,8 +191,8 @@ struct AlumaccWorker if (cell->type.in(ID($mul))) { - new_term.in_a = sigmap(cell->getPort(ID::A)); - new_term.in_b = sigmap(cell->getPort(ID::B)); + new_term.in_a = sigmap(cell->getPort(TW::A)); + new_term.in_b = sigmap(cell->getPort(TW::B)); new_term.is_signed = cell->getParam(ID::A_SIGNED).as_bool(); new_term.do_subtract = false; n->macc.terms.push_back(new_term); @@ -379,7 +379,7 @@ struct AlumaccWorker for (auto &it : sig_macc) { auto n = it.second; - auto cell = module->addCell(NEW_ID, ID($macc)); + auto cell = module->addCell(NEW_TWINE, ID($macc)); macc_counter++; @@ -389,7 +389,7 @@ struct AlumaccWorker n->macc.optimize(GetSize(n->y)); n->macc.to_cell(cell); - cell->setPort(ID::Y, n->y); + cell->setPort(TW::Y, n->y); cell->fixup_parameters(); module->remove(n->cell); delete n; @@ -418,9 +418,9 @@ struct AlumaccWorker bool cmp_equal = cell->type.in(ID($le), ID($ge)); bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); - RTLIL::SigSpec A = sigmap(cell->getPort(ID::A)); - RTLIL::SigSpec B = sigmap(cell->getPort(ID::B)); - RTLIL::SigSpec Y = sigmap(cell->getPort(ID::Y)); + RTLIL::SigSpec A = sigmap(cell->getPort(TW::A)); + RTLIL::SigSpec B = sigmap(cell->getPort(TW::B)); + RTLIL::SigSpec Y = sigmap(cell->getPort(TW::Y)); alunode_t *n = nullptr; @@ -445,7 +445,7 @@ struct AlumaccWorker n->a = A; n->b = B; n->c = State::S1; - n->y = module->addWire(NEW_ID, max(GetSize(A), GetSize(B))); + n->y = module->addWire(NEW_TWINE, max(GetSize(A), GetSize(B))); n->is_signed = is_signed; n->invert_b = true; sig_alu[RTLIL::SigSig(A, B)].insert(n); @@ -463,9 +463,9 @@ struct AlumaccWorker bool cmp_equal = cell->type.in(ID($eq), ID($eqx)); bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); - RTLIL::SigSpec A = sigmap(cell->getPort(ID::A)); - RTLIL::SigSpec B = sigmap(cell->getPort(ID::B)); - RTLIL::SigSpec Y = sigmap(cell->getPort(ID::Y)); + RTLIL::SigSpec A = sigmap(cell->getPort(TW::A)); + RTLIL::SigSpec B = sigmap(cell->getPort(TW::B)); + RTLIL::SigSpec Y = sigmap(cell->getPort(TW::Y)); alunode_t *n = nullptr; @@ -509,7 +509,7 @@ struct AlumaccWorker goto delete_node; } - n->alu_cell = module->addCell(NEW_ID, ID($alu)); + n->alu_cell = module->addCell(NEW_TWINE, ID($alu)); alu_counter++; log(" creating $alu cell for "); @@ -520,13 +520,13 @@ struct AlumaccWorker if (n->cells.size() > 0) n->alu_cell->adopt_src_from(n->cells[0]); - n->alu_cell->setPort(ID::A, n->a); - n->alu_cell->setPort(ID::B, n->b); - n->alu_cell->setPort(ID::CI, GetSize(n->c) ? n->c : State::S0); - n->alu_cell->setPort(ID::BI, n->invert_b ? State::S1 : State::S0); - n->alu_cell->setPort(ID::Y, n->y); - n->alu_cell->setPort(ID::X, module->addWire(NEW_ID, GetSize(n->y))); - n->alu_cell->setPort(ID::CO, module->addWire(NEW_ID, GetSize(n->y))); + n->alu_cell->setPort(TW::A, n->a); + n->alu_cell->setPort(TW::B, n->b); + n->alu_cell->setPort(TW::CI, GetSize(n->c) ? n->c : State::S0); + n->alu_cell->setPort(TW::BI, n->invert_b ? State::S1 : State::S0); + n->alu_cell->setPort(TW::Y, n->y); + n->alu_cell->setPort(TW::X, module->addWire(NEW_TWINE, GetSize(n->y))); + n->alu_cell->setPort(TW::CO, module->addWire(NEW_TWINE, GetSize(n->y))); n->alu_cell->fixup_parameters(n->is_signed, n->is_signed); for (auto &it : n->cmp) diff --git a/passes/techmap/arith_tree.cc b/passes/techmap/arith_tree.cc index 2a8419b44..f993737c1 100644 --- a/passes/techmap/arith_tree.cc +++ b/passes/techmap/arith_tree.cc @@ -79,15 +79,15 @@ struct AluInfo { Traversal &traversal; bool is_subtract(Cell *cell) { - SigSpec bi = traversal.sigmap(cell->getPort(ID::BI)); - SigSpec ci = traversal.sigmap(cell->getPort(ID::CI)); + SigSpec bi = traversal.sigmap(cell->getPort(TW::BI)); + SigSpec ci = traversal.sigmap(cell->getPort(TW::CI)); return GetSize(bi) == 1 && bi[0] == State::S1 && GetSize(ci) == 1 && ci[0] == State::S1; } bool is_add(Cell *cell) { - SigSpec bi = traversal.sigmap(cell->getPort(ID::BI)); - SigSpec ci = traversal.sigmap(cell->getPort(ID::CI)); + SigSpec bi = traversal.sigmap(cell->getPort(TW::BI)); + SigSpec ci = traversal.sigmap(cell->getPort(TW::CI)); return GetSize(bi) == 1 && bi[0] == State::S0 && GetSize(ci) == 1 && ci[0] == State::S0; } @@ -96,10 +96,10 @@ struct AluInfo { if (!(is_add(cell) || is_subtract(cell))) return false; - for (auto bit : traversal.sigmap(cell->getPort(ID::X))) + for (auto bit : traversal.sigmap(cell->getPort(TW::X))) if (traversal.fanout.count(bit) && traversal.fanout[bit] > 0) return false; - for (auto bit : traversal.sigmap(cell->getPort(ID::CO))) + for (auto bit : traversal.sigmap(cell->getPort(TW::CO))) if (traversal.fanout.count(bit) && traversal.fanout[bit] > 0) return false; @@ -140,7 +140,7 @@ struct Rewriter { { dict parent_of; for (auto cell : candidates) { - Cell *consumer = sole_chainable_consumer(traversal.sigmap(cell->getPort(ID::Y)), candidates); + Cell *consumer = sole_chainable_consumer(traversal.sigmap(cell->getPort(TW::Y)), candidates); if (consumer && consumer != cell) parent_of[cell] = consumer; } @@ -180,7 +180,7 @@ struct Rewriter { { pool bits; for (auto cell : chain) - for (auto bit : traversal.sigmap(cell->getPort(ID::Y))) + for (auto bit : traversal.sigmap(cell->getPort(TW::Y))) bits.insert(bit); return bits; } @@ -207,8 +207,8 @@ struct Rewriter { return false; // Check if any bit of child's Y connects to parent's B - SigSpec child_y = traversal.sigmap(child->getPort(ID::Y)); - SigSpec parent_b = traversal.sigmap(parent->getPort(ID::B)); + SigSpec child_y = traversal.sigmap(child->getPort(TW::Y)); + SigSpec parent_b = traversal.sigmap(parent->getPort(TW::B)); for (auto bit : child_y) for (auto pbit : parent_b) if (bit == pbit) @@ -247,8 +247,8 @@ struct Rewriter { for (auto cell : chain) { bool cell_neg = negated.count(cell) ? negated[cell] : false; - SigSpec a = traversal.sigmap(cell->getPort(ID::A)); - SigSpec b = traversal.sigmap(cell->getPort(ID::B)); + SigSpec a = traversal.sigmap(cell->getPort(TW::A)); + SigSpec b = traversal.sigmap(cell->getPort(TW::B)); bool a_signed = cell->getParam(ID::A_SIGNED).as_bool(); bool b_signed = cell->getParam(ID::B_SIGNED).as_bool(); bool b_sub = (cell->type == ID($sub)) || (cells.is_alu(cell) && alu_info.is_subtract(cell)); @@ -357,7 +357,7 @@ struct Rewriter { for (auto c : chain) to_remove.insert(c); - replace_with_carry_save_tree(operands, root->getPort(ID::Y), neg_compensation, "Replaced add/sub chain"); + replace_with_carry_save_tree(operands, root->getPort(TW::Y), neg_compensation, "Replaced add/sub chain"); } for (auto cell : to_remove) @@ -374,7 +374,7 @@ struct Rewriter { if (operands.size() < 3) continue; - replace_with_carry_save_tree(operands, cell->getPort(ID::Y), neg_compensation, "Replaced $macc"); + replace_with_carry_save_tree(operands, cell->getPort(TW::Y), neg_compensation, "Replaced $macc"); module->remove(cell); } } diff --git a/passes/techmap/bmuxmap.cc b/passes/techmap/bmuxmap.cc index 411b2d997..7ec37788c 100644 --- a/passes/techmap/bmuxmap.cc +++ b/passes/techmap/bmuxmap.cc @@ -59,17 +59,17 @@ struct BmuxmapPass : public Pass { if (cell->type != ID($bmux)) continue; - SigSpec sel = cell->getPort(ID::S); - SigSpec data = cell->getPort(ID::A); - int width = GetSize(cell->getPort(ID::Y)); - int s_width = GetSize(cell->getPort(ID::S)); + SigSpec sel = cell->getPort(TW::S); + SigSpec data = cell->getPort(TW::A); + int width = GetSize(cell->getPort(TW::Y)); + int s_width = GetSize(cell->getPort(TW::S)); if(pmux_mode) { int num_cases = 1 << s_width; SigSpec new_a = SigSpec(State::Sx, width); - SigSpec new_s = module->addWire(NEW_ID, num_cases); - SigSpec new_data = module->addWire(NEW_ID, width); + SigSpec new_s = module->addWire(NEW_TWINE, num_cases); + SigSpec new_data = module->addWire(NEW_TWINE, width); for (int val = 0; val < num_cases; val++) { module->addEq(NEW_ID, sel, SigSpec(val, GetSize(sel)), new_s[val]); @@ -81,7 +81,7 @@ struct BmuxmapPass : public Pass { else { for (int idx = 0; idx < GetSize(sel); idx++) { - SigSpec new_data = module->addWire(NEW_ID, GetSize(data)/2); + SigSpec new_data = module->addWire(NEW_TWINE, GetSize(data)/2); for (int i = 0; i < GetSize(new_data); i += width) { RTLIL::Cell *mux = module->addMux(NEW_ID, data.extract(i*2, width), @@ -94,7 +94,7 @@ struct BmuxmapPass : public Pass { } } - module->connect(cell->getPort(ID::Y), data); + module->connect(cell->getPort(TW::Y), data); module->remove(cell); } } diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index 630c83f8c..6e2ce7094 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -213,9 +213,9 @@ struct BoothPassWorker { bool is_signed; if (cell->type == ID($mul)) { - A = cell->getPort(ID::A); - B = cell->getPort(ID::B); - Y = cell->getPort(ID::Y); + A = cell->getPort(TW::A); + B = cell->getPort(TW::B); + Y = cell->getPort(TW::Y); log_assert(cell->getParam(ID::A_SIGNED).as_bool() == cell->getParam(ID::B_SIGNED).as_bool()); is_signed = cell->getParam(ID::A_SIGNED).as_bool(); @@ -231,7 +231,7 @@ struct BoothPassWorker { A = macc.terms[0].in_a; B = macc.terms[0].in_b; is_signed = macc.terms[0].is_signed; - Y = cell->getPort(ID::Y); + Y = cell->getPort(TW::Y); } else { continue; } @@ -290,7 +290,7 @@ struct BoothPassWorker { int required_op_size = x_sz_revised + y_sz_revised; if (required_op_size != z_sz) { - SigSpec expanded_Y = module->addWire(NEW_ID, required_op_size); + SigSpec expanded_Y = module->addWire(NEW_TWINE, required_op_size); SigSpec Y_driver = expanded_Y; Y_driver.extend_u0(Y.size(), is_signed); module->connect(Y, Y_driver); @@ -518,29 +518,29 @@ struct BoothPassWorker { int ix = 0; for (auto csa_elem : csa_tree) { printf("\tCell %d %s type %s\n", ix, csa_elem->name.c_str(), csa_elem->type.c_str()); - if (csa_elem->getPort(ID::A) == State::S0) + if (csa_elem->getPort(TW::A) == State::S0) printf("\tA set to constant 0\n"); - else if (csa_elem->getPort(ID::A) == State::S1) + else if (csa_elem->getPort(TW::A) == State::S1) printf("\tA set to constant 1\n"); else - printf("\tA driven by %s\n", csa_elem->getPort(ID::A).as_wire()->name.c_str()); + printf("\tA driven by %s\n", csa_elem->getPort(TW::A).as_wire()->name.c_str()); - if (csa_elem->getPort(ID::B) == State::S0) + if (csa_elem->getPort(TW::B) == State::S0) printf("\tB set to constant 0\n"); - else if (csa_elem->getPort(ID::B) == State::S1) + else if (csa_elem->getPort(TW::B) == State::S1) printf("\tB set to constant 1\n"); else - printf("\tB driven by %s\n", csa_elem->getPort(ID::B).as_wire()->name.c_str()); + printf("\tB driven by %s\n", csa_elem->getPort(TW::B).as_wire()->name.c_str()); - if (csa_elem->getPort(ID::C) == State::S0) + if (csa_elem->getPort(TW::C) == State::S0) printf("\tC set to constant 0\n"); - else if (csa_elem->getPort(ID::C) == State::S1) + else if (csa_elem->getPort(TW::C) == State::S1) printf("\tC set to constant 1\n"); else - printf("\tC driven by %s\n", csa_elem->getPort(ID::C).as_wire()->name.c_str()); + printf("\tC driven by %s\n", csa_elem->getPort(TW::C).as_wire()->name.c_str()); - printf("Carry out: %s\n", csa_elem->getPort(ID::X).as_wire()->name.c_str()); - printf("Sum out: %s\n", csa_elem->getPort(ID::Y).as_wire()->name.c_str()); + printf("Carry out: %s\n", csa_elem->getPort(TW::X).as_wire()->name.c_str()); + printf("Sum out: %s\n", csa_elem->getPort(TW::Y).as_wire()->name.c_str()); ix++; } @@ -718,7 +718,7 @@ struct BoothPassWorker { // End Case else if (n == s_vec.size() - 1) { // Make the carry results.. Two extra bits after fa. - SigBit carry_out = module->addWire(NEW_ID, 1); + SigBit carry_out = module->addWire(NEW_TWINE, 1); module->addFa(NEW_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)), /* A */ s_vec[n], /* B */ c_vec[n - 1], @@ -746,7 +746,7 @@ struct BoothPassWorker { } // Step case else { - SigBit carry_out = module->addWire(NEW_ID_SUFFIX(stringf("cpa_%d_carry_%d", cpa_id, n)), 1); + SigBit carry_out = module->addWire(NEW_TWINE_SUFFIX(stringf("cpa_%d_carry_%d", cpa_id, n)), 1); module->addFa(NEW_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)), /* A */ s_vec[n], /* B */ c_vec[n - 1], @@ -785,8 +785,8 @@ struct BoothPassWorker { if (first_csa_ips.size() > 0) { // build the first csa - auto s_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1); - auto c_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1); + auto s_wire = module->addWire(NEW_TWINE_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1); + auto c_wire = module->addWire(NEW_TWINE_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1); auto csa = module->addFa(NEW_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)), /* A */ first_csa_ips[0], @@ -817,8 +817,8 @@ struct BoothPassWorker { } if (csa_ips.size() > 0) { - auto c_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1); - auto s_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1); + auto c_wire = module->addWire(NEW_TWINE_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1); + auto s_wire = module->addWire(NEW_TWINE_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1); auto csa = module->addFa(NEW_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)), /* A */ s_result, @@ -850,10 +850,10 @@ struct BoothPassWorker { for (int y_ix = 0; y_ix < (!is_signed ? y_sz : y_sz - 1);) { std::string enc_name = stringf("bur_enc_%d", encoder_ix); - two_int.append(module->addWire(NEW_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1)); - one_int.append(module->addWire(NEW_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1)); - s_int.append(module->addWire(NEW_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1)); - sb_int.append(module->addWire(NEW_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1)); + two_int.append(module->addWire(NEW_TWINE_SUFFIX(stringf("two_int_%d", encoder_ix)), 1)); + one_int.append(module->addWire(NEW_TWINE_SUFFIX(stringf("one_int_%d", encoder_ix)), 1)); + s_int.append(module->addWire(NEW_TWINE_SUFFIX(stringf("s_int_%d", encoder_ix)), 1)); + sb_int.append(module->addWire(NEW_TWINE_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1)); if (y_ix == 0) { BuildBur4e(enc_name, State::S0, Y[y_ix], @@ -910,10 +910,10 @@ struct BoothPassWorker { std::string enc_name = stringf("br_enc_pad_%d", encoder_ix); - two_int.append(module->addWire(NEW_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1)); - one_int.append(module->addWire(NEW_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1)); - s_int.append(module->addWire(NEW_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1)); - sb_int.append(module->addWire(NEW_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1)); + two_int.append(module->addWire(NEW_TWINE_SUFFIX(stringf("two_int_%d", encoder_ix)), 1)); + one_int.append(module->addWire(NEW_TWINE_SUFFIX(stringf("one_int_%d", encoder_ix)), 1)); + s_int.append(module->addWire(NEW_TWINE_SUFFIX(stringf("s_int_%d", encoder_ix)), 1)); + sb_int.append(module->addWire(NEW_TWINE_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1)); SigBit one_o_int, two_o_int, s_o_int, sb_o_int; BuildBur4e(enc_name, Y[y_ix], State::S0, @@ -957,10 +957,10 @@ struct BoothPassWorker { for (unsigned encoder_ix = 1; encoder_ix <= enc_count; encoder_ix++) { std::string enc_name = stringf("enc_%d", encoder_ix); - negi_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("negi_n_int_%d", encoder_ix)), 1); - twoi_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("twoi_n_int_%d", encoder_ix)), 1); - onei_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("onei_n_int_%d", encoder_ix)), 1); - cori_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("cori_n_int_%d", encoder_ix)), 1); + negi_n_int[encoder_ix - 1] = module->addWire(NEW_TWINE_SUFFIX(stringf("negi_n_int_%d", encoder_ix)), 1); + twoi_n_int[encoder_ix - 1] = module->addWire(NEW_TWINE_SUFFIX(stringf("twoi_n_int_%d", encoder_ix)), 1); + onei_n_int[encoder_ix - 1] = module->addWire(NEW_TWINE_SUFFIX(stringf("onei_n_int_%d", encoder_ix)), 1); + cori_n_int[encoder_ix - 1] = module->addWire(NEW_TWINE_SUFFIX(stringf("cori_n_int_%d", encoder_ix)), 1); if (encoder_ix == 1) { BuildBr4e(enc_name, State::S0, Y[0], Y[1], @@ -995,10 +995,10 @@ struct BoothPassWorker { for (int encoder_ix = 1; encoder_ix <= (int)enc_count; encoder_ix++) { for (int decoder_ix = 1; decoder_ix <= dec_count; decoder_ix++) { PPij[((encoder_ix - 1) * dec_count) + decoder_ix - 1] = - module->addWire(NEW_ID_SUFFIX(stringf("ppij_%d_%d", encoder_ix, decoder_ix)), 1); + module->addWire(NEW_TWINE_SUFFIX(stringf("ppij_%d_%d", encoder_ix, decoder_ix)), 1); nxj[((encoder_ix - 1) * dec_count) + decoder_ix - 1] = - module->addWire(NEW_ID_SUFFIX(stringf("nxj_%s%d_%d", decoder_ix == 1 ? "pre_dec_" : "", + module->addWire(NEW_TWINE_SUFFIX(stringf("nxj_%s%d_%d", decoder_ix == 1 ? "pre_dec_" : "", encoder_ix, decoder_ix)), 1); } } @@ -1065,8 +1065,8 @@ struct BoothPassWorker { std::vector fa_carry; for (fa_row_ix = 0; fa_row_ix < fa_row_count; fa_row_ix++) { - fa_sum.push_back(module->addWire(NEW_ID_SUFFIX(stringf("fa_sum_%d", fa_row_ix)), fa_count)); - fa_carry.push_back(module->addWire(NEW_ID_SUFFIX(stringf("fa_carry_%d", fa_row_ix)), fa_count)); + fa_sum.push_back(module->addWire(NEW_TWINE_SUFFIX(stringf("fa_sum_%d", fa_row_ix)), fa_count)); + fa_carry.push_back(module->addWire(NEW_TWINE_SUFFIX(stringf("fa_carry_%d", fa_row_ix)), fa_count)); } // full adder creation @@ -1103,7 +1103,7 @@ struct BoothPassWorker { // instantiate the cpa SigSpec cpa_carry; if (z_sz > fa_row_count * 2) - cpa_carry = module->addWire(NEW_ID_SUFFIX("cpa_carry"), z_sz - fa_row_count * 2); + cpa_carry = module->addWire(NEW_TWINE_SUFFIX("cpa_carry"), z_sz - fa_row_count * 2); // The end case where we pass the last two summands // from prior row directly to product output diff --git a/passes/techmap/bufnorm.cc b/passes/techmap/bufnorm.cc index a5cc99532..bd6898e16 100644 --- a/passes/techmap/bufnorm.cc +++ b/passes/techmap/bufnorm.cc @@ -280,8 +280,8 @@ struct BufnormPass : public Pass { if (!cell->type.in(ID($buf), ID($_BUF_))) continue; - SigSpec insig = cell->getPort(ID::A); - SigSpec outsig = cell->getPort(ID::Y); + SigSpec insig = cell->getPort(TW::A); + SigSpec outsig = cell->getPort(TW::Y); for (int i = 0; i < GetSize(insig) && i < GetSize(outsig); i++) sigmap.add(insig[i], outsig[i]); @@ -401,7 +401,7 @@ struct BufnormPass : public Pass { it->second.sort(compare_wires_f); w = *(it->second.begin()); } else { - w = module->addWire(NEW_ID, GetSize(conn.second)); + w = module->addWire(NEW_TWINE, GetSize(conn.second)); for (int i = 0; i < GetSize(w); i++) sigmap.add(SigBit(w, i), keysig[i]); } @@ -442,20 +442,20 @@ struct BufnormPass : public Pass { old_buffers.erase(it); added_buffers.insert(cell); - if (cell->getPort(ID::A) == src) { + if (cell->getPort(TW::A) == src) { count_kept_buffers++; } else { - cell->setPort(ID::A, src); + cell->setPort(TW::A, src); count_updated_buffers++; } return; } - Cell *cell = module->addCell(NEW_ID, type); + Cell *cell = module->addCell(NEW_TWINE, type); added_buffers.insert(cell); - cell->setPort(ID::A, src); - cell->setPort(ID::Y, dst); + cell->setPort(TW::A, src); + cell->setPort(TW::Y, dst); cell->fixup_parameters(); count_created_buffers++; }; diff --git a/passes/techmap/bwmuxmap.cc b/passes/techmap/bwmuxmap.cc index 7fe1cded7..3bd794ed1 100644 --- a/passes/techmap/bwmuxmap.cc +++ b/passes/techmap/bwmuxmap.cc @@ -52,10 +52,10 @@ struct BwmuxmapPass : public Pass { { if (cell->type != ID($bwmux)) continue; - auto &sig_y = cell->getPort(ID::Y); - auto &sig_a = cell->getPort(ID::A); - auto &sig_b = cell->getPort(ID::B); - auto &sig_s = cell->getPort(ID::S); + auto &sig_y = cell->getPort(TW::Y); + auto &sig_a = cell->getPort(TW::A); + auto &sig_b = cell->getPort(TW::B); + auto &sig_s = cell->getPort(TW::S); auto not_s = module->Not(NEW_ID, sig_s); auto masked_b = module->And(NEW_ID, sig_s, sig_b); diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc index 46cf528da..4cbb0e195 100644 --- a/passes/techmap/clkbufmap.cc +++ b/passes/techmap/clkbufmap.cc @@ -261,21 +261,21 @@ struct ClkbufmapPass : public Pass { bool is_input = wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute(ID::top); if (!buf_celltype.empty() && (!is_input || buffer_inputs)) { log("Inserting %s on %s.%s[%d].\n", buf_celltype, module, wire, i); - cell = module->addCell(NEW_ID, RTLIL::escape_id(buf_celltype)); - iwire = module->addWire(NEW_ID); + cell = module->addCell(NEW_TWINE, RTLIL::escape_id(buf_celltype)); + iwire = module->addWire(NEW_TWINE); cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit); cell->setPort(RTLIL::escape_id(buf_portname2), iwire); } if (is_input) { log("Inserting %s on %s.%s[%d].\n", inpad_celltype, module, wire, i); - RTLIL::Cell *cell2 = module->addCell(NEW_ID, RTLIL::escape_id(inpad_celltype)); + RTLIL::Cell *cell2 = module->addCell(NEW_TWINE, RTLIL::escape_id(inpad_celltype)); if (iwire) { cell2->setPort(RTLIL::escape_id(inpad_portname), iwire); } else { cell2->setPort(RTLIL::escape_id(inpad_portname), mapped_wire_bit); cell = cell2; } - iwire = module->addWire(NEW_ID); + iwire = module->addWire(NEW_TWINE); cell2->setPort(RTLIL::escape_id(inpad_portname2), iwire); } if (iwire) @@ -294,7 +294,7 @@ struct ClkbufmapPass : public Pass { if (!input_bits.empty()) { // This is an input port and some buffers were inserted -- we need // to create a new input wire and transfer attributes. - Wire *new_wire = module->addWire(NEW_ID, wire); + Wire *new_wire = module->addWire(NEW_TWINE, wire); for (int i = 0; i < wire->width; i++) { SigBit wire_bit(wire, i); diff --git a/passes/techmap/clockgate.cc b/passes/techmap/clockgate.cc index 650719cd5..af2d2afe8 100644 --- a/passes/techmap/clockgate.cc +++ b/passes/techmap/clockgate.cc @@ -371,10 +371,10 @@ struct ClockgatePass : public Pass { if (!matching_icg_desc) continue; - Cell* icg = module->addCell(NEW_ID, matching_icg_desc->name); + Cell* icg = module->addCell(NEW_TWINE, matching_icg_desc->name); icg->setPort(matching_icg_desc->ce_pin, clk.ce_bit); icg->setPort(matching_icg_desc->clk_in_pin, clk.clk_bit); - gclk.new_net = module->addWire(NEW_ID); + gclk.new_net = module->addWire(NEW_TWINE); icg->setPort(matching_icg_desc->clk_out_pin, gclk.new_net); // Tie low DFT ports like scan chain enable for (auto port : matching_icg_desc->tie_lo_pins) diff --git a/passes/techmap/constmap.cc b/passes/techmap/constmap.cc index 225bca81b..f04340fe2 100644 --- a/passes/techmap/constmap.cc +++ b/passes/techmap/constmap.cc @@ -32,8 +32,8 @@ static RTLIL::SigChunk value; void constmap_worker(RTLIL::SigSpec &sig) { if (sig.is_fully_const()){ - value = module->addWire(NEW_ID, sig.size()); - RTLIL::Cell *cell = module->addCell(NEW_ID, celltype); + value = module->addWire(NEW_TWINE, sig.size()); + RTLIL::Cell *cell = module->addCell(NEW_TWINE, celltype); cell->setParam(cell_paramname, sig.as_const()); cell->setPort(cell_portname, value); sig = value; diff --git a/passes/techmap/demuxmap.cc b/passes/techmap/demuxmap.cc index 8df28ef60..f1a31b8e9 100644 --- a/passes/techmap/demuxmap.cc +++ b/passes/techmap/demuxmap.cc @@ -50,17 +50,17 @@ struct DemuxmapPass : public Pass { if (cell->type != ID($demux)) continue; - SigSpec sel = cell->getPort(ID::S); - SigSpec data = cell->getPort(ID::A); - SigSpec out = cell->getPort(ID::Y); - int width = GetSize(cell->getPort(ID::A)); + SigSpec sel = cell->getPort(TW::S); + SigSpec data = cell->getPort(TW::A); + SigSpec out = cell->getPort(TW::Y); + int width = GetSize(cell->getPort(TW::A)); for (int i = 0; i < 1 << GetSize(sel); i++) { if (width == 1 && data == State::S1) { RTLIL::Cell *eq_cell = module->addEq(NEW_ID, sel, Const(i, GetSize(sel)), out[i]); module->design->merge_src(eq_cell, cell); } else { - Wire *eq = module->addWire(NEW_ID); + Wire *eq = module->addWire(NEW_TWINE); RTLIL::Cell *eq_cell = module->addEq(NEW_ID, sel, Const(i, GetSize(sel)), eq); module->design->merge_src(eq_cell, cell); RTLIL::Cell *mux = module->addMux(NEW_ID, diff --git a/passes/techmap/dfflegalize.cc b/passes/techmap/dfflegalize.cc index 3cba527b2..90ac12a03 100644 --- a/passes/techmap/dfflegalize.cc +++ b/passes/techmap/dfflegalize.cc @@ -293,7 +293,7 @@ struct DffLegalizePass : public Pass { ff_dff.has_ce = ff.has_ce; ff_dff.sig_ce = ff.sig_ce; ff_dff.pol_ce = ff.pol_ce; - ff_dff.sig_q = ff.module->addWire(NEW_ID, ff.width); + ff_dff.sig_q = ff.module->addWire(NEW_TWINE, ff.width); ff_dff.val_init = ff.val_init; ff_dff.is_fine = ff.is_fine; @@ -310,7 +310,7 @@ struct DffLegalizePass : public Pass { ff_adff.has_ce = ff.has_ce; ff_adff.sig_ce = ff.sig_ce; ff_adff.pol_ce = ff.pol_ce; - ff_adff.sig_q = ff.module->addWire(NEW_ID, ff.width); + ff_adff.sig_q = ff.module->addWire(NEW_TWINE, ff.width); ff_adff.val_init = Const(State::Sx, ff.width); ff_adff.has_arst = true; ff_adff.sig_arst = ff.sig_arst; @@ -320,7 +320,7 @@ struct DffLegalizePass : public Pass { FfData ff_sel(ff.module, &initvals, NEW_ID); ff_sel.width = 1; - ff_sel.sig_q = ff.module->addWire(NEW_ID); + ff_sel.sig_q = ff.module->addWire(NEW_TWINE); ff_sel.has_arst = true; ff_sel.sig_arst = ff.sig_arst; ff_sel.pol_arst = ff.pol_arst; @@ -403,7 +403,7 @@ struct DffLegalizePass : public Pass { ff_clr.sig_arst = ff.sig_clr; ff_clr.pol_arst = ff.pol_clr; ff_clr.val_arst = Const(State::S0, ff.width); - ff_clr.sig_q = ff.module->addWire(NEW_ID, ff.width); + ff_clr.sig_q = ff.module->addWire(NEW_TWINE, ff.width); ff_clr.val_init = init_clr ? ff.val_init : Const(State::Sx, ff.width); ff_clr.is_fine = ff.is_fine; @@ -424,7 +424,7 @@ struct DffLegalizePass : public Pass { ff_set.sig_arst = ff.sig_set; ff_set.pol_arst = ff.pol_set; ff_set.val_arst = Const(State::S1, ff.width); - ff_set.sig_q = ff.module->addWire(NEW_ID, ff.width); + ff_set.sig_q = ff.module->addWire(NEW_TWINE, ff.width); ff_set.val_init = init_set ? ff.val_init : Const(State::Sx, ff.width); ff_set.is_fine = ff.is_fine; @@ -435,7 +435,7 @@ struct DffLegalizePass : public Pass { ff_sel.pol_set = ff.pol_set; ff_sel.sig_clr = ff.sig_clr; ff_sel.sig_set = ff.sig_set; - ff_sel.sig_q = ff.module->addWire(NEW_ID, ff.width); + ff_sel.sig_q = ff.module->addWire(NEW_TWINE, ff.width); ff_sel.val_init = Const(initsel, ff.width); ff_sel.is_fine = ff.is_fine; @@ -841,7 +841,7 @@ struct DffLegalizePass : public Pass { ff.sig_ad = State::S0; ff.val_arst = State::S1; ff.remove_init(); - Wire *new_q = ff.module->addWire(NEW_ID); + Wire *new_q = ff.module->addWire(NEW_TWINE); if (ff.is_fine) ff.module->addNotGate(NEW_ID, new_q, ff.sig_q); else diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index aee627113..2fc3a3461 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -505,7 +505,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) if (design->selected(module, cell) && cell_mappings.count(cell->type) > 0) cell_list.push_back(cell); if (cell->type == ID($_NOT_)) - notmap[sigmap(cell->getPort(ID::A))].insert(cell); + notmap[sigmap(cell->getPort(TW::A))].insert(cell); } std::map stats; @@ -536,11 +536,11 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) } else if (port.second == 'q') { RTLIL::SigSpec old_sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))]; - sig = module->addWire(NEW_ID, GetSize(old_sig)); + sig = module->addWire(NEW_TWINE, GetSize(old_sig)); if (has_q && has_qn) { for (auto &it : notmap[sigmap(old_sig)]) { - module->connect(it->getPort(ID::Y), sig); - it->setPort(ID::Y, module->addWire(NEW_ID, GetSize(old_sig))); + module->connect(it->getPort(TW::Y), sig); + it->setPort(TW::Y, module->addWire(NEW_TWINE, GetSize(old_sig))); } } else { module->addNotGate(NEW_ID, sig, old_sig); @@ -554,7 +554,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) sig = RTLIL::SigSpec(port.second == '0' ? 0 : 1, 1); } else if (port.second == 0) { - sig = module->addWire(NEW_ID); + sig = module->addWire(NEW_TWINE); } else log_abort(); new_cell->setPort("\\" + port.first, sig); diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc index 83bf5a14f..a19449727 100644 --- a/passes/techmap/extract_counter.cc +++ b/passes/techmap/extract_counter.cc @@ -135,17 +135,17 @@ int counter_tryextract( return 3; //CO and X must be unconnected (exactly one connection to each port) - if(!is_unconnected(sigmap(cell->getPort(ID::CO)), index)) + if(!is_unconnected(sigmap(cell->getPort(TW::CO)), index)) return 7; - if(!is_unconnected(sigmap(cell->getPort(ID::X)), index)) + if(!is_unconnected(sigmap(cell->getPort(TW::X)), index)) return 8; //true if $alu is performing A - B, else A + B bool alu_is_subtract; //BI and CI must be both constant 0 or both constant 1 as well - const RTLIL::SigSpec bi_port = sigmap(cell->getPort(ID::BI)); - const RTLIL::SigSpec ci_port = sigmap(cell->getPort(ID::CI)); + const RTLIL::SigSpec bi_port = sigmap(cell->getPort(TW::BI)); + const RTLIL::SigSpec ci_port = sigmap(cell->getPort(TW::CI)); if(bi_port.is_fully_const() && bi_port.as_int() == 1 && ci_port.is_fully_const() && ci_port.as_int() == 1) { @@ -169,7 +169,7 @@ int counter_tryextract( { const int a_width = cell->getParam(ID::A_WIDTH).as_int(); const int b_width = cell->getParam(ID::B_WIDTH).as_int(); - const RTLIL::SigSpec b_port = sigmap(cell->getPort(ID::B)); + const RTLIL::SigSpec b_port = sigmap(cell->getPort(TW::B)); // down, cnt <= cnt - 1 if (b_width == 1 && b_port.is_fully_const() && b_port.as_int() == 1) @@ -197,8 +197,8 @@ int counter_tryextract( { const int a_width = cell->getParam(ID::A_WIDTH).as_int(); const int b_width = cell->getParam(ID::B_WIDTH).as_int(); - const RTLIL::SigSpec a_port = sigmap(cell->getPort(ID::A)); - const RTLIL::SigSpec b_port = sigmap(cell->getPort(ID::B)); + const RTLIL::SigSpec a_port = sigmap(cell->getPort(TW::A)); + const RTLIL::SigSpec b_port = sigmap(cell->getPort(TW::B)); // down, cnt <= cnt + -1 if (b_width == a_width && b_port.is_fully_const() && b_port.is_fully_ones()) @@ -252,7 +252,7 @@ int counter_tryextract( //Y must have exactly one connection, and it has to be a $mux cell. //We must have a direct bus connection from our Y to their A. - const RTLIL::SigSpec aluy = sigmap(cell->getPort(ID::Y)); + const RTLIL::SigSpec aluy = sigmap(cell->getPort(TW::Y)); pool y_loads = get_other_cells(aluy, index, cell); if(y_loads.size() != 1) return 9; @@ -266,14 +266,14 @@ int counter_tryextract( if (extract.count_is_up) { //B connection of the mux must be 0 - const RTLIL::SigSpec underflow = sigmap(count_mux->getPort(ID::B)); + const RTLIL::SigSpec underflow = sigmap(count_mux->getPort(TW::B)); if(!(underflow.is_fully_const() && underflow.is_fully_zero())) return 12; } else { //B connection of the mux is our underflow value - const RTLIL::SigSpec underflow = sigmap(count_mux->getPort(ID::B)); + const RTLIL::SigSpec underflow = sigmap(count_mux->getPort(TW::B)); if(!underflow.is_fully_const()) return 12; extract.count_value = underflow.as_int(); @@ -281,7 +281,7 @@ int counter_tryextract( //S connection of the mux must come from an inverter if down, eq if up //(need not be the only load) - const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort(ID::S)); + const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort(TW::S)); extract.outsig = muxsel; pool muxsel_conns = get_other_cells(muxsel, index, count_mux); Cell* overflow_cell = NULL; @@ -303,7 +303,7 @@ int counter_tryextract( //Y connection of the mux must have exactly one load, the counter's internal register, if there's no clock enable //If we have a clock enable, Y drives the B input of a mux. A of that mux must come from our register - const RTLIL::SigSpec muxy = sigmap(count_mux->getPort(ID::Y)); + const RTLIL::SigSpec muxy = sigmap(count_mux->getPort(TW::Y)); pool muxy_loads = get_other_cells(muxy, index, count_mux); if(muxy_loads.size() != 1) return 14; @@ -316,23 +316,23 @@ int counter_tryextract( //This mux is probably a clock enable mux. //Find our count register (should be our only load) cemux = muxload; - cey = sigmap(cemux->getPort(ID::Y)); + cey = sigmap(cemux->getPort(TW::Y)); pool cey_loads = get_other_cells(cey, index, cemux); if(cey_loads.size() != 1) return 24; count_reg = *cey_loads.begin(); - if(sigmap(cemux->getPort(ID::Y)) != sigmap(count_reg->getPort(ID::D))) + if(sigmap(cemux->getPort(TW::Y)) != sigmap(count_reg->getPort(TW::D))) return 24; //Mux should have A driven by count Q, and B by muxy //if A and B are swapped, CE polarity is inverted - if(sigmap(cemux->getPort(ID::B)) == muxy && - sigmap(cemux->getPort(ID::A)) == sigmap(count_reg->getPort(ID::Q))) + if(sigmap(cemux->getPort(TW::B)) == muxy && + sigmap(cemux->getPort(TW::A)) == sigmap(count_reg->getPort(TW::Q))) { extract.ce_inverted = false; } - else if(sigmap(cemux->getPort(ID::A)) == muxy && - sigmap(cemux->getPort(ID::B)) == sigmap(count_reg->getPort(ID::Q))) + else if(sigmap(cemux->getPort(TW::A)) == muxy && + sigmap(cemux->getPort(TW::B)) == sigmap(count_reg->getPort(TW::Q))) { extract.ce_inverted = true; } @@ -343,7 +343,7 @@ int counter_tryextract( //Select of the mux is our clock enable extract.has_ce = true; - extract.ce = sigmap(cemux->getPort(ID::S)); + extract.ce = sigmap(cemux->getPort(TW::S)); } else extract.has_ce = false; @@ -371,7 +371,7 @@ int counter_tryextract( return 23; //Save the reset - extract.rst = sigmap(count_reg->getPort(ID::ARST)); + extract.rst = sigmap(count_reg->getPort(TW::ARST)); } //TODO: support synchronous reset else @@ -395,7 +395,7 @@ int counter_tryextract( //Register output must have exactly two loads, the inverter and ALU //(unless we have a parallel output!) //If we have a clock enable, 3 is OK - const RTLIL::SigSpec qport = count_reg->getPort(ID::Q); + const RTLIL::SigSpec qport = count_reg->getPort(TW::Q); extract.poutsig = qport; extract.has_pout = false; const RTLIL::SigSpec cnout = sigmap(qport); @@ -456,7 +456,7 @@ int counter_tryextract( if(is_full_bus(cnout, index, count_reg, ID::Q, overflow_cell, ID::A, true)) { // B must be the overflow value - const RTLIL::SigSpec overflow = sigmap(overflow_cell->getPort(ID::B)); + const RTLIL::SigSpec overflow = sigmap(overflow_cell->getPort(TW::B)); if(!overflow.is_fully_const()) return 12; extract.count_value = overflow.as_int(); @@ -464,7 +464,7 @@ int counter_tryextract( else if(is_full_bus(cnout, index, count_reg, ID::Q, overflow_cell, ID::B, true)) { // A must be the overflow value - const RTLIL::SigSpec overflow = sigmap(overflow_cell->getPort(ID::A)); + const RTLIL::SigSpec overflow = sigmap(overflow_cell->getPort(TW::A)); if(!overflow.is_fully_const()) return 12; extract.count_value = overflow.as_int(); @@ -480,7 +480,7 @@ int counter_tryextract( return 19; //Look up the clock from the register - extract.clk = sigmap(count_reg->getPort(ID::CLK)); + extract.clk = sigmap(count_reg->getPort(TW::CLK)); if(!extract.count_is_up) { @@ -522,10 +522,10 @@ void counter_worker( //A input is the count value. Check if it has COUNT_EXTRACT set. //If it's not a wire, don't even try - auto port = sigmap(cell->getPort(ID::A)); + auto port = sigmap(cell->getPort(TW::A)); if(!port.is_wire()) { - port = sigmap(cell->getPort(ID::B)); + port = sigmap(cell->getPort(TW::B)); if(!port.is_wire()) return; } @@ -614,13 +614,13 @@ void counter_worker( string countname = string("$COUNTx$") + extract.rwire->name.unescape(); //Wipe all of the old connections to the ALU - cell->unsetPort(ID::A); - cell->unsetPort(ID::B); - cell->unsetPort(ID::BI); - cell->unsetPort(ID::CI); - cell->unsetPort(ID::CO); - cell->unsetPort(ID::X); - cell->unsetPort(ID::Y); + cell->unsetPort(TW::A); + cell->unsetPort(TW::B); + cell->unsetPort(TW::BI); + cell->unsetPort(TW::CI); + cell->unsetPort(TW::CO); + cell->unsetPort(TW::X); + cell->unsetPort(TW::Y); cell->unsetParam(ID::A_SIGNED); cell->unsetParam(ID::A_WIDTH); cell->unsetParam(ID::B_SIGNED); @@ -639,7 +639,7 @@ void counter_worker( //If the reset is active low, infer an inverter ($__COUNT_ cells always have active high reset) if(extract.rst_inverted) { - auto realreset = cell->module->addWire(NEW_ID); + auto realreset = cell->module->addWire(NEW_TWINE); cell->module->addNot(NEW_ID, extract.rst, RTLIL::SigSpec(realreset)); cell->setPort(ID(RST), realreset); } @@ -656,7 +656,7 @@ void counter_worker( //cell->setParam(ID(CLKIN_DIVIDE), RTLIL::Const(1)); cell->setParam(ID(COUNT_TO), RTLIL::Const(extract.count_value)); cell->setParam(ID::WIDTH, RTLIL::Const(extract.width)); - cell->setPort(ID::CLK, extract.clk); + cell->setPort(TW::CLK, extract.clk); cell->setPort(ID(OUT), extract.outsig); //Hook up clock enable @@ -665,7 +665,7 @@ void counter_worker( cell->setParam(ID(HAS_CE), RTLIL::Const(1)); if(extract.ce_inverted) { - auto realce = cell->module->addWire(NEW_ID); + auto realce = cell->module->addWire(NEW_TWINE); cell->module->addNot(NEW_ID, extract.ce, RTLIL::SigSpec(realce)); cell->setPort(ID(CE), realce); } diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc index 15cdc54c9..181de6a2a 100644 --- a/passes/techmap/extract_fa.cc +++ b/passes/techmap/extract_fa.cc @@ -89,7 +89,7 @@ struct ExtractFaWorker ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_), ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) { - SigBit y = sigmap(SigBit(cell->getPort(ID::Y))); + SigBit y = sigmap(SigBit(cell->getPort(TW::Y))); log_assert(driver.count(y) == 0); driver[y] = cell; } @@ -281,8 +281,8 @@ struct ExtractFaWorker void assign_new_driver(SigBit bit, SigBit new_driver) { Cell *cell = driver.at(bit); - if (sigmap(cell->getPort(ID::Y)) == SigSpec(bit)) { - cell->setPort(ID::Y, module->addWire(NEW_ID)); + if (sigmap(cell->getPort(TW::Y)) == SigSpec(bit)) { + cell->setPort(TW::Y, module->addWire(NEW_TWINE)); module->connect(bit, new_driver); } } @@ -394,20 +394,20 @@ struct ExtractFaWorker } else { - Cell *cell = module->addCell(NEW_ID, ID($fa)); + Cell *cell = module->addCell(NEW_TWINE, ID($fa)); cell->setParam(ID::WIDTH, 1); log(" Created $fa cell %s.\n", cell); - cell->setPort(ID::A, f3i.inv_a ? module->NotGate(NEW_ID, A) : A); - cell->setPort(ID::B, f3i.inv_b ? module->NotGate(NEW_ID, B) : B); - cell->setPort(ID::C, f3i.inv_c ? module->NotGate(NEW_ID, C) : C); + cell->setPort(TW::A, f3i.inv_a ? module->NotGate(NEW_ID, A) : A); + cell->setPort(TW::B, f3i.inv_b ? module->NotGate(NEW_ID, B) : B); + cell->setPort(TW::C, f3i.inv_c ? module->NotGate(NEW_ID, C) : C); - X = module->addWire(NEW_ID); - Y = module->addWire(NEW_ID); + X = module->addWire(NEW_TWINE); + Y = module->addWire(NEW_TWINE); - cell->setPort(ID::X, X); - cell->setPort(ID::Y, Y); + cell->setPort(TW::X, X); + cell->setPort(TW::Y, Y); facache[fakey] = make_tuple(X, Y, cell); } @@ -501,20 +501,20 @@ struct ExtractFaWorker } else { - Cell *cell = module->addCell(NEW_ID, ID($fa)); + Cell *cell = module->addCell(NEW_TWINE, ID($fa)); cell->setParam(ID::WIDTH, 1); log(" Created $fa cell %s.\n", cell); - cell->setPort(ID::A, f2i.inv_a ? module->NotGate(NEW_ID, A) : A); - cell->setPort(ID::B, f2i.inv_b ? module->NotGate(NEW_ID, B) : B); - cell->setPort(ID::C, State::S0); + cell->setPort(TW::A, f2i.inv_a ? module->NotGate(NEW_ID, A) : A); + cell->setPort(TW::B, f2i.inv_b ? module->NotGate(NEW_ID, B) : B); + cell->setPort(TW::C, State::S0); - X = module->addWire(NEW_ID); - Y = module->addWire(NEW_ID); + X = module->addWire(NEW_TWINE); + Y = module->addWire(NEW_TWINE); - cell->setPort(ID::X, X); - cell->setPort(ID::Y, Y); + cell->setPort(TW::X, X); + cell->setPort(TW::Y, Y); } if (func2.at(key).count(xor2_func)) { diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc index 1ad880be0..3e196fc91 100644 --- a/passes/techmap/extract_reduce.cc +++ b/passes/techmap/extract_reduce.cc @@ -148,7 +148,7 @@ struct ExtractReducePass : public Pass head_cell = x; - auto y = sigmap(x->getPort(ID::Y)); + auto y = sigmap(x->getPort(TW::Y)); log_assert(y.size() == 1); // Should only continue if there is one fanout back into a cell (not to a port) @@ -166,7 +166,7 @@ struct ExtractReducePass : public Pass { //BFS, following all chains until they hit a cell of a different type //Pick the longest one - auto y = sigmap(cell->getPort(ID::Y)); + auto y = sigmap(cell->getPort(TW::Y)); pool current_loads = sig_to_sink[y]; pool next_loads; @@ -183,7 +183,7 @@ struct ExtractReducePass : public Pass continue; } - auto xy = sigmap(x->getPort(ID::Y)); + auto xy = sigmap(x->getPort(TW::Y)); //If this signal drives a port, add it to the sinks //(even though it may not be the end of a chain) @@ -256,7 +256,7 @@ struct ExtractReducePass : public Pass // Worth it to create reduce cell log(" Creating $reduce_* cell!\n"); - SigBit output = sigmap(head_cell->getPort(ID::Y)[0]); + SigBit output = sigmap(head_cell->getPort(TW::Y)[0]); SigSpec input; for (auto it : sources) { diff --git a/passes/techmap/extractinv.cc b/passes/techmap/extractinv.cc index 7444369cc..03252b6c0 100644 --- a/passes/techmap/extractinv.cc +++ b/passes/techmap/extractinv.cc @@ -105,10 +105,10 @@ struct ExtractinvPass : public Pass { cell->parameters.erase(param_name); if (invmask.is_fully_zero()) continue; - Wire *iwire = module->addWire(NEW_ID, sig.size()); + Wire *iwire = module->addWire(NEW_TWINE, sig.size()); for (int i = 0; i < sig.size(); i++) if (invmask[i] == State::S1) { - RTLIL::Cell *icell = module->addCell(NEW_ID, RTLIL::escape_id(inv_celltype)); + RTLIL::Cell *icell = module->addCell(NEW_TWINE, RTLIL::escape_id(inv_celltype)); icell->setPort(RTLIL::escape_id(inv_portname), SigSpec(iwire, i)); icell->setPort(RTLIL::escape_id(inv_portname2), sig[i]); log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype, module, cell->type.unescape(), port.first.unescape(), i); diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc index 3d9d3dc34..3d2eb1fbe 100644 --- a/passes/techmap/flowmap.cc +++ b/passes/techmap/flowmap.cc @@ -1432,7 +1432,7 @@ struct FlowmapWorker { auto origin = node_origins[node]; RTLIL::SigSpec driver = origin.cell->getPort(origin.port); - driver[origin.offset] = module->addWire(NEW_ID); + driver[origin.offset] = module->addWire(NEW_TWINE); origin.cell->setPort(origin.port, driver); } } diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc index 0cd81ded4..8fa4c5c0c 100644 --- a/passes/techmap/hilomap.cc +++ b/passes/techmap/hilomap.cc @@ -36,16 +36,16 @@ void hilomap_worker(RTLIL::SigSpec &sig) for (auto &bit : sig) { if (bit == RTLIL::State::S1 && !hicell_celltype.empty()) { if (!singleton_mode || last_hi == RTLIL::State::Sm) { - last_hi = module->addWire(NEW_ID); - RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(hicell_celltype)); + last_hi = module->addWire(NEW_TWINE); + RTLIL::Cell *cell = module->addCell(NEW_TWINE, RTLIL::escape_id(hicell_celltype)); cell->setPort(RTLIL::escape_id(hicell_portname), last_hi); } bit = last_hi; } if (bit == RTLIL::State::S0 && !locell_celltype.empty()) { if (!singleton_mode || last_lo == RTLIL::State::Sm) { - last_lo = module->addWire(NEW_ID); - RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(locell_celltype)); + last_lo = module->addWire(NEW_TWINE); + RTLIL::Cell *cell = module->addCell(NEW_TWINE, RTLIL::escape_id(locell_celltype)); cell->setPort(RTLIL::escape_id(locell_portname), last_lo); } bit = last_lo; diff --git a/passes/techmap/insbuf.cc b/passes/techmap/insbuf.cc index 5674de71f..c2c005d40 100644 --- a/passes/techmap/insbuf.cc +++ b/passes/techmap/insbuf.cc @@ -94,7 +94,7 @@ struct InsbufPass : public Pass { sigmap.add(outbit); } - Cell *cell = module->addCell(NEW_ID, celltype); + Cell *cell = module->addCell(NEW_TWINE, celltype); cell->setPort(in_portname, rhs); cell->setPort(out_portname, lhs); diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 80130f0fb..64b09f7e6 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -254,7 +254,7 @@ struct IopadmapPass : public Pass { // Gather tristate buffers and always-on drivers. for (auto cell : module->cells()) if (cell->type == ID($_TBUF_)) { - SigBit bit = cell->getPort(ID::Y).as_bit(); + SigBit bit = cell->getPort(TW::Y).as_bit(); tbuf_bits[bit] = cell; } else { for (auto port : cell->connections()) @@ -305,8 +305,8 @@ struct IopadmapPass : public Pass { if (tbuf_cell != nullptr) { // Found a tristate buffer — use it. - en_sig = tbuf_cell->getPort(ID::E).as_bit(); - data_sig = tbuf_cell->getPort(ID::A).as_bit(); + en_sig = tbuf_cell->getPort(TW::E).as_bit(); + data_sig = tbuf_cell->getPort(TW::A).as_bit(); } else if (is_driven) { // No tristate buffer, but an always-on driver is present. // If this is an inout port, we're creating a tinoutpad diff --git a/passes/techmap/lut2bmux.cc b/passes/techmap/lut2bmux.cc index 1073b1208..65f96ed2d 100644 --- a/passes/techmap/lut2bmux.cc +++ b/passes/techmap/lut2bmux.cc @@ -45,8 +45,8 @@ struct Lut2BmuxPass : public Pass { for (auto cell : module->selected_cells()) { if (cell->type == ID($lut)) { cell->type = ID($bmux); - cell->setPort(ID::S, cell->getPort(ID::A)); - cell->setPort(ID::A, cell->getParam(ID::LUT)); + cell->setPort(TW::S, cell->getPort(TW::A)); + cell->setPort(TW::A, cell->getParam(ID::LUT)); cell->unsetParam(ID::LUT); cell->fixup_parameters(); log("Converted %s.%s to BMUX cell.\n", module, cell); diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc index 2ddb16d61..24c44028d 100644 --- a/passes/techmap/lut2mux.cc +++ b/passes/techmap/lut2mux.cc @@ -25,8 +25,8 @@ PRIVATE_NAMESPACE_BEGIN int lut2mux(Cell *cell, bool word_mode) { - SigSpec sig_a = cell->getPort(ID::A); - SigSpec sig_y = cell->getPort(ID::Y); + SigSpec sig_a = cell->getPort(TW::A); + SigSpec sig_y = cell->getPort(TW::Y); Const lut = cell->getParam(ID::LUT); int count = 1; @@ -41,8 +41,8 @@ int lut2mux(Cell *cell, bool word_mode) { SigSpec sig_a_hi = sig_a[GetSize(sig_a)-1]; SigSpec sig_a_lo = sig_a.extract(0, GetSize(sig_a)-1); - SigSpec sig_y1 = cell->module->addWire(NEW_ID); - SigSpec sig_y2 = cell->module->addWire(NEW_ID); + SigSpec sig_y1 = cell->module->addWire(NEW_TWINE); + SigSpec sig_y2 = cell->module->addWire(NEW_TWINE); Const lut1 = lut.extract(0, GetSize(lut)/2); Const lut2 = lut.extract(GetSize(lut)/2, GetSize(lut)/2); diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc index cb041f615..72b6a3232 100644 --- a/passes/techmap/maccmap.cc +++ b/passes/techmap/maccmap.cc @@ -108,16 +108,16 @@ struct MaccmapWorker in3 = in3.extract(start_index, stop_index-start_index); int width = GetSize(in1); - RTLIL::Wire *w1 = module->addWire(NEW_ID, width); - RTLIL::Wire *w2 = module->addWire(NEW_ID, width); + RTLIL::Wire *w1 = module->addWire(NEW_TWINE, width); + RTLIL::Wire *w2 = module->addWire(NEW_TWINE, width); - RTLIL::Cell *cell = module->addCell(NEW_ID, ID($fa)); + RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($fa)); cell->setParam(ID::WIDTH, width); - cell->setPort(ID::A, in1); - cell->setPort(ID::B, in2); - cell->setPort(ID::C, in3); - cell->setPort(ID::Y, w1); - cell->setPort(ID::X, w2); + cell->setPort(TW::A, in1); + cell->setPort(TW::B, in2); + cell->setPort(TW::C, in3); + cell->setPort(TW::Y, w1); + cell->setPort(TW::X, w2); out1 = {out_zeros_msb, w1, out_zeros_lsb}; out2 = {out_zeros_msb, w2, out_zeros_lsb}; @@ -237,23 +237,23 @@ struct MaccmapWorker } - RTLIL::Cell *c = module->addCell(NEW_ID, ID($alu)); - c->setPort(ID::A, summands.front()); - c->setPort(ID::B, summands.back()); - c->setPort(ID::CI, State::S0); - c->setPort(ID::BI, State::S0); - c->setPort(ID::Y, module->addWire(NEW_ID, width)); - c->setPort(ID::X, module->addWire(NEW_ID, width)); - c->setPort(ID::CO, module->addWire(NEW_ID, width)); + RTLIL::Cell *c = module->addCell(NEW_TWINE, ID($alu)); + c->setPort(TW::A, summands.front()); + c->setPort(TW::B, summands.back()); + c->setPort(TW::CI, State::S0); + c->setPort(TW::BI, State::S0); + c->setPort(TW::Y, module->addWire(NEW_TWINE, width)); + c->setPort(TW::X, module->addWire(NEW_TWINE, width)); + c->setPort(TW::CO, module->addWire(NEW_TWINE, width)); c->fixup_parameters(); if (!tree_sum_bits.empty()) { - c->setPort(ID::CI, tree_sum_bits.back()); + c->setPort(TW::CI, tree_sum_bits.back()); tree_sum_bits.pop_back(); } log_assert(tree_sum_bits.empty()); - return c->getPort(ID::Y); + return c->getPort(TW::Y); } }; @@ -264,17 +264,17 @@ extern void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap = false void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap) { - int width = GetSize(cell->getPort(ID::Y)); + int width = GetSize(cell->getPort(TW::Y)); Macc macc; macc.from_cell(cell); RTLIL::SigSpec all_input_bits; - all_input_bits.append(cell->getPort(ID::A)); - all_input_bits.append(cell->getPort(ID::B)); + all_input_bits.append(cell->getPort(TW::A)); + all_input_bits.append(cell->getPort(TW::B)); if (all_input_bits.to_sigbit_set().count(RTLIL::Sx)) { - module->connect(cell->getPort(ID::Y), RTLIL::SigSpec(RTLIL::Sx, width)); + module->connect(cell->getPort(TW::Y), RTLIL::SigSpec(RTLIL::Sx, width)); return; } @@ -296,7 +296,7 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap) for (auto &term : macc.terms) { summand_t this_summand; if (GetSize(term.in_b)) { - this_summand.first = module->addWire(NEW_ID, width); + this_summand.first = module->addWire(NEW_TWINE, width); module->addMul(NEW_ID, term.in_a, term.in_b, this_summand.first, term.is_signed); } else if (GetSize(term.in_a) == 1 && GetSize(term.in_b) == 0 && !term.is_signed && !term.do_subtract) { // Mimic old 'bit_terms' treatment in case it's relevant for performance, @@ -304,7 +304,7 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap) bit_terms.append(term.in_a); continue; } else if (GetSize(term.in_a) != width) { - this_summand.first = module->addWire(NEW_ID, width); + this_summand.first = module->addWire(NEW_TWINE, width); module->addPos(NEW_ID, term.in_a, this_summand.first, term.is_signed); } else { this_summand.first = term.in_a; @@ -325,7 +325,7 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap) for (int i = 0; i < GetSize(summands); i += 2) { if (i+1 < GetSize(summands)) { summand_t this_summand; - this_summand.first = module->addWire(NEW_ID, width); + this_summand.first = module->addWire(NEW_TWINE, width); this_summand.second = summands[i].second && summands[i+1].second; if (summands[i].second == summands[i+1].second) module->addAdd(NEW_ID, summands[i].first, summands[i+1].first, this_summand.first); @@ -343,9 +343,9 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap) } if (summands.front().second) - module->addNeg(NEW_ID, summands.front().first, cell->getPort(ID::Y)); + module->addNeg(NEW_ID, summands.front().first, cell->getPort(TW::Y)); else - module->connect(cell->getPort(ID::Y), summands.front().first); + module->connect(cell->getPort(TW::Y), summands.front().first); } else { @@ -366,7 +366,7 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap) for (auto bit : bit_terms) worker.add(bit, 0); - module->connect(cell->getPort(ID::Y), worker.synth()); + module->connect(cell->getPort(TW::Y), worker.synth()); } } diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc index 719a346d8..04ff966f7 100644 --- a/passes/techmap/muxcover.cc +++ b/passes/techmap/muxcover.cc @@ -122,7 +122,7 @@ struct MuxcoverWorker } } if (cell->type == ID($_MUX_)) - sig_to_mux[sigmap(cell->getPort(ID::Y))] = cell; + sig_to_mux[sigmap(cell->getPort(TW::Y))] = cell; } log(" Treeifying %d MUXes:\n", GetSize(sig_to_mux)); @@ -141,8 +141,8 @@ struct MuxcoverWorker if (sig_to_mux.count(bit) && (bit == rootsig || !roots.count(bit))) { Cell *c = sig_to_mux.at(bit); tree.muxes[bit] = c; - wavefront.insert(sigmap(c->getPort(ID::A))); - wavefront.insert(sigmap(c->getPort(ID::B))); + wavefront.insert(sigmap(c->getPort(TW::A))); + wavefront.insert(sigmap(c->getPort(TW::B))); } } @@ -185,7 +185,7 @@ struct MuxcoverWorker tuple key(A, B, sel); if (decode_mux_cache.count(key) == 0) { auto &entry = decode_mux_cache[key]; - std::get<0>(entry) = module->addWire(NEW_ID); + std::get<0>(entry) = module->addWire(NEW_TWINE); std::get<2>(entry) = false; decode_mux_reverse_cache[std::get<0>(entry)] = key; } @@ -513,69 +513,69 @@ struct MuxcoverWorker if (GetSize(mux.inputs) == 2) { count_muxes_by_type[0]++; - Cell *cell = module->addCell(NEW_ID, ID($_MUX_)); - cell->setPort(ID::A, mux.inputs[0]); - cell->setPort(ID::B, mux.inputs[1]); - cell->setPort(ID::S, mux.selects[0]); - cell->setPort(ID::Y, bit); + Cell *cell = module->addCell(NEW_TWINE, ID($_MUX_)); + cell->setPort(TW::A, mux.inputs[0]); + cell->setPort(TW::B, mux.inputs[1]); + cell->setPort(TW::S, mux.selects[0]); + cell->setPort(TW::Y, bit); return; } if (GetSize(mux.inputs) == 4) { count_muxes_by_type[1]++; - Cell *cell = module->addCell(NEW_ID, ID($_MUX4_)); - cell->setPort(ID::A, mux.inputs[0]); - cell->setPort(ID::B, mux.inputs[1]); - cell->setPort(ID::C, mux.inputs[2]); - cell->setPort(ID::D, mux.inputs[3]); - cell->setPort(ID::S, mux.selects[0]); - cell->setPort(ID::T, mux.selects[1]); - cell->setPort(ID::Y, bit); + Cell *cell = module->addCell(NEW_TWINE, ID($_MUX4_)); + cell->setPort(TW::A, mux.inputs[0]); + cell->setPort(TW::B, mux.inputs[1]); + cell->setPort(TW::C, mux.inputs[2]); + cell->setPort(TW::D, mux.inputs[3]); + cell->setPort(TW::S, mux.selects[0]); + cell->setPort(TW::T, mux.selects[1]); + cell->setPort(TW::Y, bit); return; } if (GetSize(mux.inputs) == 8) { count_muxes_by_type[2]++; - Cell *cell = module->addCell(NEW_ID, ID($_MUX8_)); - cell->setPort(ID::A, mux.inputs[0]); - cell->setPort(ID::B, mux.inputs[1]); - cell->setPort(ID::C, mux.inputs[2]); - cell->setPort(ID::D, mux.inputs[3]); - cell->setPort(ID::E, mux.inputs[4]); - cell->setPort(ID::F, mux.inputs[5]); - cell->setPort(ID::G, mux.inputs[6]); - cell->setPort(ID::H, mux.inputs[7]); - cell->setPort(ID::S, mux.selects[0]); - cell->setPort(ID::T, mux.selects[1]); - cell->setPort(ID::U, mux.selects[2]); - cell->setPort(ID::Y, bit); + Cell *cell = module->addCell(NEW_TWINE, ID($_MUX8_)); + cell->setPort(TW::A, mux.inputs[0]); + cell->setPort(TW::B, mux.inputs[1]); + cell->setPort(TW::C, mux.inputs[2]); + cell->setPort(TW::D, mux.inputs[3]); + cell->setPort(TW::E, mux.inputs[4]); + cell->setPort(TW::F, mux.inputs[5]); + cell->setPort(TW::G, mux.inputs[6]); + cell->setPort(TW::H, mux.inputs[7]); + cell->setPort(TW::S, mux.selects[0]); + cell->setPort(TW::T, mux.selects[1]); + cell->setPort(TW::U, mux.selects[2]); + cell->setPort(TW::Y, bit); return; } if (GetSize(mux.inputs) == 16) { count_muxes_by_type[3]++; - Cell *cell = module->addCell(NEW_ID, ID($_MUX16_)); - cell->setPort(ID::A, mux.inputs[0]); - cell->setPort(ID::B, mux.inputs[1]); - cell->setPort(ID::C, mux.inputs[2]); - cell->setPort(ID::D, mux.inputs[3]); - cell->setPort(ID::E, mux.inputs[4]); - cell->setPort(ID::F, mux.inputs[5]); - cell->setPort(ID::G, mux.inputs[6]); - cell->setPort(ID::H, mux.inputs[7]); - cell->setPort(ID::I, mux.inputs[8]); - cell->setPort(ID::J, mux.inputs[9]); - cell->setPort(ID::K, mux.inputs[10]); - cell->setPort(ID::L, mux.inputs[11]); - cell->setPort(ID::M, mux.inputs[12]); - cell->setPort(ID::N, mux.inputs[13]); - cell->setPort(ID::O, mux.inputs[14]); - cell->setPort(ID::P, mux.inputs[15]); - cell->setPort(ID::S, mux.selects[0]); - cell->setPort(ID::T, mux.selects[1]); - cell->setPort(ID::U, mux.selects[2]); - cell->setPort(ID::V, mux.selects[3]); - cell->setPort(ID::Y, bit); + Cell *cell = module->addCell(NEW_TWINE, ID($_MUX16_)); + cell->setPort(TW::A, mux.inputs[0]); + cell->setPort(TW::B, mux.inputs[1]); + cell->setPort(TW::C, mux.inputs[2]); + cell->setPort(TW::D, mux.inputs[3]); + cell->setPort(TW::E, mux.inputs[4]); + cell->setPort(TW::F, mux.inputs[5]); + cell->setPort(TW::G, mux.inputs[6]); + cell->setPort(TW::H, mux.inputs[7]); + cell->setPort(TW::I, mux.inputs[8]); + cell->setPort(TW::J, mux.inputs[9]); + cell->setPort(TW::K, mux.inputs[10]); + cell->setPort(TW::L, mux.inputs[11]); + cell->setPort(TW::M, mux.inputs[12]); + cell->setPort(TW::N, mux.inputs[13]); + cell->setPort(TW::O, mux.inputs[14]); + cell->setPort(TW::P, mux.inputs[15]); + cell->setPort(TW::S, mux.selects[0]); + cell->setPort(TW::T, mux.selects[1]); + cell->setPort(TW::U, mux.selects[2]); + cell->setPort(TW::V, mux.selects[3]); + cell->setPort(TW::Y, bit); return; } diff --git a/passes/techmap/nlutmap.cc b/passes/techmap/nlutmap.cc index c823f10fe..7737a629d 100644 --- a/passes/techmap/nlutmap.cc +++ b/passes/techmap/nlutmap.cc @@ -85,7 +85,7 @@ struct NlutmapWorker if (cell->type != ID($lut) || mapped_cells.count(cell)) continue; - if (GetSize(cell->getPort(ID::A)) == lut_size || lut_size == 2) + if (GetSize(cell->getPort(TW::A)) == lut_size || lut_size == 2) candidate_ratings[cell] = 0; for (auto &conn : cell->connections()) diff --git a/passes/techmap/pmuxtree.cc b/passes/techmap/pmuxtree.cc index ff6bb549b..d916c8608 100644 --- a/passes/techmap/pmuxtree.cc +++ b/passes/techmap/pmuxtree.cc @@ -92,18 +92,18 @@ struct PmuxtreePass : public Pass { if (cell->type != ID($pmux)) continue; - SigSpec sig_data = cell->getPort(ID::B); - SigSpec sig_sel = cell->getPort(ID::S); + SigSpec sig_data = cell->getPort(TW::B); + SigSpec sig_sel = cell->getPort(TW::S); - if (!cell->getPort(ID::A).is_fully_undef()) { - sig_data.append(cell->getPort(ID::A)); + if (!cell->getPort(TW::A).is_fully_undef()) { + sig_data.append(cell->getPort(TW::A)); SigSpec sig_sel_or = module->ReduceOr(NEW_ID, sig_sel); sig_sel.append(module->Not(NEW_ID, sig_sel_or)); } SigSpec result, result_or; result = recursive_mux_generator(module, sig_data, sig_sel, result_or); - module->connect(cell->getPort(ID::Y), result); + module->connect(cell->getPort(TW::Y), result); module->remove(cell); } } diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 9f4e307f9..3c7e78e4d 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -72,12 +72,12 @@ struct ShregmapTechGreenpak4 : ShregmapTech bool fixup(Cell *cell, dict &taps) { - auto D = cell->getPort(ID::D); - auto C = cell->getPort(ID::C); + auto D = cell->getPort(TW::D); + auto C = cell->getPort(TW::C); - auto newcell = cell->module->addCell(NEW_ID, ID(GP_SHREG)); + auto newcell = cell->module->addCell(NEW_TWINE, ID(GP_SHREG)); newcell->setPort(ID(nRST), State::S1); - newcell->setPort(ID::CLK, C); + newcell->setPort(TW::CLK, C); newcell->setPort(ID(IN), D); int i = 0; @@ -142,7 +142,7 @@ struct ShregmapWorker // so that it can be identified as another chain // (omitting this common flop) // Link: https://github.com/YosysHQ/yosys/pull/1085 - Wire *wire = module->addWire(NEW_ID); + Wire *wire = module->addWire(NEW_TWINE); module->connect(wire, d_bit); sigmap.add(wire, d_bit); sigbit_chain_next.insert(std::make_pair(wire, cell)); diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index ab36abd20..2837e0989 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -34,23 +34,23 @@ static void transfer_src (Cell* to, const Cell* from) { void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->getPort(ID::A); - RTLIL::SigSpec sig_y = cell->getPort(ID::Y); + RTLIL::SigSpec sig_a = cell->getPort(TW::A); + RTLIL::SigSpec sig_y = cell->getPort(TW::Y); sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool()); for (int i = 0; i < GetSize(sig_y); i++) { - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); + RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_NOT_)); transfer_src(gate, cell); - gate->setPort(ID::A, sig_a[i]); - gate->setPort(ID::Y, sig_y[i]); + gate->setPort(TW::A, sig_a[i]); + gate->setPort(TW::Y, sig_y[i]); } } void simplemap_buf(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->getPort(ID::A); - RTLIL::SigSpec sig_y = cell->getPort(ID::Y); + RTLIL::SigSpec sig_a = cell->getPort(TW::A); + RTLIL::SigSpec sig_y = cell->getPort(TW::Y); if (sig_a.has_const(State::Sz)) { SigSpec new_a; @@ -72,8 +72,8 @@ void simplemap_buf(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->getPort(ID::A); - RTLIL::SigSpec sig_y = cell->getPort(ID::Y); + RTLIL::SigSpec sig_a = cell->getPort(TW::A); + RTLIL::SigSpec sig_y = cell->getPort(TW::Y); sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool()); @@ -82,9 +82,9 @@ void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->getPort(ID::A); - RTLIL::SigSpec sig_b = cell->getPort(ID::B); - RTLIL::SigSpec sig_y = cell->getPort(ID::Y); + RTLIL::SigSpec sig_a = cell->getPort(TW::A); + RTLIL::SigSpec sig_b = cell->getPort(TW::B); + RTLIL::SigSpec sig_y = cell->getPort(TW::Y); if (cell->type != ID($bweqx)) { sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool()); @@ -100,18 +100,18 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) log_assert(!gate_type.empty()); for (int i = 0; i < GetSize(sig_y); i++) { - RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); + RTLIL::Cell *gate = module->addCell(NEW_TWINE, gate_type); transfer_src(gate, cell); - gate->setPort(ID::A, sig_a[i]); - gate->setPort(ID::B, sig_b[i]); - gate->setPort(ID::Y, sig_y[i]); + gate->setPort(TW::A, sig_a[i]); + gate->setPort(TW::B, sig_b[i]); + gate->setPort(TW::Y, sig_y[i]); } } void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->getPort(ID::A); - RTLIL::SigSpec sig_y = cell->getPort(ID::Y); + RTLIL::SigSpec sig_a = cell->getPort(TW::A); + RTLIL::SigSpec sig_y = cell->getPort(TW::Y); if (sig_y.size() == 0) return; @@ -142,7 +142,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) while (sig_a.size() > 1) { - RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.size() / 2); + RTLIL::SigSpec sig_t = module->addWire(NEW_TWINE, sig_a.size() / 2); for (int i = 0; i < sig_a.size(); i += 2) { @@ -151,11 +151,11 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) continue; } - RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); + RTLIL::Cell *gate = module->addCell(NEW_TWINE, gate_type); transfer_src(gate, cell); - gate->setPort(ID::A, sig_a[i]); - gate->setPort(ID::B, sig_a[i+1]); - gate->setPort(ID::Y, sig_t[i/2]); + gate->setPort(TW::A, sig_a[i]); + gate->setPort(TW::B, sig_a[i+1]); + gate->setPort(TW::Y, sig_t[i/2]); last_output_cell = gate; } @@ -163,11 +163,11 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) } if (cell->type == ID($reduce_xnor)) { - RTLIL::SigSpec sig_t = module->addWire(NEW_ID); - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); + RTLIL::SigSpec sig_t = module->addWire(NEW_TWINE); + RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_NOT_)); transfer_src(gate, cell); - gate->setPort(ID::A, sig_a); - gate->setPort(ID::Y, sig_t); + gate->setPort(TW::A, sig_a); + gate->setPort(TW::Y, sig_t); last_output_cell = gate; sig_a = sig_t; } @@ -175,7 +175,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) if (last_output_cell == NULL) { module->connect(RTLIL::SigSig(sig_y, sig_a)); } else { - last_output_cell->setPort(ID::Y, sig_y); + last_output_cell->setPort(TW::Y, sig_y); } } @@ -183,7 +183,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell { while (sig.size() > 1) { - RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.size() / 2); + RTLIL::SigSpec sig_t = module->addWire(NEW_TWINE, sig.size() / 2); for (int i = 0; i < sig.size(); i += 2) { @@ -192,11 +192,11 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell continue; } - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_)); + RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_OR_)); transfer_src(gate, cell); - gate->setPort(ID::A, sig[i]); - gate->setPort(ID::B, sig[i+1]); - gate->setPort(ID::Y, sig_t[i/2]); + gate->setPort(TW::A, sig[i]); + gate->setPort(TW::B, sig[i+1]); + gate->setPort(TW::Y, sig_t[i/2]); } sig = sig_t; @@ -208,10 +208,10 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->getPort(ID::A); + RTLIL::SigSpec sig_a = cell->getPort(TW::A); logic_reduce(module, sig_a, cell); - RTLIL::SigSpec sig_y = cell->getPort(ID::Y); + RTLIL::SigSpec sig_y = cell->getPort(TW::Y); if (sig_y.size() == 0) return; @@ -221,21 +221,21 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) sig_y = sig_y.extract(0, 1); } - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); + RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_NOT_)); transfer_src(gate, cell); - gate->setPort(ID::A, sig_a); - gate->setPort(ID::Y, sig_y); + gate->setPort(TW::A, sig_a); + gate->setPort(TW::Y, sig_y); } void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->getPort(ID::A); + RTLIL::SigSpec sig_a = cell->getPort(TW::A); logic_reduce(module, sig_a, cell); - RTLIL::SigSpec sig_b = cell->getPort(ID::B); + RTLIL::SigSpec sig_b = cell->getPort(TW::B); logic_reduce(module, sig_b, cell); - RTLIL::SigSpec sig_y = cell->getPort(ID::Y); + RTLIL::SigSpec sig_y = cell->getPort(TW::Y); if (sig_y.size() == 0) return; @@ -250,28 +250,28 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) if (cell->type == ID($logic_or)) gate_type = ID($_OR_); log_assert(!gate_type.empty()); - RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); + RTLIL::Cell *gate = module->addCell(NEW_TWINE, gate_type); transfer_src(gate, cell); - gate->setPort(ID::A, sig_a); - gate->setPort(ID::B, sig_b); - gate->setPort(ID::Y, sig_y); + gate->setPort(TW::A, sig_a); + gate->setPort(TW::B, sig_b); + gate->setPort(TW::Y, sig_y); } void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->getPort(ID::A); - RTLIL::SigSpec sig_b = cell->getPort(ID::B); - RTLIL::SigSpec sig_y = cell->getPort(ID::Y); + RTLIL::SigSpec sig_a = cell->getPort(TW::A); + RTLIL::SigSpec sig_b = cell->getPort(TW::B); + RTLIL::SigSpec sig_y = cell->getPort(TW::Y); bool is_signed = cell->parameters.at(ID::A_SIGNED).as_bool(); bool is_ne = cell->type.in(ID($ne), ID($nex)); - RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b))); + RTLIL::SigSpec xor_out = module->addWire(NEW_TWINE, max(GetSize(sig_a), GetSize(sig_b))); RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed); transfer_src(xor_cell, cell); simplemap_bitop(module, xor_cell); module->remove(xor_cell); - RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID); + RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_TWINE); RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out); transfer_src(reduce_cell, cell); simplemap_reduce(module, reduce_cell); @@ -287,101 +287,101 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->getPort(ID::A); - RTLIL::SigSpec sig_b = cell->getPort(ID::B); - RTLIL::SigSpec sig_y = cell->getPort(ID::Y); + RTLIL::SigSpec sig_a = cell->getPort(TW::A); + RTLIL::SigSpec sig_b = cell->getPort(TW::B); + RTLIL::SigSpec sig_y = cell->getPort(TW::Y); for (int i = 0; i < GetSize(sig_y); i++) { - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); + RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_MUX_)); transfer_src(gate, cell); - gate->setPort(ID::A, sig_a[i]); - gate->setPort(ID::B, sig_b[i]); - gate->setPort(ID::S, cell->getPort(ID::S)); - gate->setPort(ID::Y, sig_y[i]); + gate->setPort(TW::A, sig_a[i]); + gate->setPort(TW::B, sig_b[i]); + gate->setPort(TW::S, cell->getPort(TW::S)); + gate->setPort(TW::Y, sig_y[i]); } } void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->getPort(ID::A); - RTLIL::SigSpec sig_b = cell->getPort(ID::B); - RTLIL::SigSpec sig_s = cell->getPort(ID::S); - RTLIL::SigSpec sig_y = cell->getPort(ID::Y); + RTLIL::SigSpec sig_a = cell->getPort(TW::A); + RTLIL::SigSpec sig_b = cell->getPort(TW::B); + RTLIL::SigSpec sig_s = cell->getPort(TW::S); + RTLIL::SigSpec sig_y = cell->getPort(TW::Y); for (int i = 0; i < GetSize(sig_y); i++) { - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); + RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_MUX_)); transfer_src(gate, cell); - gate->setPort(ID::A, sig_a[i]); - gate->setPort(ID::B, sig_b[i]); - gate->setPort(ID::S, sig_s[i]); - gate->setPort(ID::Y, sig_y[i]); + gate->setPort(TW::A, sig_a[i]); + gate->setPort(TW::B, sig_b[i]); + gate->setPort(TW::S, sig_s[i]); + gate->setPort(TW::Y, sig_y[i]); } } void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->getPort(ID::A); - RTLIL::SigSpec sig_e = cell->getPort(ID::EN); - RTLIL::SigSpec sig_y = cell->getPort(ID::Y); + RTLIL::SigSpec sig_a = cell->getPort(TW::A); + RTLIL::SigSpec sig_e = cell->getPort(TW::EN); + RTLIL::SigSpec sig_y = cell->getPort(TW::Y); for (int i = 0; i < GetSize(sig_y); i++) { - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_TBUF_)); + RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_TBUF_)); transfer_src(gate, cell); - gate->setPort(ID::A, sig_a[i]); - gate->setPort(ID::E, sig_e); - gate->setPort(ID::Y, sig_y[i]); + gate->setPort(TW::A, sig_a[i]); + gate->setPort(TW::E, sig_e); + gate->setPort(TW::Y, sig_y[i]); } } void simplemap_bmux(RTLIL::Module *module, RTLIL::Cell *cell) { - SigSpec sel = cell->getPort(ID::S); - SigSpec data = cell->getPort(ID::A); - int width = GetSize(cell->getPort(ID::Y)); + SigSpec sel = cell->getPort(TW::S); + SigSpec data = cell->getPort(TW::A); + int width = GetSize(cell->getPort(TW::Y)); for (int idx = 0; idx < GetSize(sel); idx++) { - SigSpec new_data = module->addWire(NEW_ID, GetSize(data)/2); + SigSpec new_data = module->addWire(NEW_TWINE, GetSize(data)/2); for (int i = 0; i < GetSize(new_data); i += width) { for (int k = 0; k < width; k++) { - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); + RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_MUX_)); transfer_src(gate, cell); - gate->setPort(ID::A, data[i*2+k]); - gate->setPort(ID::B, data[i*2+width+k]); - gate->setPort(ID::S, sel[idx]); - gate->setPort(ID::Y, new_data[i+k]); + gate->setPort(TW::A, data[i*2+k]); + gate->setPort(TW::B, data[i*2+width+k]); + gate->setPort(TW::S, sel[idx]); + gate->setPort(TW::Y, new_data[i+k]); } } data = new_data; } - module->connect(cell->getPort(ID::Y), data); + module->connect(cell->getPort(TW::Y), data); } void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell) { - SigSpec lut_ctrl = cell->getPort(ID::A); + SigSpec lut_ctrl = cell->getPort(TW::A); SigSpec lut_data = cell->getParam(ID::LUT); lut_data.extend_u0(1 << cell->getParam(ID::WIDTH).as_int()); for (int idx = 0; GetSize(lut_data) > 1; idx++) { - SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2); + SigSpec new_lut_data = module->addWire(NEW_TWINE, GetSize(lut_data)/2); for (int i = 0; i < GetSize(lut_data); i += 2) { - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); + RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_MUX_)); transfer_src(gate, cell); - gate->setPort(ID::A, lut_data[i]); - gate->setPort(ID::B, lut_data[i+1]); - gate->setPort(ID::S, lut_ctrl[idx]); - gate->setPort(ID::Y, new_lut_data[i/2]); + gate->setPort(TW::A, lut_data[i]); + gate->setPort(TW::B, lut_data[i+1]); + gate->setPort(TW::S, lut_ctrl[idx]); + gate->setPort(TW::Y, new_lut_data[i/2]); } lut_data = new_lut_data; } - module->connect(cell->getPort(ID::Y), lut_data); + module->connect(cell->getPort(TW::Y), lut_data); } void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell) { - SigSpec ctrl = cell->getPort(ID::A); + SigSpec ctrl = cell->getPort(TW::A); SigSpec table = cell->getParam(ID::TABLE); int width = cell->getParam(ID::WIDTH).as_int(); @@ -406,22 +406,22 @@ void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell) products.append(GetSize(in) > 0 ? module->Eq(NEW_ID, in, pat) : State::S1); } - module->connect(cell->getPort(ID::Y), module->ReduceOr(NEW_ID, products)); + module->connect(cell->getPort(TW::Y), module->ReduceOr(NEW_ID, products)); } void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell) { int offset = cell->parameters.at(ID::OFFSET).as_int(); - RTLIL::SigSpec sig_a = cell->getPort(ID::A); - RTLIL::SigSpec sig_y = cell->getPort(ID::Y); + RTLIL::SigSpec sig_a = cell->getPort(TW::A); + RTLIL::SigSpec sig_y = cell->getPort(TW::Y); module->connect(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size()))); } void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_ab = cell->getPort(ID::A); - sig_ab.append(cell->getPort(ID::B)); - RTLIL::SigSpec sig_y = cell->getPort(ID::Y); + RTLIL::SigSpec sig_ab = cell->getPort(TW::A); + sig_ab.append(cell->getPort(TW::B)); + RTLIL::SigSpec sig_y = cell->getPort(TW::Y); module->connect(RTLIL::SigSig(sig_y, sig_ab)); } @@ -437,10 +437,10 @@ void simplemap_ff(RTLIL::Module *, RTLIL::Cell *cell) void simplemap_pmux(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->getPort(ID::A); - RTLIL::SigSpec sig_b = cell->getPort(ID::B); - RTLIL::SigSpec sig_s = cell->getPort(ID::S); - RTLIL::SigSpec sig_y = cell->getPort(ID::Y); + RTLIL::SigSpec sig_a = cell->getPort(TW::A); + RTLIL::SigSpec sig_b = cell->getPort(TW::B); + RTLIL::SigSpec sig_s = cell->getPort(TW::S); + RTLIL::SigSpec sig_y = cell->getPort(TW::Y); int width = GetSize(sig_a); int s_width = GetSize(sig_s); @@ -454,13 +454,13 @@ void simplemap_pmux(RTLIL::Module *module, RTLIL::Cell *cell) // Implement: B_AND_BITS = B_AND_S[WIDTH*j+i] for (int j = 0; j < s_width; j++) { - RTLIL::Cell *and_gate = module->addCell(NEW_ID, ID($_AND_)); + RTLIL::Cell *and_gate = module->addCell(NEW_TWINE, ID($_AND_)); transfer_src(and_gate, cell); - and_gate->setPort(ID::A, sig_b[j * width + i]); - and_gate->setPort(ID::B, sig_s[j]); + and_gate->setPort(TW::A, sig_b[j * width + i]); + and_gate->setPort(TW::B, sig_s[j]); - RTLIL::SigSpec and_y = module->addWire(NEW_ID, 1); - and_gate->setPort(ID::Y, and_y); + RTLIL::SigSpec and_y = module->addWire(NEW_TWINE, 1); + and_gate->setPort(TW::Y, and_y); b_and_bits.append(and_y); } @@ -468,12 +468,12 @@ void simplemap_pmux(RTLIL::Module *module, RTLIL::Cell *cell) logic_reduce(module, b_and_bits, cell); // Implement: Y[i] = |S ? Y_B[i] : A[i] - RTLIL::Cell *mux_gate = module->addCell(NEW_ID, ID($_MUX_)); + RTLIL::Cell *mux_gate = module->addCell(NEW_TWINE, ID($_MUX_)); transfer_src(mux_gate, cell); - mux_gate->setPort(ID::A, sig_a[i]); - mux_gate->setPort(ID::B, b_and_bits); - mux_gate->setPort(ID::S, any_s); - mux_gate->setPort(ID::Y, sig_y[i]); + mux_gate->setPort(TW::A, sig_a[i]); + mux_gate->setPort(TW::B, b_and_bits); + mux_gate->setPort(TW::S, any_s); + mux_gate->setPort(TW::Y, sig_y[i]); } } diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 0b5ef497b..e77ee3374 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -247,7 +247,7 @@ struct TechmapWorker for (auto &it : cell->connections()) { - IdString portname = it.first; + TwineRef portname = it.first; if (positional_ports.count(portname) > 0) portname = positional_ports.at(portname); if (tpl->wire(portname) == nullptr || tpl->wire(portname)->port_id == 0) { diff --git a/passes/techmap/tribuf.cc b/passes/techmap/tribuf.cc index c7555b3d8..3810d0bfc 100644 --- a/passes/techmap/tribuf.cc +++ b/passes/techmap/tribuf.cc @@ -66,38 +66,38 @@ struct TribufWorker { for (auto cell : module->selected_cells()) { if (cell->type == ID($tribuf)) - tribuf_cells[sigmap(cell->getPort(ID::Y))].push_back(cell); + tribuf_cells[sigmap(cell->getPort(TW::Y))].push_back(cell); if (cell->type == ID($_TBUF_)) - tribuf_cells[sigmap(cell->getPort(ID::Y))].push_back(cell); + tribuf_cells[sigmap(cell->getPort(TW::Y))].push_back(cell); if (cell->type.in(ID($mux), ID($_MUX_))) { IdString en_port = cell->type == ID($mux) ? ID::EN : ID::E; IdString tri_type = cell->type == ID($mux) ? ID($tribuf) : ID($_TBUF_); - if (is_all_z(cell->getPort(ID::A)) && is_all_z(cell->getPort(ID::B))) { + if (is_all_z(cell->getPort(TW::A)) && is_all_z(cell->getPort(TW::B))) { module->remove(cell); continue; } - if (is_all_z(cell->getPort(ID::A))) { - cell->setPort(ID::A, cell->getPort(ID::B)); - cell->setPort(en_port, cell->getPort(ID::S)); - cell->unsetPort(ID::B); - cell->unsetPort(ID::S); + if (is_all_z(cell->getPort(TW::A))) { + cell->setPort(TW::A, cell->getPort(TW::B)); + cell->setPort(en_port, cell->getPort(TW::S)); + cell->unsetPort(TW::B); + cell->unsetPort(TW::S); cell->type = tri_type; - tribuf_cells[sigmap(cell->getPort(ID::Y))].push_back(cell); + tribuf_cells[sigmap(cell->getPort(TW::Y))].push_back(cell); module->design->scratchpad_set_bool("tribuf.added_something", true); continue; } - if (is_all_z(cell->getPort(ID::B))) { - cell->setPort(en_port, module->Not(NEW_ID, cell->getPort(ID::S))); - cell->unsetPort(ID::B); - cell->unsetPort(ID::S); + if (is_all_z(cell->getPort(TW::B))) { + cell->setPort(en_port, module->Not(NEW_ID, cell->getPort(TW::S))); + cell->unsetPort(TW::B); + cell->unsetPort(TW::S); cell->type = tri_type; - tribuf_cells[sigmap(cell->getPort(ID::Y))].push_back(cell); + tribuf_cells[sigmap(cell->getPort(TW::Y))].push_back(cell); module->design->scratchpad_set_bool("tribuf.added_something", true); continue; } @@ -131,12 +131,12 @@ struct TribufWorker { if (other_cell == cell) continue; else if (other_cell->type == ID($tribuf)) - others_s.append(other_cell->getPort(ID::EN)); + others_s.append(other_cell->getPort(TW::EN)); else - others_s.append(other_cell->getPort(ID::E)); + others_s.append(other_cell->getPort(TW::E)); } - auto cell_s = cell->type == ID($tribuf) ? cell->getPort(ID::EN) : cell->getPort(ID::E); + auto cell_s = cell->type == ID($tribuf) ? cell->getPort(TW::EN) : cell->getPort(TW::E); auto other_s = module->ReduceOr(NEW_ID, others_s); @@ -155,10 +155,10 @@ struct TribufWorker { SigSpec pmux_b, pmux_s; for (auto cell : it.second) { if (cell->type == ID($tribuf)) - pmux_s.append(cell->getPort(ID::EN)); + pmux_s.append(cell->getPort(TW::EN)); else - pmux_s.append(cell->getPort(ID::E)); - pmux_b.append(cell->getPort(ID::A)); + pmux_s.append(cell->getPort(TW::E)); + pmux_b.append(cell->getPort(TW::A)); module->remove(cell); } diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 3f2588bd1..1182f4fee 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -53,22 +53,22 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce wire = module->addWire(ID::A); wire->width = width; wire->port_input = true; - cell->setPort(ID::A, wire); + cell->setPort(TW::A, wire); wire = module->addWire(ID::B); wire->width = width * swidth; wire->port_input = true; - cell->setPort(ID::B, wire); + cell->setPort(TW::B, wire); wire = module->addWire(ID::S); wire->width = swidth; wire->port_input = true; - cell->setPort(ID::S, wire); + cell->setPort(TW::S, wire); wire = module->addWire(ID::Y); wire->width = width; wire->port_output = true; - cell->setPort(ID::Y, wire); + cell->setPort(TW::Y, wire); } if (cell_type.in(ID($_MUX_), ID($_NMUX_))) @@ -76,22 +76,22 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce wire = module->addWire(ID::A); wire->width = 1; wire->port_input = true; - cell->setPort(ID::A, wire); + cell->setPort(TW::A, wire); wire = module->addWire(ID::B); wire->width = 1; wire->port_input = true; - cell->setPort(ID::B, wire); + cell->setPort(TW::B, wire); wire = module->addWire(ID::S); wire->width = 1; wire->port_input = true; - cell->setPort(ID::S, wire); + cell->setPort(TW::S, wire); wire = module->addWire(ID::Y); wire->width = 1; wire->port_output = true; - cell->setPort(ID::Y, wire); + cell->setPort(TW::Y, wire); } if (cell_type == ID($bmux)) @@ -102,17 +102,17 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce wire = module->addWire(ID::A); wire->width = width << swidth; wire->port_input = true; - cell->setPort(ID::A, wire); + cell->setPort(TW::A, wire); wire = module->addWire(ID::S); wire->width = swidth; wire->port_input = true; - cell->setPort(ID::S, wire); + cell->setPort(TW::S, wire); wire = module->addWire(ID::Y); wire->width = width; wire->port_output = true; - cell->setPort(ID::Y, wire); + cell->setPort(TW::Y, wire); } if (cell_type == ID($demux)) @@ -123,17 +123,17 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce wire = module->addWire(ID::A); wire->width = width; wire->port_input = true; - cell->setPort(ID::A, wire); + cell->setPort(TW::A, wire); wire = module->addWire(ID::S); wire->width = swidth; wire->port_input = true; - cell->setPort(ID::S, wire); + cell->setPort(TW::S, wire); wire = module->addWire(ID::Y); wire->width = width << swidth; wire->port_output = true; - cell->setPort(ID::Y, wire); + cell->setPort(TW::Y, wire); } if (cell_type == ID($fa)) @@ -143,27 +143,27 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce wire = module->addWire(ID::A); wire->width = width; wire->port_input = true; - cell->setPort(ID::A, wire); + cell->setPort(TW::A, wire); wire = module->addWire(ID::B); wire->width = width; wire->port_input = true; - cell->setPort(ID::B, wire); + cell->setPort(TW::B, wire); wire = module->addWire(ID::C); wire->width = width; wire->port_input = true; - cell->setPort(ID::C, wire); + cell->setPort(TW::C, wire); wire = module->addWire(ID::X); wire->width = width; wire->port_output = true; - cell->setPort(ID::X, wire); + cell->setPort(TW::X, wire); wire = module->addWire(ID::Y); wire->width = width; wire->port_output = true; - cell->setPort(ID::Y, wire); + cell->setPort(TW::Y, wire); } if (cell_type == ID($lcu)) @@ -173,21 +173,21 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce wire = module->addWire(ID::P); wire->width = width; wire->port_input = true; - cell->setPort(ID::P, wire); + cell->setPort(TW::P, wire); wire = module->addWire(ID::G); wire->width = width; wire->port_input = true; - cell->setPort(ID::G, wire); + cell->setPort(TW::G, wire); wire = module->addWire(ID::CI); wire->port_input = true; - cell->setPort(ID::CI, wire); + cell->setPort(TW::CI, wire); wire = module->addWire(ID::CO); wire->width = width; wire->port_output = true; - cell->setPort(ID::CO, wire); + cell->setPort(TW::CO, wire); } if (cell_type == ID($macc_v2)) @@ -231,7 +231,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce wire = module->addWire(ID::Y); wire->width = width; wire->port_output = true; - cell->setPort(ID::Y, wire); + cell->setPort(TW::Y, wire); } if (cell_type == ID($lut)) @@ -241,11 +241,11 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce wire = module->addWire(ID::A); wire->width = width; wire->port_input = true; - cell->setPort(ID::A, wire); + cell->setPort(TW::A, wire); wire = module->addWire(ID::Y); wire->port_output = true; - cell->setPort(ID::Y, wire); + cell->setPort(TW::Y, wire); RTLIL::SigSpec config; for (int i = 0; i < (1 << width); i++) @@ -262,11 +262,11 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce wire = module->addWire(ID::A); wire->width = width; wire->port_input = true; - cell->setPort(ID::A, wire); + cell->setPort(TW::A, wire); wire = module->addWire(ID::Y); wire->port_output = true; - cell->setPort(ID::Y, wire); + cell->setPort(TW::Y, wire); RTLIL::SigSpec config; for (int i = 0; i < width*depth; i++) @@ -296,7 +296,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce else wire->width = 1 + xorshift32(8 * bloat_factor); wire->port_input = true; - cell->setPort(ID::A, wire); + cell->setPort(TW::A, wire); } if (cell_type_flags.find('B') != std::string::npos) { @@ -308,7 +308,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce else wire->width = 1 + xorshift32(8 * bloat_factor); wire->port_input = true; - cell->setPort(ID::B, wire); + cell->setPort(TW::B, wire); } if (cell_type_flags.find('C') != std::string::npos) { @@ -318,7 +318,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce else wire->width = 1 + xorshift32(8 * bloat_factor); wire->port_input = true; - cell->setPort(ID::C, wire); + cell->setPort(TW::C, wire); } if (cell_type_flags.find('D') != std::string::npos) { @@ -328,7 +328,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce else wire->width = 1 + xorshift32(8 * bloat_factor); wire->port_input = true; - cell->setPort(ID::D, wire); + cell->setPort(TW::D, wire); } if (cell_type_flags.find('S') != std::string::npos && xorshift32(2)) { @@ -352,7 +352,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce else wire->width = 1 + xorshift32(8 * bloat_factor); wire->port_output = true; - cell->setPort(ID::Y, wire); + cell->setPort(TW::Y, wire); } if (cell_type.in(ID($shiftx))) { @@ -364,43 +364,43 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce } if (muxdiv && cell_type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) { - auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort(ID::B)); - auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort(ID::Y))); - module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort(ID::Y)); - cell->setPort(ID::Y, div_out); + auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort(TW::B)); + auto div_out = module->addWire(NEW_TWINE, GetSize(cell->getPort(TW::Y))); + module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort(TW::Y)); + cell->setPort(TW::Y, div_out); } if (cell_type == ID($alu)) { wire = module->addWire(ID::CI); wire->port_input = true; - cell->setPort(ID::CI, wire); + cell->setPort(TW::CI, wire); wire = module->addWire(ID::BI); wire->port_input = true; - cell->setPort(ID::BI, wire); + cell->setPort(TW::BI, wire); wire = module->addWire(ID::X); - wire->width = GetSize(cell->getPort(ID::Y)); + wire->width = GetSize(cell->getPort(TW::Y)); wire->port_output = true; - cell->setPort(ID::X, wire); + cell->setPort(TW::X, wire); wire = module->addWire(ID::CO); - wire->width = GetSize(cell->getPort(ID::Y)); + wire->width = GetSize(cell->getPort(TW::Y)); wire->port_output = true; - cell->setPort(ID::CO, wire); + cell->setPort(TW::CO, wire); } if (cell_type == ID($slice)) { - int a_size = GetSize(cell->getPort(ID::A)); + int a_size = GetSize(cell->getPort(TW::A)); int y_size = 1; if (a_size > 1) y_size += (xorshift32(8 * bloat_factor) % (a_size - 1)); wire = module->addWire(ID::Y); wire->width = y_size; wire->port_output = true; - cell->setPort(ID::Y, wire); + cell->setPort(TW::Y, wire); if (a_size > y_size) cell->setParam(ID::OFFSET, (xorshift32(8 * bloat_factor) % (a_size - y_size))); else @@ -410,37 +410,37 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce if (cell_type == ID($concat)) { wire = module->addWire(ID::Y); - wire->width = GetSize(cell->getPort(ID::A)) + GetSize(cell->getPort(ID::B)); + wire->width = GetSize(cell->getPort(TW::A)) + GetSize(cell->getPort(TW::B)); wire->port_output = true; - cell->setPort(ID::Y, wire); + cell->setPort(TW::Y, wire); } if (cell_type == ID($buf)) { wire = module->addWire(ID::Y); - wire->width = GetSize(cell->getPort(ID::A)); + wire->width = GetSize(cell->getPort(TW::A)); wire->port_output = true; - cell->setPort(ID::Y, wire); + cell->setPort(TW::Y, wire); } if (cell_type.in(ID($bwmux), ID($bweqx))) { - int a_size = GetSize(cell->getPort(ID::A)); + int a_size = GetSize(cell->getPort(TW::A)); wire = module->addWire(ID::B); wire->width = a_size; wire->port_input = true; - cell->setPort(ID::B, wire); + cell->setPort(TW::B, wire); if (cell_type == ID($bwmux)) { wire = module->addWire(ID::S); wire->width = a_size; wire->port_input = true; - cell->setPort(ID::S, wire); + cell->setPort(TW::S, wire); } wire = module->addWire(ID::Y); wire->width = a_size; wire->port_output = true; - cell->setPort(ID::Y, wire); + cell->setPort(TW::Y, wire); } if (constmode) diff --git a/pyosys/wrappers_tpl.cc b/pyosys/wrappers_tpl.cc index 2e358029a..c1e65d402 100644 --- a/pyosys/wrappers_tpl.cc +++ b/pyosys/wrappers_tpl.cc @@ -112,7 +112,7 @@ namespace pyosys { void notify_connect( RTLIL::Cell *cell, - RTLIL::IdString port, + TwineRef port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig ) override { diff --git a/techlibs/anlogic/anlogic_fixcarry.cc b/techlibs/anlogic/anlogic_fixcarry.cc index 5d09498f2..1f38e0608 100644 --- a/techlibs/anlogic/anlogic_fixcarry.cc +++ b/techlibs/anlogic/anlogic_fixcarry.cc @@ -79,9 +79,9 @@ static void fix_carry_chain(Module *module) SigBit canonical_bit = sigmap(bit_ci); auto bit = mapping_bits.at(canonical_bit); log("Fixing %s cell named %s breaking carry chain.\n", cell->type.unescape(), cell); - Cell *c = module->addCell(NEW_ID, ID(AL_MAP_ADDER)); - SigBit new_bit = module->addWire(NEW_ID); - SigBit dummy_bit = module->addWire(NEW_ID); + Cell *c = module->addCell(NEW_TWINE, ID(AL_MAP_ADDER)); + SigBit new_bit = module->addWire(NEW_TWINE); + SigBit dummy_bit = module->addWire(NEW_TWINE); SigSpec bits; bits.append(dummy_bit); bits.append(new_bit); diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index b32470fd3..08f77a2c2 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1088,7 +1088,7 @@ parameter CONFIG = 4'b0000; parameter CONFIG_WIDTH = 4; // In the terms used for this cell, there's mixed meanings for the term "port". To disambiguate: -// A cell port is for example the A input (it is constructed in C++ as cell->setPort(ID::A, ...)) +// A cell port is for example the A input (it is constructed in C++ as cell->setPort(TW::A, ...)) // Multiplier ports are pairs of multiplier inputs ("factors"). // If the second signal in such a pair is zero length, no multiplication is necessary, and the first signal is just added to the sum. input [A_WIDTH-1:0] A; // Cell port A is the concatenation of all arithmetic ports diff --git a/techlibs/coolrunner2/coolrunner2_fixup.cc b/techlibs/coolrunner2/coolrunner2_fixup.cc index 2b2249596..3ba797a9d 100644 --- a/techlibs/coolrunner2/coolrunner2_fixup.cc +++ b/techlibs/coolrunner2/coolrunner2_fixup.cc @@ -136,7 +136,7 @@ struct Coolrunner2FixupPass : public Pass { if (cell->type.in(ID(FDCP), ID(FDCP_N), ID(FDDCP), ID(LDCP), ID(LDCP_N), ID(FTCP), ID(FTCP_N), ID(FTDCP), ID(FDCPE), ID(FDCPE_N), ID(FDDCPE))) { - auto output = sigmap(cell->getPort(ID::Q)[0]); + auto output = sigmap(cell->getPort(TW::Q)[0]); sig_fed_by_ff.insert(output); } } @@ -159,7 +159,7 @@ struct Coolrunner2FixupPass : public Pass { if (cell->type.in(ID(IBUF), ID(IOBUFE))) { if (cell->hasPort(ID::O)) { - auto output = sigmap(cell->getPort(ID::O)[0]); + auto output = sigmap(cell->getPort(TW::O)[0]); sig_fed_by_io.insert(output); } } @@ -182,7 +182,7 @@ struct Coolrunner2FixupPass : public Pass { { if (cell->type == ID(BUFG)) { - auto output = sigmap(cell->getPort(ID::O)[0]); + auto output = sigmap(cell->getPort(TW::O)[0]); sig_fed_by_bufg.insert(output); } } @@ -193,7 +193,7 @@ struct Coolrunner2FixupPass : public Pass { { if (cell->type == ID(BUFGSR)) { - auto output = sigmap(cell->getPort(ID::O)[0]); + auto output = sigmap(cell->getPort(TW::O)[0]); sig_fed_by_bufgsr.insert(output); } } @@ -204,7 +204,7 @@ struct Coolrunner2FixupPass : public Pass { { if (cell->type == ID(BUFGTS)) { - auto output = sigmap(cell->getPort(ID::O)[0]); + auto output = sigmap(cell->getPort(TW::O)[0]); sig_fed_by_bufgts.insert(output); } } @@ -215,7 +215,7 @@ struct Coolrunner2FixupPass : public Pass { { if (cell->type == ID(IBUF)) { - auto output = sigmap(cell->getPort(ID::O)[0]); + auto output = sigmap(cell->getPort(TW::O)[0]); sig_fed_by_ibuf.insert(output); } } @@ -259,10 +259,10 @@ struct Coolrunner2FixupPass : public Pass { { SigBit input; if (maybe_ff_cell->type.in(ID(FTCP), ID(FTCP_N), ID(FTDCP))) - input = sigmap(maybe_ff_cell->getPort(ID::T)[0]); + input = sigmap(maybe_ff_cell->getPort(TW::T)[0]); else - input = sigmap(maybe_ff_cell->getPort(ID::D)[0]); - SigBit output = sigmap(maybe_ff_cell->getPort(ID::Q)[0]); + input = sigmap(maybe_ff_cell->getPort(TW::D)[0]); + SigBit output = sigmap(maybe_ff_cell->getPort(TW::Q)[0]); if (input == ibuf_out_wire) { @@ -287,9 +287,9 @@ struct Coolrunner2FixupPass : public Pass { // to be inserted. SigBit input; if (cell->type.in(ID(FTCP), ID(FTCP_N), ID(FTDCP))) - input = sigmap(cell->getPort(ID::T)[0]); + input = sigmap(cell->getPort(TW::T)[0]); else - input = sigmap(cell->getPort(ID::D)[0]); + input = sigmap(cell->getPort(TW::D)[0]); // If the input wasn't an XOR nor an IO, then a buffer // definitely needs to be added. @@ -303,9 +303,9 @@ struct Coolrunner2FixupPass : public Pass { auto xor_to_ff_wire = makexorbuffer(module, input, cell->name.c_str()); if (cell->type.in(ID(FTCP), ID(FTCP_N), ID(FTDCP))) - cell->setPort(ID::T, xor_to_ff_wire); + cell->setPort(TW::T, xor_to_ff_wire); else - cell->setPort(ID::D, xor_to_ff_wire); + cell->setPort(TW::D, xor_to_ff_wire); } // Buffering FF clocks. FF clocks can only come from either @@ -314,9 +314,9 @@ struct Coolrunner2FixupPass : public Pass { // AND-ing two signals) but not in all cases. SigBit clock; if (cell->type.in(ID(LDCP), ID(LDCP_N))) - clock = sigmap(cell->getPort(ID::G)[0]); + clock = sigmap(cell->getPort(TW::G)[0]); else - clock = sigmap(cell->getPort(ID::C)[0]); + clock = sigmap(cell->getPort(TW::C)[0]); if (!sig_fed_by_pterm[clock] && !sig_fed_by_bufg[clock]) { @@ -325,9 +325,9 @@ struct Coolrunner2FixupPass : public Pass { auto pterm_to_ff_wire = makeptermbuffer(module, clock); if (cell->type.in(ID(LDCP), ID(LDCP_N))) - cell->setPort(ID::G, pterm_to_ff_wire); + cell->setPort(TW::G, pterm_to_ff_wire); else - cell->setPort(ID::C, pterm_to_ff_wire); + cell->setPort(TW::C, pterm_to_ff_wire); } // Buffering FF set/reset. This can only come from either @@ -347,7 +347,7 @@ struct Coolrunner2FixupPass : public Pass { } SigBit reset; - reset = sigmap(cell->getPort(ID::CLR)[0]); + reset = sigmap(cell->getPort(TW::CLR)[0]); if (reset != SigBit(false)) { if (!sig_fed_by_pterm[reset] && !sig_fed_by_bufgsr[reset]) @@ -356,7 +356,7 @@ struct Coolrunner2FixupPass : public Pass { auto pterm_to_ff_wire = makeptermbuffer(module, reset); - cell->setPort(ID::CLR, pterm_to_ff_wire); + cell->setPort(TW::CLR, pterm_to_ff_wire); } } @@ -384,7 +384,7 @@ struct Coolrunner2FixupPass : public Pass { if (cell->type == ID(IOBUFE)) { // Buffer IOBUFE inputs. This can only be fed from an XOR or FF. - SigBit input = sigmap(cell->getPort(ID::I)[0]); + SigBit input = sigmap(cell->getPort(TW::I)[0]); if ((!sig_fed_by_xor[input] && !sig_fed_by_ff[input]) || packed_reg_out[input]) @@ -393,7 +393,7 @@ struct Coolrunner2FixupPass : public Pass { auto xor_to_io_wire = makexorbuffer(module, input, cell->name.c_str()); - cell->setPort(ID::I, xor_to_io_wire); + cell->setPort(TW::I, xor_to_io_wire); } // Buffer IOBUFE enables. This can only be fed from a pterm @@ -401,14 +401,14 @@ struct Coolrunner2FixupPass : public Pass { if (cell->hasPort(ID::E)) { SigBit oe; - oe = sigmap(cell->getPort(ID::E)[0]); + oe = sigmap(cell->getPort(TW::E)[0]); if (!sig_fed_by_pterm[oe] && !sig_fed_by_bufgts[oe]) { log("Buffering output enable to \"%s\"\n", cell->name); auto pterm_to_oe_wire = makeptermbuffer(module, oe); - cell->setPort(ID::E, pterm_to_oe_wire); + cell->setPort(TW::E, pterm_to_oe_wire); } } } diff --git a/techlibs/coolrunner2/coolrunner2_sop.cc b/techlibs/coolrunner2/coolrunner2_sop.cc index 17e0d8432..3546d39ee 100644 --- a/techlibs/coolrunner2/coolrunner2_sop.cc +++ b/techlibs/coolrunner2/coolrunner2_sop.cc @@ -49,8 +49,8 @@ struct Coolrunner2SopPass : public Pass { { if (cell->type == ID($_NOT_)) { - auto not_input = sigmap(cell->getPort(ID::A)[0]); - auto not_output = sigmap(cell->getPort(ID::Y)[0]); + auto not_input = sigmap(cell->getPort(TW::A)[0]); + auto not_output = sigmap(cell->getPort(TW::Y)[0]); not_cells[not_input] = tuple(not_output, cell); } } @@ -67,17 +67,17 @@ struct Coolrunner2SopPass : public Pass { special_pterms_no_inv[sigmap(cell->getPort(ID(PRE))[0])].insert( make_tuple(cell, ID(PRE))); if (cell->hasPort(ID::CLR)) - special_pterms_no_inv[sigmap(cell->getPort(ID::CLR)[0])].insert( + special_pterms_no_inv[sigmap(cell->getPort(TW::CLR)[0])].insert( make_tuple(cell, ID::CLR)); if (cell->hasPort(ID(CE))) special_pterms_no_inv[sigmap(cell->getPort(ID(CE))[0])].insert( make_tuple(cell, ID(CE))); if (cell->hasPort(ID::C)) - special_pterms_inv[sigmap(cell->getPort(ID::C)[0])].insert( + special_pterms_inv[sigmap(cell->getPort(TW::C)[0])].insert( make_tuple(cell, ID::C)); if (cell->hasPort(ID::G)) - special_pterms_inv[sigmap(cell->getPort(ID::G)[0])].insert( + special_pterms_inv[sigmap(cell->getPort(TW::G)[0])].insert( make_tuple(cell, ID::G)); } } @@ -88,8 +88,8 @@ struct Coolrunner2SopPass : public Pass { if (cell->type == ID($sop)) { // Read the inputs/outputs/parameters of the $sop cell - auto sop_inputs = sigmap(cell->getPort(ID::A)); - auto sop_output = sigmap(cell->getPort(ID::Y))[0]; + auto sop_inputs = sigmap(cell->getPort(TW::A)); + auto sop_output = sigmap(cell->getPort(TW::Y))[0]; auto sop_depth = cell->getParam(ID::DEPTH).as_int(); auto sop_width = cell->getParam(ID::WIDTH).as_int(); auto sop_table = cell->getParam(ID::TABLE); diff --git a/techlibs/efinix/efinix_fixcarry.cc b/techlibs/efinix/efinix_fixcarry.cc index 5056dec1a..4b267954d 100644 --- a/techlibs/efinix/efinix_fixcarry.cc +++ b/techlibs/efinix/efinix_fixcarry.cc @@ -43,8 +43,8 @@ static void fix_carry_chain(Module *module) SigBit bit_i0 = get_bit_or_zero(cell->getPort(ID(I0))); SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(I1))); if (bit_i0 == State::S0 && bit_i1== State::S0) { - SigBit bit_ci = get_bit_or_zero(cell->getPort(ID::CI)); - SigBit bit_o = sigmap(cell->getPort(ID::O)); + SigBit bit_ci = get_bit_or_zero(cell->getPort(TW::CI)); + SigBit bit_o = sigmap(cell->getPort(TW::O)); ci_bits.insert(bit_ci); mapping_bits[bit_ci] = bit_o; } @@ -55,7 +55,7 @@ static void fix_carry_chain(Module *module) for (auto cell : module->cells()) { if (cell->type == ID(EFX_ADD)) { - SigBit bit_ci = get_bit_or_zero(cell->getPort(ID::CI)); + SigBit bit_ci = get_bit_or_zero(cell->getPort(TW::CI)); SigBit bit_i0 = get_bit_or_zero(cell->getPort(ID(I0))); SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(I1))); SigBit canonical_bit = sigmap(bit_ci); @@ -71,20 +71,20 @@ static void fix_carry_chain(Module *module) for (auto cell : adders_to_fix_cells) { - SigBit bit_ci = get_bit_or_zero(cell->getPort(ID::CI)); + SigBit bit_ci = get_bit_or_zero(cell->getPort(TW::CI)); SigBit canonical_bit = sigmap(bit_ci); auto bit = mapping_bits.at(canonical_bit); log("Fixing %s cell named %s breaking carry chain.\n", cell->type.unescape(), cell); - Cell *c = module->addCell(NEW_ID, ID(EFX_ADD)); - SigBit new_bit = module->addWire(NEW_ID); + Cell *c = module->addCell(NEW_TWINE, ID(EFX_ADD)); + SigBit new_bit = module->addWire(NEW_TWINE); c->setParam(ID(I0_POLARITY), State::S1); c->setParam(ID(I1_POLARITY), State::S1); c->setPort(ID(I0), bit); c->setPort(ID(I1), State::S1); - c->setPort(ID::CI, State::S0); - c->setPort(ID::CO, new_bit); + c->setPort(TW::CI, State::S0); + c->setPort(TW::CO, new_bit); - cell->setPort(ID::CI, new_bit); + cell->setPort(TW::CI, new_bit); } } diff --git a/techlibs/gatemate/gatemate_foldinv.cc b/techlibs/gatemate/gatemate_foldinv.cc index 1af6a8987..66d56188c 100644 --- a/techlibs/gatemate/gatemate_foldinv.cc +++ b/techlibs/gatemate/gatemate_foldinv.cc @@ -70,8 +70,8 @@ struct FoldInvWorker { for (auto cell : module->selected_cells()) { if (cell->type != ID($__CC_NOT)) continue; - SigBit a = sigmap(cell->getPort(ID::A)[0]); - SigBit y = sigmap(cell->getPort(ID::Y)[0]); + SigBit a = sigmap(cell->getPort(TW::A)[0]); + SigBit y = sigmap(cell->getPort(TW::Y)[0]); inverted_bits[y] = a; inverter_input[a] = cell; } @@ -143,7 +143,7 @@ struct FoldInvWorker { continue; if (!cell->hasPort(ID::O)) continue; - auto o_sig = cell->getPort(ID::O); + auto o_sig = cell->getPort(TW::O); if (GetSize(o_sig) == 0) continue; SigBit o = sigmap(o_sig[0]); @@ -156,15 +156,15 @@ struct FoldInvWorker { Cell *orig_lut = pair.first; Cell *inv = pair.second; // Find the inverter output - SigBit inv_y = sigmap(inv->getPort(ID::Y)[0]); + SigBit inv_y = sigmap(inv->getPort(TW::Y)[0]); // Inverter output might not actually be used; if all users were folded into inputs already if (!used_bits.count(inv_y)) continue; // Create a duplicate of the LUT with an inverted output // (if the uninverted version becomes unused it will be swept away) - Cell *dup_lut = module->addCell(NEW_ID, orig_lut->type); - inv->unsetPort(ID::Y); - dup_lut->setPort(ID::O, inv_y); + Cell *dup_lut = module->addCell(NEW_TWINE, orig_lut->type); + inv->unsetPort(TW::Y); + dup_lut->setPort(TW::O, inv_y); for (auto conn : orig_lut->connections()) { if (conn.first == ID::O) continue; diff --git a/techlibs/greenpak4/greenpak4_dffinv.cc b/techlibs/greenpak4/greenpak4_dffinv.cc index 691013c8e..b15874360 100644 --- a/techlibs/greenpak4/greenpak4_dffinv.cc +++ b/techlibs/greenpak4/greenpak4_dffinv.cc @@ -71,12 +71,12 @@ void invert_gp_dff(Cell *cell, bool invert_input) } if (cell_type_i) { - cell->setPort(ID::Q, cell->getPort(ID(nQ))); + cell->setPort(TW::Q, cell->getPort(ID(nQ))); cell->unsetPort(ID(nQ)); cell_type_i = false; } else { - cell->setPort(ID(nQ), cell->getPort(ID::Q)); - cell->unsetPort(ID::Q); + cell->setPort(ID(nQ), cell->getPort(TW::Q)); + cell->unsetPort(TW::Q); cell_type_i = true; } @@ -175,15 +175,15 @@ struct Greenpak4DffInvPass : public Pass { for (auto cell : dff_cells) { - SigBit d_bit = sigmap(cell->getPort(ID::D)); - SigBit q_bit = sigmap(cell->hasPort(ID::Q) ? cell->getPort(ID::Q) : cell->getPort(ID(nQ))); + SigBit d_bit = sigmap(cell->getPort(TW::D)); + SigBit q_bit = sigmap(cell->hasPort(ID::Q) ? cell->getPort(TW::Q) : cell->getPort(ID(nQ))); while (inv_out2in.count(d_bit)) { sig_use_cnt[d_bit]--; invert_gp_dff(cell, true); d_bit = inv_out2in.at(d_bit); - cell->setPort(ID::D, d_bit); + cell->setPort(TW::D, d_bit); sig_use_cnt[d_bit]++; } @@ -198,7 +198,7 @@ struct Greenpak4DffInvPass : public Pass { invert_gp_dff(cell, false); if (cell->hasPort(ID::Q)) - cell->setPort(ID::Q, new_q_bit); + cell->setPort(TW::Q, new_q_bit); else cell->setPort(ID(nQ), new_q_bit); } diff --git a/techlibs/ice40/ice40_dsp.cc b/techlibs/ice40/ice40_dsp.cc index 9e6e7cb4c..d6a080ac6 100644 --- a/techlibs/ice40/ice40_dsp.cc +++ b/techlibs/ice40/ice40_dsp.cc @@ -66,7 +66,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm) if (cell->type == ID($mul)) { log(" replacing %s with SB_MAC16 cell.\n", st.mul->type.unescape()); - cell = pm.module->addCell(NEW_ID, ID(SB_MAC16)); + cell = pm.module->addCell(NEW_TWINE, ID(SB_MAC16)); pm.module->swap_names(cell, st.mul); } else log_assert(cell->type == ID(SB_MAC16)); @@ -86,10 +86,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm) else log_assert(GetSize(CD) == 32); - cell->setPort(ID::A, A); - cell->setPort(ID::B, B); - cell->setPort(ID::C, CD.extract(16, 16)); - cell->setPort(ID::D, CD.extract(0, 16)); + cell->setPort(TW::A, A); + cell->setPort(TW::B, B); + cell->setPort(TW::C, CD.extract(16, 16)); + cell->setPort(TW::D, CD.extract(0, 16)); cell->setParam(ID(A_REG), st.ffA ? State::S1 : State::S0); cell->setParam(ID(B_REG), st.ffB ? State::S1 : State::S0); @@ -98,15 +98,15 @@ void create_ice40_dsp(ice40_dsp_pm &pm) SigSpec AHOLD, BHOLD, CDHOLD; if (st.ffA && st.ffA->hasPort(ID::EN)) - AHOLD = st.ffA->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_ID, st.ffA->getPort(ID::EN)) : st.ffA->getPort(ID::EN); + AHOLD = st.ffA->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_ID, st.ffA->getPort(TW::EN)) : st.ffA->getPort(TW::EN); else AHOLD = State::S0; if (st.ffB && st.ffB->hasPort(ID::EN)) - BHOLD = st.ffB->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_ID, st.ffB->getPort(ID::EN)) : st.ffB->getPort(ID::EN); + BHOLD = st.ffB->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_ID, st.ffB->getPort(TW::EN)) : st.ffB->getPort(TW::EN); else BHOLD = State::S0; if (st.ffCD && st.ffCD->hasPort(ID::EN)) - CDHOLD = st.ffCD->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_ID, st.ffCD->getPort(ID::EN)) : st.ffCD->getPort(ID::EN); + CDHOLD = st.ffCD->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_ID, st.ffCD->getPort(TW::EN)) : st.ffCD->getPort(TW::EN); else CDHOLD = State::S0; cell->setPort(ID(AHOLD), AHOLD); @@ -116,11 +116,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm) SigSpec IRSTTOP, IRSTBOT; if (st.ffA && st.ffA->hasPort(ID::ARST)) - IRSTTOP = st.ffA->getParam(ID::ARST_POLARITY).as_bool() ? st.ffA->getPort(ID::ARST) : pm.module->Not(NEW_ID, st.ffA->getPort(ID::ARST)); + IRSTTOP = st.ffA->getParam(ID::ARST_POLARITY).as_bool() ? st.ffA->getPort(TW::ARST) : pm.module->Not(NEW_ID, st.ffA->getPort(TW::ARST)); else IRSTTOP = State::S0; if (st.ffB && st.ffB->hasPort(ID::ARST)) - IRSTBOT = st.ffB->getParam(ID::ARST_POLARITY).as_bool() ? st.ffB->getPort(ID::ARST) : pm.module->Not(NEW_ID, st.ffB->getPort(ID::ARST)); + IRSTBOT = st.ffB->getParam(ID::ARST_POLARITY).as_bool() ? st.ffB->getPort(TW::ARST) : pm.module->Not(NEW_ID, st.ffB->getPort(TW::ARST)); else IRSTBOT = State::S0; cell->setPort(ID(IRSTTOP), IRSTTOP); @@ -128,7 +128,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm) if (st.clock != SigBit()) { - cell->setPort(ID::CLK, st.clock); + cell->setPort(TW::CLK, st.clock); cell->setPort(ID(CE), State::S1); cell->setParam(ID(NEG_TRIGGER), st.clock_pol ? State::S0 : State::S1); @@ -156,7 +156,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm) } else { - cell->setPort(ID::CLK, State::S0); + cell->setPort(TW::CLK, State::S0); cell->setPort(ID(CE), State::S0); cell->setParam(ID(NEG_TRIGGER), State::S0); } @@ -164,12 +164,12 @@ void create_ice40_dsp(ice40_dsp_pm &pm) // SB_MAC16 Cascade Interface cell->setPort(ID(SIGNEXTIN), State::Sx); - cell->setPort(ID(SIGNEXTOUT), pm.module->addWire(NEW_ID)); + cell->setPort(ID(SIGNEXTOUT), pm.module->addWire(NEW_TWINE)); - cell->setPort(ID::CI, State::Sx); + cell->setPort(TW::CI, State::Sx); cell->setPort(ID(ACCUMCI), State::Sx); - cell->setPort(ID(ACCUMCO), pm.module->addWire(NEW_ID)); + cell->setPort(ID(ACCUMCO), pm.module->addWire(NEW_TWINE)); // SB_MAC16 Output Interface @@ -181,16 +181,16 @@ void create_ice40_dsp(ice40_dsp_pm &pm) if (st.add->getParam(ID::A_SIGNED).as_bool() && st.add->getParam(ID::B_SIGNED).as_bool()) pm.module->connect(O[32], O[31]); else - cell->setPort(ID::CO, O[32]); + cell->setPort(TW::CO, O[32]); O.remove(O_width-1); } else - cell->setPort(ID::CO, pm.module->addWire(NEW_ID)); + cell->setPort(TW::CO, pm.module->addWire(NEW_TWINE)); log_assert(GetSize(O) <= 32); if (GetSize(O) < 32) - O.append(pm.module->addWire(NEW_ID, 32-GetSize(O))); + O.append(pm.module->addWire(NEW_TWINE, 32-GetSize(O))); - cell->setPort(ID::O, O); + cell->setPort(TW::O, O); bool accum = false; if (st.add) { @@ -208,7 +208,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm) SigSpec OHOLD; if (st.ffO && st.ffO->hasPort(ID::EN)) - OHOLD = st.ffO->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_ID, st.ffO->getPort(ID::EN)) : st.ffO->getPort(ID::EN); + OHOLD = st.ffO->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_ID, st.ffO->getPort(TW::EN)) : st.ffO->getPort(TW::EN); else OHOLD = State::S0; cell->setPort(ID(OHOLDTOP), OHOLD); @@ -216,7 +216,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm) SigSpec ORST; if (st.ffO && st.ffO->hasPort(ID::ARST)) - ORST = st.ffO->getParam(ID::ARST_POLARITY).as_bool() ? st.ffO->getPort(ID::ARST) : pm.module->Not(NEW_ID, st.ffO->getPort(ID::ARST)); + ORST = st.ffO->getParam(ID::ARST_POLARITY).as_bool() ? st.ffO->getPort(TW::ARST) : pm.module->Not(NEW_ID, st.ffO->getPort(TW::ARST)); else ORST = State::S0; cell->setPort(ID(ORSTTOP), ORST); @@ -225,11 +225,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm) SigSpec acc_reset = State::S0; if (st.mux) { if (st.muxAB == ID::A) - acc_reset = st.mux->getPort(ID::S); + acc_reset = st.mux->getPort(TW::S); else - acc_reset = pm.module->Not(NEW_ID, st.mux->getPort(ID::S)); + acc_reset = pm.module->Not(NEW_ID, st.mux->getPort(TW::S)); } else if (st.ffO && st.ffO->hasPort(ID::SRST)) { - acc_reset = st.ffO->getParam(ID::SRST_POLARITY).as_bool() ? st.ffO->getPort(ID::SRST) : pm.module->Not(NEW_ID, st.ffO->getPort(ID::SRST)); + acc_reset = st.ffO->getParam(ID::SRST_POLARITY).as_bool() ? st.ffO->getPort(TW::SRST) : pm.module->Not(NEW_ID, st.ffO->getPort(TW::SRST)); } cell->setPort(ID(OLOADTOP), acc_reset); cell->setPort(ID(OLOADBOT), acc_reset); @@ -259,7 +259,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm) else cell->setParam(ID(TOPOUTPUT_SELECT), Const(1, 2)); - st.ffO->connections_.at(ID::Q).replace(O, pm.module->addWire(NEW_ID, GetSize(O))); + st.ffO->connections_.at(ID::Q).replace(O, pm.module->addWire(NEW_TWINE, GetSize(O))); cell->setParam(ID(BOTOUTPUT_SELECT), Const(1, 2)); } else { diff --git a/techlibs/ice40/ice40_dsp.pmg b/techlibs/ice40/ice40_dsp.pmg index 7e4c3ace2..05d19a896 100644 --- a/techlibs/ice40/ice40_dsp.pmg +++ b/techlibs/ice40/ice40_dsp.pmg @@ -66,7 +66,7 @@ code sigA sigB sigH wire_width++; else { if (wire_width) { // add empty wires for bit offset if needed - sigH.append(module->addWire(NEW_ID, wire_width)); + sigH.append(module->addWire(NEW_TWINE, wire_width)); wire_width = 0; } sigH.append(O[j]); diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 67d3813a7..0221cc7b2 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -60,7 +60,7 @@ static void run_ice40_opts(Module *module) SigBit inbit[3] = { get_bit_or_zero(cell->getPort(ID(I0))), get_bit_or_zero(cell->getPort(ID(I1))), - get_bit_or_zero(cell->getPort(ID::CI)) + get_bit_or_zero(cell->getPort(TW::CI)) }; for (int i = 0; i < 3; i++) if (inbit[i].wire == nullptr) { @@ -79,8 +79,8 @@ static void run_ice40_opts(Module *module) replacement_output = non_const_inputs; if (GetSize(replacement_output)) { - optimized_co.insert(sigmap(cell->getPort(ID::CO)[0])); - module->connect(cell->getPort(ID::CO)[0], replacement_output); + optimized_co.insert(sigmap(cell->getPort(TW::CO)[0])); + module->connect(cell->getPort(TW::CO)[0], replacement_output); module->design->scratchpad_set_bool("opt.did_something", true); log("Optimized away SB_CARRY cell %s.%s: CO=%s\n", module, cell, log_signal(replacement_output)); @@ -95,9 +95,9 @@ static void run_ice40_opts(Module *module) int count_zeros = 0, count_ones = 0; SigBit inbit[3] = { - cell->getPort(ID::A), - cell->getPort(ID::B), - cell->getPort(ID::CI) + cell->getPort(TW::A), + cell->getPort(TW::B), + cell->getPort(TW::CI) }; for (int i = 0; i < 3; i++) if (inbit[i].wire == nullptr) { @@ -116,7 +116,7 @@ static void run_ice40_opts(Module *module) replacement_output = non_const_inputs; if (GetSize(replacement_output)) { - optimized_co.insert(sigmap(cell->getPort(ID::CO)[0])); + optimized_co.insert(sigmap(cell->getPort(TW::CO)[0])); auto it = cell->attributes.find(IdString{"\\SB_LUT4.name"}); if (it != cell->attributes.end()) { module->rename(cell, it->second.decode_string()); @@ -134,20 +134,20 @@ static void run_ice40_opts(Module *module) log_abort(); cell->attributes = std::move(new_attr); } - module->connect(cell->getPort(ID::CO)[0], replacement_output); + module->connect(cell->getPort(TW::CO)[0], replacement_output); module->design->scratchpad_set_bool("opt.did_something", true); log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", module, cell, log_signal(replacement_output)); cell->type = ID($lut); auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3))); - cell->setPort(ID::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(ID(I0))) }); - cell->setPort(ID::Y, cell->getPort(ID::O)); - cell->unsetPort(ID::B); - cell->unsetPort(ID::CI); + cell->setPort(TW::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(ID(I0))) }); + cell->setPort(TW::Y, cell->getPort(TW::O)); + cell->unsetPort(TW::B); + cell->unsetPort(TW::CI); cell->unsetPort(ID(I0)); cell->unsetPort(ID(I3)); - cell->unsetPort(ID::CO); - cell->unsetPort(ID::O); + cell->unsetPort(TW::CO); + cell->unsetPort(TW::O); cell->setParam(ID::WIDTH, 4); cell->unsetParam(ID(I3_IS_CI)); } @@ -182,18 +182,18 @@ static void run_ice40_opts(Module *module) cell->setParam(ID::LUT, cell->getParam(ID(LUT_INIT))); cell->unsetParam(ID(LUT_INIT)); - cell->setPort(ID::A, SigSpec({ + cell->setPort(TW::A, SigSpec({ get_bit_or_zero(cell->getPort(ID(I3))), get_bit_or_zero(cell->getPort(ID(I2))), get_bit_or_zero(cell->getPort(ID(I1))), get_bit_or_zero(cell->getPort(ID(I0))) })); - cell->setPort(ID::Y, cell->getPort(ID::O)[0]); + cell->setPort(TW::Y, cell->getPort(TW::O)[0]); cell->unsetPort(ID(I0)); cell->unsetPort(ID(I1)); cell->unsetPort(ID(I2)); cell->unsetPort(ID(I3)); - cell->unsetPort(ID::O); + cell->unsetPort(TW::O); cell->check(); simplemap_lut(module, cell); diff --git a/techlibs/ice40/ice40_wrapcarry.cc b/techlibs/ice40/ice40_wrapcarry.cc index 084d7f0c4..f680207a5 100644 --- a/techlibs/ice40/ice40_wrapcarry.cc +++ b/techlibs/ice40/ice40_wrapcarry.cc @@ -37,14 +37,14 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm) log(" replacing SB_LUT + SB_CARRY with $__ICE40_CARRY_WRAPPER cell.\n"); - Cell *cell = pm.module->addCell(NEW_ID, ID($__ICE40_CARRY_WRAPPER)); + Cell *cell = pm.module->addCell(NEW_TWINE, ID($__ICE40_CARRY_WRAPPER)); pm.module->swap_names(cell, st.carry); - cell->setPort(ID::A, st.carry->getPort(ID(I0))); - cell->setPort(ID::B, st.carry->getPort(ID(I1))); - auto CI = st.carry->getPort(ID::CI); - cell->setPort(ID::CI, CI); - cell->setPort(ID::CO, st.carry->getPort(ID::CO)); + cell->setPort(TW::A, st.carry->getPort(ID(I0))); + cell->setPort(TW::B, st.carry->getPort(ID(I1))); + auto CI = st.carry->getPort(TW::CI); + cell->setPort(TW::CI, CI); + cell->setPort(TW::CO, st.carry->getPort(TW::CO)); cell->setPort(ID(I0), st.lut->getPort(ID(I0))); auto I3 = st.lut->getPort(ID(I3)); @@ -55,7 +55,7 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm) else cell->setParam(ID(I3_IS_CI), State::S0); cell->setPort(ID(I3), I3); - cell->setPort(ID::O, st.lut->getPort(ID::O)); + cell->setPort(TW::O, st.lut->getPort(TW::O)); cell->setParam(ID::LUT, st.lut->getParam(ID(LUT_INIT))); for (const auto &a : st.carry->attributes) @@ -134,19 +134,19 @@ struct Ice40WrapCarryPass : public Pass { if (cell->type != ID($__ICE40_CARRY_WRAPPER)) continue; - auto carry = module->addCell(NEW_ID, ID(SB_CARRY)); - carry->setPort(ID(I0), cell->getPort(ID::A)); - carry->setPort(ID(I1), cell->getPort(ID::B)); - carry->setPort(ID::CI, cell->getPort(ID::CI)); - carry->setPort(ID::CO, cell->getPort(ID::CO)); + auto carry = module->addCell(NEW_TWINE, ID(SB_CARRY)); + carry->setPort(ID(I0), cell->getPort(TW::A)); + carry->setPort(ID(I1), cell->getPort(TW::B)); + carry->setPort(TW::CI, cell->getPort(TW::CI)); + carry->setPort(TW::CO, cell->getPort(TW::CO)); module->swap_names(carry, cell); auto lut_name = cell->attributes.at(IdString{"\\SB_LUT4.name"}, Const(NEW_ID.str())).decode_string(); auto lut = module->addCell(lut_name, ID($lut)); lut->setParam(ID::WIDTH, 4); lut->setParam(ID::LUT, cell->getParam(ID::LUT)); auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3)); - lut->setPort(ID::A, { I3, cell->getPort(ID::B), cell->getPort(ID::A), cell->getPort(ID(I0)) }); - lut->setPort(ID::Y, cell->getPort(ID::O)); + lut->setPort(TW::A, { I3, cell->getPort(TW::B), cell->getPort(TW::A), cell->getPort(ID(I0)) }); + lut->setPort(TW::Y, cell->getPort(TW::O)); std::string carry_src, lut_src, fallback_src; if (cell->src_id() != Twine::Null) diff --git a/techlibs/lattice/lattice_gsr.cc b/techlibs/lattice/lattice_gsr.cc index a60b54b16..3840bc3eb 100644 --- a/techlibs/lattice/lattice_gsr.cc +++ b/techlibs/lattice/lattice_gsr.cc @@ -102,7 +102,7 @@ struct LatticeGsrPass : public Pass { { if (cell->type != ID($_NOT_)) continue; - SigSpec sig_a = cell->getPort(ID::A), sig_y = cell->getPort(ID::Y); + SigSpec sig_a = cell->getPort(TW::A), sig_y = cell->getPort(TW::Y); if (GetSize(sig_a) < 1 || GetSize(sig_y) < 1) continue; SigBit a = sigmap(sig_a[0]); diff --git a/techlibs/microchip/microchip_dffopt.cc b/techlibs/microchip/microchip_dffopt.cc index 140ef2c9f..4a5e3264e 100644 --- a/techlibs/microchip/microchip_dffopt.cc +++ b/techlibs/microchip/microchip_dffopt.cc @@ -135,11 +135,11 @@ struct MicrochipDffOptPass : public Pass { if (cell->get_bool_attribute(ID::keep)) continue; if (cell->type == ID(INV)) { - SigBit sigout = sigmap(cell->getPort(ID::Y)); - SigBit sigin = sigmap(cell->getPort(ID::A)); + SigBit sigout = sigmap(cell->getPort(TW::Y)); + SigBit sigin = sigmap(cell->getPort(TW::A)); bit_to_lut[sigout] = make_pair(LutData(Const(1, 2), {sigin}), cell); // INIT = 01 } else if (cell->type.in(ID(CFG1), ID(CFG2), ID(CFG3), ID(CFG4))) { - SigBit sigout = sigmap(cell->getPort(ID::Y)); + SigBit sigout = sigmap(cell->getPort(TW::Y)); const Const &init = cell->getParam(ID::INIT); std::vector sigin; sigin.push_back(sigmap(cell->getPort(ID(A)))); @@ -182,7 +182,7 @@ struct MicrochipDffOptPass : public Pass { log_assert(!(has_s && has_r)); // Don't bother if D has more than one use. - SigBit sig_D = sigmap(cell->getPort(ID::D)); + SigBit sig_D = sigmap(cell->getPort(TW::D)); if (bit_uses[sig_D] > 2) continue; @@ -201,7 +201,7 @@ struct MicrochipDffOptPass : public Pass { bool worthy_post_r = false; // First, unmap CE. - SigBit sig_Q = sigmap(cell->getPort(ID::Q)); + SigBit sig_Q = sigmap(cell->getPort(TW::Q)); SigBit sig_CE = sigmap(cell->getPort(ID(EN))); LutData lut_ce = LutData(Const(2, 2), {sig_CE}); // INIT = 10 auto it_CE = bit_to_lut.find(sig_CE); @@ -309,25 +309,25 @@ struct MicrochipDffOptPass : public Pass { Cell *lut_cell = nullptr; switch (GetSize(final_lut.second)) { case 1: - lut_cell = module->addCell(NEW_ID, ID(CFG1)); + lut_cell = module->addCell(NEW_TWINE, ID(CFG1)); break; case 2: - lut_cell = module->addCell(NEW_ID, ID(CFG2)); + lut_cell = module->addCell(NEW_TWINE, ID(CFG2)); break; case 3: - lut_cell = module->addCell(NEW_ID, ID(CFG3)); + lut_cell = module->addCell(NEW_TWINE, ID(CFG3)); break; case 4: - lut_cell = module->addCell(NEW_ID, ID(CFG4)); + lut_cell = module->addCell(NEW_TWINE, ID(CFG4)); break; default: log_assert(!"unknown lut size"); } lut_cell->attributes = cell_d->attributes; - Wire *lut_out = module->addWire(NEW_ID); + Wire *lut_out = module->addWire(NEW_TWINE); lut_cell->setParam(ID::INIT, final_lut.first); - cell->setPort(ID::D, lut_out); - lut_cell->setPort(ID::Y, lut_out); + cell->setPort(TW::D, lut_out); + lut_cell->setPort(TW::Y, lut_out); lut_cell->setPort(ID(A), final_lut.second[0]); if (GetSize(final_lut.second) >= 2) lut_cell->setPort(ID(B), final_lut.second[1]); diff --git a/techlibs/microchip/microchip_dsp.cc b/techlibs/microchip/microchip_dsp.cc index df12d43b6..a1669036e 100644 --- a/techlibs/microchip/microchip_dsp.cc +++ b/techlibs/microchip/microchip_dsp.cc @@ -43,10 +43,10 @@ void microchip_dsp_pack(microchip_dsp_pm &pm) st.sigB.extend_u0(18, B_SIGNED); st.sigD.extend_u0(18, D_SIGNED); if (st.moveBtoA) { - cell->setPort(ID::A, st.sigA); // if pre-adder feeds into A, original sigB will be moved to port A + cell->setPort(TW::A, st.sigA); // if pre-adder feeds into A, original sigB will be moved to port A } - cell->setPort(ID::B, st.sigB); - cell->setPort(ID::D, st.sigD); + cell->setPort(TW::B, st.sigB); + cell->setPort(TW::D, st.sigD); // MACC_PA supports both addition and subtraction with the pre-adder. // Affects the sign of the 'D' port. if (st.preAdderStatic->type == ID($add)) @@ -75,7 +75,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm) cell->setPort(ID(CDIN_FDBK_SEL), {State::S0, State::S1}); } else { st.sigC.extend_u0(48, st.postAdderStatic->getParam(ID::A_SIGNED).as_bool()); - cell->setPort(ID::C, st.sigC); + cell->setPort(TW::C, st.sigC); } pm.autoremove(st.postAdderStatic); @@ -83,24 +83,24 @@ void microchip_dsp_pack(microchip_dsp_pm &pm) // pack registers if (st.clock != SigBit()) { - cell->setPort(ID::CLK, st.clock); + cell->setPort(TW::CLK, st.clock); // function to absorb a register auto f = [&pm, cell](SigSpec &A, Cell *ff, IdString ceport, IdString rstport, IdString bypass) { // input/output ports - SigSpec D = ff->getPort(ID::D); - SigSpec Q = (*pm.sigmap)(ff->getPort(ID::Q)); + SigSpec D = ff->getPort(TW::D); + SigSpec Q = (*pm.sigmap)(ff->getPort(TW::Q)); if (!A.empty()) A.replace(Q, D); if (rstport != IdString()) { if (ff->type.in(ID($sdff), ID($sdffe))) { - SigSpec srst = ff->getPort(ID::SRST); + SigSpec srst = ff->getPort(TW::SRST); bool rstpol_n = !ff->getParam(ID::SRST_POLARITY).as_bool(); // active low sync rst cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_ID, srst)); } else if (ff->type.in(ID($adff), ID($adffe))) { - SigSpec arst = ff->getPort(ID::ARST); + SigSpec arst = ff->getPort(TW::ARST); bool rstpol_n = !ff->getParam(ID::ARST_POLARITY).as_bool(); // active low async rst cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEW_ID, arst)); @@ -110,7 +110,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm) } } if (ff->type.in(ID($dffe), ID($sdffe), ID($adffe))) { - SigSpec ce = ff->getPort(ID::EN); + SigSpec ce = ff->getPort(TW::EN); bool cepol = ff->getParam(ID::EN_POLARITY).as_bool(); // enables are all active high cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce)); @@ -136,23 +136,23 @@ void microchip_dsp_pack(microchip_dsp_pm &pm) // NOTE: flops are not autoremoved because it is possible that they // are only partially absorbed into DSP, or have fanouts. if (st.ffA) { - SigSpec A = cell->getPort(ID::A); + SigSpec A = cell->getPort(TW::A); if (st.ffA) { f(A, st.ffA, ID(A_EN), ID(A_SRST_N), ID(A_BYPASS)); } pm.add_siguser(A, cell); - cell->setPort(ID::A, A); + cell->setPort(TW::A, A); } if (st.ffB) { - SigSpec B = cell->getPort(ID::B); + SigSpec B = cell->getPort(TW::B); if (st.ffB) { f(B, st.ffB, ID(B_EN), ID(B_SRST_N), ID(B_BYPASS)); } pm.add_siguser(B, cell); - cell->setPort(ID::B, B); + cell->setPort(TW::B, B); } if (st.ffD) { - SigSpec D = cell->getPort(ID::D); + SigSpec D = cell->getPort(TW::D); if (st.ffD->type.in(ID($adff), ID($adffe))) { f(D, st.ffD, ID(D_EN), ID(D_ARST_N), ID(D_BYPASS)); } else { @@ -160,12 +160,12 @@ void microchip_dsp_pack(microchip_dsp_pm &pm) } pm.add_siguser(D, cell); - cell->setPort(ID::D, D); + cell->setPort(TW::D, D); } if (st.ffP) { SigSpec P; // unused f(P, st.ffP, ID(P_EN), ID(P_SRST_N), ID(P_BYPASS)); - st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP))); + st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_TWINE, GetSize(st.sigP))); } log(" clock: %s (%s)\n", log_signal(st.clock), "posedge"); @@ -183,8 +183,8 @@ void microchip_dsp_pack(microchip_dsp_pm &pm) SigSpec P = st.sigP; if (GetSize(P) < 48) - P.append(pm.module->addWire(NEW_ID, 48 - GetSize(P))); - cell->setPort(ID::P, P); + P.append(pm.module->addWire(NEW_TWINE, 48 - GetSize(P))); + cell->setPort(TW::P, P); pm.blacklist(cell); } @@ -200,23 +200,23 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm) Cell *cell = st.dsp; if (st.clock != SigBit()) { - cell->setPort(ID::CLK, st.clock); + cell->setPort(TW::CLK, st.clock); // same function as above, used for the last CREG we need to absorb auto f = [&pm, cell](SigSpec &A, Cell *ff, IdString ceport, IdString rstport, IdString bypass) { // input/output ports - SigSpec D = ff->getPort(ID::D); - SigSpec Q = (*pm.sigmap)(ff->getPort(ID::Q)); + SigSpec D = ff->getPort(TW::D); + SigSpec Q = (*pm.sigmap)(ff->getPort(TW::Q)); if (!A.empty()) A.replace(Q, D); if (rstport != IdString()) { if (ff->type.in(ID($sdff), ID($sdffe))) { - SigSpec srst = ff->getPort(ID::SRST); + SigSpec srst = ff->getPort(TW::SRST); bool rstpol_n = !ff->getParam(ID::SRST_POLARITY).as_bool(); // active low sync rst cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_ID, srst)); } else if (ff->type.in(ID($adff), ID($adffe))) { - SigSpec arst = ff->getPort(ID::ARST); + SigSpec arst = ff->getPort(TW::ARST); bool rstpol_n = !ff->getParam(ID::ARST_POLARITY).as_bool(); // active low async rst cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEW_ID, arst)); @@ -226,7 +226,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm) } } if (ff->type.in(ID($dffe), ID($sdffe), ID($adffe))) { - SigSpec ce = ff->getPort(ID::EN); + SigSpec ce = ff->getPort(TW::EN); bool cepol = ff->getParam(ID::EN_POLARITY).as_bool(); // enables are all active high cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce)); @@ -250,7 +250,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm) }; if (st.ffC) { - SigSpec C = cell->getPort(ID::C); + SigSpec C = cell->getPort(TW::C); if (st.ffC->type.in(ID($adff), ID($adffe))) { f(C, st.ffC, ID(C_EN), ID(C_ARST_N), ID(C_BYPASS)); @@ -258,7 +258,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm) f(C, st.ffC, ID(C_EN), ID(C_SRST_N), ID(C_BYPASS)); } pm.add_siguser(C, cell); - cell->setPort(ID::C, C); + cell->setPort(TW::C, C); } log(" clock: %s (%s)", log_signal(st.clock), "posedge"); diff --git a/techlibs/microchip/microchip_dsp_cascade.pmg b/techlibs/microchip/microchip_dsp_cascade.pmg index ad359138d..7a8fd6c05 100644 --- a/techlibs/microchip/microchip_dsp_cascade.pmg +++ b/techlibs/microchip/microchip_dsp_cascade.pmg @@ -112,7 +112,7 @@ finally // Chain length exceeds the maximum cascade length, must split it up if (i % MAX_DSP_CASCADE > 0) { - Wire *cascade = module->addWire(NEW_ID, 48); + Wire *cascade = module->addWire(NEW_TWINE, 48); // zero port C and move wire to cascade dsp_pcin->setPort(\C, Const(0, 48)); diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc index 6e6a96035..d5ad26bbe 100644 --- a/techlibs/nanoxplore/nx_carry.cc +++ b/techlibs/nanoxplore/nx_carry.cc @@ -81,7 +81,7 @@ static void nx_carry_chain(Module *module) IdString names_B[] = { ID(B1), ID(B2), ID(B3), ID(B4) }; IdString names_S[] = { ID(S1), ID(S2), ID(S3), ID(S4) }; if (!c.second.at(0)->getPort(ID(CI)).is_fully_const()) { - cell = module->addCell(NEW_ID, ID(NX_CY)); + cell = module->addCell(NEW_TWINE, ID(NX_CY)); cell->setParam(ID(add_carry), Const(1,2)); cell->setPort(ID(CI), State::S1); @@ -92,7 +92,7 @@ static void nx_carry_chain(Module *module) for (size_t i=0 ; iaddCell(NEW_ID, ID(NX_CY)); + cell = module->addCell(NEW_TWINE, ID(NX_CY)); SigBit ci = c.second.at(i)->getPort(ID(CI)).as_bit(); cell->setPort(ID(CI), ci); if (ci.is_wire()) { @@ -106,11 +106,11 @@ static void nx_carry_chain(Module *module) } if (j==3) { if (cnt !=0 && (cnt % 24 == 0)) { - SigBit new_co = module->addWire(NEW_ID); + SigBit new_co = module->addWire(NEW_TWINE); cell->setPort(ID(A4), State::S0); cell->setPort(ID(B4), State::S0); cell->setPort(ID(S4), new_co); - cell = module->addCell(NEW_ID, ID(NX_CY)); + cell = module->addCell(NEW_TWINE, ID(NX_CY)); cell->setParam(ID(add_carry), Const(1,2)); cell->setPort(ID(CI), State::S1); cell->setPort(ID(A1), new_co); diff --git a/techlibs/quicklogic/ql_bram_merge.cc b/techlibs/quicklogic/ql_bram_merge.cc index eeb06060e..80d3b4111 100644 --- a/techlibs/quicklogic/ql_bram_merge.cc +++ b/techlibs/quicklogic/ql_bram_merge.cc @@ -127,7 +127,7 @@ struct QlBramMergeWorker { const RTLIL::IdString merged_cell_type = ID($__QLF_TDP36K_MERGED); // Create the new cell - RTLIL::Cell* merged = module->addCell(NEW_ID, merged_cell_type); + RTLIL::Cell* merged = module->addCell(NEW_TWINE, merged_cell_type); log_debug("Merging split BRAM cells %s and %s -> %s\n", bram1->name.unescape(), bram2->name.unescape(), merged->name.unescape()); for (auto &it : param_map(false)) diff --git a/techlibs/quicklogic/ql_dsp_macc.cc b/techlibs/quicklogic/ql_dsp_macc.cc index 368fb7ddd..ca6daa94d 100644 --- a/techlibs/quicklogic/ql_dsp_macc.cc +++ b/techlibs/quicklogic/ql_dsp_macc.cc @@ -80,7 +80,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm) log(" %s (%s)\n", cell, cell->type.unescape()); // Add the DSP cell - RTLIL::Cell *cell = pm.module->addCell(NEW_ID, type); + RTLIL::Cell *cell = pm.module->addCell(NEW_TWINE, type); // Set attributes cell->set_bool_attribute(ID(is_inferred), true); @@ -102,7 +102,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm) // Connect output data port, pad if needed if ((size_t) GetSize(sig_z) < tgt_z_width) { - auto *wire = pm.module->addWire(NEW_ID, tgt_z_width - GetSize(sig_z)); + auto *wire = pm.module->addWire(NEW_TWINE, tgt_z_width - GetSize(sig_z)); sig_z.append(wire); } cell->setPort(ID(z_o), sig_z); diff --git a/techlibs/quicklogic/ql_dsp_simd.cc b/techlibs/quicklogic/ql_dsp_simd.cc index da252673f..21420002e 100644 --- a/techlibs/quicklogic/ql_dsp_simd.cc +++ b/techlibs/quicklogic/ql_dsp_simd.cc @@ -148,7 +148,7 @@ struct QlDspSimdPass : public Pass { Cell *dsp_b = group[i + 1]; // Create the new cell - Cell *simd = module->addCell(NEW_ID, m_SimdDspType); + Cell *simd = module->addCell(NEW_TWINE, m_SimdDspType); log(" SIMD: %s (%s) + %s (%s) => %s (%s)\n", dsp_a, dsp_a->type.unescape(), dsp_b, dsp_b->type.unescape(), simd, simd->type.unescape()); @@ -182,7 +182,7 @@ struct QlDspSimdPass : public Pass { if (!isOutput) sigspec.append(RTLIL::SigSpec(RTLIL::Sx, padding)); else - sigspec.append(module->addWire(NEW_ID, padding)); + sigspec.append(module->addWire(NEW_TWINE, padding)); } return sigspec; }; diff --git a/techlibs/quicklogic/ql_ioff.cc b/techlibs/quicklogic/ql_ioff.cc index de7f5dbd4..2e98c0e7d 100644 --- a/techlibs/quicklogic/ql_ioff.cc +++ b/techlibs/quicklogic/ql_ioff.cc @@ -46,16 +46,16 @@ struct QlIoffPass : public Pass { for (auto cell : module->selected_cells()) { if (cell->type.in(ID(dffsre), ID(sdffsre))) { log_debug("Checking cell %s.\n", cell->name); - bool e_const = cell->getPort(ID::E).is_fully_ones(); - bool r_const = cell->getPort(ID::R).is_fully_ones(); - bool s_const = cell->getPort(ID::S).is_fully_ones(); + bool e_const = cell->getPort(TW::E).is_fully_ones(); + bool r_const = cell->getPort(TW::R).is_fully_ones(); + bool s_const = cell->getPort(TW::S).is_fully_ones(); if (!(e_const && r_const && s_const)) { log_debug("not promoting: E, R, or S is used\n"); continue; } - SigSpec d = cell->getPort(ID::D); + SigSpec d = cell->getPort(TW::D); log_assert(GetSize(d) == 1); if (modwalker.has_inputs(d)) { log_debug("Cell %s is potentially eligible for promotion to input IOFF.\n", cell->name); @@ -70,7 +70,7 @@ struct QlIoffPass : public Pass { continue; // prefer input FFs over output FFs } - SigSpec q = cell->getPort(ID::Q); + SigSpec q = cell->getPort(TW::Q); log_assert(GetSize(q) == 1); if (modwalker.has_outputs(q) && !modwalker.has_consumers(q)) { log_debug("Cell %s is potentially eligible for promotion to output IOFF.\n", cell->name); @@ -84,17 +84,17 @@ struct QlIoffPass : public Pass { } for (auto cell : input_ffs) { - log("Promoting register %s to input IOFF.\n", log_signal(cell->getPort(ID::Q))); + log("Promoting register %s to input IOFF.\n", log_signal(cell->getPort(TW::Q))); cell->type = ID(dff); - cell->unsetPort(ID::E); - cell->unsetPort(ID::R); - cell->unsetPort(ID::S); + cell->unsetPort(TW::E); + cell->unsetPort(TW::R); + cell->unsetPort(TW::S); } for (auto & [old_port_output, ioff_cells] : output_ffs) { if (std::any_of(ioff_cells.begin(), ioff_cells.end(), [](Cell * c) { return c != nullptr; })) { // create replacement output wire - RTLIL::Wire* new_port_output = module->addWire(NEW_ID, old_port_output->width); + RTLIL::Wire* new_port_output = module->addWire(NEW_TWINE, old_port_output->width); new_port_output->start_offset = old_port_output->start_offset; module->swap_names(old_port_output, new_port_output); std::swap(old_port_output->port_id, new_port_output->port_id); @@ -111,10 +111,10 @@ struct QlIoffPass : public Pass { if (ioff_cells[i]) { log("Promoting %s to output IOFF.\n", log_signal(sig_n[i])); - RTLIL::Cell *new_cell = module->addCell(NEW_ID, ID(dff)); - new_cell->setPort(ID::C, ioff_cells[i]->getPort(ID::C)); - new_cell->setPort(ID::D, ioff_cells[i]->getPort(ID::D)); - new_cell->setPort(ID::Q, sig_n[i]); + RTLIL::Cell *new_cell = module->addCell(NEW_TWINE, ID(dff)); + new_cell->setPort(TW::C, ioff_cells[i]->getPort(TW::C)); + new_cell->setPort(TW::D, ioff_cells[i]->getPort(TW::D)); + new_cell->setPort(TW::Q, sig_n[i]); new_cell->set_bool_attribute(ID::keep); } else { module->connect(sig_n[i], sig_o[i]); diff --git a/techlibs/xilinx/xilinx_dffopt.cc b/techlibs/xilinx/xilinx_dffopt.cc index 96420be6a..c15b9e710 100644 --- a/techlibs/xilinx/xilinx_dffopt.cc +++ b/techlibs/xilinx/xilinx_dffopt.cc @@ -146,11 +146,11 @@ struct XilinxDffOptPass : public Pass { if (cell->get_bool_attribute(ID::keep)) continue; if (cell->type == ID(INV)) { - SigBit sigout = sigmap(cell->getPort(ID::O)); - SigBit sigin = sigmap(cell->getPort(ID::I)); + SigBit sigout = sigmap(cell->getPort(TW::O)); + SigBit sigin = sigmap(cell->getPort(TW::I)); bit_to_lut[sigout] = make_pair(LutData(Const(1, 2), {sigin}), cell); } else if (cell->type.in(ID(LUT1), ID(LUT2), ID(LUT3), ID(LUT4), ID(LUT5), ID(LUT6))) { - SigBit sigout = sigmap(cell->getPort(ID::O)); + SigBit sigout = sigmap(cell->getPort(TW::O)); const Const &init = cell->getParam(ID::INIT); std::vector sigin; sigin.push_back(sigmap(cell->getPort(ID(I0)))); @@ -199,7 +199,7 @@ lut_sigin_done: continue; // Don't bother if D has more than one use. - SigBit sig_D = sigmap(cell->getPort(ID::D)); + SigBit sig_D = sigmap(cell->getPort(TW::D)); if (bit_uses[sig_D] > 2) continue; @@ -223,7 +223,7 @@ lut_sigin_done: bool worthy_post_r = false; // First, unmap CE. - SigBit sig_Q = sigmap(cell->getPort(ID::Q)); + SigBit sig_Q = sigmap(cell->getPort(TW::Q)); SigBit sig_CE = sigmap(cell->getPort(ID(CE))); LutData lut_ce = LutData(Const(2, 2), {sig_CE}); auto it_CE = bit_to_lut.find(sig_CE); @@ -247,7 +247,7 @@ lut_sigin_done: // Second, unmap S, if any. lut_d_post_s = lut_d_post_ce; if (has_s) { - SigBit sig_S = sigmap(cell->getPort(ID::S)); + SigBit sig_S = sigmap(cell->getPort(TW::S)); LutData lut_s = LutData(Const(2, 2), {sig_S}); bool inv_s = cell->hasParam(ID(IS_S_INVERTED)) && cell->getParam(ID(IS_S_INVERTED)).as_bool(); auto it_S = bit_to_lut.find(sig_S); @@ -269,7 +269,7 @@ lut_sigin_done: // Third, unmap R, if any. lut_d_post_r = lut_d_post_s; if (has_r) { - SigBit sig_R = sigmap(cell->getPort(ID::R)); + SigBit sig_R = sigmap(cell->getPort(TW::R)); LutData lut_r = LutData(Const(2, 2), {sig_R}); bool inv_r = cell->hasParam(ID(IS_R_INVERTED)) && cell->getParam(ID(IS_R_INVERTED)).as_bool(); auto it_R = bit_to_lut.find(sig_R); @@ -310,11 +310,11 @@ unmap: // Okay, we're doing it. Unmap ports. if (worthy_post_r) { cell->unsetParam(ID(IS_R_INVERTED)); - cell->setPort(ID::R, Const(0, 1)); + cell->setPort(TW::R, Const(0, 1)); } if (has_s && (worthy_post_r || worthy_post_s)) { cell->unsetParam(ID(IS_S_INVERTED)); - cell->setPort(ID::S, Const(0, 1)); + cell->setPort(TW::S, Const(0, 1)); } cell->setPort(ID(CE), Const(1, 1)); cell->unsetParam(ID(IS_D_INVERTED)); @@ -323,31 +323,31 @@ unmap: Cell *lut_cell = 0; switch (GetSize(final_lut.second)) { case 1: - lut_cell = module->addCell(NEW_ID, ID(LUT1)); + lut_cell = module->addCell(NEW_TWINE, ID(LUT1)); break; case 2: - lut_cell = module->addCell(NEW_ID, ID(LUT2)); + lut_cell = module->addCell(NEW_TWINE, ID(LUT2)); break; case 3: - lut_cell = module->addCell(NEW_ID, ID(LUT3)); + lut_cell = module->addCell(NEW_TWINE, ID(LUT3)); break; case 4: - lut_cell = module->addCell(NEW_ID, ID(LUT4)); + lut_cell = module->addCell(NEW_TWINE, ID(LUT4)); break; case 5: - lut_cell = module->addCell(NEW_ID, ID(LUT5)); + lut_cell = module->addCell(NEW_TWINE, ID(LUT5)); break; case 6: - lut_cell = module->addCell(NEW_ID, ID(LUT6)); + lut_cell = module->addCell(NEW_TWINE, ID(LUT6)); break; default: log_assert(!"unknown lut size"); } lut_cell->attributes = cell_d->attributes; - Wire *lut_out = module->addWire(NEW_ID); + Wire *lut_out = module->addWire(NEW_TWINE); lut_cell->setParam(ID::INIT, final_lut.first); - cell->setPort(ID::D, lut_out); - lut_cell->setPort(ID::O, lut_out); + cell->setPort(TW::D, lut_out); + lut_cell->setPort(TW::O, lut_out); lut_cell->setPort(ID(I0), final_lut.second[0]); if (GetSize(final_lut.second) >= 2) lut_cell->setPort(ID(I1), final_lut.second[1]); diff --git a/techlibs/xilinx/xilinx_dsp.cc b/techlibs/xilinx/xilinx_dsp.cc index dcd991594..0dbeb9920 100644 --- a/techlibs/xilinx/xilinx_dsp.cc +++ b/techlibs/xilinx/xilinx_dsp.cc @@ -31,7 +31,7 @@ PRIVATE_NAMESPACE_BEGIN #include "techlibs/xilinx/xilinx_dsp_cascade_pm.h" static Cell* addDsp(Module *module) { - Cell *cell = module->addCell(NEW_ID, ID(DSP48E1)); + Cell *cell = module->addCell(NEW_TWINE, ID(DSP48E1)); cell->setParam(ID(ACASCREG), 0); cell->setParam(ID(ADREG), 0); cell->setParam(ID(A_INPUT), Const("DIRECT")); @@ -52,7 +52,7 @@ static Cell* addDsp(Module *module) { cell->setParam(ID(USE_SIMD), Const("ONE48")); cell->setParam(ID(USE_DPORT), Const("FALSE")); - cell->setPort(ID::D, Const(0, 25)); + cell->setPort(TW::D, Const(0, 25)); cell->setPort(ID(INMODE), Const(0, 5)); cell->setPort(ID(ALUMODE), Const(0, 4)); cell->setPort(ID(OPMODE), Const(0, 7)); @@ -117,13 +117,13 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector & for (auto cell : selected_cells) { if (!cell->type.in(ID($add), ID($sub))) continue; - SigSpec Y = cell->getPort(ID::Y); + SigSpec Y = cell->getPort(TW::Y); if (!is_allowed(Y, simds)) continue; if (GetSize(Y) > 25) continue; - SigSpec A = cell->getPort(ID::A); - SigSpec B = cell->getPort(ID::B); + SigSpec A = cell->getPort(TW::A); + SigSpec B = cell->getPort(TW::B); if (GetSize(Y) <= 13) { if (GetSize(A) > 12) continue; @@ -149,15 +149,15 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector & } auto f12 = [module](SigSpec &AB, SigSpec &C, SigSpec &P, SigSpec &CARRYOUT, Cell *lane) { - SigSpec A = lane->getPort(ID::A); - SigSpec B = lane->getPort(ID::B); - SigSpec Y = lane->getPort(ID::Y); + SigSpec A = lane->getPort(TW::A); + SigSpec B = lane->getPort(TW::B); + SigSpec Y = lane->getPort(TW::Y); A.extend_u0(12, lane->getParam(ID::A_SIGNED).as_bool()); B.extend_u0(12, lane->getParam(ID::B_SIGNED).as_bool()); AB.append(A); C.append(B); if (GetSize(Y) < 13) - Y.append(module->addWire(NEW_ID, 13-GetSize(Y))); + Y.append(module->addWire(NEW_TWINE, 13-GetSize(Y))); else log_assert(GetSize(Y) == 13); P.append(Y.extract(0, 12)); @@ -203,24 +203,24 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector & else { AB.append(Const(0, 12)); C.append(Const(0, 12)); - P.append(module->addWire(NEW_ID, 12)); - CARRYOUT.append(module->addWire(NEW_ID, 1)); + P.append(module->addWire(NEW_TWINE, 12)); + CARRYOUT.append(module->addWire(NEW_TWINE, 1)); } } else { AB.append(Const(0, 24)); C.append(Const(0, 24)); - P.append(module->addWire(NEW_ID, 24)); - CARRYOUT.append(module->addWire(NEW_ID, 2)); + P.append(module->addWire(NEW_TWINE, 24)); + CARRYOUT.append(module->addWire(NEW_TWINE, 2)); } log_assert(GetSize(AB) == 48); log_assert(GetSize(C) == 48); log_assert(GetSize(P) == 48); log_assert(GetSize(CARRYOUT) == 4); - cell->setPort(ID::A, AB.extract(18, 30)); - cell->setPort(ID::B, AB.extract(0, 18)); - cell->setPort(ID::C, C); - cell->setPort(ID::P, P); + cell->setPort(TW::A, AB.extract(18, 30)); + cell->setPort(TW::B, AB.extract(0, 18)); + cell->setPort(TW::C, C); + cell->setPort(TW::P, P); cell->setPort(ID(CARRYOUT), CARRYOUT); if (lane1->type == ID($sub)) cell->setPort(ID(ALUMODE), Const::from_string("0011")); @@ -237,19 +237,19 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector & g12(simd12_sub); auto f24 = [module](SigSpec &AB, SigSpec &C, SigSpec &P, SigSpec &CARRYOUT, Cell *lane) { - SigSpec A = lane->getPort(ID::A); - SigSpec B = lane->getPort(ID::B); - SigSpec Y = lane->getPort(ID::Y); + SigSpec A = lane->getPort(TW::A); + SigSpec B = lane->getPort(TW::B); + SigSpec Y = lane->getPort(TW::Y); A.extend_u0(24, lane->getParam(ID::A_SIGNED).as_bool()); B.extend_u0(24, lane->getParam(ID::B_SIGNED).as_bool()); C.append(A); AB.append(B); if (GetSize(Y) < 25) - Y.append(module->addWire(NEW_ID, 25-GetSize(Y))); + Y.append(module->addWire(NEW_TWINE, 25-GetSize(Y))); else log_assert(GetSize(Y) == 25); P.append(Y.extract(0, 24)); - CARRYOUT.append(module->addWire(NEW_ID)); // TWO24 uses every other bit + CARRYOUT.append(module->addWire(NEW_TWINE)); // TWO24 uses every other bit CARRYOUT.append(Y[24]); }; auto g24 = [&f24,module](std::deque &simd24) { @@ -281,10 +281,10 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector & log_assert(GetSize(C) == 48); log_assert(GetSize(P) == 48); log_assert(GetSize(CARRYOUT) == 4); - cell->setPort(ID::A, AB.extract(18, 30)); - cell->setPort(ID::B, AB.extract(0, 18)); - cell->setPort(ID::C, C); - cell->setPort(ID::P, P); + cell->setPort(TW::A, AB.extract(18, 30)); + cell->setPort(TW::B, AB.extract(0, 18)); + cell->setPort(TW::C, C); + cell->setPort(TW::P, P); cell->setPort(ID(CARRYOUT), CARRYOUT); if (lane1->type == ID($sub)) cell->setPort(ID(ALUMODE), Const::from_string("0011")); @@ -328,12 +328,12 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) log(" preadder %s (%s)\n", preAdder, preAdder->type.unescape()); bool A_SIGNED = preAdder->getParam(ID::A_SIGNED).as_bool(); bool D_SIGNED = preAdder->getParam(ID::B_SIGNED).as_bool(); - if (st.sigA == preAdder->getPort(ID::B)) + if (st.sigA == preAdder->getPort(TW::B)) std::swap(A_SIGNED, D_SIGNED); st.sigA.extend_u0(30, A_SIGNED); st.sigD.extend_u0(25, D_SIGNED); - cell->setPort(ID::A, st.sigA); - cell->setPort(ID::D, st.sigD); + cell->setPort(TW::A, st.sigA); + cell->setPort(TW::D, st.sigD); if (preAdder->type == ID($add)) cell->setPort(ID(INMODE), Const::from_string("00100")); else @@ -342,7 +342,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) if (st.ffAD) { if (st.ffAD->type.in(ID($dffe), ID($sdffe))) { bool pol = st.ffAD->getParam(ID::EN_POLARITY).as_bool(); - SigSpec S = st.ffAD->getPort(ID::EN); + SigSpec S = st.ffAD->getPort(TW::EN); cell->setPort(ID(CEAD), pol ? S : pm.module->Not(NEW_ID, S)); } else @@ -360,7 +360,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) SigSpec &opmode = cell->connections_.at(ID(OPMODE)); if (st.postAddMux) { log_assert(st.ffP); - opmode[4] = st.postAddMux->getPort(ID::S); + opmode[4] = st.postAddMux->getPort(TW::S); pm.autoremove(st.postAddMux); } else if (st.ffP && st.sigC == st.sigP) @@ -375,7 +375,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) st.sigC.extend_u0(48, st.postAdd->getParam(ID::B_SIGNED).as_bool()); else st.sigC.extend_u0(48, st.postAdd->getParam(ID::A_SIGNED).as_bool()); - cell->setPort(ID::C, st.sigC); + cell->setPort(TW::C, st.sigC); } pm.autoremove(st.postAdd); @@ -387,7 +387,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) cell->setParam(ID(SEL_MASK), Const("MASK")); if (st.overflow->type == ID($ge)) { - Const B = st.overflow->getPort(ID::B).as_const(); + Const B = st.overflow->getPort(TW::B).as_const(); log_assert(std::count(B.begin(), B.end(), State::S1) == 1); // Since B is an exact power of 2, subtract 1 // by inverting all bits up until hitting @@ -402,7 +402,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) cell->setParam(ID(MASK), B); cell->setParam(ID(PATTERN), Const(0, 48)); - cell->setPort(ID(OVERFLOW), st.overflow->getPort(ID::Y)); + cell->setPort(ID(OVERFLOW), st.overflow->getPort(TW::Y)); } else log_abort(); @@ -411,16 +411,16 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) if (st.clock != SigBit()) { - cell->setPort(ID::CLK, st.clock); + cell->setPort(TW::CLK, st.clock); auto f = [&pm,cell](SigSpec &A, Cell* ff, IdString ceport, IdString rstport) { - SigSpec D = ff->getPort(ID::D); - SigSpec Q = (*pm.sigmap)(ff->getPort(ID::Q)); + SigSpec D = ff->getPort(TW::D); + SigSpec Q = (*pm.sigmap)(ff->getPort(TW::Q)); if (!A.empty()) A.replace(Q, D); if (rstport != IdString()) { if (ff->type.in(ID($sdff), ID($sdffe))) { - SigSpec srst = ff->getPort(ID::SRST); + SigSpec srst = ff->getPort(TW::SRST); bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool(); cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_ID, srst)); } else { @@ -428,7 +428,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) } } if (ff->type.in(ID($dffe), ID($sdffe))) { - SigSpec ce = ff->getPort(ID::EN); + SigSpec ce = ff->getPort(TW::EN); bool cepol = ff->getParam(ID::EN_POLARITY).as_bool(); cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce)); } @@ -447,7 +447,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) }; if (st.ffA2) { - SigSpec A = cell->getPort(ID::A); + SigSpec A = cell->getPort(TW::A); f(A, st.ffA2, ID(CEA2), ID(RSTA)); if (st.ffA1) { f(A, st.ffA1, ID(CEA1), IdString()); @@ -459,10 +459,10 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) cell->setParam(ID(ACASCREG), 1); } pm.add_siguser(A, cell); - cell->setPort(ID::A, A); + cell->setPort(TW::A, A); } if (st.ffB2) { - SigSpec B = cell->getPort(ID::B); + SigSpec B = cell->getPort(TW::B); f(B, st.ffB2, ID(CEB2), ID(RSTB)); if (st.ffB1) { f(B, st.ffB1, ID(CEB1), IdString()); @@ -474,25 +474,25 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) cell->setParam(ID(BCASCREG), 1); } pm.add_siguser(B, cell); - cell->setPort(ID::B, B); + cell->setPort(TW::B, B); } if (st.ffD) { - SigSpec D = cell->getPort(ID::D); + SigSpec D = cell->getPort(TW::D); f(D, st.ffD, ID(CED), ID(RSTD)); pm.add_siguser(D, cell); - cell->setPort(ID::D, D); + cell->setPort(TW::D, D); cell->setParam(ID(DREG), 1); } if (st.ffM) { SigSpec M; // unused f(M, st.ffM, ID(CEM), ID(RSTM)); - st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM))); + st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_TWINE, GetSize(st.sigM))); cell->setParam(ID(MREG), State::S1); } if (st.ffP) { SigSpec P; // unused f(P, st.ffP, ID(CEP), ID(RSTP)); - st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP))); + st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_TWINE, GetSize(st.sigP))); cell->setParam(ID(PREG), State::S1); } @@ -526,8 +526,8 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) SigSpec P = st.sigP; if (GetSize(P) < 48) - P.append(pm.module->addWire(NEW_ID, 48-GetSize(P))); - cell->setPort(ID::P, P); + P.append(pm.module->addWire(NEW_TWINE, 48-GetSize(P))); + cell->setPort(TW::P, P); pm.blacklist(cell); } @@ -559,8 +559,8 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) bool B_SIGNED = st.preAdd->getParam(ID::B_SIGNED).as_bool(); st.sigB.extend_u0(18, B_SIGNED); st.sigD.extend_u0(18, D_SIGNED); - cell->setPort(ID::B, st.sigB); - cell->setPort(ID::D, st.sigD); + cell->setPort(TW::B, st.sigB); + cell->setPort(TW::D, st.sigD); opmode[4] = State::S1; if (st.preAdd->type == ID($add)) opmode[6] = State::S0; @@ -576,7 +576,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) if (st.postAddMux) { log_assert(st.ffP); - opmode[2] = st.postAddMux->getPort(ID::S); + opmode[2] = st.postAddMux->getPort(TW::S); pm.autoremove(st.postAddMux); } else if (st.ffP && st.sigC == st.sigP) @@ -590,7 +590,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) st.sigC.extend_u0(48, st.postAdd->getParam(ID::B_SIGNED).as_bool()); else st.sigC.extend_u0(48, st.postAdd->getParam(ID::A_SIGNED).as_bool()); - cell->setPort(ID::C, st.sigC); + cell->setPort(TW::C, st.sigC); } pm.autoremove(st.postAdd); @@ -598,16 +598,16 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) if (st.clock != SigBit()) { - cell->setPort(ID::CLK, st.clock); + cell->setPort(TW::CLK, st.clock); auto f = [&pm,cell](SigSpec &A, Cell* ff, IdString ceport, IdString rstport) { - SigSpec D = ff->getPort(ID::D); - SigSpec Q = (*pm.sigmap)(ff->getPort(ID::Q)); + SigSpec D = ff->getPort(TW::D); + SigSpec Q = (*pm.sigmap)(ff->getPort(TW::Q)); if (!A.empty()) A.replace(Q, D); if (rstport != IdString()) { if (ff->type.in(ID($sdff), ID($sdffe))) { - SigSpec srst = ff->getPort(ID::SRST); + SigSpec srst = ff->getPort(TW::SRST); bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool(); cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_ID, srst)); } else { @@ -615,7 +615,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) } } if (ff->type.in(ID($dffe), ID($sdffe))) { - SigSpec ce = ff->getPort(ID::EN); + SigSpec ce = ff->getPort(TW::EN); bool cepol = ff->getParam(ID::EN_POLARITY).as_bool(); cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce)); } @@ -634,7 +634,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) }; if (st.ffA0 || st.ffA1) { - SigSpec A = cell->getPort(ID::A); + SigSpec A = cell->getPort(TW::A); if (st.ffA1) { f(A, st.ffA1, ID(CEA), ID(RSTA)); cell->setParam(ID(A1REG), 1); @@ -644,10 +644,10 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) cell->setParam(ID(A0REG), 1); } pm.add_siguser(A, cell); - cell->setPort(ID::A, A); + cell->setPort(TW::A, A); } if (st.ffB0 || st.ffB1) { - SigSpec B = cell->getPort(ID::B); + SigSpec B = cell->getPort(TW::B); if (st.ffB1) { f(B, st.ffB1, ID(CEB), ID(RSTB)); cell->setParam(ID(B1REG), 1); @@ -657,25 +657,25 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) cell->setParam(ID(B0REG), 1); } pm.add_siguser(B, cell); - cell->setPort(ID::B, B); + cell->setPort(TW::B, B); } if (st.ffD) { - SigSpec D = cell->getPort(ID::D); + SigSpec D = cell->getPort(TW::D); f(D, st.ffD, ID(CED), ID(RSTD)); pm.add_siguser(D, cell); - cell->setPort(ID::D, D); + cell->setPort(TW::D, D); cell->setParam(ID(DREG), 1); } if (st.ffM) { SigSpec M; // unused f(M, st.ffM, ID(CEM), ID(RSTM)); - st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM))); + st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_TWINE, GetSize(st.sigM))); cell->setParam(ID(MREG), State::S1); } if (st.ffP) { SigSpec P; // unused f(P, st.ffP, ID(CEP), ID(RSTP)); - st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP))); + st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_TWINE, GetSize(st.sigP))); cell->setParam(ID(PREG), State::S1); } @@ -704,8 +704,8 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) SigSpec P = st.sigP; if (GetSize(P) < 48) - P.append(pm.module->addWire(NEW_ID, 48-GetSize(P))); - cell->setPort(ID::P, P); + P.append(pm.module->addWire(NEW_TWINE, 48-GetSize(P))); + cell->setPort(TW::P, P); pm.blacklist(cell); } @@ -721,16 +721,16 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm) if (st.clock != SigBit()) { - cell->setPort(ID::CLK, st.clock); + cell->setPort(TW::CLK, st.clock); auto f = [&pm,cell](SigSpec &A, Cell* ff, IdString ceport, IdString rstport) { - SigSpec D = ff->getPort(ID::D); - SigSpec Q = (*pm.sigmap)(ff->getPort(ID::Q)); + SigSpec D = ff->getPort(TW::D); + SigSpec Q = (*pm.sigmap)(ff->getPort(TW::Q)); if (!A.empty()) A.replace(Q, D); if (rstport != IdString()) { if (ff->type.in(ID($sdff), ID($sdffe))) { - SigSpec srst = ff->getPort(ID::SRST); + SigSpec srst = ff->getPort(TW::SRST); bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool(); cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_ID, srst)); } else { @@ -738,7 +738,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm) } } if (ff->type.in(ID($dffe), ID($sdffe))) { - SigSpec ce = ff->getPort(ID::EN); + SigSpec ce = ff->getPort(TW::EN); bool cepol = ff->getParam(ID::EN_POLARITY).as_bool(); cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce)); } @@ -757,10 +757,10 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm) }; if (st.ffC) { - SigSpec C = cell->getPort(ID::C); + SigSpec C = cell->getPort(TW::C); f(C, st.ffC, ID(CEC), ID(RSTC)); pm.add_siguser(C, cell); - cell->setPort(ID::C, C); + cell->setPort(TW::C, C); cell->setParam(ID(CREG), 1); } diff --git a/techlibs/xilinx/xilinx_dsp_cascade.pmg b/techlibs/xilinx/xilinx_dsp_cascade.pmg index 587de4713..1a9c44f28 100644 --- a/techlibs/xilinx/xilinx_dsp_cascade.pmg +++ b/techlibs/xilinx/xilinx_dsp_cascade.pmg @@ -89,7 +89,7 @@ finally if (i % MAX_DSP_CASCADE > 0) { if (P >= 0) { - Wire *cascade = module->addWire(NEW_ID, 48); + Wire *cascade = module->addWire(NEW_TWINE, 48); dsp_pcin->setPort(\C, Const(0, 48)); dsp_pcin->setPort(\PCIN, cascade); dsp->setPort(\PCOUT, cascade); @@ -117,7 +117,7 @@ finally log_debug("PCOUT -> PCIN cascade for %s -> %s\n", dsp, dsp_pcin); } if (AREG >= 0) { - Wire *cascade = module->addWire(NEW_ID, 30); + Wire *cascade = module->addWire(NEW_TWINE, 30); dsp_pcin->setPort(\A, Const(0, 30)); dsp_pcin->setPort(\ACIN, cascade); dsp->setPort(\ACOUT, cascade); @@ -131,7 +131,7 @@ finally log_debug("ACOUT -> ACIN cascade for %s -> %s\n", dsp, dsp_pcin); } if (BREG >= 0) { - Wire *cascade = module->addWire(NEW_ID, 18); + Wire *cascade = module->addWire(NEW_TWINE, 18); if (dsp->type.in(\DSP48A, \DSP48A1)) { // According to UG389 p9 [https://www.xilinx.com/support/documentation/user_guides/ug389.pdf] // "The DSP48A1 component uses this input when cascading diff --git a/techlibs/xilinx/xilinx_srl.cc b/techlibs/xilinx/xilinx_srl.cc index 90978ca78..5c7e5391a 100644 --- a/techlibs/xilinx/xilinx_srl.cc +++ b/techlibs/xilinx/xilinx_srl.cc @@ -36,7 +36,7 @@ void run_fixed(xilinx_srl_pm &pm) for (auto cell : ud.longest_chain) { log_debug(" %s\n", cell); if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) { - SigBit Q = cell->getPort(ID::Q); + SigBit Q = cell->getPort(TW::Q); log_assert(Q.wire); auto it = Q.wire->attributes.find(ID::init); if (it != Q.wire->attributes.end()) { @@ -59,7 +59,7 @@ void run_fixed(xilinx_srl_pm &pm) auto first_cell = ud.longest_chain.back(); auto last_cell = ud.longest_chain.front(); - Cell *c = pm.module->addCell(NEW_ID, ID($__XILINX_SHREG_)); + Cell *c = pm.module->addCell(NEW_TWINE, ID($__XILINX_SHREG_)); pm.module->swap_names(c, first_cell); if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) { @@ -84,16 +84,16 @@ void run_fixed(xilinx_srl_pm &pm) else c->setParam(ID(ENPOL), 2); - c->setPort(ID::C, first_cell->getPort(ID::C)); - c->setPort(ID::D, first_cell->getPort(ID::D)); - c->setPort(ID::Q, last_cell->getPort(ID::Q)); - c->setPort(ID::L, GetSize(ud.longest_chain)-1); + c->setPort(TW::C, first_cell->getPort(TW::C)); + c->setPort(TW::D, first_cell->getPort(TW::D)); + c->setPort(TW::Q, last_cell->getPort(TW::Q)); + c->setPort(TW::L, GetSize(ud.longest_chain)-1); if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) - c->setPort(ID::E, State::S1); + c->setPort(TW::E, State::S1); else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) - c->setPort(ID::E, first_cell->getPort(ID::E)); + c->setPort(TW::E, first_cell->getPort(TW::E)); else if (first_cell->type.in(ID(FDRE), ID(FDRE_1))) - c->setPort(ID::E, first_cell->getPort(ID(CE))); + c->setPort(TW::E, first_cell->getPort(ID(CE))); else log_abort(); } @@ -116,7 +116,7 @@ void run_variable(xilinx_srl_pm &pm) auto slice = i.second; log_debug(" %s\n", cell); if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) { - SigBit Q = cell->getPort(ID::Q)[slice]; + SigBit Q = cell->getPort(TW::Q)[slice]; log_assert(Q.wire); auto it = Q.wire->attributes.find(ID::init); if (it != Q.wire->attributes.end()) { @@ -134,7 +134,7 @@ void run_variable(xilinx_srl_pm &pm) auto first_cell = ud.chain.back().first; auto first_slice = ud.chain.back().second; - Cell *c = pm.module->addCell(NEW_ID, ID($__XILINX_SHREG_)); + Cell *c = pm.module->addCell(NEW_TWINE, ID($__XILINX_SHREG_)); pm.module->swap_names(c, first_cell); if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) { @@ -161,20 +161,20 @@ void run_variable(xilinx_srl_pm &pm) c->setParam(ID(ENPOL), enpol); if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) - c->setPort(ID::C, first_cell->getPort(ID::C)); + c->setPort(TW::C, first_cell->getPort(TW::C)); else if (first_cell->type.in(ID($dff), ID($dffe))) - c->setPort(ID::C, first_cell->getPort(ID::CLK)); + c->setPort(TW::C, first_cell->getPort(TW::CLK)); else log_abort(); - c->setPort(ID::D, first_cell->getPort(ID::D)[first_slice]); - c->setPort(ID::Q, st.shiftx->getPort(ID::Y)); - c->setPort(ID::L, st.shiftx->getPort(ID::B)); + c->setPort(TW::D, first_cell->getPort(TW::D)[first_slice]); + c->setPort(TW::Q, st.shiftx->getPort(TW::Y)); + c->setPort(TW::L, st.shiftx->getPort(TW::B)); if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($dff))) - c->setPort(ID::E, State::S1); + c->setPort(TW::E, State::S1); else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) - c->setPort(ID::E, first_cell->getPort(ID::E)); + c->setPort(TW::E, first_cell->getPort(TW::E)); else if (first_cell->type.in(ID($dffe))) - c->setPort(ID::E, first_cell->getPort(ID::EN)); + c->setPort(TW::E, first_cell->getPort(TW::EN)); else log_abort(); } diff --git a/techlibs/xilinx/xilinx_srl.pmg b/techlibs/xilinx/xilinx_srl.pmg index 80f0a27c2..585400725 100644 --- a/techlibs/xilinx/xilinx_srl.pmg +++ b/techlibs/xilinx/xilinx_srl.pmg @@ -18,22 +18,22 @@ match first select !first->type.in(\FDRE, \FDRE_1) || port(first, \R, State::S0).is_fully_zero() filter !non_first_cells.count(first) generate - SigSpec C = module->addWire(NEW_ID); - SigSpec D = module->addWire(NEW_ID); - SigSpec Q = module->addWire(NEW_ID); + SigSpec C = module->addWire(NEW_TWINE); + SigSpec D = module->addWire(NEW_TWINE); + SigSpec Q = module->addWire(NEW_TWINE); auto r = rng(8); Cell* cell; switch (r) { case 0: case 1: - cell = module->addCell(NEW_ID, \FDRE); + cell = module->addCell(NEW_TWINE, \FDRE); cell->setPort(\C, C); cell->setPort(\D, D); cell->setPort(\Q, Q); - cell->setPort(\CE, module->addWire(NEW_ID)); + cell->setPort(\CE, module->addWire(NEW_TWINE)); if (r & 1) - cell->setPort(\R, module->addWire(NEW_ID)); + cell->setPort(\R, module->addWire(NEW_TWINE)); else { if (rng(2) == 0) cell->setPort(\R, State::S0); @@ -47,7 +47,7 @@ generate case 5: case 6: case 7: - cell = module->addDffeGate(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 2); + cell = module->addDffeGate(NEW_ID, C, module->addWire(NEW_TWINE), D, Q, r & 1, r & 2); break; default: log_abort(); } @@ -143,9 +143,9 @@ match next filter !first->type.in(\FDRE) || param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool() filter !first->type.in(\FDRE, \FDRE_1) || port(next, \R, State::S0).is_fully_zero() generate - Cell *cell = module->addCell(NEW_ID, chain.back()->type); + Cell *cell = module->addCell(NEW_TWINE, chain.back()->type); cell->setPort(\C, chain.back()->getPort(\C)); - cell->setPort(\D, module->addWire(NEW_ID)); + cell->setPort(\D, module->addWire(NEW_TWINE)); cell->setPort(\Q, chain.back()->getPort(\D)); if (cell->type == \FDRE) { if (rng(2) == 0) @@ -191,7 +191,7 @@ match shiftx filter param(shiftx, \A_WIDTH).as_int() >= minlen generate minlen = 3; - module->addShiftx(NEW_ID, module->addWire(NEW_ID, rng(6)+minlen), module->addWire(NEW_ID, 3), module->addWire(NEW_ID)); + module->addShiftx(NEW_ID, module->addWire(NEW_TWINE, rng(6)+minlen), module->addWire(NEW_TWINE, 3), module->addWire(NEW_TWINE)); endmatch code shiftx_width @@ -207,10 +207,10 @@ match first index port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1] set slice idx generate - SigSpec C = module->addWire(NEW_ID); + SigSpec C = module->addWire(NEW_TWINE); auto WIDTH = rng(3)+1; - SigSpec D = module->addWire(NEW_ID, WIDTH); - SigSpec Q = module->addWire(NEW_ID, WIDTH); + SigSpec D = module->addWire(NEW_TWINE, WIDTH); + SigSpec Q = module->addWire(NEW_TWINE, WIDTH); auto r = rng(8); Cell *cell = nullptr; switch (r) @@ -223,7 +223,7 @@ generate case 3: case 4: case 5: - //cell = module->addDffe(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 4); + //cell = module->addDffe(NEW_ID, C, module->addWire(NEW_TWINE), D, Q, r & 1, r & 4); //break; case 6: case 7: @@ -295,7 +295,7 @@ generate back->connections_.at(\D)[slice] = port(back, \Q)[new_slice]; } else { - auto D = module->addWire(NEW_ID, WIDTH); + auto D = module->addWire(NEW_TWINE, WIDTH); if (back->type == $dff) module->addDff(NEW_ID, port(back, \CLK), D, port(back, \D), param(back, \CLK_POLARITY).as_bool()); else if (back->type == $dffe) @@ -305,9 +305,9 @@ generate } } else if (back->type.begins_with("$_DFF_")) { - Cell *cell = module->addCell(NEW_ID, back->type); + Cell *cell = module->addCell(NEW_TWINE, back->type); cell->setPort(\C, back->getPort(\C)); - cell->setPort(\D, module->addWire(NEW_ID)); + cell->setPort(\D, module->addWire(NEW_TWINE)); cell->setPort(\Q, back->getPort(\D)); } else diff --git a/tests/unit/kernel/modindexTest.cc b/tests/unit/kernel/modindexTest.cc index 1921c9a93..6c9529511 100644 --- a/tests/unit/kernel/modindexTest.cc +++ b/tests/unit/kernel/modindexTest.cc @@ -40,7 +40,7 @@ TEST(ModIndexDeleteTest, has) mi.reload_module(); mi.dump_db(); Wire* a = m->addWire("\\a"); - not_->setPort(ID::A, a); + not_->setPort(TW::A, a); EXPECT_TRUE(mi.ok()); }