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https://github.com/YosysHQ/yosys
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WIP
This commit is contained in:
Emil J. Tywoniak
parent
015ab4e45b
commit
f592f2f3af
203 changed files with 4575 additions and 4481 deletions
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@ -43,10 +43,10 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
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st.sigB.extend_u0(18, B_SIGNED);
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st.sigD.extend_u0(18, D_SIGNED);
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if (st.moveBtoA) {
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cell->setPort(ID::A, st.sigA); // if pre-adder feeds into A, original sigB will be moved to port A
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cell->setPort(TW::A, st.sigA); // if pre-adder feeds into A, original sigB will be moved to port A
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}
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cell->setPort(ID::B, st.sigB);
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cell->setPort(ID::D, st.sigD);
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cell->setPort(TW::B, st.sigB);
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cell->setPort(TW::D, st.sigD);
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// MACC_PA supports both addition and subtraction with the pre-adder.
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// Affects the sign of the 'D' port.
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if (st.preAdderStatic->type == ID($add))
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@ -75,7 +75,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
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cell->setPort(ID(CDIN_FDBK_SEL), {State::S0, State::S1});
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} else {
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st.sigC.extend_u0(48, st.postAdderStatic->getParam(ID::A_SIGNED).as_bool());
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cell->setPort(ID::C, st.sigC);
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cell->setPort(TW::C, st.sigC);
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}
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pm.autoremove(st.postAdderStatic);
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@ -83,24 +83,24 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
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// pack registers
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if (st.clock != SigBit()) {
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cell->setPort(ID::CLK, st.clock);
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cell->setPort(TW::CLK, st.clock);
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// function to absorb a register
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auto f = [&pm, cell](SigSpec &A, Cell *ff, IdString ceport, IdString rstport, IdString bypass) {
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// input/output ports
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SigSpec D = ff->getPort(ID::D);
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SigSpec Q = (*pm.sigmap)(ff->getPort(ID::Q));
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SigSpec D = ff->getPort(TW::D);
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SigSpec Q = (*pm.sigmap)(ff->getPort(TW::Q));
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if (!A.empty())
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A.replace(Q, D);
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if (rstport != IdString()) {
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if (ff->type.in(ID($sdff), ID($sdffe))) {
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SigSpec srst = ff->getPort(ID::SRST);
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SigSpec srst = ff->getPort(TW::SRST);
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bool rstpol_n = !ff->getParam(ID::SRST_POLARITY).as_bool();
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// active low sync rst
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cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_ID, srst));
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} else if (ff->type.in(ID($adff), ID($adffe))) {
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SigSpec arst = ff->getPort(ID::ARST);
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SigSpec arst = ff->getPort(TW::ARST);
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bool rstpol_n = !ff->getParam(ID::ARST_POLARITY).as_bool();
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// active low async rst
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cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEW_ID, arst));
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@ -110,7 +110,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
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}
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}
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if (ff->type.in(ID($dffe), ID($sdffe), ID($adffe))) {
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SigSpec ce = ff->getPort(ID::EN);
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SigSpec ce = ff->getPort(TW::EN);
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bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
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// enables are all active high
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cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
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@ -136,23 +136,23 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
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// NOTE: flops are not autoremoved because it is possible that they
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// are only partially absorbed into DSP, or have fanouts.
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if (st.ffA) {
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SigSpec A = cell->getPort(ID::A);
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SigSpec A = cell->getPort(TW::A);
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if (st.ffA) {
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f(A, st.ffA, ID(A_EN), ID(A_SRST_N), ID(A_BYPASS));
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}
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pm.add_siguser(A, cell);
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cell->setPort(ID::A, A);
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cell->setPort(TW::A, A);
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}
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if (st.ffB) {
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SigSpec B = cell->getPort(ID::B);
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SigSpec B = cell->getPort(TW::B);
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if (st.ffB) {
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f(B, st.ffB, ID(B_EN), ID(B_SRST_N), ID(B_BYPASS));
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}
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pm.add_siguser(B, cell);
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cell->setPort(ID::B, B);
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cell->setPort(TW::B, B);
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}
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if (st.ffD) {
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SigSpec D = cell->getPort(ID::D);
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SigSpec D = cell->getPort(TW::D);
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if (st.ffD->type.in(ID($adff), ID($adffe))) {
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f(D, st.ffD, ID(D_EN), ID(D_ARST_N), ID(D_BYPASS));
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} else {
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@ -160,12 +160,12 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
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}
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pm.add_siguser(D, cell);
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cell->setPort(ID::D, D);
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cell->setPort(TW::D, D);
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}
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if (st.ffP) {
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SigSpec P; // unused
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f(P, st.ffP, ID(P_EN), ID(P_SRST_N), ID(P_BYPASS));
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st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
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st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_TWINE, GetSize(st.sigP)));
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}
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log(" clock: %s (%s)\n", log_signal(st.clock), "posedge");
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@ -183,8 +183,8 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
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SigSpec P = st.sigP;
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if (GetSize(P) < 48)
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P.append(pm.module->addWire(NEW_ID, 48 - GetSize(P)));
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cell->setPort(ID::P, P);
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P.append(pm.module->addWire(NEW_TWINE, 48 - GetSize(P)));
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cell->setPort(TW::P, P);
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pm.blacklist(cell);
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}
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@ -200,23 +200,23 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
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Cell *cell = st.dsp;
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if (st.clock != SigBit()) {
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cell->setPort(ID::CLK, st.clock);
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cell->setPort(TW::CLK, st.clock);
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// same function as above, used for the last CREG we need to absorb
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auto f = [&pm, cell](SigSpec &A, Cell *ff, IdString ceport, IdString rstport, IdString bypass) {
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// input/output ports
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SigSpec D = ff->getPort(ID::D);
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SigSpec Q = (*pm.sigmap)(ff->getPort(ID::Q));
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SigSpec D = ff->getPort(TW::D);
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SigSpec Q = (*pm.sigmap)(ff->getPort(TW::Q));
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if (!A.empty())
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A.replace(Q, D);
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if (rstport != IdString()) {
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if (ff->type.in(ID($sdff), ID($sdffe))) {
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SigSpec srst = ff->getPort(ID::SRST);
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SigSpec srst = ff->getPort(TW::SRST);
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bool rstpol_n = !ff->getParam(ID::SRST_POLARITY).as_bool();
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// active low sync rst
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cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_ID, srst));
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} else if (ff->type.in(ID($adff), ID($adffe))) {
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SigSpec arst = ff->getPort(ID::ARST);
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SigSpec arst = ff->getPort(TW::ARST);
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bool rstpol_n = !ff->getParam(ID::ARST_POLARITY).as_bool();
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// active low async rst
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cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEW_ID, arst));
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@ -226,7 +226,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
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}
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}
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if (ff->type.in(ID($dffe), ID($sdffe), ID($adffe))) {
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SigSpec ce = ff->getPort(ID::EN);
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SigSpec ce = ff->getPort(TW::EN);
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bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
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// enables are all active high
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cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
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@ -250,7 +250,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
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};
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if (st.ffC) {
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SigSpec C = cell->getPort(ID::C);
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SigSpec C = cell->getPort(TW::C);
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if (st.ffC->type.in(ID($adff), ID($adffe))) {
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f(C, st.ffC, ID(C_EN), ID(C_ARST_N), ID(C_BYPASS));
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@ -258,7 +258,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
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f(C, st.ffC, ID(C_EN), ID(C_SRST_N), ID(C_BYPASS));
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}
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pm.add_siguser(C, cell);
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cell->setPort(ID::C, C);
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cell->setPort(TW::C, C);
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}
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log(" clock: %s (%s)", log_signal(st.clock), "posedge");
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