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This commit is contained in:
Emil J. Tywoniak 2026-06-10 19:22:53 +02:00
parent 015ab4e45b
commit f592f2f3af
203 changed files with 4575 additions and 4481 deletions
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24
techlibs/microchip/microchip_dffopt.cc
View file

@ -135,11 +135,11 @@ struct MicrochipDffOptPass : public Pass {
if (cell->get_bool_attribute(ID::keep))
continue;
if (cell->type == ID(INV)) {
SigBit sigout = sigmap(cell->getPort(ID::Y));
SigBit sigin = sigmap(cell->getPort(ID::A));
SigBit sigout = sigmap(cell->getPort(TW::Y));
SigBit sigin = sigmap(cell->getPort(TW::A));
bit_to_lut[sigout] = make_pair(LutData(Const(1, 2), {sigin}), cell); // INIT = 01
} else if (cell->type.in(ID(CFG1), ID(CFG2), ID(CFG3), ID(CFG4))) {
SigBit sigout = sigmap(cell->getPort(ID::Y));
SigBit sigout = sigmap(cell->getPort(TW::Y));
const Const &init = cell->getParam(ID::INIT);
std::vector<SigBit> sigin;
sigin.push_back(sigmap(cell->getPort(ID(A))));
@ -182,7 +182,7 @@ struct MicrochipDffOptPass : public Pass {
log_assert(!(has_s && has_r));
// Don't bother if D has more than one use.
SigBit sig_D = sigmap(cell->getPort(ID::D));
SigBit sig_D = sigmap(cell->getPort(TW::D));
if (bit_uses[sig_D] > 2)
continue;
@ -201,7 +201,7 @@ struct MicrochipDffOptPass : public Pass {
bool worthy_post_r = false;
// First, unmap CE.
SigBit sig_Q = sigmap(cell->getPort(ID::Q));
SigBit sig_Q = sigmap(cell->getPort(TW::Q));
SigBit sig_CE = sigmap(cell->getPort(ID(EN)));
LutData lut_ce = LutData(Const(2, 2), {sig_CE}); // INIT = 10
auto it_CE = bit_to_lut.find(sig_CE);
@ -309,25 +309,25 @@ struct MicrochipDffOptPass : public Pass {
Cell *lut_cell = nullptr;
switch (GetSize(final_lut.second)) {
case 1:
lut_cell = module->addCell(NEW_ID, ID(CFG1));
lut_cell = module->addCell(NEW_TWINE, ID(CFG1));
break;
case 2:
lut_cell = module->addCell(NEW_ID, ID(CFG2));
lut_cell = module->addCell(NEW_TWINE, ID(CFG2));
break;
case 3:
lut_cell = module->addCell(NEW_ID, ID(CFG3));
lut_cell = module->addCell(NEW_TWINE, ID(CFG3));
break;
case 4:
lut_cell = module->addCell(NEW_ID, ID(CFG4));
lut_cell = module->addCell(NEW_TWINE, ID(CFG4));
break;
default:
log_assert(!"unknown lut size");
}
lut_cell->attributes = cell_d->attributes;
Wire *lut_out = module->addWire(NEW_ID);
Wire *lut_out = module->addWire(NEW_TWINE);
lut_cell->setParam(ID::INIT, final_lut.first);
cell->setPort(ID::D, lut_out);
lut_cell->setPort(ID::Y, lut_out);
cell->setPort(TW::D, lut_out);
lut_cell->setPort(TW::Y, lut_out);
lut_cell->setPort(ID(A), final_lut.second[0]);
if (GetSize(final_lut.second) >= 2)
lut_cell->setPort(ID(B), final_lut.second[1]);

54
techlibs/microchip/microchip_dsp.cc
View file

@ -43,10 +43,10 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
st.sigB.extend_u0(18, B_SIGNED);
st.sigD.extend_u0(18, D_SIGNED);
if (st.moveBtoA) {
cell->setPort(ID::A, st.sigA); // if pre-adder feeds into A, original sigB will be moved to port A
cell->setPort(TW::A, st.sigA); // if pre-adder feeds into A, original sigB will be moved to port A
}
cell->setPort(ID::B, st.sigB);
cell->setPort(ID::D, st.sigD);
cell->setPort(TW::B, st.sigB);
cell->setPort(TW::D, st.sigD);
// MACC_PA supports both addition and subtraction with the pre-adder.
// Affects the sign of the 'D' port.
if (st.preAdderStatic->type == ID($add))
@ -75,7 +75,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
cell->setPort(ID(CDIN_FDBK_SEL), {State::S0, State::S1});
} else {
st.sigC.extend_u0(48, st.postAdderStatic->getParam(ID::A_SIGNED).as_bool());
cell->setPort(ID::C, st.sigC);
cell->setPort(TW::C, st.sigC);
}
pm.autoremove(st.postAdderStatic);
@ -83,24 +83,24 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
// pack registers
if (st.clock != SigBit()) {
cell->setPort(ID::CLK, st.clock);
cell->setPort(TW::CLK, st.clock);
// function to absorb a register
auto f = [&pm, cell](SigSpec &A, Cell *ff, IdString ceport, IdString rstport, IdString bypass) {
// input/output ports
SigSpec D = ff->getPort(ID::D);
SigSpec Q = (*pm.sigmap)(ff->getPort(ID::Q));
SigSpec D = ff->getPort(TW::D);
SigSpec Q = (*pm.sigmap)(ff->getPort(TW::Q));
if (!A.empty())
A.replace(Q, D);
if (rstport != IdString()) {
if (ff->type.in(ID($sdff), ID($sdffe))) {
SigSpec srst = ff->getPort(ID::SRST);
SigSpec srst = ff->getPort(TW::SRST);
bool rstpol_n = !ff->getParam(ID::SRST_POLARITY).as_bool();
// active low sync rst
cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_ID, srst));
} else if (ff->type.in(ID($adff), ID($adffe))) {
SigSpec arst = ff->getPort(ID::ARST);
SigSpec arst = ff->getPort(TW::ARST);
bool rstpol_n = !ff->getParam(ID::ARST_POLARITY).as_bool();
// active low async rst
cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEW_ID, arst));
@ -110,7 +110,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
}
}
if (ff->type.in(ID($dffe), ID($sdffe), ID($adffe))) {
SigSpec ce = ff->getPort(ID::EN);
SigSpec ce = ff->getPort(TW::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
// enables are all active high
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
@ -136,23 +136,23 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
// NOTE: flops are not autoremoved because it is possible that they
// are only partially absorbed into DSP, or have fanouts.
if (st.ffA) {
SigSpec A = cell->getPort(ID::A);
SigSpec A = cell->getPort(TW::A);
if (st.ffA) {
f(A, st.ffA, ID(A_EN), ID(A_SRST_N), ID(A_BYPASS));
}
pm.add_siguser(A, cell);
cell->setPort(ID::A, A);
cell->setPort(TW::A, A);
}
if (st.ffB) {
SigSpec B = cell->getPort(ID::B);
SigSpec B = cell->getPort(TW::B);
if (st.ffB) {
f(B, st.ffB, ID(B_EN), ID(B_SRST_N), ID(B_BYPASS));
}
pm.add_siguser(B, cell);
cell->setPort(ID::B, B);
cell->setPort(TW::B, B);
}
if (st.ffD) {
SigSpec D = cell->getPort(ID::D);
SigSpec D = cell->getPort(TW::D);
if (st.ffD->type.in(ID($adff), ID($adffe))) {
f(D, st.ffD, ID(D_EN), ID(D_ARST_N), ID(D_BYPASS));
} else {
@ -160,12 +160,12 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
}
pm.add_siguser(D, cell);
cell->setPort(ID::D, D);
cell->setPort(TW::D, D);
}
if (st.ffP) {
SigSpec P; // unused
f(P, st.ffP, ID(P_EN), ID(P_SRST_N), ID(P_BYPASS));
st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_TWINE, GetSize(st.sigP)));
}
log(" clock: %s (%s)\n", log_signal(st.clock), "posedge");
@ -183,8 +183,8 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
SigSpec P = st.sigP;
if (GetSize(P) < 48)
P.append(pm.module->addWire(NEW_ID, 48 - GetSize(P)));
cell->setPort(ID::P, P);
P.append(pm.module->addWire(NEW_TWINE, 48 - GetSize(P)));
cell->setPort(TW::P, P);
pm.blacklist(cell);
}
@ -200,23 +200,23 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
Cell *cell = st.dsp;
if (st.clock != SigBit()) {
cell->setPort(ID::CLK, st.clock);
cell->setPort(TW::CLK, st.clock);
// same function as above, used for the last CREG we need to absorb
auto f = [&pm, cell](SigSpec &A, Cell *ff, IdString ceport, IdString rstport, IdString bypass) {
// input/output ports
SigSpec D = ff->getPort(ID::D);
SigSpec Q = (*pm.sigmap)(ff->getPort(ID::Q));
SigSpec D = ff->getPort(TW::D);
SigSpec Q = (*pm.sigmap)(ff->getPort(TW::Q));
if (!A.empty())
A.replace(Q, D);
if (rstport != IdString()) {
if (ff->type.in(ID($sdff), ID($sdffe))) {
SigSpec srst = ff->getPort(ID::SRST);
SigSpec srst = ff->getPort(TW::SRST);
bool rstpol_n = !ff->getParam(ID::SRST_POLARITY).as_bool();
// active low sync rst
cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_ID, srst));
} else if (ff->type.in(ID($adff), ID($adffe))) {
SigSpec arst = ff->getPort(ID::ARST);
SigSpec arst = ff->getPort(TW::ARST);
bool rstpol_n = !ff->getParam(ID::ARST_POLARITY).as_bool();
// active low async rst
cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEW_ID, arst));
@ -226,7 +226,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
}
}
if (ff->type.in(ID($dffe), ID($sdffe), ID($adffe))) {
SigSpec ce = ff->getPort(ID::EN);
SigSpec ce = ff->getPort(TW::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
// enables are all active high
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
@ -250,7 +250,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
};
if (st.ffC) {
SigSpec C = cell->getPort(ID::C);
SigSpec C = cell->getPort(TW::C);
if (st.ffC->type.in(ID($adff), ID($adffe))) {
f(C, st.ffC, ID(C_EN), ID(C_ARST_N), ID(C_BYPASS));
@ -258,7 +258,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
f(C, st.ffC, ID(C_EN), ID(C_SRST_N), ID(C_BYPASS));
}
pm.add_siguser(C, cell);
cell->setPort(ID::C, C);
cell->setPort(TW::C, C);
}
log(" clock: %s (%s)", log_signal(st.clock), "posedge");

2
techlibs/microchip/microchip_dsp_cascade.pmg
View file

@ -112,7 +112,7 @@ finally
// Chain length exceeds the maximum cascade length, must split it up
if (i % MAX_DSP_CASCADE > 0) {
Wire *cascade = module->addWire(NEW_ID, 48);
Wire *cascade = module->addWire(NEW_TWINE, 48);
// zero port C and move wire to cascade
dsp_pcin->setPort(\C, Const(0, 48));