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This commit is contained in:
Emil J. Tywoniak 2026-06-10 19:22:53 +02:00
parent 015ab4e45b
commit f592f2f3af
203 changed files with 4575 additions and 4481 deletions
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226
passes/techmap/simplemap.cc
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@ -34,23 +34,23 @@ static void transfer_src (Cell* to, const Cell* from) {
void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_NOT_));
transfer_src(gate, cell);
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::Y, sig_y[i]);
gate->setPort(TW::A, sig_a[i]);
gate->setPort(TW::Y, sig_y[i]);
}
}
void simplemap_buf(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
if (sig_a.has_const(State::Sz)) {
SigSpec new_a;
@ -72,8 +72,8 @@ void simplemap_buf(RTLIL::Module *module, RTLIL::Cell *cell)
void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
@ -82,9 +82,9 @@ void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
if (cell->type != ID($bweqx)) {
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
@ -100,18 +100,18 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
log_assert(!gate_type.empty());
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
RTLIL::Cell *gate = module->addCell(NEW_TWINE, gate_type);
transfer_src(gate, cell);
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_b[i]);
gate->setPort(ID::Y, sig_y[i]);
gate->setPort(TW::A, sig_a[i]);
gate->setPort(TW::B, sig_b[i]);
gate->setPort(TW::Y, sig_y[i]);
}
}
void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
if (sig_y.size() == 0)
return;
@ -142,7 +142,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
while (sig_a.size() > 1)
{
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.size() / 2);
RTLIL::SigSpec sig_t = module->addWire(NEW_TWINE, sig_a.size() / 2);
for (int i = 0; i < sig_a.size(); i += 2)
{
@ -151,11 +151,11 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
continue;
}
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
RTLIL::Cell *gate = module->addCell(NEW_TWINE, gate_type);
transfer_src(gate, cell);
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_a[i+1]);
gate->setPort(ID::Y, sig_t[i/2]);
gate->setPort(TW::A, sig_a[i]);
gate->setPort(TW::B, sig_a[i+1]);
gate->setPort(TW::Y, sig_t[i/2]);
last_output_cell = gate;
}
@ -163,11 +163,11 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
}
if (cell->type == ID($reduce_xnor)) {
RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::SigSpec sig_t = module->addWire(NEW_TWINE);
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_NOT_));
transfer_src(gate, cell);
gate->setPort(ID::A, sig_a);
gate->setPort(ID::Y, sig_t);
gate->setPort(TW::A, sig_a);
gate->setPort(TW::Y, sig_t);
last_output_cell = gate;
sig_a = sig_t;
}
@ -175,7 +175,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
if (last_output_cell == NULL) {
module->connect(RTLIL::SigSig(sig_y, sig_a));
} else {
last_output_cell->setPort(ID::Y, sig_y);
last_output_cell->setPort(TW::Y, sig_y);
}
}
@ -183,7 +183,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
{
while (sig.size() > 1)
{
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.size() / 2);
RTLIL::SigSpec sig_t = module->addWire(NEW_TWINE, sig.size() / 2);
for (int i = 0; i < sig.size(); i += 2)
{
@ -192,11 +192,11 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
continue;
}
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_OR_));
transfer_src(gate, cell);
gate->setPort(ID::A, sig[i]);
gate->setPort(ID::B, sig[i+1]);
gate->setPort(ID::Y, sig_t[i/2]);
gate->setPort(TW::A, sig[i]);
gate->setPort(TW::B, sig[i+1]);
gate->setPort(TW::Y, sig_t[i/2]);
}
sig = sig_t;
@ -208,10 +208,10 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
logic_reduce(module, sig_a, cell);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
if (sig_y.size() == 0)
return;
@ -221,21 +221,21 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
sig_y = sig_y.extract(0, 1);
}
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_NOT_));
transfer_src(gate, cell);
gate->setPort(ID::A, sig_a);
gate->setPort(ID::Y, sig_y);
gate->setPort(TW::A, sig_a);
gate->setPort(TW::Y, sig_y);
}
void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
logic_reduce(module, sig_a, cell);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
logic_reduce(module, sig_b, cell);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
if (sig_y.size() == 0)
return;
@ -250,28 +250,28 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
if (cell->type == ID($logic_or)) gate_type = ID($_OR_);
log_assert(!gate_type.empty());
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
RTLIL::Cell *gate = module->addCell(NEW_TWINE, gate_type);
transfer_src(gate, cell);
gate->setPort(ID::A, sig_a);
gate->setPort(ID::B, sig_b);
gate->setPort(ID::Y, sig_y);
gate->setPort(TW::A, sig_a);
gate->setPort(TW::B, sig_b);
gate->setPort(TW::Y, sig_y);
}
void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
bool is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
bool is_ne = cell->type.in(ID($ne), ID($nex));
RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
RTLIL::SigSpec xor_out = module->addWire(NEW_TWINE, max(GetSize(sig_a), GetSize(sig_b)));
RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
transfer_src(xor_cell, cell);
simplemap_bitop(module, xor_cell);
module->remove(xor_cell);
RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID);
RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_TWINE);
RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out);
transfer_src(reduce_cell, cell);
simplemap_reduce(module, reduce_cell);
@ -287,101 +287,101 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_MUX_));
transfer_src(gate, cell);
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_b[i]);
gate->setPort(ID::S, cell->getPort(ID::S));
gate->setPort(ID::Y, sig_y[i]);
gate->setPort(TW::A, sig_a[i]);
gate->setPort(TW::B, sig_b[i]);
gate->setPort(TW::S, cell->getPort(TW::S));
gate->setPort(TW::Y, sig_y[i]);
}
}
void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_s = cell->getPort(ID::S);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
RTLIL::SigSpec sig_s = cell->getPort(TW::S);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_MUX_));
transfer_src(gate, cell);
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_b[i]);
gate->setPort(ID::S, sig_s[i]);
gate->setPort(ID::Y, sig_y[i]);
gate->setPort(TW::A, sig_a[i]);
gate->setPort(TW::B, sig_b[i]);
gate->setPort(TW::S, sig_s[i]);
gate->setPort(TW::Y, sig_y[i]);
}
}
void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_e = cell->getPort(ID::EN);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_e = cell->getPort(TW::EN);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_TBUF_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_TBUF_));
transfer_src(gate, cell);
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::E, sig_e);
gate->setPort(ID::Y, sig_y[i]);
gate->setPort(TW::A, sig_a[i]);
gate->setPort(TW::E, sig_e);
gate->setPort(TW::Y, sig_y[i]);
}
}
void simplemap_bmux(RTLIL::Module *module, RTLIL::Cell *cell)
{
SigSpec sel = cell->getPort(ID::S);
SigSpec data = cell->getPort(ID::A);
int width = GetSize(cell->getPort(ID::Y));
SigSpec sel = cell->getPort(TW::S);
SigSpec data = cell->getPort(TW::A);
int width = GetSize(cell->getPort(TW::Y));
for (int idx = 0; idx < GetSize(sel); idx++) {
SigSpec new_data = module->addWire(NEW_ID, GetSize(data)/2);
SigSpec new_data = module->addWire(NEW_TWINE, GetSize(data)/2);
for (int i = 0; i < GetSize(new_data); i += width) {
for (int k = 0; k < width; k++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_MUX_));
transfer_src(gate, cell);
gate->setPort(ID::A, data[i*2+k]);
gate->setPort(ID::B, data[i*2+width+k]);
gate->setPort(ID::S, sel[idx]);
gate->setPort(ID::Y, new_data[i+k]);
gate->setPort(TW::A, data[i*2+k]);
gate->setPort(TW::B, data[i*2+width+k]);
gate->setPort(TW::S, sel[idx]);
gate->setPort(TW::Y, new_data[i+k]);
}
}
data = new_data;
}
module->connect(cell->getPort(ID::Y), data);
module->connect(cell->getPort(TW::Y), data);
}
void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell)
{
SigSpec lut_ctrl = cell->getPort(ID::A);
SigSpec lut_ctrl = cell->getPort(TW::A);
SigSpec lut_data = cell->getParam(ID::LUT);
lut_data.extend_u0(1 << cell->getParam(ID::WIDTH).as_int());
for (int idx = 0; GetSize(lut_data) > 1; idx++) {
SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2);
SigSpec new_lut_data = module->addWire(NEW_TWINE, GetSize(lut_data)/2);
for (int i = 0; i < GetSize(lut_data); i += 2) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_MUX_));
transfer_src(gate, cell);
gate->setPort(ID::A, lut_data[i]);
gate->setPort(ID::B, lut_data[i+1]);
gate->setPort(ID::S, lut_ctrl[idx]);
gate->setPort(ID::Y, new_lut_data[i/2]);
gate->setPort(TW::A, lut_data[i]);
gate->setPort(TW::B, lut_data[i+1]);
gate->setPort(TW::S, lut_ctrl[idx]);
gate->setPort(TW::Y, new_lut_data[i/2]);
}
lut_data = new_lut_data;
}
module->connect(cell->getPort(ID::Y), lut_data);
module->connect(cell->getPort(TW::Y), lut_data);
}
void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell)
{
SigSpec ctrl = cell->getPort(ID::A);
SigSpec ctrl = cell->getPort(TW::A);
SigSpec table = cell->getParam(ID::TABLE);
int width = cell->getParam(ID::WIDTH).as_int();
@ -406,22 +406,22 @@ void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell)
products.append(GetSize(in) > 0 ? module->Eq(NEW_ID, in, pat) : State::S1);
}
module->connect(cell->getPort(ID::Y), module->ReduceOr(NEW_ID, products));
module->connect(cell->getPort(TW::Y), module->ReduceOr(NEW_ID, products));
}
void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)
{
int offset = cell->parameters.at(ID::OFFSET).as_int();
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
module->connect(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size())));
}
void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_ab = cell->getPort(ID::A);
sig_ab.append(cell->getPort(ID::B));
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_ab = cell->getPort(TW::A);
sig_ab.append(cell->getPort(TW::B));
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
module->connect(RTLIL::SigSig(sig_y, sig_ab));
}
@ -437,10 +437,10 @@ void simplemap_ff(RTLIL::Module *, RTLIL::Cell *cell)
void simplemap_pmux(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_s = cell->getPort(ID::S);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
RTLIL::SigSpec sig_s = cell->getPort(TW::S);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
int width = GetSize(sig_a);
int s_width = GetSize(sig_s);
@ -454,13 +454,13 @@ void simplemap_pmux(RTLIL::Module *module, RTLIL::Cell *cell)
// Implement: B_AND_BITS = B_AND_S[WIDTH*j+i]
for (int j = 0; j < s_width; j++) {
RTLIL::Cell *and_gate = module->addCell(NEW_ID, ID($_AND_));
RTLIL::Cell *and_gate = module->addCell(NEW_TWINE, ID($_AND_));
transfer_src(and_gate, cell);
and_gate->setPort(ID::A, sig_b[j * width + i]);
and_gate->setPort(ID::B, sig_s[j]);
and_gate->setPort(TW::A, sig_b[j * width + i]);
and_gate->setPort(TW::B, sig_s[j]);
RTLIL::SigSpec and_y = module->addWire(NEW_ID, 1);
and_gate->setPort(ID::Y, and_y);
RTLIL::SigSpec and_y = module->addWire(NEW_TWINE, 1);
and_gate->setPort(TW::Y, and_y);
b_and_bits.append(and_y);
}
@ -468,12 +468,12 @@ void simplemap_pmux(RTLIL::Module *module, RTLIL::Cell *cell)
logic_reduce(module, b_and_bits, cell);
// Implement: Y[i] = |S ? Y_B[i] : A[i]
RTLIL::Cell *mux_gate = module->addCell(NEW_ID, ID($_MUX_));
RTLIL::Cell *mux_gate = module->addCell(NEW_TWINE, ID($_MUX_));
transfer_src(mux_gate, cell);
mux_gate->setPort(ID::A, sig_a[i]);
mux_gate->setPort(ID::B, b_and_bits);
mux_gate->setPort(ID::S, any_s);
mux_gate->setPort(ID::Y, sig_y[i]);
mux_gate->setPort(TW::A, sig_a[i]);
mux_gate->setPort(TW::B, b_and_bits);
mux_gate->setPort(TW::S, any_s);
mux_gate->setPort(TW::Y, sig_y[i]);
}
}